TI OMAP mailbox is the inter-processor mailbox IP found in TI K3 devices (AM62X, AM64X, J721E .etc). The mailbox hardware uses a queued mailbox interrupt mechanism that provides a communication channel between processors through a set of registers and their associated interrupt signals by sending and receiving messages. The interrupt/bank associated with each processor entity is found through the usr_id property from device tree. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> |
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| arc/synopsys | ||
| arm | ||
| arm64 | ||
| bindings | ||
| common | ||
| nios2/intel | ||
| posix | ||
| riscv | ||
| sparc/gaisler | ||
| x86/intel | ||
| xtensa | ||
| binding-template.yaml | ||
| Kconfig | ||