fe03e0c4bb
Fix IRQ number error of UART4 in DTS of gd32f4xx. Signed-off-by: Chang Feng <chang_196700@hotmail.com>
650 lines
15 KiB
Text
650 lines
15 KiB
Text
/*
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* Copyright (c) 2021, Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/clock/gd32f4xx-clocks.h>
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#include <zephyr/dt-bindings/reset/gd32f4xx.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m4f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv7m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(112)>;
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};
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rcu: reset-clock-controller@40023800 {
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compatible = "gd,gd32-rcu";
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reg = <0x40023800 0x400>;
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status = "okay";
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cctl: clock-controller {
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compatible = "gd,gd32-cctl";
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#clock-cells = <1>;
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status = "okay";
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};
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rctl: reset-controller {
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compatible = "gd,gd32-rctl";
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#reset-cells = <1>;
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status = "okay";
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};
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};
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fmc: flash-controller@40023c00 {
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compatible = "gd,gd32-flash-controller";
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reg = <0x40023c00 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "gd,gd32-nv-flash-v3", "soc-nv-flash";
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write-block-size = <2>;
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max-erase-time-ms = <8000>;
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};
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};
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usart0: usart@40011000 {
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compatible = "gd,gd32-usart";
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reg = <0x40011000 0x400>;
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interrupts = <37 0>;
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clocks = <&cctl GD32_CLOCK_USART0>;
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resets = <&rctl GD32_RESET_USART0>;
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status = "disabled";
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};
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usart1: usart@40004400 {
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compatible = "gd,gd32-usart";
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reg = <0x40004400 0x400>;
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interrupts = <38 0>;
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clocks = <&cctl GD32_CLOCK_USART1>;
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resets = <&rctl GD32_RESET_USART1>;
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status = "disabled";
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};
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usart2: usart@40004800 {
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compatible = "gd,gd32-usart";
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reg = <0x40004800 0x400>;
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interrupts = <39 0>;
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clocks = <&cctl GD32_CLOCK_USART2>;
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resets = <&rctl GD32_RESET_USART2>;
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status = "disabled";
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};
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uart3: usart@40004c00 {
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compatible = "gd,gd32-usart";
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reg = <0x40004c00 0x400>;
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interrupts = <52 0>;
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clocks = <&cctl GD32_CLOCK_UART3>;
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resets = <&rctl GD32_RESET_UART3>;
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status = "disabled";
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};
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uart4: usart@40005000 {
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compatible = "gd,gd32-usart";
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reg = <0x40005000 0x400>;
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interrupts = <53 0>;
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clocks = <&cctl GD32_CLOCK_UART4>;
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resets = <&rctl GD32_RESET_UART4>;
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status = "disabled";
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};
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usart5: usart@40011400 {
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compatible = "gd,gd32-usart";
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reg = <0x40011400 0x400>;
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interrupts = <71 0>;
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clocks = <&cctl GD32_CLOCK_USART5>;
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resets = <&rctl GD32_RESET_USART5>;
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status = "disabled";
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};
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uart6: usart@40007800 {
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compatible = "gd,gd32-usart";
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reg = <0x40007800 0x400>;
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interrupts = <82 0>;
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clocks = <&cctl GD32_CLOCK_UART6>;
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resets = <&rctl GD32_RESET_UART6>;
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status = "disabled";
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};
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uart7: usart@40007c00 {
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compatible = "gd,gd32-usart";
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reg = <0x40007c00 0x400>;
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interrupts = <83 0>;
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clocks = <&cctl GD32_CLOCK_UART7>;
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resets = <&rctl GD32_RESET_UART7>;
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status = "disabled";
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};
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dac: dac@40007400 {
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compatible = "gd,gd32-dac";
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reg = <0x40007400 0x400>;
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clocks = <&cctl GD32_CLOCK_DAC>;
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resets = <&rctl GD32_RESET_DAC>;
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num-channels = <2>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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i2c0: i2c@40005400 {
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compatible = "gd,gd32-i2c";
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reg = <0x40005400 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <31 0>, <32 0>;
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interrupt-names = "event", "error";
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clocks = <&cctl GD32_CLOCK_I2C0>;
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resets = <&rctl GD32_RESET_I2C0>;
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status = "disabled";
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};
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i2c1: i2c@40005800 {
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compatible = "gd,gd32-i2c";
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reg = <0x40005800 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "event", "error";
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clocks = <&cctl GD32_CLOCK_I2C1>;
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resets = <&rctl GD32_RESET_I2C1>;
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status = "disabled";
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};
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i2c2: i2c@40005c00 {
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compatible = "gd,gd32-i2c";
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reg = <0x40005c00 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <72 0>, <73 0>;
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interrupt-names = "event", "error";
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clocks = <&cctl GD32_CLOCK_I2C2>;
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resets = <&rctl GD32_RESET_I2C2>;
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status = "disabled";
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};
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spi0: spi@40013000 {
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compatible = "gd,gd32-spi";
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reg = <0x40013000 0x400>;
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interrupts = <35 0>;
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clocks = <&cctl GD32_CLOCK_SPI0>;
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resets = <&rctl GD32_RESET_SPI0>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@40003800 {
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compatible = "gd,gd32-spi";
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reg = <0x40003800 0x400>;
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interrupts = <36 0>;
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clocks = <&cctl GD32_CLOCK_SPI1>;
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resets = <&rctl GD32_RESET_SPI1>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi2: spi@40003c00 {
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compatible = "gd,gd32-spi";
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reg = <0x40003c00 0x400>;
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interrupts = <51 0>;
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clocks = <&cctl GD32_CLOCK_SPI2>;
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resets = <&rctl GD32_RESET_SPI2>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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adc0: adc@40012000 {
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compatible = "gd,gd32-adc";
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reg = <0x40012000 0x100>;
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interrupts = <18 0>;
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clocks = <&cctl GD32_CLOCK_ADC0>;
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resets = <&rctl GD32_RESET_ADC0>;
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channels = <16>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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adc1: adc@40012100 {
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compatible = "gd,gd32-adc";
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reg = <0x40012100 0x100>;
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interrupts = <18 0>;
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clocks = <&cctl GD32_CLOCK_ADC1>;
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resets = <&rctl GD32_RESET_ADC1>;
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channels = <16>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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adc2: adc@40012200 {
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compatible = "gd,gd32-adc";
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reg = <0x40012200 0x100>;
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interrupts = <18 0>;
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clocks = <&cctl GD32_CLOCK_ADC2>;
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resets = <&rctl GD32_RESET_ADC2>;
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channels = <16>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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syscfg: syscfg@40013800 {
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compatible = "gd,gd32-syscfg";
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reg = <0x40013800 0x400>;
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clocks = <&cctl GD32_CLOCK_SYSCFG>;
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};
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exti: interrupt-controller@40013c00 {
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compatible = "gd,gd32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x40013c00 0x400>;
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num-lines = <23>;
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interrupts = <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <23 0>,
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<40 0>;
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interrupt-names = "line0", "line1", "line2", "line3",
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"line4", "line5-9", "line10-15";
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status = "okay";
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};
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fwdgt: watchdog@40003000 {
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compatible = "gd,gd32-fwdgt";
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reg = <0x40003000 0x400>;
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status = "disabled";
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};
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wwdgt: watchdog@40002c00 {
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compatible = "gd,gd32-wwdgt";
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reg = <0x40002C00 0x400>;
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clocks = <&cctl GD32_CLOCK_WWDGT>;
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resets = <&rctl GD32_RESET_WWDGT>;
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interrupts = <0 0>;
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status = "disabled";
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};
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pinctrl: pin-controller@40020000 {
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compatible = "gd,gd32-pinctrl-af";
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reg = <0x40020000 0x2400>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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gpioa: gpio@40020000 {
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compatible = "gd,gd32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020000 0x400>;
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clocks = <&cctl GD32_CLOCK_GPIOA>;
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resets = <&rctl GD32_RESET_GPIOA>;
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status = "disabled";
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};
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gpiob: gpio@40020400 {
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compatible = "gd,gd32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020400 0x400>;
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clocks = <&cctl GD32_CLOCK_GPIOB>;
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resets = <&rctl GD32_RESET_GPIOB>;
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status = "disabled";
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};
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gpioc: gpio@40020800 {
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compatible = "gd,gd32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020800 0x400>;
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clocks = <&cctl GD32_CLOCK_GPIOC>;
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resets = <&rctl GD32_RESET_GPIOC>;
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status = "disabled";
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};
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gpiod: gpio@40020c00 {
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compatible = "gd,gd32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020c00 0x400>;
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clocks = <&cctl GD32_CLOCK_GPIOD>;
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resets = <&rctl GD32_RESET_GPIOD>;
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status = "disabled";
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};
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gpioe: gpio@40021000 {
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compatible = "gd,gd32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40021000 0x400>;
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clocks = <&cctl GD32_CLOCK_GPIOE>;
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resets = <&rctl GD32_RESET_GPIOE>;
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status = "disabled";
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};
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gpiof: gpio@40021400 {
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compatible = "gd,gd32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40021400 0x400>;
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clocks = <&cctl GD32_CLOCK_GPIOF>;
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resets = <&rctl GD32_RESET_GPIOF>;
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status = "disabled";
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};
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gpiog: gpio@40021800 {
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compatible = "gd,gd32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40021800 0x400>;
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clocks = <&cctl GD32_CLOCK_GPIOG>;
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resets = <&rctl GD32_RESET_GPIOG>;
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status = "disabled";
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};
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gpioh: gpio@40021c00 {
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compatible = "gd,gd32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40021c00 0x400>;
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clocks = <&cctl GD32_CLOCK_GPIOH>;
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resets = <&rctl GD32_RESET_GPIOH>;
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status = "disabled";
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};
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gpioi: gpio@40022000 {
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compatible = "gd,gd32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40022000 0x400>;
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clocks = <&cctl GD32_CLOCK_GPIOI>;
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resets = <&rctl GD32_RESET_GPIOI>;
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status = "disabled";
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};
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};
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timer0: timer@40010000 {
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compatible = "gd,gd32-timer";
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reg = <0x40010000 0x400>;
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interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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clocks = <&cctl GD32_CLOCK_TIMER0>;
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resets = <&rctl GD32_RESET_TIMER0>;
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is-advanced;
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channels = <4>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer1: timer@40000000 {
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compatible = "gd,gd32-timer";
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reg = <0x40000000 0x400>;
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interrupts = <28 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER1>;
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resets = <&rctl GD32_RESET_TIMER1>;
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is-32bit;
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channels = <4>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer2: timer@40000400 {
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compatible = "gd,gd32-timer";
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reg = <0x40000400 0x400>;
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interrupts = <29 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER2>;
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resets = <&rctl GD32_RESET_TIMER2>;
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channels = <4>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer3: timer@40000800 {
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compatible = "gd,gd32-timer";
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reg = <0x40000800 0x400>;
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interrupts = <30 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER3>;
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resets = <&rctl GD32_RESET_TIMER3>;
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channels = <4>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer4: timer@40000c00 {
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compatible = "gd,gd32-timer";
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reg = <0x40000c00 0x400>;
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interrupts = <50 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER4>;
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resets = <&rctl GD32_RESET_TIMER4>;
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is-32bit;
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channels = <4>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer5: timer@40001000 {
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compatible = "gd,gd32-timer";
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reg = <0x40001000 0x400>;
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interrupts = <54 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER5>;
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resets = <&rctl GD32_RESET_TIMER5>;
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channels = <0>;
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status = "disabled";
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};
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timer6: timer@40001400 {
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compatible = "gd,gd32-timer";
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reg = <0x40001400 0x400>;
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interrupts = <55 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER6>;
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resets = <&rctl GD32_RESET_TIMER6>;
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channels = <0>;
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status = "disabled";
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};
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timer7: timer@40010400 {
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compatible = "gd,gd32-timer";
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reg = <0x40010400 0x400>;
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interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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clocks = <&cctl GD32_CLOCK_TIMER7>;
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resets = <&rctl GD32_RESET_TIMER7>;
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is-advanced;
|
|
channels = <4>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "gd,gd32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timer8: timer@40014000 {
|
|
compatible = "gd,gd32-timer";
|
|
reg = <0x40014000 0x400>;
|
|
interrupts = <24 0>;
|
|
interrupt-names = "global";
|
|
clocks = <&cctl GD32_CLOCK_TIMER8>;
|
|
resets = <&rctl GD32_RESET_TIMER8>;
|
|
channels = <2>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "gd,gd32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timer9: timer@40014400 {
|
|
compatible = "gd,gd32-timer";
|
|
reg = <0x40014400 0x400>;
|
|
interrupts = <25 0>;
|
|
interrupt-names = "global";
|
|
clocks = <&cctl GD32_CLOCK_TIMER9>;
|
|
resets = <&rctl GD32_RESET_TIMER9>;
|
|
channels = <1>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "gd,gd32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timer10: timer@40014800 {
|
|
compatible = "gd,gd32-timer";
|
|
reg = <0x40014800 0x400>;
|
|
interrupts = <26 0>;
|
|
interrupt-names = "global";
|
|
clocks = <&cctl GD32_CLOCK_TIMER10>;
|
|
resets = <&rctl GD32_RESET_TIMER10>;
|
|
channels = <1>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "gd,gd32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timer11: timer@40001800 {
|
|
compatible = "gd,gd32-timer";
|
|
reg = <0x40001800 0x400>;
|
|
interrupts = <43 0>;
|
|
interrupt-names = "global";
|
|
clocks = <&cctl GD32_CLOCK_TIMER11>;
|
|
resets = <&rctl GD32_RESET_TIMER11>;
|
|
channels = <2>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "gd,gd32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timer12: timer@40001c00 {
|
|
compatible = "gd,gd32-timer";
|
|
reg = <0x40001c00 0x400>;
|
|
interrupts = <44 0>;
|
|
interrupt-names = "global";
|
|
clocks = <&cctl GD32_CLOCK_TIMER12>;
|
|
resets = <&rctl GD32_RESET_TIMER12>;
|
|
channels = <1>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "gd,gd32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timer13: timer@40002000 {
|
|
compatible = "gd,gd32-timer";
|
|
reg = <0x40002000 0x400>;
|
|
interrupts = <45 0>;
|
|
interrupt-names = "global";
|
|
clocks = <&cctl GD32_CLOCK_TIMER13>;
|
|
resets = <&rctl GD32_RESET_TIMER13>;
|
|
channels = <1>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "gd,gd32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
dma0: dma@40026000 {
|
|
compatible = "gd,gd32-dma-v1";
|
|
reg = <0x40026000 0x400>;
|
|
interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
|
|
<15 0>, <16 0>, <17 0>, <47 0>;
|
|
clocks = <&cctl GD32_CLOCK_DMA0>;
|
|
resets = <&rctl GD32_RESET_DMA0>;
|
|
dma-channels = <8>;
|
|
gd,mem2mem;
|
|
#dma-cells = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dma1: dma@40026400 {
|
|
compatible = "gd,gd32-dma-v1";
|
|
reg = <0x40026400 0x400>;
|
|
interrupts = <56 0>, <57 0>, <58 0>, <59 0>,
|
|
<60 0>, <68 0>, <69 0>, <70 0>;
|
|
clocks = <&cctl GD32_CLOCK_DMA1>;
|
|
resets = <&rctl GD32_RESET_DMA1>;
|
|
dma-channels = <8>;
|
|
gd,mem2mem;
|
|
#dma-cells = <4>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <4>;
|
|
};
|