fe5c11db05
Add Zephyr support for the Audio DSP on the MT8196 SOC. This is a very similar device to previous designs. Most of this patch is just DTS. The biggest delta is the more complicated second level interrupt controller, though it is still able to be represented using some vaguely clever DTS config over the older intc_mtk_adsp driver. Also the memory layout is slightly different, requiring a little indirection to set the initial boot stack address and log output buffer. And the timer "irq_ack" register bits moved. Signed-off-by: Andy Ross <andyross@google.com>
73 lines
2 KiB
C
73 lines
2 KiB
C
/* Copyright 2023 The ChromiumOS Authors
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/irq.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/device.h>
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bool intc_mtk_adsp_get_enable(const struct device *dev, int irq);
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void intc_mtk_adsp_set_enable(const struct device *dev, int irq, bool val);
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/* Sort of annoying: assumes there are exactly two controller devices
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* and that their instance IDs (i.e. the order in which they appear in
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* the .dts file) match their order in the _sw_isr_table[]. A better
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* scheme would be able to enumerate the tree at runtime.
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*/
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static const struct device *irq_dev(unsigned int *irq_inout)
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{
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#ifdef CONFIG_SOC_SERIES_MT8195
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/* Controller 0 is on Xtensa vector 1, controller 1 on vector 23. */
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if ((*irq_inout & 0xff) == 1) {
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*irq_inout >>= 8;
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return DEVICE_DT_GET(DT_INST(0, mediatek_adsp_intc));
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}
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__ASSERT_NO_MSG((*irq_inout & 0xff) == 23);
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*irq_inout = (*irq_inout >> 8) - 1;
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return DEVICE_DT_GET(DT_INST(1, mediatek_adsp_intc));
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#elif defined(CONFIG_SOC_SERIES_MT8196)
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/* Two subcontrollers on core IRQs 1 and 2 */
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uint32_t lvl1 = *irq_inout & 0xff;
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*irq_inout = (*irq_inout >> 8) - 1;
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if (lvl1 == 1) {
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return DEVICE_DT_GET(DT_INST(0, mediatek_adsp_intc));
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}
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__ASSERT_NO_MSG(lvl1 == 2);
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return DEVICE_DT_GET(DT_INST(1, mediatek_adsp_intc));
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#else
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/* Only one on 818x */
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return DEVICE_DT_GET(DT_INST(0, mediatek_adsp_intc));
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#endif
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}
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void z_soc_irq_enable(unsigned int irq)
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{
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/* First 32 IRQs are the Xtensa architectural vectors, */
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if (irq < 32) {
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xtensa_irq_enable(irq);
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} else {
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const struct device *dev = irq_dev(&irq);
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intc_mtk_adsp_set_enable(dev, irq, true);
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}
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}
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void z_soc_irq_disable(unsigned int irq)
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{
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if (irq < 32) {
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xtensa_irq_disable(irq);
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} else {
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const struct device *dev = irq_dev(&irq);
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intc_mtk_adsp_set_enable(dev, irq, false);
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}
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}
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int z_soc_irq_is_enabled(unsigned int irq)
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{
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if (irq < 32) {
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return xtensa_irq_is_enabled(irq);
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}
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return intc_mtk_adsp_get_enable(irq_dev(&irq), irq);
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}
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