Giuliano Zaro
29bfe96f8e
Fix compiler error
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Removed unnecessary bracket
missing usb padcal
2019-06-14 11:35:05 +02:00
GMagician
7a550677bc
[SAMD51] Add softwater calibration init on startup
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Use calibration software area fuses to initialize devices
2019-06-08 18:45:23 +02:00
Limor "Ladyada" Fried
bc8d8b861f
Overclocking and optimizer settings for M4 boards ( #100 )
2019-04-21 01:47:47 -04:00
aryelevin
98e2a3e429
Some fixes to the startup code - clocks configs ( #89 )
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* Reverted 1MHz clock generator to GCLK5 instead GCLK7
Fixed the clock divider of 1MHz clock generator to be 48 (its source is DFLL which clocking at 48MHz, so 48 / 48 = 1, it was 48 / 24 = 2).
Updated the PLLs to the proper Ratio afetr the change of the 1MHz clock source.
Disabled GCLK_GENCTRL_DIVSEL reg on the 12MHz clock generator, since this caused the clock to be 1.5MHz.
* Fixed a description comment.
2019-02-13 15:27:27 -05:00
Bill Westfield
2ca67fc36b
Fix delayMicroseconds() on SAMD51 ( #77 )
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* Fix pulseIn() on SAMD51 by writing it in plain C, so that
the CM0+-specific pulse_asm won't need to be linked.
The SAMD51 is fast enough that we can time pulses with micros()
Tested with a bunch of pulse lengths from <1us to >1s
* Implement a new delayMicroseconds() function for SAMD51
This version enables the "Debug Watchpoint and Trace" module (DWT)
in startup.c and then uses the 32bit cycle counter that is part
of DWT to count cycles indepenent of instruction timing.
Tested for good accuracy with various values between 1 and 2000us.
2019-01-09 19:57:43 -05:00
deanm1278
9828191030
add grand central m4 ( #67 )
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* DM: grandcentral variant
* DM: updates for m4 mega
* DM: metro mega updates
* DM: fixes for mega m4 pcc
* DM: fix grandcentral boards.txt naming
* DM: remove openocd for samd51, fix include guards
* DM: remove unnecessary debug scripts for m4 boards
2018-11-20 08:26:01 -08:00
dean
87eae6f55c
DM: add copyrights
2018-08-30 15:12:51 -04:00
ladyada
19e4a449f4
re-fix xtalless, add cache & freq fix
2018-08-30 15:12:33 -04:00
dean
a3493e3625
update clocks to match arduino samd
2018-08-30 15:12:32 -04:00
ladyada
49775dd780
see https://github.com/adafruit/ArduinoCore-samd/issues/37
2018-08-30 15:11:47 -04:00
dean
540780d3d1
DM: fix dac clock and first write bug
2018-08-30 15:11:21 -04:00
dean
7f74c2126e
update usb stuff
2018-08-30 15:08:16 -04:00
dean
b8b35ee319
DM: fix worst bug in entire world
2018-08-30 14:59:48 -04:00
dean
dc93e828f0
DM: fixed USB enumeration bug in bootloader and core
2018-08-30 14:56:11 -04:00
dean
850c490a53
DM: fixed dpll1 freq
2018-08-30 14:56:11 -04:00
dean
9ace80d803
DM: not crystalless
2018-08-30 14:54:36 -04:00
dean
01de36ef16
DM: oops committed wrong stuff, actually fixed DPLL problems
2018-08-30 14:54:36 -04:00
dean
1cc5f0cde4
DM: lets not feed PLLs from xosc
2018-08-30 14:54:36 -04:00
dean
785aea4f65
DM: fixed DAC, SPI
2018-08-30 14:53:33 -04:00
dean
c1827b289d
DM: added support for samd51J20A
2018-08-30 14:46:42 -04:00
dean
b5c2b6483b
DM: clocked to 120MHZ, peripherals to 100, USB to 48
2018-08-30 14:44:35 -04:00
dean
77a2f2e9ea
DM: fixed tone
2018-08-30 14:44:35 -04:00
dean
358b11addd
DM: added samd51 support
2018-08-30 14:32:21 -04:00
Cristian Maglie
af0263a60a
More accurate approximation for multiplication factor of PLL to make 48Mhz.
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Fix #223
2017-09-01 21:35:15 +02:00
ladyada
06ae2087ce
fix for crystal-less startup stability
2017-07-11 15:59:31 +02:00
Martino Facchin
4ac0cc1df0
Fix 8MHz clock being generated incorrectly
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CMSIS-Atmel 4.5 changed the prescaler defines to match the bit mask, not the actual prescaler value, thus `SYSCTRL_OSC8M_PRESC_1_Val` now means "divide by 2"
Fixes https://github.com/arduino/ArduinoCore-samd/issues/214
2017-02-28 09:43:02 +01:00
Cristian Maglie
2f3b976652
Updated crystalless startup to be compliant with CMSIS-Atmel 4.5
2016-12-19 16:02:20 +01:00
Cristian Maglie
7b8e0b11ed
Added support for crystal-less configurations
2016-12-19 14:48:29 +01:00
Cristian Maglie
0d57cfefe7
Set MANW bit of NVMCTRL to 1 at startup (default is 0).
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This prevents accidental overwrites of the bootloader if a NULL
pointer is used for writing by mistake.
2016-02-26 17:23:06 +01:00
Cristian Maglie
e748f0985f
Moved USB ISR handler in startup.c
2015-09-09 15:42:58 +02:00
Cristian Maglie
d9df90830e
Fixed cortex-M hooks for RTOS
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Fixes #4
2015-06-26 10:28:52 +02:00
Cristian Maglie
1a1856c2fc
License fix and cosmetic changes.
2015-06-14 17:16:37 +02:00
Thibaut VIARD
980947c44f
Adding breakpoints in handlers for DEBUG mode
2015-05-27 20:29:32 +02:00
Thibaut VIARD
30d3861324
Cleaning core interrupts handlers
2015-05-27 20:29:32 +02:00
Claudio Indellicati
3912d9d827
Loaded ADC calibration values at startup.
2015-05-20 15:16:08 +02:00
Thibaut VIARD
13d4fabbfa
Fixing wrong comment of SystemInit()
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Signed-off-by: Thibaut VIARD <thibaut.viard@atmel.com>
2015-03-19 00:49:42 +01:00
Claudio Indellicati
e1dbd13d34
Added first tone library implementation.
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Interrupt based implementation that works on every pin.
2015-03-16 15:35:41 +01:00
Thibaut VIARD
df1262a92a
CORE files update following headers update
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Signed-off-by: Thibaut VIARD <thibaut.viard@atmel.com>
2014-09-11 14:56:36 +02:00
Thibaut VIARD
ae42fd1167
Adding license in files, update platform.txt
2014-07-25 17:11:29 +02:00
Thibaut VIARD
3e2f4e77f2
Cosmetic polishing on clock setup code
2014-05-09 10:11:29 +02:00
Thibaut VIARD
61f33c3204
Finalizing clocks setup
2014-05-09 09:38:00 +02:00
Thibaut VIARD
54f8371b39
Clocks inits checkpoint
2014-05-08 23:30:37 +02:00
Thibaut VIARD
ec55df1e98
compilation checkpoint
2014-05-07 09:59:31 +02:00
Thibaut VIARD
0070eed06f
compilation checkpoint 2
2014-05-05 12:29:33 +02:00
Thibaut VIARD
5736c4b382
fixing clock setup according to review
2014-04-28 11:24:16 +02:00
Thibaut VIARD
336de7146e
Fix DFLL48M configuration in closed-loop mode
2014-04-24 18:07:27 +02:00
Thibaut VIARD
a92bdab17a
Fixing startup.c
2014-04-24 16:32:40 +02:00
Thibaut VIARD
d2f66d93cd
Bring startup and syscalls
2014-04-23 20:22:27 +02:00
