205 lines
7.4 KiB
C
205 lines
7.4 KiB
C
/*
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Copyright (c) 2015 Arduino LLC. All right reserved.
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SAMD51 support added by Adafruit - Copyright (c) 2018 Dean Miller for Adafruit Industries
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "Arduino.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(__SAMD51__)
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uint32_t SystemCoreClock=F_CPU;
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#else
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/*
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* System Core Clock is at 1MHz (8MHz/8) at Reset.
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* It is switched to 48MHz in the Reset Handler (startup.c)
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*/
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uint32_t SystemCoreClock=1000000ul ;
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#endif
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/*
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void calibrateADC()
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{
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volatile uint32_t valeur = 0;
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for(int i = 0; i < 5; ++i)
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{
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ADC->SWTRIG.bit.START = 1;
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while( ADC->INTFLAG.bit.RESRDY == 0 || ADC->STATUS.bit.SYNCBUSY == 1 )
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{
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// Waiting for a complete conversion and complete synchronization
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}
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valeur += ADC->RESULT.bit.RESULT;
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}
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valeur = valeur/5;
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}*/
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/*
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* Arduino Zero board initialization
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*
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* Good to know:
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* - At reset, ResetHandler did the system clock configuration. Core is running at 48MHz.
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* - Watchdog is disabled by default, unless someone plays with NVM User page
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* - During reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled.
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*/
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void init( void )
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{
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// Set Systick to 1ms interval, common to all Cortex-M variants
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if ( SysTick_Config( SystemCoreClock / 1000 ) )
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{
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// Capture error
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while ( 1 ) ;
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}
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NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 2); /* set Priority for Systick Interrupt (2nd lowest) */
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// Clock PORT for Digital I/O
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// PM->APBBMASK.reg |= PM_APBBMASK_PORT ;
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//
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// // Clock EIC for I/O interrupts
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// PM->APBAMASK.reg |= PM_APBAMASK_EIC ;
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#if defined(__SAMD51__)
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MCLK->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0 | MCLK_APBAMASK_SERCOM1 | MCLK_APBAMASK_TC0 | MCLK_APBAMASK_TC1;
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MCLK->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2 | MCLK_APBBMASK_SERCOM3 | MCLK_APBBMASK_TCC0 | MCLK_APBBMASK_TCC1 | MCLK_APBBMASK_TC3 | MCLK_APBBMASK_TC2;
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MCLK->APBCMASK.reg |= MCLK_APBCMASK_TCC2 | MCLK_APBCMASK_TCC3 | MCLK_APBCMASK_TC4 | MCLK_APBCMASK_TC5;
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MCLK->APBDMASK.reg |= MCLK_APBDMASK_DAC | MCLK_APBDMASK_SERCOM4 | MCLK_APBDMASK_SERCOM5 | MCLK_APBDMASK_ADC0 | MCLK_APBDMASK_ADC1 | MCLK_APBDMASK_TCC4
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| MCLK_APBDMASK_TC6 | MCLK_APBDMASK_TC7 | MCLK_APBDMASK_SERCOM6 | MCLK_APBDMASK_SERCOM7;
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#else
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// Clock SERCOM for Serial
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PM->APBCMASK.reg |= PM_APBCMASK_SERCOM0 | PM_APBCMASK_SERCOM1 | PM_APBCMASK_SERCOM2 | PM_APBCMASK_SERCOM3 | PM_APBCMASK_SERCOM4 | PM_APBCMASK_SERCOM5 ;
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// Clock TC/TCC for Pulse and Analog
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PM->APBCMASK.reg |= PM_APBCMASK_TCC0 | PM_APBCMASK_TCC1 | PM_APBCMASK_TCC2 | PM_APBCMASK_TC3 | PM_APBCMASK_TC4 | PM_APBCMASK_TC5 ;
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// ATSAMR, for example, doesn't have a DAC
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#ifdef PM_APBCMASK_DAC
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// Clock ADC/DAC for Analog
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PM->APBCMASK.reg |= PM_APBCMASK_ADC | PM_APBCMASK_DAC ;
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#endif
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#endif
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/*
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Commented out to leave pins in default tri-state. This is
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aimed at avoiding power consumption in DeepSleep.
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// Setup all pins (digital and analog) in INPUT mode (default is nothing)
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for (uint32_t ul = 0 ; ul < NUM_DIGITAL_PINS ; ul++ )
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{
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pinMode( ul, INPUT ) ;
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}
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*/
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// Initialize Analog Controller
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// Setting clock
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#if defined(__SAMD51__)
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//set to 1/(1/(48000000/32) * 6) = 250000 SPS
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GCLK->PCHCTRL[ADC0_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK1_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); //use clock generator 1 (48Mhz)
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GCLK->PCHCTRL[ADC1_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK1_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); //use clock generator 1 (48Mhz)
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Adc *adcs[] = {ADC0, ADC1};
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for(int i=0; i<2; i++){
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adcs[i]->CTRLA.bit.PRESCALER = ADC_CTRLA_PRESCALER_DIV32_Val;
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adcs[i]->CTRLB.bit.RESSEL = ADC_CTRLB_RESSEL_10BIT_Val;
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while( adcs[i]->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLB ); //wait for sync
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adcs[i]->SAMPCTRL.reg = 5; // sampling Time Length
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while( adcs[i]->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL ); //wait for sync
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adcs[i]->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND; // No Negative input (Internal Ground)
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while( adcs[i]->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL ); //wait for sync
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// Averaging (see datasheet table in AVGCTRL register description)
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adcs[i]->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM_1 | // 1 sample only (no oversampling nor averaging)
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ADC_AVGCTRL_ADJRES(0x0ul); // Adjusting result by 0
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while( adcs[i]->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL ); //wait for sync
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}
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analogReference( AR_DEFAULT ) ; // Analog Reference is AREF pin (3.3v)
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GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK4_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); //use clock generator 4 (12mhz)
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while (GCLK->PCHCTRL[DAC_GCLK_ID].bit.CHEN == 0);
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while ( DAC->SYNCBUSY.bit.SWRST == 1 ); // Wait for synchronization of registers between the clock domains
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DAC->CTRLA.bit.SWRST = 1;
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while ( DAC->SYNCBUSY.bit.SWRST == 1 ); // Wait for synchronization of registers between the clock domains
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DAC->CTRLB.reg = DAC_CTRLB_REFSEL_VREFPU; // TODO: fix this once silicon bug is fixed
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//set refresh rates
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DAC->DACCTRL[0].bit.REFRESH = 2;
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DAC->DACCTRL[1].bit.REFRESH = 2;
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#else
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//set to 1/(1/(48000000/32) * 6) = 250000 SPS
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while(GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GCM_ADC ) | // Generic Clock ADC
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GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
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GCLK_CLKCTRL_CLKEN ;
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while( ADC->STATUS.bit.SYNCBUSY == 1 ); // Wait for synchronization of registers between the clock domains
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ADC->CTRLB.reg = ADC_CTRLB_PRESCALER_DIV32 | // Divide Clock by 32.
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ADC_CTRLB_RESSEL_10BIT; // 10 bits resolution as default
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ADC->SAMPCTRL.reg = 5; // Sampling Time Length
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while( ADC->STATUS.bit.SYNCBUSY == 1 ); // Wait for synchronization of registers between the clock domains
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ADC->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND; // No Negative input (Internal Ground)
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// Averaging (see datasheet table in AVGCTRL register description)
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ADC->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM_1 | // 1 sample only (no oversampling nor averaging)
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ADC_AVGCTRL_ADJRES(0x0ul); // Adjusting result by 0
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analogReference( AR_DEFAULT ) ; // Analog Reference is AREF pin (3.3v)
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// Initialize DAC
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// Setting clock
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while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY );
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GCM_DAC ) | // Generic Clock ADC
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GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
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GCLK_CLKCTRL_CLKEN ;
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// ATSAMR, for example, doesn't have a DAC
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#ifdef DAC
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while ( DAC->STATUS.bit.SYNCBUSY == 1 ); // Wait for synchronization of registers between the clock domains
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DAC->CTRLB.reg = DAC_CTRLB_REFSEL_AVCC | // Using the 3.3V reference
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DAC_CTRLB_EOEN ; // External Output Enable (Vout)
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#endif
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#endif //SAMD51
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}
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#ifdef __cplusplus
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}
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#endif
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