2ca67fc36b
* Fix pulseIn() on SAMD51 by writing it in plain C, so that the CM0+-specific pulse_asm won't need to be linked. The SAMD51 is fast enough that we can time pulses with micros() Tested with a bunch of pulse lengths from <1us to >1s * Implement a new delayMicroseconds() function for SAMD51 This version enables the "Debug Watchpoint and Trace" module (DWT) in startup.c and then uses the 32bit cycle counter that is part of DWT to count cycles indepenent of instruction timing. Tested for good accuracy with various values between 1 and 2000us.
538 lines
19 KiB
C
538 lines
19 KiB
C
/*
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Copyright (c) 2015 Arduino LLC. All right reserved.
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SAMD51 support added by Adafruit - Copyright (c) 2018 Dean Miller for Adafruit Industries
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "sam.h"
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#include "variant.h"
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#include <stdio.h>
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// Constants for Clock generators
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#define GENERIC_CLOCK_GENERATOR_MAIN (0u)
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#if defined(__SAMD51__)
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#define GENERIC_CLOCK_GENERATOR_XOSC32K (3u)
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#define GENERIC_CLOCK_GENERATOR_48M (1u)
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#define GENERIC_CLOCK_GENERATOR_48M_SYNC GCLK_SYNCBUSY_GENCTRL1
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#define GENERIC_CLOCK_GENERATOR_100M (2u)
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#define GENERIC_CLOCK_GENERATOR_100M_SYNC GCLK_SYNCBUSY_GENCTRL2
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#define GENERIC_CLOCK_GENERATOR_12M (4u)
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#define GENERIC_CLOCK_GENERATOR_12M_SYNC GCLK_SYNCBUSY_GENCTRL4
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//USE DPLL0 for 120MHZ
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#define MAIN_CLOCK_SOURCE GCLK_GENCTRL_SRC_DPLL0
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#define GENERIC_CLOCK_GENERATOR_1M (7u)
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//#define CRYSTALLESS
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#else
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#define GENERIC_CLOCK_GENERATOR_XOSC32K (1u)
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#endif
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#define GENERIC_CLOCK_GENERATOR_OSC32K (1u)
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#define GENERIC_CLOCK_GENERATOR_OSCULP32K (2u) /* Initialized at reset for WDT */
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#define GENERIC_CLOCK_GENERATOR_OSC8M (3u)
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// Constants for Clock multiplexers
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#define GENERIC_CLOCK_MULTIPLEXER_DFLL48M (0u)
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void SystemInit( void )
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{
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//***************** SAMD51 ************************//
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#if defined(__SAMD51__)
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NVMCTRL->CTRLA.reg |= NVMCTRL_CTRLA_RWS(0);
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#ifndef CRYSTALLESS
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/* ----------------------------------------------------------------------------------------------
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* 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator)
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*/
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OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_ENABLE | OSC32KCTRL_XOSC32K_EN32K | OSC32KCTRL_XOSC32K_EN32K | OSC32KCTRL_XOSC32K_CGM_XT | OSC32KCTRL_XOSC32K_XTALEN;
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while( (OSC32KCTRL->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) == 0 ){
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/* Wait for oscillator to be ready */
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}
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#endif //CRYSTALLESS
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//software reset
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GCLK->CTRLA.bit.SWRST = 1;
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while ( GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST ){
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/* wait for reset to complete */
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}
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#ifndef CRYSTALLESS
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/* ----------------------------------------------------------------------------------------------
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* 2) Put XOSC32K as source of Generic Clock Generator 3
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*/
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GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_XOSC32K].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_XOSC32K) | //generic clock gen 3
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GCLK_GENCTRL_GENEN;
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#else
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/* ----------------------------------------------------------------------------------------------
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* 2) Put OSCULP32K as source of Generic Clock Generator 3
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*/
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GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_XOSC32K].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSCULP32K) | GCLK_GENCTRL_GENEN; //generic clock gen 3
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#endif
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while ( GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3 ){
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/* Wait for synchronization */
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}
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/* ----------------------------------------------------------------------------------------------
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* 3) Put Generic Clock Generator 3 as source for Generic Clock Gen 0 (DFLL48M reference)
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*/
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GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSCULP32K) | GCLK_GENCTRL_GENEN;
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/* ----------------------------------------------------------------------------------------------
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* 4) Enable DFLL48M clock
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*/
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while ( GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0 ){
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/* Wait for synchronization */
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}
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/* DFLL Configuration in Open Loop mode */
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OSCCTRL->DFLLCTRLA.reg = 0;
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//GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK3_Val);
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OSCCTRL->DFLLMUL.reg = OSCCTRL_DFLLMUL_CSTEP( 0x1 ) |
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OSCCTRL_DFLLMUL_FSTEP( 0x1 ) |
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OSCCTRL_DFLLMUL_MUL( 0 );
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while ( OSCCTRL->DFLLSYNC.reg & OSCCTRL_DFLLSYNC_DFLLMUL )
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{
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/* Wait for synchronization */
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}
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OSCCTRL->DFLLCTRLB.reg = 0;
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while ( OSCCTRL->DFLLSYNC.reg & OSCCTRL_DFLLSYNC_DFLLCTRLB )
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{
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/* Wait for synchronization */
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}
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OSCCTRL->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE;
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while ( OSCCTRL->DFLLSYNC.reg & OSCCTRL_DFLLSYNC_ENABLE )
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{
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/* Wait for synchronization */
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}
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OSCCTRL->DFLLVAL.reg = OSCCTRL->DFLLVAL.reg;
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while( OSCCTRL->DFLLSYNC.bit.DFLLVAL );
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OSCCTRL->DFLLCTRLB.reg = OSCCTRL_DFLLCTRLB_WAITLOCK |
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OSCCTRL_DFLLCTRLB_CCDIS | OSCCTRL_DFLLCTRLB_USBCRM ;
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while ( !OSCCTRL->STATUS.bit.DFLLRDY )
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{
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/* Wait for synchronization */
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}
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GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_1M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_DIV(24u);
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while ( GCLK->SYNCBUSY.bit.GENCTRL5 ){
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/* Wait for synchronization */
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}
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/* ------------------------------------------------------------------------
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* Set up the PLLs
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*/
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//PLL0 is 120MHz
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GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK7_Val);
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OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(59); //120 Mhz
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while(OSCCTRL->Dpll[0].DPLLSYNCBUSY.bit.DPLLRATIO);
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//MUST USE LBYPASS DUE TO BUG IN REV A OF SAMD51
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OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_GCLK | OSCCTRL_DPLLCTRLB_LBYPASS;
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OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
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while( OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY == 0 || OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK == 0 );
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//PLL1 is 100MHz
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GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK7_Val);
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OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(49); //100 Mhz
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while(OSCCTRL->Dpll[1].DPLLSYNCBUSY.bit.DPLLRATIO);
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//MUST USE LBYPASS DUE TO BUG IN REV A OF SAMD51
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OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_GCLK | OSCCTRL_DPLLCTRLB_LBYPASS;
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OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
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while( OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY == 0 || OSCCTRL->Dpll[1].DPLLSTATUS.bit.LOCK == 0 );
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/* ------------------------------------------------------------------------
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* Set up the peripheral clocks
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*/
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//48MHZ CLOCK FOR USB AND STUFF
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GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_48M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) |
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GCLK_GENCTRL_IDC |
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//GCLK_GENCTRL_OE |
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GCLK_GENCTRL_GENEN;
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while ( GCLK->SYNCBUSY.reg & GENERIC_CLOCK_GENERATOR_48M_SYNC)
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{
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/* Wait for synchronization */
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}
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//100MHZ CLOCK FOR OTHER PERIPHERALS
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GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_100M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DPLL1_Val) |
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GCLK_GENCTRL_IDC |
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//GCLK_GENCTRL_OE |
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GCLK_GENCTRL_GENEN;
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while ( GCLK->SYNCBUSY.reg & GENERIC_CLOCK_GENERATOR_100M_SYNC)
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{
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/* Wait for synchronization */
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}
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//12MHZ CLOCK FOR DAC
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GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_12M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) |
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GCLK_GENCTRL_IDC |
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GCLK_GENCTRL_DIV(4) |
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GCLK_GENCTRL_DIVSEL |
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//GCLK_GENCTRL_OE |
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GCLK_GENCTRL_GENEN;
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while ( GCLK->SYNCBUSY.reg & GENERIC_CLOCK_GENERATOR_12M_SYNC)
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{
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/* Wait for synchronization */
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}
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/*---------------------------------------------------------------------
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* Set up main clock
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*/
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GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_MAIN].reg = GCLK_GENCTRL_SRC(MAIN_CLOCK_SOURCE) |
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GCLK_GENCTRL_IDC |
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//GCLK_GENCTRL_OE |
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GCLK_GENCTRL_GENEN;
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while ( GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0 )
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{
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/* Wait for synchronization */
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}
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MCLK->CPUDIV.reg = MCLK_CPUDIV_DIV_DIV1;
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/* Use the LDO regulator by default */
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SUPC->VREG.bit.SEL = 0;
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/* If desired, enable cache! */
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#if defined(ENABLE_CACHE)
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__disable_irq();
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CMCC->CTRL.reg = 1;
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__enable_irq();
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#endif
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/*---------------------------------------------------------------------
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* Start up the "Debug Watchpoint and Trace" unit, so that we can use
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* it's 32bit cycle counter for timing.
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*/
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
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//*************** END SAMD51 *************************//
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#else
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//********************** SAMD21 *********************//
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/**
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* \brief SystemInit() configures the needed clocks and according Flash Read Wait States.
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* At reset:
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* - OSC8M clock source is enabled with a divider by 8 (1MHz).
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* - Generic Clock Generator 0 (GCLKMAIN) is using OSC8M as source.
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* We need to:
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* 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator), will be used as DFLL48M reference.
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* 2) Put XOSC32K as source of Generic Clock Generator 1
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* 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
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* 4) Enable DFLL48M clock
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* 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
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* 6) Modify PRESCaler value of OSCM to have 8MHz
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* 7) Put OSC8M as source for Generic Clock Generator 3
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*/
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/* Set 1 Flash Wait State for 48MHz, cf tables 20.9 and 35.27 in SAMD21 Datasheet */
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NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val ;
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/* Turn on the digital interface clock */
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PM->APBAMASK.reg |= PM_APBAMASK_GCLK ;
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#if defined(CRYSTALLESS)
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/* ----------------------------------------------------------------------------------------------
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* 1) Enable OSC32K clock (Internal 32.768Hz oscillator)
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*/
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uint32_t calib = (*((uint32_t *) FUSES_OSC32K_CAL_ADDR) & FUSES_OSC32K_CAL_Msk) >> FUSES_OSC32K_CAL_Pos;
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SYSCTRL->OSC32K.reg = SYSCTRL_OSC32K_CALIB(calib) |
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SYSCTRL_OSC32K_STARTUP( 0x6u ) | // cf table 15.10 of product datasheet in chapter 15.8.6
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SYSCTRL_OSC32K_EN32K |
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SYSCTRL_OSC32K_ENABLE;
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY) == 0 ); // Wait for oscillator stabilization
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#else // has crystal
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/* ----------------------------------------------------------------------------------------------
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* 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator)
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*/
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SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP( 0x6u ) | /* cf table 15.10 of product datasheet in chapter 15.8.6 */
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SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K ;
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SYSCTRL->XOSC32K.bit.ENABLE = 1 ; /* separate call, as described in chapter 15.6.3 */
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY) == 0 )
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{
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/* Wait for oscillator stabilization */
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}
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#endif
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/* Software reset the module to ensure it is re-initialized correctly */
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/* Note: Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete.
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* CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete, as described in chapter 13.8.1
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*/
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GCLK->CTRL.reg = GCLK_CTRL_SWRST ;
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while ( (GCLK->CTRL.reg & GCLK_CTRL_SWRST) && (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) )
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{
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/* Wait for reset to complete */
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}
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/* ----------------------------------------------------------------------------------------------
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* 2) Put XOSC32K as source of Generic Clock Generator 1
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*/
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GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) ; // Generic Clock Generator 1
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while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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{
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/* Wait for synchronization */
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}
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/* Write Generic Clock Generator 1 configuration */
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_OSC32K ) | // Generic Clock Generator 1
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#if defined(CRYSTALLESS)
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GCLK_GENCTRL_SRC_OSC32K | // Selected source is Internal 32KHz Oscillator
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#else
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GCLK_GENCTRL_SRC_XOSC32K | // Selected source is External 32KHz Oscillator
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#endif
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// GCLK_GENCTRL_OE | // Output clock to a pin for tests
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GCLK_GENCTRL_GENEN ;
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while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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{
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/* Wait for synchronization */
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}
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/* ----------------------------------------------------------------------------------------------
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* 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
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*/
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GENERIC_CLOCK_MULTIPLEXER_DFLL48M ) | // Generic Clock Multiplexer 0
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GCLK_CLKCTRL_GEN_GCLK1 | // Generic Clock Generator 1 is source
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GCLK_CLKCTRL_CLKEN ;
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while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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{
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/* Wait for synchronization */
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}
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/* ----------------------------------------------------------------------------------------------
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* 4) Enable DFLL48M clock
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*/
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/* DFLL Configuration in Closed Loop mode, cf product datasheet chapter 15.6.7.1 - Closed-Loop Operation */
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/* Remove the OnDemand mode, Bug http://avr32.icgroup.norway.atmel.com/bugzilla/show_bug.cgi?id=9905 */
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
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{
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/* Wait for synchronization */
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}
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SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 31 ) | // Coarse step is 31, half of the max value
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SYSCTRL_DFLLMUL_FSTEP( 511 ) | // Fine step is 511, half of the max value
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SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK + VARIANT_MAINOSC/2) / VARIANT_MAINOSC ) ; // External 32KHz is the reference
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
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{
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/* Wait for synchronization */
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}
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#if defined(CRYSTALLESS)
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#define NVM_SW_CALIB_DFLL48M_COARSE_VAL 58
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// Turn on DFLL
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uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4) + (NVM_SW_CALIB_DFLL48M_COARSE_VAL / 32)) >> (NVM_SW_CALIB_DFLL48M_COARSE_VAL % 32) )
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& ((1 << 6) - 1);
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if (coarse == 0x3f) {
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coarse = 0x1f;
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}
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// TODO(tannewt): Load this value from memory we've written previously. There
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// isn't a value from the Atmel factory.
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uint32_t fine = 0x1ff;
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SYSCTRL->DFLLVAL.bit.COARSE = coarse;
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SYSCTRL->DFLLVAL.bit.FINE = fine;
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/* Write full configuration to DFLL control register */
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SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 0x1f / 4 ) | // Coarse step is 31, half of the max value
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SYSCTRL_DFLLMUL_FSTEP( 10 ) |
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SYSCTRL_DFLLMUL_MUL( (48000) ) ;
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SYSCTRL->DFLLCTRL.reg = 0;
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
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{
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/* Wait for synchronization */
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}
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_MODE |
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SYSCTRL_DFLLCTRL_CCDIS |
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SYSCTRL_DFLLCTRL_USBCRM | /* USB correction */
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SYSCTRL_DFLLCTRL_BPLCKC;
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
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{
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/* Wait for synchronization */
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}
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/* Enable the DFLL */
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SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
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#else // has crystal
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/* Write full configuration to DFLL control register */
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SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE | /* Enable the closed loop mode */
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SYSCTRL_DFLLCTRL_WAITLOCK |
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SYSCTRL_DFLLCTRL_QLDIS ; /* Disable Quick lock */
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|
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|
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
|
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{
|
|
/* Wait for synchronization */
|
|
}
|
|
|
|
/* Enable the DFLL */
|
|
SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
|
|
|
|
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
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(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0 )
|
|
{
|
|
/* Wait for locks flags */
|
|
}
|
|
|
|
#endif
|
|
|
|
while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
|
|
{
|
|
/* Wait for synchronization */
|
|
}
|
|
|
|
/* ----------------------------------------------------------------------------------------------
|
|
* 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
|
|
*/
|
|
GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_MAIN ) ; // Generic Clock Generator 0
|
|
|
|
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
|
|
{
|
|
/* Wait for synchronization */
|
|
}
|
|
|
|
/* Write Generic Clock Generator 0 configuration */
|
|
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_MAIN ) | // Generic Clock Generator 0
|
|
GCLK_GENCTRL_SRC_DFLL48M | // Selected source is DFLL 48MHz
|
|
// GCLK_GENCTRL_OE | // Output clock to a pin for tests
|
|
GCLK_GENCTRL_IDC | // Set 50/50 duty cycle
|
|
GCLK_GENCTRL_GENEN ;
|
|
|
|
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
|
|
{
|
|
/* Wait for synchronization */
|
|
}
|
|
|
|
/* ----------------------------------------------------------------------------------------------
|
|
* 6) Modify PRESCaler value of OSC8M to have 8MHz
|
|
*/
|
|
SYSCTRL->OSC8M.bit.PRESC = SYSCTRL_OSC8M_PRESC_0_Val ; //CMSIS 4.5 changed the prescaler defines
|
|
SYSCTRL->OSC8M.bit.ONDEMAND = 0 ;
|
|
|
|
/* ----------------------------------------------------------------------------------------------
|
|
* 7) Put OSC8M as source for Generic Clock Generator 3
|
|
*/
|
|
GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) ; // Generic Clock Generator 3
|
|
|
|
/* Write Generic Clock Generator 3 configuration */
|
|
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) | // Generic Clock Generator 3
|
|
GCLK_GENCTRL_SRC_OSC8M | // Selected source is RC OSC 8MHz (already enabled at reset)
|
|
// GCLK_GENCTRL_OE | // Output clock to a pin for tests
|
|
GCLK_GENCTRL_GENEN ;
|
|
|
|
while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
|
|
{
|
|
/* Wait for synchronization */
|
|
}
|
|
|
|
/*
|
|
* Now that all system clocks are configured, we can set CPU and APBx BUS clocks.
|
|
* There values are normally the one present after Reset.
|
|
*/
|
|
PM->CPUSEL.reg = PM_CPUSEL_CPUDIV_DIV1 ;
|
|
PM->APBASEL.reg = PM_APBASEL_APBADIV_DIV1_Val ;
|
|
PM->APBBSEL.reg = PM_APBBSEL_APBBDIV_DIV1_Val ;
|
|
PM->APBCSEL.reg = PM_APBCSEL_APBCDIV_DIV1_Val ;
|
|
|
|
SystemCoreClock=VARIANT_MCK ;
|
|
|
|
/* ----------------------------------------------------------------------------------------------
|
|
* 8) Load ADC factory calibration values
|
|
*/
|
|
|
|
// ADC Bias Calibration
|
|
uint32_t bias = (*((uint32_t *) ADC_FUSES_BIASCAL_ADDR) & ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos;
|
|
|
|
// ADC Linearity bits 4:0
|
|
uint32_t linearity = (*((uint32_t *) ADC_FUSES_LINEARITY_0_ADDR) & ADC_FUSES_LINEARITY_0_Msk) >> ADC_FUSES_LINEARITY_0_Pos;
|
|
|
|
// ADC Linearity bits 7:5
|
|
linearity |= ((*((uint32_t *) ADC_FUSES_LINEARITY_1_ADDR) & ADC_FUSES_LINEARITY_1_Msk) >> ADC_FUSES_LINEARITY_1_Pos) << 5;
|
|
|
|
ADC->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | ADC_CALIB_LINEARITY_CAL(linearity);
|
|
|
|
/*
|
|
* 9) Disable automatic NVM write operations
|
|
*/
|
|
NVMCTRL->CTRLB.bit.MANW = 1;
|
|
#endif
|
|
}
|
|
|