From f02bef6fac3af0d481da87eddda5e76b3ab60579 Mon Sep 17 00:00:00 2001 From: jean-marcharvengt Date: Wed, 21 Aug 2019 11:47:50 +0200 Subject: [PATCH] extra emus for ESP32 --- MCUME_esp32/esp8086/.DS_Store | Bin 0 -> 6148 bytes MCUME_esp32/esp8086/Makefile | 9 + MCUME_esp32/esp8086/components/.DS_Store | Bin 0 -> 6148 bytes .../{ => esp8086/components/Audio}/.DS_Store | Bin 6148 -> 6148 bytes .../esp8086/components/Audio/component.mk | 11 + .../esp8086/components/Audio/esp32-hal-dac.c | 56 + .../esp8086/components/Audio/esp32-hal-dac.h | 36 + .../components/Audio/esp32-hal-timer.c | 293 + .../components/Audio/esp32-hal-timer.h | 72 + MCUME_esp32/esp8086/components/Wire/.DS_Store | Bin 0 -> 6148 bytes MCUME_esp32/esp8086/components/Wire/Wire.cpp | 368 + MCUME_esp32/esp8086/components/Wire/Wire.h | 132 + .../esp8086/components/Wire/component.mk | 11 + .../esp8086/components/Wire/esp32-hal-gpio.c | 309 + .../esp8086/components/Wire/esp32-hal-gpio.h | 88 + .../esp8086/components/Wire/esp32-hal-i2c.c | 1683 + .../esp8086/components/Wire/esp32-hal-i2c.h | 82 + .../components/Wire/esp32-hal-matrix.c | 52 + .../components/Wire/esp32-hal-matrix.h | 35 + MCUME_esp32/esp8086/flashapp.sh | 3 + MCUME_esp32/esp8086/main/.DS_Store | Bin 0 -> 6148 bytes MCUME_esp32/esp8086/main/AudioPlaySystem.cpp | 290 + MCUME_esp32/esp8086/main/AudioPlaySystem.h | 23 + MCUME_esp32/esp8086/main/bmpjoy.h | 40 + MCUME_esp32/esp8086/main/bmpvbar.h | 151 + MCUME_esp32/esp8086/main/component.mk | 11 + MCUME_esp32/esp8086/main/cpu.cpp | 2264 ++ MCUME_esp32/esp8086/main/disk.cpp | 263 + MCUME_esp32/esp8086/main/emu.h | 153 + MCUME_esp32/esp8086/main/emuapi.cpp | 1112 + MCUME_esp32/esp8086/main/emuapi.h | 132 + MCUME_esp32/esp8086/main/emul.cpp | 620 + MCUME_esp32/esp8086/main/emul.h | 4 + MCUME_esp32/esp8086/main/font.h | 263 + MCUME_esp32/esp8086/main/font8x8.h | 136 + MCUME_esp32/esp8086/main/go.cpp | 112 + MCUME_esp32/esp8086/main/go.h | 8 + MCUME_esp32/esp8086/main/i8253.cpp | 121 + MCUME_esp32/esp8086/main/i8259.cpp | 83 + MCUME_esp32/esp8086/main/ili9341_t3dma.cpp | 680 + MCUME_esp32/esp8086/main/ili9341_t3dma.h | 154 + MCUME_esp32/esp8086/main/iopins.h | 59 + MCUME_esp32/esp8086/main/keyboard_osd.h | 20 + MCUME_esp32/esp8086/main/main.c | 31 + MCUME_esp32/esp8086/main/network.cpp | 146 + MCUME_esp32/esp8086/main/ports.cpp | 98 + MCUME_esp32/esp8086/main/ps2.h | 89 + MCUME_esp32/esp8086/main/rom.h | 3748 ++ MCUME_esp32/esp8086/partitions.csv | 5 + MCUME_esp32/esp8086/sdkconfig | 721 + MCUME_esp32/esp8086/sdkconfig.old | 705 + MCUME_esp32/espcastaway/.DS_Store | Bin 0 -> 6148 bytes MCUME_esp32/espcastaway/Makefile | 9 + MCUME_esp32/espcastaway/components/.DS_Store | Bin 0 -> 6148 bytes .../espcastaway/components/Audio/.DS_Store | Bin 0 -> 6148 bytes .../espcastaway/components/Audio/component.mk | 11 + .../components/Audio/esp32-hal-dac.c | 56 + .../components/Audio/esp32-hal-dac.h | 36 + .../components/Audio/esp32-hal-timer.c | 293 + .../components/Audio/esp32-hal-timer.h | 72 + .../espcastaway/components/Wire/.DS_Store | Bin 0 -> 6148 bytes .../espcastaway/components/Wire/Wire.cpp | 368 + .../espcastaway/components/Wire/Wire.h | 132 + .../espcastaway/components/Wire/component.mk | 11 + .../components/Wire/esp32-hal-gpio.c | 309 + .../components/Wire/esp32-hal-gpio.h | 88 + .../components/Wire/esp32-hal-i2c.c | 1683 + .../components/Wire/esp32-hal-i2c.h | 82 + .../components/Wire/esp32-hal-matrix.c | 52 + .../components/Wire/esp32-hal-matrix.h | 35 + MCUME_esp32/espcastaway/flashapp.sh | 3 + MCUME_esp32/espcastaway/main/.DS_Store | Bin 0 -> 6148 bytes .../espcastaway/main/68kfame/.DS_Store | Bin 0 -> 6148 bytes .../espcastaway/main/68kfame/component.mk | 14 + MCUME_esp32/espcastaway/main/68kfame/dis.h | 1043 + MCUME_esp32/espcastaway/main/68kfame/fame.h | 190 + .../espcastaway/main/68kfame/famec.cpp | 6052 +++ .../espcastaway/main/68kfame/famec_opcodes.h | 33591 ++++++++++++++++ .../espcastaway/main/68kfame/jumptable.h | 4098 ++ .../espcastaway/main/68kfame/m68k_intrf.cpp | 322 + .../espcastaway/main/68kfame/m68k_intrf.h | 232 + .../espcastaway/main/68korig/68000.cpp | 275 + MCUME_esp32/espcastaway/main/68korig/68000.h | 187 + .../espcastaway/main/68korig/component.mk | 14 + .../espcastaway/main/68korig/m68k_intrf.h | 231 + .../espcastaway/main/68korig/op68000.h | 1066 + .../espcastaway/main/68korig/op68010.h | 1066 + MCUME_esp32/espcastaway/main/68korig/op68k.h | 577 + .../espcastaway/main/68korig/op68kadd.cpp | 809 + .../espcastaway/main/68korig/op68karith.cpp | 844 + .../espcastaway/main/68korig/op68klogop.cpp | 974 + .../espcastaway/main/68korig/op68kmisc.cpp | 1896 + .../espcastaway/main/68korig/op68kmove.cpp | 1335 + .../espcastaway/main/68korig/op68kshift.cpp | 864 + .../espcastaway/main/68korig/op68ksub.cpp | 810 + MCUME_esp32/espcastaway/main/68korig/operin.h | 1 + MCUME_esp32/espcastaway/main/68korig/proto.h | 99 + .../espcastaway/main/68korigbad/.DS_Store | Bin 0 -> 6148 bytes .../espcastaway/main/68korigbad/68000.cpp | 275 + .../espcastaway/main/68korigbad/68000.h | 187 + .../espcastaway/main/68korigbad/component.mk | 19 + .../espcastaway/main/68korigbad/debug.cpp | 1210 + .../espcastaway/main/68korigbad/m68k_intrf.h | 231 + .../espcastaway/main/68korigbad/op68000.h | 1066 + .../espcastaway/main/68korigbad/op68010.h | 1066 + .../espcastaway/main/68korigbad/op68k.h | 577 + .../espcastaway/main/68korigbad/op68kadd.cpp | 809 + .../main/68korigbad/op68karith.cpp | 844 + .../main/68korigbad/op68klogop.cpp | 974 + .../espcastaway/main/68korigbad/op68kmisc.cpp | 1896 + .../espcastaway/main/68korigbad/op68kmove.cpp | 1335 + .../main/68korigbad/op68kshift.cpp | 864 + .../espcastaway/main/68korigbad/op68ksub.cpp | 810 + .../espcastaway/main/68korigbad/operin.h | 1 + .../espcastaway/main/68korigbad/proto.h | 99 + .../espcastaway/main/AudioPlaySystem.cpp | 290 + .../espcastaway/main/AudioPlaySystem.h | 23 + MCUME_esp32/espcastaway/main/blitter.cpp | 211 + MCUME_esp32/espcastaway/main/bmpjoy.h | 40 + MCUME_esp32/espcastaway/main/bmpvbar.h | 151 + MCUME_esp32/espcastaway/main/component.mk | 19 + MCUME_esp32/espcastaway/main/config.h | 129 + MCUME_esp32/espcastaway/main/dcastaway.h | 18 + MCUME_esp32/espcastaway/main/emu.cpp | 580 + MCUME_esp32/espcastaway/main/emu.h | 4 + MCUME_esp32/espcastaway/main/emuapi.cpp | 1112 + MCUME_esp32/espcastaway/main/emuapi.h | 133 + MCUME_esp32/espcastaway/main/fdc.cpp | 520 + MCUME_esp32/espcastaway/main/fdc.cpp_new | 549 + MCUME_esp32/espcastaway/main/font8x8.h | 136 + MCUME_esp32/espcastaway/main/go.cpp | 113 + MCUME_esp32/espcastaway/main/go.h | 8 + MCUME_esp32/espcastaway/main/ikbd.cpp | 814 + MCUME_esp32/espcastaway/main/ikbd.cpp__ | 519 + .../espcastaway/main/ili9341_t3dma.cpp | 680 + MCUME_esp32/espcastaway/main/ili9341_t3dma.h | 154 + MCUME_esp32/espcastaway/main/iopins.h | 60 + MCUME_esp32/espcastaway/main/keyboard_osd.h | 20 + MCUME_esp32/espcastaway/main/main.c | 31 + MCUME_esp32/espcastaway/main/mem.cpp | 510 + MCUME_esp32/espcastaway/main/mem.h | 34 + MCUME_esp32/espcastaway/main/sound.cpp | 493 + MCUME_esp32/espcastaway/main/sound.h | 137 + MCUME_esp32/espcastaway/main/st.cpp | 619 + MCUME_esp32/espcastaway/main/st.h | 306 + .../main/tab_EnvelopeShapeValues.h | 1026 + MCUME_esp32/espcastaway/main/tab_LogTable.h | 18 + MCUME_esp32/espcastaway/main/tab_LogTable16.h | 3 + MCUME_esp32/espcastaway/main/tab_MixTable.h | 130 + .../espcastaway/main/tosnonswap/tos10.h | 12290 ++++++ .../espcastaway/main/tosnonswap/tos12.h | 12290 ++++++ .../espcastaway/main/tosnonswap/tos14.h | 12290 ++++++ MCUME_esp32/espcastaway/main/tossw10.h | 12290 ++++++ MCUME_esp32/espcastaway/main/tossw12.h | 12290 ++++++ MCUME_esp32/espcastaway/main/tossw14.h | 12290 ++++++ MCUME_esp32/espcastaway/partitions.csv | 5 + MCUME_esp32/espcastaway/sdkconfig | 721 + MCUME_esp32/espcastaway/sdkconfig.old | 705 + MCUME_esp32/espvectrex/.DS_Store | Bin 0 -> 6148 bytes MCUME_esp32/espvectrex/Makefile | 9 + MCUME_esp32/espvectrex/components/.DS_Store | Bin 0 -> 6148 bytes .../espvectrex/components/Audio/.DS_Store | Bin 0 -> 6148 bytes .../espvectrex/components/Audio/component.mk | 11 + .../components/Audio/esp32-hal-dac.c | 56 + .../components/Audio/esp32-hal-dac.h | 36 + .../components/Audio/esp32-hal-timer.c | 293 + .../components/Audio/esp32-hal-timer.h | 72 + .../espvectrex/components/Wire/.DS_Store | Bin 0 -> 6148 bytes .../espvectrex/components/Wire/Wire.cpp | 368 + MCUME_esp32/espvectrex/components/Wire/Wire.h | 132 + .../espvectrex/components/Wire/component.mk | 11 + .../components/Wire/esp32-hal-gpio.c | 309 + .../components/Wire/esp32-hal-gpio.h | 88 + .../components/Wire/esp32-hal-i2c.c | 1683 + .../components/Wire/esp32-hal-i2c.h | 82 + .../components/Wire/esp32-hal-matrix.c | 52 + .../components/Wire/esp32-hal-matrix.h | 35 + MCUME_esp32/espvectrex/flashapp.sh | 3 + MCUME_esp32/espvectrex/main/.DS_Store | Bin 0 -> 6148 bytes .../espvectrex/main/AudioPlaySystem.cpp | 290 + MCUME_esp32/espvectrex/main/AudioPlaySystem.h | 23 + MCUME_esp32/espvectrex/main/bmpjoy.h | 40 + MCUME_esp32/espvectrex/main/bmpvbar.h | 151 + MCUME_esp32/espvectrex/main/component.mk | 11 + MCUME_esp32/espvectrex/main/e6809.c | 2623 ++ MCUME_esp32/espvectrex/main/e6809.h | 12 + MCUME_esp32/espvectrex/main/e8910.c | 537 + MCUME_esp32/espvectrex/main/e8910.h | 8 + MCUME_esp32/espvectrex/main/emu.cpp | 280 + MCUME_esp32/espvectrex/main/emu.h | 4 + MCUME_esp32/espvectrex/main/emuapi.cpp | 1113 + MCUME_esp32/espvectrex/main/emuapi.h | 134 + MCUME_esp32/espvectrex/main/font8x8.h | 136 + MCUME_esp32/espvectrex/main/go.cpp | 112 + MCUME_esp32/espvectrex/main/go.h | 8 + MCUME_esp32/espvectrex/main/ili9341_t3dma.cpp | 680 + MCUME_esp32/espvectrex/main/ili9341_t3dma.h | 154 + MCUME_esp32/espvectrex/main/iopins.h | 59 + MCUME_esp32/espvectrex/main/keyboard_osd.h | 20 + MCUME_esp32/espvectrex/main/main.c | 31 + MCUME_esp32/espvectrex/main/osint.h | 8 + MCUME_esp32/espvectrex/main/rom.h | 514 + MCUME_esp32/espvectrex/main/vecx.c | 951 + MCUME_esp32/espvectrex/main/vecx.h | 60 + MCUME_esp32/espvectrex/partitions.csv | 5 + MCUME_esp32/espvectrex/sdkconfig | 721 + MCUME_esp32/espvectrex/sdkconfig.old | 705 + 207 files changed, 184966 insertions(+) create mode 100644 MCUME_esp32/esp8086/.DS_Store create mode 100644 MCUME_esp32/esp8086/Makefile create mode 100644 MCUME_esp32/esp8086/components/.DS_Store rename MCUME_esp32/{ => esp8086/components/Audio}/.DS_Store (92%) create mode 100644 MCUME_esp32/esp8086/components/Audio/component.mk create mode 100644 MCUME_esp32/esp8086/components/Audio/esp32-hal-dac.c create mode 100644 MCUME_esp32/esp8086/components/Audio/esp32-hal-dac.h create mode 100644 MCUME_esp32/esp8086/components/Audio/esp32-hal-timer.c create mode 100644 MCUME_esp32/esp8086/components/Audio/esp32-hal-timer.h create mode 100644 MCUME_esp32/esp8086/components/Wire/.DS_Store create mode 100644 MCUME_esp32/esp8086/components/Wire/Wire.cpp create mode 100644 MCUME_esp32/esp8086/components/Wire/Wire.h create mode 100644 MCUME_esp32/esp8086/components/Wire/component.mk create mode 100644 MCUME_esp32/esp8086/components/Wire/esp32-hal-gpio.c create mode 100644 MCUME_esp32/esp8086/components/Wire/esp32-hal-gpio.h create mode 100644 MCUME_esp32/esp8086/components/Wire/esp32-hal-i2c.c create mode 100644 MCUME_esp32/esp8086/components/Wire/esp32-hal-i2c.h create mode 100644 MCUME_esp32/esp8086/components/Wire/esp32-hal-matrix.c create mode 100644 MCUME_esp32/esp8086/components/Wire/esp32-hal-matrix.h create mode 100755 MCUME_esp32/esp8086/flashapp.sh create mode 100644 MCUME_esp32/esp8086/main/.DS_Store create mode 100644 MCUME_esp32/esp8086/main/AudioPlaySystem.cpp create mode 100644 MCUME_esp32/esp8086/main/AudioPlaySystem.h create mode 100644 MCUME_esp32/esp8086/main/bmpjoy.h create mode 100644 MCUME_esp32/esp8086/main/bmpvbar.h create mode 100644 MCUME_esp32/esp8086/main/component.mk create mode 100755 MCUME_esp32/esp8086/main/cpu.cpp create mode 100755 MCUME_esp32/esp8086/main/disk.cpp create mode 100755 MCUME_esp32/esp8086/main/emu.h create mode 100644 MCUME_esp32/esp8086/main/emuapi.cpp create mode 100644 MCUME_esp32/esp8086/main/emuapi.h create mode 100644 MCUME_esp32/esp8086/main/emul.cpp create mode 100644 MCUME_esp32/esp8086/main/emul.h create mode 100755 MCUME_esp32/esp8086/main/font.h create mode 100644 MCUME_esp32/esp8086/main/font8x8.h create mode 100644 MCUME_esp32/esp8086/main/go.cpp create mode 100644 MCUME_esp32/esp8086/main/go.h create mode 100755 MCUME_esp32/esp8086/main/i8253.cpp create mode 100755 MCUME_esp32/esp8086/main/i8259.cpp create mode 100644 MCUME_esp32/esp8086/main/ili9341_t3dma.cpp create mode 100644 MCUME_esp32/esp8086/main/ili9341_t3dma.h create mode 100644 MCUME_esp32/esp8086/main/iopins.h create mode 100644 MCUME_esp32/esp8086/main/keyboard_osd.h create mode 100644 MCUME_esp32/esp8086/main/main.c create mode 100755 MCUME_esp32/esp8086/main/network.cpp create mode 100755 MCUME_esp32/esp8086/main/ports.cpp create mode 100755 MCUME_esp32/esp8086/main/ps2.h create mode 100755 MCUME_esp32/esp8086/main/rom.h create mode 100755 MCUME_esp32/esp8086/partitions.csv create mode 100644 MCUME_esp32/esp8086/sdkconfig create mode 100644 MCUME_esp32/esp8086/sdkconfig.old create mode 100644 MCUME_esp32/espcastaway/.DS_Store create mode 100644 MCUME_esp32/espcastaway/Makefile create mode 100644 MCUME_esp32/espcastaway/components/.DS_Store create mode 100644 MCUME_esp32/espcastaway/components/Audio/.DS_Store create mode 100644 MCUME_esp32/espcastaway/components/Audio/component.mk create mode 100644 MCUME_esp32/espcastaway/components/Audio/esp32-hal-dac.c create mode 100644 MCUME_esp32/espcastaway/components/Audio/esp32-hal-dac.h create mode 100644 MCUME_esp32/espcastaway/components/Audio/esp32-hal-timer.c create mode 100644 MCUME_esp32/espcastaway/components/Audio/esp32-hal-timer.h create mode 100644 MCUME_esp32/espcastaway/components/Wire/.DS_Store create mode 100644 MCUME_esp32/espcastaway/components/Wire/Wire.cpp create mode 100644 MCUME_esp32/espcastaway/components/Wire/Wire.h create mode 100644 MCUME_esp32/espcastaway/components/Wire/component.mk create mode 100644 MCUME_esp32/espcastaway/components/Wire/esp32-hal-gpio.c create mode 100644 MCUME_esp32/espcastaway/components/Wire/esp32-hal-gpio.h create mode 100644 MCUME_esp32/espcastaway/components/Wire/esp32-hal-i2c.c create mode 100644 MCUME_esp32/espcastaway/components/Wire/esp32-hal-i2c.h create mode 100644 MCUME_esp32/espcastaway/components/Wire/esp32-hal-matrix.c create mode 100644 MCUME_esp32/espcastaway/components/Wire/esp32-hal-matrix.h create mode 100755 MCUME_esp32/espcastaway/flashapp.sh create mode 100644 MCUME_esp32/espcastaway/main/.DS_Store create mode 100644 MCUME_esp32/espcastaway/main/68kfame/.DS_Store create mode 100755 MCUME_esp32/espcastaway/main/68kfame/component.mk create mode 100644 MCUME_esp32/espcastaway/main/68kfame/dis.h create mode 100644 MCUME_esp32/espcastaway/main/68kfame/fame.h create mode 100644 MCUME_esp32/espcastaway/main/68kfame/famec.cpp create mode 100644 MCUME_esp32/espcastaway/main/68kfame/famec_opcodes.h create mode 100644 MCUME_esp32/espcastaway/main/68kfame/jumptable.h create mode 100644 MCUME_esp32/espcastaway/main/68kfame/m68k_intrf.cpp create mode 100644 MCUME_esp32/espcastaway/main/68kfame/m68k_intrf.h create mode 100755 MCUME_esp32/espcastaway/main/68korig/68000.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korig/68000.h create mode 100755 MCUME_esp32/espcastaway/main/68korig/component.mk create mode 100755 MCUME_esp32/espcastaway/main/68korig/m68k_intrf.h create mode 100755 MCUME_esp32/espcastaway/main/68korig/op68000.h create mode 100755 MCUME_esp32/espcastaway/main/68korig/op68010.h create mode 100755 MCUME_esp32/espcastaway/main/68korig/op68k.h create mode 100755 MCUME_esp32/espcastaway/main/68korig/op68kadd.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korig/op68karith.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korig/op68klogop.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korig/op68kmisc.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korig/op68kmove.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korig/op68kshift.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korig/op68ksub.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korig/operin.h create mode 100755 MCUME_esp32/espcastaway/main/68korig/proto.h create mode 100644 MCUME_esp32/espcastaway/main/68korigbad/.DS_Store create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/68000.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/68000.h create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/component.mk create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/debug.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/m68k_intrf.h create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/op68000.h create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/op68010.h create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/op68k.h create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/op68kadd.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/op68karith.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/op68klogop.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/op68kmisc.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/op68kmove.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/op68kshift.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/op68ksub.cpp create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/operin.h create mode 100755 MCUME_esp32/espcastaway/main/68korigbad/proto.h create mode 100644 MCUME_esp32/espcastaway/main/AudioPlaySystem.cpp create mode 100644 MCUME_esp32/espcastaway/main/AudioPlaySystem.h create mode 100755 MCUME_esp32/espcastaway/main/blitter.cpp create mode 100644 MCUME_esp32/espcastaway/main/bmpjoy.h create mode 100644 MCUME_esp32/espcastaway/main/bmpvbar.h create mode 100644 MCUME_esp32/espcastaway/main/component.mk create mode 100755 MCUME_esp32/espcastaway/main/config.h create mode 100755 MCUME_esp32/espcastaway/main/dcastaway.h create mode 100644 MCUME_esp32/espcastaway/main/emu.cpp create mode 100644 MCUME_esp32/espcastaway/main/emu.h create mode 100644 MCUME_esp32/espcastaway/main/emuapi.cpp create mode 100644 MCUME_esp32/espcastaway/main/emuapi.h create mode 100755 MCUME_esp32/espcastaway/main/fdc.cpp create mode 100644 MCUME_esp32/espcastaway/main/fdc.cpp_new create mode 100644 MCUME_esp32/espcastaway/main/font8x8.h create mode 100644 MCUME_esp32/espcastaway/main/go.cpp create mode 100644 MCUME_esp32/espcastaway/main/go.h create mode 100644 MCUME_esp32/espcastaway/main/ikbd.cpp create mode 100644 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MCUME_esp32/espvectrex/main/AudioPlaySystem.cpp create mode 100644 MCUME_esp32/espvectrex/main/AudioPlaySystem.h create mode 100644 MCUME_esp32/espvectrex/main/bmpjoy.h create mode 100644 MCUME_esp32/espvectrex/main/bmpvbar.h create mode 100644 MCUME_esp32/espvectrex/main/component.mk create mode 100755 MCUME_esp32/espvectrex/main/e6809.c create mode 100755 MCUME_esp32/espvectrex/main/e6809.h create mode 100755 MCUME_esp32/espvectrex/main/e8910.c create mode 100755 MCUME_esp32/espvectrex/main/e8910.h create mode 100644 MCUME_esp32/espvectrex/main/emu.cpp create mode 100644 MCUME_esp32/espvectrex/main/emu.h create mode 100644 MCUME_esp32/espvectrex/main/emuapi.cpp create mode 100644 MCUME_esp32/espvectrex/main/emuapi.h create mode 100644 MCUME_esp32/espvectrex/main/font8x8.h create mode 100644 MCUME_esp32/espvectrex/main/go.cpp create mode 100644 MCUME_esp32/espvectrex/main/go.h create mode 100644 MCUME_esp32/espvectrex/main/ili9341_t3dma.cpp create mode 100644 MCUME_esp32/espvectrex/main/ili9341_t3dma.h create mode 100644 MCUME_esp32/espvectrex/main/iopins.h create mode 100644 MCUME_esp32/espvectrex/main/keyboard_osd.h create mode 100644 MCUME_esp32/espvectrex/main/main.c create mode 100755 MCUME_esp32/espvectrex/main/osint.h create mode 100644 MCUME_esp32/espvectrex/main/rom.h create mode 100755 MCUME_esp32/espvectrex/main/vecx.c create mode 100755 MCUME_esp32/espvectrex/main/vecx.h create mode 100755 MCUME_esp32/espvectrex/partitions.csv create mode 100644 MCUME_esp32/espvectrex/sdkconfig create mode 100644 MCUME_esp32/espvectrex/sdkconfig.old diff --git a/MCUME_esp32/esp8086/.DS_Store b/MCUME_esp32/esp8086/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..4234c397f36bcbf3dd4ed3658a4d5ac4beab650f GIT binary patch literal 6148 zcmeHK%}(1u5S|4?H%5pYkXmlO^p=Co?+M8Y>7lnuM(v@kf*l89$=S7Hho}vy{0u#| zZ`2nkZ@{51(b=C^K@L^9AQbILv)}B_%>I0lcQXJ$+T+**XaWF56=>PmED_-sT9Y+B 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It is assumed the directory this Makefile resides in is a +# project subdirectory. +# + +PROJECT_NAME := esp8086 + +include $(IDF_PATH)/make/project.mk + diff --git a/MCUME_esp32/esp8086/components/.DS_Store b/MCUME_esp32/esp8086/components/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..068957253063d9e869b6dca041f8d18a7dd61c92 GIT binary patch literal 6148 zcmeHK%}N6?5T4O36uk84F|Sa;`?jo4(1RBbLRVC<|%e`*uyVBBCXVAWNfQGF+rCe6o)pOP91F{w=aB4uK^y9+ zrB^ELf5aZTrfK_+J<;dG;zkcNVcS30LV-}=)C%Cu7F%8!MjZ--0-?a5fZPuWMX+|vhI)0N(i8w#VOR}q$tA=m zIo6KZ5DbjX6=<&PDF&N6#*@#h9kZdi6MOQ(9{D$UVU3RUlTIhD4WkYPLV>9Qm)2d$ z`+tYOOfkuyxS9f512&f=Yg#sr~;0I9mJyiez literal 0 HcmV?d00001 diff --git a/MCUME_esp32/.DS_Store b/MCUME_esp32/esp8086/components/Audio/.DS_Store similarity index 92% rename from MCUME_esp32/.DS_Store rename to MCUME_esp32/esp8086/components/Audio/.DS_Store index 29ca7c8c706c5f1e9b0de429704e285021f10da5..5008ddfcf53c02e82d7eee2e57c38e5672ef89f6 100644 GIT binary patch delta 68 zcmZoMXfc=|&Zs)EP;8=}A_oHyFfuR*Y`kd3KJh`-W_At%4o20D7r!%4<`+>E1WGX^ QfYbm1h~2Q+QRFZ)066Lo1poj5 delta 149 zcmZoMXfc=|&e%RNQEZ}~qA(K!0|O%ig8&1ANm+1FUQT{q`ou&{N02ZpLn=ctLji*s zLJFdofg385$B@sE#!v+0`~2M-5h`^LoY%#-;=6a_&B QD*$l<5QD*HN0GzK0IrH3e*gdg diff --git a/MCUME_esp32/esp8086/components/Audio/component.mk b/MCUME_esp32/esp8086/components/Audio/component.mk new file mode 100644 index 0000000..61ff442 --- /dev/null +++ b/MCUME_esp32/esp8086/components/Audio/component.mk @@ -0,0 +1,11 @@ +# +# Main component makefile. +# +# This Makefile can be left empty. By default, it will take the sources in the +# src/ directory, compile them and link them into lib(subdirectory_name).a +# in the build directory. This behaviour is entirely configurable, +# please read the ESP-IDF documents if you need to do this. +# + +COMPONENT_ADD_INCLUDEDIRS := . +COMPONENT_SRCDIRS := . \ No newline at end of file diff --git a/MCUME_esp32/esp8086/components/Audio/esp32-hal-dac.c b/MCUME_esp32/esp8086/components/Audio/esp32-hal-dac.c new file mode 100644 index 0000000..4d211fe --- /dev/null +++ b/MCUME_esp32/esp8086/components/Audio/esp32-hal-dac.c @@ -0,0 +1,56 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-dac.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "rom/ets_sys.h" +#include "esp_attr.h" +#include "esp_intr.h" +#include "soc/rtc_io_reg.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/sens_reg.h" +#include "esp32-hal-gpio.h" + + +void IRAM_ATTR __dacWrite(uint8_t pin, uint8_t value) +{ + if(pin < 25 || pin > 26){ + return;//not dac pin + } + pinMode(pin, ANALOG); + uint8_t channel = pin - 25; + + + //Disable Tone + CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL1_REG, SENS_SW_TONE_EN); + + if (channel) { + //Disable Channel Tone + CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN2_M); + //Set the Dac value + SET_PERI_REG_BITS(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_DAC, value, RTC_IO_PDAC2_DAC_S); //dac_output + //Channel output enable + SET_PERI_REG_MASK(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_XPD_DAC | RTC_IO_PDAC2_DAC_XPD_FORCE); + } else { + //Disable Channel Tone + CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN1_M); + //Set the Dac value + SET_PERI_REG_BITS(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_DAC, value, RTC_IO_PDAC1_DAC_S); //dac_output + //Channel output enable + SET_PERI_REG_MASK(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_XPD_DAC | RTC_IO_PDAC1_DAC_XPD_FORCE); + } +} + +extern void dacWrite(uint8_t pin, uint8_t value) __attribute__ ((weak, alias("__dacWrite"))); diff --git a/MCUME_esp32/esp8086/components/Audio/esp32-hal-dac.h b/MCUME_esp32/esp8086/components/Audio/esp32-hal-dac.h new file mode 100644 index 0000000..c311be1 --- /dev/null +++ b/MCUME_esp32/esp8086/components/Audio/esp32-hal-dac.h @@ -0,0 +1,36 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAIN_ESP32_HAL_DAC_H_ +#define MAIN_ESP32_HAL_DAC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +//#include "esp32-hal.h" +#include "driver/gpio.h" + +void dacWrite(uint8_t pin, uint8_t value); + +#ifdef __cplusplus +} +#endif + +#endif /* MAIN_ESP32_HAL_DAC_H_ */ diff --git a/MCUME_esp32/esp8086/components/Audio/esp32-hal-timer.c b/MCUME_esp32/esp8086/components/Audio/esp32-hal-timer.c new file mode 100644 index 0000000..17743a4 --- /dev/null +++ b/MCUME_esp32/esp8086/components/Audio/esp32-hal-timer.c @@ -0,0 +1,293 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-timer.h" +#include "freertos/FreeRTOS.h" +#include "freertos/xtensa_api.h" +#include "freertos/task.h" +#include "rom/ets_sys.h" +#include "soc/timer_group_struct.h" +#include "soc/dport_reg.h" +#include "esp_attr.h" +#include "esp_intr.h" + +#define HWTIMER_LOCK() portENTER_CRITICAL(timer->lock) +#define HWTIMER_UNLOCK() portEXIT_CRITICAL(timer->lock) + +typedef struct { + union { + struct { + uint32_t reserved0: 10; + uint32_t alarm_en: 1; /*When set alarm is enabled*/ + uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/ + uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/ + uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/ + uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/ + uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/ + uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/ + }; + uint32_t val; + } config; + uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/ + uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/ + uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/ + uint32_t alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ + uint32_t alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ + uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/ + uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/ + uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/ +} hw_timer_reg_t; + +typedef struct hw_timer_s { + hw_timer_reg_t * dev; + uint8_t num; + uint8_t group; + uint8_t timer; + portMUX_TYPE lock; +} hw_timer_t; + +static hw_timer_t hw_timer[4] = { + {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE),0,0,0,portMUX_INITIALIZER_UNLOCKED}, + {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x0024),1,0,1,portMUX_INITIALIZER_UNLOCKED}, + {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x1000),2,1,0,portMUX_INITIALIZER_UNLOCKED}, + {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x1024),3,1,1,portMUX_INITIALIZER_UNLOCKED} +}; + +typedef void (*voidFuncPtr)(void); +static voidFuncPtr __timerInterruptHandlers[4] = {0,0,0,0}; + +void IRAM_ATTR __timerISR(void * arg){ + uint32_t s0 = TIMERG0.int_st_timers.val; + uint32_t s1 = TIMERG1.int_st_timers.val; + TIMERG0.int_clr_timers.val = s0; + TIMERG1.int_clr_timers.val = s1; + uint8_t status = (s1 & 3) << 2 | (s0 & 3); + uint8_t i = 4; + //restart the timers that should autoreload + while(i--){ + hw_timer_reg_t * dev = hw_timer[i].dev; + if((status & (1 << i)) && dev->config.autoreload){ + dev->config.alarm_en = 1; + } + } + i = 4; + //call callbacks + while(i--){ + if(__timerInterruptHandlers[i] && status & (1 << i)){ + __timerInterruptHandlers[i](); + } + } +} + +uint64_t timerRead(hw_timer_t *timer){ + timer->dev->update = 1; + uint64_t h = timer->dev->cnt_high; + uint64_t l = timer->dev->cnt_low; + return (h << 32) | l; +} + +uint64_t timerAlarmRead(hw_timer_t *timer){ + uint64_t h = timer->dev->alarm_high; + uint64_t l = timer->dev->alarm_low; + return (h << 32) | l; +} + +void timerWrite(hw_timer_t *timer, uint64_t val){ + timer->dev->load_high = (uint32_t) (val >> 32); + timer->dev->load_low = (uint32_t) (val); + timer->dev->reload = 1; +} + +void timerAlarmWrite(hw_timer_t *timer, uint64_t alarm_value, bool autoreload){ + timer->dev->alarm_high = (uint32_t) (alarm_value >> 32); + timer->dev->alarm_low = (uint32_t) alarm_value; + timer->dev->config.autoreload = autoreload; +} + +void timerSetConfig(hw_timer_t *timer, uint32_t config){ + timer->dev->config.val = config; +} + +uint32_t timerGetConfig(hw_timer_t *timer){ + return timer->dev->config.val; +} + +void timerSetCountUp(hw_timer_t *timer, bool countUp){ + timer->dev->config.increase = countUp; +} + +bool timerGetCountUp(hw_timer_t *timer){ + return timer->dev->config.increase; +} + +void timerSetAutoReload(hw_timer_t *timer, bool autoreload){ + timer->dev->config.autoreload = autoreload; +} + +bool timerGetAutoReload(hw_timer_t *timer){ + return timer->dev->config.autoreload; +} + +void timerSetDivider(hw_timer_t *timer, uint16_t divider){//2 to 65536 + if(!divider){ + divider = 0xFFFF; + } else if(divider == 1){ + divider = 2; + } + int timer_en = timer->dev->config.enable; + timer->dev->config.enable = 0; + timer->dev->config.divider = divider; + timer->dev->config.enable = timer_en; +} + +uint16_t timerGetDivider(hw_timer_t *timer){ + return timer->dev->config.divider; +} + +void timerStart(hw_timer_t *timer){ + timer->dev->config.enable = 1; +} + +void timerStop(hw_timer_t *timer){ + timer->dev->config.enable = 0; +} + +void timerRestart(hw_timer_t *timer){ + timer->dev->config.enable = 0; + timer->dev->config.enable = 1; +} + +bool timerStarted(hw_timer_t *timer){ + return timer->dev->config.enable; +} + +void timerAlarmEnable(hw_timer_t *timer){ + timer->dev->config.alarm_en = 1; +} + +void timerAlarmDisable(hw_timer_t *timer){ + timer->dev->config.alarm_en = 0; +} + +bool timerAlarmEnabled(hw_timer_t *timer){ + return timer->dev->config.alarm_en; +} + +hw_timer_t * timerBegin(uint8_t num, uint16_t divider, bool countUp){ + if(num > 3){ + return NULL; + } + hw_timer_t * timer = &hw_timer[num]; + if(timer->group) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST); + TIMERG1.int_ena.val &= ~BIT(timer->timer); + } else { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST); + TIMERG0.int_ena.val &= ~BIT(timer->timer); + } + timer->dev->config.enable = 0; + timerSetDivider(timer, divider); + timerSetCountUp(timer, countUp); + timerSetAutoReload(timer, false); + timerAttachInterrupt(timer, NULL, false); + timerWrite(timer, 0); + timer->dev->config.enable = 1; + return timer; +} + +void timerEnd(hw_timer_t *timer){ + timer->dev->config.enable = 0; + timerAttachInterrupt(timer, NULL, false); +} + +void timerAttachInterrupt(hw_timer_t *timer, void (*fn)(void), bool edge){ + static bool initialized = false; + static intr_handle_t intr_handle = NULL; + if(intr_handle){ + esp_intr_disable(intr_handle); + } + if(fn == NULL){ + timer->dev->config.level_int_en = 0; + timer->dev->config.edge_int_en = 0; + timer->dev->config.alarm_en = 0; + if(timer->num & 2){ + TIMERG1.int_ena.val &= ~BIT(timer->timer); + } else { + TIMERG0.int_ena.val &= ~BIT(timer->timer); + } + __timerInterruptHandlers[timer->num] = NULL; + } else { + __timerInterruptHandlers[timer->num] = fn; + timer->dev->config.level_int_en = edge?0:1;//When set, an alarm will generate a level type interrupt. + timer->dev->config.edge_int_en = edge?1:0;//When set, an alarm will generate an edge type interrupt. + int intr_source = 0; + if(!edge){ + if(timer->group){ + intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer->timer; + } else { + intr_source = ETS_TG0_T0_LEVEL_INTR_SOURCE + timer->timer; + } + } else { + if(timer->group){ + intr_source = ETS_TG1_T0_EDGE_INTR_SOURCE + timer->timer; + } else { + intr_source = ETS_TG0_T0_EDGE_INTR_SOURCE + timer->timer; + } + } + if(!initialized){ + initialized = true; + esp_intr_alloc(intr_source, (int)(ESP_INTR_FLAG_IRAM|ESP_INTR_FLAG_LOWMED|ESP_INTR_FLAG_EDGE), __timerISR, NULL, &intr_handle); + } else { + intr_matrix_set(esp_intr_get_cpu(intr_handle), intr_source, esp_intr_get_intno(intr_handle)); + } + if(timer->group){ + TIMERG1.int_ena.val |= BIT(timer->timer); + } else { + TIMERG0.int_ena.val |= BIT(timer->timer); + } + } + if(intr_handle){ + esp_intr_enable(intr_handle); + } +} + +void timerDetachInterrupt(hw_timer_t *timer){ + timerAttachInterrupt(timer, NULL, false); +} + +uint64_t timerReadMicros(hw_timer_t *timer){ + uint64_t timer_val = timerRead(timer); + uint16_t div = timerGetDivider(timer); + return timer_val * div / 80; +} + +double timerReadSeconds(hw_timer_t *timer){ + uint64_t timer_val = timerRead(timer); + uint16_t div = timerGetDivider(timer); + return (double)timer_val * div / 80000000; +} + +uint64_t timerAlarmReadMicros(hw_timer_t *timer){ + uint64_t timer_val = timerAlarmRead(timer); + uint16_t div = timerGetDivider(timer); + return timer_val * div / 80; +} + +double timerAlarmReadSeconds(hw_timer_t *timer){ + uint64_t timer_val = timerAlarmRead(timer); + uint16_t div = timerGetDivider(timer); + return (double)timer_val * div / 80000000; +} diff --git a/MCUME_esp32/esp8086/components/Audio/esp32-hal-timer.h b/MCUME_esp32/esp8086/components/Audio/esp32-hal-timer.h new file mode 100644 index 0000000..fa4e8c7 --- /dev/null +++ b/MCUME_esp32/esp8086/components/Audio/esp32-hal-timer.h @@ -0,0 +1,72 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAIN_ESP32_HAL_TIMER_H_ +#define MAIN_ESP32_HAL_TIMER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +//#include "esp32-hal.h" +#include "freertos/FreeRTOS.h" + +struct hw_timer_s; +typedef struct hw_timer_s hw_timer_t; + +hw_timer_t * timerBegin(uint8_t timer, uint16_t divider, bool countUp); +void timerEnd(hw_timer_t *timer); + +void timerSetConfig(hw_timer_t *timer, uint32_t config); +uint32_t timerGetConfig(hw_timer_t *timer); + +void timerAttachInterrupt(hw_timer_t *timer, void (*fn)(void), bool edge); +void timerDetachInterrupt(hw_timer_t *timer); + +void timerStart(hw_timer_t *timer); +void timerStop(hw_timer_t *timer); +void timerRestart(hw_timer_t *timer); +void timerWrite(hw_timer_t *timer, uint64_t val); +void timerSetDivider(hw_timer_t *timer, uint16_t divider); +void timerSetCountUp(hw_timer_t *timer, bool countUp); +void timerSetAutoReload(hw_timer_t *timer, bool autoreload); + +bool timerStarted(hw_timer_t *timer); +uint64_t timerRead(hw_timer_t *timer); +uint64_t timerReadMicros(hw_timer_t *timer); +double timerReadSeconds(hw_timer_t *timer); +uint16_t timerGetDivider(hw_timer_t *timer); +bool timerGetCountUp(hw_timer_t *timer); +bool timerGetAutoReload(hw_timer_t *timer); + +void timerAlarmEnable(hw_timer_t *timer); +void timerAlarmDisable(hw_timer_t *timer); +void timerAlarmWrite(hw_timer_t *timer, uint64_t interruptAt, bool autoreload); + +bool timerAlarmEnabled(hw_timer_t *timer); +uint64_t timerAlarmRead(hw_timer_t *timer); +uint64_t timerAlarmReadMicros(hw_timer_t *timer); +double timerAlarmReadSeconds(hw_timer_t *timer); + + +#ifdef __cplusplus +} +#endif + +#endif /* MAIN_ESP32_HAL_TIMER_H_ */ diff --git a/MCUME_esp32/esp8086/components/Wire/.DS_Store b/MCUME_esp32/esp8086/components/Wire/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..5008ddfcf53c02e82d7eee2e57c38e5672ef89f6 GIT binary patch literal 6148 zcmeH~Jr2S!425mzP>H1@V-^m;4Wg<&0T*E43hX&L&p$$qDprKhvt+--jT7}7np#A3 zem<@ulZcFPQ@L2!n>{z**++&mCkOWA81W14cNZlEfg7;MkzE(HCqgga^y>{tEnwC%0;vJ&^%eQ zLs35+`xjp>T0 +#include +#include +} + +#include "esp32-hal-i2c.h" +#include "Wire.h" +//#include "Arduino.h" + + + + + +TwoWire::TwoWire(uint8_t bus_num) + :num(bus_num & 1) + ,sda(-1) + ,scl(-1) + ,i2c(NULL) + ,rxIndex(0) + ,rxLength(0) + ,rxQueued(0) + ,txIndex(0) + ,txLength(0) + ,txAddress(0) + ,txQueued(0) + ,transmitting(0) + ,last_error(I2C_ERROR_OK) + ,_timeOutMillis(50) +{} + +TwoWire::~TwoWire() +{ + flush(); + if(i2c) { + i2cRelease(i2c); + i2c=NULL; + } +} + +bool TwoWire::begin(int sdaPin, int sclPin, uint32_t frequency) +{ + if(sdaPin < 0) { // default param passed + if(num == 0) { + if(sda==-1) { + sdaPin = SDA; //use Default Pin + } else { + sdaPin = sda; // reuse prior pin + } + } else { + if(sda==-1) { + //log_e("no Default SDA Pin for Second Peripheral"); + return false; //no Default pin for Second Peripheral + } else { + sdaPin = sda; // reuse prior pin + } + } + } + + if(sclPin < 0) { // default param passed + if(num == 0) { + if(scl == -1) { + sclPin = SCL; // use Default pin + } else { + sclPin = scl; // reuse prior pin + } + } else { + if(scl == -1) { + //log_e("no Default SCL Pin for Second Peripheral"); + return false; //no Default pin for Second Peripheral + } else { + sclPin = scl; // reuse prior pin + } + } + } + + sda = sdaPin; + scl = sclPin; + i2c = i2cInit(num, sdaPin, sclPin, frequency); + if(!i2c) { + printf("I2C init failed"); + return false; + } + + flush(); + return true; + +} + +void TwoWire::setTimeOut(uint16_t timeOutMillis) +{ + _timeOutMillis = timeOutMillis; +} + +uint16_t TwoWire::getTimeOut() +{ + return _timeOutMillis; +} + +void TwoWire::setClock(uint32_t frequency) +{ + i2cSetFrequency(i2c, frequency); +} + +size_t TwoWire::getClock() +{ + return i2cGetFrequency(i2c); +} + +/* stickBreaker Nov 2017 ISR, and bigblock 64k-1 + */ +i2c_err_t TwoWire::writeTransmission(uint16_t address, uint8_t *buff, uint16_t size, bool sendStop) +{ + last_error = i2cWrite(i2c, address, buff, size, sendStop, _timeOutMillis); + return last_error; +} + +i2c_err_t TwoWire::readTransmission(uint16_t address, uint8_t *buff, uint16_t size, bool sendStop, uint32_t *readCount) +{ + last_error = i2cRead(i2c, address, buff, size, sendStop, _timeOutMillis, readCount); + return last_error; +} + +void TwoWire::beginTransmission(uint16_t address) +{ + transmitting = 1; + txAddress = address; + txIndex = txQueued; // allow multiple beginTransmission(),write(),endTransmission(false) until endTransmission(true) + txLength = txQueued; + last_error = I2C_ERROR_OK; +} + +/*stickbreaker isr + */ +uint8_t TwoWire::endTransmission(bool sendStop) // Assumes Wire.beginTransaction(), Wire.write() +{ + if(transmitting == 1) { + last_error = writeTransmission(txAddress, &txBuffer[txQueued], txLength - txQueued, sendStop); + rxIndex = 0; + rxLength = rxQueued; + rxQueued = 0; + txQueued = 0; // the SendStop=true will restart all Queueing + if(last_error == I2C_ERROR_CONTINUE){ + // txlength is howmany bytes in txbuffer have been use + txQueued = txLength; + } + } else { + last_error = I2C_ERROR_NO_BEGIN; + flush(); + } + txIndex = 0; + txLength = 0; + transmitting = 0; + return last_error; +} + +/* @stickBreaker 11/2017 fix for ReSTART timeout, ISR + */ +uint8_t TwoWire::requestFrom(uint16_t address, uint8_t size, bool sendStop) +{ + //use internal Wire rxBuffer, multiple requestFrom()'s may be pending, try to share rxBuffer + uint32_t cnt = rxQueued; // currently queued reads, next available position in rxBuffer + if(cnt < (I2C_BUFFER_LENGTH-1) && (size + cnt) <= I2C_BUFFER_LENGTH) { // any room left in rxBuffer + rxQueued += size; + } else { // no room to receive more! + //log_e("rxBuff overflow %d", cnt + size); + cnt = 0; + last_error = I2C_ERROR_MEMORY; + flush(); + return cnt; + } + + last_error = readTransmission(address, &rxBuffer[cnt], size, sendStop, &cnt); + rxIndex = 0; + rxLength = rxQueued; + rxQueued = 0; + txQueued = 0; // the SendStop=true will restart all Queueing + if(last_error != I2C_ERROR_OK){ + cnt = 0; + } + return cnt; +} + +size_t TwoWire::write(uint8_t data) +{ + if(transmitting) { + if(txLength >= I2C_BUFFER_LENGTH) { + last_error = I2C_ERROR_MEMORY; + return 0; + } + txBuffer[txIndex] = data; + ++txIndex; + txLength = txIndex; + return 1; + } + last_error = I2C_ERROR_NO_BEGIN; // no begin, not transmitting + return 0; +} + +size_t TwoWire::write(const uint8_t *data, size_t quantity) +{ + for(size_t i = 0; i < quantity; ++i) { + if(!write(data[i])) { + return i; + } + } + return quantity; + +} + +int TwoWire::available(void) +{ + int result = rxLength - rxIndex; + return result; +} + +int TwoWire::read(void) +{ + int value = -1; + if(rxIndex < rxLength) { + value = rxBuffer[rxIndex]; + ++rxIndex; + } + return value; +} + +int TwoWire::peek(void) +{ + int value = -1; + if(rxIndex < rxLength) { + value = rxBuffer[rxIndex]; + } + return value; +} + +void TwoWire::flush(void) +{ + rxIndex = 0; + rxLength = 0; + txIndex = 0; + txLength = 0; + rxQueued = 0; + txQueued = 0; + i2cFlush(i2c); // cleanup +} + +uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop) +{ + return requestFrom(static_cast(address), static_cast(quantity), static_cast(sendStop)); +} + +uint8_t TwoWire::requestFrom(uint16_t address, uint8_t quantity, uint8_t sendStop) +{ + return requestFrom(address, static_cast(quantity), static_cast(sendStop)); +} + +uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity) +{ + return requestFrom(static_cast(address), static_cast(quantity), true); +} + +uint8_t TwoWire::requestFrom(uint16_t address, uint8_t quantity) +{ + return requestFrom(address, static_cast(quantity), true); +} + +uint8_t TwoWire::requestFrom(int address, int quantity) +{ + return requestFrom(static_cast(address), static_cast(quantity), true); +} + +uint8_t TwoWire::requestFrom(int address, int quantity, int sendStop) +{ + return static_cast(requestFrom(static_cast(address), static_cast(quantity), static_cast(sendStop))); +} + +void TwoWire::beginTransmission(int address) +{ + beginTransmission(static_cast(address)); +} + +void TwoWire::beginTransmission(uint8_t address) +{ + beginTransmission(static_cast(address)); +} + +uint8_t TwoWire::endTransmission(void) +{ + return endTransmission(true); +} + +/* stickbreaker Nov2017 better error reporting + */ +uint8_t TwoWire::lastError() +{ + return (uint8_t)last_error; +} + +const char ERRORTEXT[] = + "OK\0" + "DEVICE\0" + "ACK\0" + "TIMEOUT\0" + "BUS\0" + "BUSY\0" + "MEMORY\0" + "CONTINUE\0" + "NO_BEGIN\0" + "\0"; + + +char * TwoWire::getErrorText(uint8_t err) +{ + uint8_t t = 0; + bool found = false; + char * message = (char*)&ERRORTEXT; + + while(!found && message[0]) { + found = t == err; + if(!found) { + message = message + strlen(message) + 1; + t++; + } + } + if(!found) { + return NULL; + } else { + return message; + } +} + +/*stickbreaker Dump i2c Interrupt buffer, i2c isr Debugging + */ + +uint32_t TwoWire::setDebugFlags( uint32_t setBits, uint32_t resetBits){ + return i2cDebug(i2c,setBits,resetBits); +} + +bool TwoWire::busy(void){ + return ((i2cGetStatus(i2c) & 16 )==16); +} + +TwoWire Wire = TwoWire(0); +TwoWire Wire1 = TwoWire(1); diff --git a/MCUME_esp32/esp8086/components/Wire/Wire.h b/MCUME_esp32/esp8086/components/Wire/Wire.h new file mode 100644 index 0000000..0420b2e --- /dev/null +++ b/MCUME_esp32/esp8086/components/Wire/Wire.h @@ -0,0 +1,132 @@ +/* + TwoWire.h - TWI/I2C library for Arduino & Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts + Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support + Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support + Modified November 2017 by Chuck Todd to use ISR and increase stability. +*/ + +#ifndef TwoWire_h +#define TwoWire_h + +#include "esp32-hal-i2c.h" +#include "freertos/FreeRTOS.h" +#include "freertos/queue.h" + + + +#define SDA (gpio_num_t)4 +#define SCL (gpio_num_t)5 + + +#define STICKBREAKER V1.0.1 +#define I2C_BUFFER_LENGTH 128 +typedef void(*user_onRequest)(void); +typedef void(*user_onReceive)(uint8_t*, int); + +class TwoWire +{ +protected: + uint8_t num; + int8_t sda; + int8_t scl; + i2c_t * i2c; + + uint8_t rxBuffer[I2C_BUFFER_LENGTH]; + uint16_t rxIndex; + uint16_t rxLength; + uint16_t rxQueued; //@stickBreaker + + uint8_t txBuffer[I2C_BUFFER_LENGTH]; + uint16_t txIndex; + uint16_t txLength; + uint16_t txAddress; + uint16_t txQueued; //@stickbreaker + + uint8_t transmitting; + /* slave Mode, not yet Stickbreaker + static user_onRequest uReq[2]; + static user_onReceive uRcv[2]; + void onRequestService(void); + void onReceiveService(uint8_t*, int); + */ + i2c_err_t last_error; // @stickBreaker from esp32-hal-i2c.h + uint16_t _timeOutMillis; + +public: + TwoWire(uint8_t bus_num); + ~TwoWire(); + bool begin(int sda=-1, int scl=-1, uint32_t frequency=0); + + void setClock(uint32_t frequency); // change bus clock without initing hardware + size_t getClock(); // current bus clock rate in hz + + void setTimeOut(uint16_t timeOutMillis); + uint16_t getTimeOut(); + + uint8_t lastError(); + char * getErrorText(uint8_t err); + + //@stickBreaker for big blocks and ISR model + i2c_err_t writeTransmission(uint16_t address, uint8_t* buff, uint16_t size, bool sendStop=true); + i2c_err_t readTransmission(uint16_t address, uint8_t* buff, uint16_t size, bool sendStop=true, uint32_t *readCount=NULL); + + void beginTransmission(uint16_t address); + void beginTransmission(uint8_t address); + void beginTransmission(int address); + + uint8_t endTransmission(bool sendStop); + uint8_t endTransmission(void); + + uint8_t requestFrom(uint16_t address, uint8_t size, bool sendStop); + uint8_t requestFrom(uint16_t address, uint8_t size, uint8_t sendStop); + uint8_t requestFrom(uint16_t address, uint8_t size); + uint8_t requestFrom(uint8_t address, uint8_t size, uint8_t sendStop); + uint8_t requestFrom(uint8_t address, uint8_t size); + uint8_t requestFrom(int address, int size, int sendStop); + uint8_t requestFrom(int address, int size); + + size_t write(uint8_t); + size_t write(const uint8_t *, size_t); + int available(void); + int read(void); + int peek(void); + void flush(void); + + + + void onReceive( void (*)(int) ); + void onRequest( void (*)(void) ); + + uint32_t setDebugFlags( uint32_t setBits, uint32_t resetBits); + bool busy(); +}; + +extern TwoWire Wire; +extern TwoWire Wire1; + + +/* +V1.0.1 02AUG2018 First Fix after release, Correct ReSTART handling, change Debug control, change begin() + to a function, this allow reporting if bus cannot be initialized, Wire.begin() can be used to recover + a hung bus busy condition. +V0.2.2 13APR2018 preserve custom SCL,SDA,Frequency when no parameters passed to begin() +V0.2.1 15MAR2018 Hardware reset, Glitch prevention, adding destructor for second i2c testing +*/ +#endif diff --git a/MCUME_esp32/esp8086/components/Wire/component.mk b/MCUME_esp32/esp8086/components/Wire/component.mk new file mode 100644 index 0000000..61ff442 --- /dev/null +++ b/MCUME_esp32/esp8086/components/Wire/component.mk @@ -0,0 +1,11 @@ +# +# Main component makefile. +# +# This Makefile can be left empty. By default, it will take the sources in the +# src/ directory, compile them and link them into lib(subdirectory_name).a +# in the build directory. This behaviour is entirely configurable, +# please read the ESP-IDF documents if you need to do this. +# + +COMPONENT_ADD_INCLUDEDIRS := . +COMPONENT_SRCDIRS := . \ No newline at end of file diff --git a/MCUME_esp32/esp8086/components/Wire/esp32-hal-gpio.c b/MCUME_esp32/esp8086/components/Wire/esp32-hal-gpio.c new file mode 100644 index 0000000..999113f --- /dev/null +++ b/MCUME_esp32/esp8086/components/Wire/esp32-hal-gpio.c @@ -0,0 +1,309 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include "stdint.h" +#include "esp32-hal-gpio.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "rom/ets_sys.h" +#include "esp_attr.h" +#include "esp_intr.h" +#include "rom/gpio.h" +#include "soc/gpio_reg.h" +#include "soc/io_mux_reg.h" +#include "soc/gpio_struct.h" +#include "soc/rtc_io_reg.h" +#include "esp_system.h" + +#define ESP_REG(addr) *((volatile uint32_t *)(addr)) + +const int8_t esp32_adc2gpio[20] = {36, 37, 38, 39, 32, 33, 34, 35, -1, -1, 4, 0, 2, 15, 13, 12, 14, 27, 25, 26}; + +const DRAM_ATTR esp32_gpioMux_t esp32_gpioMux[GPIO_PIN_COUNT]={ + {0x44, 11, 11, 1}, + {0x88, -1, -1, -1}, + {0x40, 12, 12, 2}, + {0x84, -1, -1, -1}, + {0x48, 10, 10, 0}, + {0x6c, -1, -1, -1}, + {0x60, -1, -1, -1}, + {0x64, -1, -1, -1}, + {0x68, -1, -1, -1}, + {0x54, -1, -1, -1}, + {0x58, -1, -1, -1}, + {0x5c, -1, -1, -1}, + {0x34, 15, 15, 5}, + {0x38, 14, 14, 4}, + {0x30, 16, 16, 6}, + {0x3c, 13, 13, 3}, + {0x4c, -1, -1, -1}, + {0x50, -1, -1, -1}, + {0x70, -1, -1, -1}, + {0x74, -1, -1, -1}, + {0x78, -1, -1, -1}, + {0x7c, -1, -1, -1}, + {0x80, -1, -1, -1}, + {0x8c, -1, -1, -1}, + {0, -1, -1, -1}, + {0x24, 6, 18, -1}, //DAC1 + {0x28, 7, 19, -1}, //DAC2 + {0x2c, 17, 17, 7}, + {0, -1, -1, -1}, + {0, -1, -1, -1}, + {0, -1, -1, -1}, + {0, -1, -1, -1}, + {0x1c, 9, 4, 9}, + {0x20, 8, 5, 8}, + {0x14, 4, 6, -1}, + {0x18, 5, 7, -1}, + {0x04, 0, 0, -1}, + {0x08, 1, 1, -1}, + {0x0c, 2, 2, -1}, + {0x10, 3, 3, -1} +}; + +typedef void (*voidFuncPtr)(void); +typedef void (*voidFuncPtrArg)(void*); +typedef struct { + voidFuncPtr fn; + void* arg; + bool functional; +} InterruptHandle_t; +static InterruptHandle_t __pinInterruptHandlers[GPIO_PIN_COUNT] = {0,}; + +#include "driver/rtc_io.h" + +extern void IRAM_ATTR __pinMode(uint8_t pin, uint8_t mode) +{ + + if(!digitalPinIsValid(pin)) { + return; + } + + uint32_t rtc_reg = rtc_gpio_desc[pin].reg; + if(mode == ANALOG) { + if(!rtc_reg) { + return;//not rtc pin + } + //lock rtc + uint32_t reg_val = ESP_REG(rtc_reg); + if(reg_val & rtc_gpio_desc[pin].mux){ + return;//already in adc mode + } + reg_val &= ~( + (RTC_IO_TOUCH_PAD1_FUN_SEL_V << rtc_gpio_desc[pin].func) + |rtc_gpio_desc[pin].ie + |rtc_gpio_desc[pin].pullup + |rtc_gpio_desc[pin].pulldown); + ESP_REG(RTC_GPIO_ENABLE_W1TC_REG) = (1 << (rtc_gpio_desc[pin].rtc_num + RTC_GPIO_ENABLE_W1TC_S)); + ESP_REG(rtc_reg) = reg_val | rtc_gpio_desc[pin].mux; + //unlock rtc + ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioMux[pin].reg) = ((uint32_t)2 << MCU_SEL_S) | ((uint32_t)2 << FUN_DRV_S) | FUN_IE; + return; + } + + //RTC pins PULL settings + if(rtc_reg) { + //lock rtc + ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].mux); + if(mode & PULLUP) { + ESP_REG(rtc_reg) = (ESP_REG(rtc_reg) | rtc_gpio_desc[pin].pullup) & ~(rtc_gpio_desc[pin].pulldown); + } else if(mode & PULLDOWN) { + ESP_REG(rtc_reg) = (ESP_REG(rtc_reg) | rtc_gpio_desc[pin].pulldown) & ~(rtc_gpio_desc[pin].pullup); + } else { + ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].pullup | rtc_gpio_desc[pin].pulldown); + } + //unlock rtc + } + + uint32_t pinFunction = 0, pinControl = 0; + + //lock gpio + if(mode & INPUT) { + if(pin < 32) { + GPIO.enable_w1tc = ((uint32_t)1 << pin); + } else { + GPIO.enable1_w1tc.val = ((uint32_t)1 << (pin - 32)); + } + } else if(mode & OUTPUT) { + if(pin > 33){ + //unlock gpio + return;//pins above 33 can be only inputs + } else if(pin < 32) { + GPIO.enable_w1ts = ((uint32_t)1 << pin); + } else { + GPIO.enable1_w1ts.val = ((uint32_t)1 << (pin - 32)); + } + } + + if(mode & PULLUP) { + pinFunction |= FUN_PU; + } else if(mode & PULLDOWN) { + pinFunction |= FUN_PD; + } + + pinFunction |= ((uint32_t)2 << FUN_DRV_S);//what are the drivers? + pinFunction |= FUN_IE;//input enable but required for output as well? + + if(mode & (INPUT | OUTPUT)) { + pinFunction |= ((uint32_t)2 << MCU_SEL_S); + } else if(mode == SPECIAL) { + pinFunction |= ((uint32_t)(((pin)==1||(pin)==3)?0:1) << MCU_SEL_S); + } else { + pinFunction |= ((uint32_t)(mode >> 5) << MCU_SEL_S); + } + + ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioMux[pin].reg) = pinFunction; + + if(mode & OPEN_DRAIN) { + pinControl = (1 << GPIO_PIN0_PAD_DRIVER_S); + } + + GPIO.pin[pin].val = pinControl; + //unlock gpio +} + +extern void IRAM_ATTR __digitalWrite(uint8_t pin, uint8_t val) +{ + if(val) { + if(pin < 32) { + GPIO.out_w1ts = ((uint32_t)1 << pin); + } else if(pin < 34) { + GPIO.out1_w1ts.val = ((uint32_t)1 << (pin - 32)); + } + } else { + if(pin < 32) { + GPIO.out_w1tc = ((uint32_t)1 << pin); + } else if(pin < 34) { + GPIO.out1_w1tc.val = ((uint32_t)1 << (pin - 32)); + } + } +} + +extern int IRAM_ATTR __digitalRead(uint8_t pin) +{ + if(pin < 32) { + return (GPIO.in >> pin) & 0x1; + } else if(pin < 40) { + return (GPIO.in1.val >> (pin - 32)) & 0x1; + } + return 0; +} + +static intr_handle_t gpio_intr_handle = NULL; + +static void IRAM_ATTR __onPinInterrupt() +{ + uint32_t gpio_intr_status_l=0; + uint32_t gpio_intr_status_h=0; + + gpio_intr_status_l = GPIO.status; + gpio_intr_status_h = GPIO.status1.val; + GPIO.status_w1tc = gpio_intr_status_l;//Clear intr for gpio0-gpio31 + GPIO.status1_w1tc.val = gpio_intr_status_h;//Clear intr for gpio32-39 + + uint8_t pin=0; + if(gpio_intr_status_l) { + do { + if(gpio_intr_status_l & ((uint32_t)1 << pin)) { + if(__pinInterruptHandlers[pin].fn) { + if(__pinInterruptHandlers[pin].arg){ + ((voidFuncPtrArg)__pinInterruptHandlers[pin].fn)(__pinInterruptHandlers[pin].arg); + } else { + __pinInterruptHandlers[pin].fn(); + } + } + } + } while(++pin<32); + } + if(gpio_intr_status_h) { + pin=32; + do { + if(gpio_intr_status_h & ((uint32_t)1 << (pin - 32))) { + if(__pinInterruptHandlers[pin].fn) { + if(__pinInterruptHandlers[pin].arg){ + ((voidFuncPtrArg)__pinInterruptHandlers[pin].fn)(__pinInterruptHandlers[pin].arg); + } else { + __pinInterruptHandlers[pin].fn(); + } + } + } + } while(++pin + +#define NOP() asm volatile ("nop") + +unsigned long IRAM_ATTR micros() +{ + return (unsigned long) esp_timer_get_time(); +} + +unsigned long IRAM_ATTR millis() +{ + return (unsigned long) (esp_timer_get_time() / 1000); +} + +void delay(uint32_t ms) +{ + vTaskDelay(ms / portTICK_PERIOD_MS); +} + +void IRAM_ATTR delayMicroseconds(uint32_t us) +{ + uint32_t m = micros(); + if(us){ + uint32_t e = (m + us); + if(m > e){ //overflow + while(micros() > e){ + NOP(); + } + } + while(micros() < e){ + NOP(); + } + } +} +//#define I2C_DEV(i) (volatile i2c_dev_t *)((i)?DR_REG_I2C1_EXT_BASE:DR_REG_I2C_EXT_BASE) +//#define I2C_DEV(i) ((i2c_dev_t *)(REG_I2C_BASE(i))) +#define I2C_SCL_IDX(p) ((p==0)?I2CEXT0_SCL_OUT_IDX:((p==1)?I2CEXT1_SCL_OUT_IDX:0)) +#define I2C_SDA_IDX(p) ((p==0)?I2CEXT0_SDA_OUT_IDX:((p==1)?I2CEXT1_SDA_OUT_IDX:0)) + +#define DR_REG_I2C_EXT_BASE_FIXED 0x60013000 +#define DR_REG_I2C1_EXT_BASE_FIXED 0x60027000 + +/* Stickbreaker ISR mode debug support + +ENABLE_I2C_DEBUG_BUFFER + Enable debug interrupt history buffer, fifoTx history buffer. + Setting this define will result in 2570 bytes of RAM being used whenever CORE_DEBUG_LEVEL + is higher than WARNING. Unless you are debugging a problem in the I2C subsystem, + I would recommend you leave it commented out. + */ + +//#define ENABLE_I2C_DEBUG_BUFFER + +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) +#define INTBUFFMAX 64 +#define FIFOMAX 512 +static uint32_t intBuff[INTBUFFMAX][3][2]; +static uint32_t intPos[2]= {0,0}; +static uint16_t fifoBuffer[FIFOMAX]; +static uint16_t fifoPos = 0; +#endif + +// start from tools/sdk/include/soc/soc/i2c_struct.h + +typedef union { + struct { + uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ + uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ + uint32_t reserved14: 17; + uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/ + }; + uint32_t val; +} I2C_COMMAND_t; + +typedef union { + struct { + uint32_t rx_fifo_full_thrhd: 5; + uint32_t tx_fifo_empty_thrhd:5; //Config tx_fifo empty threhd value when using apb fifo access * / + uint32_t nonfifo_en: 1; //Set this bit to enble apb nonfifo access. * / + uint32_t fifo_addr_cfg_en: 1; //When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram. * / + uint32_t rx_fifo_rst: 1; //Set this bit to reset rx fifo when using apb fifo access. * / + // chuck while this bit is 1, the RX fifo is held in REST, Toggle it * / + uint32_t tx_fifo_rst: 1; //Set this bit to reset tx fifo when using apb fifo access. * / + // chuck while this bit is 1, the TX fifo is held in REST, Toggle it * / + uint32_t nonfifo_rx_thres: 6; //when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.* / + uint32_t nonfifo_tx_thres: 6; //when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data. * / + uint32_t reserved26: 6; + }; + uint32_t val; +} I2C_FIFO_CONF_t; + +typedef union { + struct { + uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/ + uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/ + uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/ + uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } I2C_FIFO_ST_t; + +// end from tools/sdk/include/soc/soc/i2c_struct.h + +// sync between dispatch(i2cProcQueue) and worker(i2c_isr_handler_default) +typedef enum { + //I2C_NONE=0, + I2C_STARTUP=1, + I2C_RUNNING, + I2C_DONE +} I2C_STAGE_t; + +typedef enum { + I2C_NONE=0, + I2C_MASTER, + I2C_SLAVE, + I2C_MASTERSLAVE +} I2C_MODE_t; + +// internal Error condition +typedef enum { + // I2C_NONE=0, + I2C_OK=1, + I2C_ERROR, + I2C_ADDR_NAK, + I2C_DATA_NAK, + I2C_ARBITRATION, + I2C_TIMEOUT +} I2C_ERROR_t; + +// i2c_event bits for EVENTGROUP bits +// needed to minimize change events, FreeRTOS Daemon overload, so ISR will only set values +// on Exit. Dispatcher will set bits for each dq before/after ISR completion +#define EVENT_ERROR_NAK (BIT(0)) +#define EVENT_ERROR (BIT(1)) +#define EVENT_ERROR_BUS_BUSY (BIT(2)) +#define EVENT_RUNNING (BIT(3)) +#define EVENT_DONE (BIT(4)) +#define EVENT_IN_END (BIT(5)) +#define EVENT_ERROR_PREV (BIT(6)) +#define EVENT_ERROR_TIMEOUT (BIT(7)) +#define EVENT_ERROR_ARBITRATION (BIT(8)) +#define EVENT_ERROR_DATA_NAK (BIT(9)) +#define EVENT_MASK 0x3F + +// control record for each dq entry +typedef union { + struct { + uint32_t addr: 16; // I2C address, if 10bit must have 0x7800 mask applied, else 8bit + uint32_t mode: 1; // transaction direction 0 write, 1 read + uint32_t stop: 1; // sendStop 0 no, 1 yes + uint32_t startCmdSent: 1; // START cmd has been added to command[] + uint32_t addrCmdSent: 1; // addr WRITE cmd has been added to command[] + uint32_t dataCmdSent: 1; // all necessary DATA(READ/WRITE) cmds added to command[] + uint32_t stopCmdSent: 1; // completed all necessary commands + uint32_t addrReq: 2; // number of addr bytes need to send address + uint32_t addrSent: 2; // number of addr bytes added to FIFO + uint32_t reserved_31: 6; + }; + uint32_t val; +} I2C_DATA_CTRL_t; + +// individual dq element +typedef struct { + uint8_t *data; // data pointer for read/write buffer + uint16_t length; // size of data buffer + uint16_t position; // current position for next char in buffer (lock, portMAX_DELAY) != pdPASS) +#define I2C_MUTEX_UNLOCK() xSemaphoreGive(i2c->lock) + +static i2c_t _i2c_bus_array[2] = { + {(volatile i2c_dev_t *)(DR_REG_I2C_EXT_BASE_FIXED), NULL, 0, -1, -1, I2C_NONE,I2C_NONE,I2C_ERROR_OK,NULL,NULL,NULL,0,0,0,0,0,0}, + {(volatile i2c_dev_t *)(DR_REG_I2C1_EXT_BASE_FIXED), NULL, 1, -1, -1,I2C_NONE,I2C_NONE,I2C_ERROR_OK,NULL,NULL,NULL,0,0,0,0,0,0} +}; +#endif + +/* + * index - command index (0 to 15) + * op_code - is the command + * byte_num - This register is to store the amounts of data that is read and written. byte_num in RSTART, STOP, END is null. + * ack_val - Each data byte is terminated by an ACK bit used to set the bit level. + * ack_exp - This bit is to set an expected ACK value for the transmitter. + * ack_check - This bit is to decide whether the transmitter checks ACK bit. 1 means yes and 0 means no. + * */ + + +/* Stickbreaker ISR mode debug support + */ +static void IRAM_ATTR i2cDumpCmdQueue(i2c_t *i2c) +{ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR)&&(defined ENABLE_I2C_DEBUG_BUFFER) + static const char * const cmdName[] ={"RSTART","WRITE","READ","STOP","END"}; + uint8_t i=0; + while(i<16) { + I2C_COMMAND_t c; + c.val=i2c->dev->command[i].val; + i++; + } +#endif +} + +/* Stickbreaker ISR mode debug support + */ +static void i2cDumpDqData(i2c_t * i2c) +{ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER) + uint16_t a=0; + char buff[140]; + I2C_DATA_QUEUE_t *tdq; + int digits=0,lenDigits=0; + a = i2c->queueCount; + while(a>0) { + digits++; + a /= 10; + } + while(aqueueCount) { // find maximum number of len decimal digits for formatting + if (i2c->dq[a].length > lenDigits ) lenDigits = i2c->dq[a].length; + a++; + } + a=0; + while(lenDigits>0){ + a++; + lenDigits /= 10; + } + lenDigits = a; + a = 0; + while(aqueueCount) { + tdq=&i2c->dq[a]; + char buf1[10],buf2[10]; + sprintf(buf1,"%0*d",lenDigits,tdq->length); + sprintf(buf2,"%0*d",lenDigits,tdq->position); + (tdq->ctrl.addr>0x100)?"10":"7", + (tdq->ctrl.addr>0x100)?(((tdq->ctrl.addr&0x600)>>1)|(tdq->ctrl.addr&0xff)):(tdq->ctrl.addr>>1), + (tdq->ctrl.mode)?'R':'W', + (tdq->ctrl.stop)?"STOP":"", + tdq->data, + buf1,buf2, + tdq->ctrl.startCmdSent,tdq->ctrl.addrCmdSent,tdq->ctrl.dataCmdSent,(tdq->ctrl.stop)?tdq->ctrl.stopCmdSent:0,tdq->ctrl.addrSent + ); + uint16_t offset = 0; + while(offsetlength) { + memset(buff,' ',140); + buff[139]='\0'; + uint16_t i = 0,j; + j=sprintf(buff,"0x%04x: ",offset); + while((i<32)&&(offset < tdq->length)) { + char ch = tdq->data[offset]; + sprintf((char*)&buff[(i*3)+41],"%02x ",ch); + if((ch<32)||(ch>126)) { + ch='.'; + } + j+=sprintf((char*)&buff[j],"%c",ch); + buff[j]=' '; + i++; + offset++; + } + } + a++; + } +#endif +} + +static void i2cDumpI2c(i2c_t * i2c) +{ +#if !CONFIG_DISABLE_HAL_LOCKS +#endif + + if(i2c->dq) { + i2cDumpDqData(i2c); + } +} + +static void i2cDumpInts(uint8_t num) +{ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + + uint32_t b; + for(uint32_t a=1; a<=INTBUFFMAX; a++) { + b=(a+intPos[num])%INTBUFFMAX; + if(intBuff[b][0][num]!=0) { + //log_i("[%02d]\t0x%04x\t0x%04x\t0x%04x\t0x%04x\t0x%08x",b,((intBuff[b][0][num]>>16)&0xFFFF),(intBuff[b][0][num]&0xFFFF),((intBuff[b][1][num]>>16)&0xFFFF),(intBuff[b][1][num]&0xFFFF),intBuff[b][2][num]); + } + } +#else +#endif +} + +static void IRAM_ATTR i2cDumpStatus(i2c_t * i2c){ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER) + typedef union { + struct { + uint32_t ack_rec: 1; /*This register stores the value of ACK bit.*/ + uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write slave.*/ + uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/ + uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes to high level.*/ + uint32_t bus_busy: 1; /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ + uint32_t slave_addressed: 1; /*when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level.*/ + uint32_t byte_trans: 1; /*This register changes to high level when one byte is transferred.*/ + uint32_t reserved7: 1; + uint32_t rx_fifo_cnt: 6; /*This register represent the amount of data need to send.*/ + uint32_t reserved14: 4; + uint32_t tx_fifo_cnt: 6; /*This register stores the amount of received data in ram.*/ + uint32_t scl_main_state_last: 3; /*This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ + uint32_t reserved27: 1; + uint32_t scl_state_last: 3; /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } status_reg; + + status_reg sr; + sr.val= i2c->dev->status_reg.val; + +#endif +} + +static void i2cDumpFifo(i2c_t * i2c){ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER) +char buf[64]; +uint16_t k = 0; +uint16_t i = fifoPos+1; + i %=FIFOMAX; +while((fifoBuffer[i]==0)&&(i!=fifoPos)){ + i++; + i %=FIFOMAX; +} +if(i != fifoPos){// actual data + do{ + if(fifoBuffer[i] & 0x8000){ // address byte + if(fifoBuffer[i] & 0x100) { // read + if(fifoBuffer[i] & 0x1) { // valid read dev id + k+= sprintf(&buf[k],"READ 0x%02X",(fifoBuffer[i]&0xff)>>1); + } else { // invalid read dev id + k+= sprintf(&buf[k],"Bad READ 0x%02X",(fifoBuffer[i]&0xff)); + } + } else { // write + if(fifoBuffer[i] & 0x1) { // bad write dev id + k+= sprintf(&buf[k],"bad WRITE 0x%02X",(fifoBuffer[i]&0xff)); + } else { // good Write + k+= sprintf(&buf[k],"WRITE 0x%02X",(fifoBuffer[i]&0xff)>>1); + } + } + } else k += sprintf(&buf[k],"% 4X ",fifoBuffer[i]); + + i++; + i %= FIFOMAX; + bool outBuffer=false; + if( fifoBuffer[i] & 0x8000){ + outBuffer=true; + k=0; + } + outBuffer = false; + if(k>50) { + k=sprintf(buf,"-> "); + } + }while( i!= fifoPos); +} +#endif +} + +static void IRAM_ATTR i2cTriggerDumps(i2c_t * i2c, uint8_t trigger, const char locus[]){ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER) + if( trigger ){ + //log_i("%s",locus); + if(trigger & 1) i2cDumpI2c(i2c); + if(trigger & 2) i2cDumpInts(i2c->num); + if(trigger & 4) i2cDumpCmdQueue(i2c); + if(trigger & 8) i2cDumpStatus(i2c); + if(trigger & 16) i2cDumpFifo(i2c); + } +#endif +} + // end of debug support routines + +static void IRAM_ATTR i2cSetCmd(i2c_t * i2c, uint8_t index, uint8_t op_code, uint8_t byte_num, bool ack_val, bool ack_exp, bool ack_check) +{ + I2C_COMMAND_t cmd; + cmd.val=0; + cmd.ack_en = ack_check; + cmd.ack_exp = ack_exp; + cmd.ack_val = ack_val; + cmd.byte_num = byte_num; + cmd.op_code = op_code; + i2c->dev->command[index].val = cmd.val; +} + + +static void IRAM_ATTR fillCmdQueue(i2c_t * i2c, bool INTS) +{ + /* this function is called on initial i2cProcQueue() or when a I2C_END_DETECT_INT occurs + */ + uint16_t cmdIdx = 0; + uint16_t qp = i2c->queuePos; // all queues before queuePos have been completely processed, + // so look start by checking the 'current queue' so see if it needs commands added to + // hardware peripheral command list. walk through each queue entry until all queues have been + // checked + bool done; + bool needMoreCmds = false; + bool ena_rx=false; // if we add a read op, better enable Rx_Fifo IRQ + bool ena_tx=false; // if we add a Write op, better enable TX_Fifo IRQ + + while(!needMoreCmds&&(qp < i2c->queueCount)) { // check if more possible cmds + if(i2c->dq[qp].ctrl.stopCmdSent) {// marks that all required cmds[] have been added to peripheral + qp++; + } else { + needMoreCmds=true; + } + } + + done=(!needMoreCmds)||(cmdIdx>14); + + while(!done) { // fill the command[] until either 0..14 filled or out of cmds and last cmd is STOP + //CMD START + I2C_DATA_QUEUE_t *tdq=&i2c->dq[qp]; // simpler coding + + if((!tdq->ctrl.startCmdSent) && (cmdIdx < 14)) { // has this dq element's START command been added? + // (cmdIdx<14) because a START op cannot directly precede an END op, else a time out cascade occurs + i2cSetCmd(i2c, cmdIdx++, I2C_CMD_RSTART, 0, false, false, false); + tdq->ctrl.startCmdSent=1; + } + + //CMD WRITE ADDRESS + if((!done)&&(tdq->ctrl.startCmdSent)) { // have to leave room for continue(END), and START must have been sent! + if(!tdq->ctrl.addrCmdSent) { + i2cSetCmd(i2c, cmdIdx++, I2C_CMD_WRITE, tdq->ctrl.addrReq, false, false, true); //load address in cmdlist, validate (low) ack + tdq->ctrl.addrCmdSent=1; + done =(cmdIdx>14); + ena_tx=true; // tx Data necessary + } + } + + /* Can I have another Sir? + ALL CMD queues must be terminated with either END or STOP. + + If END is used, when refilling the cmd[] next time, no entries from END to [15] can be used. + AND the cmd[] must be filled starting at [0] with commands. Either fill all 15 [0]..[14] and leave the + END in [15] or include a STOP in one of the positions [0]..[14]. Any entries after a STOP are IGNORED by the StateMachine. + The END operation does not complete until ctr->trans_start=1 has been issued. + + So, only refill from [0]..[14], leave [15] for a continuation(END) if necessary. + As a corollary, once END exists in [15], you do not need to overwrite it for the + next continuation. It is never modified. But, I update it every time because it might + actually be the first time! + + 23NOV17 START cannot proceed END. if START is in[14], END cannot be in [15]. + So, if END is moved to [14], [14] and [15] can no longer be used for anything other than END. + If a START is found in [14] then a prior READ or WRITE must be expanded so that there is no START element in [14]. + */ + + if((!done)&&(tdq->ctrl.addrCmdSent)) { //room in command[] for at least One data (read/Write) cmd + uint8_t blkSize=0; // max is 255 + while(( tdq->cmdBytesNeeded > tdq->ctrl.mode )&&(!done )) { // more bytes needed and room in cmd queue, leave room for END + blkSize = (tdq->cmdBytesNeeded > 255)?255:(tdq->cmdBytesNeeded - tdq->ctrl.mode); // Last read cmd needs different ACK setting, so leave 1 byte remainder on reads + tdq->cmdBytesNeeded -= blkSize; + if(tdq->ctrl.mode==1) { //read mode + i2cSetCmd(i2c, (cmdIdx)++, I2C_CMD_READ, blkSize,false,false,false); // read cmd, this can't be the last read. + ena_rx=true; // need to enable rxFifo IRQ + } else { // write + i2cSetCmd(i2c, cmdIdx++, I2C_CMD_WRITE, blkSize, false, false, true); // check for Nak + ena_tx=true; // need to enable txFifo IRQ + } + done = cmdIdx>14; //have to leave room for END + } + + if(!done) { // buffer is not filled completely + if((tdq->ctrl.mode==1)&&(tdq->cmdBytesNeeded==1)) { //special last read byte NAK + i2cSetCmd(i2c, (cmdIdx)++, I2C_CMD_READ, 1,true,false,false); + // send NAK to mark end of read + tdq->cmdBytesNeeded=0; + done = cmdIdx > 14; + ena_rx=true; + } + } + + tdq->ctrl.dataCmdSent=(tdq->cmdBytesNeeded==0); // enough command[] to send all data + + if((!done)&&(tdq->ctrl.dataCmdSent)) { // possibly add stop + if(!tdq->ctrl.stopCmdSent){ + if(tdq->ctrl.stop) { //send a stop + i2cSetCmd(i2c, (cmdIdx)++,I2C_CMD_STOP,0,false,false,false); + done = cmdIdx > 14; + } + tdq->ctrl.stopCmdSent = 1; + } + } + } + + if((cmdIdx==14)&&(!tdq->ctrl.startCmdSent)) { + // START would have preceded END, causes SM TIMEOUT + // need to stretch out a prior WRITE or READ to two Command[] elements + done = false; // reuse it + uint16_t i = 13; // start working back until a READ/WRITE has >1 numBytes + cmdIdx =15; + while(!done) { + i2c->dev->command[i+1].val = i2c->dev->command[i].val; // push it down + if (((i2c->dev->command[i].op_code == 1)||(i2c->dev->command[i].op_code==2))) { + /* add a dummy read/write cmd[] with num_bytes set to zero,just a place holder in the cmd[]list + */ + i2c->dev->command[i].byte_num = 0; + done = true; + + } else { + if(i > 0) { + i--; + } else { // unable to stretch, fatal + i2cDumpCmdQueue(i2c); + done = true; + } + } + } + + } + + + if(cmdIdx==15) { //need continuation, even if STOP is in 14, it will not matter + // cmd buffer is almost full, Add END as a continuation feature + i2cSetCmd(i2c, (cmdIdx)++,I2C_CMD_END, 0,false,false,false); + i2c->dev->int_ena.end_detect=1; + i2c->dev->int_clr.end_detect=1; + done = true; + } + + if(!done) { + if(tdq->ctrl.stopCmdSent) { // this queue element has been completely added to command[] buffer + qp++; + if(qp < i2c->queueCount) { + tdq = &i2c->dq[qp]; + } else { + done = true; + } + } + } + + }// while(!done) + if(INTS) { // don't want to prematurely enable fifo ints until ISR is ready to handle them. + if(ena_rx) { + i2c->dev->int_ena.rx_fifo_full = 1; + } + if(ena_tx) { + i2c->dev->int_ena.tx_fifo_empty = 1; + } + } +} + +static void IRAM_ATTR fillTxFifo(i2c_t * i2c) +{ + /* + 12/01/2017 The Fifo's are independent, 32 bytes of tx and 32 bytes of Rx. + overlap is not an issue, just keep them full/empty the status_reg.xx_fifo_cnt + tells the truth. And the INT's fire correctly + */ + uint16_t a=i2c->queuePos; // currently executing dq, + bool full=!(i2c->dev->status_reg.tx_fifo_cnt<31); + uint8_t cnt; + bool rxQueueEncountered = false; + while((a < i2c->queueCount) && !full) { + I2C_DATA_QUEUE_t *tdq = &i2c->dq[a]; + cnt=0; + // add to address to fifo ctrl.addr already has R/W bit positioned correctly + if(tdq->ctrl.addrSent < tdq->ctrl.addrReq) { // need to send address bytes + if(tdq->ctrl.addrReq==2) { //10bit + if(tdq->ctrl.addrSent==0) { //10bit highbyte needs sent + if(!full) { // room in fifo + i2c->dev->fifo_data.val = ((tdq->ctrl.addr>>8)&0xFF); + cnt++; + tdq->ctrl.addrSent=1; //10bit highbyte sent + } + } + full=!(i2c->dev->status_reg.tx_fifo_cnt<31); + + if(tdq->ctrl.addrSent==1) { //10bit Lowbyte needs sent + if(!full) { // room in fifo + i2c->dev->fifo_data.val = tdq->ctrl.addr&0xFF; + cnt++; + tdq->ctrl.addrSent=2; //10bit lowbyte sent + } + } + } else { // 7bit} + if(tdq->ctrl.addrSent==0) { // 7bit Lowbyte needs sent + if(!full) { // room in fifo + i2c->dev->fifo_data.val = tdq->ctrl.addr&0xFF; + cnt++; + tdq->ctrl.addrSent=1; // 7bit lowbyte sent +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + uint16_t a = 0x8000 | tdq->ctrl.addr | (tdq->ctrl.mode<<8); + fifoBuffer[fifoPos++] = a; + fifoPos %= FIFOMAX; +#endif + } + } + } + } + // add write data to fifo + if(tdq->ctrl.mode==0) { // write + if(tdq->ctrl.addrSent == tdq->ctrl.addrReq) { //address has been sent, is Write Mode! + uint32_t moveCnt = 32 - i2c->dev->status_reg.tx_fifo_cnt; // how much room in txFifo? + while(( moveCnt>0)&&(tdq->position < tdq->length)) { +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + fifoBuffer[fifoPos++] = tdq->data[tdq->position]; + fifoPos %= FIFOMAX; +#endif + i2c->dev->fifo_data.val = tdq->data[tdq->position++]; + cnt++; + moveCnt--; + + } + } + } else { // read Queue Encountered, can't update QueuePos past this point, emptyRxfifo will do it + if( ! rxQueueEncountered ) { + rxQueueEncountered = true; + if(a > i2c->queuePos){ + i2c->queuePos = a; + } + } + } +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + + // update debug buffer tx counts + cnt += intBuff[intPos[i2c->num]][1][i2c->num]>>16; + intBuff[intPos[i2c->num]][1][i2c->num] = (intBuff[intPos[i2c->num]][1][i2c->num]&0xFFFF)|(cnt<<16); + +#endif + full=!(i2c->dev->status_reg.tx_fifo_cnt<31); + if(!full) { + a++; // check next buffer for address tx, or write data + } + } + + if(a >= i2c->queueCount ) { // disable TX IRQ, all tx Data has been queued + i2c->dev->int_ena.tx_fifo_empty= 0; + } + + i2c->dev->int_clr.tx_fifo_empty=1; +} + + +static void IRAM_ATTR emptyRxFifo(i2c_t * i2c) +{ + uint32_t d, cnt=0, moveCnt; + + moveCnt = i2c->dev->status_reg.rx_fifo_cnt;//no need to check the reg until this many are read + + while((moveCnt > 0)&&(i2c->queuePos < i2c->queueCount)){ // data to move + + I2C_DATA_QUEUE_t *tdq =&i2c->dq[i2c->queuePos]; //short cut + + while((tdq->position >= tdq->length)&&( i2c->queuePos < i2c->queueCount)){ // find were to store + i2c->queuePos++; + tdq = &i2c->dq[i2c->queuePos]; + } + + if(i2c->queuePos >= i2c->queueCount){ // bad stuff, rx data but no place to put it! + // discard + while(moveCnt>0){ + d = i2c->dev->fifo_data.val; + moveCnt--; + cnt++; + } + break; + } + + if(tdq->ctrl.mode == 1){ // read command + if(moveCnt > (tdq->length - tdq->position)) { //make sure they go in this dq + // part of these reads go into the next dq + moveCnt = (tdq->length - tdq->position); + } + } else {// error + // discard + while(moveCnt>0){ + d = i2c->dev->fifo_data.val; + moveCnt--; + cnt++; + } + break; + } + + while(moveCnt > 0) { // store data + d = i2c->dev->fifo_data.val; + moveCnt--; + cnt++; + tdq->data[tdq->position++] = (d&0xFF); + } + + moveCnt = i2c->dev->status_reg.rx_fifo_cnt; //any more out there? + } + +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&& (defined ENABLE_I2C_DEBUG_BUFFER) + // update Debug rxCount + cnt += (intBuff[intPos[i2c->num]][1][i2c->num])&0xffFF; + intBuff[intPos[i2c->num]][1][i2c->num] = (intBuff[intPos[i2c->num]][1][i2c->num]&0xFFFF0000)|cnt; +#endif +} + +static void IRAM_ATTR i2cIsrExit(i2c_t * i2c,const uint32_t eventCode,bool Fatal) +{ + + switch(eventCode) { + case EVENT_DONE: + i2c->error = I2C_OK; + break; + case EVENT_ERROR_NAK : + i2c->error =I2C_ADDR_NAK; + break; + case EVENT_ERROR_DATA_NAK : + i2c->error =I2C_DATA_NAK; + break; + case EVENT_ERROR_TIMEOUT : + i2c->error = I2C_TIMEOUT; + break; + case EVENT_ERROR_ARBITRATION: + i2c->error = I2C_ARBITRATION; + break; + default : + i2c->error = I2C_ERROR; + } + uint32_t exitCode = EVENT_DONE | eventCode |(Fatal?EVENT_ERROR:0); + if((i2c->queuePos < i2c->queueCount) && (i2c->dq[i2c->queuePos].ctrl.mode == 1)) { + emptyRxFifo(i2c); // grab last few characters + } + i2c->dev->int_ena.val = 0; // shut down interrupts + i2c->dev->int_clr.val = 0x1FFF; + i2c->stage = I2C_DONE; + i2c->exitCode = exitCode; //true eventcode + + portBASE_TYPE HPTaskAwoken = pdFALSE,xResult; + // try to notify Dispatch we are done, + // else the 50ms time out will recover the APP, just a little slower + HPTaskAwoken = pdFALSE; + xResult = xEventGroupSetBitsFromISR(i2c->i2c_event, exitCode, &HPTaskAwoken); + if(xResult == pdPASS) { + if(HPTaskAwoken==pdTRUE) { + portYIELD_FROM_ISR(); + } + } + +} + +static void IRAM_ATTR i2c_update_error_byte_cnt(i2c_t * i2c) +{ +/* i2c_update_error_byte_cnt 07/18/2018 + Only called after an error has occurred, so, most of the time this function is never used. + This function obliterates the need to interrupt monitor each byte transferred, at high bitrates + the byte interrupts were overwhelming the OS. Spurious Interrupts were being generated. + it updates errorByteCnt, errorQueue. + */ + uint16_t a=0; // start at top of DQ, count how many bytes added to tx fifo, and received from rx_fifo. + int16_t bc = 0; + I2C_DATA_QUEUE_t *tdq; + i2c->errorByteCnt = 0; + while( a < i2c->queueCount){ // add up all bytes loaded into fifo's + tdq = &i2c->dq[a]; + i2c->errorByteCnt += tdq->ctrl.addrSent; + i2c->errorByteCnt += tdq->position; + a++; + } + // now errorByteCnt contains total bytes moved into and out of FIFO's + // but, there may still be bytes waiting in Fifo's + i2c->errorByteCnt -= i2c->dev->status_reg.tx_fifo_cnt; // waiting to go out; + i2c->errorByteCnt += i2c->dev->status_reg.rx_fifo_cnt; // already received +// now walk thru DQ again, find which byte is 'current' + bc = i2c->errorByteCnt; + i2c->errorQueue = 0; + while( i2c->errorQueue < i2c->queueCount ){ + tdq = &i2c->dq[i2c->errorQueue]; + if(bc>0){ // not found yet + if( tdq->ctrl.addrSent >= bc){ // in address + bc = -1; // in address + break; + } else { + bc -= tdq->ctrl.addrSent; + if( tdq->length > bc) { // data nak + break; + } else { // count down + bc -= tdq->length; + } + } + } else break; + + i2c->errorQueue++; + } + + i2c->errorByteCnt = bc; + } + +static void IRAM_ATTR i2c_isr_handler_default(void* arg) +{ + i2c_t* p_i2c = (i2c_t*) arg; // recover data + uint32_t activeInt = p_i2c->dev->int_status.val&0x7FF; + + if(p_i2c->stage==I2C_DONE) { //get Out, can't service, not configured + p_i2c->dev->int_ena.val = 0; + p_i2c->dev->int_clr.val = 0x1FFF; +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + uint32_t raw = p_i2c->dev->int_raw.val; + //log_w("eject raw=%p, int=%p",raw,activeInt); +#endif + return; + } + while (activeInt != 0) { // Ordering of 'if(activeInt)' statements is important, don't change + + #if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + if(activeInt==(intBuff[intPos[p_i2c->num]][0][p_i2c->num]&0x1fff)) { + intBuff[intPos[p_i2c->num]][0][p_i2c->num] = (((intBuff[intPos[p_i2c->num]][0][p_i2c->num]>>16)+1)<<16)|activeInt; + } else { + intPos[p_i2c->num]++; + intPos[p_i2c->num] %= INTBUFFMAX; + intBuff[intPos[p_i2c->num]][0][p_i2c->num] = (1<<16) | activeInt; + intBuff[intPos[p_i2c->num]][1][p_i2c->num] = 0; + } + + intBuff[intPos[p_i2c->num]][2][p_i2c->num] = xTaskGetTickCountFromISR(); // when IRQ fired + +#endif + + if (activeInt & I2C_TRANS_START_INT_ST_M) { + if(p_i2c->stage==I2C_STARTUP) { + p_i2c->stage=I2C_RUNNING; + } + + activeInt &=~I2C_TRANS_START_INT_ST_M; + p_i2c->dev->int_ena.trans_start = 1; // already enabled? why Again? + p_i2c->dev->int_clr.trans_start = 1; // so that will trigger after next 'END' + } + + if (activeInt & I2C_TXFIFO_EMPTY_INT_ST) {//should this be before Trans_start? + fillTxFifo(p_i2c); //fillTxFifo will enable/disable/clear interrupt + activeInt&=~I2C_TXFIFO_EMPTY_INT_ST; + } + + if(activeInt & I2C_RXFIFO_FULL_INT_ST) { + emptyRxFifo(p_i2c); + p_i2c->dev->int_clr.rx_fifo_full=1; + p_i2c->dev->int_ena.rx_fifo_full=1; //why? + + activeInt &=~I2C_RXFIFO_FULL_INT_ST; + } + + if (activeInt & I2C_ACK_ERR_INT_ST_M) {//fatal error, abort i2c service + if (p_i2c->mode == I2C_MASTER) { + i2c_update_error_byte_cnt(p_i2c); // calc which byte caused ack Error, check if address or data + if(p_i2c->errorByteCnt < 0 ) { // address + i2cIsrExit(p_i2c,EVENT_ERROR_NAK,true); + } else { + i2cIsrExit(p_i2c,EVENT_ERROR_DATA_NAK,true); //data + } + } + return; + } + + if (activeInt & I2C_TIME_OUT_INT_ST_M) { + // let Gross timeout occur, Slave may release SCL before the configured timeout expires + // the Statemachine only has a 13.1ms max timout, some Devices >500ms + p_i2c->dev->int_clr.time_out =1; + activeInt &=~I2C_TIME_OUT_INT_ST; + // since a timeout occurred, capture the rxFifo data + emptyRxFifo(p_i2c); + p_i2c->dev->int_clr.rx_fifo_full=1; + p_i2c->dev->int_ena.rx_fifo_full=1; //why? + + } + + if (activeInt & I2C_TRANS_COMPLETE_INT_ST_M) { + p_i2c->dev->int_clr.trans_complete = 1; + i2cIsrExit(p_i2c,EVENT_DONE,false); + return; // no more work to do + /* + // how does slave mode act? + if (p_i2c->mode == I2C_SLAVE) { // STOP detected + // empty fifo + // dispatch callback + */ + } + + if (activeInt & I2C_ARBITRATION_LOST_INT_ST_M) { //fatal + i2cIsrExit(p_i2c,EVENT_ERROR_ARBITRATION,true); + return; // no more work to do + } + + if (activeInt & I2C_SLAVE_TRAN_COMP_INT_ST_M) { + p_i2c->dev->int_clr.slave_tran_comp = 1; + // need to complete this ! + } + + if (activeInt & I2C_END_DETECT_INT_ST_M) { + p_i2c->dev->int_ena.end_detect = 0; + p_i2c->dev->int_clr.end_detect = 1; + p_i2c->dev->ctr.trans_start=0; + fillCmdQueue(p_i2c,true); // enable interrupts + p_i2c->dev->ctr.trans_start=1; // go for it + activeInt&=~I2C_END_DETECT_INT_ST_M; + } + + if(activeInt) { // clear unhandled if possible? What about Disabling interrupt? + p_i2c->dev->int_clr.val = activeInt; + // disable unhandled IRQ, + p_i2c->dev->int_ena.val = p_i2c->dev->int_ena.val & (~activeInt); + } + +// activeInt = p_i2c->dev->int_status.val; // start all over if another interrupt happened +// 01AUG2018 if another interrupt happened, the OS will schedule another interrupt +// this is the source of spurious interrupts + } +} + +/* Stickbreaker added for ISR 11/2017 +functional with Silicon date=0x16042000 + */ +static i2c_err_t i2cAddQueue(i2c_t * i2c,uint8_t mode, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen,bool sendStop, bool dataOnly, EventGroupHandle_t event) +{ + // need to grab a MUTEX for exclusive Queue, + // what about if ISR is running? + + if(i2c==NULL) { + return I2C_ERROR_DEV; + } + + I2C_DATA_QUEUE_t dqx; + dqx.data = dataPtr; + dqx.length = dataLen; + dqx.position = 0; + dqx.cmdBytesNeeded = dataLen; + dqx.ctrl.val = 0; + if( dataOnly) { + /* special case to add a queue data only element. + START and devAddr will not be sent, this dq element can have a STOP. + allows multiple buffers to be used for one transaction. + sequence: normal transaction(sendStop==false), [dataonly(sendStop==false)],dataOnly(sendStop==true) + *** Currently only works with WRITE, final byte NAK an READ will cause a fail between dq buffer elements. (in progress 30JUL2018) + */ + dqx.ctrl.startCmdSent = 1; // mark as already sent + dqx.ctrl.addrCmdSent = 1; + } else { + dqx.ctrl.addrReq = ((i2cDeviceAddr&0xFC00)==0x7800)?2:1; // 10bit or 7bit address + } + dqx.ctrl.addr = i2cDeviceAddr; + dqx.ctrl.mode = mode; + dqx.ctrl.stop= sendStop; + dqx.queueEvent = event; + + if(event) { // an eventGroup exist, so, initialize it + xEventGroupClearBits(event, EVENT_MASK); // all of them + } + + if(i2c->dq!=NULL) { // expand + //log_i("expand"); + I2C_DATA_QUEUE_t* tq =(I2C_DATA_QUEUE_t*)realloc(i2c->dq,sizeof(I2C_DATA_QUEUE_t)*(i2c->queueCount +1)); + if(tq!=NULL) { // ok + i2c->dq = tq; + memmove(&i2c->dq[i2c->queueCount++],&dqx,sizeof(I2C_DATA_QUEUE_t)); + } else { // bad stuff, unable to allocate more memory! + return I2C_ERROR_MEMORY; + } + } else { // first Time + //log_i("new"); + i2c->queueCount=0; + i2c->dq =(I2C_DATA_QUEUE_t*)malloc(sizeof(I2C_DATA_QUEUE_t)); + if(i2c->dq!=NULL) { + memmove(&i2c->dq[i2c->queueCount++],&dqx,sizeof(I2C_DATA_QUEUE_t)); + } else { + return I2C_ERROR_MEMORY; + } + } + return I2C_ERROR_OK; +} + +i2c_err_t i2cAddQueueWrite(i2c_t * i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen,bool sendStop,EventGroupHandle_t event) +{ + return i2cAddQueue(i2c,0,i2cDeviceAddr,dataPtr,dataLen,sendStop,false,event); +} + +i2c_err_t i2cAddQueueRead(i2c_t * i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen,bool sendStop,EventGroupHandle_t event) +{ + //10bit read is kind of weird, first you do a 0byte Write with 10bit + // address, then a ReSTART then a 7bit Read using the the upper 7bit + + // readBit. + + // this might cause an internal register pointer problem with 10bit + // devices, But, Don't have any to test against. + // this is the Industry Standard specification. + + if((i2cDeviceAddr &0xFC00)==0x7800) { // ten bit read + i2c_err_t err = i2cAddQueue(i2c,0,i2cDeviceAddr,NULL,0,false,false,event); + if(err==I2C_ERROR_OK) { + return i2cAddQueue(i2c,1,(i2cDeviceAddr>>8),dataPtr,dataLen,sendStop,false,event); + } else { + return err; + } + } + return i2cAddQueue(i2c,1,i2cDeviceAddr,dataPtr,dataLen,sendStop,false,event); +} + +i2c_err_t i2cProcQueue(i2c_t * i2c, uint32_t *readCount, uint16_t timeOutMillis) +{ + /* do the hard stuff here + install ISR if necessary + setup EventGroup + handle bus busy? + */ + //log_e("procQueue i2c=%p",&i2c); + if(readCount){ //total reads accomplished in all queue elements + *readCount = 0; + } + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + if(i2c->debugFlags & 0xff000000) i2cTriggerDumps(i2c,(i2c->debugFlags>>24),"before ProcQueue"); + if (i2c->dev->status_reg.bus_busy) { // return error, let TwoWire() handle resetting the hardware. + /* if multi master then this if should be changed to this 03/12/2018 + if(multiMaster){// try to let the bus clear by its self + uint32_t timeOutTick = millis(); + while((i2c->dev->status_reg.bus_busy)&&(millis()-timeOutTickdev->status_reg.bus_busy){ // still busy, so die + */ + return I2C_ERROR_BUSY; + } + + I2C_MUTEX_LOCK(); + /* what about co-existence with SLAVE mode? + Should I check if a slaveMode xfer is in progress and hang + until it completes? + if i2c->stage == I2C_RUNNING or I2C_SLAVE_ACTIVE + */ + i2c->stage = I2C_DONE; // until ready + +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + for(uint16_t i=0; inum] = 0; + intBuff[i][1][i2c->num] = 0; + intBuff[i][2][i2c->num] = 0; + } + intPos[i2c->num] = 0; + fifoPos = 0; + memset(fifoBuffer,0,FIFOMAX); +#endif + // EventGroup is used to signal transmission completion from ISR + // not always reliable. Sometimes, the FreeRTOS scheduler is maxed out and refuses request + // if that happens, this call hangs until the timeout period expires, then it continues. + if(!i2c->i2c_event) { + i2c->i2c_event = xEventGroupCreate(); + } + if(i2c->i2c_event) { + xEventGroupClearBits(i2c->i2c_event, 0xFF); + } else { // failed to create EventGroup + I2C_MUTEX_UNLOCK(); + return I2C_ERROR_MEMORY; + } + + i2c_err_t reason = I2C_ERROR_OK; + i2c->mode = I2C_MASTER; + i2c->dev->ctr.trans_start=0; // Pause Machine + i2c->dev->timeout.tout = 0xFFFFF; // max 13ms + i2c->dev->int_clr.val = 0x1FFF; // kill them All! + + i2c->dev->ctr.ms_mode = 1; // master! + i2c->queuePos=0; + i2c->errorByteCnt=0; + i2c->errorQueue = 0; + uint32_t totalBytes=0; // total number of bytes to be Moved! + // convert address field to required I2C format + while(i2c->queuePos < i2c->queueCount) { // need to push these address modes upstream, to AddQueue + I2C_DATA_QUEUE_t *tdq = &i2c->dq[i2c->queuePos++]; + uint16_t taddr=0; + if(tdq->ctrl.addrReq ==2) { // 10bit address + taddr =((tdq->ctrl.addr >> 7) & 0xFE) + |tdq->ctrl.mode; + taddr = (taddr <<8) || (tdq->ctrl.addr&0xFF); + } else { // 7bit address + taddr = ((tdq->ctrl.addr<<1)&0xFE) + |tdq->ctrl.mode; + } + tdq->ctrl.addr = taddr; // all fixed with R/W bit + totalBytes += tdq->length + tdq->ctrl.addrReq; // total number of byte to be moved! + } + i2c->queuePos=0; + + fillCmdQueue(i2c,false); // don't enable Tx/RX irq's + // start adding command[], END irq will keep it full + //Data Fifo will be filled after trans_start is issued + i2c->exitCode=0; + + I2C_FIFO_CONF_t f; + f.val = i2c->dev->fifo_conf.val; + f.rx_fifo_rst = 1; // fifo in reset + f.tx_fifo_rst = 1; // fifo in reset + f.nonfifo_en = 0; // use fifo mode + f.nonfifo_tx_thres = 31; + // need to adjust threshold based on I2C clock rate, at 100k, 30 usually works, + // sometimes the emptyRx() actually moves 31 bytes + // it hasn't overflowed yet, I cannot tell if the new byte is added while + // emptyRX() is executing or before? + // let i2cSetFrequency() set thrhds + // f.rx_fifo_full_thrhd = 30; // 30 bytes before INT is issued + // f.tx_fifo_empty_thrhd = 0; + f.fifo_addr_cfg_en = 0; // no directed access + i2c->dev->fifo_conf.val = f.val; // post them all + + f.rx_fifo_rst = 0; // release fifo + f.tx_fifo_rst = 0; + i2c->dev->fifo_conf.val = f.val; // post them all + + i2c->stage = I2C_STARTUP; // everything configured, now start the I2C StateMachine, and + // As soon as interrupts are enabled, the ISR will start handling them. + // it should receive a TXFIFO_EMPTY immediately, even before it + // receives the TRANS_START + + + uint32_t interruptsEnabled = + I2C_ACK_ERR_INT_ENA | // (BIT(10)) Causes Fatal Error Exit + I2C_TRANS_START_INT_ENA | // (BIT(9)) Triggered by trans_start=1, initial,END + I2C_TIME_OUT_INT_ENA | //(BIT(8)) Trigger by SLAVE SCL stretching, NOT an ERROR + I2C_TRANS_COMPLETE_INT_ENA | // (BIT(7)) triggered by STOP, successful exit + I2C_ARBITRATION_LOST_INT_ENA | // (BIT(5)) cause fatal error exit + I2C_SLAVE_TRAN_COMP_INT_ENA | // (BIT(4)) unhandled + I2C_END_DETECT_INT_ENA | // (BIT(3)) refills cmd[] list + I2C_RXFIFO_OVF_INT_ENA | //(BIT(2)) unhandled + I2C_TXFIFO_EMPTY_INT_ENA | // (BIT(1)) triggers fillTxFifo() + I2C_RXFIFO_FULL_INT_ENA; // (BIT(0)) trigger emptyRxFifo() + + i2c->dev->int_ena.val = interruptsEnabled; + + if(!i2c->intr_handle) { // create ISR for either peripheral + // log_i("create ISR %d",i2c->num); + uint32_t ret = 0; + uint32_t flags = ESP_INTR_FLAG_IRAM | //< ISR can be called if cache is disabled + ESP_INTR_FLAG_LOWMED | //< Low and medium prio interrupts. These can be handled in C. + ESP_INTR_FLAG_SHARED; //< Reduce resource requirements, Share interrupts + + if(i2c->num) { + ret = esp_intr_alloc_intrstatus(ETS_I2C_EXT1_INTR_SOURCE, flags, (uint32_t)&i2c->dev->int_status.val, interruptsEnabled, &i2c_isr_handler_default,i2c, &i2c->intr_handle); + } else { + ret = esp_intr_alloc_intrstatus(ETS_I2C_EXT0_INTR_SOURCE, flags, (uint32_t)&i2c->dev->int_status.val, interruptsEnabled, &i2c_isr_handler_default,i2c, &i2c->intr_handle); + } + + if(ret!=ESP_OK) { + I2C_MUTEX_UNLOCK(); + return I2C_ERROR_MEMORY; + } + } + //hang until it completes. + + // how many ticks should it take to transfer totalBytes through the I2C hardware, + // add user supplied timeOutMillis to Calculated Value + + portTickType ticksTimeOut = ((totalBytes*10*1000)/(i2cGetFrequency(i2c))+timeOutMillis)/portTICK_PERIOD_MS; + + i2c->dev->ctr.trans_start=1; // go for it + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR + portTickType tBefore=xTaskGetTickCount(); +#endif + + // wait for ISR to complete the transfer, or until timeOut in case of bus fault, hardware problem + + uint32_t eBits = xEventGroupWaitBits(i2c->i2c_event,EVENT_DONE,pdFALSE,pdTRUE,ticksTimeOut); + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR + portTickType tAfter=xTaskGetTickCount(); +#endif + + + // if xEventGroupSetBitsFromISR() failed, the ISR could have succeeded but never been + // able to mark the success + + if(i2c->exitCode!=eBits) { // try to recover from O/S failure + // log_e("EventGroup Failed:%p!=%p",eBits,i2c->exitCode); + eBits=i2c->exitCode; + } + if((eBits&EVENT_ERROR)||(!(eBits & EVENT_DONE))){ // need accurate errorByteCnt for debug + i2c_update_error_byte_cnt(i2c); + } + + if(!(eBits==EVENT_DONE)&&(eBits&~(EVENT_ERROR_NAK|EVENT_ERROR_DATA_NAK|EVENT_ERROR|EVENT_DONE))) { // not only Done, therefore error, exclude ADDR NAK, DATA_NAK +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO + i2cDumpI2c(i2c); + i2cDumpInts(i2c->num); +#endif + } + + if(eBits&EVENT_DONE) { // no gross timeout + switch(i2c->error) { + case I2C_OK : + reason = I2C_ERROR_OK; + break; + case I2C_ERROR : + reason = I2C_ERROR_DEV; + break; + case I2C_ADDR_NAK: + reason = I2C_ERROR_ACK; + break; + case I2C_DATA_NAK: + reason = I2C_ERROR_ACK; + break; + case I2C_ARBITRATION: + reason = I2C_ERROR_BUS; + break; + case I2C_TIMEOUT: + reason = I2C_ERROR_TIMEOUT; + break; + default : + reason = I2C_ERROR_DEV; + } + } else { // GROSS timeout, shutdown ISR , report Timeout + i2c->stage = I2C_DONE; + i2c->dev->int_ena.val =0; + i2c->dev->int_clr.val = 0x1FFF; + i2c_update_error_byte_cnt(i2c); + if((i2c->errorByteCnt == 0)&&(i2c->errorQueue==0)) { // Bus Busy no bytes Moved + reason = I2C_ERROR_BUSY; + eBits = eBits | EVENT_ERROR_BUS_BUSY|EVENT_ERROR|EVENT_DONE; +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + //log_d(" Busy Timeout start=0x%x, end=0x%x, =%d, max=%d error=%d",tBefore,tAfter,(tAfter-tBefore),ticksTimeOut,i2c->error); + i2cDumpI2c(i2c); + i2cDumpInts(i2c->num); +#endif + } else { // just a timeout, some data made it out or in. + reason = I2C_ERROR_TIMEOUT; + eBits = eBits | EVENT_ERROR_TIMEOUT|EVENT_ERROR|EVENT_DONE; + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + //log_d(" Gross Timeout Dead start=0x%x, end=0x%x, =%d, max=%d error=%d",tBefore,tAfter,(tAfter-tBefore),ticksTimeOut,i2c->error); + i2cDumpI2c(i2c); + i2cDumpInts(i2c->num); +#endif + } + } + + /* offloading all EventGroups to dispatch, EventGroups in ISR is not always successful + 11/20/2017 + if error, need to trigger all succeeding dataQueue events with the EVENT_ERROR_PREV + 07/22/2018 + Need to use the queueEvent value to identify transaction blocks, if an error occurs, + all subsequent queue items with the same queueEvent value will receive the EVENT_ERROR_PREV. + But, ProcQue should re-queue queue items that have a different queueEvent value(different transaction) + This change will support multi-thread i2c usage. Use the queueEvent as the transaction event + identifier. + */ + uint32_t b = 0; + + while(b < i2c->queueCount) { + if(i2c->dq[b].ctrl.mode==1 && readCount) { + *readCount += i2c->dq[b].position; // number of data bytes received + } + if(b < i2c->queuePos) { // before any error + if(i2c->dq[b].queueEvent) { // this data queue element has an EventGroup + xEventGroupSetBits(i2c->dq[b].queueEvent,EVENT_DONE); + } + } else if(b == i2c->queuePos) { // last processed queue + if(i2c->dq[b].queueEvent) { // this data queue element has an EventGroup + xEventGroupSetBits(i2c->dq[b].queueEvent,eBits); + } + } else { // never processed queues + if(i2c->dq[b].queueEvent) { // this data queue element has an EventGroup + xEventGroupSetBits(i2c->dq[b].queueEvent,eBits|EVENT_ERROR_PREV); + } + } + b++; + } + if(i2c->debugFlags & 0x00ff0000) i2cTriggerDumps(i2c,(i2c->debugFlags>>16),"after ProcQueue"); + + I2C_MUTEX_UNLOCK(); + return reason; +} + +static void i2cReleaseISR(i2c_t * i2c) +{ + if(i2c->intr_handle) { + esp_intr_free(i2c->intr_handle); + i2c->intr_handle=NULL; + } +} + +static bool i2cCheckLineState(int8_t sda, int8_t scl){ + if(sda < 0 || scl < 0){ + return false;//return false since there is nothing to do + } + // if the bus is not 'clear' try the cycling SCL until SDA goes High or 9 cycles + digitalWrite(sda, HIGH); + digitalWrite(scl, HIGH); + pinMode(sda, PULLUP|OPEN_DRAIN|INPUT); + pinMode(scl, PULLUP|OPEN_DRAIN|OUTPUT); + + if(!digitalRead(sda) || !digitalRead(scl)) { // bus in busy state + //log_w("invalid state sda(%d)=%d, scl(%d)=%d", sda, digitalRead(sda), scl, digitalRead(scl)); + digitalWrite(scl, HIGH); + for(uint8_t a=0; a<9; a++) { + delayMicroseconds(5); + digitalWrite(scl, LOW); + delayMicroseconds(5); + digitalWrite(scl, HIGH); + if(digitalRead(sda)){ // bus recovered + //log_d("Recovered after %d Cycles",a+1); + break; + } + } + } + + if(!digitalRead(sda) || !digitalRead(scl)) { // bus in busy state + return false; // bus is busy + } + return true; +} + +i2c_err_t i2cAttachSCL(i2c_t * i2c, int8_t scl) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + digitalWrite(scl, HIGH); + pinMode(scl, OPEN_DRAIN | PULLUP | INPUT | OUTPUT); + pinMatrixOutAttach(scl, I2C_SCL_IDX(i2c->num), false, false); + pinMatrixInAttach(scl, I2C_SCL_IDX(i2c->num), false); + return I2C_ERROR_OK; +} + +i2c_err_t i2cDetachSCL(i2c_t * i2c, int8_t scl) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + pinMatrixOutDetach(scl, false, false); + pinMatrixInDetach(I2C_SCL_IDX(i2c->num), false, false); + pinMode(scl, INPUT | PULLUP); + return I2C_ERROR_OK; +} + +i2c_err_t i2cAttachSDA(i2c_t * i2c, int8_t sda) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + digitalWrite(sda, HIGH); + pinMode(sda, OPEN_DRAIN | PULLUP | INPUT | OUTPUT ); + pinMatrixOutAttach(sda, I2C_SDA_IDX(i2c->num), false, false); + pinMatrixInAttach(sda, I2C_SDA_IDX(i2c->num), false); + return I2C_ERROR_OK; +} + +i2c_err_t i2cDetachSDA(i2c_t * i2c, int8_t sda) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + pinMatrixOutDetach(sda, false, false); + pinMatrixInDetach(I2C_SDA_IDX(i2c->num), false, false); + pinMode(sda, INPUT | PULLUP); + return I2C_ERROR_OK; +} + +/* + * PUBLIC API + * */ +// 24Nov17 only supports Master Mode +i2c_t * i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t frequency) //before this is called, pins should be detached, else glitch +{ + //log_v("num=%d sda=%d scl=%d freq=%d",i2c_num, sda, scl, frequency); + if(i2c_num > 1) { + return NULL; + } + + i2c_t * i2c = &_i2c_bus_array[i2c_num]; + + if(i2c->sda >= 0){ + i2cDetachSDA(i2c, i2c->sda); + } + if(i2c->scl >= 0){ + i2cDetachSCL(i2c, i2c->scl); + } + i2c->sda = sda; + i2c->scl = scl; + +#if !CONFIG_DISABLE_HAL_LOCKS + if(i2c->lock == NULL) { + i2c->lock = xSemaphoreCreateMutex(); + if(i2c->lock == NULL) { + return NULL; + } + } +#endif + I2C_MUTEX_LOCK(); + + i2cReleaseISR(i2c); // ISR exists, release it before disabling hardware + + if(frequency == 0) {// don't change existing frequency + frequency = i2cGetFrequency(i2c); + if(frequency == 0) { + frequency = 100000L; // default to 100khz + } + } + + if(i2c_num == 0) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST); //reset hardware + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT0_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST);// release reset + } else { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST); //reset Hardware + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT1_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST); + } + i2c->dev->ctr.val = 0; + i2c->dev->ctr.ms_mode = 1; + i2c->dev->ctr.sda_force_out = 1 ; + i2c->dev->ctr.scl_force_out = 1 ; + i2c->dev->ctr.clk_en = 1; + + //the max clock number of receiving a data + i2c->dev->timeout.tout = 400000;//clocks max=1048575 + //disable apb nonfifo access + i2c->dev->fifo_conf.nonfifo_en = 0; + + i2c->dev->slave_addr.val = 0; + I2C_MUTEX_UNLOCK(); + + i2cSetFrequency(i2c, frequency); // reconfigure + + if(!i2cCheckLineState(i2c->sda, i2c->scl)){ + return NULL; + } + + if(i2c->sda >= 0){ + i2cAttachSDA(i2c, i2c->sda); + } + if(i2c->scl >= 0){ + i2cAttachSCL(i2c, i2c->scl); + } + return i2c; +} + +void i2cRelease(i2c_t *i2c) // release all resources, power down peripheral +{ + I2C_MUTEX_LOCK(); + + if(i2c->sda >= 0){ + i2cDetachSDA(i2c, i2c->sda); + } + if(i2c->scl >= 0){ + i2cDetachSCL(i2c, i2c->scl); + } + + i2cReleaseISR(i2c); + + if(i2c->i2c_event) { + vEventGroupDelete(i2c->i2c_event); + i2c->i2c_event = NULL; + } + + i2cFlush(i2c); + + // reset the I2C hardware and shut off the clock, power it down. + if(i2c->num == 0) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST); //reset hardware + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT0_CLK_EN); // shutdown hardware + } else { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST); //reset Hardware + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT1_CLK_EN); // shutdown Hardware + } + + I2C_MUTEX_UNLOCK(); +} + +i2c_err_t i2cFlush(i2c_t * i2c) +{ + if(i2c==NULL) { + return I2C_ERROR_DEV; + } + i2cTriggerDumps(i2c,i2c->debugFlags & 0xff, "FLUSH"); + + // need to grab a MUTEX for exclusive Queue, + // what out if ISR is running? + i2c_err_t rc=I2C_ERROR_OK; + if(i2c->dq!=NULL) { + // log_i("free"); + // what about EventHandle? + free(i2c->dq); + i2c->dq = NULL; + } + i2c->queueCount=0; + i2c->queuePos=0; + // release Mutex + return rc; +} + +i2c_err_t i2cWrite(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis){ + i2c_err_t last_error = i2cAddQueueWrite(i2c, address, buff, size, sendStop, NULL); + + if(last_error == I2C_ERROR_OK) { //queued + if(sendStop) { //now actually process the queued commands, including READs + last_error = i2cProcQueue(i2c, NULL, timeOutMillis); + if(last_error == I2C_ERROR_BUSY) { // try to clear the bus + if(i2cInit(i2c->num, i2c->sda, i2c->scl, 0)) { + last_error = i2cProcQueue(i2c, NULL, timeOutMillis); + } + } + i2cFlush(i2c); + } else { // stop not received, so wait for I2C stop, + last_error = I2C_ERROR_CONTINUE; + } + } + return last_error; +} + +i2c_err_t i2cRead(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis, uint32_t *readCount){ + i2c_err_t last_error=i2cAddQueueRead(i2c, address, buff, size, sendStop, NULL); + + if(last_error == I2C_ERROR_OK) { //queued + if(sendStop) { //now actually process the queued commands, including READs + last_error = i2cProcQueue(i2c, readCount, timeOutMillis); + if(last_error == I2C_ERROR_BUSY) { // try to clear the bus + if(i2cInit(i2c->num, i2c->sda, i2c->scl, 0)) { + last_error = i2cProcQueue(i2c, readCount, timeOutMillis); + } + } + i2cFlush(i2c); + } else { // stop not received, so wait for I2C stop, + last_error = I2C_ERROR_CONTINUE; + } + } + return last_error; +} + +i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + I2C_FIFO_CONF_t f; + + uint32_t period = (APB_CLK_FREQ/clk_speed) / 2; + uint32_t halfPeriod = period/2; + uint32_t quarterPeriod = period/4; + + I2C_MUTEX_LOCK(); + + // Adjust Fifo thresholds based on frequency + f.val = i2c->dev->fifo_conf.val; + uint32_t a = (clk_speed / 50000L )+1; + if (a > 24) a=24; + f.rx_fifo_full_thrhd = 32 - a; + f.tx_fifo_empty_thrhd = a; + i2c->dev->fifo_conf.val = f.val; // set thresholds + //log_v("Fifo threshold=%d",a); + + //the clock num during SCL is low level + i2c->dev->scl_low_period.period = period; + //the clock num during SCL is high level + i2c->dev->scl_high_period.period = period; + + //the clock num between the negedge of SDA and negedge of SCL for start mark + i2c->dev->scl_start_hold.time = halfPeriod; + //the clock num between the posedge of SCL and the negedge of SDA for restart mark + i2c->dev->scl_rstart_setup.time = halfPeriod; + + //the clock num after the STOP bit's posedge + i2c->dev->scl_stop_hold.time = halfPeriod; + //the clock num between the posedge of SCL and the posedge of SDA + i2c->dev->scl_stop_setup.time = halfPeriod; + + //the clock num I2C used to hold the data after the negedge of SCL. + i2c->dev->sda_hold.time = quarterPeriod; + //the clock num I2C used to sample data on SDA after the posedge of SCL + i2c->dev->sda_sample.time = quarterPeriod; + I2C_MUTEX_UNLOCK(); + return I2C_ERROR_OK; +} + +uint32_t i2cGetFrequency(i2c_t * i2c) +{ + if(i2c == NULL) { + return 0; + } + uint32_t result = 0; + uint32_t old_count = (i2c->dev->scl_low_period.period+i2c->dev->scl_high_period.period); + if(old_count>0) { + result = APB_CLK_FREQ / old_count; + } else { + result = 0; + } + return result; +} + + +uint32_t i2cDebug(i2c_t * i2c, uint32_t setBits, uint32_t resetBits){ + if(i2c != NULL) { + i2c->debugFlags = ((i2c->debugFlags | setBits) & ~resetBits); + return i2c->debugFlags; + } + return 0; + + } + +uint32_t i2cGetStatus(i2c_t * i2c){ + if(i2c != NULL){ + return i2c->dev->status_reg.val; + } + else return 0; +} +/* todo + 22JUL18 + need to add multi-thread capability, use dq.queueEvent as the group marker. When multiple threads + transactions are present in the same queue, and an error occurs, abort all succeeding unserviced transactions + with the same dq.queueEvent value. Succeeding unserviced transactions with different dq.queueEvent values + can be re-queued and processed independently. + 30JUL18 complete data only queue elements, this will allow transfers to use multiple data blocks, + */ + diff --git a/MCUME_esp32/esp8086/components/Wire/esp32-hal-i2c.h b/MCUME_esp32/esp8086/components/Wire/esp32-hal-i2c.h new file mode 100644 index 0000000..1a696ac --- /dev/null +++ b/MCUME_esp32/esp8086/components/Wire/esp32-hal-i2c.h @@ -0,0 +1,82 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// modified Nov 2017 by Chuck Todd to support Interrupt Driven I/O + +#ifndef _ESP32_HAL_I2C_H_ +#define _ESP32_HAL_I2C_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/event_groups.h" + +// External Wire.h equivalent error Codes +typedef enum { + I2C_ERROR_OK=0, + I2C_ERROR_DEV, + I2C_ERROR_ACK, + I2C_ERROR_TIMEOUT, + I2C_ERROR_BUS, + I2C_ERROR_BUSY, + I2C_ERROR_MEMORY, + I2C_ERROR_CONTINUE, + I2C_ERROR_NO_BEGIN +} i2c_err_t; + +struct i2c_struct_t; +typedef struct i2c_struct_t i2c_t; + +i2c_t * i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t clk_speed); +void i2cRelease(i2c_t *i2c); // free ISR, Free DQ, Power off peripheral clock. Must call i2cInit() to recover +i2c_err_t i2cWrite(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis); +i2c_err_t i2cRead(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis, uint32_t *readCount); +i2c_err_t i2cFlush(i2c_t *i2c); +i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed); +uint32_t i2cGetFrequency(i2c_t * i2c); +uint32_t i2cGetStatus(i2c_t * i2c); // Status register of peripheral + +//Functions below should be used only if well understood +//Might be deprecated and removed in future +i2c_err_t i2cAttachSCL(i2c_t * i2c, int8_t scl); +i2c_err_t i2cDetachSCL(i2c_t * i2c, int8_t scl); +i2c_err_t i2cAttachSDA(i2c_t * i2c, int8_t sda); +i2c_err_t i2cDetachSDA(i2c_t * i2c, int8_t sda); + +//Stickbreakers ISR Support +i2c_err_t i2cProcQueue(i2c_t *i2c, uint32_t *readCount, uint16_t timeOutMillis); +i2c_err_t i2cAddQueueWrite(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen, bool SendStop, EventGroupHandle_t event); +i2c_err_t i2cAddQueueRead(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen, bool SendStop, EventGroupHandle_t event); + +//stickbreaker debug support +uint32_t i2cDebug(i2c_t *, uint32_t setBits, uint32_t resetBits); +// Debug actions have 3 currently defined locus +// 0xXX------ : at entry of ProcQueue +// 0x--XX---- : at exit of ProcQueue +// 0x------XX : at entry of Flush +// +// bit 0 causes DumpI2c to execute +// bit 1 causes DumpInts to execute +// bit 2 causes DumpCmdqueue to execute +// bit 3 causes DumpStatus to execute +// bit 4 causes DumpFifo to execute + +#ifdef __cplusplus +} +#endif + +#endif /* _ESP32_HAL_I2C_H_ */ diff --git a/MCUME_esp32/esp8086/components/Wire/esp32-hal-matrix.c b/MCUME_esp32/esp8086/components/Wire/esp32-hal-matrix.c new file mode 100644 index 0000000..93e8849 --- /dev/null +++ b/MCUME_esp32/esp8086/components/Wire/esp32-hal-matrix.c @@ -0,0 +1,52 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include +#include +#include "esp32-hal-matrix.h" +#include "esp_attr.h" +#include "rom/gpio.h" + + + +#define MATRIX_DETACH_OUT_SIG 0x100 +#define MATRIX_DETACH_IN_LOW_PIN 0x30 +#define MATRIX_DETACH_IN_LOW_HIGH 0x38 + +void IRAM_ATTR pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable) +{ + gpio_matrix_out(pin, function, invertOut, invertEnable); +} + +void IRAM_ATTR pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable) +{ + gpio_matrix_out(pin, MATRIX_DETACH_OUT_SIG, invertOut, invertEnable); +} + +void IRAM_ATTR pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted) +{ + gpio_matrix_in(pin, signal, inverted); +} + +void IRAM_ATTR pinMatrixInDetach(uint8_t signal, bool high, bool inverted) +{ + gpio_matrix_in(high?MATRIX_DETACH_IN_LOW_HIGH:MATRIX_DETACH_IN_LOW_PIN, signal, inverted); +} +/* +void IRAM_ATTR intrMatrixAttach(uint32_t source, uint32_t inum){ + intr_matrix_set(PRO_CPU_NUM, source, inum); +} +*/ + diff --git a/MCUME_esp32/esp8086/components/Wire/esp32-hal-matrix.h b/MCUME_esp32/esp8086/components/Wire/esp32-hal-matrix.h new file mode 100644 index 0000000..7feefea --- /dev/null +++ b/MCUME_esp32/esp8086/components/Wire/esp32-hal-matrix.h @@ -0,0 +1,35 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP32_HAL_MATRIX_H_ +#define _ESP32_HAL_MATRIX_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + +//#include "esp32-hal.h" +//#include "soc/gpio_sig_map.h" + +void pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable); +void pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable); +void pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted); +void pinMatrixInDetach(uint8_t signal, bool high, bool inverted); + +#ifdef __cplusplus +} +#endif + +#endif /* COMPONENTS_ARDUHAL_INCLUDE_ESP32_HAL_MATRIX_H_ */ diff --git a/MCUME_esp32/esp8086/flashapp.sh b/MCUME_esp32/esp8086/flashapp.sh new file mode 100755 index 0000000..42c1834 --- /dev/null +++ b/MCUME_esp32/esp8086/flashapp.sh @@ -0,0 +1,3 @@ +#!/bin/bash +. ${IDF_PATH}/add_path.sh +esptool.py --chip esp32 --port "/dev/cu.SLAB_USBtoUART" --baud $((230400*4)) write_flash -fs 4MB 0x10000 ../esp8086/build/esp8086.bin diff --git a/MCUME_esp32/esp8086/main/.DS_Store b/MCUME_esp32/esp8086/main/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..5008ddfcf53c02e82d7eee2e57c38e5672ef89f6 GIT binary patch literal 6148 zcmeH~Jr2S!425mzP>H1@V-^m;4Wg<&0T*E43hX&L&p$$qDprKhvt+--jT7}7np#A3 zem<@ulZcFPQ@L2!n>{z**++&mCkOWA81W14cNZlEfg7;MkzE(HCqgga^y>{tEnwC%0;vJ&^%eQ zLs35+`xjp>T0> 1; + + short v0=chan[0].vol; + short v1=chan[1].vol; + short v2=chan[2].vol; + short v3=chan[3].vol; + short v4=chan[4].vol; + short v5=chan[5].vol; + for (i=0;i>8)&0x3f]) ); + s+= ( v1*(square[(chan[1].spos>>8)&0x3f]) ); + s+= ( v2*(square[(chan[2].spos>>8)&0x3f]) ); + s+= ( v3*(noise[(chan[3].spos>>8)&(NOISEBSIZE-1)]) ); + s+= ( v4*(noise[(chan[4].spos>>8)&(NOISEBSIZE-1)]) ); + s+= ( v5*(noise[(chan[5].spos>>8)&(NOISEBSIZE-1)]) ); + *stream++ = int16_t((s>>11)); + chan[0].spos += chan[0].sinc; + chan[1].spos += chan[1].sinc; + chan[2].spos += chan[2].sinc; + chan[3].spos += chan[3].sinc; + chan[4].spos += chan[4].sinc; + chan[5].spos += chan[5].sinc; + } +#endif + } +} + +#ifdef USE_I2S +#else +void IRAM_ATTR onTimer() +{ + // Sound playing code, plays whatever's in the buffer continuously. Big change from previous versions + if(LastDacValue!=Buffer[NextPlayPos]) // Send value to DAC only of changed since last value else no need + { + // value to DAC has changed, send to actual hardware, else we just leave setting as is as it's not changed + LastDacValue=Buffer[NextPlayPos]; + dacWrite(DacPin,uint8_t((LastDacValue>>8)+127)); // write out the data + } + Buffer[NextPlayPos]=0; // Reset this buffer byte back to silence + NextPlayPos++; // Move play pos to next byte in buffer + if(NextPlayPos==BufferSize) // If gone past end of buffer, + NextPlayPos=0; // set back to beginning +} + +#endif + +void AudioPlaySystem::begin(void) +{ +#ifdef USE_I2S + Buffer = (uint16_t *)malloc(DEFAULT_SAMPLESIZE*4); //16bits, L+R + uint16_t * dst=(uint16_t *)Buffer; + for (int i=0; i>1; + } +} + +void AudioPlaySystem::step(void) +{ +#ifdef USE_I2S + int left=DEFAULT_SAMPLERATE/50; + + while(left) { + int n=DEFAULT_SAMPLESIZE; + if (n>left) n=left; + snd_Mixer16((uint16_t*)Buffer, n); + //16 bit mono -> 16 bit r+l + for (int i=n-1; i>=0; i--) { + Buffer[i*2+1]=Buffer[i]+32767; + Buffer[i*2]=Buffer[i]+32767; + } + i2s_write_bytes(I2S_NUM, (const void*)Buffer, n*4, portMAX_DELAY); + left-=n; + } +#else + + int32_t CurPos=NextPlayPos; + int32_t samples; + if (CurPos > LastPlayPos) { + snd_Mixer16((uint16_t *)&Buffer[LastPlayPos], CurPos-LastPlayPos); + samples = CurPos-LastPlayPos; + } + else { + snd_Mixer16((uint16_t *)&Buffer[LastPlayPos], BufferSize-LastPlayPos); + snd_Mixer16((uint16_t *)&Buffer[0], CurPos); + samples = BufferSize-LastPlayPos; + samples += CurPos; + } + LastPlayPos = CurPos; + //printf("sam %d\n",bytes); +#endif +} +#endif + + diff --git a/MCUME_esp32/esp8086/main/AudioPlaySystem.h b/MCUME_esp32/esp8086/main/AudioPlaySystem.h new file mode 100644 index 0000000..c1e918f --- /dev/null +++ b/MCUME_esp32/esp8086/main/AudioPlaySystem.h @@ -0,0 +1,23 @@ +#ifndef audioplaysystem_h_ +#define audioplaysystem_h_ + +#define DEFAULT_SAMPLESIZE 512 // 22050/50=443 samples per 20ms +#define DEFAULT_SAMPLERATE 22050 + +class AudioPlaySystem +{ +public: +AudioPlaySystem(void) { begin(); } + void begin(void); + void setSampleParameters(float clockfreq, float samplerate); + void reset(void); + void start(void); + void stop(void); + bool isPlaying(void); + void sound(int C, int F, int V); + void buzz(int size, int val); + void step(void); +}; + + +#endif diff --git a/MCUME_esp32/esp8086/main/bmpjoy.h b/MCUME_esp32/esp8086/main/bmpjoy.h new file mode 100644 index 0000000..def4d7c --- /dev/null +++ b/MCUME_esp32/esp8086/main/bmpjoy.h @@ -0,0 +1,40 @@ +const uint16_t bmpjoy[] = { +0x001e,0x0026,0x0000,0x0000,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x0000,0x0000, +0x0000,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xf4d2,0xeaea,0xe227,0xe268,0xebce,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x0000, +0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xeaa9,0xe984,0xe164,0xd964,0xe184,0xe1a4,0xe1a5,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c, +0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xe207,0xe984,0xe206,0xe2e9,0xe267,0xd964,0xd9a5,0xd984,0xf1a5,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c, +0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xebef,0xe984,0xe288,0xeb8b,0xeb0a,0xe247,0xd984,0xd984,0xd9a5,0xe1a5,0xe1c6,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c, 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+0x0000,0x0000,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x0000,0x0000}; + diff --git a/MCUME_esp32/esp8086/main/bmpvbar.h b/MCUME_esp32/esp8086/main/bmpvbar.h new file mode 100644 index 0000000..22dd775 --- /dev/null +++ b/MCUME_esp32/esp8086/main/bmpvbar.h @@ -0,0 +1,151 @@ +const uint16_t bmpvbar[] = { +0x0020,0x0094, +0x0000,0x0000,0x0000,0xad96,0xdf3d,0xd6fc,0xd6fc,0xd6fd,0xd6fd,0xd71d,0xdf1d,0xd71d,0xd71c,0xd71d,0xd71d,0xd71d,0xd71d,0xd71d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf3d,0xbe18,0x0000,0x0000,0x0000,0x0861, +0x0000,0x0000,0xbe39,0xcedc,0xb63b,0xadfa,0xadfb,0xadfb,0xadfb,0xadfb,0xae1b,0xae1b,0xae1b,0xae1b,0xae1b,0xae1b,0xae3b,0xae3b,0xae3b,0xae3b,0xb63b,0xb63b,0xb63c,0xb63c,0xb65c,0xb65c,0xb65c,0xc69c,0xd71d,0x5b0c,0x0000,0x0861, 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By default, it will take the sources in the +# src/ directory, compile them and link them into lib(subdirectory_name).a +# in the build directory. This behaviour is entirely configurable, +# please read the ESP-IDF documents if you need to do this. +# + +CPPFLAGS += -Wno-error=parentheses -Wno-error=maybe-uninitialized #-DEMULATED_JOYSTICK -DUSE_SHORT_SLICE -DUSE_DOUBLE_BUFFER -DNO_SOUND -fno-common -fno-builtin -fno-exceptions -fstrict-aliasing -Wno-narrowing -Wno-error=unused-value -Wno-error=return-type -Wno-error=sequence-point -Wno-error=implicit-int -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=implicit-function-declaration -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-error=char-subscripts -Wno-error=attributes +#-Werror=maybe-uninitialized diff --git a/MCUME_esp32/esp8086/main/cpu.cpp b/MCUME_esp32/esp8086/main/cpu.cpp new file mode 100755 index 0000000..739588f --- /dev/null +++ b/MCUME_esp32/esp8086/main/cpu.cpp @@ -0,0 +1,2264 @@ +#include +#include +//#include +//#include +#include "emu.h" +#include "rom.h" + +extern void portout(uint16_t portnum, uint16_t value); +extern uint16_t portin(uint16_t portnum); + +extern void readdisk(uint8_t drivenum, uint16_t dstseg, uint16_t dstoff, uint16_t cyl, uint16_t sect, uint16_t head, uint16_t sectcount); +extern void insertdisk(); + +extern void doirq(uint8_t irqnum); +extern uint8_t nextintr(); +extern struct structpic { + uint8_t imr; //mask register + uint8_t irr; //request register + uint8_t isr; //service register + uint8_t icwstep; //used during initialization to keep track of which ICW we're at + uint8_t icw[5]; + uint8_t intoffset; //interrupt vector offset + uint8_t priority; //which IRQ has highest priority + uint8_t autoeoi; //automatic EOI mode + uint8_t readmode; //remember what to return on read register from OCW3 + uint8_t enabled; +} i8259; + +extern uint8_t curkey; +void intcall86(uint8_t intnum); + +uint64_t curtimer, lasttimer, timerfreq; + +char *biosfile = NULL; +uint8_t byteregtable[8] = { regal, regcl, regdl, regbl, regah, regch, regdh, regbh }; + +uint8_t parity[0x100]; + +_bytewordregs_ regs; + +uint16_t segregs[6]; +uint8_t opcode, segoverride, reptype, bootdrive, hdcount = 0; +uint16_t savecs, saveip, ip, useseg, oldsp; +uint8_t tempcf, oldcf, cf, pf, af, zf, sf, tf, ifl, df, of, nt, iopriv, mode, reg, rm, msw = 0; +uint16_t oper1, oper2, res16, disp16, temp16, dummy, stacksize, frametemp; +uint8_t oper1b, oper2b, res8, disp8, temp8, nestlev, addrbyte; +uint16_t cr0 = 0, cr1 = 0, cr2 = 0, cr3 = 0; +uint32_t ldtr = 0, gdtr = 0, gdtlimit = 0, idtr = 0, idtlimit = 0; +uint32_t temp1, temp2, temp3, temp4, temp5, temp32, tempaddr32, ea; +int32_t result, speed = 0; +uint32_t totalexec; +uint32_t ips[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +uint16_t *tempwordptr; + +uint8_t vidmode, cgabg, blankattr, vidgfxmode, vidcolor; +uint16_t cursx, cursy, cols, rows, vgapage, cursorposition, cursorvisible; +uint8_t updatedscreen, port3da, port6, portout16; +//uint16_t VGA_SC[0xFF], VGA_CRTC[0xFF], VGA_ATTR[0xFF], VGA_GC[0xFF]; +uint32_t videobase, textbase, x, y; + +uint8_t debugmode, showcsip, verbose, mouseemu; + + +extern uint8_t * RAM; +extern uint8_t * LORAM; //LORAM[]; + +void write86(uint32_t addr32, uint8_t value) { + if (addr32 < NATIVE_RAM) { + LORAM[addr32] = value; + return; + } + else if (addr32 < RAM_SIZE) { + RAM[addr32] = value; + return; + } + else if ((addr32 >= 0xB8000) && (addr32 < 0xC0000)) { + VRAM_write(addr32 - 0xB8000UL, value); + } +} + +#define writew86(addr32,value) {write86((addr32),(uint8_t)(value));write86((addr32)+1,(uint8_t)((uint16_t)(value)>>8));} + +uint8_t read86(uint32_t addr32) { + if (addr32 < NATIVE_RAM) { + switch (addr32) { //some hardcoded values for the BIOS data area + case 0x410: //0040:0010 is the equipment word +#ifdef VGA + return (0x41); //video type (0x41 is VGA/EGA, 0x61 is CGA, 0x31 = MDA) +#else + return (0x61); //video type (0x41 is VGA/EGA, 0x61 is CGA, 0x31 = MDA) +#endif + case 0x475: //hard drive count + return (hdcount); + default: + return LORAM[addr32]; + } + } + else if (addr32 < RAM_SIZE) { + return RAM[addr32]; + } + else if ((addr32 >= 0xB8000) && (addr32 < 0xC0000)) { + addr32 -= 0xB8000UL; + return VRAM_read(addr32); + } + else if (addr32 >= 0xFE000UL) { + addr32 -= 0xFE000UL; + return ROM_READ(BIOS, addr32); //BIOS[addr32]; + } + else if ((addr32 >= 0xD0000) && (addr32 < 0xD0640)) { + return net_read_ram(addr32 - 0xD0000); + } + else if ((addr32 >= 0xE0000) && (addr32 < 0xE0006)) { + return net_mac[addr32 - 0xE0000]; + } +#ifdef INCLUDE_ROM_BASIC + else if ((addr32 >= 0xF6000UL) && (addr32 < 0xFA000UL)) { + addr32 -= 0xF6000UL; + return ROM_READ(BASICL, addr32); //BASICL[addr32]; + } else if ((addr32 >= 0xFA000UL) && (addr32 < 0xFE000UL)) { + addr32 -= 0xFA000UL; + return ROM_READ(BASICH, addr32); //BASICH[addr32]; + } +#endif + else return 0; +} + + + +#define readw86(addr32) ((uint16_t)read86((addr32))|((uint16_t)read86((addr32)+1)<<8)) + +//inline void flag_szp8(uint8_t value) { +#define flag_szp8(value) {\ + if (!(value)) zf = 1; else zf = 0;\ + if ((value) & 0x80) sf = 1; else sf = 0;\ + pf = parity[value];\ +} + +//inline void flag_szp16(uint16_t value) { +#define flag_szp16(value) {\ + if (!(value)) zf = 1; else zf = 0;\ + if (value & 0x8000) sf = 1; else sf = 0;\ + pf = parity[(uint8_t)value];\ +} + +//inline void flag_log8(uint8_t value) { +#define flag_log8(value) {\ + flag_szp8(value);\ + cf = 0; of = 0;\ +} + +//inline void flag_log16(uint16_t value) { +#define flag_log16(value) {\ + flag_szp16(value);\ + cf = 0; of = 0;\ +} + +//inline void flag_adc8(uint8_t v1, uint8_t v2, uint8_t v3) { //v1 = destination operand, v2 = source operand, v3 = carry flag +#define flag_adc8(v1, v2, v3) {\ + uint16_t dst;\ + dst = (uint16_t)(v1) + (uint16_t)(v2) + (uint16_t)(v3);\ + flag_szp8((uint8_t)dst);\ + if (((dst ^ (v1)) & (dst ^ (v2)) & 0x80) == 0x80) of = 1; else of = 0;\ + if (dst & 0xFF00) cf = 1; else cf = 0;\ + if ((((v1) ^ (v2) ^ dst) & 0x10) == 0x10) af = 1; else af = 0;\ +} + +//inline void flag_adc16(uint16_t v1, uint16_t v2, uint16_t v3) { //v1 = destination operand, v2 = source operand, v3 = carry flag +#define flag_adc16(v1, v2, v3) {\ + uint32_t dst;\ + dst = (uint32_t)(v1) + (uint32_t)(v2) + (uint32_t)(v3);\ + flag_szp16((uint16_t)dst);\ + if ((((dst ^ (v1)) & (dst ^ (v2))) & 0x8000) == 0x8000) of = 1; else of = 0;\ + if (dst & 0xFFFF0000UL) cf = 1; else cf = 0;\ + if ((((v1) ^ (v2) ^ dst) & 0x10) == 0x10) af = 1; else af = 0;\ +} + +//inline void flag_add8(uint8_t v1, uint8_t v2) { //v1 = destination operand, v2 = source operand +#define flag_add8(v1, v2) {\ + uint16_t dst;\ + dst = (uint16_t)(v1) + (uint16_t)(v2);\ + flag_szp8((uint8_t)dst);\ + if (dst & 0xFF00) cf = 1; else cf = 0;\ + if (((dst ^ (v1)) & (dst ^ (v2)) & 0x80) == 0x80) of = 1; else of = 0;\ + if ((((v1) ^ (v2) ^ dst) & 0x10) == 0x10) af = 1; else af = 0;\ +} + +//inline void flag_add16(uint16_t v1, uint16_t v2) { //v1 = destination operand, v2 = source operand +#define flag_add16(v1, v2) {\ + uint32_t dst;\ + dst = (uint32_t)(v1) + (uint32_t)(v2);\ + flag_szp16((uint16_t)dst);\ + if (dst & 0xFFFF0000UL) cf = 1; else cf = 0;\ + if (((dst ^ (v1)) & (dst ^ (v2)) & 0x8000) == 0x8000) of = 1; else of = 0;\ + if ((((v1) ^ (v2) ^ dst) & 0x10) == 0x10) af = 1; else af = 0;\ +} + +//inline void flag_sbb8(uint8_t v1, uint8_t v2, uint8_t v3) { //v1 = destination operand, v2 = source operand, v3 = carry flag +#define flag_sbb8(v1, v2, v3) {\ + uint16_t dst;\ + uint16_t newv2;\ + newv2 = (uint16_t)(v2) + (uint16_t)(v3);\ + dst = (uint16_t)(v1) - (uint16_t)newv2;\ + flag_szp8((uint8_t)dst);\ + if (dst & 0xFF00) cf = 1; else cf = 0;\ + if ((dst ^ (v1)) & ((v1) ^ newv2) & 0x80) of = 1; else of = 0;\ + if (((v1) ^ newv2 ^ dst) & 0x10) af = 1; else af = 0;\ +} + +//inline void flag_sbb16(uint16_t v1, uint16_t v2, uint16_t v3) { //v1 = destination operand, v2 = source operand, v3 = carry flag +#define flag_sbb16(v1, v2, v3){\ + uint32_t dst;\ + uint32_t newv2;\ + newv2 = (uint32_t)(v2) + (uint32_t)(v3);\ + dst = (uint32_t)v1 - newv2;\ + flag_szp16((uint16_t)dst);\ + if (dst & 0xFFFF0000UL) cf = 1; else cf = 0;\ + if ((dst ^ (v1)) & (v1 ^ newv2) & 0x8000) of = 1; else of = 0;\ + if (((v1) ^ newv2 ^ dst) & 0x10) af = 1; else af = 0;\ +} + +//inline void flag_sub8(uint8_t v1, uint8_t v2) { //v1 = destination operand, v2 = source operand +#define flag_sub8(v1, v2) {\ + uint16_t dst;\ + dst = (uint16_t)(v1) - (uint16_t)(v2);\ + flag_szp8((uint8_t)dst);\ + if (dst & 0xFF00) cf = 1; else cf = 0;\ + if ((dst ^ (v1)) & ((v1) ^ (v2)) & 0x80) of = 1; else of = 0;\ + if (((v1) ^ (v2) ^ dst) & 0x10) af = 1; else af = 0;\ +} + +//inline void flag_sub16(uint16_t v1, uint16_t v2) { //v1 = destination operand, v2 = source operand +#define flag_sub16(v1, v2) {\ + uint32_t dst;\ + dst = (uint32_t)(v1) - (uint32_t)(v2);\ + flag_szp16((uint16_t)dst);\ + if (dst & 0xFFFF0000UL) cf = 1; else cf = 0;\ + if ((dst ^ (v1)) & ((v1) ^ (v2)) & 0x8000) of = 1; else of = 0;\ + if (((v1) ^ (v2) ^ dst) & 0x10) af = 1; else af = 0;\ +} + +//inline void op_adc8() { +#define op_adc8() {\ + res8 = oper1b + oper2b + cf;\ + flag_adc8(oper1b, oper2b, cf);\ +} + +//inline void op_adc16() { +#define op_adc16() {\ + res16 = oper1 + oper2 + cf;\ + flag_adc16(oper1, oper2, cf);\ +} + +//inline void op_add8() { +#define op_add8() {\ + res8 = oper1b + oper2b;\ + flag_add8(oper1b, oper2b);\ +} + +//inline void op_add16() { +#define op_add16() {\ + res16 = oper1 + oper2;\ + flag_add16(oper1, oper2);\ +} + +//inline void op_and8() { +#define op_and8() {\ + res8 = oper1b & oper2b;\ + flag_log8(res8);\ +} + +//inline void op_and16() { +#define op_and16() {\ + res16 = oper1 & oper2;\ + flag_log16(res16);\ +} + +//inline void op_or8() { +#define op_or8() {\ + res8 = oper1b | oper2b;\ + flag_log8(res8);\ +} + +//inline void op_or16() { +#define op_or16() {\ + res16 = oper1 | oper2;\ + flag_log16(res16);\ +} + +//inline void op_xor8() { +#define op_xor8() {\ + res8 = oper1b ^ oper2b;\ + flag_log8(res8);\ +} + +//inline void op_xor16() { +#define op_xor16() {\ + res16 = oper1 ^ oper2;\ + flag_log16(res16);\ +} + +//inline void op_sub8() { +#define op_sub8() {\ + res8 = oper1b - oper2b;\ + flag_sub8(oper1b, oper2b);\ +} + +//inline void op_sub16() { +#define op_sub16() {\ + res16 = oper1 - oper2;\ + flag_sub16(oper1, oper2);\ +} + +//inline void op_sbb8() { +#define op_sbb8() {\ + res8 = oper1b - (oper2b + cf);\ + flag_sbb8(oper1b, oper2b, cf);\ +} + +//inline void op_sbb16() { +#define op_sbb16() {\ + res16 = oper1 - (oper2 + cf);\ + flag_sbb16(oper1, oper2, cf);\ +} + +//inline void modregrm() { +#define modregrm() {\ + addrbyte = getmem8(segregs[regcs], ip); StepIP(1);\ + mode = addrbyte >> 6;\ + reg = (addrbyte >> 3) & 7;\ + rm = addrbyte & 7;\ + switch (mode) {\ + case 0:\ + if (rm == 6) {\ + disp16 = getmem16(segregs[regcs], ip);\ + StepIP(2);\ + }\ + if (((rm == 2) || (rm == 3)) && !segoverride) useseg = segregs[regss]; break;\ + case 1:\ + disp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1);\ + if (((rm == 2) || (rm == 3) || (rm == 6)) && !segoverride) useseg = segregs[regss]; break;\ + case 2:\ + disp16 = getmem16(segregs[regcs], ip); StepIP(2);\ + if (((rm == 2) || (rm == 3) || (rm == 6)) && !segoverride) useseg = segregs[regss]; break;\ + default:\ + disp8 = 0; disp16 = 0;\ + }\ + if (mode < 3) getea(rm);\ +} + +//inline void getea(uint8_t rmval) { +#define getea(rmval) {\ + uint32_t tempea;\ + tempea = 0;\ + switch (mode) {\ + case 0:\ + switch (rmval) {\ + case 0: tempea = regs.wordregs[regbx] + regs.wordregs[regsi]; break;\ + case 1: tempea = regs.wordregs[regbx] + regs.wordregs[regdi]; break;\ + case 2: tempea = regs.wordregs[regbp] + regs.wordregs[regsi]; break;\ + case 3: tempea = regs.wordregs[regbp] + regs.wordregs[regdi]; break;\ + case 4: tempea = regs.wordregs[regsi]; break;\ + case 5: tempea = regs.wordregs[regdi]; break;\ + case 6: tempea = disp16; break;\ + case 7: tempea = regs.wordregs[regbx]; break;\ + } break;\ + case 1: case 2:\ + switch (rmval) {\ + case 0: tempea = regs.wordregs[regbx] + regs.wordregs[regsi] + disp16; break;\ + case 1: tempea = regs.wordregs[regbx] + regs.wordregs[regdi] + disp16; break;\ + case 2: tempea = regs.wordregs[regbp] + regs.wordregs[regsi] + disp16; break;\ + case 3: tempea = regs.wordregs[regbp] + regs.wordregs[regdi] + disp16; break;\ + case 4: tempea = regs.wordregs[regsi] + disp16; break;\ + case 5: tempea = regs.wordregs[regdi] + disp16; break;\ + case 6: tempea = regs.wordregs[regbp] + disp16; break;\ + case 7: tempea = regs.wordregs[regbx] + disp16; break;\ + } break;\ + }\ + ea = useseg;\ + ea <<= 4;\ + ea += (tempea & 0xFFFF);\ +} + +inline void push(uint16_t pushval) { + putreg16(regsp, getreg16(regsp) - 2); + //printf(" %04X:%04X PUSH\n", segregs[regss], getreg16(regsp)); + putmem16(segregs[regss], getreg16(regsp), pushval); +} + +inline uint16_t pop() { + uint16_t tempval; + //printf(" %04X:%04X POP\n", segregs[regss], getreg16(regsp)); + tempval = getmem16(segregs[regss], getreg16(regsp)); + putreg16(regsp, getreg16(regsp) + 2); + return (tempval); +} + +void reset86() { + uint16_t i, cnt, bitcount; + segregs[regcs] = 0xFFFF; + ip = 0x0000; + segregs[regss] = 0x0000; + regs.wordregs[regsp] = 0xFFFE; + + //generate parity lookup table + for (i = 0; i < 256; i++) { + bitcount = 0; + for (cnt = 0; cnt < 8; cnt++) + bitcount += ((i >> cnt) & 1); + if (bitcount & 1) parity[i] = 0; else parity[i] = 1; + } +} + +/*inline uint16_t readrm16(uint8_t rmval) { + if (mode < 3) { + getea(rmval); + return (read86(ea) | ((uint16_t)read86(ea + 1) << 8)); + } else { + return (getreg16(rmval)); + } +}*/ + +#define readrm16(rmval) ( (mode < 3) ? (read86(ea) | ((uint16_t)read86(ea + 1) << 8)) : (getreg16(rmval)) ) + +/*inline uint8_t readrm8(uint8_t rmval) { + if (mode < 3) { + //getea(rmval); + return (read86(ea)); + } else { + return (getreg8(rmval)); + } +}*/ + +#define readrm8(rmval) ( (mode < 3) ? read86(ea) : getreg8(rmval) ) + +inline void writerm16(uint8_t rmval, uint16_t value) { +//#define writerm16(rmval, value) { + if (mode < 3) {\ + /*getea(rmval);*/\ + write86(ea, value & 0xFF);\ + write86(ea + 1, value >> 8);\ + } else {\ + putreg16(rmval, value);\ + }\ +} + +inline void writerm8(uint8_t rmval, uint8_t value) { +//#define writerm8(rmval, value) { + if (mode < 3) {\ + /*getea(rmval);*/\ + write86(ea, value);\ + } else {\ + putreg8(rmval, value);\ + }\ +} + +inline uint8_t op_grp2_8(uint8_t cnt) { + uint16_t s, oldcf, msb; + uint8_t shift; + s = oper1b; + oldcf = cf; + switch (reg) { + case 0: //ROL r/m8 + for (shift = 1; shift <= cnt; shift++) { + if (s & 0x80) cf = 1; else cf = 0; + s = s << 1; + s = s | cf; + } + if (cnt == 1) of = cf ^ ((s >> 7) & 1); + break; + + case 1: //ROR r/m8 + for (shift = 1; shift <= cnt; shift++) { + cf = s & 1; + s = (s >> 1) | (cf << 7); + } + if (cnt == 1) of = (s >> 7) ^ ((s >> 6) & 1); + break; + + case 2: //RCL r/m8 + for (shift = 1; shift <= cnt; shift++) { + oldcf = cf; + if (s & 0x80) cf = 1; else cf = 0; + s = s << 1; + s = s | oldcf; + } + if (cnt == 1) of = cf ^ ((s >> 7) & 1); + break; + + case 3: //RCR r/m8 + for (shift = 1; shift <= cnt; shift++) { + oldcf = cf; + cf = s & 1; + s = (s >> 1) | (oldcf << 7); + } + if (cnt == 1) of = (s >> 7) ^ ((s >> 6) & 1); + break; + + case 4: case 6: //SHL r/m8 + for (shift = 1; shift <= cnt; shift++) { + if (s & 0x80) cf = 1; else cf = 0; + s = (s << 1) & 0xFF; + } + if ((cnt == 1) && (cf == (s >> 7))) of = 0; else of = 1; + flag_szp8((uint8_t)s); break; + + case 5: //SHR r/m8 + if ((cnt == 1) && (s & 0x80)) of = 1; else of = 0; + for (shift = 1; shift <= cnt; shift++) { + cf = s & 1; + s = s >> 1; + } + flag_szp8((uint8_t)s); break; + + case 7: //SAR r/m8 + for (shift = 1; shift <= cnt; shift++) { + msb = s & 0x80; + cf = s & 1; + s = (s >> 1) | msb; + } + of = 0; + flag_szp8((uint8_t)s); break; + + } + return (s & 0xFF); +} + +inline uint16_t op_grp2_16(uint8_t cnt) { + uint32_t s, oldcf, msb; + uint8_t shift; + s = oper1; + oldcf = cf; + switch (reg) { + case 0: //ROL r/m8 + for (shift = 1; shift <= cnt; shift++) { + if (s & 0x8000) cf = 1; else cf = 0; + s = s << 1; + s = s | cf; + } + if (cnt == 1) of = cf ^ ((s >> 15) & 1); + break; + + case 1: //ROR r/m8 + for (shift = 1; shift <= cnt; shift++) { + cf = s & 1; + s = (s >> 1) | (cf << 15); + } + if (cnt == 1) of = (s >> 15) ^ ((s >> 14) & 1); + break; + + case 2: //RCL r/m8 + for (shift = 1; shift <= cnt; shift++) { + oldcf = cf; + if (s & 0x8000) cf = 1; else cf = 0; + s = s << 1; + s = s | oldcf; + } + if (cnt == 1) of = cf ^ ((s >> 15) & 1); + break; + + case 3: //RCR r/m8 + for (shift = 1; shift <= cnt; shift++) { + oldcf = cf; + cf = s & 1; + s = (s >> 1) | (oldcf << 15); + } + if (cnt == 1) of = (s >> 15) ^ ((s >> 14) & 1); + break; + + case 4: case 6: //SHL r/m8 + for (shift = 1; shift <= cnt; shift++) { + if (s & 0x8000) cf = 1; else cf = 0; + s = (uint16_t)(s << 1); + } + if ((cnt == 1) && (cf == (s >> 15))) of = 0; else of = 1; + flag_szp16((uint16_t)s); break; + + case 5: //SHR r/m8 + if ((cnt == 1) && (s & 0x8000)) of = 1; else of = 0; + for (shift = 1; shift <= cnt; shift++) { + cf = s & 1; + s = s >> 1; + } + flag_szp16((uint16_t)s); break; + + case 7: //SAR r/m8 + for (shift = 1; shift <= cnt; shift++) { + msb = s & 0x8000; + cf = s & 1; + s = (s >> 1) | msb; + } + of = 0; + flag_szp16((uint16_t)s); break; + + } + return ((uint16_t)s); +} + +inline void op_div8(uint16_t valdiv, uint8_t divisor) { + if (divisor == 0) { + intcall86(0); + return; + } + if ((valdiv / (uint16_t)divisor) > 0xFF) { + intcall86(0); + return; + } + regs.byteregs[regah] = valdiv % (uint16_t)divisor; + regs.byteregs[regal] = valdiv / (uint16_t)divisor; +} + +inline void op_idiv8(uint16_t valdiv, uint8_t divisor) { + uint16_t s1, s2, d1, d2, sign; + if (divisor == 0) { + intcall86(0); + return; + } + s1 = valdiv; + s2 = divisor; + sign = (((s1 ^ s2) & 0x8000) != 0); + s1 = (s1 < 0x8000) ? s1 : (uint16_t)(~s1 + 1); + s2 = (s2 < 0x8000) ? s2 : (uint16_t)(~s2 + 1); + d1 = s1 / s2; + d2 = s1 % s2; + if (d1 & 0xFF00) { + intcall86(0); + return; + } + if (sign) { + d1 = (~d1 + 1) & 0xff; + d2 = (~d2 + 1) & 0xff; + } + regs.byteregs[regah] = d2; + regs.byteregs[regal] = d1; +} + +inline void op_grp3_8() { + oper1 = signext(oper1b); oper2 = signext(oper2b); + switch (reg) { + case 0: case 1: //TEST + flag_log8(oper1b & getmem8(segregs[regcs], ip)); StepIP(1); + break; + + case 2: //NOT + res8 = ~oper1b; break; + + case 3: //NEG + res8 = (~oper1b) + 1; + flag_sub8(0, oper1b); + if (res8 == 0) cf = 0; else cf = 1; + break; + + case 4: //MUL + temp1 = (uint32_t)oper1b * (uint32_t)regs.byteregs[regal]; + putreg16(regax, (uint16_t)temp1); + flag_szp8((uint8_t)temp1); + if (regs.byteregs[regah]) { + cf = 1; + of = 1; + } else { + cf = 0; + of = 0; + } + break; + + case 5: //IMUL + oper1 = signext(oper1b); + temp1 = signext(regs.byteregs[regal]); + temp2 = oper1; + if ((temp1 & 0x80) == 0x80) temp1 = temp1 | 0xFFFFFF00UL; + if ((temp2 & 0x80) == 0x80) temp2 = temp2 | 0xFFFFFF00UL; + temp3 = (uint16_t)(temp1 * temp2); + putreg16(regax, (uint16_t)temp3); + if (regs.byteregs[regah]) { + cf = 1; + of = 1; + } else { + cf = 0; + of = 0; + } + break; + + case 6: //DIV + op_div8(getreg16(regax), oper1b); + break; + + case 7: //IDIV + op_idiv8(getreg16(regax), oper1b); + break; + } +} + +void op_div16(uint32_t valdiv, uint16_t divisor) { + if (divisor == 0) { + intcall86(0); + return; + } + if ((valdiv / (uint32_t)divisor) > 0xFFFF) { + intcall86(0); + return; + } + putreg16(regdx, valdiv % (uint32_t)divisor); + putreg16(regax, valdiv / (uint32_t)divisor); +} + +void op_idiv16(uint32_t valdiv, uint16_t divisor) { + uint32_t d1, d2, s1, s2, sign; + if (divisor == 0) { + intcall86(0); + return; + } + s1 = valdiv; + s2 = divisor; + s2 = (s2 & 0x8000) ? (s2 | 0xffff0000UL) : s2; + sign = (((s1 ^ s2) & 0x80000000UL) != 0); + s1 = (s1 < 0x80000000UL) ? s1 : ((~s1 + 1) & 0xffffffffUL); + s2 = (s2 < 0x80000000UL) ? s2 : ((~s2 + 1) & 0xffffffffUL); + d1 = s1 / s2; + d2 = s1 % s2; + if (d1 & 0xFFFF0000UL) { + intcall86(0); + return; + } + if (sign) { + d1 = (uint16_t)(~d1 + 1); + d2 = (uint16_t)(~d2 + 1); + } + putreg16(regax, d1); + putreg16(regdx, d2); +} + +inline void op_grp3_16() { + switch (reg) { + case 0: case 1: //TEST + flag_log16(oper1 & getmem16(segregs[regcs], ip)); StepIP(2); break; + case 2: //NOT + res16 = ~oper1; break; + case 3: //NEG + res16 = (~oper1) + 1; + flag_sub16(0, oper1); + if (res16) cf = 1; else cf = 0; + break; + case 4: //MUL + temp1 = (uint32_t)oper1 * (uint32_t)getreg16(regax); + putreg16(regax, (uint16_t)temp1); + putreg16(regdx, temp1 >> 16); + flag_szp16((uint16_t)temp1); + if (getreg16(regdx)) { + cf = 1; + of = 1; + } else { + cf = 0; + of = 0; + } + break; + case 5: //IMUL + temp1 = getreg16(regax); + temp2 = oper1; + if (temp1 & 0x8000) temp1 |= 0xFFFF0000UL; + if (temp2 & 0x8000) temp2 |= 0xFFFF0000UL; + temp3 = temp1 * temp2; + putreg16(regax, (uint16_t)temp3); //into register ax + putreg16(regdx, temp3 >> 16); //into register dx + if (getreg16(regdx)) { + cf = 1; + of = 1; + } else { + cf = 0; + of = 0; + } + break; + case 6: //DIV + op_div16(((uint32_t)getreg16(regdx) << 16) + (uint32_t)getreg16(regax), oper1); break; + case 7: //DIV + op_idiv16(((uint32_t)getreg16(regdx) << 16) + (uint32_t)getreg16(regax), oper1); break; + } +} + +//inline void op_grp5() { +#define op_grp5() {\ + switch (reg) {\ + case 0: /*INC Ev*/\ + oper2 = 1;\ + tempcf = cf;\ + op_add16();\ + cf = tempcf;\ + writerm16(rm, res16); break;\ + case 1: /*DEC Ev*/\ + oper2 = 1;\ + tempcf = cf;\ + op_sub16();\ + cf = tempcf;\ + writerm16(rm, res16); break;\ + case 2: /*CALL Ev*/\ + push(ip);\ + ip = oper1; break;\ + case 3: /*CALL Mp*/\ + push(segregs[regcs]); push(ip);\ + /*getea(rm);*/\ + ip = (uint16_t)read86(ea) + ((uint16_t)read86(ea + 1) << 8);\ + segregs[regcs] = (uint16_t)read86(ea + 2) + ((uint16_t)read86(ea + 3) << 8); break;\ + case 4: /*JMP Ev*/\ + ip = oper1; break;\ + case 5: /*JMP Mp*/\ + /*getea(rm);*/\ + ip = (uint16_t)read86(ea) + ((uint16_t)read86(ea + 1) << 8);\ + segregs[regcs] = (uint16_t)read86(ea + 2) + ((uint16_t)read86(ea + 3) << 8); break;\ + case 6: /*PUSH Ev*/\ + push(oper1); break;\ + }\ +} + +uint8_t didintr = 0; + +void intcall86(uint8_t intnum) { + didintr = 1; + + switch (intnum) { + case 0x10: //video services + if (regs.byteregs[regah] == 0) { //video mode set +#ifdef ADVANCED_CLIENT + Serial.write(0xFF); + Serial.write(0x02); + Serial.write(regs.byteregs[regal]); + Serial.write(regs.byteregs[regal]); //duplicate for checksum + Serial.write(0xFE); + Serial.write(0x02); +#endif +#ifdef USE_DISPLAY + if (vidmode != regs.byteregs[regal]) clear_display(); + palettereset(); +#endif + vidmode = regs.byteregs[regal]; + //Serial.print("vidmode = "); Serial.println(vidmode); + } + break; + case 0x13: //disk services + diskhandler(); + return; + case 0x19: //bootstrap + //Serial.println("Bootstrap!"); + if (bootdrive < 255) { //read first sector of boot drive into 07C0:0000 and execute it + regs.byteregs[regdl] = bootdrive; + readdisk((bootdrive & 0x80) ? bootdrive - 126 : bootdrive, 0x07C0, 0x0000, 0, 1, 0, 1); + segregs[regcs] = 0x0000; ip = 0x7C00; + } else { + segregs[regcs] = 0xF600; //start ROM BASIC at bootstrap if requested + ip = 0x0000; + } + return; + case 0xFC: + net_handler(); + return; + default: + break; + } + + push(makeflagsword()); + push(segregs[regcs]); + push(ip); + segregs[regcs] = getmem16(0, ((uint16_t)intnum << 2) + 2); + ip = getmem16(0, (uint16_t)intnum << 2); + ifl = 0; + tf = 0; +} + +uint64_t frametimer = 0, didwhen = 0, didticks = 0; +uint32_t makeupticks = 0; +extern float timercomp; +uint64_t timerticks = 0, realticks = 0; +uint64_t lastcountertimer = 0, counterticks = 10000; + +#ifdef PROFILING +uint32_t startmicros, endmicros; +uint32_t instrtime[0x100]; +#endif + +#ifdef PS2_KEYBOARD +extern uint8_t kbloop; +#endif + +extern volatile uint8_t timerTick; + +void exec86(uint32_t execloops) { + uint32_t loopcount; + uint8_t docontinue; + static uint16_t firstip, trap_toggle = 0; + + for (loopcount = 0; loopcount < execloops; loopcount++) { + /*Serial.print(segregs[regcs], HEX); + Serial.write(':'); + Serial.println(ip, HEX);*/ + #ifdef PS2_KEYBOARD + if (kbloop) { + uint32_t msnow; + msnow = micros(); + while ((micros() - msnow) < 20000) { } + kbloop = 0; + ps2poll(); + } + #endif + + if (timerTick) { + //printf("isr\n"); + timerTick = 0; + doirq(0); + } + + if (trap_toggle) intcall86(1); + if (tf) trap_toggle = 1; + else trap_toggle = 0; + if (!trap_toggle && (ifl && (i8259.irr & (~i8259.imr)))) intcall86(nextintr()); //get next interrupt from the i8259, if any + reptype = 0; segoverride = 0; + useseg = segregs[regds]; docontinue = 0; + firstip = ip; + while (!docontinue) { + segregs[regcs] = segregs[regcs] & 0xFFFF; ip = ip & 0xFFFF; + savecs = segregs[regcs]; saveip = ip; + opcode = getmem8(segregs[regcs], ip); StepIP(1); + + switch (opcode) { + //segment prefix check + case 0x2E: //segment segregs[regcs] + useseg = segregs[regcs]; segoverride = 1; break; + case 0x3E: //segment segregs[regds] + useseg = segregs[regds]; segoverride = 1; break; + case 0x26: //segment segregs[reges] + useseg = segregs[reges]; segoverride = 1; break; + case 0x36: //segment segregs[regss] + useseg = segregs[regss]; segoverride = 1; break; + + //repetition prefix check + case 0xF3: //REP/REPE/REPZ + reptype = 1; break; + case 0xF2: //REPNE/REPNZ + reptype = 2; break; + default: + docontinue = 1; + break; + } + } + totalexec++; + //printf("%04X:%04X %02X\n", segregs[regcs], ip, opcode); + //if ((segregs[regcs]==0xF000) && (ip < 0xE000)) exit(0); + +#ifdef PROFILING + startmicros = micros(); +#endif + switch (opcode) { + case 0x0: //00 ADD Eb Gb + modregrm(); + oper1b = readrm8(rm); oper2b = getreg8(reg); + op_add8(); + writerm8(rm, res8); + break; + case 0x1: //01 ADD Ev Gv + modregrm(); + oper1 = readrm16(rm); oper2 = getreg16(reg); + op_add16(); + writerm16(rm, res16); + break; + case 0x2: //02 ADD Gb Eb + modregrm(); + oper1b = getreg8(reg); oper2b = readrm8(rm); + op_add8(); + putreg8(reg, res8); + break; + case 0x3: //03 ADD Gv Ev + modregrm(); + oper1 = getreg16(reg); oper2 = readrm16(rm); + op_add16(); + putreg16(reg, res16); + break; + case 0x4: //04 ADD regs.byteregs[regal] Ib + oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1); + op_add8(); + regs.byteregs[regal] = res8; + break; + case 0x5: //05 ADD eAX Iv + oper1 = (getreg16(regax)); oper2 = getmem16(segregs[regcs], ip); StepIP(2); + op_add16(); + putreg16(regax, res16); + break; + case 0x6: //06 PUSH segregs[reges] + push(segregs[reges]); + break; + case 0x7: //07 POP segregs[reges] + segregs[reges] = pop(); + break; + case 0x8: //08 OR Eb Gb + modregrm(); + oper1b = readrm8(rm); oper2b = getreg8(reg); + op_or8(); + writerm8(rm, res8); + break; + case 0x9: //09 OR Ev Gv + modregrm(); + oper1 = readrm16(rm); oper2 = getreg16(reg); + op_or16(); + writerm16(rm, res16); + break; + case 0xA: //0A OR Gb Eb + modregrm(); + oper1b = getreg8(reg); oper2b = readrm8(rm); + op_or8(); + putreg8(reg, res8); + break; + case 0xB: //0B OR Gv Ev + modregrm(); + oper1 = getreg16(reg); oper2 = readrm16(rm); + op_or16(); + if ((oper1 == 0xF802) && (oper2 == 0xF802)) sf = 0; //cheap hack to make Wolf 3D think we're a 286 so it plays + putreg16(reg, res16); + break; + case 0xC: //0C OR regs.byteregs[regal] Ib + oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1); + op_or8(); + regs.byteregs[regal] = res8; + break; + case 0xD: //0D OR eAX Iv + oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2); + op_or16(); + putreg16(regax, res16); + break; + case 0xE: //0E PUSH segregs[regcs] + push(segregs[regcs]); + break; + case 0xF: //0F POP CS + segregs[regcs] = pop(); + break; + /*case 0xF: //0F 80286+ extended opcodes + segregs[regcs] = segregs[regcs] & 0xFFFF; ip = ip & 0xFFFF; + savecs = segregs[regcs]; saveip = ip; + opcode = getmem8(segregs[regcs], ip); StepIP(1); + op_286(); + break;*/ + case 0x10: //10 ADC Eb Gb + modregrm(); + oper1b = readrm8(rm); oper2b = getreg8(reg); + op_adc8(); + writerm8(rm, res8); + break; + case 0x11: //11 ADC Ev Gv + modregrm(); + oper1 = readrm16(rm); oper2 = getreg16(reg); + op_adc16(); + writerm16(rm, res16); + break; + case 0x12: //12 ADC Gb Eb + modregrm(); + oper1b = getreg8(reg); oper2b = readrm8(rm); + op_adc8(); + putreg8(reg, res8); + break; + case 0x13: //13 ADC Gv Ev + modregrm(); + oper1 = getreg16(reg); oper2 = readrm16(rm); + op_adc16(); + putreg16(reg, res16); + break; + case 0x14: //14 ADC regs.byteregs[regal] Ib + oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1); + op_adc8(); + regs.byteregs[regal] = res8; + break; + case 0x15: //15 ADC eAX Iv + oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2); + op_adc16(); + putreg16(regax, res16); + break; + case 0x16: //16 PUSH segregs[regss] + push(segregs[regss]); + break; + case 0x17: //17 POP segregs[regss] + segregs[regss] = pop(); + break; + case 0x18: //18 SBB Eb Gb + modregrm(); + oper1b = readrm8(rm); oper2b = getreg8(reg); + op_sbb8(); + writerm8(rm, res8); + break; + case 0x19: //19 SBB Ev Gv + modregrm(); + oper1 = readrm16(rm); oper2 = getreg16(reg); + op_sbb16(); + writerm16(rm, res16); + break; + case 0x1A: //1A SBB Gb Eb + modregrm(); + oper1b = getreg8(reg); oper2b = readrm8(rm); + op_sbb8(); + putreg8(reg, res8); + break; + case 0x1B: //1B SBB Gv Ev + modregrm(); + oper1 = getreg16(reg); oper2 = readrm16(rm); + op_sbb16(); + putreg16(reg, res16); + break; + case 0x1C: //1C SBB regs.byteregs[regal] Ib; + oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1); + op_sbb8(); + regs.byteregs[regal] = res8; + break; + case 0x1D: //1D SBB eAX Iv + oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2); + op_sbb16(); + putreg16(regax, res16); + break; + case 0x1E: //1E PUSH segregs[regds] + push(segregs[regds]); + break; + case 0x1F: //1F POP segregs[regds] + segregs[regds] = pop(); + break; + case 0x20: //20 AND Eb Gb + modregrm(); + oper1b = readrm8(rm); oper2b = getreg8(reg); + op_and8(); + writerm8(rm, res8); + break; + case 0x21: //21 AND Ev Gv + modregrm(); + oper1 = readrm16(rm); oper2 = getreg16(reg); + op_and16(); + writerm16(rm, res16); + break; + case 0x22: //22 AND Gb Eb + modregrm(); + oper1b = getreg8(reg); oper2b = readrm8(rm); + op_and8(); + putreg8(reg, res8); + break; + case 0x23: //23 AND Gv Ev + modregrm(); + oper1 = getreg16(reg); oper2 = readrm16(rm); + op_and16(); + putreg16(reg, res16); + break; + case 0x24: //24 AND regs.byteregs[regal] Ib + oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1); + op_and8(); + regs.byteregs[regal] = res8; + break; + case 0x25: //25 AND eAX Iv + oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2); + op_and16(); + putreg16(regax, res16); + break; + case 0x27: //27 DAA + if (((regs.byteregs[regal] & 0xF) > 9) || (af == 1)) { + oper1 = regs.byteregs[regal] + 6; + regs.byteregs[regal] = oper1 & 255; + if (oper1 & 0xFF00) cf = 1; else cf = 0; + af = 1; + } else af = 0; + if (((regs.byteregs[regal] & 0xF0) > 0x90) || (cf == 1)) { + regs.byteregs[regal] = regs.byteregs[regal] + 0x60; + cf = 1; + } else cf = 0; + regs.byteregs[regal] = regs.byteregs[regal] & 255; + flag_szp8(regs.byteregs[regal]); + break; + case 0x28: //28 SUB Eb Gb + modregrm(); + oper1b = readrm8(rm); oper2b = getreg8(reg); + op_sub8(); + writerm8(rm, res8); + break; + case 0x29: //29 SUB Ev Gv + modregrm(); + oper1 = readrm16(rm); oper2 = getreg16(reg); + op_sub16(); + writerm16(rm, res16); + break; + case 0x2A: //2A SUB Gb Eb + modregrm(); + oper1b = getreg8(reg); oper2b = readrm8(rm); + op_sub8(); + putreg8(reg, res8); + break; + case 0x2B: //2B SUB Gv Ev + modregrm(); + oper1 = getreg16(reg); oper2 = readrm16(rm); + op_sub16(); + putreg16(reg, res16); + break; + case 0x2C: //2C SUB regs.byteregs[regal] Ib + oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1); + op_sub8(); + regs.byteregs[regal] = res8; + break; + case 0x2D: //2D SUB eAX Iv + oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2); + op_sub16(); + putreg16(regax, res16); + break; + case 0x2F: //2F DAS + if (((regs.byteregs[regal] & 15) > 9) || (af == 1)) { + oper1 = regs.byteregs[regal] - 6; + regs.byteregs[regal] = oper1 & 255; + if (oper1 & 0xFF00) cf = 1; else cf = 0; + af = 1; + } else af = 0; + if (((regs.byteregs[regal] & 0xF0) > 0x90) || (cf == 1)) { + regs.byteregs[regal] = regs.byteregs[regal] - 0x60; + cf = 1; + } else cf = 0; + flag_szp8(regs.byteregs[regal]); + break; + case 0x30: //30 XOR Eb Gb + modregrm(); + oper1b = readrm8(rm); oper2b = getreg8(reg); + op_xor8(); + writerm8(rm, res8); + break; + case 0x31: //31 XOR Ev Gv + modregrm(); + oper1 = readrm16(rm); oper2 = getreg16(reg); + op_xor16(); + writerm16(rm, res16); + break; + case 0x32: //32 XOR Gb Eb + modregrm(); + oper1b = getreg8(reg); oper2b = readrm8(rm); + op_xor8(); + putreg8(reg, res8); + break; + case 0x33: //33 XOR Gv Ev + modregrm(); + oper1 = getreg16(reg); oper2 = readrm16(rm); + op_xor16(); + putreg16(reg, res16); + break; + case 0x34: //34 XOR regs.byteregs[regal] Ib + oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1); + op_xor8(); + regs.byteregs[regal] = res8; + break; + case 0x35: //35 XOR eAX Iv + oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2); + op_xor16(); + putreg16(regax, res16); + break; + case 0x37: //37 AAA ASCII + if (((regs.byteregs[regal] & 0xF) > 9) || (af == 1)) { + regs.byteregs[regal] = regs.byteregs[regal] + 6; + regs.byteregs[regah] = regs.byteregs[regah] + 1; + af = 1; + cf = 1; + } else { + af = 0; + cf = 0; + } + regs.byteregs[regal] = regs.byteregs[regal] & 0xF; + break; + case 0x38: //38 CMP Eb Gb + modregrm(); + oper1b = readrm8(rm); oper2b = getreg8(reg); + flag_sub8(oper1b, oper2b); + break; + case 0x39: //39 CMP Ev Gv + modregrm(); + oper1 = readrm16(rm); oper2 = getreg16(reg); + flag_sub16(oper1, oper2); + break; + case 0x3A: //3A CMP Gb Eb + modregrm(); + oper1b = getreg8(reg); oper2b = readrm8(rm); + flag_sub8(oper1b, oper2b); + break; + case 0x3B: //3B CMP Gv Ev + modregrm(); + oper1 = getreg16(reg); oper2 = readrm16(rm); + flag_sub16(oper1, oper2); + break; + case 0x3C: //3C CMP regs.byteregs[regal] Ib + oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1); + flag_sub8(oper1b, oper2b); + break; + case 0x3D: //3D CMP eAX Iv + oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2); + flag_sub16(oper1, oper2); + break; + case 0x3F: //3F AAS ASCII + if (((regs.byteregs[regal] & 0xF) > 9) || (af == 1)) { + regs.byteregs[regal] = regs.byteregs[regal] - 6; + regs.byteregs[regah] = regs.byteregs[regah] - 1; + af = 1; + cf = 1; + } else { + af = 0; + cf = 0; + } + regs.byteregs[regal] = regs.byteregs[regal] & 0xF; + break; + case 0x40: //40 INC eAX + oldcf = cf; + oper1 = getreg16(regax); oper2 = 1; + op_add16(); + cf = oldcf; + putreg16(regax, res16); + break; + case 0x41: //41 INC eCX + oldcf = cf; + oper1 = getreg16(regcx); oper2 = 1; + op_add16(); + cf = oldcf; + putreg16(regcx, res16); + break; + case 0x42: //42 INC eDX + oldcf = cf; + oper1 = getreg16(regdx); oper2 = 1; + op_add16(); + cf = oldcf; + putreg16(regdx, res16); + break; + case 0x43: //43 INC eBX + oldcf = cf; + oper1 = getreg16(regbx); oper2 = 1; + op_add16(); + cf = oldcf; + putreg16(regbx, res16); + break; + case 0x44: //44 INC eSP + oldcf = cf; + oper1 = getreg16(regsp); oper2 = 1; + op_add16(); + cf = oldcf; + putreg16(regsp, res16); + break; + case 0x45: //45 INC eBP + oldcf = cf; + oper1 = getreg16(regbp); oper2 = 1; + op_add16(); + cf = oldcf; + putreg16(regbp, res16); + break; + case 0x46: //46 INC eSI + oldcf = cf; + oper1 = getreg16(regsi); oper2 = 1; + op_add16(); + cf = oldcf; + putreg16(regsi, res16); + break; + case 0x47: //47 INC eDI + oldcf = cf; + oper1 = getreg16(regdi); oper2 = 1; + op_add16(); + cf = oldcf; + putreg16(regdi, res16); + break; + case 0x48: //48 DEC eAX + oldcf = cf; + oper1 = getreg16(regax); oper2 = 1; + op_sub16(); + cf = oldcf; + putreg16(regax, res16); + break; + case 0x49: //49 DEC eCX + oldcf = cf; + oper1 = getreg16(regcx); oper2 = 1; + op_sub16(); + cf = oldcf; + putreg16(regcx, res16); + break; + case 0x4A: //4A DEC eDX + oldcf = cf; + oper1 = getreg16(regdx); oper2 = 1; + op_sub16(); + cf = oldcf; + putreg16(regdx, res16); + break; + case 0x4B: //4B DEC eBX + oldcf = cf; + oper1 = getreg16(regbx); oper2 = 1; + op_sub16(); + cf = oldcf; + putreg16(regbx, res16); + break; + case 0x4C: //4C DEC eSP + oldcf = cf; + oper1 = getreg16(regsp); oper2 = 1; + op_sub16(); + cf = oldcf; + putreg16(regsp, res16); + break; + case 0x4D: //4D DEC eBP + oldcf = cf; + oper1 = getreg16(regbp); oper2 = 1; + op_sub16(); + cf = oldcf; + putreg16(regbp, res16); + break; + case 0x4E: //4E DEC eSI + oldcf = cf; + oper1 = getreg16(regsi); oper2 = 1; + op_sub16(); + cf = oldcf; + putreg16(regsi, res16); + break; + case 0x4F: //4F DEC eDI + oldcf = cf; + oper1 = getreg16(regdi); oper2 = 1; + op_sub16(); + cf = oldcf; + putreg16(regdi, res16); + break; + case 0x50: //50 PUSH eAX + push (getreg16(regax)); + break; + case 0x51: //51 PUSH eCX + push (getreg16(regcx)); + break; + case 0x52: //52 PUSH eDX + push (getreg16(regdx)); + break; + case 0x53: //53 PUSH eBX + push (getreg16(regbx)); + break; + case 0x54: //54 PUSH eSP + push (getreg16(regsp) - 2); + break; + case 0x55: //55 PUSH eBP + push (getreg16(regbp)); + break; + case 0x56: //56 PUSH eSI + push (getreg16(regsi)); + break; + case 0x57: //57 PUSH eDI + push (getreg16(regdi)); + break; + case 0x58: //58 POP eAX + putreg16(regax, pop()); + break; + case 0x59: //59 POP eCX + putreg16(regcx, pop()); + break; + case 0x5A: //5A POP eDX + putreg16(regdx, pop()); + break; + case 0x5B: //5B POP eBX + putreg16(regbx, pop()); + break; + case 0x5C: //5C POP eSP + putreg16(regsp, pop()); + break; + case 0x5D: //5D POP eBP + putreg16(regbp, pop()); + break; + case 0x5E: //5E POP eSI + putreg16(regsi, pop()); + break; + case 0x5F: //5F POP eDI + putreg16(regdi, pop()); + break; + case 0x60: //60 PUSHA (80186+) + oldsp = getreg16(regsp); + push(getreg16(regax)); + push(getreg16(regcx)); + push(getreg16(regdx)); + push(getreg16(regbx)); + push(oldsp); + push(getreg16(regbp)); + push(getreg16(regsi)); + push(getreg16(regdi)); + break; + case 0x61: //61 POPA (80186+) + putreg16(regdi, pop()); + putreg16(regsi, pop()); + putreg16(regbp, pop()); + dummy = pop(); + putreg16(regbx, pop()); + putreg16(regdx, pop()); + putreg16(regcx, pop()); + putreg16(regax, pop()); + break; + case 0x68: //68 PUSH Iv (80186+) + push(getmem16(segregs[regcs], ip)); StepIP(2); + break; + case 0x69: //69 IMUL Gv Ev Iv (80186+) + //print("WE HIT 69h IMUL\r\n"); + modregrm(); + temp1 = readrm16(rm); + temp2 = getmem16(segregs[regcs], ip); StepIP(2); + if ((temp1 & 0x8000L) == 0x8000L) temp1 = temp1 | 0xFFFF0000L; + if ((temp2 & 0x8000L) == 0x8000L) temp2 = temp2 | 0xFFFF0000L; + temp3 = temp1 * temp2; + putreg16(reg, temp3 & 0xFFFFL); + if (temp3 & 0xFFFF0000L) { + cf = 1; + of = 1; + } else { + cf = 0; + of = 0; + } + break; + case 0x6A: //6A PUSH Ib (80186+) + push(getmem8(segregs[regcs], ip)); StepIP(1); + break; + case 0x6B: //6B IMUL Gv Eb Ib (80186+) + //print("WE HIT 6Bh IMUL\r\n"); + modregrm(); + temp1 = readrm16(rm); + temp2 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if ((temp1 & 0x8000L) == 0x8000L) temp1 = temp1 | 0xFFFF0000L; + if ((temp2 & 0x8000L) == 0x8000L) temp2 = temp2 | 0xFFFF0000L; + temp3 = temp1 * temp2; + putreg16(reg, temp3 & 0xFFFFL); + if (temp3 & 0xFFFF0000L) { + cf = 1; + of = 1; + } else { + cf = 0; + of = 0; + } + break; + //case 0x6C ... 0x6F: //80186 port operations, just act as if they//re NOPs for now... + // StepIP(1); //they have a modregrm(); byte we must skip... i may properly emulate these later. + // break; + case 0x6E: //6E OUTSB + if (reptype && (getreg16(regcx) == 0)) break; + portout16 = 0; + portout(regs.wordregs[regdx], getmem16(useseg, getreg16(regsi))); + if (df) { + putreg16(regsi, getreg16(regsi) - 1); + putreg16(regdi, getreg16(regdi) - 1); + } + else { + putreg16(regsi, getreg16(regsi) + 1); + putreg16(regdi, getreg16(regdi) + 1); + } + if (reptype) putreg16(regcx, getreg16(regcx) - 1); + if (!reptype) break; + ip = firstip; + break; + case 0x6F: //6F OUTSW + if (reptype && (getreg16(regcx) == 0)) break; + portout16 = 1; + portout(regs.wordregs[regdx], getmem16(useseg, getreg16(regsi))); + if (df) { + putreg16(regsi, getreg16(regsi) - 2); + putreg16(regdi, getreg16(regdi) - 2); + } + else { + putreg16(regsi, getreg16(regsi) + 2); + putreg16(regdi, getreg16(regdi) + 2); + } + if (reptype) putreg16(regcx, getreg16(regcx) - 1); + if (!reptype) break; + ip = firstip; + break; + + case 0x70: //70 JO Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (of) ip = ip + temp16; + break; + case 0x71: //71 JNO Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (!of) ip = ip + temp16; + break; + case 0x72: //72 JB Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (cf) ip = ip + temp16; + break; + case 0x73: //73 JNB Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (!cf) ip = ip + temp16; + break; + case 0x74: //74 JZ Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (zf) ip = ip + temp16; + break; + case 0x75: //75 JNZ Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (!zf) ip = ip + temp16; + break; + case 0x76: //76 JBE Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (cf || zf) ip = ip + temp16; + break; + case 0x77: //77 JA Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (!cf && !zf) ip = ip + temp16; + break; + case 0x78: //78 JS Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (sf) ip = ip + temp16; + break; + case 0x79: //79 JNS Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (!sf) ip = ip + temp16; + break; + case 0x7A: //7A JPE Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (pf) ip = ip + temp16; + break; + case 0x7B: //7B JPO Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (!pf) ip = ip + temp16; + break; + case 0x7C: //7C JL Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (sf != of) ip = ip + temp16; + break; + case 0x7D: //7D JGE Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (sf == of) ip = ip + temp16; + break; + case 0x7E: //7E JLE Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if ((sf != of) || zf) ip = ip + temp16; + break; + case 0x7F: //7F JG Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (!zf && (sf == of)) ip = ip + temp16; + break; + case 0x80: case 0x82: //80/82 GRP1 Eb Ib + modregrm(); + oper1b = readrm8(rm); + oper2b = getmem8(segregs[regcs], ip); StepIP(1); + switch (reg) { + case 0: op_add8(); break; + case 1: op_or8(); break; + case 2: op_adc8(); break; + case 3: op_sbb8(); break; + case 4: op_and8(); break; + case 5: op_sub8(); break; + case 6: op_xor8(); break; + case 7: flag_sub8(oper1b, oper2b); break; + default: break; //to avoid compiler warnings + } + if (reg < 7) writerm8(rm, res8); + break; + case 0x81: //81 GRP1 Ev Iv + case 0x83: //83 GRP1 Ev Ib + modregrm(); + oper1 = readrm16(rm); + if (opcode == 0x81) { + oper2 = getmem16(segregs[regcs], ip); StepIP(2); + } else { + oper2 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + } + switch (reg) { + case 0: op_add16(); break; + case 1: op_or16(); break; + case 2: op_adc16(); break; + case 3: op_sbb16(); break; + case 4: op_and16(); break; + case 5: op_sub16(); break; + case 6: op_xor16(); break; + case 7: flag_sub16(oper1, oper2); break; + default: break; //to avoid compiler warnings + } + if (reg < 7) writerm16(rm, res16); + break; + case 0x84: //84 TEST Gb Eb + modregrm(); + oper1b = getreg8(reg); oper2b = readrm8(rm); + flag_log8(oper1b & oper2b); + break; + case 0x85: //85 TEST Gv Ev + modregrm(); + oper1 = getreg16(reg); oper2 = readrm16(rm); + flag_log16(oper1 & oper2); + break; + case 0x86: //86 XCHG Gb Eb + modregrm(); + oper1b = getreg8(reg); + putreg8(reg, readrm8(rm)); + writerm8(rm, oper1b); + break; + case 0x87: //87 XCHG Gv Ev + modregrm(); + oper1 = getreg16(reg); + putreg16(reg, readrm16(rm)); + writerm16(rm, oper1); + break; + case 0x88: //88 MOV Eb Gb + modregrm(); + writerm8(rm, getreg8(reg)); + break; + case 0x89: //89 MOV Ev Gv + modregrm(); + writerm16(rm, getreg16(reg)); + break; + case 0x8A: //8A MOV Gb Eb + modregrm(); + putreg8(reg, readrm8(rm)); + break; + case 0x8B: //8B MOV Gv Ev + modregrm(); + putreg16(reg, readrm16(rm)); + break; + case 0x8C: //8C MOV Ew Sw + modregrm(); + writerm16(rm, getsegreg(reg)); + break; + case 0x8D: //8D LEA Gv M + modregrm(); + //getea(rm); + putreg16(reg, ea - segbase(useseg)); + break; + case 0x8E: //8E MOV Sw Ew + modregrm(); + putsegreg(reg, readrm16(rm)); + break; + case 0x8F: //8F POP Ev + modregrm(); + writerm16(rm, pop()); + break; + case 0x90: //90 NOP + break; + case 0x91: //91 XCHG eCX eAX + oper1 = getreg16(regcx); + putreg16(regcx, getreg16(regax)); + putreg16(regax, oper1); + break; + case 0x92: //92 XCHG eDX eAX + oper1 = getreg16(regdx); + putreg16(regdx, getreg16(regax)); + putreg16(regax, oper1); + break; + case 0x93: //93 XCHG eBX eAX + oper1 = getreg16(regbx); + putreg16(regbx, getreg16(regax)); + putreg16(regax, oper1); + break; + case 0x94: //94 XCHG eSP eAX + oper1 = getreg16(regsp); + putreg16(regsp, getreg16(regax)); + putreg16(regax, oper1); + break; + case 0x95: //95 XCHG eBP eAX + oper1 = getreg16(regbp); + putreg16(regbp, getreg16(regax)); + putreg16(regax, oper1); + break; + case 0x96: //96 XCHG eSI eAX + oper1 = getreg16(regsi); + putreg16(regsi, getreg16(regax)); + putreg16(regax, oper1); + break; + case 0x97: //97 XCHG eDI eAX + oper1 = getreg16(regdi); + putreg16(regdi, getreg16(regax)); + putreg16(regax, oper1); + break; + case 0x98: //98 CBW + if ((regs.byteregs[regal] & 0x80) == 0x80) regs.byteregs[regah] = 0xFF; else regs.byteregs[regah] = 0; + break; + case 0x99: //99 CWD + if ((regs.byteregs[regah] & 0x80) == 0x80) putreg16(regdx, 0xFFFF); else putreg16(regdx, 0); + break; + case 0x9A: //9A CALL Ap + oper1 = getmem16(segregs[regcs], ip); StepIP(2); + oper2 = getmem16(segregs[regcs], ip); StepIP(2); + push(segregs[regcs]); push(ip); ip = oper1; segregs[regcs] = oper2; + break; + case 0x9B: //9B WAIT + break; + case 0x9C: //9C PUSHF + push(makeflagsword() | 0xF800); + break; + case 0x9D: //9D POPF + temp16 = pop(); + decodeflagsword(temp16); + break; + case 0x9E: //9E SAHF + decodeflagsword ((makeflagsword() & 0xFF00) | regs.byteregs[regah]); + break; + case 0x9F: //9F LAHF + regs.byteregs[regah] = makeflagsword() & 0xFF; + break; + case 0xA0: //A0 MOV regs.byteregs[regal] Ob + regs.byteregs[regal] = getmem8(useseg, getmem16(segregs[regcs], ip)); StepIP(2); + break; + case 0xA1: //A1 MOV eAX Ov + oper1 = getmem16(useseg, getmem16(segregs[regcs], ip)); StepIP(2); + putreg16(regax, oper1); + break; + case 0xA2: //A2 MOV Ob regs.byteregs[regal] + putmem8(useseg, getmem16(segregs[regcs], ip), regs.byteregs[regal]); StepIP(2); + break; + case 0xA3: //A3 MOV Ov eAX + putmem16(useseg, getmem16(segregs[regcs], ip), getreg16(regax)); StepIP(2); + break; + case 0xA4: //A4 MOVSB + if (reptype && (getreg16(regcx) == 0)) break; + putmem8(segregs[reges], getreg16(regdi), getmem8(useseg, getreg16(regsi))); + if (df) { + putreg16(regsi, getreg16(regsi) - 1); + putreg16(regdi, getreg16(regdi) - 1); + } + else { + putreg16(regsi, getreg16(regsi) + 1); + putreg16(regdi, getreg16(regdi) + 1); + } + if (reptype) putreg16(regcx, getreg16(regcx) - 1); + if (!reptype) break; + ip = firstip; + break; + case 0xA5: //A5 MOVSW + if (reptype && (getreg16(regcx) == 0)) break; + putmem16(segregs[reges], getreg16(regdi), getmem16(useseg, getreg16(regsi))); + if (df) { + putreg16(regsi, getreg16(regsi) - 2); + putreg16(regdi, getreg16(regdi) - 2); + } + else { + putreg16(regsi, getreg16(regsi) + 2); + putreg16(regdi, getreg16(regdi) + 2); + } + if (reptype) putreg16(regcx, getreg16(regcx) - 1); + if (!reptype) break; + ip = firstip; + break; + case 0xA6: //A6 CMPSB + if (reptype && (getreg16(regcx) == 0)) break; + oper1b = getmem8(useseg, getreg16(regsi)); oper2b = getmem8(segregs[reges], getreg16(regdi)); + if (df) { + putreg16(regsi, getreg16(regsi) - 1); + putreg16(regdi, getreg16(regdi) - 1); + } + else { + putreg16(regsi, getreg16(regsi) + 1); + putreg16(regdi, getreg16(regdi) + 1); + } + flag_sub8(oper1b, oper2b); + if (reptype) putreg16(regcx, getreg16(regcx) - 1); + if ((reptype == 1) && !zf) break; + else if ((reptype == 2) && (zf == 1)) break; + if (!reptype) break; + ip = firstip; + break; + case 0xA7: //A7 CMPSW + if (reptype && (getreg16(regcx) == 0)) break; + oper1 = getmem16(useseg, getreg16(regsi)); oper2 = getmem16(segregs[reges], getreg16(regdi)); + if (df) { + putreg16(regsi, getreg16(regsi) - 2); + putreg16(regdi, getreg16(regdi) - 2); + } + else { + putreg16(regsi, getreg16(regsi) + 2); + putreg16(regdi, getreg16(regdi) + 2); + } + flag_sub16(oper1, oper2); + if (reptype) putreg16(regcx, getreg16(regcx) - 1); + if ((reptype == 1) && !zf) break; + if ((reptype == 2) && (zf == 1)) break; + if (!reptype) break; + ip = firstip; + break; + case 0xA8: //A8 TEST regs.byteregs[regal] Ib + oper1b = regs.byteregs[regal]; oper2b = getmem8(segregs[regcs], ip); StepIP(1); + flag_log8(oper1b & oper2b); + break; + case 0xA9: //A9 TEST eAX Iv + oper1 = getreg16(regax); oper2 = getmem16(segregs[regcs], ip); StepIP(2); + flag_log16(oper1 & oper2); + break; + case 0xAA: //AA STOSB + if (reptype && (getreg16(regcx) == 0)) break; + putmem8(segregs[reges], getreg16(regdi), regs.byteregs[regal]); + if (df) putreg16(regdi, getreg16(regdi) - 1); + else putreg16(regdi, getreg16(regdi) + 1); + if (reptype) putreg16(regcx, getreg16(regcx) - 1); + if (!reptype) break; + ip = firstip; + break; + case 0xAB: //AB STOSW + if (reptype && (getreg16(regcx) == 0)) break; + putmem16(segregs[reges], getreg16(regdi), getreg16(regax)); + if (df) putreg16(regdi, getreg16(regdi) - 2); + else putreg16(regdi, getreg16(regdi) + 2); + if (reptype) putreg16(regcx, getreg16(regcx) - 1); + if (!reptype) break; + ip = firstip; + break; + case 0xAC: //AC LODSB + if (reptype && (getreg16(regcx) == 0)) break; + regs.byteregs[regal] = getmem8(useseg, getreg16(regsi)); + if (df) putreg16(regsi, getreg16(regsi) - 1); + else putreg16(regsi, getreg16(regsi) + 1); + if (reptype) putreg16(regcx, getreg16(regcx) - 1); + if (!reptype) break; + ip = firstip; + break; + case 0xAD: //AD LODSW + if (reptype && (getreg16(regcx) == 0)) break; + oper1 = getmem16(useseg, getreg16(regsi)); + putreg16(regax, oper1); + if (df) putreg16(regsi, getreg16(regsi) - 2); + else putreg16(regsi, getreg16(regsi) + 2); + if (reptype) putreg16(regcx, getreg16(regcx) - 1); + if (!reptype) break; + ip = firstip; + break; + case 0xAE: //AE SCASB + if (reptype && (getreg16(regcx) == 0)) break; + oper1b = getmem8(segregs[reges], getreg16(regdi)); oper2b = regs.byteregs[regal]; + flag_sub8(oper1b, oper2b); + if (df) putreg16(regdi, getreg16(regdi) - 1); + else putreg16(regdi, getreg16(regdi) + 1); + if (reptype) putreg16(regcx, getreg16(regcx) - 1); + if ((reptype == 1) && !zf) break; + else if ((reptype == 2) && (zf == 1)) break; + if (!reptype) break; + ip = firstip; + break; + case 0xAF: //AF SCASW + if (reptype && (getreg16(regcx) == 0)) break; + oper1 = getmem16(segregs[reges], getreg16(regdi)); oper2 = getreg16(regax); + flag_sub16(oper1, oper2); + if (df) putreg16(regdi, getreg16(regdi) - 2); + else putreg16(regdi, getreg16(regdi) + 2); + if (reptype) putreg16(regcx, getreg16(regcx) - 1); + if ((reptype == 1) && !zf) break; + else if ((reptype == 2) & (zf == 1)) break; + if (!reptype) break; + ip = firstip; + break; + case 0xB0: //B0 MOV regs.byteregs[regal] Ib + regs.byteregs[regal] = getmem8(segregs[regcs], ip); StepIP(1); + break; + case 0xB1: //B1 MOV regs.byteregs[regcl] Ib + regs.byteregs[regcl] = getmem8(segregs[regcs], ip); StepIP(1); + break; + case 0xB2: //B2 MOV regs.byteregs[regdl] Ib + regs.byteregs[regdl] = getmem8(segregs[regcs], ip); StepIP(1); + break; + case 0xB3: //B3 MOV regs.byteregs[regbl] Ib + regs.byteregs[regbl] = getmem8(segregs[regcs], ip); StepIP(1); + break; + case 0xB4: //B4 MOV regs.byteregs[regah] Ib + regs.byteregs[regah] = getmem8(segregs[regcs], ip); StepIP(1); + break; + case 0xB5: //B5 MOV regs.byteregs[regch] Ib + regs.byteregs[regch] = getmem8(segregs[regcs], ip); StepIP(1); + break; + case 0xB6: //B6 MOV regs.byteregs[regdh] Ib + regs.byteregs[regdh] = getmem8(segregs[regcs], ip); StepIP(1); + break; + case 0xB7: //B7 MOV regs.byteregs[regbh] Ib + regs.byteregs[regbh] = getmem8(segregs[regcs], ip); StepIP(1); + break; + case 0xB8: //B8 MOV eAX Iv + oper1 = getmem16(segregs[regcs], ip); StepIP(2); + putreg16(regax, oper1); + break; + case 0xB9: //B9 MOV eCX Iv + oper1 = getmem16(segregs[regcs], ip); StepIP(2); + putreg16(regcx, oper1); + break; + case 0xBA: //BA MOV eDX Iv + oper1 = getmem16(segregs[regcs], ip); StepIP(2); + putreg16(regdx, oper1); + break; + case 0xBB: //BB MOV eBX Iv + oper1 = getmem16(segregs[regcs], ip); StepIP(2); + putreg16(regbx, oper1); + break; + case 0xBC: //BC MOV eSP Iv + putreg16(regsp, getmem16(segregs[regcs], ip)); StepIP(2); + break; + case 0xBD: //BD MOV eBP Iv + putreg16(regbp, getmem16(segregs[regcs], ip)); StepIP(2); + break; + case 0xBE: //BE MOV eSI Iv + putreg16(regsi, getmem16(segregs[regcs], ip)); StepIP(2); + break; + case 0xBF: //BF MOV eDI Iv + putreg16(regdi, getmem16(segregs[regcs], ip)); StepIP(2); + break; + case 0xC0: //C0 GRP2 byte imm8 (80186+) + modregrm(); + oper1b = readrm8(rm); + oper2b = getmem8(segregs[regcs], ip); StepIP(1); + writerm8(rm, op_grp2_8(oper2b)); + break; + case 0xC1: //C1 GRP2 word imm8 (80186+) + modregrm(); + oper1 = readrm16(rm); + oper2 = getmem8(segregs[regcs], ip); StepIP(1); + writerm16(rm, op_grp2_16(oper2)); + break; + case 0xC2: //C2 RET Iw + oper1 = getmem16(segregs[regcs], ip); + ip = pop(); + putreg16(regsp, getreg16(regsp) + oper1); + break; + case 0xC3: //C3 RET + ip = pop(); + break; + case 0xC4: //C4 LES Gv Mp + modregrm(); + //getea(rm); + putreg16(reg, read86(ea) + ((uint16_t)read86(ea + 1) << 8)); + segregs[reges] = read86(ea + 2) + ((uint16_t)read86(ea + 3) << 8); + break; + case 0xC5: //C5 LDS Gv Mp + modregrm(); + //getea(rm); + putreg16(reg, read86(ea) + ((uint16_t)read86(ea + 1) << 8)); + segregs[regds] = read86(ea + 2) + ((uint16_t)read86(ea + 3) << 8); + break; + case 0xC6: //C6 MOV Eb Ib + modregrm(); + writerm8(rm, getmem8(segregs[regcs], ip)); StepIP(1); + break; + case 0xC7: //C7 MOV Ev Iv + modregrm(); + writerm16(rm, getmem16(segregs[regcs], ip)); StepIP(2); + break; + case 0xC8: //C8 ENTER (80186+) + stacksize = getmem16(segregs[regcs], ip); StepIP(2); + nestlev = getmem8(segregs[regcs], ip); StepIP(1); + push(getreg16(regbp)); + frametemp = getreg16(regsp); + if (nestlev) { + for (temp16 = 1; temp16 < nestlev; temp16++) { + putreg16(regbp, getreg16(regbp) - 2); + push(getreg16(regbp)); + } + push(getreg16(regsp)); + } + putreg16(regbp, frametemp); + putreg16(regsp, getreg16(regbp) - stacksize); + + break; + case 0xC9: //C9 LEAVE (80186+) + putreg16(regsp, getreg16(regbp)); + putreg16(regbp, pop()); + + break; + case 0xCA: //CA RETF Iw + oper1 = getmem16(segregs[regcs], ip); + ip = pop(); segregs[regcs] = pop(); + putreg16(regsp, getreg16(regsp) + oper1); + break; + case 0xCB: //CB RETF + ip = pop();; segregs[regcs] = pop(); + break; + case 0xCC: //CC INT 3 + intcall86(3); + break; + case 0xCD: //CD INT Ib + oper1 = getmem8(segregs[regcs], ip); StepIP(1); + intcall86(oper1); + break; + case 0xCE: //CE INTO + if (of) intcall86(4); + break; + case 0xCF: //CF IRET + ip = pop(); segregs[regcs] = pop(); + decodeflagsword(pop()); + //if (net.enabled) net.canrecv = 1; + break; + case 0xD0: //D0 GRP2 Eb 1 + modregrm(); + oper1b = readrm8(rm); + writerm8(rm, op_grp2_8(1)); + break; + case 0xD1: //D1 GRP2 Ev 1 + modregrm(); + oper1 = readrm16(rm); + writerm16(rm, op_grp2_16(1)); + break; + case 0xD2: //D2 GRP2 Eb regs.byteregs[regcl] + modregrm(); + oper1b = readrm8(rm); + writerm8(rm, op_grp2_8(regs.byteregs[regcl])); + break; + case 0xD3: //D3 GRP2 Ev regs.byteregs[regcl] + modregrm(); + oper1 = readrm16(rm); + writerm16(rm, op_grp2_16(regs.byteregs[regcl])); + break; + case 0xD4: //D4 AAM I0 + oper1 = getmem8(segregs[regcs], ip); StepIP(1); + if (!oper1) { + intcall86(0); //division by zero + return; + } + regs.byteregs[regah] = (regs.byteregs[regal] / oper1) & 255; + regs.byteregs[regal] = (regs.byteregs[regal] % oper1) & 255; + flag_szp16 (getreg16(regax)); + break; + case 0xD5: //D5 AAD I0 + oper1 = getmem8(segregs[regcs], ip); StepIP(1); + regs.byteregs[regal] = (regs.byteregs[regah] * oper1 + regs.byteregs[regal]) & 255; + regs.byteregs[regah] = 0; + flag_szp16(regs.byteregs[regah] * oper1 + regs.byteregs[regal]); + sf = 0; + break; + case 0xD6: //D6 XLAT on V20/V30, SALC on 8086/8088 + regs.byteregs[regal] = cf; + break; + case 0xD7: //D7 XLAT + putreg8(regal, read86(segbase(useseg) + (uint32_t)getreg16(regbx) + (uint32_t)getreg8(regal))); + break; + case 0xD8: case 0xD9: case 0xDA: case 0xDB: case 0xDC: case 0xDE: case 0xDD: case 0xDF: //escape + StepIP(1); + break; + case 0xE0: //E0 LOOPNZ Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + putreg16(regcx, getreg16(regcx) - 1); + if ((getreg16(regcx)) && !zf) ip = ip + temp16; + break; + case 0xE1: //E1 LOOPZ Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + putreg16(regcx, (getreg16(regcx)) - 1); + if ((getreg16(regcx)) && (zf == 1)) ip = ip + temp16; + break; + case 0xE2: //E2 LOOP Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + putreg16(regcx, (getreg16(regcx)) - 1); + if (getreg16(regcx)) ip = ip + temp16; + break; + case 0xE3: //E3 JCXZ Jb + temp16 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + if (!(getreg16(regcx))) ip = ip + temp16; + break; + case 0xE4: //E4 IN regs.byteregs[regal] Ib + oper1b = getmem8(segregs[regcs], ip); + StepIP(1); + regs.byteregs[regal] = portin(oper1b); + break; + case 0xE5: //E5 IN eAX Ib + oper1b = getmem8(segregs[regcs], ip); + StepIP(1); + putreg16(regax, portin(oper1b)); + break; + case 0xE6: //E6 OUT Ib regs.byteregs[regal] + oper1b = getmem8(segregs[regcs], ip); + StepIP(1); + portout16 = 0; + portout(oper1b, regs.byteregs[regal]); + break; + case 0xE7: //E7 OUT Ib eAX + oper1b = getmem8(segregs[regcs], ip); + StepIP(1); + portout16 = 1; + portout(oper1b, (getreg16(regax))); + break; + case 0xE8: //E8 CALL Jv + oper1 = getmem16(segregs[regcs], ip); StepIP(2); + push(ip); + ip = ip + oper1; + break; + case 0xE9: //E9 JMP Jv + oper1 = getmem16(segregs[regcs], ip); StepIP(2); + ip = ip + oper1; + break; + case 0xEA: //EA JMP Ap + oper1 = getmem16(segregs[regcs], ip); StepIP(2); + oper2 = getmem16(segregs[regcs], ip); + ip = oper1; segregs[regcs] = oper2; + break; + case 0xEB: //EB JMP Jb + oper1 = signext(getmem8(segregs[regcs], ip)); StepIP(1); + ip = ip + oper1; + break; + case 0xEC: //EC IN regs.byteregs[regal] regdx + oper1 = (getreg16(regdx)); + regs.byteregs[regal] = portin(oper1); + break; + case 0xED: //ED IN eAX regdx + oper1 = (getreg16(regdx)); + putreg16(regax, portin(oper1)); + break; + case 0xEE: //EE OUT regdx regs.byteregs[regal] + oper1 = (getreg16(regdx)); + portout16 = 0; + portout(oper1, regs.byteregs[regal]); + break; + case 0xEF: //EF OUT regdx eAX + oper1 = (getreg16(regdx)); + portout16 = 1; + portout(oper1, (getreg16(regax))); + break; + case 0xF0: //F0 LOCK + case 0xF4: //F4 HLT + break; + case 0xF5: //F5 CMC + if (!cf) cf = 1; else cf = 0; + break; + case 0xF6: //F6 GRP3a Eb + modregrm(); + oper1b = readrm8(rm); + op_grp3_8(); + if ((reg > 1) && (reg < 4)) writerm8(rm, res8); + + break; + case 0xF7: //F7 GRP3b Ev + modregrm(); + oper1 = readrm16(rm); + op_grp3_16(); + if ((reg > 1) && (reg < 4)) writerm16(rm, res16); + break; + case 0xF8: //F8 CLC + cf = 0; + break; + case 0xF9: //F9 STC + cf = 1; + break; + case 0xFA: //FA CLI + ifl = 0; + break; + case 0xFB: //FB STI + ifl = 1; + break; + case 0xFC: //FC CLD + df = 0; + break; + case 0xFD: //FD STD + df = 1; + break; + case 0xFE: //FE GRP4 Eb + modregrm(); + oper1b = readrm8(rm); oper2b = 1; + if (!reg) { + tempcf = cf; + res8 = oper1b + oper2b; + flag_add8(oper1b, oper2b); + cf = tempcf; writerm8(rm, res8); + } else { + tempcf = cf; + res8 = oper1b - oper2b; + flag_sub8(oper1b, oper2b); + cf = tempcf; writerm8(rm, res8); + } + break; + case 0xFF: //FF GRP5 Ev + modregrm(); + oper1 = readrm16(rm); + op_grp5(); + break; + default: + intcall86(6); //trip invalid opcode exception (this occurs on the 80186+, 8086/8088 CPUs treat them as NOPs + if (verbose) { + //if (opcode==0xF) sprintf(msg, "Illegal opcode: %02X @ %04X:%04X\n", opcode, savecs, saveip); + //else + //sprintf(msg, "Illegal opcode: %02X %02X @ %04X:%04X\n", opcode, getmem8(savecs, saveip + 1), savecs, saveip); + } + + break; + } +#ifdef PROFILING + endmicros = micros(); + if (instrtime[opcode]) { + instrtime[opcode] = (instrtime[opcode] + (endmicros - startmicros)) >> 1; + } else { + instrtime[opcode] = endmicros - startmicros; + } +#endif + //if (!running) return; + } +} + +void testmem() { + +} + diff --git a/MCUME_esp32/esp8086/main/disk.cpp b/MCUME_esp32/esp8086/main/disk.cpp new file mode 100755 index 0000000..0469e2c --- /dev/null +++ b/MCUME_esp32/esp8086/main/disk.cpp @@ -0,0 +1,263 @@ +#include +#include +#include "emu.h" + + +extern uint8_t bootdrive, hdcount; +extern uint16_t segregs[6]; +extern uint8_t cf; +extern _bytewordregs_ regs; + +FILE *file; + +struct struct_drive { + uint32_t filesize; + uint16_t cyls; + uint16_t sects; + uint16_t heads; + uint8_t inserted; +} disk[4]; +uint8_t sectorbuffer[512]; + +uint8_t insertdisk(uint8_t drivenum) { + if (drivenum & 0x80) { + drivenum -= 126; + disk[drivenum].sects = 63; + disk[drivenum].heads = 16; + disk[drivenum].cyls = 1023; //up to 512 MB + hdcount = 1; + } else { +#ifdef FDD_144M + disk[drivenum].cyls = 80; + disk[drivenum].sects = 18; + disk[drivenum].heads = 2; +#endif +#ifdef FDD_122M + disk[drivenum].cyls = 80; + disk[drivenum].sects = 15; + disk[drivenum].heads = 2; +#endif +#ifdef FDD_720K + disk[drivenum].cyls = 80; + disk[drivenum].sects = 9; + disk[drivenum].heads = 2; +#endif +#ifdef FDD_360K + disk[drivenum].cyls = 40; + disk[drivenum].sects = 9; + disk[drivenum].heads = 2; +#endif +#ifdef FDD_320K + disk[drivenum].cyls = 40; + disk[drivenum].sects = 8; + disk[drivenum].heads = 2; +#endif +#ifdef FDD_180K + disk[drivenum].cyls = 40; + disk[drivenum].sects = 9; + disk[drivenum].heads = 1; +#endif + } + disk[drivenum].inserted = 1; + return 0; +} + +void ejectdisk(uint8_t drivenum) { + if (drivenum & 0x80) drivenum -= 126; + disk[drivenum].inserted = 0; +} + +extern uint16_t ramseg; +extern "C" { +extern void emu_SdReadBlock(int block, void * buf); +} +uint8_t sectdone; +void getsect(uint32_t lba, uint8_t *dst) { +#ifdef USB_DISK + uint8_t chksum; + uint32_t curmicros; +retrysectget: + Serial.write(0xFF); + Serial.write(0x05); + outByte(lba & 0xFF); chksum = lba & 0xFF; + outByte((lba >> 8) & 0xFF); chksum += (lba >> 8) & 0xFF; + outByte((lba >> 16) & 0xFF); chksum += (lba >> 16) & 0xFF; + outByte((lba >> 24) & 0xFF); chksum += (lba >> 24) & 0xFF; + outByte(chksum); + Serial.write(0xFE); + Serial.write(0x02); + sectdone = 0; + curmicros = micros(); + while (!sectdone) { + if (micros() < curmicros) curmicros = micros(); + if ((micros() - curmicros) >= 200000) goto retrysectget; + net_loop(); + } +#else + if (file) + { + //printf("read block %d\n",lba); + fseek(file,lba*512,SEEK_SET); + fread(dst,1,512,file); + } +#endif +} + +void putsect(uint32_t lba, uint8_t *src) { +#ifdef USB_DISK + uint8_t chksum; + uint16_t i; + uint32_t curmicros; +retrysectput: + Serial.write(0xFF); + Serial.write(0x06); + outByte(lba & 0xFF); chksum = lba & 0xFF; + outByte((lba >> 8) & 0xFF); chksum += (lba >> 8) & 0xFF; + outByte((lba >> 16) & 0xFF); chksum += (lba >> 16) & 0xFF; + outByte((lba >> 24) & 0xFF); chksum += (lba >> 24) & 0xFF; + for (i=0; i<512; i++) { + outByte(src[i]); + chksum += src[i]; + } + outByte(chksum); + Serial.write(0xFE); + Serial.write(0x02); + sectdone = 0; + curmicros = micros(); + while (!sectdone) { + if (micros() < curmicros) curmicros = micros(); + if ((micros() - curmicros) >= 200000) goto retrysectput; + net_loop(); + } +#else + //card.writeBlock(lba, src); +#endif +} +void readdisk(uint8_t drivenum, uint16_t dstseg, uint16_t dstoff, uint16_t cyl, uint16_t sect, uint16_t head, uint16_t sectcount) { + uint32_t memdest, goodsects, dummy, lba; + if ((sect == 0) || !disk[drivenum].inserted) return; +#ifdef MEGA + SPI.setClockDivider(SPI_CLOCK_SDCARD); +#endif + lba = ((long)cyl * (long)disk[drivenum].heads + (long)head) * (long)disk[drivenum].sects + (long)sect - 1; + memdest = (uint32_t)dstseg * 16 + (uint32_t)dstoff; + for (goodsects = 0; goodsects < sectcount; goodsects++) { + getsect(lba, sectorbuffer); + memdest = (uint32_t)dstseg * 16 + (uint32_t)dstoff; + for (dummy = 0; dummy < 512; dummy++) { + write86(memdest++, sectorbuffer[dummy]); + //Serial.write(sectorbuffer[dummy]); + } + dstoff += 512; + lba++; + } + cf = 0; regs.byteregs[regah] = 0; regs.byteregs[regal] = sectcount; +#ifdef MEGA + SPI.setClockDivider(SPI_CLOCK_SPIRAM); +#endif +} + +void writedisk(uint8_t drivenum, uint16_t dstseg, uint16_t dstoff, uint16_t cyl, uint16_t sect, uint16_t head, uint16_t sectcount) { + uint32_t memdest, goodsects, dummy, lba; + if ((sect == 0) || !disk[drivenum].inserted) return; +#ifdef MEGA + SPI.setClockDivider(SPI_CLOCK_SDCARD); +#endif + lba = ((long)cyl * (long)disk[drivenum].heads + (long)head) * (long)disk[drivenum].sects + (long)sect - 1; + for (goodsects = 0; goodsects < sectcount; goodsects++) { + memdest = (uint32_t)dstseg * 16 + (uint32_t)dstoff; + for (dummy = 0; dummy < 512; dummy++) { + sectorbuffer[dummy] = read86(memdest++); + } + //card.erase(lba, lba); + putsect(lba, sectorbuffer); + dstoff += 512; + lba++; + } + cf = 0; regs.byteregs[regah] = 0; regs.byteregs[regal] = sectcount; +#ifdef MEGA + SPI.setClockDivider(SPI_CLOCK_SPIRAM); +#endif +} + +void diskhandler() { + static uint8_t lastdiskah[4], lastdiskcf[4]; + uint8_t drivenum; + drivenum = regs.byteregs[regdl]; + if (drivenum & 0x80) drivenum -= 126; + switch (regs.byteregs[regah]) { + case 0: //reset disk system + regs.byteregs[regah] = 0; cf = 0; //useless function in an emulator. say success and return. + break; + case 1: //return last status + regs.byteregs[regah] = lastdiskah[drivenum]; + cf = lastdiskcf[drivenum]; + return; + case 2: //read sector(s) into memory + if (disk[drivenum].inserted) { + readdisk(drivenum, segregs[reges], getreg16(regbx), (uint16_t)regs.byteregs[regch] + ((uint16_t)regs.byteregs[regcl] / 64) * 256, regs.byteregs[regcl] & 63, regs.byteregs[regdh], regs.byteregs[regal]); + cf = 0; regs.byteregs[regah] = 0; + } else { + cf = 1; + regs.byteregs[regah] = 1; + } + break; + case 3: //write sector(s) from memory + if (disk[drivenum].inserted) { + writedisk(drivenum, segregs[reges], getreg16(regbx), regs.byteregs[regch] + (regs.byteregs[regcl] / 64) * 256, regs.byteregs[regcl] & 63, regs.byteregs[regdh], regs.byteregs[regal]); + cf = 0; regs.byteregs[regah] = 0; + } else { + cf = 1; + regs.byteregs[regah] = 1; + } + break; + case 4: + case 5: //format track + cf = 0; regs.byteregs[regah] = 0; + break; + case 8: //get drive parameters + if (disk[drivenum].inserted) { + cf = 0; regs.byteregs[regah] = 0; + regs.byteregs[regch] = disk[drivenum].cyls - 1; + regs.byteregs[regcl] = disk[drivenum].sects & 63; + regs.byteregs[regcl] = regs.byteregs[regcl] + (disk[drivenum].cyls / 256) * 64; + regs.byteregs[regdh] = disk[drivenum].heads - 1; + //segregs[reges] = 0; regs.wordregs[regdi] = 0x7C0B; //floppy parameter table + if (drivenum < 2) { + regs.byteregs[regbl] = 4; //else regs.byteregs[regbl] = 0; + regs.byteregs[regdl] = 2; + } else regs.byteregs[regdl] = hdcount; + } else { + cf = 1; regs.byteregs[regah] = 0xAA; + } + break; + default: + cf = 1; + } + lastdiskah[drivenum] = regs.byteregs[regah]; + lastdiskcf[drivenum] = cf; + if (regs.byteregs[regdl] & 0x80) write86(0x474, regs.byteregs[regah]); +} + +void initDisk(char * filename) { + int len=0; + if (NULL != (file = fopen(filename, "rb"))) { + fseek(file,0,SEEK_END); + len = ftell(file); + //printf("disk size %d\n",len); + fseek(file,0,SEEK_SET); + + } + + if (len) { + bootdrive = 0x80; + insertdisk(0x80); + hdcount = 1; + } + else { + bootdrive = 0xFF; + fclose(file); + file = NULL; + } +} + diff --git a/MCUME_esp32/esp8086/main/emu.h b/MCUME_esp32/esp8086/main/emu.h new file mode 100755 index 0000000..5c2d1b7 --- /dev/null +++ b/MCUME_esp32/esp8086/main/emu.h @@ -0,0 +1,153 @@ +//Uncomment MEGA define if using a Mega 2560, otherwise leave undefined if using a Teensy 3.6 +//#define MEGA + + + #define RAM_SIZE 655360UL + #define NATIVE_RAM (32768) // 231424UL + #define NATIVE_START 0UL + + + + #define ROM_READ(a,b) a[b] + + +//#define INCLUDE_ROM_BASIC + + +//#define BOOT_FDD +#define BOOT_HDD +//#define BOOT_BASIC + +//#define FDD_180K +//#define FDD_320K +//#define FDD_360K +//#define FDD_720K +//#define FDD_122M +//#define FDD_144M + + +#define BAUD_RATE 1000000 + +//#define USE_NETWORKING +//#define USE_PARALLEL + +//#define PROFILING + +// END ARDUINO86 USER CONFIGURABLE OPTIONS + +#define regax 0 +#define regcx 1 +#define regdx 2 +#define regbx 3 +#define regsp 4 +#define regbp 5 +#define regsi 6 +#define regdi 7 +#define reges 0 +#define regcs 1 +#define regss 2 +#define regds 3 + +#define regal 0 +#define regah 1 +#define regcl 2 +#define regch 3 +#define regdl 4 +#define regdh 5 +#define regbl 6 +#define regbh 7 + +#define StepIP(x) ip+=x +#define getmem8(x,y) read86(segbase(x)+(uint32_t)y) +//#define getmem16(x,y) (read86(segbase(x)+y) | ((uint16_t)read86(segbase(x)+y+1)<<8)) +#define getmem16(x,y) readw86(segbase(x)+(uint32_t)y) +#define putmem8(x,y,z) write86(segbase(x)+(uint32_t)y, z) +//#define putmem16(x,y,z) write86(segbase(x)+y, ((z)&0xFF)); write86(segbase(x)+y+1, (((z)>>8)&0xFF)) +#define putmem16(x,y,z) writew86(segbase(x)+(uint32_t)y, z) +#define signext(value) ((((uint16_t)value&0x80)*0x1FE)|(uint16_t)value) +#define signext32(value) ((((uint32_t)value&0x8000)*0x1FFFE)|(uint32_t)value) +#define getreg16(regid) regs.wordregs[regid] +#define getreg8(regid) regs.byteregs[byteregtable[regid]] +#define putreg16(regid, writeval) regs.wordregs[regid] = writeval +#define putreg8(regid, writeval) regs.byteregs[byteregtable[regid]] = writeval +#define getsegreg(regid) segregs[regid] +#define putsegreg(regid, writeval) segregs[regid] = writeval +#define segbase(x) ((uint32_t)x<<4) + +#define makeflagsword() (2 | (uint16_t)cf | ((uint16_t)pf << 2) | ((uint16_t)af << 4) | ((uint16_t)zf << 6) \ + | ((uint16_t)sf << 7) | ((uint16_t)tf << 8) | ((uint16_t)ifl << 9) | ((uint16_t)df << 10) | ((uint16_t)of << 11)) + +#define decodeflagsword(x) {\ + temp16 = x;\ + cf = temp16 & 1;\ + pf = (temp16 >> 2) & 1;\ + af = (temp16 >> 4) & 1;\ + zf = (temp16 >> 6) & 1;\ + sf = (temp16 >> 7) & 1;\ + tf = (temp16 >> 8) & 1;\ + ifl = (temp16 >> 9) & 1;\ + df = (temp16 >> 10) & 1;\ + of = (temp16 >> 11) & 1;\ +} + + + +//#define RAM_write(a,v) { +//} + +//#define RAM_read(a,v) { +//} + + +void setup_memory(); +void setup_timer(); +uint8_t insertdisk(uint8_t drivenum); +void reset86(); +void exec86(uint32_t execloops); +uint8_t read86(uint32_t addr32); +void write86(uint32_t addr32, uint8_t value); +void doirq(uint8_t irqnum); +void incsends(); +void init_display(); +void write_video(uint16_t addr); +void clear_display(); +void palettereset(); +void display_CSIP(); +void ps2poll(); +void setup_ps2(uint8_t data_pin, uint8_t irq_pin); +void video_init(); +uint8_t VRAM_read(uint32_t addr32); +void VRAM_write(uint32_t addr32, uint8_t value); +void setup_ps2(uint8_t data_pin, uint8_t irq_pin); +void ps2poll(); +void out8253 (uint16_t portnum, uint8_t value); +uint8_t in8253 (uint16_t portnum); +void init8259(); +void out8259(uint16_t portnum, uint8_t value); +uint8_t in8259(uint16_t portnum); + +extern uint8_t port3da; + +void initDisk(char * filename); +void init8253(); +void net_init(); +void net_loop(); +void net_handler(); +uint8_t cached_read(uint32_t addr32); +void cached_write(uint32_t addr32, uint8_t value); +void cache_init(); + +uint8_t net_read_ram(uint32_t addr32); +void diskhandler(); + +//extern uint8_t SPI_RAM_pins[8]; +extern uint8_t net_mac[6]; +extern uint8_t bufSerial[1600]; +void outByte(uint8_t cc); + +extern struct i8253_s i8253; +union _bytewordregs_{ + uint16_t wordregs[8]; + uint8_t byteregs[8]; +} ; + diff --git a/MCUME_esp32/esp8086/main/emuapi.cpp b/MCUME_esp32/esp8086/main/emuapi.cpp new file mode 100644 index 0000000..50014ff --- /dev/null +++ b/MCUME_esp32/esp8086/main/emuapi.cpp @@ -0,0 +1,1112 @@ +#define KEYMAP_PRESENT 1 + +#include +#include +#include +#include + +extern "C" { + #include "emuapi.h" + #include "iopins.h" +} + +#include "ili9341_t3dma.h" +//#include "logo.h" +#include "bmpjoy.h" +#include "bmpvbar.h" + +#include "esp_event.h" +#include "esp_vfs_fat.h" +#include "driver/sdspi_host.h" +#include +#include +#include + +#ifdef HAS_I2CKBD +#ifdef USE_WIRE +#include "Wire.h" +#else +#include +#define ACK_CHECK_EN 0x1 /*!< I2C master will check ack from slave*/ +#define ACK_CHECK_DIS 0x0 /*!< I2C master will not check ack from slave */ +#define ACK_VAL 0x0 /*!< I2C ack value */ +#define NACK_VAL 0x1 /*!< I2C nack value */ +#endif + +#define I2C_FREQ_HZ 400000 /*!< I2C master clock frequency */ +static bool i2cKeyboardPresent = false; +#endif + + +extern ILI9341_t3DMA tft; + +static char romspath[64]; +static int calMinX=-1,calMinY=-1,calMaxX=-1,calMaxY=-1; +static sdmmc_card_t* card; +const uint16_t deflogo[] = { + 0x0000,0x0000 +}; +static const uint16_t * logo = deflogo; + +#define CALIBRATION_FILE "/sdcard/cal.cfg" + +#define MAX_FILENAME_SIZE 28 +#define MAX_MENULINES (MKEY_L9) +#define TEXT_HEIGHT 16 +#define TEXT_WIDTH 8 +#define MENU_FILE_XOFFSET (6*TEXT_WIDTH) +#define MENU_FILE_YOFFSET (2*TEXT_HEIGHT) +#define MENU_FILE_W (MAX_FILENAME_SIZE*TEXT_WIDTH) +#define MENU_FILE_H (MAX_MENULINES*TEXT_HEIGHT) +#define MENU_FILE_FGCOLOR RGBVAL16(0xff,0xff,0xff) +#define MENU_FILE_BGCOLOR RGBVAL16(0x00,0x00,0x20) +#define MENU_JOYS_YOFFSET (12*TEXT_HEIGHT) +#define MENU_VBAR_XOFFSET (0*TEXT_WIDTH) +#define MENU_VBAR_YOFFSET (MENU_FILE_YOFFSET) + + +#define MKEY_L1 1 +#define MKEY_L2 2 +#define MKEY_L3 3 +#define MKEY_L4 4 +#define MKEY_L5 5 +#define MKEY_L6 6 +#define MKEY_L7 7 +#define MKEY_L8 8 +#define MKEY_L9 9 +#define MKEY_UP 20 +#define MKEY_DOWN 21 +#define MKEY_JOY 22 + + +const unsigned short menutouchareas[] = { + TAREA_XY,MENU_FILE_XOFFSET,MENU_FILE_YOFFSET, + TAREA_WH,MENU_FILE_W, TEXT_HEIGHT, + TAREA_NEW_COL,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT, + + TAREA_XY,MENU_VBAR_XOFFSET,MENU_VBAR_YOFFSET, + TAREA_WH,32,48, + TAREA_NEW_COL, 72,72,8,40, + + TAREA_END}; + +const unsigned short menutouchactions[] = { + MKEY_L1,MKEY_L2,MKEY_L3,MKEY_L4,MKEY_L5,MKEY_L6,MKEY_L7,MKEY_L8,MKEY_L9, + MKEY_UP,MKEY_DOWN,ACTION_NONE,MKEY_JOY}; + + +static bool menuOn=true; +static bool callibrationOn=false; +static int callibrationStep=0; +static bool menuRedraw=true; +static int nbFiles=0; +static int curFile=0; +static int topFile=0; +static char selection[MAX_FILENAME_SIZE+1]=""; +static uint8_t prev_zt=0; + +static int readNbFiles(void) { + int totalFiles = 0; + + DIR* dir = opendir(romspath); + while (true) { + struct dirent* de = readdir(dir); + if (!de) { + // no more files + break; + } + if (de->d_type == DT_REG) { + totalFiles++; + } + else if (de->d_type == DT_DIR) { + if ( (strcmp(de->d_name,".")) && (strcmp(de->d_name,"..")) ) { + totalFiles++; + } + } + } + closedir(dir); + return totalFiles; +} + +static char captureTouchZone(const unsigned short * areas, const unsigned short * actions, int *rx, int *ry, int *rw, int * rh) { + uint16_t xt=0; + uint16_t yt=0; + uint16_t zt=0; + bool hDir=true; + + if (tft.isTouching()) + { + if (prev_zt == 0) { + prev_zt =1; + tft.readCal(&xt,&yt,&zt); + if (zt<1000) { + prev_zt=0; + return ACTION_NONE; + } + int i=0; + int k=0; + int y2=0, y1=0; + int x2=0, x1=0; + int x=KEYBOARD_X,y=KEYBOARD_Y; + int w=TAREA_W_DEF,h=TAREA_H_DEF; + uint8_t s; + while ( (s=areas[i++]) != TAREA_END ) { + if (s == TAREA_XY) { + x = areas[i++]; + y = areas[i++]; + x2 = x; + y2 = y; + } + else if (s == TAREA_WH) { + w = areas[i++]; + h = areas[i++]; + } + else if (s == TAREA_NEW_ROW) { + hDir = true; + y1 = y2; + y2 = y1 + h; + x2 = x; + } + else if (s == TAREA_NEW_COL) { + hDir = false; + x1 = x2; + x2 = x1 + w; + y2 = y; + } + else { + if (hDir) { + x1 = x2; + x2 = x1+s; + } else { + y1 = y2; + y2 = y1+s; + } + if ( (yt >= y1) && (yt < y2) && (xt >= x1) && (xt < x2) ) { + *rx = x1; + *ry = y1; + *rw = x2-x1; + *rh = y2-y1; + return (actions[k]); + } + k++; + } + } + } + prev_zt =1; + } else { + prev_zt=0; + } + + return ACTION_NONE; +} + +void toggleMenu(bool on) { + if (on) { + callibrationOn=false; + menuOn=true; + menuRedraw=true; + tft.fillScreenNoDma(RGBVAL16(0x00,0x00,0x00)); + tft.drawTextNoDma(0,0, TITLE, RGBVAL16(0x00,0xff,0xff), RGBVAL16(0x00,0x00,0xff), true); + tft.drawSpriteNoDma(MENU_VBAR_XOFFSET,MENU_VBAR_YOFFSET,(uint16_t*)bmpvbar); + } else { + menuOn = false; + } +} + + +static void callibrationInit(void) +{ + callibrationOn=true; + menuOn=false; + callibrationStep = 0; + calMinX=0,calMinY=0,calMaxX=0,calMaxY=0; + tft.fillScreenNoDma(RGBVAL16(0xff,0xff,0xff)); + tft.drawTextNoDma(0,100, " Callibration process:", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,116, " Hit the red cross at each corner", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,0, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + prev_zt = 1; +} + +static void readCallibration(void) +{ + FILE * file = fopen(CALIBRATION_FILE, "rb"); + if (file) { + fscanf(file,"%d %d %d %d\n",&calMinX,&calMinY,&calMaxX,&calMaxY); + fclose(file); + printf("Current callibration params: %d %d %d %d\n",calMinX,calMinY,calMaxX,calMaxY); + } + else { + printf("Callibration read error\n"); + } + tft.callibrateTouch(calMinX,calMinY,calMaxX,calMaxY); +} + +static void writeCallibration(void) +{ + tft.callibrateTouch(calMinX,calMinY,calMaxX,calMaxY); + FILE * file = fopen(CALIBRATION_FILE, "wb"); + if (file) { + fprintf(file,"%d %d %d %d\n",calMinX,calMinY,calMaxX,calMaxY); + fclose(file); + } + else { + printf("Callibration write error\n"); + } +} + + +bool callibrationActive(void) +{ + return (callibrationOn); +} + + + +int handleCallibration(uint16_t bClick) { + uint16_t xt=0; + uint16_t yt=0; + uint16_t zt=0; + if (tft.isTouching()) { + if (prev_zt == 0) { + prev_zt = 1; + tft.readRaw(&xt,&yt,&zt); + if (zt < 1000) { + return 0; + } + switch (callibrationStep) + { + case 0: + callibrationStep++; + tft.drawTextNoDma(0,0, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(ILI9341_TFTREALWIDTH-8,0, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMinX += xt; + calMinY += yt; + break; + case 1: + callibrationStep++; + tft.drawTextNoDma(ILI9341_TFTREALWIDTH-8,0, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(ILI9341_TFTREALWIDTH-8,ILI9341_TFTREALHEIGHT-16, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMaxX += xt; + calMinY += yt; + break; + case 2: + callibrationStep++; + tft.drawTextNoDma(ILI9341_TFTREALWIDTH-8,ILI9341_TFTREALHEIGHT-16, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,ILI9341_TFTREALHEIGHT-16, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMaxX += xt; + calMaxY += yt; + break; + case 3: + tft.fillScreenNoDma(RGBVAL16(0xff,0xff,0xff)); + tft.drawTextNoDma(0,100, " Callibration done!", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,116, " (Click center to exit)", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + callibrationStep++; + calMinX += xt; + calMaxY += yt; + break; + case 4: + if ( (xt > (ILI9341_TFTREALWIDTH/4)) && (xt < (ILI9341_TFTREALWIDTH*3)/4) + && (yt > (ILI9341_TFTREALHEIGHT/4)) && (yt < (ILI9341_TFTREALHEIGHT*3)/4) ) { + calMinX /= 2; + calMinY /= 2; + calMaxX /= 2; + calMaxY /= 2; + writeCallibration(); + toggleMenu(true); + } + else { + callibrationInit(); + } + break; + + } + vTaskDelay(100 / portTICK_PERIOD_MS); + } + } + else { + prev_zt = 0; + } + return 1; +} + + + +bool menuActive(void) +{ + return (menuOn); +} + +int handleMenu(uint16_t bClick) +{ + int action = ACTION_NONE; + + char newpath[80]; + strcpy(newpath, romspath); + strcat(newpath, "/"); + strcat(newpath, selection); + + struct stat st; + bool newPathIsDir = false; + if(stat(newpath,&st) == 0) + if((st.st_mode & S_IFDIR) != 0) + newPathIsDir = true; + + int rx=0,ry=0,rw=0,rh=0; + char c = captureTouchZone(menutouchareas, menutouchactions, &rx,&ry,&rw,&rh); + if ( ( (bClick & MASK_JOY2_BTN) || (bClick & MASK_KEY_USER1) ) && (newPathIsDir) ) { + menuRedraw=true; + strcpy(romspath,newpath); + curFile = 0; + nbFiles = readNbFiles(); + } + else if ( (c >= MKEY_L1) && (c <= MKEY_L9) ) { + if ( (topFile+(int)c-1) <= (nbFiles-1) ) + { + curFile = topFile + (int)c -1; + menuRedraw=true; + //tft.drawRectNoDma( rx,ry,rw,rh, KEYBOARD_HIT_COLOR ); + } + } + else if ( (bClick & MASK_JOY2_BTN) ) { + menuRedraw=true; + action = ACTION_RUNTFT; + } + else if (bClick & MASK_JOY2_UP) { + if (curFile!=0) { + menuRedraw=true; + curFile--; + } + } + else if ( (bClick & MASK_JOY2_RIGHT) || (c == MKEY_UP) ) { + if ((curFile-9)>=0) { + menuRedraw=true; + curFile -= 9; + } else if (curFile!=0) { + menuRedraw=true; + curFile--; + } + } + else if (bClick & MASK_JOY2_DOWN) { + if ((curFile<(nbFiles-1)) && (nbFiles)) { + curFile++; + menuRedraw=true; + } + } + else if ( (bClick & MASK_JOY2_LEFT) || (c == MKEY_DOWN) ) { + if ((curFile<(nbFiles-9)) && (nbFiles)) { + curFile += 9; + menuRedraw=true; + } + else if ((curFile<(nbFiles-1)) && (nbFiles)) { + curFile++; + menuRedraw=true; + } + } + else if ( (bClick & MASK_KEY_USER1) || (c == MKEY_JOY) ) { + emu_SwapJoysticks(0); + menuRedraw=true; + } + + + if (menuRedraw && nbFiles) { + + int fileIndex = 0; + DIR* dir = opendir(romspath); + tft.drawRectNoDma(MENU_FILE_XOFFSET,MENU_FILE_YOFFSET, MENU_FILE_W, MENU_FILE_H, MENU_FILE_BGCOLOR); +// if (curFile <= (MAX_MENULINES/2-1)) topFile=0; +// else topFile=curFile-(MAX_MENULINES/2); + if (curFile <= (MAX_MENULINES-1)) topFile=0; + else topFile=curFile-(MAX_MENULINES/2); + + int i=0; + while (id_type == DT_REG) || ((de->d_type == DT_DIR) && (strcmp(de->d_name,".")) && (strcmp(de->d_name,"..")) ) ) { + if (fileIndex >= topFile) { + if ((i+topFile) < nbFiles ) { + if ((i+topFile)==curFile) { + tft.drawTextNoDma(MENU_FILE_XOFFSET,i*TEXT_HEIGHT+MENU_FILE_YOFFSET, de->d_name, RGBVAL16(0xff,0xff,0x00), RGBVAL16(0xff,0x00,0x00), true); + strcpy(selection,de->d_name); + } + else { + tft.drawTextNoDma(MENU_FILE_XOFFSET,i*TEXT_HEIGHT+MENU_FILE_YOFFSET, de->d_name, MENU_FILE_FGCOLOR, MENU_FILE_BGCOLOR, true); + } + } + i++; + } + fileIndex++; + } + } + closedir(dir); + + tft.drawSpriteNoDma(0,MENU_JOYS_YOFFSET,(uint16_t*)bmpjoy); + tft.drawTextNoDma(48,MENU_JOYS_YOFFSET+8, (emu_SwapJoysticks(1)?(char*)"SWAP=1":(char*)"SWAP=0"), RGBVAL16(0x00,0xff,0xff), RGBVAL16(0xff,0x00,0x00), false); + + menuRedraw=false; + } + + + return (action); +} + +char * menuSelection(void) +{ + static char nnewpath[80]; + strcpy(nnewpath, romspath); + strcat(nnewpath, "/"); + strcat(nnewpath, selection); + return (nnewpath); +} + +#ifdef HAS_I2CKBD +#ifdef USE_WIRE +#else +static esp_err_t i2c_master_read_slave_reg(i2c_port_t i2c_num, uint8_t i2c_addr, uint8_t* data_rd, size_t size) +{ + if (size == 0) { + return ESP_OK; + } + i2c_cmd_handle_t cmd = i2c_cmd_link_create(); + i2c_master_start(cmd); + i2c_master_write_byte(cmd, ( i2c_addr << 1 ) | I2C_MASTER_READ, ACK_CHECK_EN); + if (size > 1) { + i2c_master_read(cmd, data_rd, size - 1, (i2c_ack_type_t)ACK_VAL); + } + i2c_master_read_byte(cmd, data_rd + size - 1, (i2c_ack_type_t)NACK_VAL); + i2c_master_stop(cmd); + esp_err_t ret = i2c_master_cmd_begin(i2c_num, cmd, 1000 / portTICK_RATE_MS); + i2c_cmd_link_delete(cmd); + return ret; +} +#endif +#endif + + +void emu_init(void) +{ + + esp_err_t ret = 0; + + printf("mounting sd...\n"); + + sdmmc_host_t host = SDSPI_HOST_DEFAULT(); + host.max_freq_khz = 10000; + //host.slot = HSPI_HOST; + + sdspi_slot_config_t slot_config = SDSPI_SLOT_CONFIG_DEFAULT(); + slot_config.gpio_miso = SPIN_NUM_MISO; + slot_config.gpio_mosi = SPIN_NUM_MOSI; + slot_config.gpio_sck = SPIN_NUM_CLK; + slot_config.gpio_cs = SPIN_NUM_CS; + slot_config.dma_channel = 2; + + + esp_vfs_fat_sdmmc_mount_config_t mount_config = { + .format_if_mount_failed = false, + .max_files = 5, + .allocation_unit_size = 16 * 1024 + }; + + + + while((ret = esp_vfs_fat_sdmmc_mount("/sdcard", &host, &slot_config, &mount_config, &card)) != ESP_OK) { + printf("retrying\n"); + vTaskDelay(500 / portTICK_PERIOD_MS); + } + + strcpy(romspath,"/sdcard/"); + strcat(romspath,ROMSDIR); + printf("dir is : %s\n",romspath); + + nbFiles = readNbFiles(); + printf("SD initialized, files found: %d\n",nbFiles); + +/* + tft.touchBegin(); +*/ + + + emu_InitJoysticks(); +/* + readCallibration(); + + if ((tft.isTouching()) || (emu_ReadKeys() & MASK_JOY2_BTN) ) { + callibrationInit(); + } else { +*/ + toggleMenu(true); +/* + } +*/ + +#ifdef HAS_I2CKBD + uint8_t msg[7]={0,0,0,0,0,0,0}; + +#ifdef USE_WIRE + Wire.begin(I2C_SDA_IO, I2C_SCL_IO); + Wire.requestFrom(8, 7, I2C_FREQ_HZ); // request 5 bytes from slave device #8 + int i = 0; + int hitindex=-1; + while (Wire.available() && (i<7) ) { // slave may send less than requested + uint8_t b = Wire.read(); // receive a byte + if (b != 0xff) hitindex=i; + msg[i++] = b; + } +#else + int i2c_master_port = I2C_NUM_1; + i2c_config_t conf; + conf.mode = I2C_MODE_MASTER; + conf.sda_io_num = I2C_SDA_IO; + conf.sda_pullup_en = GPIO_PULLUP_ENABLE; + conf.scl_io_num = I2C_SCL_IO; + conf.scl_pullup_en = GPIO_PULLUP_ENABLE; + conf.master.clk_speed = I2C_FREQ_HZ; + i2c_param_config((i2c_port_t)i2c_master_port, &conf); + if (i2c_driver_install((i2c_port_t)i2c_master_port, conf.mode,0, 0, 0) != ESP_OK) + printf("I2C Failed initialized\n"); + + if (i2c_master_read_slave_reg( I2C_NUM_1, 8, &msg[0], 7 ) != ESP_OK) + printf("I2C Failed \n"); +#endif + + + + + if ( (msg[0] == 0xff) && (msg[1] == 0xff) && + (msg[2] == 0xff) && (msg[3] == 0xff) && + (msg[4] == 0xff) && (msg[5] == 0xff) && (msg[6] == 0xff)) { + i2cKeyboardPresent = true; + printf("i2C keyboard found\n"); + } + +#endif +} + + +void emu_printf(char * text) +{ + printf("%s\n",text); +} + + +void emu_printi(int val) +{ + printf("%d\n",val); +} + +void * emu_Malloc(int size) +{ + void * retval = malloc(size); + if (!retval) { + printf("failled to allocate %d\n",size); + } + else { + printf("could allocate %d\n",size); + } + + return retval; +} + +void emu_Free(void * pt) +{ + free(pt); +} + + +static FILE * lastfileOpened; + + +int emu_FileOpen(char * filename) +{ + int retval = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + //printf("FileOpen...%s\n",filepath); + + lastfileOpened = fopen(filepath, "rb"); + if (lastfileOpened) { + retval = 1; + } + else { + //printf("FileOpen failed\n"); + } + return (retval); +} + +int emu_FileRead(char * buf, int size) +{ + int retval = fread(buf, 1, size, lastfileOpened); + if (retval != size) { + printf("FileRead failed\n"); + } + return (retval); +} + +unsigned char emu_FileGetc(void) { + unsigned char c; + int retval = fread(&c, 1, 1, lastfileOpened); + if (retval != 1) { + printf("emu_FileGetc failed\n"); + } + return c; +} + + +void emu_FileClose(void) +{ + fclose(lastfileOpened); +} + +int emu_FileSize(char * filename) +{ + int filesize=0; + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + printf("FileSize...%s\n",filepath); + + FILE * file = fopen(filepath, "rb"); + if (file) { + fseek(file, 0L, SEEK_END); + filesize = ftell(file); + //fseek(file, 0L, SEEK_SET); + printf("filesize is...%d\n",filesize); + fclose(file); + } + + return(filesize); +} + +int emu_FileSeek(int seek) +{ + fseek(lastfileOpened, seek, SEEK_SET); + return (seek); +} + +int emu_LoadFile(char * filename, char * buf, int size) +{ + int filesize = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + printf("LoadFile...%s\n",filepath); + + filesize = emu_FileSize(filename); + FILE * file = fopen(filepath, "rb"); + if (file) { + if (size >= filesize) + { + if (fread(buf, 1, filesize, file) != filesize) { + printf("File read failed\n"); + } + } + fclose(file); + } + + return(filesize); +} + +int emu_LoadFileSeek(char * filename, char * buf, int size, int seek) +{ + int filesize = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + printf("LoadFileSeek...%d bytes at %d from %s\n",size,seek,filepath); + + FILE * file = fopen(filepath, "rb"); + if (file) { + fseek(file, seek, SEEK_SET); + if (fread(buf, size, 1, file) != size) { + printf("File read failed\n"); + } + fclose(file); + } + + return(filesize); +} + +static int keypadval=0; +static bool joySwapped = false; +static uint16_t bLastState; +static int xRef; +static int yRef; + +int emu_ReadAnalogJoyX(int min, int max) +{ + int val; //adc1_get_raw((adc1_channel_t)PIN_JOY2_A1X); + adc2_get_raw((adc2_channel_t)PIN_JOY2_A1X, ADC_WIDTH_BIT_12,&val); + //printf("refX:%d X:%d\n",xRef,val); + val = val-xRef; + //val = ((val*140)/100); + if ( (val > -xRef/4) && (val < xRef/4) ) val = 0; +#if INVX + val = xRef-val; +#else + val = val+xRef; +#endif + + return (val*(max-min))/(xRef*2); +} + +int emu_ReadAnalogJoyY(int min, int max) +{ + int val; //= adc1_get_raw((adc1_channel_t)PIN_JOY2_A2Y); + adc2_get_raw((adc2_channel_t)PIN_JOY2_A2Y, ADC_WIDTH_BIT_12,&val); + //printf("refY:%d Y:%d\n",yRef,val); + val = val-yRef; + //val = ((val*120)/100); + if ( (val > -yRef/4) && (val < yRef/4) ) val = 0; +#if INVY + val = yRef-val; +#else + val = val+yRef; +#endif + return (val*(max-min))/(yRef*2); +} + + +static uint16_t readAnalogJoystick(void) +{ + uint16_t joysval = 0; + + int xReading = emu_ReadAnalogJoyX(0,256); + if (xReading > 128) joysval |= MASK_JOY2_LEFT; + else if (xReading < 128) joysval |= MASK_JOY2_RIGHT; + + int yReading = emu_ReadAnalogJoyY(0,256); + if (yReading < 128) joysval |= MASK_JOY2_UP; + else if (yReading > 128) joysval |= MASK_JOY2_DOWN; + +#ifdef PIN_JOY2_BTN + joysval |= ((gpio_get_level((gpio_num_t)PIN_JOY2_BTN) == 1) ? 0 : MASK_JOY2_BTN); +#endif + + return (joysval); +} + + +int emu_SwapJoysticks(int statusOnly) { + if (!statusOnly) { + if (joySwapped) { + joySwapped = false; + } + else { + joySwapped = true; + } + } + return(joySwapped?1:0); +} + +int emu_GetPad(void) +{ + return(keypadval|((joySwapped?1:0)<<7)); +} + +int emu_ReadKeys(void) +{ + uint16_t retval; + uint16_t j1 = readAnalogJoystick(); + + uint16_t j2 = 0; + + if (joySwapped) { + retval = ((j1 << 8) | j2); + } + else { + retval = ((j2 << 8) | j1); + } + +#ifdef PIN_KEY_USER1 + if (gpio_get_level((gpio_num_t)PIN_KEY_USER1) == 0 ) retval |= MASK_KEY_USER1; +#endif +#ifdef PIN_KEY_USER2 + if (gpio_get_level((gpio_num_t)PIN_KEY_USER2) == 0 ) retval |= MASK_KEY_USER2; +#endif +#ifdef PIN_KEY_USER3 + if (gpio_get_level((gpio_num_t)PIN_KEY_USER3) == 0 ) retval |= MASK_KEY_USER3; +#endif +#ifdef PIN_KEY_USER4 + if (gpio_get_level((gpio_num_t)PIN_KEY_USER4) == 0 ) retval |= MASK_KEY_USER4; +#endif + + //printf("%d\n",retval); + return (retval); +} + +unsigned short emu_DebounceLocalKeys(void) +{ + uint16_t bCurState = emu_ReadKeys(); + uint16_t bClick = bCurState & ~bLastState; + bLastState = bCurState; + + return (bClick); +} + + +int emu_ReadI2CKeyboard(void) { + int retval=0; +#ifdef HAS_I2CKBD + if (i2cKeyboardPresent) { + uint8_t msg[7]; +#ifdef USE_WIRE + Wire.requestFrom(8, 7, I2C_FREQ_HZ); // request 5 bytes from slave device #8 + int i = 0; + int hitindex=-1; + while (Wire.available() && (i<7) ) { // slave may send less than requested + uint8_t b = Wire.read(); // receive a byte + if (b != 0xff) hitindex=i; + msg[i++] = b; + } +#else + if (i2c_master_read_slave_reg( I2C_NUM_1, 8, &msg[0], 7 ) != ESP_OK) + printf("I2C Failed \n"); + int hitindex=-1; + int i = 0; + while (i<7) { + if (msg[i] != 0xff) hitindex=i; + i++; + } +#endif + //printf("I2C 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X\n", + // msg[0],msg[1],msg[2],msg[3],msg[4],msg[5],msg[6]); + if ((hitindex >=0 ) && (hitindex <=6 )) { + unsigned short match = ((~msg[hitindex])&0x00FF) | (hitindex<<8); + for (i=0; i=1) && (c <= ACTION_MAXKBDVAL) ) { + keypadval = c; + keyPressCount = 10; + vTaskDelay(50 / portTICK_PERIOD_MS); + vkeyRefresh = true; + exitVkbd = true; + } + else if (c == ACTION_EXITKBD) { + vkeyRefresh = true; + exitVkbd = true; + } + } + } + + if (vkeyRefresh) { + vkeyRefresh = false; + tft.drawSpriteNoDma(0,0,(uint16_t*)logo, rx, ry, rw, rh); + } + + if ( (exitVkbd) && (vkbActive) ) { + if (!vkbKeepOn) { + toggleVirtualkeyboard(false); + } + else { + toggleVirtualkeyboard(true); + } + } +} + +int emu_setKeymap(int index) { + if (index) { + //logo = ; + //keysw = ; + } + else { + //logo = ; + //keysw = ; + } + return 0; +} + + + +static unsigned short palette16[PALETTE_SIZE]; +static int fskip=0; + +void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index) +{ + if (index +#define TITLE " 8086 Emulator " +#define ROMSDIR "pc" + +#define emu_Init(ROM) {mac_Init(); mac_Start(ROM); } +#define emu_Step(x) { mac_Step(); } +#define emu_Input(x) { mac_Input(x); } + +#define VID_FRAME_SKIP 0x0 +#define PALETTE_SIZE 256 +#define SINGLELINE_RENDERING 1 +#define TFT_VBUFFER_YCROP 0 + +#define ACTION_NONE 0 +#define ACTION_MAXKBDVAL 225 +#define ACTION_EXITKBD 128 +#define ACTION_RUNTFT 129 + +#ifdef KEYMAP_PRESENT + +#define TAREA_W_DEF 32 +#define TAREA_H_DEF 32 +#define TAREA_END 255 +#define TAREA_NEW_ROW 254 +#define TAREA_NEW_COL 253 +#define TAREA_XY 252 +#define TAREA_WH 251 + +#define KEYBOARD_X 16 +#define KEYBOARD_Y 32 +#define KEYBOARD_KEY_H 30 +#define KEYBOARD_KEY_W 28 +#define KEYBOARD_HIT_COLOR RGBVAL16(0xff,0x00,0x00) + +const unsigned short keysw[]= +{ TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + //TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_END}; + +const unsigned short keys[]={ +'1','2','3','4','5','6','7','8','9',0xFF09, +'Q','W','E','R','T','Y','U','I','O','P', +'A','S','D','F','G','H','J','K','L', 0xFF0D, +'Z','X','C','V','B','N','M',',','.',' ' }; + + + + +#ifdef HAS_I2CKBD +const unsigned short i2ckeys[] = { + 0X0080,0X0008,0X0180,0X0108,0X0280,0X0208,0X0380,0X0308,0X0480,0X0408, + 0X0040,0X0004,0X0140,0X0104,0X0240,0X0204,0X0340,0X0304,0X0440,0X0404, + 0X0020,0X0002,0X0120,0X0102,0X0220,0X0202,0X0320,0X0302,0X0420,0X0402, + 0X0010,0X0001,0X0110,0X0101,0X0210,0X0201,0X0310,0X0301,0X0410,0X0401 }; + //0X0580,0X0540,0X0520,0X0510,0X0508,0X0504,0X0502,0X0501,0X0680,0X0640 }; +#endif + +#endif + +#define MASK_JOY2_RIGHT 0x0001 +#define MASK_JOY2_LEFT 0x0002 +#define MASK_JOY2_UP 0x0004 +#define MASK_JOY2_DOWN 0x0008 +#define MASK_JOY2_BTN 0x0010 +#define MASK_KEY_USER1 0x0020 +#define MASK_KEY_USER2 0x0040 +#define MASK_KEY_USER3 0x0080 +#define MASK_JOY1_RIGHT 0x0100 +#define MASK_JOY1_LEFT 0x0200 +#define MASK_JOY1_UP 0x0400 +#define MASK_JOY1_DOWN 0x0800 +#define MASK_JOY1_BTN 0x1000 +#define MASK_KEY_USER4 0x2000 + + +extern void emu_init(void); +extern void emu_printf(char * text); +extern void emu_printi(int val); +extern void * emu_Malloc(int size); +extern void emu_Free(void * pt); + +extern int emu_FileOpen(char * filename); +extern int emu_FileRead(char * buf, int size); +extern unsigned char emu_FileGetc(void); +extern int emu_FileSeek(int seek); +extern void emu_FileClose(void); +extern int emu_FileSize(char * filename); +extern int emu_LoadFile(char * filename, char * buf, int size); +extern int emu_LoadFileSeek(char * filename, char * buf, int size, int seek); + +extern void emu_InitJoysticks(void); +extern int emu_SwapJoysticks(int statusOnly); +extern unsigned short emu_DebounceLocalKeys(void); +extern int emu_ReadKeys(void); +extern int emu_GetPad(void); +extern int emu_ReadAnalogJoyX(int min, int max); +extern int emu_ReadAnalogJoyY(int min, int max); +extern int emu_ReadI2CKeyboard(void); +extern int emu_setKeymap(int index); + +extern void emu_sndInit(); +extern void emu_sndPlaySound(int chan, int volume, int freq); +extern void emu_sndPlayBuzz(int size, int val); + +extern void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index); +extern void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride); +extern void emu_DrawLine(unsigned char * VBuf, int width, int height, int line); +extern void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line); +extern void emu_DrawVsync(void); +extern int emu_FrameSkip(void); + + +#endif + + + + diff --git a/MCUME_esp32/esp8086/main/emul.cpp b/MCUME_esp32/esp8086/main/emul.cpp new file mode 100644 index 0000000..c420dd4 --- /dev/null +++ b/MCUME_esp32/esp8086/main/emul.cpp @@ -0,0 +1,620 @@ +#include +#include +#include +#include +extern "C" { +#include "emuapi.h" +} +#include "emu.h" +#include "ps2.h" + + + +uint8_t * RAM; +uint8_t * LORAM; //LORAM[NATIVE_RAM]; + + + + + + +#define PALMULT8(x) ((x)<<5) +#define RGBVAL16(r,g,b) ( (((r>>3)&0x1f)<<11) | (((g>>2)&0x3f)<<5) | (((b>>3)&0x1f)<<0) ) + + + + + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#include "esp_system.h" + + + +struct i8253_s { + uint16_t chandata[3]; + uint8_t accessmode[3]; + uint8_t bytetoggle[3]; + uint32_t effectivedata[3]; + float chanfreq[3]; + uint8_t active[3]; + uint16_t counter[3]; +}; + +extern struct i8253_s i8253; + +void doirq(uint8_t irqnum); +void write86(uint32_t addr32, uint8_t value); +uint8_t read86(uint32_t addr32); + +uint8_t curkey = 0; + + + +uint8_t VRAM[16384]; + + +uint32_t updateaddrs[64]; +uint8_t updatepos = 0; + +void VRAM_write(uint32_t addr32, uint8_t value) { + + if (addr32 < 16384) { + VRAM[addr32] = value; + +//printf("%d %d\n",addr32,value); + } +} + +uint8_t VRAM_read(uint32_t addr32) { + + if (addr32 < 16384) return VRAM[addr32]; + return 0; +} + +uint8_t ansicolor[16] = { 0, 4, 2, 6, 1, 5, 3, 7, 0, 4, 2, 6, 1, 5, 3, 7 }; +uint16_t palettecga[16], palettevga[256]; + + +void installPalette(void) { + palettecga[0] = RGBVAL16(0, 0, 0); + palettecga[1] = RGBVAL16(0, 0, 0xAA); + palettecga[2] = RGBVAL16(0, 0xAA, 0); + palettecga[3] = RGBVAL16(0, 0xAA, 0xAA); + palettecga[4] = RGBVAL16(0xAA, 0, 0); + palettecga[5] = RGBVAL16(0xAA, 0, 0xAA); + palettecga[6] = RGBVAL16(0xAA, 0x55, 0); + palettecga[7] = RGBVAL16(0xAA, 0xAA, 0xAA); + palettecga[8] = RGBVAL16(0x55, 0x55, 0x55); + palettecga[9] = RGBVAL16(0x55, 0x55, 0xFF); + palettecga[10] = RGBVAL16(0x55, 0xFF, 0x55); + palettecga[11] = RGBVAL16(0x55, 0xFF, 0xFF); + palettecga[12] = RGBVAL16(0xFF, 0x55, 0x55); + palettecga[13] = RGBVAL16(0xFF, 0x55, 0xFF); + palettecga[14] = RGBVAL16(0xFF, 0xFF, 0x55); + palettecga[15] = RGBVAL16(0xFF, 0xFF, 0xFF); + palettevga[0] = RGBVAL16(0, 0, 0); + palettevga[1] = RGBVAL16(0, 0, 169); + palettevga[2] = RGBVAL16(0, 169, 0); + palettevga[3] = RGBVAL16(0, 169, 169); + palettevga[4] = RGBVAL16(169, 0, 0); + palettevga[5] = RGBVAL16(169, 0, 169); + palettevga[6] = RGBVAL16(169, 169, 0); + palettevga[7] = RGBVAL16(169, 169, 169); + palettevga[8] = RGBVAL16(0, 0, 84); + palettevga[9] = RGBVAL16(0, 0, 255); + palettevga[10] = RGBVAL16(0, 169, 84); + palettevga[11] = RGBVAL16(0, 169, 255); + palettevga[12] = RGBVAL16(169, 0, 84); + palettevga[13] = RGBVAL16(169, 0, 255); + palettevga[14] = RGBVAL16(169, 169, 84); + palettevga[15] = RGBVAL16(169, 169, 255); + palettevga[16] = RGBVAL16(0, 84, 0); + palettevga[17] = RGBVAL16(0, 84, 169); + palettevga[18] = RGBVAL16(0, 255, 0); + palettevga[19] = RGBVAL16(0, 255, 169); + palettevga[20] = RGBVAL16(169, 84, 0); + palettevga[21] = RGBVAL16(169, 84, 169); + palettevga[22] = RGBVAL16(169, 255, 0); + palettevga[23] = RGBVAL16(169, 255, 169); + palettevga[24] = RGBVAL16(0, 84, 84); + palettevga[25] = RGBVAL16(0, 84, 255); + palettevga[26] = RGBVAL16(0, 255, 84); + palettevga[27] = RGBVAL16(0, 255, 255); + palettevga[28] = RGBVAL16(169, 84, 84); + palettevga[29] = RGBVAL16(169, 84, 255); + palettevga[30] = RGBVAL16(169, 255, 84); + palettevga[31] = RGBVAL16(169, 255, 255); + palettevga[32] = RGBVAL16(84, 0, 0); + palettevga[33] = RGBVAL16(84, 0, 169); + palettevga[34] = RGBVAL16(84, 169, 0); + palettevga[35] = RGBVAL16(84, 169, 169); + palettevga[36] = RGBVAL16(255, 0, 0); + palettevga[37] = RGBVAL16(255, 0, 169); + palettevga[38] = RGBVAL16(255, 169, 0); + palettevga[39] = RGBVAL16(255, 169, 169); + palettevga[40] = RGBVAL16(84, 0, 84); + palettevga[41] = RGBVAL16(84, 0, 255); + palettevga[42] = RGBVAL16(84, 169, 84); + palettevga[43] = RGBVAL16(84, 169, 255); + palettevga[44] = RGBVAL16(255, 0, 84); + palettevga[45] = RGBVAL16(255, 0, 255); + palettevga[46] = RGBVAL16(255, 169, 84); + palettevga[47] = RGBVAL16(255, 169, 255); + palettevga[48] = RGBVAL16(84, 84, 0); + palettevga[49] = RGBVAL16(84, 84, 169); + palettevga[50] = RGBVAL16(84, 255, 0); + palettevga[51] = RGBVAL16(84, 255, 169); + palettevga[52] = RGBVAL16(255, 84, 0); + palettevga[53] = RGBVAL16(255, 84, 169); + palettevga[54] = RGBVAL16(255, 255, 0); + palettevga[55] = RGBVAL16(255, 255, 169); + palettevga[56] = RGBVAL16(84, 84, 84); + palettevga[57] = RGBVAL16(84, 84, 255); + palettevga[58] = RGBVAL16(84, 255, 84); + palettevga[59] = RGBVAL16(84, 255, 255); + palettevga[60] = RGBVAL16(255, 84, 84); + palettevga[61] = RGBVAL16(255, 84, 255); + palettevga[62] = RGBVAL16(255, 255, 84); + palettevga[63] = RGBVAL16(255, 255, 255); + palettevga[64] = RGBVAL16(255, 125, 125); + palettevga[65] = RGBVAL16(255, 157, 125); + palettevga[66] = RGBVAL16(255, 190, 125); + palettevga[67] = RGBVAL16(255, 222, 125); + palettevga[68] = RGBVAL16(255, 255, 125); + palettevga[69] = RGBVAL16(222, 255, 125); + palettevga[70] = RGBVAL16(190, 255, 125); + palettevga[71] = RGBVAL16(157, 255, 125); + palettevga[72] = RGBVAL16(125, 255, 125); + palettevga[73] = RGBVAL16(125, 255, 157); + palettevga[74] = RGBVAL16(125, 255, 190); + palettevga[75] = RGBVAL16(125, 255, 222); + palettevga[76] = RGBVAL16(125, 255, 255); + palettevga[77] = RGBVAL16(125, 222, 255); + palettevga[78] = RGBVAL16(125, 190, 255); + palettevga[79] = RGBVAL16(125, 157, 255); + palettevga[80] = RGBVAL16(182, 182, 255); + palettevga[81] = RGBVAL16(198, 182, 255); + palettevga[82] = RGBVAL16(218, 182, 255); + palettevga[83] = RGBVAL16(234, 182, 255); + palettevga[84] = RGBVAL16(255, 182, 255); + palettevga[85] = RGBVAL16(255, 182, 234); + palettevga[86] = RGBVAL16(255, 182, 218); + palettevga[87] = RGBVAL16(255, 182, 198); + palettevga[88] = RGBVAL16(255, 182, 182); + palettevga[89] = RGBVAL16(255, 198, 182); + palettevga[90] = RGBVAL16(255, 218, 182); + palettevga[91] = RGBVAL16(255, 234, 182); + palettevga[92] = RGBVAL16(255, 255, 182); + palettevga[93] = RGBVAL16(234, 255, 182); + palettevga[94] = RGBVAL16(218, 255, 182); + palettevga[95] = RGBVAL16(198, 255, 182); + palettevga[96] = RGBVAL16(182, 255, 182); + palettevga[97] = RGBVAL16(182, 255, 198); + palettevga[98] = RGBVAL16(182, 255, 218); + palettevga[99] = RGBVAL16(182, 255, 234); + palettevga[100] = RGBVAL16(182, 255, 255); + palettevga[101] = RGBVAL16(182, 234, 255); + palettevga[102] = RGBVAL16(182, 218, 255); + palettevga[103] = RGBVAL16(182, 198, 255); + palettevga[104] = RGBVAL16(0, 0, 113); + palettevga[105] = RGBVAL16(28, 0, 113); + palettevga[106] = RGBVAL16(56, 0, 113); + palettevga[107] = RGBVAL16(84, 0, 113); + palettevga[108] = RGBVAL16(113, 0, 113); + palettevga[109] = RGBVAL16(113, 0, 84); + palettevga[110] = RGBVAL16(113, 0, 56); + palettevga[111] = RGBVAL16(113, 0, 28); + palettevga[112] = RGBVAL16(113, 0, 0); + palettevga[113] = RGBVAL16(113, 28, 0); + palettevga[114] = RGBVAL16(113, 56, 0); + palettevga[115] = RGBVAL16(113, 84, 0); + palettevga[116] = RGBVAL16(113, 113, 0); + palettevga[117] = RGBVAL16(84, 113, 0); + palettevga[118] = RGBVAL16(56, 113, 0); + palettevga[119] = RGBVAL16(28, 113, 0); + palettevga[120] = RGBVAL16(0, 113, 0); + palettevga[121] = RGBVAL16(0, 113, 28); + palettevga[122] = RGBVAL16(0, 113, 56); + palettevga[123] = RGBVAL16(0, 113, 84); + palettevga[124] = RGBVAL16(0, 113, 113); + palettevga[125] = RGBVAL16(0, 84, 113); + palettevga[126] = RGBVAL16(0, 56, 113); + palettevga[127] = RGBVAL16(0, 28, 113); + palettevga[128] = RGBVAL16(56, 56, 113); + palettevga[129] = RGBVAL16(68, 56, 113); + palettevga[130] = RGBVAL16(84, 56, 113); + palettevga[131] = RGBVAL16(97, 56, 113); + palettevga[132] = RGBVAL16(113, 56, 113); + palettevga[133] = RGBVAL16(113, 56, 97); + palettevga[134] = RGBVAL16(113, 56, 84); + palettevga[135] = RGBVAL16(113, 56, 68); + palettevga[136] = RGBVAL16(113, 56, 56); + palettevga[137] = RGBVAL16(113, 68, 56); + palettevga[138] = RGBVAL16(113, 84, 56); + palettevga[139] = RGBVAL16(113, 97, 56); + palettevga[140] = RGBVAL16(113, 113, 56); + palettevga[141] = RGBVAL16(97, 113, 56); + palettevga[142] = RGBVAL16(84, 113, 56); + palettevga[143] = RGBVAL16(68, 113, 56); + palettevga[144] = RGBVAL16(56, 113, 56); + palettevga[145] = RGBVAL16(56, 113, 68); + palettevga[146] = RGBVAL16(56, 113, 84); + palettevga[147] = RGBVAL16(56, 113, 97); + palettevga[148] = RGBVAL16(56, 113, 113); + palettevga[149] = RGBVAL16(56, 97, 113); + palettevga[150] = RGBVAL16(56, 84, 113); + palettevga[151] = RGBVAL16(56, 68, 113); + palettevga[152] = RGBVAL16(80, 80, 113); + palettevga[153] = RGBVAL16(89, 80, 113); + palettevga[154] = RGBVAL16(97, 80, 113); + palettevga[155] = RGBVAL16(105, 80, 113); + palettevga[156] = RGBVAL16(113, 80, 113); + palettevga[157] = RGBVAL16(113, 80, 105); + palettevga[158] = RGBVAL16(113, 80, 97); + palettevga[159] = RGBVAL16(113, 80, 89); + palettevga[160] = RGBVAL16(113, 80, 80); + palettevga[161] = RGBVAL16(113, 89, 80); + palettevga[162] = RGBVAL16(113, 97, 80); + palettevga[163] = RGBVAL16(113, 105, 80); + palettevga[164] = RGBVAL16(113, 113, 80); + palettevga[165] = RGBVAL16(105, 113, 80); + palettevga[166] = RGBVAL16(97, 113, 80); + palettevga[167] = RGBVAL16(89, 113, 80); + palettevga[168] = RGBVAL16(80, 113, 80); + palettevga[169] = RGBVAL16(80, 113, 89); + palettevga[170] = RGBVAL16(80, 113, 97); + palettevga[171] = RGBVAL16(80, 113, 105); + palettevga[172] = RGBVAL16(80, 113, 113); + palettevga[173] = RGBVAL16(80, 105, 113); + palettevga[174] = RGBVAL16(80, 97, 113); + palettevga[175] = RGBVAL16(80, 89, 113); + palettevga[176] = RGBVAL16(0, 0, 64); + palettevga[177] = RGBVAL16(16, 0, 64); + palettevga[178] = RGBVAL16(32, 0, 64); + palettevga[179] = RGBVAL16(48, 0, 64); + palettevga[180] = RGBVAL16(64, 0, 64); + palettevga[181] = RGBVAL16(64, 0, 48); + palettevga[182] = RGBVAL16(64, 0, 32); + palettevga[183] = RGBVAL16(64, 0, 16); + palettevga[184] = RGBVAL16(64, 0, 0); + palettevga[185] = RGBVAL16(64, 16, 0); + palettevga[186] = RGBVAL16(64, 32, 0); + palettevga[187] = RGBVAL16(64, 48, 0); + palettevga[188] = RGBVAL16(64, 64, 0); + palettevga[189] = RGBVAL16(48, 64, 0); + palettevga[190] = RGBVAL16(32, 64, 0); + palettevga[191] = RGBVAL16(16, 64, 0); + palettevga[192] = RGBVAL16(0, 64, 0); + palettevga[193] = RGBVAL16(0, 64, 16); + palettevga[194] = RGBVAL16(0, 64, 32); + palettevga[195] = RGBVAL16(0, 64, 48); + palettevga[196] = RGBVAL16(0, 64, 64); + palettevga[197] = RGBVAL16(0, 48, 64); + palettevga[198] = RGBVAL16(0, 32, 64); + palettevga[199] = RGBVAL16(0, 16, 64); + palettevga[200] = RGBVAL16(32, 32, 64); + palettevga[201] = RGBVAL16(40, 32, 64); + palettevga[202] = RGBVAL16(48, 32, 64); + palettevga[203] = RGBVAL16(56, 32, 64); + palettevga[204] = RGBVAL16(64, 32, 64); + palettevga[205] = RGBVAL16(64, 32, 56); + palettevga[206] = RGBVAL16(64, 32, 48); + palettevga[207] = RGBVAL16(64, 32, 40); + palettevga[208] = RGBVAL16(64, 32, 32); + palettevga[209] = RGBVAL16(64, 40, 32); + palettevga[210] = RGBVAL16(64, 48, 32); + palettevga[211] = RGBVAL16(64, 56, 32); + palettevga[212] = RGBVAL16(64, 64, 32); + palettevga[213] = RGBVAL16(56, 64, 32); + palettevga[214] = RGBVAL16(48, 64, 32); + palettevga[215] = RGBVAL16(40, 64, 32); + palettevga[216] = RGBVAL16(32, 64, 32); + palettevga[217] = RGBVAL16(32, 64, 40); + palettevga[218] = RGBVAL16(32, 64, 48); + palettevga[219] = RGBVAL16(32, 64, 56); + palettevga[220] = RGBVAL16(32, 64, 64); + palettevga[221] = RGBVAL16(32, 56, 64); + palettevga[222] = RGBVAL16(32, 48, 64); + palettevga[223] = RGBVAL16(32, 40, 64); + palettevga[224] = RGBVAL16(44, 44, 64); + palettevga[225] = RGBVAL16(48, 44, 64); + palettevga[226] = RGBVAL16(52, 44, 64); + palettevga[227] = RGBVAL16(60, 44, 64); + palettevga[228] = RGBVAL16(64, 44, 64); + palettevga[229] = RGBVAL16(64, 44, 60); + palettevga[230] = RGBVAL16(64, 44, 52); + palettevga[231] = RGBVAL16(64, 44, 48); + palettevga[232] = RGBVAL16(64, 44, 44); + palettevga[233] = RGBVAL16(64, 48, 44); + palettevga[234] = RGBVAL16(64, 52, 44); + palettevga[235] = RGBVAL16(64, 60, 44); + palettevga[236] = RGBVAL16(64, 64, 44); + palettevga[237] = RGBVAL16(60, 64, 44); + palettevga[238] = RGBVAL16(52, 64, 44); + palettevga[239] = RGBVAL16(48, 64, 44); + palettevga[240] = RGBVAL16(44, 64, 44); + palettevga[241] = RGBVAL16(44, 64, 48); + palettevga[242] = RGBVAL16(44, 64, 52); + palettevga[243] = RGBVAL16(44, 64, 60); + palettevga[244] = RGBVAL16(44, 64, 64); + palettevga[245] = RGBVAL16(44, 60, 64); + palettevga[246] = RGBVAL16(44, 52, 64); + palettevga[247] = RGBVAL16(44, 48, 64); + palettevga[248] = RGBVAL16(0, 0, 0); + palettevga[249] = RGBVAL16(0, 0, 0); + palettevga[250] = RGBVAL16(0, 0, 0); + palettevga[251] = RGBVAL16(0, 0, 0); + palettevga[252] = RGBVAL16(0, 0, 0); + palettevga[253] = RGBVAL16(0, 0, 0); + palettevga[254] = RGBVAL16(0, 0, 0); + palettevga[255] = RGBVAL16(0, 0, 0); +} + +extern uint8_t vidmode, portram[0x400]; + + + +#include "font.h" + + +static unsigned short line[320]; + + +void drawscreentext80(void) { + uint16_t row, col, y, x, xpos; + uint16_t fontdata; + + for (y=0; y<(25*8); y++) + { + row = y>>3; + uint8_t * vrampt=&VRAM[160*row]; + xpos = 0; + for (col=0; col<80; col++) + { + uint8_t bold, attrib, cc, bg, fg; + cc = *vrampt++; + attrib = *vrampt++; + bg = (attrib >> 4) & 7; + fg = attrib & 0x0F; + //if (y == 0) {printf("0x%02X",cc);} + fontdata = ROM_READ(font, ((uint32_t)cc << 3) + (y&0x7)); + for (x=0; x<4; x++) + { + if (fontdata & 1) { + line[xpos++] = palettecga[fg]; + //tft.drawPixel(realx++, realy, palettecga[fg]); + } else { + line[xpos++] = palettecga[bg]; + //tft.drawPixel(realx++, realy, palettecga[bg]); + } + fontdata >>= 2; + } + } + //if (y == 0) {printf("\n");} + + emu_DrawLine16(&line[0], 320, 200, y); + } +} + +void drawscreenlorescga(void) { + //uint16_t row; + uint16_t y, x, xpos; + uint8_t intensity, usepal; + uint16_t color; + usepal = (portram[0x3D9]>>5) & 1; + intensity = ( (portram[0x3D9]>>4) & 1) << 3; + + for (y=0; y<(25*8); y++) + { + //row = y>>3; + //uint8_t * vrampt=&VRAM[160*row]; + xpos = 0; + for (x=0; x<320; x++) + { + int ychar = y;// >> 1; + int xchar = x;// >> 1; + uint8_t curchar = VRAM[((ychar & 1) * 8192 + (ychar >> 1) * 80 + (xchar >> 2))]; + switch (xchar & 3) { + case 3: color = curchar & 3; break; + case 2: color = (curchar >> 2) & 3; break; + case 1: color = (curchar >> 4) & 3; break; + case 0: color = (curchar >> 6) & 3; break; + } + color = (color << 1) + usepal + intensity; + if (color == (usepal + intensity)) color = 0; + line[xpos++] = palettecga[color]; + } + + + /* + for (col=0; col<80; col++) + { + uint8_t value = *vrampt++; + for (i=0; i<4; i++) + { + uint8_t packedcolor; + packedcolor = value >> 6; + if (!packedcolor) color = 0; else color = packedcolor * 2 + usepal + intensity; + line[xpos++] = palettecga[color]; + value <<= 2; + } + } + */ + //if (y == 0) {printf("\n");} + + emu_DrawLine16(&line[0], 320, 200, y); + } +} + + +void drawscreenhirescga(void) { + uint16_t y, x, xpos; + uint16_t color; + for (y=0; y<(25*8); y++) + { + xpos = 0; + for (x=0; x<320; x++) + { + int ychar = y >> 1; + int xchar = x; + uint8_t curchar = VRAM[((ychar & 1) * 8192 + (ychar >> 1) * 80 + (xchar >> 3))]; + color = ((curchar >> (7-(x&7))) & 1) ? 15 : 0; + line[xpos++] = palettecga[color]; + } + + emu_DrawLine16(&line[0], 320, 200, y); + } +} + + +void updatescreen() { + switch (vidmode & 0x7F) { + case 0: + case 1: + //drawtext40(origaddr, value); + break; + case 2: + case 3: + //case 7: + drawscreentext80(); + break; + case 4: + drawscreenlorescga(); + break; + case 5: + drawscreenlorescga(); //change to BW function later + break; + case 6: + drawscreenhirescga(); + break; + } +//printf("%d\n",vidmode & 0x7F); +} + + +void mac_Init(void) +{ + RAM = (uint8_t*) heap_caps_malloc(RAM_SIZE,MALLOC_CAP_SPIRAM); //malloc (MEMSIZE); + if (!RAM)printf("SPI RAM malloc failed\n"); + + LORAM = (uint8_t*)malloc(NATIVE_RAM); + if (!LORAM)printf("LORAM malloc failed\n"); + + + installPalette(); + init8253(); + reset86(); + init8259(); +} + + +static uint8_t nbkeys=0; +static uint8_t kcnt=0; +static int toggle=1; + +//static char * seq="DIR\r"; +static char * seq="CAT.EXE\r"; +//static char * seq="PRINCE.BAT\r"; + + +static int hk=0; +static int k=0; +static bool isMouse = true; +static int prev_key = 0; +static int prev_j = 0; + +static void keyevent(int keysym, int isdown) +{ + uint8_t scancode = translatescancode(keysym); + if (scancode != 0xFF) { + portram[0x60] = scancode; + if (!isdown) portram[0x60] |= 0x80; + portram[0x64] |= 2; + doirq(1); + vTaskDelay(50 / portTICK_PERIOD_MS); + } +} + +void mac_Input(int bClick) +{ + hk = emu_ReadI2CKeyboard(); + k = emu_ReadKeys(); + + if (nbkeys == 0) { + if (bClick & MASK_JOY2_BTN) { + nbkeys = strlen(seq); + kcnt=0; + } + } + else { + char k = seq[kcnt]; + if (k == 13) keyevent(0xFF0D,toggle); + else keyevent(k,toggle); + //setKey(ascii2scan[k],toggle); + if (!toggle) { + kcnt++; + nbkeys--; + toggle = true; + } + else { + toggle = false; + } + } +} + + + + + +void mac_Step(void) +{ + exec86(8000); + updatescreen(); + + //hk = emu_ReadI2CKeyboard(); + if ( (hk != 0) && (hk != prev_key) ) { + printf("press %d\n", hk); + prev_key = hk; + keyevent ( hk, 0 ); + } else{ + if (prev_key) { + printf("release %d\n", prev_key); + keyevent ( prev_key, 1 ); + prev_key = 0; + } + } + + + int j = 0; + if (( k & MASK_JOY1_RIGHT) || ( k & MASK_JOY2_RIGHT)) { + j |= 0x08; + } + if (( k & MASK_JOY1_LEFT) || ( k & MASK_JOY2_LEFT)) { + j |= 0x04; + } + if (( k & MASK_JOY1_UP) || ( k & MASK_JOY2_UP)) { + j |= 0x01; + } + if (( k & MASK_JOY1_DOWN) || ( k & MASK_JOY2_DOWN)) { + j |= 0x02; + } + if ( k & MASK_JOY2_BTN) { + printf("fire\n"); + j |= 0x80; + } + //if (j != prev_j) IkbdJoystickChange(joynum,j); + prev_j = j; + +} + + + + +void mac_Start(char * filename) +{ + initDisk(filename); +} + + diff --git a/MCUME_esp32/esp8086/main/emul.h b/MCUME_esp32/esp8086/main/emul.h new file mode 100644 index 0000000..3aa56ff --- /dev/null +++ b/MCUME_esp32/esp8086/main/emul.h @@ -0,0 +1,4 @@ +extern void mac_Init(void); +extern void mac_Step(void); +extern void mac_Start(char * filename); +extern void mac_Input(int bClick); diff --git a/MCUME_esp32/esp8086/main/font.h b/MCUME_esp32/esp8086/main/font.h new file mode 100755 index 0000000..0c74ef5 --- /dev/null +++ b/MCUME_esp32/esp8086/main/font.h @@ -0,0 +1,263 @@ +#ifdef MEGA + const uint8_t font[2048] PROGMEM = { +#else + const uint8_t font[2048] = { +#endif + 0,0,0,0,0,0,0, + 0,126,129,165,129,189,153,129, + 126,126,255,219,255,195,231,255, + 126,54,127,127,127,62,28,8, + 0,8,28,62,127,62,28,8, + 0,28,62,28,127,127,62,28, + 62,8,8,28,62,127,62,28, + 62,0,0,0,0,0,0,0, + 0,255,255,231,195,195,231,255, + 255,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,254,198,254,198,198,230,103, + 3,153,90,60,231,231,60,90, + 153,1,7,31,127,31,7,1, + 0,64,112,124,127,124,112,64, + 0,24,60,126,24,24,126,60, + 24,102,102,102,102,102,0,102, + 0,254,219,219,222,216,216,216, + 0,124,198,28,54,54,28,51, + 30,0,0,0,0,126,126,126, + 0,24,60,126,24,126,60,24, + 255,24,60,126,24,24,24,24, + 0,24,24,24,24,126,60,24, + 0,0,24,48,127,48,24,0, + 0,0,12,6,127,6,12,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,12,30,30,12,12,0,12, + 0,54,54,54,0,0,0,0, + 0,54,54,127,54,127,54,54, + 0,12,62,3,30,48,31,12, + 0,0,99,51,24,12,102,99, + 0,28,54,28,110,59,51,110, + 0,6,6,3,0,0,0,0, + 0,24,12,6,6,6,12,24, + 0,6,12,24,24,24,12,6, + 0,0,102,60,255,60,102,0, + 0,0,12,12,63,12,12,0, + 0,0,0,0,0,0,12,12, + 6,0,0,0,63,0,0,0, + 0,0,0,0,0,0,12,12, + 0,96,48,24,12,6,3,1, + 0,62,99,115,123,111,103,62, + 0,12,14,12,12,12,12,63, + 0,30,51,48,28,6,51,63, + 0,30,51,48,28,48,51,30, + 0,56,60,54,51,127,48,120, + 0,63,3,31,48,48,51,30, + 0,28,6,3,31,51,51,30, + 0,63,51,48,24,12,12,12, + 0,30,51,51,30,51,51,30, + 0,30,51,51,62,48,24,14, + 0,0,12,12,0,0,12,12, + 0,0,12,12,0,0,12,12, + 6,24,12,6,3,6,12,24, + 0,0,0,63,0,0,63,0, + 0,6,12,24,48,24,12,6, + 0,30,51,48,24,12,0,12, + 0,62,99,123,123,123,3,30, + 0,12,30,51,51,63,51,51, + 0,63,102,102,62,102,102,63, + 0,60,102,3,3,3,102,60, + 0,31,54,102,102,102,54,31, + 0,127,70,22,30,22,70,127, + 0,127,70,22,30,22,6,15, + 0,60,102,3,3,115,102,124, + 0,51,51,51,63,51,51,51, + 0,30,12,12,12,12,12,30, + 0,120,48,48,48,51,51,30, + 0,103,102,54,30,54,102,103, + 0,15,6,6,6,70,102,127, + 0,99,119,127,127,107,99,99, + 0,99,103,111,123,115,99,99, + 0,28,54,99,99,99,54,28, + 0,63,102,102,62,6,6,15, + 0,30,51,51,51,59,30,56, + 0,63,102,102,62,54,102,103, + 0,30,51,7,14,56,51,30, + 0,63,45,12,12,12,12,30, + 0,51,51,51,51,51,51,63, + 0,51,51,51,51,51,30,12, + 0,99,99,99,107,127,119,99, + 0,99,99,54,28,28,54,99, + 0,51,51,51,30,12,12,30, + 0,127,99,49,24,76,102,127, + 0,30,6,6,6,6,6,30, + 0,3,6,12,24,48,96,64, + 0,30,24,24,24,24,24,30, + 0,8,28,54,99,0,0,0, + 0,0,0,0,0,0,0,0, + 255,12,12,24,0,0,0,0, + 0,0,0,30,48,62,51,110, + 0,7,6,6,62,102,102,59, + 0,0,0,30,51,3,51,30, + 0,56,48,48,62,51,51,110, + 0,0,0,30,51,63,3,30, + 0,28,54,6,15,6,6,15, + 0,0,0,110,51,51,62,48, + 31,7,6,54,110,102,102,103, + 0,12,0,14,12,12,12,30, + 0,48,0,48,48,48,51,51, + 30,7,6,102,54,30,54,103, + 0,14,12,12,12,12,12,30, + 0,0,0,51,127,127,107,99, + 0,0,0,31,51,51,51,51, + 0,0,0,30,51,51,51,30, + 0,0,0,59,102,102,62,6, + 15,0,0,110,51,51,62,48, + 120,0,0,59,110,102,6,15, + 0,0,0,62,3,30,48,31, + 0,8,12,62,12,12,44,24, + 0,0,0,51,51,51,51,110, + 0,0,0,51,51,51,30,12, + 0,0,0,99,107,127,127,54, + 0,0,0,99,54,28,54,99, + 0,0,0,51,51,51,62,48, + 31,0,0,63,25,12,38,63, + 0,56,12,12,7,12,12,56, + 0,24,24,24,0,24,24,24, + 0,7,12,12,56,12,12,7, + 0,110,59,0,0,0,0,0, + 0,0,8,28,54,99,99,127, + 0,30,51,3,51,30,24,48, + 30,0,51,0,51,51,51,126, + 0,56,0,30,51,63,3,30, + 0,126,195,60,96,124,102,252, + 0,51,0,30,48,62,51,126, + 0,7,0,30,48,62,51,126, + 0,12,12,30,48,62,51,126, + 0,0,0,30,3,3,30,48, + 28,126,195,60,102,126,6,60, + 0,51,0,30,51,63,3,30, + 0,7,0,30,51,63,3,30, + 0,51,0,14,12,12,12,30, + 0,62,99,28,24,24,24,60, + 0,7,0,14,12,12,12,30, + 0,99,28,54,99,127,99,99, + 0,12,12,0,30,51,63,51, + 0,56,0,63,6,30,6,63, + 0,0,0,254,48,254,51,254, + 0,124,54,51,127,51,51,115, + 0,30,51,0,30,51,51,30, + 0,0,51,0,30,51,51,30, + 0,0,7,0,30,51,51,30, + 0,30,51,0,51,51,51,126, + 0,0,7,0,51,51,51,126, + 0,0,51,0,51,51,62,48, + 31,195,24,60,102,102,60,24, + 0,51,0,51,51,51,51,30, + 0,24,24,126,3,3,126,24, + 24,28,54,38,15,6,103,63, + 0,51,51,30,63,12,63,12, + 12,31,51,51,95,99,243,99, + 227,112,216,24,60,24,24,27, + 14,56,0,30,48,62,51,126, + 0,28,0,14,12,12,12,30, + 0,0,56,0,30,51,51,30, + 0,0,56,0,51,51,51,126, + 0,0,31,0,31,51,51,51, + 0,63,0,51,55,63,59,51, + 0,60,54,54,124,0,126,0, + 0,28,54,54,28,0,62,0, + 0,12,0,12,6,3,51,30, + 0,0,0,0,63,3,3,0, + 0,0,0,0,63,48,48,0, + 0,195,99,51,123,204,102,51, + 240,195,99,51,219,236,246,243, + 192,24,24,0,24,24,24,24, + 0,0,204,102,51,102,204,0, + 0,0,51,102,204,102,51,0, + 0,68,17,68,17,68,17,68, + 17,170,85,170,85,170,85,170, + 85,219,238,219,119,219,238,219, + 119,24,24,24,24,24,24,24, + 24,24,24,24,24,31,24,24, + 24,24,24,31,24,31,24,24, + 24,108,108,108,108,111,108,108, + 108,0,0,0,0,127,108,108, + 108,0,0,31,24,31,24,24, + 24,108,108,111,96,111,108,108, + 108,108,108,108,108,108,108,108, + 108,0,0,127,96,111,108,108, + 108,108,108,111,96,127,0,0, + 0,108,108,108,108,127,0,0, + 0,24,24,31,24,31,0,0, + 0,0,0,0,0,31,24,24, + 24,24,24,24,24,248,0,0, + 0,24,24,24,24,255,0,0, + 0,0,0,0,0,255,24,24, + 24,24,24,24,24,248,24,24, + 24,0,0,0,0,255,0,0, + 0,24,24,24,24,255,24,24, + 24,24,24,248,24,248,24,24, + 24,108,108,108,108,236,108,108, + 108,108,108,236,12,252,0,0, + 0,0,0,252,12,236,108,108, + 108,108,108,239,0,255,0,0, + 0,0,0,255,0,239,108,108, + 108,108,108,236,12,236,108,108, + 108,0,0,255,0,255,0,0, + 0,108,108,239,0,239,108,108, + 108,24,24,255,0,255,0,0, + 0,108,108,108,108,255,0,0, + 0,0,0,255,0,255,24,24, + 24,0,0,0,0,255,108,108, + 108,108,108,108,108,252,0,0, + 0,24,24,248,24,248,0,0, + 0,0,0,248,24,248,24,24, + 24,0,0,0,0,252,108,108, + 108,108,108,108,108,255,108,108, + 108,24,24,255,24,255,24,24, + 24,24,24,24,24,31,0,0, + 0,0,0,0,0,248,24,24, + 24,255,255,255,255,255,255,255, + 255,0,0,0,0,255,255,255, + 255,15,15,15,15,15,15,15, + 15,240,240,240,240,240,240,240, + 240,255,255,255,255,0,0,0, + 0,0,0,110,59,19,59,110, + 0,0,30,51,31,51,31,3, + 3,0,63,51,3,3,3,3, + 0,0,127,54,54,54,54,54, + 0,63,51,6,12,6,51,63, + 0,0,0,126,27,27,27,14, + 0,0,102,102,102,102,62,6, + 3,0,110,59,24,24,24,24, + 0,63,12,30,51,51,30,12, + 63,28,54,99,127,99,54,28, + 0,28,54,99,99,54,54,119, + 0,56,12,24,62,51,51,30, + 0,0,0,126,219,219,126,0, + 0,96,48,126,219,219,126,6, + 3,28,6,3,31,3,6,28, + 0,30,51,51,51,51,51,51, + 0,0,63,0,63,0,63,0, + 0,12,12,63,12,12,0,63, + 0,6,12,24,12,6,0,63, + 0,24,12,6,12,24,0,63, + 0,112,216,216,24,24,24,24, + 24,24,24,24,24,24,27,27, + 14,12,12,0,63,0,12,12, + 0,0,110,59,0,110,59,0, + 0,28,54,54,28,0,0,0, + 0,0,0,0,24,24,0,0, + 0,0,0,0,0,24,0,0, + 0,240,48,48,48,55,54,60, + 56,30,54,54,54,54,0,0, + 0,14,24,12,6,30,0,0, + 0,0,0,60,60,60,60,0, + 0,0,0,0,0,0,0,0,0 +}; + diff --git a/MCUME_esp32/esp8086/main/font8x8.h b/MCUME_esp32/esp8086/main/font8x8.h new file mode 100644 index 0000000..bab272e --- /dev/null +++ b/MCUME_esp32/esp8086/main/font8x8.h @@ -0,0 +1,136 @@ + +// Font: c64_lower.64c + +const unsigned char font8x8[128][8] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0000 (nul) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0001 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0002 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0003 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0004 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0005 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0006 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0007 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0008 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0009 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000A + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000B + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000C + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000E + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000F + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0010 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0011 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0012 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0013 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0014 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0015 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0016 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0017 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0018 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0019 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001A + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001B + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001C + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001E + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001F + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0020 (space) + { 0x18, 0x3C, 0x3C, 0x18, 0x18, 0x00, 0x18, 0x00}, // U+0021 (!) + { 0x36, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0022 (") + { 0x36, 0x36, 0x7F, 0x36, 0x7F, 0x36, 0x36, 0x00}, // U+0023 (#) + { 0x0C, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x0C, 0x00}, // U+0024 ($) + { 0x00, 0x63, 0x33, 0x18, 0x0C, 0x66, 0x63, 0x00}, // U+0025 (%) + { 0x1C, 0x36, 0x1C, 0x6E, 0x3B, 0x33, 0x6E, 0x00}, // U+0026 (&) + { 0x06, 0x06, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0027 (') + { 0x18, 0x0C, 0x06, 0x06, 0x06, 0x0C, 0x18, 0x00}, // U+0028 (() + { 0x06, 0x0C, 0x18, 0x18, 0x18, 0x0C, 0x06, 0x00}, // U+0029 ()) + { 0x00, 0x66, 0x3C, 0xFF, 0x3C, 0x66, 0x00, 0x00}, // U+002A (*) + { 0x00, 0x0C, 0x0C, 0x3F, 0x0C, 0x0C, 0x00, 0x00}, // U+002B (+) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x06}, // U+002C (,) + { 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00}, // U+002D (-) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00}, // U+002E (.) + { 0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x01, 0x00}, // U+002F (/) + { 0x3E, 0x63, 0x73, 0x7B, 0x6F, 0x67, 0x3E, 0x00}, // U+0030 (0) + { 0x0C, 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x3F, 0x00}, // U+0031 (1) + { 0x1E, 0x33, 0x30, 0x1C, 0x06, 0x33, 0x3F, 0x00}, // U+0032 (2) + { 0x1E, 0x33, 0x30, 0x1C, 0x30, 0x33, 0x1E, 0x00}, // U+0033 (3) + { 0x38, 0x3C, 0x36, 0x33, 0x7F, 0x30, 0x78, 0x00}, // U+0034 (4) + { 0x3F, 0x03, 0x1F, 0x30, 0x30, 0x33, 0x1E, 0x00}, // U+0035 (5) + { 0x1C, 0x06, 0x03, 0x1F, 0x33, 0x33, 0x1E, 0x00}, // U+0036 (6) + { 0x3F, 0x33, 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x00}, // U+0037 (7) + { 0x1E, 0x33, 0x33, 0x1E, 0x33, 0x33, 0x1E, 0x00}, // U+0038 (8) + { 0x1E, 0x33, 0x33, 0x3E, 0x30, 0x18, 0x0E, 0x00}, // U+0039 (9) + { 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x00}, // U+003A (:) + { 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x06}, // U+003B (//) + { 0x18, 0x0C, 0x06, 0x03, 0x06, 0x0C, 0x18, 0x00}, // U+003C (<) + { 0x00, 0x00, 0x3F, 0x00, 0x00, 0x3F, 0x00, 0x00}, // U+003D (=) + { 0x06, 0x0C, 0x18, 0x30, 0x18, 0x0C, 0x06, 0x00}, // U+003E (>) + { 0x1E, 0x33, 0x30, 0x18, 0x0C, 0x00, 0x0C, 0x00}, // U+003F (?) + { 0x3E, 0x63, 0x7B, 0x7B, 0x7B, 0x03, 0x1E, 0x00}, // U+0040 (@) + { 0x0C, 0x1E, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x00}, // U+0041 (A) + { 0x3F, 0x66, 0x66, 0x3E, 0x66, 0x66, 0x3F, 0x00}, // U+0042 (B) + { 0x3C, 0x66, 0x03, 0x03, 0x03, 0x66, 0x3C, 0x00}, // U+0043 (C) + { 0x1F, 0x36, 0x66, 0x66, 0x66, 0x36, 0x1F, 0x00}, // U+0044 (D) + { 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x46, 0x7F, 0x00}, // U+0045 (E) + { 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x06, 0x0F, 0x00}, // U+0046 (F) + { 0x3C, 0x66, 0x03, 0x03, 0x73, 0x66, 0x7C, 0x00}, // U+0047 (G) + { 0x33, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x33, 0x00}, // U+0048 (H) + { 0x1E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0049 (I) + { 0x78, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E, 0x00}, // U+004A (J) + { 0x67, 0x66, 0x36, 0x1E, 0x36, 0x66, 0x67, 0x00}, // U+004B (K) + { 0x0F, 0x06, 0x06, 0x06, 0x46, 0x66, 0x7F, 0x00}, // U+004C (L) + { 0x63, 0x77, 0x7F, 0x7F, 0x6B, 0x63, 0x63, 0x00}, // U+004D (M) + { 0x63, 0x67, 0x6F, 0x7B, 0x73, 0x63, 0x63, 0x00}, // U+004E (N) + { 0x1C, 0x36, 0x63, 0x63, 0x63, 0x36, 0x1C, 0x00}, // U+004F (O) + { 0x3F, 0x66, 0x66, 0x3E, 0x06, 0x06, 0x0F, 0x00}, // U+0050 (P) + { 0x1E, 0x33, 0x33, 0x33, 0x3B, 0x1E, 0x38, 0x00}, // U+0051 (Q) + { 0x3F, 0x66, 0x66, 0x3E, 0x36, 0x66, 0x67, 0x00}, // U+0052 (R) + { 0x1E, 0x33, 0x07, 0x0E, 0x38, 0x33, 0x1E, 0x00}, // U+0053 (S) + { 0x3F, 0x2D, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0054 (T) + { 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x3F, 0x00}, // U+0055 (U) + { 0x33, 0x33, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00}, // U+0056 (V) + { 0x63, 0x63, 0x63, 0x6B, 0x7F, 0x77, 0x63, 0x00}, // U+0057 (W) + { 0x63, 0x63, 0x36, 0x1C, 0x1C, 0x36, 0x63, 0x00}, // U+0058 (X) + { 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x0C, 0x1E, 0x00}, // U+0059 (Y) + { 0x7F, 0x63, 0x31, 0x18, 0x4C, 0x66, 0x7F, 0x00}, // U+005A (Z) + { 0x1E, 0x06, 0x06, 0x06, 0x06, 0x06, 0x1E, 0x00}, // U+005B ([) + { 0x03, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x40, 0x00}, // U+005C (\) + { 0x1E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1E, 0x00}, // U+005D (]) + { 0x08, 0x1C, 0x36, 0x63, 0x00, 0x00, 0x00, 0x00}, // U+005E (^) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF}, // U+005F (_) + { 0x0C, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0060 (`) + { 0x00, 0x00, 0x1E, 0x30, 0x3E, 0x33, 0x6E, 0x00}, // U+0061 (a) + { 0x07, 0x06, 0x06, 0x3E, 0x66, 0x66, 0x3B, 0x00}, // U+0062 (b) + { 0x00, 0x00, 0x1E, 0x33, 0x03, 0x33, 0x1E, 0x00}, // U+0063 (c) + { 0x38, 0x30, 0x30, 0x3e, 0x33, 0x33, 0x6E, 0x00}, // U+0064 (d) + { 0x00, 0x00, 0x1E, 0x33, 0x3f, 0x03, 0x1E, 0x00}, // U+0065 (e) + { 0x1C, 0x36, 0x06, 0x0f, 0x06, 0x06, 0x0F, 0x00}, // U+0066 (f) + { 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x1F}, // U+0067 (g) + { 0x07, 0x06, 0x36, 0x6E, 0x66, 0x66, 0x67, 0x00}, // U+0068 (h) + { 0x0C, 0x00, 0x0E, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0069 (i) + { 0x30, 0x00, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E}, // U+006A (j) + { 0x07, 0x06, 0x66, 0x36, 0x1E, 0x36, 0x67, 0x00}, // U+006B (k) + { 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+006C (l) + { 0x00, 0x00, 0x33, 0x7F, 0x7F, 0x6B, 0x63, 0x00}, // U+006D (m) + { 0x00, 0x00, 0x1F, 0x33, 0x33, 0x33, 0x33, 0x00}, // U+006E (n) + { 0x00, 0x00, 0x1E, 0x33, 0x33, 0x33, 0x1E, 0x00}, // U+006F (o) + { 0x00, 0x00, 0x3B, 0x66, 0x66, 0x3E, 0x06, 0x0F}, // U+0070 (p) + { 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x78}, // U+0071 (q) + { 0x00, 0x00, 0x3B, 0x6E, 0x66, 0x06, 0x0F, 0x00}, // U+0072 (r) + { 0x00, 0x00, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x00}, // U+0073 (s) + { 0x08, 0x0C, 0x3E, 0x0C, 0x0C, 0x2C, 0x18, 0x00}, // U+0074 (t) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x33, 0x6E, 0x00}, // U+0075 (u) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00}, // U+0076 (v) + { 0x00, 0x00, 0x63, 0x6B, 0x7F, 0x7F, 0x36, 0x00}, // U+0077 (w) + { 0x00, 0x00, 0x63, 0x36, 0x1C, 0x36, 0x63, 0x00}, // U+0078 (x) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x3E, 0x30, 0x1F}, // U+0079 (y) + { 0x00, 0x00, 0x3F, 0x19, 0x0C, 0x26, 0x3F, 0x00}, // U+007A (z) + { 0x38, 0x0C, 0x0C, 0x07, 0x0C, 0x0C, 0x38, 0x00}, // U+007B ({) + { 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x00}, // U+007C (|) + { 0x07, 0x0C, 0x0C, 0x38, 0x0C, 0x0C, 0x07, 0x00}, // U+007D (}) + { 0x6E, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+007E (~) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} // U+007F +}; + + diff --git a/MCUME_esp32/esp8086/main/go.cpp b/MCUME_esp32/esp8086/main/go.cpp new file mode 100644 index 0000000..fc2c8ae --- /dev/null +++ b/MCUME_esp32/esp8086/main/go.cpp @@ -0,0 +1,112 @@ +#include "go.h" + +extern "C" { + #include "emuapi.h" + #include "iopins.h" +} + +#include "esp_event.h" + +#include "keyboard_osd.h" +#include "ili9341_t3dma.h" +#ifdef HAS_SND +#include "AudioPlaySystem.h" +#endif + +#include "emul.h" + + +ILI9341_t3DMA tft = ILI9341_t3DMA(PIN_NUM_CS, PIN_NUM_DC, -1, PIN_NUM_MOSI, PIN_NUM_CLK, PIN_NUM_MISO, TPIN_NUM_CS, TPIN_NUM_IRQ); +#ifdef HAS_SND +AudioPlaySystem audio; +#endif + + +static void spi_task(void *args) +{ + while(true) { + tft.refresh(); + } +} + +static void input_task(void *args) +{ + while(true) { + /* + if ((emu_ReadKeys() & (MASK_KEY_USER1+MASK_KEY_USER2)) == (MASK_KEY_USER1+MASK_KEY_USER2)) { + printf("rebooting\n"); + esp_restart(); + } + */ + + uint16_t bClick = emu_DebounceLocalKeys(); + /* + if (bClick & MASK_KEY_USER2) { + printf("%d\n",emu_SwapJoysticks(1)); + emu_SwapJoysticks(0); + } + else + */ + { + emu_Input(bClick); + } +#ifdef HAS_SND + audio.step(); +#endif + vTaskDelay(20 / portTICK_PERIOD_MS); + } +} + +static void main_step() { + if (menuActive()) { + uint16_t bClick = emu_DebounceLocalKeys(); + int action = handleMenu(bClick); + char * filename = menuSelection(); + if (action == ACTION_RUNTFT) { +#ifdef HAS_SND + audio.begin(); + audio.start(); +#endif + toggleMenu(false); + tft.fillScreenNoDma( RGBVAL16(0x00,0x00,0x00) ); + xTaskCreatePinnedToCore(input_task, "inputthread", 4096, NULL, 2, NULL, 0); + emu_Init(filename); + } + //vTaskDelay(20 / portTICK_PERIOD_MS); + } + else { + emu_Step(); + } +} + + +void setup(void) +{ + printf("Starting emulator\n"); + + tft.begin(); + //tft.flipscreen(true); + tft.start(); + tft.refresh(); + + emu_init(); + + xTaskCreatePinnedToCore(spi_task, "spithread", 4096, NULL, 1, NULL, 0); + //vTaskPrioritySet(NULL, tskIDLE_PRIORITY+1); + //toggleMenu(false); + //xTaskCreatePinnedToCore(input_task, "inputthread", 4096, NULL, 2, NULL, 0); + + //emu_Init("filename"); + +} + +void loop(void) +{ + unsigned long t = esp_timer_get_time(); + main_step(); + //printf("%d\n",(int)((esp_timer_get_time()-t)/1000)); +} + + + + diff --git a/MCUME_esp32/esp8086/main/go.h b/MCUME_esp32/esp8086/main/go.h new file mode 100644 index 0000000..12c65e0 --- /dev/null +++ b/MCUME_esp32/esp8086/main/go.h @@ -0,0 +1,8 @@ +#ifdef __cplusplus +extern "C" { +#endif +void setup(void); +void loop(void); +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/MCUME_esp32/esp8086/main/i8253.cpp b/MCUME_esp32/esp8086/main/i8253.cpp new file mode 100755 index 0000000..8956067 --- /dev/null +++ b/MCUME_esp32/esp8086/main/i8253.cpp @@ -0,0 +1,121 @@ +#include +#include + + +#ifdef MEGA + #include +#else +#include "esp32-hal-timer.h" +//IntervalTimer myTimer; +hw_timer_t * timer = NULL; +#endif + +#define PIT_MODE_LATCHCOUNT 0 +#define PIT_MODE_LOBYTE 1 +#define PIT_MODE_HIBYTE 2 +#define PIT_MODE_TOGGLE 3 + + +struct i8253_s { + uint16_t chandata[3]; + uint8_t accessmode[3]; + uint8_t bytetoggle[3]; + uint32_t effectivedata[3]; + float chanfreq[3]; + uint8_t active[3]; + uint16_t counter[3]; +} i8253; + +volatile uint8_t timerTick = 0; + +void timer_isr() { + timerTick = 1; +} + +void out8253 (uint16_t portnum, uint8_t value) { + uint8_t curbyte; + portnum &= 3; + switch (portnum) { + case 0: + case 1: + case 2: //channel data + if ( (i8253.accessmode[portnum] == PIT_MODE_LOBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 0) ) ) curbyte = 0; + else if ( (i8253.accessmode[portnum] == PIT_MODE_HIBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 1) ) ) curbyte = 1; + if (curbyte == 0) { //low byte + i8253.chandata[portnum] = (i8253.chandata[portnum] & 0xFF00) | value; + } + else { //high byte + i8253.chandata[portnum] = (i8253.chandata[portnum] & 0x00FF) | ( (uint16_t) value << 8); + } + if (i8253.chandata[portnum] == 0) i8253.effectivedata[portnum] = 65536; + else i8253.effectivedata[portnum] = i8253.chandata[portnum]; + i8253.active[portnum] = 1; + if (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) i8253.bytetoggle[portnum] = (~i8253.bytetoggle[portnum]) & 1; + //i8253.chanfreq[portnum] = (float) ( (uint32_t) ( ( (float) 1193182.0 / (float) i8253.effectivedata[portnum]) * (float) 1000.0) ); + //Serial.print("period "); Serial.println((uint32_t) ((float)1000000.0 / ( ( (float) 1193182.0 / (float) i8253.effectivedata[portnum])))); + if (portnum == 0) { + uint32_t period; + period = (uint32_t) ((float)1000000.0 / ( ( (float) 1193182.0 / (float) i8253.effectivedata[portnum]))); +#ifdef MEGA + if (period < 4000) period = 4000; //limit to 250 Hz, or the emulator just can't keep up on a Mega + //Serial.println((float)1000000.0 / (float)period); + Timer1.attachInterrupt(timer_isr, period); +#else + //myTimer.begin(timer_isr, period); + //printf("timer %d\n",period); + timerAttachInterrupt(timer, &timer_isr, true); // P3= edge triggered + timerAlarmWrite(timer, period, true); // will trigger 22050 times per sec (443 per 20 ms=22050/50) + timerAlarmEnable(timer); + +#endif + } + break; + case 3: //mode/command + i8253.accessmode[value>>6] = (value >> 4) & 3; + if (i8253.accessmode[value>>6] == PIT_MODE_TOGGLE) i8253.bytetoggle[value>>6] = 0; + break; + } +} + +uint8_t in8253 (uint16_t portnum) { + uint8_t curbyte; + portnum &= 3; + switch (portnum) { + case 0: + case 1: + case 2: //channel data + if ( (i8253.accessmode[portnum] == 0) || (i8253.accessmode[portnum] == PIT_MODE_LOBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 0) ) ) curbyte = 0; + else if ( (i8253.accessmode[portnum] == PIT_MODE_HIBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 1) ) ) curbyte = 1; + if ( (i8253.accessmode[portnum] == 0) || (i8253.accessmode[portnum] == PIT_MODE_LOBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 0) ) ) curbyte = 0; + else if ( (i8253.accessmode[portnum] == PIT_MODE_HIBYTE) || ( (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) && (i8253.bytetoggle[portnum] == 1) ) ) curbyte = 1; + if ( (i8253.accessmode[portnum] == 0) || (i8253.accessmode[portnum] == PIT_MODE_TOGGLE) ) i8253.bytetoggle[portnum] = (~i8253.bytetoggle[portnum]) & 1; + if (curbyte == 0) { //low byte + if (i8253.counter[portnum] < 10) i8253.counter[portnum] = i8253.chandata[portnum]; + i8253.counter[portnum] -= 10; + return ( (uint8_t) i8253.counter[portnum]); + } + else { //high byte + return ( (uint8_t) (i8253.counter[portnum] >> 8) ); + } + break; + } + return (0); +} + +void init8253() { + memset (&i8253, 0, sizeof (i8253) ); +#ifdef MEGA + Timer1.initialize(54925); + Timer1.attachInterrupt(timer_isr, 54925); +#else + //myTimer.begin(timer_isr, 54925); + timer = timerBegin(0, 80, true); // use timer 0, pre-scaler is 80 (divide by 8000), count up + timerAttachInterrupt(timer, &timer_isr, true); + timerAlarmWrite(timer, 54925, true); + timerAlarmEnable(timer); + +#endif + //set_port_write_redirector (0x40, 0x43, &out8253); + //set_port_read_redirector (0x40, 0x43, &in8253); +} + diff --git a/MCUME_esp32/esp8086/main/i8259.cpp b/MCUME_esp32/esp8086/main/i8259.cpp new file mode 100755 index 0000000..f26f2cd --- /dev/null +++ b/MCUME_esp32/esp8086/main/i8259.cpp @@ -0,0 +1,83 @@ +/* i8259.c - emulation code for the Intel 8259 controller. + Note: This is not a very complete i8259 interrupt controller + implementation, but for the purposes of a PC, it's all we need. */ + +#include +#include + +struct structpic { + uint8_t imr; //mask register + uint8_t irr; //request register + uint8_t isr; //service register + uint8_t icwstep; //used during initialization to keep track of which ICW we're at + uint8_t icw[5]; + uint8_t intoffset; //interrupt vector offset + uint8_t priority; //which IRQ has highest priority + uint8_t autoeoi; //automatic EOI mode + uint8_t readmode; //remember what to return on read register from OCW3 + uint8_t enabled; +} i8259; + + +void init8259() { + memset((void *)&i8259, 0, sizeof(i8259)); +} + +uint8_t in8259(uint16_t portnum) { + switch (portnum & 1) { + case 0: + if (i8259.readmode==0) return(i8259.irr); else return(i8259.isr); + case 1: //read mask register + return(i8259.imr); + } + return(0); //can't get here, but the compiler bitches +} + +extern uint32_t makeupticks; +void out8259(uint16_t portnum, uint8_t value) { + uint8_t i; + switch (portnum & 1) { + case 0: + if (value & 0x10) { //begin initialization sequence + i8259.icwstep = 1; + i8259.imr = 0; //clear interrupt mask register + i8259.icw[i8259.icwstep++] = value; + return; + } + if ((value & 0x98)==8) { //it's an OCW3 + if (value & 2) i8259.readmode = value & 2; + } + if (value & 0x20) { //EOI command + for (i=0; i<8; i++) + if ((i8259.isr >> i) & 1) { + i8259.isr ^= (1 << i); + if ((i==0) && (makeupticks>0)) { makeupticks = 0; i8259.irr |= 1; } + return; + } + } + break; + case 1: + if ((i8259.icwstep==3) && (i8259.icw[1] & 2)) i8259.icwstep = 4; //single mode, so don't read ICW3 + if (i8259.icwstep<5) { i8259.icw[i8259.icwstep++] = value; return; } + //if we get to this point, this is just a new IMR value + i8259.imr = value; + break; + } +} + +uint8_t nextintr() { + uint8_t i, tmpirr; + tmpirr = i8259.irr & (~i8259.imr); //XOR request register with inverted mask register + for (i=0; i<8; i++) + if ((tmpirr >> i) & 1) { + i8259.irr ^= (1 << i); + i8259.isr |= (1 << i); + return(i8259.icw[2] + i); + } + return(0); //can't get here, but the compiler bitches +} + +void doirq(uint8_t irqnum) { + i8259.irr |= (1 << irqnum); +} + diff --git a/MCUME_esp32/esp8086/main/ili9341_t3dma.cpp b/MCUME_esp32/esp8086/main/ili9341_t3dma.cpp new file mode 100644 index 0000000..1d92aff --- /dev/null +++ b/MCUME_esp32/esp8086/main/ili9341_t3dma.cpp @@ -0,0 +1,680 @@ +/* + ILI9341 SPI driver inspired from the Teensy version of Frank Bösing, 2017 +*/ + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#include "esp_system.h" +#include "driver/spi_master.h" +#include "soc/gpio_struct.h" +#include "driver/gpio.h" + +#include + +#include "ili9341_t3dma.h" +#include "font8x8.h" + + + +static spi_device_handle_t lcdspi; +static spi_transaction_t trans[MAX_SPI_TRANS]; + +static uint16_t *blocks[NR_OF_BLOCK]; +static uint8_t _rst, _cs, _dc; +static uint8_t _miso, _mosi, _clk; +static uint8_t _touch_irq, _touch_cs; + +//DRAM_ATTR static uint16_t block0[320*LINES_PER_BLOCK]; +//DRAM_ATTR static uint16_t block1[320*LINES_PER_BLOCK]; + +static const lcd_init_cmd_t ili_init_cmds[]={ + {0xEF, {0x03, 0x80, 0x02}, 3}, + {0xCF, {0x00, 0XC1, 0X30}, 3}, + {0xED, {0x64, 0x03, 0X12, 0X81}, 4}, + {0xE8, {0x85, 0x00, 0x78}, 3}, + {0xCB, {0x39, 0x2C, 0x00, 0x34, 0x02}, 5}, + {0xF7, {0x20}, 1}, + {0xEA, {0x00, 0x00}, 2}, + {ILI9341_PWCTR1, {0x23}, 1}, // Power control + {ILI9341_PWCTR2, {0x10}, 1}, // Power control + {ILI9341_VMCTR1, {0x3e, 0x28}, 2}, // VCM control + {ILI9341_VMCTR2, {0x86}, 1}, // VCM control2 + {ILI9341_MADCTL, {0x48}, 1}, // Memory Access Control + {ILI9341_PIXFMT, {0x55}, 1}, + {ILI9341_FRMCTR1, {0x00, 0x18}, 2}, + {ILI9341_DFUNCTR, {0x08, 0x82, 0x27}, 3}, // Display Function Control + {0xF2, {0x00}, 1}, // Gamma Function Disable + {ILI9341_GAMMASET, {0x01}, 1}, // Gamma curve selected + {ILI9341_GMCTRP1, {0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, + 0x4E, 0xF1, 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00}, 15}, // Set Gamma + {ILI9341_GMCTRN1, {0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, + 0x31, 0xC1, 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F}, 15}, // Set Gamma +// 3, 0xb1, 0x00, 0x1f, // FrameRate Control 61Hz + {0xb1, {0x00, 0x10}, 2}, // FrameRate Control 119Hz + {ILI9341_MADCTL, {MADCTL_MX | MADCTL_MY | MADCTL_MV | MADCTL_BGR}, 1}, + + /* Sleep out */ + {ILI9341_SLPOUT, {0}, 0x80}, + /* Display on */ + {ILI9341_DISPON, {0}, 0x80}, + + + // Area width, hight + {ILI9341_CASET, {0, 0, (ILI9341_TFTREALWIDTH)>>8, (ILI9341_TFTREALWIDTH)&0xff}, 4}, + {ILI9341_PASET, {0, 0, (ILI9341_TFTREALHEIGHT)>>8, (ILI9341_TFTREALHEIGHT)&0xff}, 4}, + + {0, {0}, 0xff}, +}; + +static void lcd_cmd(spi_device_handle_t spi, const uint8_t cmd) +{ + esp_err_t ret; + spi_transaction_t t; + memset(&t, 0, sizeof(t)); //Zero out the transaction + t.length=8; //Command is 8 bits + t.tx_buffer=&cmd; //The data is the cmd itself + t.user=(void*)0; //D/C needs to be set to 0 + t.flags=0; + ret=spi_device_polling_transmit(spi, &t); //Transmit! + assert(ret==ESP_OK); //Should have had no issues. +} + + +static void lcd_data(spi_device_handle_t spi, const uint8_t *data, int len) +{ + esp_err_t ret; + spi_transaction_t t; + if (len==0) return; //no need to send anything + memset(&t, 0, sizeof(t)); //Zero out the transaction + t.length=len*8; //Len is in bytes, transaction length is in bits. + t.tx_buffer=data; //Data + t.user=(void*)1; //D/C needs to be set to 1 + t.flags=0; + ret=spi_device_polling_transmit(spi, &t); //Transmit! + assert(ret==ESP_OK); //Should have had no issues. +} + +//This function is called (in irq context!) just before a transmission starts. It will +//set the D/C line to the value indicated in the user field. +static void lcd_spi_pre_transfer_callback(spi_transaction_t *t) +{ + int dc=(int)t->user; + gpio_set_level((gpio_num_t)_dc, dc); +} + + +//Initialize the display +static void lcd_init(spi_device_handle_t spi) +{ + //Initialize non-SPI GPIOs + gpio_set_direction((gpio_num_t)_dc, GPIO_MODE_OUTPUT); + + printf("LCD ILI9341 initialization.\n"); + //Send all the commands + + + //memcpy(ili_init_cmds, ili_init_cmdos, sizeof(ili_init_cmdos)); + int cmd=0; + while (ili_init_cmds[cmd].databytes!=0xff) { + lcd_cmd(spi, ili_init_cmds[cmd].cmd); + lcd_data(spi, ili_init_cmds[cmd].data, ili_init_cmds[cmd].databytes&0x1F); + if (ili_init_cmds[cmd].databytes&0x80) { + vTaskDelay(100 / portTICK_RATE_MS); + } + cmd++; + } + + + + //Allocate memory block buffers and DMA transactions + printf("Allocate video mem and DMA transactions\n"); + + int i=0; + trans[i].tx_data[0]=ILI9341_RAMWR; + trans[i].length=8; + trans[i].user=(void*)0; + trans[i++].flags=SPI_TRANS_USE_TXDATA; + + //blocks[0]= &block0[0]; + //blocks[1]= &block1[0]; + + int remaininglines=ILI9341_TFTREALHEIGHT; + for (int j=0; j 1)*/ blocks[j]= (uint16_t*)heap_caps_malloc(ILI9341_TFTREALWIDTH*lines_per_block*sizeof(uint16_t), MALLOC_CAP_DMA); + assert(blocks[j]!=NULL); + + trans[i].tx_buffer=blocks[j]; + trans[i].length=ILI9341_TFTREALWIDTH*2*8*lines_per_block; + trans[i].user=(void*)1; + trans[i++].flags=0; //undo SPI_TRANS_USE_TXDATA flag + + uint16_t color; + switch (j) { + case 0: + color=0xf000; + break; + case 1: + color=0x0f00; + break; + case 2: + color=0x00f0; + break; + case 3: + default: + color=0x000f; + break; + } + uint16_t * fb = blocks[j]; + for (int y=0;y>6]; + return(&block[(j&0x3F)*ILI9341_TFTREALWIDTH]); +} + + +void ILI9341_t3DMA::fillScreen(uint16_t color) { + int i,j; + color=SPI_SWAP_DATA_TX(color,16); + for (j=0; j>6]; + uint16_t * dst=&block[(j&0x3F)*ILI9341_TFTREALWIDTH]; + for (i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH]; + src=buffer; + for (i=0; i>6]; + dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH]; + src=buffer; + for (i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH+(ILI9341_TFTREALWIDTH-width)/2]; + src=buffer; + for (i=0; i>6]; + dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH+(ILI9341_TFTREALWIDTH-width)/2]; + src=buffer; + for (i=0; i height) + y += (ILI9341_TFTHEIGHT - height)/2; + uint8_t * src=buf; + uint16_t * block=blocks[y>>6]; + uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH]; + if (ILI9341_TFTWIDTH > width) + dst += (ILI9341_TFTWIDTH - width)/2; + for (int i=0; i height) + y += (ILI9341_TFTHEIGHT - height)/2; + uint16_t * src=buf; + uint16_t * block=blocks[y>>6]; + uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH]; + if (ILI9341_TFTWIDTH > width) + dst += (ILI9341_TFTWIDTH - width)/2; + for (int i=0; i>6]; + uint16_t * dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+x]; + for (i=0; i(arx+arw)) || ((x+w)(ary+arh)) || ((y+h) arx) && (x<(arx+arw)) ) { + arw = arw - (x-arx); + arx = arx + (x-arx); + } else { + bmp_offx = arx; + } + if ( ((x+w) > arx) && ((x+w)<(arx+arw)) ) { + arw -= (arx+arw-x-w); + } + if ( (y > ary) && (y<(ary+arh)) ) { + arh = arh - (y-ary); + ary = ary + (y-ary); + } else { + bmp_offy = ary; + } + if ( ((y+h) > ary) && ((y+h)<(ary+arh)) ) { + arh -= (ary+arh-y-h); + } + } + + + int l=ary; + bitmap = bitmap + bmp_offy*w + bmp_offx; + for (int row=0;row>6]; + uint16_t * dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+arx]; + bmp_ptr = (uint16_t*)bitmap; + for (int col=0;col>6]; + dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+x]; + bits = *charpt; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + l++; + } + block=blocks[l>>6]; + dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+x]; + bits = *charpt++; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + l++; + } + x +=8; + } +} + + + +// TOUCH +#define _BV(bit) (1 << (bit)) +#define XPT2046_CFG_START _BV(7) +#define XPT2046_CFG_MUX(v) ((v&0b111) << (4)) +#define XPT2046_CFG_8BIT _BV(3) +#define XPT2046_CFG_12BIT (0) +#define XPT2046_CFG_SER _BV(2) +#define XPT2046_CFG_DFR (0) +#define XPT2046_CFG_PWR(v) ((v&0b11)) +#define XPT2046_MUX_Y 0b101 +#define XPT2046_MUX_X 0b001 +#define XPT2046_MUX_Z1 0b011 +#define XPT2046_MUX_Z2 0b100 + + + +static spi_device_handle_t touchspi; + +//void ILI9341_t3DMA::touchBegin(uint8_t mosi, uint8_t miso, uint8_t clk, uint8_t cs) { +void ILI9341_t3DMA::touchBegin() { + esp_err_t ret; + + gpio_set_direction((gpio_num_t)_touch_irq, GPIO_MODE_INPUT); + gpio_set_pull_mode((gpio_num_t)_touch_irq, GPIO_PULLUP_ONLY); + + spi_device_interface_config_t devcfg; + memset(&devcfg, 0, sizeof(devcfg)); + devcfg.clock_speed_hz=2500000; + devcfg.mode=0; + devcfg.spics_io_num=_touch_cs; + devcfg.queue_size=2; + devcfg.flags = SPI_DEVICE_HALFDUPLEX ; + + /* + spi_bus_config_t buscfg; + memset(&buscfg, 0, sizeof(buscfg)); + buscfg.miso_io_num=miso; + buscfg.mosi_io_num=mosi; + buscfg.sclk_io_num=clk; + buscfg.quadwp_io_num=-1; + buscfg.quadhd_io_num=-1; + buscfg.max_transfer_sz=48; + + ret=spi_bus_initialize(HSPI_HOST, &buscfg, 2); + ESP_ERROR_CHECK(ret); + */ + + ret=spi_bus_add_device(HSPI_HOST, &devcfg, &touchspi); + ESP_ERROR_CHECK(ret); +} + + +uint16_t touch_get_data(spi_device_handle_t spi, const uint8_t cmd) +{ + spi_transaction_t t; + memset(&t, 0, sizeof(t)); //Zero out the transaction + t.length=8; //Command is 8 bits + t.tx_buffer=&cmd; //The data is the cmd itself + esp_err_t ret=spi_device_polling_transmit(spi, &t); //Transmit! + if (ret==ESP_OK) { + memset(&t, 0, sizeof(t)); + t.rxlength=8*2; + t.flags = SPI_TRANS_USE_RXDATA; + ret = spi_device_polling_transmit(spi, &t); + if (ret==ESP_OK) { + printf("touch data failed\n"); + return 0; + } + } + else { + printf("touch cmd failed\n"); + } + return *(uint16_t*)t.rx_data; +} + + + +bool ILI9341_t3DMA::isTouching() +{ + return ((gpio_get_level((gpio_num_t)_touch_irq) == 0 ? true : false)); +} + +void ILI9341_t3DMA::readRo(uint16_t * oX, uint16_t * oY, uint16_t * oZ) { + uint16_t x = 0; + uint16_t y = 0; + uint16_t z1 = 0; + uint16_t z2 = 0; + uint8_t i = 0; + int16_t xraw=0, yraw=0; + + + for(; i < 15; i++) { + y += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Y) | XPT2046_CFG_PWR(3))); + x += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_X) | XPT2046_CFG_PWR(3))); + z1 += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z1)| XPT2046_CFG_PWR(3))); + z2 += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z2)| XPT2046_CFG_PWR(3))); + } + printf("%d %d %d %d \n",x/15,y/15,z1/15,z2/15); +/* + SPI.beginTransaction(SPI_SETTING); + digitalWrite(_touch_cs, LOW); + + for(; i < 15; i++) { + // SPI requirer 32bit aliment + uint8_t buf[12] = { + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Y) | XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_X) | XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z1)| XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z2)| XPT2046_CFG_PWR(3)), 0x00, 0x00 + }; + SPI.transfer(&buf[0], &buf[0], 12); + y += (buf[1] << 8 | buf[2])>>3; + x += (buf[4] << 8 | buf[5])>>3; + z1 += (buf[7] << 8 | buf[8])>>3; + z2 += (buf[10] << 8 | buf[11])>>3; + } + */ +} + +void ILI9341_t3DMA::readRaw(uint16_t * oX, uint16_t * oY, uint16_t * oZ) { + +} + +void ILI9341_t3DMA::readCal(uint16_t * oX, uint16_t * oY, uint16_t * oZ){ + +} + +void ILI9341_t3DMA::callibrateTouch(uint16_t xMin,uint16_t yMin,uint16_t xMax,uint16_t yMax){ + +} + + diff --git a/MCUME_esp32/esp8086/main/ili9341_t3dma.h b/MCUME_esp32/esp8086/main/ili9341_t3dma.h new file mode 100644 index 0000000..6f09662 --- /dev/null +++ b/MCUME_esp32/esp8086/main/ili9341_t3dma.h @@ -0,0 +1,154 @@ +/* + ILI9341 SPI driver inspired from the Teensy version of Frank Bösing, 2017 +*/ + +#ifndef _ILI9341_T3DMAH_ +#define _ILI9341_T3DMAH_ + + +#define FLIP_SCREEN 1 + + +#define RGBVAL32(r,g,b) ( (r<<16) | (g<<8) | b ) +#define RGBVAL16(r,g,b) ( (((r>>3)&0x1f)<<11) | (((g>>2)&0x3f)<<5) | (((b>>3)&0x1f)<<0) ) +#define RGBVAL8(r,g,b) ( (((r>>5)&0x07)<<5) | (((g>>5)&0x07)<<2) | (((b>>6)&0x3)<<0) ) + + +#define ILI9341_TFTWIDTH 320 +#define ILI9341_TFTHEIGHT 200 +#define ILI9341_TFTREALWIDTH 320 +#define ILI9341_TFTREALHEIGHT 240 + + +#define ILI9341_NOP 0x00 +#define ILI9341_SWRESET 0x01 +#define ILI9341_RDDID 0x04 +#define ILI9341_RDDST 0x09 + +#define ILI9341_SLPIN 0x10 +#define ILI9341_SLPOUT 0x11 +#define ILI9341_PTLON 0x12 +#define ILI9341_NORON 0x13 + +#define ILI9341_RDMODE 0x0A +#define ILI9341_RDMADCTL 0x0B +#define ILI9341_RDPIXFMT 0x0C +#define ILI9341_RDIMGFMT 0x0D +#define ILI9341_RDSELFDIAG 0x0F + +#define ILI9341_INVOFF 0x20 +#define ILI9341_INVON 0x21 +#define ILI9341_GAMMASET 0x26 +#define ILI9341_DISPOFF 0x28 +#define ILI9341_DISPON 0x29 + +#define ILI9341_CASET 0x2A +#define ILI9341_PASET 0x2B +#define ILI9341_RAMWR 0x2C +#define ILI9341_RAMRD 0x2E + +#define ILI9341_PTLAR 0x30 +#define ILI9341_MADCTL 0x36 +#define ILI9341_VSCRSADD 0x37 +#define ILI9341_PIXFMT 0x3A + +#define ILI9341_FRMCTR1 0xB1 +#define ILI9341_FRMCTR2 0xB2 +#define ILI9341_FRMCTR3 0xB3 +#define ILI9341_INVCTR 0xB4 +#define ILI9341_DFUNCTR 0xB6 + +#define ILI9341_PWCTR1 0xC0 +#define ILI9341_PWCTR2 0xC1 +#define ILI9341_PWCTR3 0xC2 +#define ILI9341_PWCTR4 0xC3 +#define ILI9341_PWCTR5 0xC4 +#define ILI9341_VMCTR1 0xC5 +#define ILI9341_VMCTR2 0xC7 + +#define ILI9341_RDID1 0xDA +#define ILI9341_RDID2 0xDB +#define ILI9341_RDID3 0xDC +#define ILI9341_RDID4 0xDD + +#define ILI9341_GMCTRP1 0xE0 +#define ILI9341_GMCTRN1 0xE1 + +#define MADCTL_MY 0x80 +#define MADCTL_MX 0x40 +#define MADCTL_MV 0x20 +#define MADCTL_ML 0x10 +#define MADCTL_RGB 0x00 +#define MADCTL_BGR 0x08 +#define MADCTL_MH 0x04 + +#ifdef __cplusplus + + +#define MAX_SPI_TRANS 7 +#define NR_OF_BLOCK 4 +#define LINES_PER_BLOCK 64 //(ILI9341_TFTREALHEIGHT/4) + +typedef struct { + uint8_t cmd; + uint8_t data[16]; + uint8_t databytes; //No of data in data; bit 7 = delay after set; 0xFF = end of cmds. +} lcd_init_cmd_t; + + +class ILI9341_t3DMA +{ + public: + ILI9341_t3DMA(uint8_t _CS = 17, uint8_t _DC = 18, uint8_t _RST = 255, uint8_t _MOSI=23, uint8_t _CLK=18, uint8_t _MISO=19, uint8_t touch_cs=32, uint8_t touch_irq=33); + + //void setFrameBuffer(uint16_t * fb); + //static uint16_t * getFrameBuffer(void); + + void begin(void); + void flipscreen(bool flip); + bool isflipped(void); + void start(void); + void refresh(void); + void refreshPrepare(void); + void refreshFinish(void); + //void stop(); + //void wait(void); + uint16_t * getLineBuffer(int j); + + void fillScreen(uint16_t color); + void writeScreen(int width, int height, int stride, uint8_t *buffer, uint16_t *palette16); + void writeLine(int width, int height, int stride, uint8_t *buffer, uint16_t *palette16); + void writeLine(int width, int height, int stride, uint16_t *buffer); + void drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color); + void drawSprite(int16_t x, int16_t y, const uint16_t *bitmap); + void drawSprite(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh); + void drawText(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize); + + void fillScreenNoDma(uint16_t color) { fillScreen(color); }; + void drawSpriteNoDma(int16_t x, int16_t y, const uint16_t *bitmap) { drawSprite(x,y,bitmap); }; + void drawSpriteNoDma(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh) { drawSprite(x,y,bitmap,croparx,cropary,croparw,croparh); }; + void drawRectNoDma(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color) { drawRect(x,y,w,h,color); }; + void drawTextNoDma(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize) { drawText(x,y,text,fgcolor,bgcolor,doublesize); }; + + /* + void writeScreenNoDma(const uint16_t *pcolors); + void drawPixel(int16_t x, int16_t y, uint16_t color); + uint16_t getPixel(int16_t x, int16_t y); + */ + + + void touchBegin(); + void readRo(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + bool isTouching(); + void readRaw(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + void readCal(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + void callibrateTouch(uint16_t xMin,uint16_t yMin,uint16_t xMax,uint16_t yMax); + + protected: + bool flipped=false; + void enableTouchIrq(); +}; + +#endif +#endif + diff --git a/MCUME_esp32/esp8086/main/iopins.h b/MCUME_esp32/esp8086/main/iopins.h new file mode 100644 index 0000000..703f6e1 --- /dev/null +++ b/MCUME_esp32/esp8086/main/iopins.h @@ -0,0 +1,59 @@ +#ifndef IOPINS_H +#define IOPINS_H + +// ILI9341 +//#define PIN_NUM_CS (gpio_num_t)15 +//#define PIN_NUM_CLK (gpio_num_t)14 +//#define PIN_NUM_MISO (gpio_num_t)12 +//#define PIN_NUM_MOSI (gpio_num_t)13 +//#define PIN_NUM_DC (gpio_num_t)16 + +#define TPIN_NUM_CS (gpio_num_t)32 +#define TPIN_NUM_IRQ (gpio_num_t)33 + + +#define PIN_NUM_CS (gpio_num_t)22 //17 +#define PIN_NUM_CLK (gpio_num_t)18 +#define PIN_NUM_MISO (gpio_num_t)19 +#define PIN_NUM_MOSI (gpio_num_t)23 +#define PIN_NUM_DC (gpio_num_t)21 + +// SD card SPI +#define SPIN_NUM_CS (gpio_num_t)15 +#define SPIN_NUM_CLK (gpio_num_t)14 +#define SPIN_NUM_MISO (gpio_num_t)12 +#define SPIN_NUM_MOSI (gpio_num_t)13 + + +// I2C keyboard +#define I2C_SCL_IO (gpio_num_t)5 +#define I2C_SDA_IO (gpio_num_t)4 + + +// Analog joystick (primary) for JOY2 and 5 extra buttons +#define PIN_JOY2_A1X ADC2_CHANNEL_7 // 27 //ADC1_CHANNEL_0 +#define PIN_JOY2_A2Y ADC2_CHANNEL_2 // 2 //ADC1_CHANNEL_3 +#define PIN_JOY2_BTN 32 + +#define PIN_KEY_USER1 35 +#define PIN_KEY_USER2 34 +#define PIN_KEY_USER3 39 +#define PIN_KEY_USER4 36 +/* +#define PIN_KEY_ESCAPE 23 +*/ + +// Second joystick +/* +#define PIN_JOY1_BTN 30 +#define PIN_JOY1_1 16 +#define PIN_JOY1_2 17 +#define PIN_JOY1_3 18 +#define PIN_JOY1_4 19 +*/ + +#endif + + + + diff --git a/MCUME_esp32/esp8086/main/keyboard_osd.h b/MCUME_esp32/esp8086/main/keyboard_osd.h new file mode 100644 index 0000000..062eb4e --- /dev/null +++ b/MCUME_esp32/esp8086/main/keyboard_osd.h @@ -0,0 +1,20 @@ + +#ifndef keyboard_osd_h_ +#define keyboard_osd_h_ + +extern bool virtualkeyboardIsActive(void); +extern void drawVirtualkeyboard(void); +extern void toggleVirtualkeyboard(bool keepOn); +extern void handleVirtualkeyboard(void); + +extern bool callibrationActive(void); +extern int handleCallibration(uint16_t bClick); + +extern bool menuActive(void); +extern char * menuSelection(void); +extern void toggleMenu(bool on); +extern int handleMenu(uint16_t bClick); + + +#endif + diff --git a/MCUME_esp32/esp8086/main/main.c b/MCUME_esp32/esp8086/main/main.c new file mode 100644 index 0000000..5dc5bee --- /dev/null +++ b/MCUME_esp32/esp8086/main/main.c @@ -0,0 +1,31 @@ + +#include "freertos/FreeRTOS.h" +#include "esp_wifi.h" +#include "esp_system.h" +#include "esp_event.h" +#include "esp_event_loop.h" +#include "nvs_flash.h" +#include "driver/gpio.h" +#include "esp_partition.h" + +#include "go.h" + + +int app_main(void) +{ + printf("Test start!\n"); + + setup(); + while(1) { + loop(); + } + + for (int i = 10; i >= 0; i--) { + printf("Restarting in %d seconds...\n", i); + vTaskDelay(1000 / portTICK_PERIOD_MS); + } + printf("Restarting now.\n"); + fflush(stdout); + esp_restart(); +} + diff --git a/MCUME_esp32/esp8086/main/network.cpp b/MCUME_esp32/esp8086/main/network.cpp new file mode 100755 index 0000000..3c10ff5 --- /dev/null +++ b/MCUME_esp32/esp8086/main/network.cpp @@ -0,0 +1,146 @@ + +#include +#include + +#include "emu.h" + + +#ifdef USE_ENC28J60 +#include + +byte ENC28J60::buffer[1514]; +//uint8_t net_mac[6] = { 0x90, 0xAD, 0xBE, 0xEF, 0x13, 0x37 }; +uint8_t net_mac[6] = { 0x2C, 0xFD, 0x13, 0x37, 0x13, 0x37 }; + +extern union _bytewordregs_ regs; +extern uint16_t segregs[6]; + +struct netstruct { + uint8_t enabled; + uint8_t canrecv; + uint16_t pktlen; +} net; + +void net_handler() { + uint32_t i; + uint16_t j; + //if (ethif==254) return; //networking not enabled + switch (regs.byteregs[regah]) { //function number + case 0x00: //enable packet reception + net.enabled = 1; + net.canrecv = 1; + return; + case 0x01: //send packet of CX at DS:SI + //if (verbose) { + //Serial.println("Sending packet of %u bytes.", regs.wordregs[regcx]); + //} + //sendpkt (&RAM[ ( (uint32_t) segregs[regds] << 4) + (uint32_t) regs.wordregs[regsi]], regs.wordregs[regcx]); + i = ( (uint32_t) segregs[regds] << 4) + (uint32_t) regs.wordregs[regsi]; + for (j=0; j 0) { + for (i=0; i +#include "emu.h" + +volatile uint16_t pit0counter = 65535; +volatile uint32_t speakercountdown, latch42, pit0latch, pit0command, pit0divisor; +uint8_t portram[0x400]; +uint8_t crt_controller_idx, crt_controller[256], port3D9 = 0; + +void portout(uint16_t portnum, uint16_t value) { + if (portnum < 0x400) portram[portnum] = value; + switch (portnum) { + case 0x20: + case 0x21: //i8259 + out8259(portnum, value); + return; + case 0x40: + case 0x41: + case 0x42: + case 0x43: //i8253 + out8253(portnum, value); + break; + case 0x3D4: + crt_controller_idx = value; + break; + case 0x3D5: + crt_controller[crt_controller_idx] = value; + if ((crt_controller_idx == 0x0E) || (crt_controller_idx == 0x0F)) { + //setcursor(((uint16_t)crt_controller[0x0E] << 8) | crt_controller[0x0F]); + //Serial.write(27); Serial.write('['); Serial.print(crt_controller[0x0E] + 1); Serial.write(';'); Serial.print(crt_controller[0x0F] + 1); Serial.write('H'); + } + break; + case 0x3D9: + port3D9 = value; + break; + } + +#ifdef ADVANCED_CLIENT + if ((portnum >= 0x3C0) && (portnum <= 0x3DA)) { + uint8_t chksum; + Serial.write(0xFF); + Serial.write(0x04); + outByte(portnum & 0xFF); chksum = portnum & 0xFF; + outByte(portnum >> 8); chksum += portnum >> 8; + outByte(value); chksum += value; + outByte(chksum); + Serial.write(0xFE); + Serial.write(0x02); + } +#endif + +#ifdef VGA + if ((portnum >= 0x3C0) && (portnum <= 0x3DA)) outVGA(portnum, value); +#endif +} + +uint16_t portin(uint16_t portnum) { +#ifdef VGA + if ((portnum >= 0x3C0) && (portnum <= 0x3DA)) return inVGA(portnum); +#endif +/* uint8_t chksum; + Serial.write(0xFF); + Serial.write(0x07); + outByte(portnum & 0xFF); chksum = portnum & 0xFF; + outByte((portnum >> 8) & 0xFF); chksum += (portnum >> 8) & 0xFF; + outByte(chksum); + Serial.write(0xFE); + Serial.write(0x02);*/ + switch (portnum) { + case 0x20: + case 0x21: //i8259 + return (in8259(portnum)); + case 0x40: + case 0x41: + case 0x42: + case 0x43: //i8253 + return in8253(portnum); + case 0x60: + case 0x64: + return portram[portnum]; + case 0x3D4: + return crt_controller_idx; + break; + case 0x3D5: + return crt_controller[crt_controller_idx]; + break; + case 0x3DA: + port3da ^= 1; + if (!(port3da & 1)) port3da ^= 8; + //port3da = random(256) & 9; + return (port3da); + default: + return (0xFF); + } +} + + diff --git a/MCUME_esp32/esp8086/main/ps2.h b/MCUME_esp32/esp8086/main/ps2.h new file mode 100755 index 0000000..dc6f578 --- /dev/null +++ b/MCUME_esp32/esp8086/main/ps2.h @@ -0,0 +1,89 @@ +uint8_t translatescancode(uint32_t keysym) { + if ((keysym >= 'a') && (keysym <= 'z')) { + keysym -= 0x20; + } + switch (keysym) { + case 0xFF08: return 0x0E; //backspace + case 0xFF09: return 0x0F; //tab + case 0xFF0D: return 0x1C; //enter + case 0xFF1B: return 0x01; //escape + case 0xFF63: return 0x52; //KP 0 / insert + case 0xFFFF: return 0x53; //KP . / delete + case 0xFF55: return 0x49; //pgup + case 0xFF56: return 0x51; //pgdn + case 0xFF50: return 0x47; //home + case 0xFF57: return 0x4F; //end + case 'A': return 0x1E; + case 'B': return 0x30; + case 'C': return 0x2E; + case 'D': return 0x20; + case 'E': return 0x12; + case 'F': return 0x21; + case 'G': return 0x22; + case 'H': return 0x23; + case 'I': return 0x17; + case 'J': return 0x24; + case 'K': return 0x25; + case 'L': return 0x26; + case 'M': return 0x32; + case 'N': return 0x31; + case 'O': return 0x18; + case 'P': return 0x19; + case 'Q': return 0x10; + case 'R': return 0x13; + case 'S': return 0x1F; + case 'T': return 0x14; + case 'U': return 0x16; + case 'V': return 0x2F; + case 'W': return 0x11; + case 'X': return 0x2D; + case 'Y': return 0x15; + case 'Z': return 0x2C; + case '0': case ')': return 0x0B; + case '1': case '!': return 0x02; + case '2': case '@': return 0x03; + case '3': case '#': return 0x04; + case '4': case '$': return 0x05; + case '5': case '%': return 0x06; + case '6': case '^': return 0x07; + case '7': case '&': return 0x08; + case '8': case '*': return 0x09; + case '9': case '(': return 0x0A; + case '`': case '~': return 0x29; + case '-': case '_': return 0x0C; + case '=': case '+': return 0x0D; + case '[': case '{': return 0x1A; + case ']': case '}': return 0x1B; + case '\\': case '|': return 0x2B; + case ';': case ':': return 0x27; + case '\'': case '"': return 0x28; + case ' ': return 0x39; + case ',': case '<': return 0x33; + case '.': case '>': return 0x34; + case '/': case '?': return 0x35; + case 0xFFBE: return 0x3B; //F1 + case 0xFFBF: return 0x3C; //F2 + case 0xFFC0: return 0x3D; //F3 + case 0xFFC1: return 0x3E; //F4 + case 0xFFC2: return 0x3F; //F5 + case 0xFFC3: return 0x40; //F6 + case 0xFFC4: return 0x41; //F7 + case 0xFFC5: return 0x42; //F8 + case 0xFFC6: return 0x43; //F9 + case 0xFFC7: return 0x44; //F10 + case 0xFFC8: return 0x57; //F11 + case 0xFFC9: return 0x58; //F12 + case 0xFFE1: return 0x2A; //left shift + case 0xFFE2: return 0x36; //right shift + case 0xFFE3: case 0xFFE4: return 0x1D; //control + case 0xFFE9: case 0xFFEA: return 0x38; //alt + case 0xFF51: return 0x4B; //left + case 0xFF52: return 0x48; //up + case 0xFF53: return 0x4D; //right + case 0xFF54: return 0x50; //down + } + return 0xFF; +} + + + diff --git a/MCUME_esp32/esp8086/main/rom.h b/MCUME_esp32/esp8086/main/rom.h new file mode 100755 index 0000000..1aac54b --- /dev/null +++ b/MCUME_esp32/esp8086/main/rom.h @@ -0,0 +1,3748 @@ +#ifdef MEGA + const uint8_t BIOS[8192] PROGMEM = { +#else + const uint8_t BIOS[8192] = { +#endif + 0x54, 0x75, 0x72, 0x62, 0x6F, 0x20, 0x58, 0x54, 0x20, 0x42, 0x49, + 0x4F, 0x53, 0x20, 0x76, 0x32, 0x2E, 0x35, 0x20, 0x66, 0x6F, 0x72, + 0x20, 0x38, 0x30, 0x38, 0x38, 0x2F, 0x56, 0x32, 0x30, 0x00, 0xC3, + 0x20, 0x45, 0x47, 0x41, 0x2F, 0x56, 0x47, 0x41, 0x20, 0x47, 0x72, + 0x61, 0x70, 0x68, 0x69, 0x63, 0x73, 0x00, 0xC3, 0x20, 0x50, 0x61, + 0x72, 0x61, 0x6C, 0x6C, 0x65, 0x6C, 0x20, 0x50, 0x6F, 0x72, 0x74, + 0x20, 0x61, 0x74, 0x20, 0x00, 0xC3, 0x20, 0x47, 0x61, 0x6D, 0x65, + 0x20, 0x50, 0x6F, 0x72, 0x74, 0x20, 0x61, 0x74, 0x20, 0x32, 0x30, + 0x31, 0x68, 0x00, 0xB8, 0x40, 0x00, 0x8E, 0xD8, 0xC7, 0x06, 0x72, + 0x00, 0x00, 0x00, 0xFA, 0xFC, 0xB0, 0x00, 0xE6, 0xA0, 0xBA, 0xD8, + 0x03, 0xEE, 0xBA, 0xB8, 0x03, 0xFE, 0xC0, 0xEE, 0xB0, 0x99, 0xE6, + 0x63, 0xB0, 0xA5, 0xE6, 0x61, 0xB0, 0x54, 0xE6, 0x43, 0xB0, 0x12, + 0xE6, 0x41, 0xB0, 0x40, 0xE6, 0x43, 0xB0, 0x00, 0xE6, 0x81, 0xE6, + 0x82, 0xE6, 0x83, 0xE6, 0x0D, 0xB0, 0x58, 0xE6, 0x0B, 0xB0, 0x41, + 0xE6, 0x0B, 0xB0, 0x42, 0xE6, 0x0B, 0xB0, 0x43, 0xE6, 0x0B, 0xB0, + 0xFF, 0xE6, 0x01, 0xE6, 0x01, 0xB0, 0x00, 0xE6, 0x08, 0xE6, 0x0A, + 0xB0, 0x36, 0xE6, 0x43, 0xB0, 0x00, 0xE6, 0x40, 0xE6, 0x40, 0xBA, + 0x13, 0x02, 0xB0, 0x01, 0xEE, 0xB8, 0x40, 0x00, 0x8E, 0xD8, 0x8B, + 0x36, 0x72, 0x00, 0x33, 0xC0, 0x8B, 0xE8, 0x8B, 0xD8, 0xBA, 0xAA, + 0x55, 0xFC, 0x33, 0xFF, 0x8E, 0xC3, 0x26, 0x89, 0x15, 0x26, 0x3B, + 0x15, 0x75, 0x0D, 0xB9, 0x00, 0x20, 0xF3, 0xAB, 0x80, 0xC7, 0x04, + 0x80, 0xFF, 0xA0, 0x72, 0xE7, 0x33, 0xC0, 0x8E, 0xC0, 0xB8, 0x80, + 0x00, 0x8E, 0xD0, 0xBC, 0x00, 0x01, 0x55, 0x53, 0xBD, 0x02, 0x00, + 0xE8, 0x19, 0x19, 0x89, 0x36, 0x72, 0x00, 0x58, 0xB1, 0x06, 0xD3, + 0xE8, 0xA3, 0x13, 0x00, 0x58, 0x73, 0x02, 0x0C, 0x10, 0xA2, 0x15, + 0x00, 0x33, 0xC0, 0x50, 0x50, 0x50, 0x50, 0x50, 0xB8, 0x30, 0x00, + 0x8E, 0xD0, 0xBC, 0x00, 0x01, 0x1E, 0xBB, 0x00, 0xE0, 0x0E, 0x1F, + 0xB4, 0x01, 0xE8, 0xDE, 0x18, 0x1F, 0x74, 0x05, 0x80, 0x0E, 0x15, + 0x00, 0x01, 0xFA, 0xB0, 0x13, 0xE6, 0x20, 0xB0, 0x08, 0xE6, 0x21, + 0xB0, 0x09, 0xE6, 0x21, 0xB0, 0xFF, 0xE6, 0x21, 0x1E, 0x33, 0xC0, + 0x8E, 0xC0, 0x0E, 0x1F, 0xB9, 0x08, 0x00, 0x33, 0xFF, 0xB8, 0x23, + 0xFF, 0xAB, 0x8C, 0xC8, 0xAB, 0xE2, 0xF7, 0xBE, 0xF3, 0xFE, 0xB9, + 0x18, 0x00, 0xA5, 0x8C, 0xC8, 0xAB, 0xE2, 0xFA, 0xB8, 0x00, 0xF6, + 0x8E, 0xD8, 0x33, 0xDB, 0xB4, 0x04, 0x8B, 0xEC, 0x0E, 0xBA, 0x88, + 0xE1, 0x52, 0xBA, 0x90, 0xEA, 0x52, 0xBA, 0x8B, 0x17, 0x52, 0x16, + 0x8B, 0xD4, 0x83, 0xC2, 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0x69, 0x6D, 0x65, 0x72, 0x00, 0xFF, 0x52, + 0x33, 0xD2, 0x8A, 0xE2, 0xB0, 0x0A, 0xCD, 0x17, 0xB4, 0x00, 0xB0, + 0x0D, 0xCD, 0x17, 0x5A, 0xC3, 0xC7, 0x06, 0x60, 0x00, 0x07, 0x06, + 0x80, 0x3E, 0x49, 0x00, 0x07, 0x75, 0x06, 0xC7, 0x06, 0x60, 0x00, + 0x0C, 0x0B, 0xC3, 0xEA, 0x5B, 0xE0, 0x00, 0xF0, 0x30, 0x35, 0x2F, + 0x30, 0x32, 0x2F, 0x31, 0x32, 0xFF, 0xFE, 0xE2 +}; + +#ifdef INCLUDE_ROM_BASIC +#ifdef MEGA + const uint8_t BASICL[16384] PROGMEM = { +#else + const uint8_t BASICL[16384] = { +#endif + 0xE9, 0x8F, 0x7E, 0xE8, 0xA7, 0x6B, 0xCB, 0xE8, 0x2, 0x65, 0xCB, + 0x5D, 0xE8, 0xC7, 0x2F, 0x74, 0xD, 0x8B, 0x36, 0xE9, 0x4, 0x8A, + 0x44, 0x2E, 0x3C, 0xFE, 0x74, 0x2, 0x3C, 0xFD, 0xC3, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x33, 0x2E, 0x94, 0xD, 0x68, 0x73, 0x5B, + 0x11, 0x59, 0x15, 0x66, 0x37, 0x3E, 0x16, 0x8F, 0x11, 0xED, 0x10, + 0xB6, 0x10, 0xF8, 0x12, 0xC, 0x2E, 0xCE, 0x10, 0x35, 0x11, 0x5F, + 0x11, 0x2D, 0x2E, 0x48, 0x13, 0x50, 0x2F, 0x35, 0x1F, 0x1B, 0x2D, + 0xFE, 0x11, 0x58, 0x1E, 0xF0, 0x1B, 0x91, 0x22, 0x85, 0x2E, 0xBE, + 0x7, 0xBE, 0x7, 0x53, 0x1E, 0x43, 0x13, 0x2E, 0x1F, 0x0, 0x0, + 0x8A, 0x1E, 0x5F, 0x11, 0x9C, 0x2E, 0x9D, 0x2E, 0xA3, 0x2E, 0xF3, + 0x2E, 0xDF, 0x36, 0xA9, 0x12, 0x58, 0x12, 0x39, 0x22, 0xB8, 0x12, + 0xD8, 0x22, 0xFB, 0xF, 0xFE, 0xF, 0x1, 0x10, 0x4, 0x10, 0xD9, + 0x14, 0x4, 0x3D, 0x30, 0x3D, 0xA0, 0x5D, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0xA9, 0x3D, 0x3F, 0x24, 0x9E, 0x24, 0x4, 0x40, 0x52, + 0x43, 0x6C, 0x41, 0x6D, 0x41, 0xCE, 0x41, 0x2F, 0x53, 0xE7, 0x52, + 0x26, 0x5D, 0x13, 0x46, 0x33, 0x46, 0x29, 0x58, 0xD, 0x58, 0xD1, + 0x47, 0xCD, 0x47, 0x93, 0x51, 0x2A, 0x50, 0x17, 0x54, 0x68, 0x29, + 0xA5, 0x29, 0xB1, 0x29, 0x1C, 0x65, 0x80, 0x7E, 0x96, 0x7D, 0xF1, + 0x70, 0x87, 0x78, 0xE, 0x7A, 0xC, 0x73, 0x84, 0x62, 0xF4, 0x79, + 0xAD, 0x7A, 0xCD, 0x7A, 0x8C, 0x2B, 0x3D, 0x1E, 0x7A, 0x1B, 0xE8, + 0x28, 0x17, 0x26, 0xE9, 0x29, 0xF8, 0x28, 0xB, 0x29, 0x80, 0x22, + 0x47, 0x29, 0xD, 0x26, 0x12, 0x26, 0x75, 0x1B, 0xAD, 0x6B, 0x51, + 0x6B, 0x82, 0x6B, 0x9C, 0x65, 0xFA, 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0x46, 0x49, 0x4E, + 0xD4, 0xAD, 0x45, 0x46, 0x53, 0x4E, 0xC7, 0xAE, 0x45, 0x46, 0x44, + 0x42, 0xCC, 0xAF, 0x45, 0xC6, 0x97, 0x0, 0x4C, 0x53, 0xC5, 0xA1, + 0x4E, 0xC4, 0x81, 0x52, 0x41, 0x53, 0xC5, 0xA5, 0x44, 0x49, 0xD4, + 0xA6, 0x52, 0x52, 0x4F, 0xD2, 0xA7, 0x52, 0xCC, 0xD4, 0x52, 0xD2, + 0xD5, 0x58, 0xD0, 0xB, 0x4F, 0xC6, 0x23, 0x51, 0xD6, 0xF1, 0x0, + 0x4F, 0xD2, 0x82, 0xCE, 0xD1, 0x52, 0xC5, 0xF, 0x49, 0xD8, 0x1F, + 0x0, 0x4F, 0x54, 0xCF, 0x89, 0x4F, 0x20, 0x54, 0xCF, 0x89, 0x4F, + 0x53, 0x55, 0xC2, 0x8D, 0x0, 0x45, 0x58, 0xA4, 0x1A, 0x0, 0x4E, + 0x50, 0x55, 0xD4, 0x85, 0xC6, 0x8B, 0x4E, 0x53, 0x54, 0xD2, 0xD8, + 0x4E, 0xD4, 0x5, 0x4E, 0xD0, 0x10, 0x4D, 0xD0, 0xF2, 0x4E, 0x4B, + 0x45, 0x59, 0xA4, 0xDE, 0x0, 0x0, 0x45, 0xD9, 0xC9, 0x0, 0x4F, + 0x43, 0x41, 0x54, 0xC5, 0xCA, 0x50, 0x52, 0x49, 0x4E, 0xD4, 0x9D, + 0x4C, 0x49, 0x53, 0xD4, 0x9E, 0x50, 0x4F, 0xD3, 0x1B, 0x45, 0xD4, + 0x88, 0x49, 0x4E, 0xC5, 0xB0, 0x4F, 0x41, 0xC4, 0xBC, 0x49, 0x53, + 0xD4, 0x93, 0x4F, 0xC7, 0xA, 0x4F, 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0x8A, 0x7, 0xA, 0xC0, 0xF9, 0xC3, 0x4B, + 0xE8, 0x35, 0xCF, 0x3C, 0x23, 0x75, 0x3, 0xE8, 0x2E, 0xCF, 0xE8, + 0x2A, 0xDF, 0x5E, 0x87, 0xDE, 0x56, 0x53, 0xE8, 0xAB, 0xFF, 0x75, + 0x3, 0xE9, 0x9B, 0xC7, 0x89 +}; + +#ifdef MEGA + const uint8_t BASICH[16384] PROGMEM = { +#else + const uint8_t BASICH[16384] = { +#endif + 0x1E, 0xE9, 0x4, 0xC3, 0xB9, 0x98, 0x14, 0x51, 0xE8, 0x1C, 0xD7, + 0x8A, 0x7, 0x3C, 0x2C, 0x75, 0x59, 0x53, 0xE8, 0x91, 0xE8, 0x8A, + 0x7, 0xA, 0xC0, 0x75, 0x3, 0xE9, 0x7C, 0xC7, 0x43, 0x8B, 0x1F, + 0x8A, 0x7, 0x24, 0xDF, 0xB2, 0x1, 0x3C, 0x49, 0x74, 0x15, 0xB2, + 0x2, 0x3C, 0x4F, 0x74, 0xF, 0xB2, 0x4, 0x3C, 0x52, 0x74, 0x9, + 0xB2, 0x8, 0x3C, 0x41, 0x74, 0x3, 0xE9, 0x54, 0xC7, 0x5B, 0x52, + 0xE8, 0xAF, 0xED, 0x2C, 0x3C, 0x23, 0x75, 0x3, 0xE8, 0xD0, 0xCE, + 0xE8, 0xCC, 0xDE, 0xE8, 0xA1, 0xED, 0x2C, 0x8A, 0xC2, 0xA, 0xC0, + 0x75, 0x3, 0xE9, 0x3D, 0xC7, 0x50, 0xE8, 0xB2, 0xFE, 0x58, 0x59, + 0x8A, 0xD1, 0xCD, 0xDD, 0xE9, 0x83, 0x0, 0xE8, 0xA9, 0xFE, 0x8A, + 0x7, 0x3C, 0x82, 0xB2, 0x4, 0x75, 0x59, 0xE8, 0xA5, 0xCE, 0x3C, + 0x85, 0xB2, 0x1, 0x74, 0x4D, 0x3C, 0x4F, 0x74, 0x20, 0x3C, 0x49, + 0x74, 0x37, 0xE8, 0x6B, 0xED, 0x41, 0xE8, 0x67, 0xED, 0x50, 0xE8, + 0x63, 0xED, 0x50, 0xE8, 0x5F, 0xED, 0x45, 0xE8, 0x5B, 0xED, 0x4E, + 0xE8, 0x57, 0xED, 0x44, 0xB2, 0x8, 0xEB, 0x2C, 0xE8, 0x78, 0xCE, + 0xE8, 0x4C, 0xED, 0x55, 0xE8, 0x48, 0xED, 0x54, 0xE8, 0x44, 0xED, + 0x50, 0xE8, 0x40, 0xED, 0x55, 0xE8, 0x3C, 0xED, 0x54, 0xB2, 0x2, + 0xEB, 0x11, 0xE8, 0x5D, 0xCE, 0xE8, 0x31, 0xED, 0x42, 0xE8, 0x2D, + 0xED, 0x4D, 0xB2, 0x20, 0x4B, 0xE8, 0x4F, 0xCE, 0xE8, 0x23, 0xED, + 0x41, 0xE8, 0x1F, 0xED, 0x53, 0x52, 0x8A, 0x7, 0x3C, 0x23, 0x75, + 0x3, 0xE8, 0x3D, 0xCE, 0xE8, 0x39, 0xDE, 0xA, 0xC0, 0x75, 0x3, + 0xE9, 0xB0, 0xC6, 0xCD, 0xDE, 0xB4, 0x52, 0x4B, 0x8A, 0xD0, 0xE8, + 0x29, 0xCE, 0x74, 0x3, 0xE9, 0xC5, 0xC6, 0x5E, 0x87, 0xDE, 0x56, + 0x8A, 0xC2, 0x9F, 0x86, 0xC4, 0x50, 0x86, 0xC4, 0x53, 0xE8, 0x9C, + 0xFE, 0x74, 0x3, 0xE9, 0x95, 0xC6, 0x5A, 0x8A, 0xC6, 0x3C, 0x9, + 0xCD, 0xDF, 0x73, 0x3, 0xE9, 0x83, 0xC6, 0x53, 0xB9, 0x2E, 0x0, + 0x3, 0xD9, 0x88, 0x37, 0xB0, 0x0, 0x5B, 0xE9, 0x91, 0xFD, 0x53, + 0xA, 0xC0, 0x75, 0xA, 0xA0, 0x36, 0x5, 0x24, 0x1, 0x74, 0x3, + 0xE9, 0x46, 0x3, 0xE8, 0x6B, 0xFE, 0x74, 0x15, 0x89, 0x1E, 0xE9, + 0x4, 0x53, 0xB0, 0x2, 0x73, 0x3, 0xE9, 0x71, 0xFD, 0xCD, 0xE0, + 0xE9, 0x50, 0xC6, 0xE8, 0x24, 0x3, 0x5B, 0x53, 0xBA, 0x31, 0x0, + 0x3, 0xDA, 0x88, 0x7, 0x8A, 0xF8, 0x8A, 0xD8, 0x89, 0x1E, 0xE9, + 0x4, 0x5B, 0x2, 0x7, 0xC6, 0x7, 0x0, 0x5B, 0xC3, 0xF9, 0xEB, + 0x3, 0xD, 0x32, 0xC0, 0x9F, 0x50, 0xE8, 0x9F, 0xFD, 0xCD, 0xE9, + 0x58, 0x9E, 0x9F, 0x50, 0x74, 0x14, 0x8A, 0x7, 0x2C, 0x2C, 0xA, + 0xC0, 0x75, 0xC, 0xE8, 0x96, 0xCD, 0xE8, 0x6A, 0xEC, 0x52, 0x58, + 0x9E, 0xF9, 0x9F, 0x50, 0x9F, 0x50, 0x32, 0xC0, 0xB2, 0x1, 0xE8, + 0x54, 0xFF, 0x8B, 0x1E, 0xE9, 0x4, 0xB9, 0x31, 0x0, 0x3, 0xD9, + 0x58, 0x9E, 0x1A, 0xC0, 0x24, 0x80, 0xC, 0x1, 0xA2, 0x36, 0x5, + 0x58, 0x9E, 0x9F, 0x50, 0x1A, 0xC0, 0xA2, 0xEF, 0x4, 0x8A, 0x7, + 0xA, 0xC0, 0x79, 0x3, 0xE9, 0xD8, 0x0, 0x58, 0x9E, 0x74, 0x3, + 0xE8, 0x57, 0xEB, 0x32, 0xC0, 0xE8, 0x2C, 0xFE, 0xE9, 0x5, 0xC7, + 0xE8, 0x42, 0xFD, 0xCD, 0xEA, 0x4B, 0xE8, 0x46, 0xCD, 0xB2, 0x80, + 0xF9, 0x75, 0x3, 0xE8, 0x79, 0x5, 0x74, 0x18, 0xE8, 0x10, 0xEC, + 0x2C, 0x3C, 0x50, 0xB2, 0x92, 0x75, 0x6, 0xE8, 0x2F, 0xCD, 0xF9, + 0xEB, 0x8, 0xE8, 0x0, 0xEC, 0x41, 0xA, 0xC0, 0xB2, 0x2, 0x9F, + 0x50, 0x8A, 0xC2, 0x24, 0x10, 0xA2, 0x62, 0x4, 0x58, 0x9E, 0x9F, + 0x50, 0xFE, 0xC0, 0xA2, 0x5F, 0x0, 0x32, 0xC0, 0xE8, 0xDD, 0xFE, + 0x58, 0x9E, 0x53, 0x8B, 0x1E, 0xE9, 0x4, 0x8A, 0x7, 0x5B, 0x24, + 0x80, 0x75, 0x3, 0xE9, 0x14, 0xDD, 0x53, 0xE8, 0x63, 0xE1, 0xA0, + 0x62, 0x4, 0xA, 0xC0, 0x74, 0x3, 0xE8, 0x79, 0x4, 0x8B, 0x1E, + 0x58, 0x3, 0x89, 0x1E, 0x4, 0x7, 0x8B, 0x1E, 0x30, 0x0, 0x53, + 0x8B, 0x1E, 0xE9, 0x4, 0xE8, 0xC6, 0x0, 0xA, 0xC0, 0x79, 0x3, + 0xE9, 0x16, 0x0, 0xE9, 0x4D, 0xC5, 0xA0, 0x62, 0x4, 0xA, 0xC0, + 0x74, 0x3, 0xE8, 0xA2, 0x4, 0x5B, 0x32, 0xC0, 0xA2, 0x62, 0x4, + 0xE9, 0xC8, 0xFE, 0x5B, 0xE8, 0x2, 0x0, 0xEB, 0xE7, 0xE8, 0xA0, + 0x0, 0x3C, 0xFC, 0x75, 0x3, 0xE9, 0xD, 0x1A, 0xCD, 0xEB, 0xE9, + 0x1F, 0xC5, 0x8B, 0x1E, 0x30, 0x0, 0xA, 0xC0, 0xE8, 0x3, 0x0, + 0xE9, 0x46, 0x0, 0x9F, 0x50, 0xE8, 0x83, 0x0, 0x3C, 0xFC, 0x75, + 0x3, 0xE9, 0x36, 0x1A, 0x58, 0x9E, 0xCD, 0xEC, 0xE9, 0x0, 0xC5, + 0x58, 0x9E, 0xC3, 0x24, 0x20, 0xA2, 0x63, 0x4, 0x58, 0x9E, 0x75, + 0x3, 0xE9, 0xF1, 0xC4, 0xE8, 0x77, 0xEA, 0xA0, 0x63, 0x4, 0xA2, + 0x64, 0x4, 0xE8, 0xAB, 0x0, 0x32, 0xC0, 0xE8, 0xF1, 0xFC, 0xC6, + 0x7, 0x80, 0x89, 0x1E, 0xE9, 0x4, 0xE8, 0x4B, 0x0, 0xA, 0xC0, + 0x78, 0xB3, 0xCD, 0xED, 0xE9, 0xD3, 0xC4, 0xA0, 0x64, 0x4, 0xA, + 0xC0, 0x74, 0x3, 0xE8, 0x28, 0x4, 0xE8, 0x27, 0xC7, 0x43, 0x43, + 0x89, 0x1E, 0x58, 0x3, 0xE8, 0x5A, 0xEA, 0x32, 0xC0, 0xA2, 0x36, + 0x5, 0xE8, 0x43, 0xFE, 0xA0, 0xEF, 0x4, 0xA, 0xC0, 0x74, 0x3, + 0xE9, 0xF9, 0xCB, 0xE9, 0xC4, 0xC5, 0x87, 0xDA, 0x8B, 0x1E, 0x2F, + 0x3, 0x87, 0xDA, 0x3B, 0xDA, 0x72, 0x98, 0xE8, 0x1C, 0xEA, 0x32, + 0xC0, 0xA2, 0x36, 0x5, 0xE9, 0xEB, 0xE9, 0x53, 0x52, 0x8B, 0x1E, + 0xE9, 0x4, 0xBA, 0x2E, 0x0, 0x3, 0xDA, 0x8A, 0x7, 0x5A, 0x5B, + 0xC3, 0x75, 0x1E, 0x53, 0x51, 0x50, 0xBA, 0x26, 0x43, 0x52, 0x51, + 0xA, 0xC0, 0xC3, 0x58, 0x59, 0xFE, 0xC8, 0x79, 0xF0, 0x5B, 0xC3, + 0x59, 0x5B, 0x8A, 0x7, 0x3C, 0x2C, 0x75, 0xF7, 0xE8, 0xE4, 0xCB, + 0x51, 0x8A, 0x7, 0x3C, 0x23, 0x75, 0x3, 0xE8, 0xDA, 0xCB, 0xE8, + 0xD6, 0xDB, 0x5E, 0x87, 0xDE, 0x56, 0x53, 0xBA, 0x2E, 0x43, 0x52, + 0xF9, 0xFF, 0xE3, 0xB9, 0x28, 0x41, 0xA0, 0xDF, 0x4, 0xEB, 0xBF, + 0xA0, 0x36, 0x5, 0xA, 0xC0, 0x78, 0xCC, 0xB9, 0x28, 0x41, 0x32, + 0xC0, 0xA0, 0xDF, 0x4, 0xEB, 0xAE, 0x32, 0xC0, 0x8A, 0xE8, 0x8A, + 0xC5, 0xE8, 0x31, 0xFC, 0xC6, 0x7, 0x0, 0xA0, 0xDF, 0x4, 0xFE, + 0xC5, 0x2A, 0xC5, 0x73, 0xEF, 0x32, 0xC0, 0xA2, 0x36, 0x5, 0xE8, + 0x95, 0xE9, 0x8B, 0x1E, 0x30, 0x0, 0x4B, 0xC6, 0x7, 0x0, 0xE9, + 0xDB, 0xC3, 0x5B, 0x58, 0x86, 0xC4, 0x9E, 0x53, 0x52, 0x51, 0x9F, + 0x86, 0xC4, 0x50, 0x86, 0xC4, 0x8B, 0x1E, 0xE9, 0x4, 0xB0, 0x6, + 0xE8, 0x5, 0x0, 0xCD, 0xE3, 0xE9, 0xEB, 0xC3, 0x9F, 0x86, 0xC4, + 0x50, 0x86, 0xC4, 0x52, 0x87, 0xDA, 0xBB, 0x2E, 0x0, 0x3, 0xDA, + 0x8A, 0x7, 0x87, 0xDA, 0x5A, 0x3C, 0x9, 0x73, 0x3, 0xE9, 0xCA, + 0x0, 0x58, 0x86, 0xC4, 0x9E, 0x5E, 0x87, 0xDE, 0x56, 0x5B, 0xE9, + 0xE4, 0xFA, 0x51, 0x53, 0x52, 0x8B, 0x1E, 0xE9, 0x4, 0xB0, 0x8, + 0xE8, 0xCE, 0xFF, 0xCD, 0xE4, 0xE9, 0xB4, 0xC3, 0x5A, 0x5B, 0x59, + 0xC3, 0xE8, 0x30, 0xCB, 0xE8, 0x4, 0xEA, 0x24, 0xE8, 0x0, 0xEA, + 0x28, 0x53, 0x8B, 0x1E, 0xE9, 0x4, 0x53, 0xBB, 0x0, 0x0, 0x89, + 0x1E, 0xE9, 0x4, 0x5B, 0x5E, 0x87, 0xDE, 0x56, 0xE8, 0x12, 0xDB, + 0x52, 0x8A, 0x7, 0x3C, 0x2C, 0x75, 0xB, 0xE8, 0x9, 0xCB, 0xE8, + 0xCD, 0xFB, 0x5B, 0x32, 0xC0, 0x8A, 0x7, 0x9F, 0x50, 0xE8, 0xD3, + 0xE9, 0x29, 0x58, 0x9E, 0x5E, 0x87, 0xDE, 0x56, 0x9F, 0x50, 0x8A, + 0xC3, 0xA, 0xC0, 0x75, 0x3, 0xE9, 0x26, 0xCC, 0x53, 0xE8, 0x7, + 0xE2, 0x87, 0xDA, 0x59, 0x58, 0x9E, 0x9F, 0x50, 0x74, 0x28, 0xE8, + 0x16, 0xE8, 0x3C, 0x3, 0x74, 0x13, 0x88, 0x7, 0x43, 0xFE, 0xC9, + 0x75, 0xEC, 0x58, 0x9E, 0x59, 0x5B, 0x89, 0x1E, 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0x53, 0x5B, 0xE8, 0x80, + 0xE5, 0xBB, 0xDC, 0x7F, 0xE8, 0x7F, 0xFB, 0xE8, 0x98, 0xAC, 0xE9, + 0x8F, 0xC3, 0x20, 0x42, 0x79, 0x74, 0x65, 0x73, 0x20, 0x66, 0x72, + 0x65, 0x65, 0x0, 0x14, 0xE8, 0xA5, 0xF0, 0x33, 0xC9, 0x52, 0xFF, + 0x36, 0x81, 0x4, 0xE9, 0x68, 0xF6, 0xFD, 0xFF, 0x3, 0xBF, 0xC9, + 0x1B, 0xE, 0xB6, 0x0, 0x0 +}; +#endif + diff --git a/MCUME_esp32/esp8086/partitions.csv b/MCUME_esp32/esp8086/partitions.csv new file mode 100755 index 0000000..79c1f89 --- /dev/null +++ b/MCUME_esp32/esp8086/partitions.csv @@ -0,0 +1,5 @@ +# Name, Type, SubType, Offset, Size +# Note: if you change the phy_init or app partition offset, make sure to change the offset in Kconfig.projbuild +nvs, data, nvs, 0x9000, 0x6000 +phy_init, data, phy, 0xf000, 0x1000 +factory, app, factory, 0x10000, 2M, diff --git a/MCUME_esp32/esp8086/sdkconfig b/MCUME_esp32/esp8086/sdkconfig new file mode 100644 index 0000000..cfcca67 --- /dev/null +++ b/MCUME_esp32/esp8086/sdkconfig @@ -0,0 +1,721 @@ +# +# Automatically generated file; DO NOT EDIT. +# Espressif IoT Development Framework Configuration +# +CONFIG_IDF_TARGET="esp32" + +# +# SDK tool configuration +# +CONFIG_TOOLPREFIX="xtensa-esp32-elf-" +CONFIG_PYTHON="python" +CONFIG_MAKE_WARN_UNDEFINED_VARIABLES=y + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +CONFIG_APP_EXCLUDE_PROJECT_VER_VAR= +CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR= + +# +# Bootloader config +# +CONFIG_LOG_BOOTLOADER_LEVEL_NONE= +CONFIG_LOG_BOOTLOADER_LEVEL_ERROR= +CONFIG_LOG_BOOTLOADER_LEVEL_WARN= +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG= +CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE= +CONFIG_LOG_BOOTLOADER_LEVEL=3 +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V= +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +CONFIG_BOOTLOADER_FACTORY_RESET= +CONFIG_BOOTLOADER_APP_TEST= +CONFIG_BOOTLOADER_WDT_ENABLE=y +CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE= +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +CONFIG_APP_ROLLBACK_ENABLE= + +# +# Security features +# +CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT= +CONFIG_SECURE_BOOT_ENABLED= +CONFIG_FLASH_ENCRYPTION_ENABLED= + +# +# Serial flasher config +# +CONFIG_ESPTOOLPY_PORT="/dev/cu.SLAB_USBtoUART" +CONFIG_ESPTOOLPY_BAUD_115200B=y +CONFIG_ESPTOOLPY_BAUD_230400B= +CONFIG_ESPTOOLPY_BAUD_921600B= +CONFIG_ESPTOOLPY_BAUD_2MB= +CONFIG_ESPTOOLPY_BAUD_OTHER= +CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 +CONFIG_ESPTOOLPY_BAUD=115200 +CONFIG_ESPTOOLPY_COMPRESSED=y +CONFIG_FLASHMODE_QIO= +CONFIG_FLASHMODE_QOUT= +CONFIG_FLASHMODE_DIO=y +CONFIG_FLASHMODE_DOUT= +CONFIG_ESPTOOLPY_FLASHMODE="dio" +CONFIG_ESPTOOLPY_FLASHFREQ_80M= +CONFIG_ESPTOOLPY_FLASHFREQ_40M=y +CONFIG_ESPTOOLPY_FLASHFREQ_26M= +CONFIG_ESPTOOLPY_FLASHFREQ_20M= +CONFIG_ESPTOOLPY_FLASHFREQ="40m" +CONFIG_ESPTOOLPY_FLASHSIZE_1MB= +CONFIG_ESPTOOLPY_FLASHSIZE_2MB= +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +CONFIG_ESPTOOLPY_FLASHSIZE_8MB= +CONFIG_ESPTOOLPY_FLASHSIZE_16MB= +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" +CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y +CONFIG_ESPTOOLPY_BEFORE_RESET=y +CONFIG_ESPTOOLPY_BEFORE_NORESET= +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +CONFIG_ESPTOOLPY_AFTER_NORESET= +CONFIG_ESPTOOLPY_AFTER="hard_reset" +CONFIG_MONITOR_BAUD_9600B= +CONFIG_MONITOR_BAUD_57600B= +CONFIG_MONITOR_BAUD_115200B=y +CONFIG_MONITOR_BAUD_230400B= +CONFIG_MONITOR_BAUD_921600B= +CONFIG_MONITOR_BAUD_2MB= +CONFIG_MONITOR_BAUD_OTHER= +CONFIG_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_MONITOR_BAUD=115200 + +# +# Partition Table +# +CONFIG_PARTITION_TABLE_SINGLE_APP= +CONFIG_PARTITION_TABLE_TWO_OTA= +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y + +# +# Compiler options +# +CONFIG_OPTIMIZATION_LEVEL_DEBUG= +CONFIG_OPTIMIZATION_LEVEL_RELEASE=y +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +CONFIG_OPTIMIZATION_ASSERTIONS_SILENT= +CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED= +CONFIG_CXX_EXCEPTIONS= +CONFIG_STACK_CHECK_NONE=y +CONFIG_STACK_CHECK_NORM= +CONFIG_STACK_CHECK_STRONG= +CONFIG_STACK_CHECK_ALL= +CONFIG_STACK_CHECK= +CONFIG_WARN_WRITE_STRINGS= +CONFIG_DISABLE_GCC8_WARNINGS= + +# +# Component config +# + +# +# Application Level Tracing +# +CONFIG_ESP32_APPTRACE_DEST_TRAX= +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_ENABLE= +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +CONFIG_AWS_IOT_SDK= + +# +# Bluetooth +# +CONFIG_BT_ENABLED= +CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0 +CONFIG_BT_RESERVE_DRAM=0 + +# +# Driver configurations +# + +# +# ADC configuration +# +CONFIG_ADC_FORCE_XPD_FSM= +CONFIG_ADC2_DISABLE_DAC=y + +# +# SPI configuration +# +CONFIG_SPI_MASTER_IN_IRAM= +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +CONFIG_SPI_SLAVE_IN_IRAM= +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y + +# +# eFuse Bit Manager +# +CONFIG_EFUSE_CUSTOM_TABLE= +CONFIG_EFUSE_VIRTUAL= +CONFIG_EFUSE_CODE_SCHEME_COMPAT_NONE= +CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4=y +CONFIG_EFUSE_CODE_SCHEME_COMPAT_REPEAT= +CONFIG_EFUSE_MAX_BLK_LEN=192 + +# +# ESP32-specific +# +CONFIG_IDF_TARGET_ESP32=y +CONFIG_ESP32_DEFAULT_CPU_FREQ_80= +CONFIG_ESP32_DEFAULT_CPU_FREQ_160= +CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y +CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240 +CONFIG_SPIRAM_SUPPORT=y + +# +# SPI RAM config +# +CONFIG_SPIRAM_BOOT_INIT=y +CONFIG_SPIRAM_IGNORE_NOTFOUND= +CONFIG_SPIRAM_USE_MEMMAP= +CONFIG_SPIRAM_USE_CAPS_ALLOC=y +CONFIG_SPIRAM_USE_MALLOC= +CONFIG_SPIRAM_TYPE_AUTO=y +CONFIG_SPIRAM_TYPE_ESPPSRAM32= +CONFIG_SPIRAM_TYPE_ESPPSRAM64= +CONFIG_SPIRAM_SIZE=-1 +CONFIG_SPIRAM_SPEED_40M=y +CONFIG_SPIRAM_MEMTEST=y +CONFIG_SPIRAM_CACHE_WORKAROUND=y +CONFIG_SPIRAM_BANKSWITCH_ENABLE=y +CONFIG_SPIRAM_BANKSWITCH_RESERVE=8 +CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST= +CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY= +CONFIG_PICO_PSRAM_CS_IO=10 +CONFIG_MEMMAP_TRACEMEM= +CONFIG_MEMMAP_TRACEMEM_TWOBANKS= +CONFIG_ESP32_TRAX= +CONFIG_TRACEMEM_RESERVE_DRAM=0x0 +CONFIG_TWO_UNIVERSAL_MAC_ADDRESS= +CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y +CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4 +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +CONFIG_IPC_TASK_STACK_SIZE=1024 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF= +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR= +CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF= +CONFIG_NEWLIB_STDIN_LINE_ENDING_LF= +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +CONFIG_NEWLIB_NANO_FORMAT= +CONFIG_CONSOLE_UART_DEFAULT=y +CONFIG_CONSOLE_UART_CUSTOM= +CONFIG_CONSOLE_UART_NONE= +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ULP_COPROC_ENABLED= +CONFIG_ULP_COPROC_RESERVE_MEM=0 +CONFIG_ESP32_PANIC_PRINT_HALT= +CONFIG_ESP32_PANIC_PRINT_REBOOT=y +CONFIG_ESP32_PANIC_SILENT_REBOOT= +CONFIG_ESP32_PANIC_GDBSTUB= +CONFIG_ESP32_DEBUG_OCDAWARE=y +CONFIG_ESP32_DEBUG_STUBS_ENABLE=y +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_INT_WDT_CHECK_CPU1=y +CONFIG_TASK_WDT=y +CONFIG_TASK_WDT_PANIC= +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +CONFIG_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_0=y +CONFIG_BROWNOUT_DET_LVL_SEL_1= +CONFIG_BROWNOUT_DET_LVL_SEL_2= +CONFIG_BROWNOUT_DET_LVL_SEL_3= +CONFIG_BROWNOUT_DET_LVL_SEL_4= +CONFIG_BROWNOUT_DET_LVL_SEL_5= +CONFIG_BROWNOUT_DET_LVL_SEL_6= +CONFIG_BROWNOUT_DET_LVL_SEL_7= +CONFIG_BROWNOUT_DET_LVL=0 +CONFIG_REDUCE_PHY_TX_POWER=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC= +CONFIG_ESP32_TIME_SYSCALL_USE_FRC1= +CONFIG_ESP32_TIME_SYSCALL_USE_NONE= +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y +CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL= +CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC= +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256= +CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP32_XTAL_FREQ_40=y +CONFIG_ESP32_XTAL_FREQ_26= +CONFIG_ESP32_XTAL_FREQ_AUTO= +CONFIG_ESP32_XTAL_FREQ=40 +CONFIG_DISABLE_BASIC_ROM_CONSOLE= +CONFIG_NO_BLOBS= +CONFIG_ESP_TIMER_PROFILING= +CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS= +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y + +# +# Wi-Fi +# +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER= +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16 +CONFIG_ESP32_WIFI_CSI_ENABLED= +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1= +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP32_WIFI_DEBUG_LOG_ENABLE= +CONFIG_ESP32_WIFI_IRAM_OPT=y + +# +# PHY +# +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION= +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 + +# +# Power Management +# +CONFIG_PM_ENABLE= + +# +# ADC-Calibration +# +CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y +CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y +CONFIG_ADC_CAL_LUT_ENABLE=y + +# +# Event Loop Library +# +CONFIG_EVENT_LOOP_PROFILING= + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS= + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y + +# +# ESP HTTPS OTA +# +CONFIG_OTA_ALLOW_HTTP= + +# +# Core dump +# +CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH= +CONFIG_ESP32_ENABLE_COREDUMP_TO_UART= +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +CONFIG_ESP32_ENABLE_COREDUMP= + +# +# Ethernet +# +CONFIG_DMA_RX_BUF_NUM=10 +CONFIG_DMA_TX_BUF_NUM=10 +CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE=y +CONFIG_EMAC_CHECK_LINK_PERIOD_MS=2000 +CONFIG_EMAC_TASK_PRIORITY=20 +CONFIG_EMAC_TASK_STACK_SIZE=3072 + +# +# FAT Filesystem support +# +CONFIG_FATFS_CODEPAGE_DYNAMIC= +CONFIG_FATFS_CODEPAGE_437=y +CONFIG_FATFS_CODEPAGE_720= +CONFIG_FATFS_CODEPAGE_737= +CONFIG_FATFS_CODEPAGE_771= +CONFIG_FATFS_CODEPAGE_775= +CONFIG_FATFS_CODEPAGE_850= +CONFIG_FATFS_CODEPAGE_852= +CONFIG_FATFS_CODEPAGE_855= +CONFIG_FATFS_CODEPAGE_857= +CONFIG_FATFS_CODEPAGE_860= +CONFIG_FATFS_CODEPAGE_861= +CONFIG_FATFS_CODEPAGE_862= +CONFIG_FATFS_CODEPAGE_863= +CONFIG_FATFS_CODEPAGE_864= +CONFIG_FATFS_CODEPAGE_865= +CONFIG_FATFS_CODEPAGE_866= +CONFIG_FATFS_CODEPAGE_869= +CONFIG_FATFS_CODEPAGE_932= +CONFIG_FATFS_CODEPAGE_936= +CONFIG_FATFS_CODEPAGE_949= +CONFIG_FATFS_CODEPAGE_950= +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_LFN_NONE= +CONFIG_FATFS_LFN_HEAP= +CONFIG_FATFS_LFN_STACK=y +CONFIG_FATFS_MAX_LFN=255 +CONFIG_FATFS_API_ENCODING_ANSI_OEM=y +CONFIG_FATFS_API_ENCODING_UTF_16= +CONFIG_FATFS_API_ENCODING_UTF_8= +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y + +# +# Modbus configuration +# +CONFIG_MB_QUEUE_LENGTH=20 +CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048 +CONFIG_MB_SERIAL_BUF_SIZE=256 +CONFIG_MB_SERIAL_TASK_PRIO=10 +CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT= +CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_MB_CONTROLLER_STACK_SIZE=4096 +CONFIG_MB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_MB_TIMER_PORT_ENABLED=y +CONFIG_MB_TIMER_GROUP=0 +CONFIG_MB_TIMER_INDEX=0 + +# +# FreeRTOS +# +CONFIG_FREERTOS_UNICORE= +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_CORETIMER_0=y +CONFIG_FREERTOS_CORETIMER_1= +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE= +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL= +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK= +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y +CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE= +CONFIG_FREERTOS_ASSERT_DISABLE= +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +CONFIG_FREERTOS_LEGACY_HOOKS= +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +CONFIG_SUPPORT_STATIC_ALLOCATION=y +CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK= +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_USE_TRACE_FACILITY= +CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS= +CONFIG_FREERTOS_DEBUG_INTERNALS= + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +CONFIG_HEAP_POISONING_LIGHT= +CONFIG_HEAP_POISONING_COMPREHENSIVE= +CONFIG_HEAP_TRACING= + +# +# libsodium +# +CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y + +# +# Log output +# +CONFIG_LOG_DEFAULT_LEVEL_NONE= +CONFIG_LOG_DEFAULT_LEVEL_ERROR= +CONFIG_LOG_DEFAULT_LEVEL_WARN= +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +CONFIG_LOG_DEFAULT_LEVEL_DEBUG= +CONFIG_LOG_DEFAULT_LEVEL_VERBOSE= +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_COLORS=y + +# +# LWIP +# +CONFIG_L2_TO_L3_COPY= +CONFIG_LWIP_IRAM_OPTIMIZATION= +CONFIG_LWIP_MAX_SOCKETS=10 +CONFIG_USE_ONLY_LWIP_SELECT= +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +CONFIG_LWIP_SO_RCVBUF= +CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 +CONFIG_LWIP_IP_FRAG= +CONFIG_LWIP_IP_REASSEMBLY= +CONFIG_LWIP_STATS= +CONFIG_LWIP_ETHARP_TRUST_IP_MAC= +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +CONFIG_LWIP_DHCP_RESTORE_LAST_IP= + +# +# DHCP server +# +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +CONFIG_LWIP_AUTOIP= +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=6 +CONFIG_TCP_MSS=1436 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5744 +CONFIG_TCP_WND_DEFAULT=5744 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES= +CONFIG_TCP_OVERSIZE_MSS=y +CONFIG_TCP_OVERSIZE_QUARTER_MSS= +CONFIG_TCP_OVERSIZE_DISABLE= + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +CONFIG_TCPIP_TASK_AFFINITY_CPU0= +CONFIG_TCPIP_TASK_AFFINITY_CPU1= +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +CONFIG_PPP_SUPPORT= + +# +# ICMP +# +CONFIG_LWIP_MULTICAST_PING= +CONFIG_LWIP_BROADCAST_PING= + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC= +CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC= +CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC= +CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384 +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN= +CONFIG_MBEDTLS_DEBUG= +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_HARDWARE_MPI= +CONFIG_MBEDTLS_HARDWARE_SHA= +CONFIG_MBEDTLS_HAVE_TIME=y +CONFIG_MBEDTLS_HAVE_TIME_DATE= +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +CONFIG_MBEDTLS_TLS_SERVER_ONLY= +CONFIG_MBEDTLS_TLS_CLIENT_ONLY= +CONFIG_MBEDTLS_TLS_DISABLED= +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +CONFIG_MBEDTLS_PSK_MODES= +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +CONFIG_MBEDTLS_SSL_PROTO_SSL3= +CONFIG_MBEDTLS_SSL_PROTO_TLS1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +CONFIG_MBEDTLS_SSL_PROTO_DTLS= +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +CONFIG_MBEDTLS_CAMELLIA_C= +CONFIG_MBEDTLS_DES_C= +CONFIG_MBEDTLS_RC4_DISABLED=y +CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT= +CONFIG_MBEDTLS_RC4_ENABLED= +CONFIG_MBEDTLS_BLOWFISH_C= +CONFIG_MBEDTLS_XTEA_C= +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +CONFIG_MBEDTLS_RIPEMD160_C= + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y + +# +# mDNS +# +CONFIG_MDNS_MAX_SERVICES=10 + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +CONFIG_MQTT_USE_CUSTOM_CONFIG= +CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED= +CONFIG_MQTT_CUSTOM_OUTBOX= + +# +# NVS +# + +# +# OpenSSL +# +CONFIG_OPENSSL_DEBUG= +CONFIG_OPENSSL_ASSERT_DO_NOTHING=y +CONFIG_OPENSSL_ASSERT_EXIT= + +# +# PThreads +# +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0= +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1= +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" + +# +# SPI Flash driver +# +CONFIG_SPI_FLASH_VERIFY_WRITE= +CONFIG_SPI_FLASH_ENABLE_COUNTERS= +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +CONFIG_SPIFFS_CACHE_STATS= +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +CONFIG_SPIFFS_GC_STATS= +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +CONFIG_SPIFFS_DBG= +CONFIG_SPIFFS_API_DBG= +CONFIG_SPIFFS_GC_DBG= +CONFIG_SPIFFS_CACHE_DBG= +CONFIG_SPIFFS_CHECK_DBG= +CONFIG_SPIFFS_TEST_VISUALISATION= + +# +# TCP/IP Adapter +# +CONFIG_IP_LOST_TIMER_INTERVAL=120 +CONFIG_TCPIP_LWIP=y + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +CONFIG_UNITY_ENABLE_COLOR= +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +CONFIG_UNITY_ENABLE_FIXTURE= + +# +# Virtual file system +# +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y + +# +# Wear Levelling +# +CONFIG_WL_SECTOR_SIZE_512= +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 diff --git a/MCUME_esp32/esp8086/sdkconfig.old b/MCUME_esp32/esp8086/sdkconfig.old new file mode 100644 index 0000000..e6b5dbe --- /dev/null +++ b/MCUME_esp32/esp8086/sdkconfig.old @@ -0,0 +1,705 @@ +# +# Automatically generated file; DO NOT EDIT. +# Espressif IoT Development Framework Configuration +# +CONFIG_IDF_TARGET="esp32" + +# +# SDK tool configuration +# +CONFIG_TOOLPREFIX="xtensa-esp32-elf-" +CONFIG_PYTHON="python" +CONFIG_MAKE_WARN_UNDEFINED_VARIABLES=y + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y + +# +# Bootloader config +# +CONFIG_LOG_BOOTLOADER_LEVEL_NONE= +CONFIG_LOG_BOOTLOADER_LEVEL_ERROR= +CONFIG_LOG_BOOTLOADER_LEVEL_WARN= +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG= +CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE= +CONFIG_LOG_BOOTLOADER_LEVEL=3 +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V= +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +CONFIG_BOOTLOADER_FACTORY_RESET= +CONFIG_BOOTLOADER_APP_TEST= +CONFIG_BOOTLOADER_WDT_ENABLE=y +CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE= +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 + +# +# Security features +# +CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT= +CONFIG_SECURE_BOOT_ENABLED= +CONFIG_FLASH_ENCRYPTION_ENABLED= + +# +# Serial flasher config +# +CONFIG_ESPTOOLPY_PORT="/dev/cu.SLAB_USBtoUART" +CONFIG_ESPTOOLPY_BAUD_115200B=y +CONFIG_ESPTOOLPY_BAUD_230400B= +CONFIG_ESPTOOLPY_BAUD_921600B= +CONFIG_ESPTOOLPY_BAUD_2MB= +CONFIG_ESPTOOLPY_BAUD_OTHER= +CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 +CONFIG_ESPTOOLPY_BAUD=115200 +CONFIG_ESPTOOLPY_COMPRESSED=y +CONFIG_FLASHMODE_QIO= +CONFIG_FLASHMODE_QOUT= +CONFIG_FLASHMODE_DIO=y +CONFIG_FLASHMODE_DOUT= +CONFIG_ESPTOOLPY_FLASHMODE="dio" +CONFIG_ESPTOOLPY_FLASHFREQ_80M= +CONFIG_ESPTOOLPY_FLASHFREQ_40M=y +CONFIG_ESPTOOLPY_FLASHFREQ_26M= +CONFIG_ESPTOOLPY_FLASHFREQ_20M= +CONFIG_ESPTOOLPY_FLASHFREQ="40m" +CONFIG_ESPTOOLPY_FLASHSIZE_1MB= +CONFIG_ESPTOOLPY_FLASHSIZE_2MB= +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +CONFIG_ESPTOOLPY_FLASHSIZE_8MB= +CONFIG_ESPTOOLPY_FLASHSIZE_16MB= +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" +CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y +CONFIG_ESPTOOLPY_BEFORE_RESET=y +CONFIG_ESPTOOLPY_BEFORE_NORESET= +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +CONFIG_ESPTOOLPY_AFTER_NORESET= +CONFIG_ESPTOOLPY_AFTER="hard_reset" +CONFIG_MONITOR_BAUD_9600B= +CONFIG_MONITOR_BAUD_57600B= +CONFIG_MONITOR_BAUD_115200B=y +CONFIG_MONITOR_BAUD_230400B= +CONFIG_MONITOR_BAUD_921600B= +CONFIG_MONITOR_BAUD_2MB= +CONFIG_MONITOR_BAUD_OTHER= +CONFIG_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_MONITOR_BAUD=115200 + +# +# Partition Table +# +CONFIG_PARTITION_TABLE_SINGLE_APP= +CONFIG_PARTITION_TABLE_TWO_OTA= +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y + +# +# Compiler options +# +CONFIG_OPTIMIZATION_LEVEL_DEBUG= +CONFIG_OPTIMIZATION_LEVEL_RELEASE=y +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +CONFIG_OPTIMIZATION_ASSERTIONS_SILENT= +CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED= +CONFIG_CXX_EXCEPTIONS= +CONFIG_STACK_CHECK_NONE=y +CONFIG_STACK_CHECK_NORM= +CONFIG_STACK_CHECK_STRONG= +CONFIG_STACK_CHECK_ALL= +CONFIG_STACK_CHECK= +CONFIG_WARN_WRITE_STRINGS= +CONFIG_DISABLE_GCC8_WARNINGS= + +# +# Component config +# + +# +# Application Level Tracing +# +CONFIG_ESP32_APPTRACE_DEST_TRAX= +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_ENABLE= +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +CONFIG_AWS_IOT_SDK= + +# +# Bluetooth +# +CONFIG_BT_ENABLED= +CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0 +CONFIG_BT_RESERVE_DRAM=0 + +# +# Driver configurations +# + +# +# ADC configuration +# +CONFIG_ADC_FORCE_XPD_FSM= +CONFIG_ADC2_DISABLE_DAC=y + +# +# SPI configuration +# +CONFIG_SPI_MASTER_IN_IRAM= +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +CONFIG_SPI_SLAVE_IN_IRAM= +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y + +# +# ESP32-specific +# +CONFIG_IDF_TARGET_ESP32=y +CONFIG_ESP32_DEFAULT_CPU_FREQ_80= +CONFIG_ESP32_DEFAULT_CPU_FREQ_160= +CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y +CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240 +CONFIG_SPIRAM_SUPPORT=y + +# +# SPI RAM config +# +CONFIG_SPIRAM_BOOT_INIT=y +CONFIG_SPIRAM_IGNORE_NOTFOUND= +CONFIG_SPIRAM_USE_MEMMAP= +CONFIG_SPIRAM_USE_CAPS_ALLOC=y +CONFIG_SPIRAM_USE_MALLOC= +CONFIG_SPIRAM_TYPE_AUTO=y +CONFIG_SPIRAM_TYPE_ESPPSRAM32= +CONFIG_SPIRAM_TYPE_ESPPSRAM64= +CONFIG_SPIRAM_SIZE=-1 +CONFIG_SPIRAM_SPEED_40M=y +CONFIG_SPIRAM_MEMTEST=y +CONFIG_SPIRAM_CACHE_WORKAROUND=y +CONFIG_SPIRAM_BANKSWITCH_ENABLE=y +CONFIG_SPIRAM_BANKSWITCH_RESERVE=8 +CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST= +CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY= +CONFIG_MEMMAP_TRACEMEM= +CONFIG_MEMMAP_TRACEMEM_TWOBANKS= +CONFIG_ESP32_TRAX= +CONFIG_TRACEMEM_RESERVE_DRAM=0x0 + +# +# Core dump +# +CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH= +CONFIG_ESP32_ENABLE_COREDUMP_TO_UART= +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +CONFIG_ESP32_ENABLE_COREDUMP= +CONFIG_TWO_UNIVERSAL_MAC_ADDRESS= +CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y +CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4 +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +CONFIG_IPC_TASK_STACK_SIZE=1024 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF= +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR= +CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF= +CONFIG_NEWLIB_STDIN_LINE_ENDING_LF= +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +CONFIG_NEWLIB_NANO_FORMAT= +CONFIG_CONSOLE_UART_DEFAULT=y +CONFIG_CONSOLE_UART_CUSTOM= +CONFIG_CONSOLE_UART_NONE= +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ULP_COPROC_ENABLED= +CONFIG_ULP_COPROC_RESERVE_MEM=0 +CONFIG_ESP32_PANIC_PRINT_HALT= +CONFIG_ESP32_PANIC_PRINT_REBOOT=y +CONFIG_ESP32_PANIC_SILENT_REBOOT= +CONFIG_ESP32_PANIC_GDBSTUB= +CONFIG_ESP32_DEBUG_OCDAWARE=y +CONFIG_ESP32_DEBUG_STUBS_ENABLE=y +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_INT_WDT_CHECK_CPU1=y +CONFIG_TASK_WDT=y +CONFIG_TASK_WDT_PANIC= +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +CONFIG_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_0=y +CONFIG_BROWNOUT_DET_LVL_SEL_1= +CONFIG_BROWNOUT_DET_LVL_SEL_2= +CONFIG_BROWNOUT_DET_LVL_SEL_3= +CONFIG_BROWNOUT_DET_LVL_SEL_4= +CONFIG_BROWNOUT_DET_LVL_SEL_5= +CONFIG_BROWNOUT_DET_LVL_SEL_6= +CONFIG_BROWNOUT_DET_LVL_SEL_7= +CONFIG_BROWNOUT_DET_LVL=0 +CONFIG_REDUCE_PHY_TX_POWER=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC= +CONFIG_ESP32_TIME_SYSCALL_USE_FRC1= +CONFIG_ESP32_TIME_SYSCALL_USE_NONE= +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y +CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL= +CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC= +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256= +CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP32_XTAL_FREQ_40=y +CONFIG_ESP32_XTAL_FREQ_26= +CONFIG_ESP32_XTAL_FREQ_AUTO= +CONFIG_ESP32_XTAL_FREQ=40 +CONFIG_DISABLE_BASIC_ROM_CONSOLE= +CONFIG_NO_BLOBS= +CONFIG_ESP_TIMER_PROFILING= +CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS= +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y + +# +# Wi-Fi +# +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER= +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16 +CONFIG_ESP32_WIFI_CSI_ENABLED= +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1= +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_DEBUG_LOG_ENABLE= + +# +# PHY +# +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION= +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 + +# +# Power Management +# +CONFIG_PM_ENABLE= + +# +# ADC-Calibration +# +CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y +CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y +CONFIG_ADC_CAL_LUT_ENABLE=y + +# +# Event Loop Library +# +CONFIG_EVENT_LOOP_PROFILING= + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS= + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 + +# +# Ethernet +# +CONFIG_DMA_RX_BUF_NUM=10 +CONFIG_DMA_TX_BUF_NUM=10 +CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE=y +CONFIG_EMAC_CHECK_LINK_PERIOD_MS=2000 +CONFIG_EMAC_TASK_PRIORITY=20 +CONFIG_EMAC_TASK_STACK_SIZE=3072 + +# +# FAT Filesystem support +# +CONFIG_FATFS_CODEPAGE_DYNAMIC= +CONFIG_FATFS_CODEPAGE_437=y +CONFIG_FATFS_CODEPAGE_720= +CONFIG_FATFS_CODEPAGE_737= +CONFIG_FATFS_CODEPAGE_771= +CONFIG_FATFS_CODEPAGE_775= +CONFIG_FATFS_CODEPAGE_850= +CONFIG_FATFS_CODEPAGE_852= +CONFIG_FATFS_CODEPAGE_855= +CONFIG_FATFS_CODEPAGE_857= +CONFIG_FATFS_CODEPAGE_860= +CONFIG_FATFS_CODEPAGE_861= +CONFIG_FATFS_CODEPAGE_862= +CONFIG_FATFS_CODEPAGE_863= +CONFIG_FATFS_CODEPAGE_864= +CONFIG_FATFS_CODEPAGE_865= +CONFIG_FATFS_CODEPAGE_866= +CONFIG_FATFS_CODEPAGE_869= +CONFIG_FATFS_CODEPAGE_932= +CONFIG_FATFS_CODEPAGE_936= +CONFIG_FATFS_CODEPAGE_949= +CONFIG_FATFS_CODEPAGE_950= +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_LFN_NONE= +CONFIG_FATFS_LFN_HEAP= +CONFIG_FATFS_LFN_STACK=y +CONFIG_FATFS_MAX_LFN=255 +CONFIG_FATFS_API_ENCODING_ANSI_OEM=y +CONFIG_FATFS_API_ENCODING_UTF_16= +CONFIG_FATFS_API_ENCODING_UTF_8= +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y + +# +# Modbus configuration +# +CONFIG_MB_UART_RXD=22 +CONFIG_MB_UART_TXD=23 +CONFIG_MB_UART_RTS=18 +CONFIG_MB_QUEUE_LENGTH=20 +CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048 +CONFIG_MB_SERIAL_BUF_SIZE=256 +CONFIG_MB_SERIAL_TASK_PRIO=10 +CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT= +CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_MB_CONTROLLER_STACK_SIZE=4096 +CONFIG_MB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_MB_TIMER_PORT_ENABLED=y +CONFIG_MB_TIMER_GROUP=0 +CONFIG_MB_TIMER_INDEX=0 + +# +# FreeRTOS +# +CONFIG_FREERTOS_UNICORE= +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_CORETIMER_0=y +CONFIG_FREERTOS_CORETIMER_1= +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE= +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL= +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK= +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y +CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE= +CONFIG_FREERTOS_ASSERT_DISABLE= +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +CONFIG_FREERTOS_LEGACY_HOOKS= +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +CONFIG_SUPPORT_STATIC_ALLOCATION=y +CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK= +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_USE_TRACE_FACILITY= +CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS= +CONFIG_FREERTOS_DEBUG_INTERNALS= + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +CONFIG_HEAP_POISONING_LIGHT= +CONFIG_HEAP_POISONING_COMPREHENSIVE= +CONFIG_HEAP_TRACING= + +# +# libsodium +# +CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y + +# +# Log output +# +CONFIG_LOG_DEFAULT_LEVEL_NONE= +CONFIG_LOG_DEFAULT_LEVEL_ERROR= +CONFIG_LOG_DEFAULT_LEVEL_WARN= +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +CONFIG_LOG_DEFAULT_LEVEL_DEBUG= +CONFIG_LOG_DEFAULT_LEVEL_VERBOSE= +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_COLORS=y + +# +# LWIP +# +CONFIG_L2_TO_L3_COPY= +CONFIG_LWIP_IRAM_OPTIMIZATION= +CONFIG_LWIP_MAX_SOCKETS=10 +CONFIG_USE_ONLY_LWIP_SELECT= +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +CONFIG_LWIP_SO_RCVBUF= +CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 +CONFIG_LWIP_IP_FRAG= +CONFIG_LWIP_IP_REASSEMBLY= +CONFIG_LWIP_STATS= +CONFIG_LWIP_ETHARP_TRUST_IP_MAC= +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +CONFIG_LWIP_DHCP_RESTORE_LAST_IP= + +# +# DHCP server +# +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +CONFIG_LWIP_AUTOIP= +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=6 +CONFIG_TCP_MSS=1436 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5744 +CONFIG_TCP_WND_DEFAULT=5744 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES= +CONFIG_TCP_OVERSIZE_MSS=y +CONFIG_TCP_OVERSIZE_QUARTER_MSS= +CONFIG_TCP_OVERSIZE_DISABLE= + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +CONFIG_TCPIP_TASK_AFFINITY_CPU0= +CONFIG_TCPIP_TASK_AFFINITY_CPU1= +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +CONFIG_PPP_SUPPORT= + +# +# ICMP +# +CONFIG_LWIP_MULTICAST_PING= +CONFIG_LWIP_BROADCAST_PING= + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC= +CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC= +CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC= +CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384 +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN= +CONFIG_MBEDTLS_DEBUG= +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_HARDWARE_MPI= +CONFIG_MBEDTLS_HARDWARE_SHA= +CONFIG_MBEDTLS_HAVE_TIME=y +CONFIG_MBEDTLS_HAVE_TIME_DATE= +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +CONFIG_MBEDTLS_TLS_SERVER_ONLY= +CONFIG_MBEDTLS_TLS_CLIENT_ONLY= +CONFIG_MBEDTLS_TLS_DISABLED= +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +CONFIG_MBEDTLS_PSK_MODES= +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +CONFIG_MBEDTLS_SSL_PROTO_SSL3= +CONFIG_MBEDTLS_SSL_PROTO_TLS1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +CONFIG_MBEDTLS_SSL_PROTO_DTLS= +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +CONFIG_MBEDTLS_CAMELLIA_C= +CONFIG_MBEDTLS_DES_C= +CONFIG_MBEDTLS_RC4_DISABLED=y +CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT= +CONFIG_MBEDTLS_RC4_ENABLED= +CONFIG_MBEDTLS_BLOWFISH_C= +CONFIG_MBEDTLS_XTEA_C= +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +CONFIG_MBEDTLS_RIPEMD160_C= + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y + +# +# mDNS +# +CONFIG_MDNS_MAX_SERVICES=10 + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +CONFIG_MQTT_USE_CUSTOM_CONFIG= +CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED= +CONFIG_MQTT_CUSTOM_OUTBOX= + +# +# NVS +# + +# +# OpenSSL +# +CONFIG_OPENSSL_DEBUG= +CONFIG_OPENSSL_ASSERT_DO_NOTHING=y +CONFIG_OPENSSL_ASSERT_EXIT= + +# +# PThreads +# +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0= +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1= +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" + +# +# SPI Flash driver +# +CONFIG_SPI_FLASH_VERIFY_WRITE= +CONFIG_SPI_FLASH_ENABLE_COUNTERS= +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS= +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED= + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +CONFIG_SPIFFS_CACHE_STATS= +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +CONFIG_SPIFFS_GC_STATS= +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +CONFIG_SPIFFS_DBG= +CONFIG_SPIFFS_API_DBG= +CONFIG_SPIFFS_GC_DBG= +CONFIG_SPIFFS_CACHE_DBG= +CONFIG_SPIFFS_CHECK_DBG= +CONFIG_SPIFFS_TEST_VISUALISATION= + +# +# TCP/IP Adapter +# +CONFIG_IP_LOST_TIMER_INTERVAL=120 +CONFIG_TCPIP_LWIP=y + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +CONFIG_UNITY_ENABLE_COLOR= +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +CONFIG_UNITY_ENABLE_FIXTURE= + +# +# Virtual file system +# +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y + +# +# Wear Levelling +# +CONFIG_WL_SECTOR_SIZE_512= +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 diff --git a/MCUME_esp32/espcastaway/.DS_Store b/MCUME_esp32/espcastaway/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..06928c756d78095890aa3134f60a0f7e36549427 GIT binary patch literal 6148 zcmeHK&2G~`5T0!fY>W^&RD$02(p!*fP*8e6vO+lYR>`P60BY?xG?tuQD|U!V2=X)Z z*uGI;pnZcLc!|#b#7gB9!3CjcN1FX+cV_nIi@ciw0Mebr9zYWSD5^xq#b$*_ztoy+ zm=T#r)Eojh3{VTmYteSVGGH0_-x!eJt_yt-FoF!*>ibPky`V2f+0uqr#*IX;7f*^l zz)ky>tLO*f;y;SZhP8Da+*=3<@MxN6Q7R%_!eSU1`=bzPWrxvWGMFAWx84h0gb5#vRdNy!Fy!-5!ecS*iV2T% zHBX=&ls0JNxVb%>wf9==mG^pY-eNPa{kGF$oz9#2yg^^=c<=U4MrYq=KjuF#G=l_h zNF~n=F5nW4>Vzv;uY5~Pe?9-D(wBS{yEWhM82uKEc`EoR&bHX!VqX^5odNTU)2Hix zP@$m9?86|wZqA`mZ6@YN|AA;MwNn%d5)DKpW>IOO3=rof#@47HR1@0{Ue}g Lu#IKlpE7U<|%e`*uyVBBCXVAWNfQGF+rCe6o)pOP91F{w=aB4uK^y9+ zrB^ELf5aZTrfK_+J<;dG;zkcNVcS30LV-}=)C%Cu7F%8!MjZ--0-?a5fZPuWMX+|vhI)0N(i8w#VOR}q$tA=m zIo6KZ5DbjX6=<&PDF&N6#*@#h9kZdi6MOQ(9{D$UVU3RUlTIhD4WkYPLV>9Qm)2d$ z`+tYOOfkuyxS9f512&f=Yg#sr~;0I9mJyiez literal 0 HcmV?d00001 diff --git a/MCUME_esp32/espcastaway/components/Audio/.DS_Store b/MCUME_esp32/espcastaway/components/Audio/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..5008ddfcf53c02e82d7eee2e57c38e5672ef89f6 GIT binary patch literal 6148 zcmeH~Jr2S!425mzP>H1@V-^m;4Wg<&0T*E43hX&L&p$$qDprKhvt+--jT7}7np#A3 zem<@ulZcFPQ@L2!n>{z**++&mCkOWA81W14cNZlEfg7;MkzE(HCqgga^y>{tEnwC%0;vJ&^%eQ zLs35+`xjp>T0 26){ + return;//not dac pin + } + pinMode(pin, ANALOG); + uint8_t channel = pin - 25; + + + //Disable Tone + CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL1_REG, SENS_SW_TONE_EN); + + if (channel) { + //Disable Channel Tone + CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN2_M); + //Set the Dac value + SET_PERI_REG_BITS(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_DAC, value, RTC_IO_PDAC2_DAC_S); //dac_output + //Channel output enable + SET_PERI_REG_MASK(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_XPD_DAC | RTC_IO_PDAC2_DAC_XPD_FORCE); + } else { + //Disable Channel Tone + CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN1_M); + //Set the Dac value + SET_PERI_REG_BITS(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_DAC, value, RTC_IO_PDAC1_DAC_S); //dac_output + //Channel output enable + SET_PERI_REG_MASK(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_XPD_DAC | RTC_IO_PDAC1_DAC_XPD_FORCE); + } +} + +extern void dacWrite(uint8_t pin, uint8_t value) __attribute__ ((weak, alias("__dacWrite"))); diff --git a/MCUME_esp32/espcastaway/components/Audio/esp32-hal-dac.h b/MCUME_esp32/espcastaway/components/Audio/esp32-hal-dac.h new file mode 100644 index 0000000..c311be1 --- /dev/null +++ b/MCUME_esp32/espcastaway/components/Audio/esp32-hal-dac.h @@ -0,0 +1,36 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAIN_ESP32_HAL_DAC_H_ +#define MAIN_ESP32_HAL_DAC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +//#include "esp32-hal.h" +#include "driver/gpio.h" + +void dacWrite(uint8_t pin, uint8_t value); + +#ifdef __cplusplus +} +#endif + +#endif /* MAIN_ESP32_HAL_DAC_H_ */ diff --git a/MCUME_esp32/espcastaway/components/Audio/esp32-hal-timer.c b/MCUME_esp32/espcastaway/components/Audio/esp32-hal-timer.c new file mode 100644 index 0000000..17743a4 --- /dev/null +++ b/MCUME_esp32/espcastaway/components/Audio/esp32-hal-timer.c @@ -0,0 +1,293 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-timer.h" +#include "freertos/FreeRTOS.h" +#include "freertos/xtensa_api.h" +#include "freertos/task.h" +#include "rom/ets_sys.h" +#include "soc/timer_group_struct.h" +#include "soc/dport_reg.h" +#include "esp_attr.h" +#include "esp_intr.h" + +#define HWTIMER_LOCK() portENTER_CRITICAL(timer->lock) +#define HWTIMER_UNLOCK() portEXIT_CRITICAL(timer->lock) + +typedef struct { + union { + struct { + uint32_t reserved0: 10; + uint32_t alarm_en: 1; /*When set alarm is enabled*/ + uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/ + uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/ + uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/ + uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/ + uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/ + uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/ + }; + uint32_t val; + } config; + uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/ + uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/ + uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/ + uint32_t alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ + uint32_t alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ + uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/ + uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/ + uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/ +} hw_timer_reg_t; + +typedef struct hw_timer_s { + hw_timer_reg_t * dev; + uint8_t num; + uint8_t group; + uint8_t timer; + portMUX_TYPE lock; +} hw_timer_t; + +static hw_timer_t hw_timer[4] = { + {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE),0,0,0,portMUX_INITIALIZER_UNLOCKED}, + {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x0024),1,0,1,portMUX_INITIALIZER_UNLOCKED}, + {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x1000),2,1,0,portMUX_INITIALIZER_UNLOCKED}, + {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x1024),3,1,1,portMUX_INITIALIZER_UNLOCKED} +}; + +typedef void (*voidFuncPtr)(void); +static voidFuncPtr __timerInterruptHandlers[4] = {0,0,0,0}; + +void IRAM_ATTR __timerISR(void * arg){ + uint32_t s0 = TIMERG0.int_st_timers.val; + uint32_t s1 = TIMERG1.int_st_timers.val; + TIMERG0.int_clr_timers.val = s0; + TIMERG1.int_clr_timers.val = s1; + uint8_t status = (s1 & 3) << 2 | (s0 & 3); + uint8_t i = 4; + //restart the timers that should autoreload + while(i--){ + hw_timer_reg_t * dev = hw_timer[i].dev; + if((status & (1 << i)) && dev->config.autoreload){ + dev->config.alarm_en = 1; + } + } + i = 4; + //call callbacks + while(i--){ + if(__timerInterruptHandlers[i] && status & (1 << i)){ + __timerInterruptHandlers[i](); + } + } +} + +uint64_t timerRead(hw_timer_t *timer){ + timer->dev->update = 1; + uint64_t h = timer->dev->cnt_high; + uint64_t l = timer->dev->cnt_low; + return (h << 32) | l; +} + +uint64_t timerAlarmRead(hw_timer_t *timer){ + uint64_t h = timer->dev->alarm_high; + uint64_t l = timer->dev->alarm_low; + return (h << 32) | l; +} + +void timerWrite(hw_timer_t *timer, uint64_t val){ + timer->dev->load_high = (uint32_t) (val >> 32); + timer->dev->load_low = (uint32_t) (val); + timer->dev->reload = 1; +} + +void timerAlarmWrite(hw_timer_t *timer, uint64_t alarm_value, bool autoreload){ + timer->dev->alarm_high = (uint32_t) (alarm_value >> 32); + timer->dev->alarm_low = (uint32_t) alarm_value; + timer->dev->config.autoreload = autoreload; +} + +void timerSetConfig(hw_timer_t *timer, uint32_t config){ + timer->dev->config.val = config; +} + +uint32_t timerGetConfig(hw_timer_t *timer){ + return timer->dev->config.val; +} + +void timerSetCountUp(hw_timer_t *timer, bool countUp){ + timer->dev->config.increase = countUp; +} + +bool timerGetCountUp(hw_timer_t *timer){ + return timer->dev->config.increase; +} + +void timerSetAutoReload(hw_timer_t *timer, bool autoreload){ + timer->dev->config.autoreload = autoreload; +} + +bool timerGetAutoReload(hw_timer_t *timer){ + return timer->dev->config.autoreload; +} + +void timerSetDivider(hw_timer_t *timer, uint16_t divider){//2 to 65536 + if(!divider){ + divider = 0xFFFF; + } else if(divider == 1){ + divider = 2; + } + int timer_en = timer->dev->config.enable; + timer->dev->config.enable = 0; + timer->dev->config.divider = divider; + timer->dev->config.enable = timer_en; +} + +uint16_t timerGetDivider(hw_timer_t *timer){ + return timer->dev->config.divider; +} + +void timerStart(hw_timer_t *timer){ + timer->dev->config.enable = 1; +} + +void timerStop(hw_timer_t *timer){ + timer->dev->config.enable = 0; +} + +void timerRestart(hw_timer_t *timer){ + timer->dev->config.enable = 0; + timer->dev->config.enable = 1; +} + +bool timerStarted(hw_timer_t *timer){ + return timer->dev->config.enable; +} + +void timerAlarmEnable(hw_timer_t *timer){ + timer->dev->config.alarm_en = 1; +} + +void timerAlarmDisable(hw_timer_t *timer){ + timer->dev->config.alarm_en = 0; +} + +bool timerAlarmEnabled(hw_timer_t *timer){ + return timer->dev->config.alarm_en; +} + +hw_timer_t * timerBegin(uint8_t num, uint16_t divider, bool countUp){ + if(num > 3){ + return NULL; + } + hw_timer_t * timer = &hw_timer[num]; + if(timer->group) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST); + TIMERG1.int_ena.val &= ~BIT(timer->timer); + } else { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST); + TIMERG0.int_ena.val &= ~BIT(timer->timer); + } + timer->dev->config.enable = 0; + timerSetDivider(timer, divider); + timerSetCountUp(timer, countUp); + timerSetAutoReload(timer, false); + timerAttachInterrupt(timer, NULL, false); + timerWrite(timer, 0); + timer->dev->config.enable = 1; + return timer; +} + +void timerEnd(hw_timer_t *timer){ + timer->dev->config.enable = 0; + timerAttachInterrupt(timer, NULL, false); +} + +void timerAttachInterrupt(hw_timer_t *timer, void (*fn)(void), bool edge){ + static bool initialized = false; + static intr_handle_t intr_handle = NULL; + if(intr_handle){ + esp_intr_disable(intr_handle); + } + if(fn == NULL){ + timer->dev->config.level_int_en = 0; + timer->dev->config.edge_int_en = 0; + timer->dev->config.alarm_en = 0; + if(timer->num & 2){ + TIMERG1.int_ena.val &= ~BIT(timer->timer); + } else { + TIMERG0.int_ena.val &= ~BIT(timer->timer); + } + __timerInterruptHandlers[timer->num] = NULL; + } else { + __timerInterruptHandlers[timer->num] = fn; + timer->dev->config.level_int_en = edge?0:1;//When set, an alarm will generate a level type interrupt. + timer->dev->config.edge_int_en = edge?1:0;//When set, an alarm will generate an edge type interrupt. + int intr_source = 0; + if(!edge){ + if(timer->group){ + intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer->timer; + } else { + intr_source = ETS_TG0_T0_LEVEL_INTR_SOURCE + timer->timer; + } + } else { + if(timer->group){ + intr_source = ETS_TG1_T0_EDGE_INTR_SOURCE + timer->timer; + } else { + intr_source = ETS_TG0_T0_EDGE_INTR_SOURCE + timer->timer; + } + } + if(!initialized){ + initialized = true; + esp_intr_alloc(intr_source, (int)(ESP_INTR_FLAG_IRAM|ESP_INTR_FLAG_LOWMED|ESP_INTR_FLAG_EDGE), __timerISR, NULL, &intr_handle); + } else { + intr_matrix_set(esp_intr_get_cpu(intr_handle), intr_source, esp_intr_get_intno(intr_handle)); + } + if(timer->group){ + TIMERG1.int_ena.val |= BIT(timer->timer); + } else { + TIMERG0.int_ena.val |= BIT(timer->timer); + } + } + if(intr_handle){ + esp_intr_enable(intr_handle); + } +} + +void timerDetachInterrupt(hw_timer_t *timer){ + timerAttachInterrupt(timer, NULL, false); +} + +uint64_t timerReadMicros(hw_timer_t *timer){ + uint64_t timer_val = timerRead(timer); + uint16_t div = timerGetDivider(timer); + return timer_val * div / 80; +} + +double timerReadSeconds(hw_timer_t *timer){ + uint64_t timer_val = timerRead(timer); + uint16_t div = timerGetDivider(timer); + return (double)timer_val * div / 80000000; +} + +uint64_t timerAlarmReadMicros(hw_timer_t *timer){ + uint64_t timer_val = timerAlarmRead(timer); + uint16_t div = timerGetDivider(timer); + return timer_val * div / 80; +} + +double timerAlarmReadSeconds(hw_timer_t *timer){ + uint64_t timer_val = timerAlarmRead(timer); + uint16_t div = timerGetDivider(timer); + return (double)timer_val * div / 80000000; +} diff --git a/MCUME_esp32/espcastaway/components/Audio/esp32-hal-timer.h b/MCUME_esp32/espcastaway/components/Audio/esp32-hal-timer.h new file mode 100644 index 0000000..fa4e8c7 --- /dev/null +++ b/MCUME_esp32/espcastaway/components/Audio/esp32-hal-timer.h @@ -0,0 +1,72 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAIN_ESP32_HAL_TIMER_H_ +#define MAIN_ESP32_HAL_TIMER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +//#include "esp32-hal.h" +#include "freertos/FreeRTOS.h" + +struct hw_timer_s; +typedef struct hw_timer_s hw_timer_t; + +hw_timer_t * timerBegin(uint8_t timer, uint16_t divider, bool countUp); +void timerEnd(hw_timer_t *timer); + +void timerSetConfig(hw_timer_t *timer, uint32_t config); +uint32_t timerGetConfig(hw_timer_t *timer); + +void timerAttachInterrupt(hw_timer_t *timer, void (*fn)(void), bool edge); +void timerDetachInterrupt(hw_timer_t *timer); + +void timerStart(hw_timer_t *timer); +void timerStop(hw_timer_t *timer); +void timerRestart(hw_timer_t *timer); +void timerWrite(hw_timer_t *timer, uint64_t val); +void timerSetDivider(hw_timer_t *timer, uint16_t divider); +void timerSetCountUp(hw_timer_t *timer, bool countUp); +void timerSetAutoReload(hw_timer_t *timer, bool autoreload); + +bool timerStarted(hw_timer_t *timer); +uint64_t timerRead(hw_timer_t *timer); +uint64_t timerReadMicros(hw_timer_t *timer); +double timerReadSeconds(hw_timer_t *timer); +uint16_t timerGetDivider(hw_timer_t *timer); +bool timerGetCountUp(hw_timer_t *timer); +bool timerGetAutoReload(hw_timer_t *timer); + +void timerAlarmEnable(hw_timer_t *timer); +void timerAlarmDisable(hw_timer_t *timer); +void timerAlarmWrite(hw_timer_t *timer, uint64_t interruptAt, bool autoreload); + +bool timerAlarmEnabled(hw_timer_t *timer); +uint64_t timerAlarmRead(hw_timer_t *timer); +uint64_t timerAlarmReadMicros(hw_timer_t *timer); +double timerAlarmReadSeconds(hw_timer_t *timer); + + +#ifdef __cplusplus +} +#endif + +#endif /* MAIN_ESP32_HAL_TIMER_H_ */ diff --git a/MCUME_esp32/espcastaway/components/Wire/.DS_Store b/MCUME_esp32/espcastaway/components/Wire/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..5008ddfcf53c02e82d7eee2e57c38e5672ef89f6 GIT binary patch literal 6148 zcmeH~Jr2S!425mzP>H1@V-^m;4Wg<&0T*E43hX&L&p$$qDprKhvt+--jT7}7np#A3 zem<@ulZcFPQ@L2!n>{z**++&mCkOWA81W14cNZlEfg7;MkzE(HCqgga^y>{tEnwC%0;vJ&^%eQ zLs35+`xjp>T0 +#include +#include +} + +#include "esp32-hal-i2c.h" +#include "Wire.h" +//#include "Arduino.h" + + + + + +TwoWire::TwoWire(uint8_t bus_num) + :num(bus_num & 1) + ,sda(-1) + ,scl(-1) + ,i2c(NULL) + ,rxIndex(0) + ,rxLength(0) + ,rxQueued(0) + ,txIndex(0) + ,txLength(0) + ,txAddress(0) + ,txQueued(0) + ,transmitting(0) + ,last_error(I2C_ERROR_OK) + ,_timeOutMillis(50) +{} + +TwoWire::~TwoWire() +{ + flush(); + if(i2c) { + i2cRelease(i2c); + i2c=NULL; + } +} + +bool TwoWire::begin(int sdaPin, int sclPin, uint32_t frequency) +{ + if(sdaPin < 0) { // default param passed + if(num == 0) { + if(sda==-1) { + sdaPin = SDA; //use Default Pin + } else { + sdaPin = sda; // reuse prior pin + } + } else { + if(sda==-1) { + //log_e("no Default SDA Pin for Second Peripheral"); + return false; //no Default pin for Second Peripheral + } else { + sdaPin = sda; // reuse prior pin + } + } + } + + if(sclPin < 0) { // default param passed + if(num == 0) { + if(scl == -1) { + sclPin = SCL; // use Default pin + } else { + sclPin = scl; // reuse prior pin + } + } else { + if(scl == -1) { + //log_e("no Default SCL Pin for Second Peripheral"); + return false; //no Default pin for Second Peripheral + } else { + sclPin = scl; // reuse prior pin + } + } + } + + sda = sdaPin; + scl = sclPin; + i2c = i2cInit(num, sdaPin, sclPin, frequency); + if(!i2c) { + printf("I2C init failed"); + return false; + } + + flush(); + return true; + +} + +void TwoWire::setTimeOut(uint16_t timeOutMillis) +{ + _timeOutMillis = timeOutMillis; +} + +uint16_t TwoWire::getTimeOut() +{ + return _timeOutMillis; +} + +void TwoWire::setClock(uint32_t frequency) +{ + i2cSetFrequency(i2c, frequency); +} + +size_t TwoWire::getClock() +{ + return i2cGetFrequency(i2c); +} + +/* stickBreaker Nov 2017 ISR, and bigblock 64k-1 + */ +i2c_err_t TwoWire::writeTransmission(uint16_t address, uint8_t *buff, uint16_t size, bool sendStop) +{ + last_error = i2cWrite(i2c, address, buff, size, sendStop, _timeOutMillis); + return last_error; +} + +i2c_err_t TwoWire::readTransmission(uint16_t address, uint8_t *buff, uint16_t size, bool sendStop, uint32_t *readCount) +{ + last_error = i2cRead(i2c, address, buff, size, sendStop, _timeOutMillis, readCount); + return last_error; +} + +void TwoWire::beginTransmission(uint16_t address) +{ + transmitting = 1; + txAddress = address; + txIndex = txQueued; // allow multiple beginTransmission(),write(),endTransmission(false) until endTransmission(true) + txLength = txQueued; + last_error = I2C_ERROR_OK; +} + +/*stickbreaker isr + */ +uint8_t TwoWire::endTransmission(bool sendStop) // Assumes Wire.beginTransaction(), Wire.write() +{ + if(transmitting == 1) { + last_error = writeTransmission(txAddress, &txBuffer[txQueued], txLength - txQueued, sendStop); + rxIndex = 0; + rxLength = rxQueued; + rxQueued = 0; + txQueued = 0; // the SendStop=true will restart all Queueing + if(last_error == I2C_ERROR_CONTINUE){ + // txlength is howmany bytes in txbuffer have been use + txQueued = txLength; + } + } else { + last_error = I2C_ERROR_NO_BEGIN; + flush(); + } + txIndex = 0; + txLength = 0; + transmitting = 0; + return last_error; +} + +/* @stickBreaker 11/2017 fix for ReSTART timeout, ISR + */ +uint8_t TwoWire::requestFrom(uint16_t address, uint8_t size, bool sendStop) +{ + //use internal Wire rxBuffer, multiple requestFrom()'s may be pending, try to share rxBuffer + uint32_t cnt = rxQueued; // currently queued reads, next available position in rxBuffer + if(cnt < (I2C_BUFFER_LENGTH-1) && (size + cnt) <= I2C_BUFFER_LENGTH) { // any room left in rxBuffer + rxQueued += size; + } else { // no room to receive more! + //log_e("rxBuff overflow %d", cnt + size); + cnt = 0; + last_error = I2C_ERROR_MEMORY; + flush(); + return cnt; + } + + last_error = readTransmission(address, &rxBuffer[cnt], size, sendStop, &cnt); + rxIndex = 0; + rxLength = rxQueued; + rxQueued = 0; + txQueued = 0; // the SendStop=true will restart all Queueing + if(last_error != I2C_ERROR_OK){ + cnt = 0; + } + return cnt; +} + +size_t TwoWire::write(uint8_t data) +{ + if(transmitting) { + if(txLength >= I2C_BUFFER_LENGTH) { + last_error = I2C_ERROR_MEMORY; + return 0; + } + txBuffer[txIndex] = data; + ++txIndex; + txLength = txIndex; + return 1; + } + last_error = I2C_ERROR_NO_BEGIN; // no begin, not transmitting + return 0; +} + +size_t TwoWire::write(const uint8_t *data, size_t quantity) +{ + for(size_t i = 0; i < quantity; ++i) { + if(!write(data[i])) { + return i; + } + } + return quantity; + +} + +int TwoWire::available(void) +{ + int result = rxLength - rxIndex; + return result; +} + +int TwoWire::read(void) +{ + int value = -1; + if(rxIndex < rxLength) { + value = rxBuffer[rxIndex]; + ++rxIndex; + } + return value; +} + +int TwoWire::peek(void) +{ + int value = -1; + if(rxIndex < rxLength) { + value = rxBuffer[rxIndex]; + } + return value; +} + +void TwoWire::flush(void) +{ + rxIndex = 0; + rxLength = 0; + txIndex = 0; + txLength = 0; + rxQueued = 0; + txQueued = 0; + i2cFlush(i2c); // cleanup +} + +uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop) +{ + return requestFrom(static_cast(address), static_cast(quantity), static_cast(sendStop)); +} + +uint8_t TwoWire::requestFrom(uint16_t address, uint8_t quantity, uint8_t sendStop) +{ + return requestFrom(address, static_cast(quantity), static_cast(sendStop)); +} + +uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity) +{ + return requestFrom(static_cast(address), static_cast(quantity), true); +} + +uint8_t TwoWire::requestFrom(uint16_t address, uint8_t quantity) +{ + return requestFrom(address, static_cast(quantity), true); +} + +uint8_t TwoWire::requestFrom(int address, int quantity) +{ + return requestFrom(static_cast(address), static_cast(quantity), true); +} + +uint8_t TwoWire::requestFrom(int address, int quantity, int sendStop) +{ + return static_cast(requestFrom(static_cast(address), static_cast(quantity), static_cast(sendStop))); +} + +void TwoWire::beginTransmission(int address) +{ + beginTransmission(static_cast(address)); +} + +void TwoWire::beginTransmission(uint8_t address) +{ + beginTransmission(static_cast(address)); +} + +uint8_t TwoWire::endTransmission(void) +{ + return endTransmission(true); +} + +/* stickbreaker Nov2017 better error reporting + */ +uint8_t TwoWire::lastError() +{ + return (uint8_t)last_error; +} + +const char ERRORTEXT[] = + "OK\0" + "DEVICE\0" + "ACK\0" + "TIMEOUT\0" + "BUS\0" + "BUSY\0" + "MEMORY\0" + "CONTINUE\0" + "NO_BEGIN\0" + "\0"; + + +char * TwoWire::getErrorText(uint8_t err) +{ + uint8_t t = 0; + bool found = false; + char * message = (char*)&ERRORTEXT; + + while(!found && message[0]) { + found = t == err; + if(!found) { + message = message + strlen(message) + 1; + t++; + } + } + if(!found) { + return NULL; + } else { + return message; + } +} + +/*stickbreaker Dump i2c Interrupt buffer, i2c isr Debugging + */ + +uint32_t TwoWire::setDebugFlags( uint32_t setBits, uint32_t resetBits){ + return i2cDebug(i2c,setBits,resetBits); +} + +bool TwoWire::busy(void){ + return ((i2cGetStatus(i2c) & 16 )==16); +} + +TwoWire Wire = TwoWire(0); +TwoWire Wire1 = TwoWire(1); diff --git a/MCUME_esp32/espcastaway/components/Wire/Wire.h b/MCUME_esp32/espcastaway/components/Wire/Wire.h new file mode 100644 index 0000000..0420b2e --- /dev/null +++ b/MCUME_esp32/espcastaway/components/Wire/Wire.h @@ -0,0 +1,132 @@ +/* + TwoWire.h - TWI/I2C library for Arduino & Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts + Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support + Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support + Modified November 2017 by Chuck Todd to use ISR and increase stability. +*/ + +#ifndef TwoWire_h +#define TwoWire_h + +#include "esp32-hal-i2c.h" +#include "freertos/FreeRTOS.h" +#include "freertos/queue.h" + + + +#define SDA (gpio_num_t)4 +#define SCL (gpio_num_t)5 + + +#define STICKBREAKER V1.0.1 +#define I2C_BUFFER_LENGTH 128 +typedef void(*user_onRequest)(void); +typedef void(*user_onReceive)(uint8_t*, int); + +class TwoWire +{ +protected: + uint8_t num; + int8_t sda; + int8_t scl; + i2c_t * i2c; + + uint8_t rxBuffer[I2C_BUFFER_LENGTH]; + uint16_t rxIndex; + uint16_t rxLength; + uint16_t rxQueued; //@stickBreaker + + uint8_t txBuffer[I2C_BUFFER_LENGTH]; + uint16_t txIndex; + uint16_t txLength; + uint16_t txAddress; + uint16_t txQueued; //@stickbreaker + + uint8_t transmitting; + /* slave Mode, not yet Stickbreaker + static user_onRequest uReq[2]; + static user_onReceive uRcv[2]; + void onRequestService(void); + void onReceiveService(uint8_t*, int); + */ + i2c_err_t last_error; // @stickBreaker from esp32-hal-i2c.h + uint16_t _timeOutMillis; + +public: + TwoWire(uint8_t bus_num); + ~TwoWire(); + bool begin(int sda=-1, int scl=-1, uint32_t frequency=0); + + void setClock(uint32_t frequency); // change bus clock without initing hardware + size_t getClock(); // current bus clock rate in hz + + void setTimeOut(uint16_t timeOutMillis); + uint16_t getTimeOut(); + + uint8_t lastError(); + char * getErrorText(uint8_t err); + + //@stickBreaker for big blocks and ISR model + i2c_err_t writeTransmission(uint16_t address, uint8_t* buff, uint16_t size, bool sendStop=true); + i2c_err_t readTransmission(uint16_t address, uint8_t* buff, uint16_t size, bool sendStop=true, uint32_t *readCount=NULL); + + void beginTransmission(uint16_t address); + void beginTransmission(uint8_t address); + void beginTransmission(int address); + + uint8_t endTransmission(bool sendStop); + uint8_t endTransmission(void); + + uint8_t requestFrom(uint16_t address, uint8_t size, bool sendStop); + uint8_t requestFrom(uint16_t address, uint8_t size, uint8_t sendStop); + uint8_t requestFrom(uint16_t address, uint8_t size); + uint8_t requestFrom(uint8_t address, uint8_t size, uint8_t sendStop); + uint8_t requestFrom(uint8_t address, uint8_t size); + uint8_t requestFrom(int address, int size, int sendStop); + uint8_t requestFrom(int address, int size); + + size_t write(uint8_t); + size_t write(const uint8_t *, size_t); + int available(void); + int read(void); + int peek(void); + void flush(void); + + + + void onReceive( void (*)(int) ); + void onRequest( void (*)(void) ); + + uint32_t setDebugFlags( uint32_t setBits, uint32_t resetBits); + bool busy(); +}; + +extern TwoWire Wire; +extern TwoWire Wire1; + + +/* +V1.0.1 02AUG2018 First Fix after release, Correct ReSTART handling, change Debug control, change begin() + to a function, this allow reporting if bus cannot be initialized, Wire.begin() can be used to recover + a hung bus busy condition. +V0.2.2 13APR2018 preserve custom SCL,SDA,Frequency when no parameters passed to begin() +V0.2.1 15MAR2018 Hardware reset, Glitch prevention, adding destructor for second i2c testing +*/ +#endif diff --git a/MCUME_esp32/espcastaway/components/Wire/component.mk b/MCUME_esp32/espcastaway/components/Wire/component.mk new file mode 100644 index 0000000..61ff442 --- /dev/null +++ b/MCUME_esp32/espcastaway/components/Wire/component.mk @@ -0,0 +1,11 @@ +# +# Main component makefile. +# +# This Makefile can be left empty. By default, it will take the sources in the +# src/ directory, compile them and link them into lib(subdirectory_name).a +# in the build directory. This behaviour is entirely configurable, +# please read the ESP-IDF documents if you need to do this. +# + +COMPONENT_ADD_INCLUDEDIRS := . +COMPONENT_SRCDIRS := . \ No newline at end of file diff --git a/MCUME_esp32/espcastaway/components/Wire/esp32-hal-gpio.c b/MCUME_esp32/espcastaway/components/Wire/esp32-hal-gpio.c new file mode 100644 index 0000000..999113f --- /dev/null +++ b/MCUME_esp32/espcastaway/components/Wire/esp32-hal-gpio.c @@ -0,0 +1,309 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include "stdint.h" +#include "esp32-hal-gpio.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "rom/ets_sys.h" +#include "esp_attr.h" +#include "esp_intr.h" +#include "rom/gpio.h" +#include "soc/gpio_reg.h" +#include "soc/io_mux_reg.h" +#include "soc/gpio_struct.h" +#include "soc/rtc_io_reg.h" +#include "esp_system.h" + +#define ESP_REG(addr) *((volatile uint32_t *)(addr)) + +const int8_t esp32_adc2gpio[20] = {36, 37, 38, 39, 32, 33, 34, 35, -1, -1, 4, 0, 2, 15, 13, 12, 14, 27, 25, 26}; + +const DRAM_ATTR esp32_gpioMux_t esp32_gpioMux[GPIO_PIN_COUNT]={ + {0x44, 11, 11, 1}, + {0x88, -1, -1, -1}, + {0x40, 12, 12, 2}, + {0x84, -1, -1, -1}, + {0x48, 10, 10, 0}, + {0x6c, -1, -1, -1}, + {0x60, -1, -1, -1}, + {0x64, -1, -1, -1}, + {0x68, -1, -1, -1}, + {0x54, -1, -1, -1}, + {0x58, -1, -1, -1}, + {0x5c, -1, -1, -1}, + {0x34, 15, 15, 5}, + {0x38, 14, 14, 4}, + {0x30, 16, 16, 6}, + {0x3c, 13, 13, 3}, + {0x4c, -1, -1, -1}, + {0x50, -1, -1, -1}, + {0x70, -1, -1, -1}, + {0x74, -1, -1, -1}, + {0x78, -1, -1, -1}, + {0x7c, -1, -1, -1}, + {0x80, -1, -1, -1}, + {0x8c, -1, -1, -1}, + {0, -1, -1, -1}, + {0x24, 6, 18, -1}, //DAC1 + {0x28, 7, 19, -1}, //DAC2 + {0x2c, 17, 17, 7}, + {0, -1, -1, -1}, + {0, -1, -1, -1}, + {0, -1, -1, -1}, + {0, -1, -1, -1}, + {0x1c, 9, 4, 9}, + {0x20, 8, 5, 8}, + {0x14, 4, 6, -1}, + {0x18, 5, 7, -1}, + {0x04, 0, 0, -1}, + {0x08, 1, 1, -1}, + {0x0c, 2, 2, -1}, + {0x10, 3, 3, -1} +}; + +typedef void (*voidFuncPtr)(void); +typedef void (*voidFuncPtrArg)(void*); +typedef struct { + voidFuncPtr fn; + void* arg; + bool functional; +} InterruptHandle_t; +static InterruptHandle_t __pinInterruptHandlers[GPIO_PIN_COUNT] = {0,}; + +#include "driver/rtc_io.h" + +extern void IRAM_ATTR __pinMode(uint8_t pin, uint8_t mode) +{ + + if(!digitalPinIsValid(pin)) { + return; + } + + uint32_t rtc_reg = rtc_gpio_desc[pin].reg; + if(mode == ANALOG) { + if(!rtc_reg) { + return;//not rtc pin + } + //lock rtc + uint32_t reg_val = ESP_REG(rtc_reg); + if(reg_val & rtc_gpio_desc[pin].mux){ + return;//already in adc mode + } + reg_val &= ~( + (RTC_IO_TOUCH_PAD1_FUN_SEL_V << rtc_gpio_desc[pin].func) + |rtc_gpio_desc[pin].ie + |rtc_gpio_desc[pin].pullup + |rtc_gpio_desc[pin].pulldown); + ESP_REG(RTC_GPIO_ENABLE_W1TC_REG) = (1 << (rtc_gpio_desc[pin].rtc_num + RTC_GPIO_ENABLE_W1TC_S)); + ESP_REG(rtc_reg) = reg_val | rtc_gpio_desc[pin].mux; + //unlock rtc + ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioMux[pin].reg) = ((uint32_t)2 << MCU_SEL_S) | ((uint32_t)2 << FUN_DRV_S) | FUN_IE; + return; + } + + //RTC pins PULL settings + if(rtc_reg) { + //lock rtc + ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].mux); + if(mode & PULLUP) { + ESP_REG(rtc_reg) = (ESP_REG(rtc_reg) | rtc_gpio_desc[pin].pullup) & ~(rtc_gpio_desc[pin].pulldown); + } else if(mode & PULLDOWN) { + ESP_REG(rtc_reg) = (ESP_REG(rtc_reg) | rtc_gpio_desc[pin].pulldown) & ~(rtc_gpio_desc[pin].pullup); + } else { + ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].pullup | rtc_gpio_desc[pin].pulldown); + } + //unlock rtc + } + + uint32_t pinFunction = 0, pinControl = 0; + + //lock gpio + if(mode & INPUT) { + if(pin < 32) { + GPIO.enable_w1tc = ((uint32_t)1 << pin); + } else { + GPIO.enable1_w1tc.val = ((uint32_t)1 << (pin - 32)); + } + } else if(mode & OUTPUT) { + if(pin > 33){ + //unlock gpio + return;//pins above 33 can be only inputs + } else if(pin < 32) { + GPIO.enable_w1ts = ((uint32_t)1 << pin); + } else { + GPIO.enable1_w1ts.val = ((uint32_t)1 << (pin - 32)); + } + } + + if(mode & PULLUP) { + pinFunction |= FUN_PU; + } else if(mode & PULLDOWN) { + pinFunction |= FUN_PD; + } + + pinFunction |= ((uint32_t)2 << FUN_DRV_S);//what are the drivers? + pinFunction |= FUN_IE;//input enable but required for output as well? + + if(mode & (INPUT | OUTPUT)) { + pinFunction |= ((uint32_t)2 << MCU_SEL_S); + } else if(mode == SPECIAL) { + pinFunction |= ((uint32_t)(((pin)==1||(pin)==3)?0:1) << MCU_SEL_S); + } else { + pinFunction |= ((uint32_t)(mode >> 5) << MCU_SEL_S); + } + + ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioMux[pin].reg) = pinFunction; + + if(mode & OPEN_DRAIN) { + pinControl = (1 << GPIO_PIN0_PAD_DRIVER_S); + } + + GPIO.pin[pin].val = pinControl; + //unlock gpio +} + +extern void IRAM_ATTR __digitalWrite(uint8_t pin, uint8_t val) +{ + if(val) { + if(pin < 32) { + GPIO.out_w1ts = ((uint32_t)1 << pin); + } else if(pin < 34) { + GPIO.out1_w1ts.val = ((uint32_t)1 << (pin - 32)); + } + } else { + if(pin < 32) { + GPIO.out_w1tc = ((uint32_t)1 << pin); + } else if(pin < 34) { + GPIO.out1_w1tc.val = ((uint32_t)1 << (pin - 32)); + } + } +} + +extern int IRAM_ATTR __digitalRead(uint8_t pin) +{ + if(pin < 32) { + return (GPIO.in >> pin) & 0x1; + } else if(pin < 40) { + return (GPIO.in1.val >> (pin - 32)) & 0x1; + } + return 0; +} + +static intr_handle_t gpio_intr_handle = NULL; + +static void IRAM_ATTR __onPinInterrupt() +{ + uint32_t gpio_intr_status_l=0; + uint32_t gpio_intr_status_h=0; + + gpio_intr_status_l = GPIO.status; + gpio_intr_status_h = GPIO.status1.val; + GPIO.status_w1tc = gpio_intr_status_l;//Clear intr for gpio0-gpio31 + GPIO.status1_w1tc.val = gpio_intr_status_h;//Clear intr for gpio32-39 + + uint8_t pin=0; + if(gpio_intr_status_l) { + do { + if(gpio_intr_status_l & ((uint32_t)1 << pin)) { + if(__pinInterruptHandlers[pin].fn) { + if(__pinInterruptHandlers[pin].arg){ + ((voidFuncPtrArg)__pinInterruptHandlers[pin].fn)(__pinInterruptHandlers[pin].arg); + } else { + __pinInterruptHandlers[pin].fn(); + } + } + } + } while(++pin<32); + } + if(gpio_intr_status_h) { + pin=32; + do { + if(gpio_intr_status_h & ((uint32_t)1 << (pin - 32))) { + if(__pinInterruptHandlers[pin].fn) { + if(__pinInterruptHandlers[pin].arg){ + ((voidFuncPtrArg)__pinInterruptHandlers[pin].fn)(__pinInterruptHandlers[pin].arg); + } else { + __pinInterruptHandlers[pin].fn(); + } + } + } + } while(++pin + +#define NOP() asm volatile ("nop") + +unsigned long IRAM_ATTR micros() +{ + return (unsigned long) esp_timer_get_time(); +} + +unsigned long IRAM_ATTR millis() +{ + return (unsigned long) (esp_timer_get_time() / 1000); +} + +void delay(uint32_t ms) +{ + vTaskDelay(ms / portTICK_PERIOD_MS); +} + +void IRAM_ATTR delayMicroseconds(uint32_t us) +{ + uint32_t m = micros(); + if(us){ + uint32_t e = (m + us); + if(m > e){ //overflow + while(micros() > e){ + NOP(); + } + } + while(micros() < e){ + NOP(); + } + } +} +//#define I2C_DEV(i) (volatile i2c_dev_t *)((i)?DR_REG_I2C1_EXT_BASE:DR_REG_I2C_EXT_BASE) +//#define I2C_DEV(i) ((i2c_dev_t *)(REG_I2C_BASE(i))) +#define I2C_SCL_IDX(p) ((p==0)?I2CEXT0_SCL_OUT_IDX:((p==1)?I2CEXT1_SCL_OUT_IDX:0)) +#define I2C_SDA_IDX(p) ((p==0)?I2CEXT0_SDA_OUT_IDX:((p==1)?I2CEXT1_SDA_OUT_IDX:0)) + +#define DR_REG_I2C_EXT_BASE_FIXED 0x60013000 +#define DR_REG_I2C1_EXT_BASE_FIXED 0x60027000 + +/* Stickbreaker ISR mode debug support + +ENABLE_I2C_DEBUG_BUFFER + Enable debug interrupt history buffer, fifoTx history buffer. + Setting this define will result in 2570 bytes of RAM being used whenever CORE_DEBUG_LEVEL + is higher than WARNING. Unless you are debugging a problem in the I2C subsystem, + I would recommend you leave it commented out. + */ + +//#define ENABLE_I2C_DEBUG_BUFFER + +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) +#define INTBUFFMAX 64 +#define FIFOMAX 512 +static uint32_t intBuff[INTBUFFMAX][3][2]; +static uint32_t intPos[2]= {0,0}; +static uint16_t fifoBuffer[FIFOMAX]; +static uint16_t fifoPos = 0; +#endif + +// start from tools/sdk/include/soc/soc/i2c_struct.h + +typedef union { + struct { + uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ + uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ + uint32_t reserved14: 17; + uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/ + }; + uint32_t val; +} I2C_COMMAND_t; + +typedef union { + struct { + uint32_t rx_fifo_full_thrhd: 5; + uint32_t tx_fifo_empty_thrhd:5; //Config tx_fifo empty threhd value when using apb fifo access * / + uint32_t nonfifo_en: 1; //Set this bit to enble apb nonfifo access. * / + uint32_t fifo_addr_cfg_en: 1; //When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram. * / + uint32_t rx_fifo_rst: 1; //Set this bit to reset rx fifo when using apb fifo access. * / + // chuck while this bit is 1, the RX fifo is held in REST, Toggle it * / + uint32_t tx_fifo_rst: 1; //Set this bit to reset tx fifo when using apb fifo access. * / + // chuck while this bit is 1, the TX fifo is held in REST, Toggle it * / + uint32_t nonfifo_rx_thres: 6; //when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.* / + uint32_t nonfifo_tx_thres: 6; //when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data. * / + uint32_t reserved26: 6; + }; + uint32_t val; +} I2C_FIFO_CONF_t; + +typedef union { + struct { + uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/ + uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/ + uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/ + uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } I2C_FIFO_ST_t; + +// end from tools/sdk/include/soc/soc/i2c_struct.h + +// sync between dispatch(i2cProcQueue) and worker(i2c_isr_handler_default) +typedef enum { + //I2C_NONE=0, + I2C_STARTUP=1, + I2C_RUNNING, + I2C_DONE +} I2C_STAGE_t; + +typedef enum { + I2C_NONE=0, + I2C_MASTER, + I2C_SLAVE, + I2C_MASTERSLAVE +} I2C_MODE_t; + +// internal Error condition +typedef enum { + // I2C_NONE=0, + I2C_OK=1, + I2C_ERROR, + I2C_ADDR_NAK, + I2C_DATA_NAK, + I2C_ARBITRATION, + I2C_TIMEOUT +} I2C_ERROR_t; + +// i2c_event bits for EVENTGROUP bits +// needed to minimize change events, FreeRTOS Daemon overload, so ISR will only set values +// on Exit. Dispatcher will set bits for each dq before/after ISR completion +#define EVENT_ERROR_NAK (BIT(0)) +#define EVENT_ERROR (BIT(1)) +#define EVENT_ERROR_BUS_BUSY (BIT(2)) +#define EVENT_RUNNING (BIT(3)) +#define EVENT_DONE (BIT(4)) +#define EVENT_IN_END (BIT(5)) +#define EVENT_ERROR_PREV (BIT(6)) +#define EVENT_ERROR_TIMEOUT (BIT(7)) +#define EVENT_ERROR_ARBITRATION (BIT(8)) +#define EVENT_ERROR_DATA_NAK (BIT(9)) +#define EVENT_MASK 0x3F + +// control record for each dq entry +typedef union { + struct { + uint32_t addr: 16; // I2C address, if 10bit must have 0x7800 mask applied, else 8bit + uint32_t mode: 1; // transaction direction 0 write, 1 read + uint32_t stop: 1; // sendStop 0 no, 1 yes + uint32_t startCmdSent: 1; // START cmd has been added to command[] + uint32_t addrCmdSent: 1; // addr WRITE cmd has been added to command[] + uint32_t dataCmdSent: 1; // all necessary DATA(READ/WRITE) cmds added to command[] + uint32_t stopCmdSent: 1; // completed all necessary commands + uint32_t addrReq: 2; // number of addr bytes need to send address + uint32_t addrSent: 2; // number of addr bytes added to FIFO + uint32_t reserved_31: 6; + }; + uint32_t val; +} I2C_DATA_CTRL_t; + +// individual dq element +typedef struct { + uint8_t *data; // data pointer for read/write buffer + uint16_t length; // size of data buffer + uint16_t position; // current position for next char in buffer (lock, portMAX_DELAY) != pdPASS) +#define I2C_MUTEX_UNLOCK() xSemaphoreGive(i2c->lock) + +static i2c_t _i2c_bus_array[2] = { + {(volatile i2c_dev_t *)(DR_REG_I2C_EXT_BASE_FIXED), NULL, 0, -1, -1, I2C_NONE,I2C_NONE,I2C_ERROR_OK,NULL,NULL,NULL,0,0,0,0,0,0}, + {(volatile i2c_dev_t *)(DR_REG_I2C1_EXT_BASE_FIXED), NULL, 1, -1, -1,I2C_NONE,I2C_NONE,I2C_ERROR_OK,NULL,NULL,NULL,0,0,0,0,0,0} +}; +#endif + +/* + * index - command index (0 to 15) + * op_code - is the command + * byte_num - This register is to store the amounts of data that is read and written. byte_num in RSTART, STOP, END is null. + * ack_val - Each data byte is terminated by an ACK bit used to set the bit level. + * ack_exp - This bit is to set an expected ACK value for the transmitter. + * ack_check - This bit is to decide whether the transmitter checks ACK bit. 1 means yes and 0 means no. + * */ + + +/* Stickbreaker ISR mode debug support + */ +static void IRAM_ATTR i2cDumpCmdQueue(i2c_t *i2c) +{ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR)&&(defined ENABLE_I2C_DEBUG_BUFFER) + static const char * const cmdName[] ={"RSTART","WRITE","READ","STOP","END"}; + uint8_t i=0; + while(i<16) { + I2C_COMMAND_t c; + c.val=i2c->dev->command[i].val; + i++; + } +#endif +} + +/* Stickbreaker ISR mode debug support + */ +static void i2cDumpDqData(i2c_t * i2c) +{ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER) + uint16_t a=0; + char buff[140]; + I2C_DATA_QUEUE_t *tdq; + int digits=0,lenDigits=0; + a = i2c->queueCount; + while(a>0) { + digits++; + a /= 10; + } + while(aqueueCount) { // find maximum number of len decimal digits for formatting + if (i2c->dq[a].length > lenDigits ) lenDigits = i2c->dq[a].length; + a++; + } + a=0; + while(lenDigits>0){ + a++; + lenDigits /= 10; + } + lenDigits = a; + a = 0; + while(aqueueCount) { + tdq=&i2c->dq[a]; + char buf1[10],buf2[10]; + sprintf(buf1,"%0*d",lenDigits,tdq->length); + sprintf(buf2,"%0*d",lenDigits,tdq->position); + (tdq->ctrl.addr>0x100)?"10":"7", + (tdq->ctrl.addr>0x100)?(((tdq->ctrl.addr&0x600)>>1)|(tdq->ctrl.addr&0xff)):(tdq->ctrl.addr>>1), + (tdq->ctrl.mode)?'R':'W', + (tdq->ctrl.stop)?"STOP":"", + tdq->data, + buf1,buf2, + tdq->ctrl.startCmdSent,tdq->ctrl.addrCmdSent,tdq->ctrl.dataCmdSent,(tdq->ctrl.stop)?tdq->ctrl.stopCmdSent:0,tdq->ctrl.addrSent + ); + uint16_t offset = 0; + while(offsetlength) { + memset(buff,' ',140); + buff[139]='\0'; + uint16_t i = 0,j; + j=sprintf(buff,"0x%04x: ",offset); + while((i<32)&&(offset < tdq->length)) { + char ch = tdq->data[offset]; + sprintf((char*)&buff[(i*3)+41],"%02x ",ch); + if((ch<32)||(ch>126)) { + ch='.'; + } + j+=sprintf((char*)&buff[j],"%c",ch); + buff[j]=' '; + i++; + offset++; + } + } + a++; + } +#endif +} + +static void i2cDumpI2c(i2c_t * i2c) +{ +#if !CONFIG_DISABLE_HAL_LOCKS +#endif + + if(i2c->dq) { + i2cDumpDqData(i2c); + } +} + +static void i2cDumpInts(uint8_t num) +{ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + + uint32_t b; + for(uint32_t a=1; a<=INTBUFFMAX; a++) { + b=(a+intPos[num])%INTBUFFMAX; + if(intBuff[b][0][num]!=0) { + //log_i("[%02d]\t0x%04x\t0x%04x\t0x%04x\t0x%04x\t0x%08x",b,((intBuff[b][0][num]>>16)&0xFFFF),(intBuff[b][0][num]&0xFFFF),((intBuff[b][1][num]>>16)&0xFFFF),(intBuff[b][1][num]&0xFFFF),intBuff[b][2][num]); + } + } +#else +#endif +} + +static void IRAM_ATTR i2cDumpStatus(i2c_t * i2c){ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER) + typedef union { + struct { + uint32_t ack_rec: 1; /*This register stores the value of ACK bit.*/ + uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write slave.*/ + uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/ + uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes to high level.*/ + uint32_t bus_busy: 1; /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ + uint32_t slave_addressed: 1; /*when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level.*/ + uint32_t byte_trans: 1; /*This register changes to high level when one byte is transferred.*/ + uint32_t reserved7: 1; + uint32_t rx_fifo_cnt: 6; /*This register represent the amount of data need to send.*/ + uint32_t reserved14: 4; + uint32_t tx_fifo_cnt: 6; /*This register stores the amount of received data in ram.*/ + uint32_t scl_main_state_last: 3; /*This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ + uint32_t reserved27: 1; + uint32_t scl_state_last: 3; /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } status_reg; + + status_reg sr; + sr.val= i2c->dev->status_reg.val; + +#endif +} + +static void i2cDumpFifo(i2c_t * i2c){ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER) +char buf[64]; +uint16_t k = 0; +uint16_t i = fifoPos+1; + i %=FIFOMAX; +while((fifoBuffer[i]==0)&&(i!=fifoPos)){ + i++; + i %=FIFOMAX; +} +if(i != fifoPos){// actual data + do{ + if(fifoBuffer[i] & 0x8000){ // address byte + if(fifoBuffer[i] & 0x100) { // read + if(fifoBuffer[i] & 0x1) { // valid read dev id + k+= sprintf(&buf[k],"READ 0x%02X",(fifoBuffer[i]&0xff)>>1); + } else { // invalid read dev id + k+= sprintf(&buf[k],"Bad READ 0x%02X",(fifoBuffer[i]&0xff)); + } + } else { // write + if(fifoBuffer[i] & 0x1) { // bad write dev id + k+= sprintf(&buf[k],"bad WRITE 0x%02X",(fifoBuffer[i]&0xff)); + } else { // good Write + k+= sprintf(&buf[k],"WRITE 0x%02X",(fifoBuffer[i]&0xff)>>1); + } + } + } else k += sprintf(&buf[k],"% 4X ",fifoBuffer[i]); + + i++; + i %= FIFOMAX; + bool outBuffer=false; + if( fifoBuffer[i] & 0x8000){ + outBuffer=true; + k=0; + } + outBuffer = false; + if(k>50) { + k=sprintf(buf,"-> "); + } + }while( i!= fifoPos); +} +#endif +} + +static void IRAM_ATTR i2cTriggerDumps(i2c_t * i2c, uint8_t trigger, const char locus[]){ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER) + if( trigger ){ + //log_i("%s",locus); + if(trigger & 1) i2cDumpI2c(i2c); + if(trigger & 2) i2cDumpInts(i2c->num); + if(trigger & 4) i2cDumpCmdQueue(i2c); + if(trigger & 8) i2cDumpStatus(i2c); + if(trigger & 16) i2cDumpFifo(i2c); + } +#endif +} + // end of debug support routines + +static void IRAM_ATTR i2cSetCmd(i2c_t * i2c, uint8_t index, uint8_t op_code, uint8_t byte_num, bool ack_val, bool ack_exp, bool ack_check) +{ + I2C_COMMAND_t cmd; + cmd.val=0; + cmd.ack_en = ack_check; + cmd.ack_exp = ack_exp; + cmd.ack_val = ack_val; + cmd.byte_num = byte_num; + cmd.op_code = op_code; + i2c->dev->command[index].val = cmd.val; +} + + +static void IRAM_ATTR fillCmdQueue(i2c_t * i2c, bool INTS) +{ + /* this function is called on initial i2cProcQueue() or when a I2C_END_DETECT_INT occurs + */ + uint16_t cmdIdx = 0; + uint16_t qp = i2c->queuePos; // all queues before queuePos have been completely processed, + // so look start by checking the 'current queue' so see if it needs commands added to + // hardware peripheral command list. walk through each queue entry until all queues have been + // checked + bool done; + bool needMoreCmds = false; + bool ena_rx=false; // if we add a read op, better enable Rx_Fifo IRQ + bool ena_tx=false; // if we add a Write op, better enable TX_Fifo IRQ + + while(!needMoreCmds&&(qp < i2c->queueCount)) { // check if more possible cmds + if(i2c->dq[qp].ctrl.stopCmdSent) {// marks that all required cmds[] have been added to peripheral + qp++; + } else { + needMoreCmds=true; + } + } + + done=(!needMoreCmds)||(cmdIdx>14); + + while(!done) { // fill the command[] until either 0..14 filled or out of cmds and last cmd is STOP + //CMD START + I2C_DATA_QUEUE_t *tdq=&i2c->dq[qp]; // simpler coding + + if((!tdq->ctrl.startCmdSent) && (cmdIdx < 14)) { // has this dq element's START command been added? + // (cmdIdx<14) because a START op cannot directly precede an END op, else a time out cascade occurs + i2cSetCmd(i2c, cmdIdx++, I2C_CMD_RSTART, 0, false, false, false); + tdq->ctrl.startCmdSent=1; + } + + //CMD WRITE ADDRESS + if((!done)&&(tdq->ctrl.startCmdSent)) { // have to leave room for continue(END), and START must have been sent! + if(!tdq->ctrl.addrCmdSent) { + i2cSetCmd(i2c, cmdIdx++, I2C_CMD_WRITE, tdq->ctrl.addrReq, false, false, true); //load address in cmdlist, validate (low) ack + tdq->ctrl.addrCmdSent=1; + done =(cmdIdx>14); + ena_tx=true; // tx Data necessary + } + } + + /* Can I have another Sir? + ALL CMD queues must be terminated with either END or STOP. + + If END is used, when refilling the cmd[] next time, no entries from END to [15] can be used. + AND the cmd[] must be filled starting at [0] with commands. Either fill all 15 [0]..[14] and leave the + END in [15] or include a STOP in one of the positions [0]..[14]. Any entries after a STOP are IGNORED by the StateMachine. + The END operation does not complete until ctr->trans_start=1 has been issued. + + So, only refill from [0]..[14], leave [15] for a continuation(END) if necessary. + As a corollary, once END exists in [15], you do not need to overwrite it for the + next continuation. It is never modified. But, I update it every time because it might + actually be the first time! + + 23NOV17 START cannot proceed END. if START is in[14], END cannot be in [15]. + So, if END is moved to [14], [14] and [15] can no longer be used for anything other than END. + If a START is found in [14] then a prior READ or WRITE must be expanded so that there is no START element in [14]. + */ + + if((!done)&&(tdq->ctrl.addrCmdSent)) { //room in command[] for at least One data (read/Write) cmd + uint8_t blkSize=0; // max is 255 + while(( tdq->cmdBytesNeeded > tdq->ctrl.mode )&&(!done )) { // more bytes needed and room in cmd queue, leave room for END + blkSize = (tdq->cmdBytesNeeded > 255)?255:(tdq->cmdBytesNeeded - tdq->ctrl.mode); // Last read cmd needs different ACK setting, so leave 1 byte remainder on reads + tdq->cmdBytesNeeded -= blkSize; + if(tdq->ctrl.mode==1) { //read mode + i2cSetCmd(i2c, (cmdIdx)++, I2C_CMD_READ, blkSize,false,false,false); // read cmd, this can't be the last read. + ena_rx=true; // need to enable rxFifo IRQ + } else { // write + i2cSetCmd(i2c, cmdIdx++, I2C_CMD_WRITE, blkSize, false, false, true); // check for Nak + ena_tx=true; // need to enable txFifo IRQ + } + done = cmdIdx>14; //have to leave room for END + } + + if(!done) { // buffer is not filled completely + if((tdq->ctrl.mode==1)&&(tdq->cmdBytesNeeded==1)) { //special last read byte NAK + i2cSetCmd(i2c, (cmdIdx)++, I2C_CMD_READ, 1,true,false,false); + // send NAK to mark end of read + tdq->cmdBytesNeeded=0; + done = cmdIdx > 14; + ena_rx=true; + } + } + + tdq->ctrl.dataCmdSent=(tdq->cmdBytesNeeded==0); // enough command[] to send all data + + if((!done)&&(tdq->ctrl.dataCmdSent)) { // possibly add stop + if(!tdq->ctrl.stopCmdSent){ + if(tdq->ctrl.stop) { //send a stop + i2cSetCmd(i2c, (cmdIdx)++,I2C_CMD_STOP,0,false,false,false); + done = cmdIdx > 14; + } + tdq->ctrl.stopCmdSent = 1; + } + } + } + + if((cmdIdx==14)&&(!tdq->ctrl.startCmdSent)) { + // START would have preceded END, causes SM TIMEOUT + // need to stretch out a prior WRITE or READ to two Command[] elements + done = false; // reuse it + uint16_t i = 13; // start working back until a READ/WRITE has >1 numBytes + cmdIdx =15; + while(!done) { + i2c->dev->command[i+1].val = i2c->dev->command[i].val; // push it down + if (((i2c->dev->command[i].op_code == 1)||(i2c->dev->command[i].op_code==2))) { + /* add a dummy read/write cmd[] with num_bytes set to zero,just a place holder in the cmd[]list + */ + i2c->dev->command[i].byte_num = 0; + done = true; + + } else { + if(i > 0) { + i--; + } else { // unable to stretch, fatal + i2cDumpCmdQueue(i2c); + done = true; + } + } + } + + } + + + if(cmdIdx==15) { //need continuation, even if STOP is in 14, it will not matter + // cmd buffer is almost full, Add END as a continuation feature + i2cSetCmd(i2c, (cmdIdx)++,I2C_CMD_END, 0,false,false,false); + i2c->dev->int_ena.end_detect=1; + i2c->dev->int_clr.end_detect=1; + done = true; + } + + if(!done) { + if(tdq->ctrl.stopCmdSent) { // this queue element has been completely added to command[] buffer + qp++; + if(qp < i2c->queueCount) { + tdq = &i2c->dq[qp]; + } else { + done = true; + } + } + } + + }// while(!done) + if(INTS) { // don't want to prematurely enable fifo ints until ISR is ready to handle them. + if(ena_rx) { + i2c->dev->int_ena.rx_fifo_full = 1; + } + if(ena_tx) { + i2c->dev->int_ena.tx_fifo_empty = 1; + } + } +} + +static void IRAM_ATTR fillTxFifo(i2c_t * i2c) +{ + /* + 12/01/2017 The Fifo's are independent, 32 bytes of tx and 32 bytes of Rx. + overlap is not an issue, just keep them full/empty the status_reg.xx_fifo_cnt + tells the truth. And the INT's fire correctly + */ + uint16_t a=i2c->queuePos; // currently executing dq, + bool full=!(i2c->dev->status_reg.tx_fifo_cnt<31); + uint8_t cnt; + bool rxQueueEncountered = false; + while((a < i2c->queueCount) && !full) { + I2C_DATA_QUEUE_t *tdq = &i2c->dq[a]; + cnt=0; + // add to address to fifo ctrl.addr already has R/W bit positioned correctly + if(tdq->ctrl.addrSent < tdq->ctrl.addrReq) { // need to send address bytes + if(tdq->ctrl.addrReq==2) { //10bit + if(tdq->ctrl.addrSent==0) { //10bit highbyte needs sent + if(!full) { // room in fifo + i2c->dev->fifo_data.val = ((tdq->ctrl.addr>>8)&0xFF); + cnt++; + tdq->ctrl.addrSent=1; //10bit highbyte sent + } + } + full=!(i2c->dev->status_reg.tx_fifo_cnt<31); + + if(tdq->ctrl.addrSent==1) { //10bit Lowbyte needs sent + if(!full) { // room in fifo + i2c->dev->fifo_data.val = tdq->ctrl.addr&0xFF; + cnt++; + tdq->ctrl.addrSent=2; //10bit lowbyte sent + } + } + } else { // 7bit} + if(tdq->ctrl.addrSent==0) { // 7bit Lowbyte needs sent + if(!full) { // room in fifo + i2c->dev->fifo_data.val = tdq->ctrl.addr&0xFF; + cnt++; + tdq->ctrl.addrSent=1; // 7bit lowbyte sent +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + uint16_t a = 0x8000 | tdq->ctrl.addr | (tdq->ctrl.mode<<8); + fifoBuffer[fifoPos++] = a; + fifoPos %= FIFOMAX; +#endif + } + } + } + } + // add write data to fifo + if(tdq->ctrl.mode==0) { // write + if(tdq->ctrl.addrSent == tdq->ctrl.addrReq) { //address has been sent, is Write Mode! + uint32_t moveCnt = 32 - i2c->dev->status_reg.tx_fifo_cnt; // how much room in txFifo? + while(( moveCnt>0)&&(tdq->position < tdq->length)) { +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + fifoBuffer[fifoPos++] = tdq->data[tdq->position]; + fifoPos %= FIFOMAX; +#endif + i2c->dev->fifo_data.val = tdq->data[tdq->position++]; + cnt++; + moveCnt--; + + } + } + } else { // read Queue Encountered, can't update QueuePos past this point, emptyRxfifo will do it + if( ! rxQueueEncountered ) { + rxQueueEncountered = true; + if(a > i2c->queuePos){ + i2c->queuePos = a; + } + } + } +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + + // update debug buffer tx counts + cnt += intBuff[intPos[i2c->num]][1][i2c->num]>>16; + intBuff[intPos[i2c->num]][1][i2c->num] = (intBuff[intPos[i2c->num]][1][i2c->num]&0xFFFF)|(cnt<<16); + +#endif + full=!(i2c->dev->status_reg.tx_fifo_cnt<31); + if(!full) { + a++; // check next buffer for address tx, or write data + } + } + + if(a >= i2c->queueCount ) { // disable TX IRQ, all tx Data has been queued + i2c->dev->int_ena.tx_fifo_empty= 0; + } + + i2c->dev->int_clr.tx_fifo_empty=1; +} + + +static void IRAM_ATTR emptyRxFifo(i2c_t * i2c) +{ + uint32_t d, cnt=0, moveCnt; + + moveCnt = i2c->dev->status_reg.rx_fifo_cnt;//no need to check the reg until this many are read + + while((moveCnt > 0)&&(i2c->queuePos < i2c->queueCount)){ // data to move + + I2C_DATA_QUEUE_t *tdq =&i2c->dq[i2c->queuePos]; //short cut + + while((tdq->position >= tdq->length)&&( i2c->queuePos < i2c->queueCount)){ // find were to store + i2c->queuePos++; + tdq = &i2c->dq[i2c->queuePos]; + } + + if(i2c->queuePos >= i2c->queueCount){ // bad stuff, rx data but no place to put it! + // discard + while(moveCnt>0){ + d = i2c->dev->fifo_data.val; + moveCnt--; + cnt++; + } + break; + } + + if(tdq->ctrl.mode == 1){ // read command + if(moveCnt > (tdq->length - tdq->position)) { //make sure they go in this dq + // part of these reads go into the next dq + moveCnt = (tdq->length - tdq->position); + } + } else {// error + // discard + while(moveCnt>0){ + d = i2c->dev->fifo_data.val; + moveCnt--; + cnt++; + } + break; + } + + while(moveCnt > 0) { // store data + d = i2c->dev->fifo_data.val; + moveCnt--; + cnt++; + tdq->data[tdq->position++] = (d&0xFF); + } + + moveCnt = i2c->dev->status_reg.rx_fifo_cnt; //any more out there? + } + +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&& (defined ENABLE_I2C_DEBUG_BUFFER) + // update Debug rxCount + cnt += (intBuff[intPos[i2c->num]][1][i2c->num])&0xffFF; + intBuff[intPos[i2c->num]][1][i2c->num] = (intBuff[intPos[i2c->num]][1][i2c->num]&0xFFFF0000)|cnt; +#endif +} + +static void IRAM_ATTR i2cIsrExit(i2c_t * i2c,const uint32_t eventCode,bool Fatal) +{ + + switch(eventCode) { + case EVENT_DONE: + i2c->error = I2C_OK; + break; + case EVENT_ERROR_NAK : + i2c->error =I2C_ADDR_NAK; + break; + case EVENT_ERROR_DATA_NAK : + i2c->error =I2C_DATA_NAK; + break; + case EVENT_ERROR_TIMEOUT : + i2c->error = I2C_TIMEOUT; + break; + case EVENT_ERROR_ARBITRATION: + i2c->error = I2C_ARBITRATION; + break; + default : + i2c->error = I2C_ERROR; + } + uint32_t exitCode = EVENT_DONE | eventCode |(Fatal?EVENT_ERROR:0); + if((i2c->queuePos < i2c->queueCount) && (i2c->dq[i2c->queuePos].ctrl.mode == 1)) { + emptyRxFifo(i2c); // grab last few characters + } + i2c->dev->int_ena.val = 0; // shut down interrupts + i2c->dev->int_clr.val = 0x1FFF; + i2c->stage = I2C_DONE; + i2c->exitCode = exitCode; //true eventcode + + portBASE_TYPE HPTaskAwoken = pdFALSE,xResult; + // try to notify Dispatch we are done, + // else the 50ms time out will recover the APP, just a little slower + HPTaskAwoken = pdFALSE; + xResult = xEventGroupSetBitsFromISR(i2c->i2c_event, exitCode, &HPTaskAwoken); + if(xResult == pdPASS) { + if(HPTaskAwoken==pdTRUE) { + portYIELD_FROM_ISR(); + } + } + +} + +static void IRAM_ATTR i2c_update_error_byte_cnt(i2c_t * i2c) +{ +/* i2c_update_error_byte_cnt 07/18/2018 + Only called after an error has occurred, so, most of the time this function is never used. + This function obliterates the need to interrupt monitor each byte transferred, at high bitrates + the byte interrupts were overwhelming the OS. Spurious Interrupts were being generated. + it updates errorByteCnt, errorQueue. + */ + uint16_t a=0; // start at top of DQ, count how many bytes added to tx fifo, and received from rx_fifo. + int16_t bc = 0; + I2C_DATA_QUEUE_t *tdq; + i2c->errorByteCnt = 0; + while( a < i2c->queueCount){ // add up all bytes loaded into fifo's + tdq = &i2c->dq[a]; + i2c->errorByteCnt += tdq->ctrl.addrSent; + i2c->errorByteCnt += tdq->position; + a++; + } + // now errorByteCnt contains total bytes moved into and out of FIFO's + // but, there may still be bytes waiting in Fifo's + i2c->errorByteCnt -= i2c->dev->status_reg.tx_fifo_cnt; // waiting to go out; + i2c->errorByteCnt += i2c->dev->status_reg.rx_fifo_cnt; // already received +// now walk thru DQ again, find which byte is 'current' + bc = i2c->errorByteCnt; + i2c->errorQueue = 0; + while( i2c->errorQueue < i2c->queueCount ){ + tdq = &i2c->dq[i2c->errorQueue]; + if(bc>0){ // not found yet + if( tdq->ctrl.addrSent >= bc){ // in address + bc = -1; // in address + break; + } else { + bc -= tdq->ctrl.addrSent; + if( tdq->length > bc) { // data nak + break; + } else { // count down + bc -= tdq->length; + } + } + } else break; + + i2c->errorQueue++; + } + + i2c->errorByteCnt = bc; + } + +static void IRAM_ATTR i2c_isr_handler_default(void* arg) +{ + i2c_t* p_i2c = (i2c_t*) arg; // recover data + uint32_t activeInt = p_i2c->dev->int_status.val&0x7FF; + + if(p_i2c->stage==I2C_DONE) { //get Out, can't service, not configured + p_i2c->dev->int_ena.val = 0; + p_i2c->dev->int_clr.val = 0x1FFF; +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + uint32_t raw = p_i2c->dev->int_raw.val; + //log_w("eject raw=%p, int=%p",raw,activeInt); +#endif + return; + } + while (activeInt != 0) { // Ordering of 'if(activeInt)' statements is important, don't change + + #if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + if(activeInt==(intBuff[intPos[p_i2c->num]][0][p_i2c->num]&0x1fff)) { + intBuff[intPos[p_i2c->num]][0][p_i2c->num] = (((intBuff[intPos[p_i2c->num]][0][p_i2c->num]>>16)+1)<<16)|activeInt; + } else { + intPos[p_i2c->num]++; + intPos[p_i2c->num] %= INTBUFFMAX; + intBuff[intPos[p_i2c->num]][0][p_i2c->num] = (1<<16) | activeInt; + intBuff[intPos[p_i2c->num]][1][p_i2c->num] = 0; + } + + intBuff[intPos[p_i2c->num]][2][p_i2c->num] = xTaskGetTickCountFromISR(); // when IRQ fired + +#endif + + if (activeInt & I2C_TRANS_START_INT_ST_M) { + if(p_i2c->stage==I2C_STARTUP) { + p_i2c->stage=I2C_RUNNING; + } + + activeInt &=~I2C_TRANS_START_INT_ST_M; + p_i2c->dev->int_ena.trans_start = 1; // already enabled? why Again? + p_i2c->dev->int_clr.trans_start = 1; // so that will trigger after next 'END' + } + + if (activeInt & I2C_TXFIFO_EMPTY_INT_ST) {//should this be before Trans_start? + fillTxFifo(p_i2c); //fillTxFifo will enable/disable/clear interrupt + activeInt&=~I2C_TXFIFO_EMPTY_INT_ST; + } + + if(activeInt & I2C_RXFIFO_FULL_INT_ST) { + emptyRxFifo(p_i2c); + p_i2c->dev->int_clr.rx_fifo_full=1; + p_i2c->dev->int_ena.rx_fifo_full=1; //why? + + activeInt &=~I2C_RXFIFO_FULL_INT_ST; + } + + if (activeInt & I2C_ACK_ERR_INT_ST_M) {//fatal error, abort i2c service + if (p_i2c->mode == I2C_MASTER) { + i2c_update_error_byte_cnt(p_i2c); // calc which byte caused ack Error, check if address or data + if(p_i2c->errorByteCnt < 0 ) { // address + i2cIsrExit(p_i2c,EVENT_ERROR_NAK,true); + } else { + i2cIsrExit(p_i2c,EVENT_ERROR_DATA_NAK,true); //data + } + } + return; + } + + if (activeInt & I2C_TIME_OUT_INT_ST_M) { + // let Gross timeout occur, Slave may release SCL before the configured timeout expires + // the Statemachine only has a 13.1ms max timout, some Devices >500ms + p_i2c->dev->int_clr.time_out =1; + activeInt &=~I2C_TIME_OUT_INT_ST; + // since a timeout occurred, capture the rxFifo data + emptyRxFifo(p_i2c); + p_i2c->dev->int_clr.rx_fifo_full=1; + p_i2c->dev->int_ena.rx_fifo_full=1; //why? + + } + + if (activeInt & I2C_TRANS_COMPLETE_INT_ST_M) { + p_i2c->dev->int_clr.trans_complete = 1; + i2cIsrExit(p_i2c,EVENT_DONE,false); + return; // no more work to do + /* + // how does slave mode act? + if (p_i2c->mode == I2C_SLAVE) { // STOP detected + // empty fifo + // dispatch callback + */ + } + + if (activeInt & I2C_ARBITRATION_LOST_INT_ST_M) { //fatal + i2cIsrExit(p_i2c,EVENT_ERROR_ARBITRATION,true); + return; // no more work to do + } + + if (activeInt & I2C_SLAVE_TRAN_COMP_INT_ST_M) { + p_i2c->dev->int_clr.slave_tran_comp = 1; + // need to complete this ! + } + + if (activeInt & I2C_END_DETECT_INT_ST_M) { + p_i2c->dev->int_ena.end_detect = 0; + p_i2c->dev->int_clr.end_detect = 1; + p_i2c->dev->ctr.trans_start=0; + fillCmdQueue(p_i2c,true); // enable interrupts + p_i2c->dev->ctr.trans_start=1; // go for it + activeInt&=~I2C_END_DETECT_INT_ST_M; + } + + if(activeInt) { // clear unhandled if possible? What about Disabling interrupt? + p_i2c->dev->int_clr.val = activeInt; + // disable unhandled IRQ, + p_i2c->dev->int_ena.val = p_i2c->dev->int_ena.val & (~activeInt); + } + +// activeInt = p_i2c->dev->int_status.val; // start all over if another interrupt happened +// 01AUG2018 if another interrupt happened, the OS will schedule another interrupt +// this is the source of spurious interrupts + } +} + +/* Stickbreaker added for ISR 11/2017 +functional with Silicon date=0x16042000 + */ +static i2c_err_t i2cAddQueue(i2c_t * i2c,uint8_t mode, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen,bool sendStop, bool dataOnly, EventGroupHandle_t event) +{ + // need to grab a MUTEX for exclusive Queue, + // what about if ISR is running? + + if(i2c==NULL) { + return I2C_ERROR_DEV; + } + + I2C_DATA_QUEUE_t dqx; + dqx.data = dataPtr; + dqx.length = dataLen; + dqx.position = 0; + dqx.cmdBytesNeeded = dataLen; + dqx.ctrl.val = 0; + if( dataOnly) { + /* special case to add a queue data only element. + START and devAddr will not be sent, this dq element can have a STOP. + allows multiple buffers to be used for one transaction. + sequence: normal transaction(sendStop==false), [dataonly(sendStop==false)],dataOnly(sendStop==true) + *** Currently only works with WRITE, final byte NAK an READ will cause a fail between dq buffer elements. (in progress 30JUL2018) + */ + dqx.ctrl.startCmdSent = 1; // mark as already sent + dqx.ctrl.addrCmdSent = 1; + } else { + dqx.ctrl.addrReq = ((i2cDeviceAddr&0xFC00)==0x7800)?2:1; // 10bit or 7bit address + } + dqx.ctrl.addr = i2cDeviceAddr; + dqx.ctrl.mode = mode; + dqx.ctrl.stop= sendStop; + dqx.queueEvent = event; + + if(event) { // an eventGroup exist, so, initialize it + xEventGroupClearBits(event, EVENT_MASK); // all of them + } + + if(i2c->dq!=NULL) { // expand + //log_i("expand"); + I2C_DATA_QUEUE_t* tq =(I2C_DATA_QUEUE_t*)realloc(i2c->dq,sizeof(I2C_DATA_QUEUE_t)*(i2c->queueCount +1)); + if(tq!=NULL) { // ok + i2c->dq = tq; + memmove(&i2c->dq[i2c->queueCount++],&dqx,sizeof(I2C_DATA_QUEUE_t)); + } else { // bad stuff, unable to allocate more memory! + return I2C_ERROR_MEMORY; + } + } else { // first Time + //log_i("new"); + i2c->queueCount=0; + i2c->dq =(I2C_DATA_QUEUE_t*)malloc(sizeof(I2C_DATA_QUEUE_t)); + if(i2c->dq!=NULL) { + memmove(&i2c->dq[i2c->queueCount++],&dqx,sizeof(I2C_DATA_QUEUE_t)); + } else { + return I2C_ERROR_MEMORY; + } + } + return I2C_ERROR_OK; +} + +i2c_err_t i2cAddQueueWrite(i2c_t * i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen,bool sendStop,EventGroupHandle_t event) +{ + return i2cAddQueue(i2c,0,i2cDeviceAddr,dataPtr,dataLen,sendStop,false,event); +} + +i2c_err_t i2cAddQueueRead(i2c_t * i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen,bool sendStop,EventGroupHandle_t event) +{ + //10bit read is kind of weird, first you do a 0byte Write with 10bit + // address, then a ReSTART then a 7bit Read using the the upper 7bit + + // readBit. + + // this might cause an internal register pointer problem with 10bit + // devices, But, Don't have any to test against. + // this is the Industry Standard specification. + + if((i2cDeviceAddr &0xFC00)==0x7800) { // ten bit read + i2c_err_t err = i2cAddQueue(i2c,0,i2cDeviceAddr,NULL,0,false,false,event); + if(err==I2C_ERROR_OK) { + return i2cAddQueue(i2c,1,(i2cDeviceAddr>>8),dataPtr,dataLen,sendStop,false,event); + } else { + return err; + } + } + return i2cAddQueue(i2c,1,i2cDeviceAddr,dataPtr,dataLen,sendStop,false,event); +} + +i2c_err_t i2cProcQueue(i2c_t * i2c, uint32_t *readCount, uint16_t timeOutMillis) +{ + /* do the hard stuff here + install ISR if necessary + setup EventGroup + handle bus busy? + */ + //log_e("procQueue i2c=%p",&i2c); + if(readCount){ //total reads accomplished in all queue elements + *readCount = 0; + } + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + if(i2c->debugFlags & 0xff000000) i2cTriggerDumps(i2c,(i2c->debugFlags>>24),"before ProcQueue"); + if (i2c->dev->status_reg.bus_busy) { // return error, let TwoWire() handle resetting the hardware. + /* if multi master then this if should be changed to this 03/12/2018 + if(multiMaster){// try to let the bus clear by its self + uint32_t timeOutTick = millis(); + while((i2c->dev->status_reg.bus_busy)&&(millis()-timeOutTickdev->status_reg.bus_busy){ // still busy, so die + */ + return I2C_ERROR_BUSY; + } + + I2C_MUTEX_LOCK(); + /* what about co-existence with SLAVE mode? + Should I check if a slaveMode xfer is in progress and hang + until it completes? + if i2c->stage == I2C_RUNNING or I2C_SLAVE_ACTIVE + */ + i2c->stage = I2C_DONE; // until ready + +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + for(uint16_t i=0; inum] = 0; + intBuff[i][1][i2c->num] = 0; + intBuff[i][2][i2c->num] = 0; + } + intPos[i2c->num] = 0; + fifoPos = 0; + memset(fifoBuffer,0,FIFOMAX); +#endif + // EventGroup is used to signal transmission completion from ISR + // not always reliable. Sometimes, the FreeRTOS scheduler is maxed out and refuses request + // if that happens, this call hangs until the timeout period expires, then it continues. + if(!i2c->i2c_event) { + i2c->i2c_event = xEventGroupCreate(); + } + if(i2c->i2c_event) { + xEventGroupClearBits(i2c->i2c_event, 0xFF); + } else { // failed to create EventGroup + I2C_MUTEX_UNLOCK(); + return I2C_ERROR_MEMORY; + } + + i2c_err_t reason = I2C_ERROR_OK; + i2c->mode = I2C_MASTER; + i2c->dev->ctr.trans_start=0; // Pause Machine + i2c->dev->timeout.tout = 0xFFFFF; // max 13ms + i2c->dev->int_clr.val = 0x1FFF; // kill them All! + + i2c->dev->ctr.ms_mode = 1; // master! + i2c->queuePos=0; + i2c->errorByteCnt=0; + i2c->errorQueue = 0; + uint32_t totalBytes=0; // total number of bytes to be Moved! + // convert address field to required I2C format + while(i2c->queuePos < i2c->queueCount) { // need to push these address modes upstream, to AddQueue + I2C_DATA_QUEUE_t *tdq = &i2c->dq[i2c->queuePos++]; + uint16_t taddr=0; + if(tdq->ctrl.addrReq ==2) { // 10bit address + taddr =((tdq->ctrl.addr >> 7) & 0xFE) + |tdq->ctrl.mode; + taddr = (taddr <<8) || (tdq->ctrl.addr&0xFF); + } else { // 7bit address + taddr = ((tdq->ctrl.addr<<1)&0xFE) + |tdq->ctrl.mode; + } + tdq->ctrl.addr = taddr; // all fixed with R/W bit + totalBytes += tdq->length + tdq->ctrl.addrReq; // total number of byte to be moved! + } + i2c->queuePos=0; + + fillCmdQueue(i2c,false); // don't enable Tx/RX irq's + // start adding command[], END irq will keep it full + //Data Fifo will be filled after trans_start is issued + i2c->exitCode=0; + + I2C_FIFO_CONF_t f; + f.val = i2c->dev->fifo_conf.val; + f.rx_fifo_rst = 1; // fifo in reset + f.tx_fifo_rst = 1; // fifo in reset + f.nonfifo_en = 0; // use fifo mode + f.nonfifo_tx_thres = 31; + // need to adjust threshold based on I2C clock rate, at 100k, 30 usually works, + // sometimes the emptyRx() actually moves 31 bytes + // it hasn't overflowed yet, I cannot tell if the new byte is added while + // emptyRX() is executing or before? + // let i2cSetFrequency() set thrhds + // f.rx_fifo_full_thrhd = 30; // 30 bytes before INT is issued + // f.tx_fifo_empty_thrhd = 0; + f.fifo_addr_cfg_en = 0; // no directed access + i2c->dev->fifo_conf.val = f.val; // post them all + + f.rx_fifo_rst = 0; // release fifo + f.tx_fifo_rst = 0; + i2c->dev->fifo_conf.val = f.val; // post them all + + i2c->stage = I2C_STARTUP; // everything configured, now start the I2C StateMachine, and + // As soon as interrupts are enabled, the ISR will start handling them. + // it should receive a TXFIFO_EMPTY immediately, even before it + // receives the TRANS_START + + + uint32_t interruptsEnabled = + I2C_ACK_ERR_INT_ENA | // (BIT(10)) Causes Fatal Error Exit + I2C_TRANS_START_INT_ENA | // (BIT(9)) Triggered by trans_start=1, initial,END + I2C_TIME_OUT_INT_ENA | //(BIT(8)) Trigger by SLAVE SCL stretching, NOT an ERROR + I2C_TRANS_COMPLETE_INT_ENA | // (BIT(7)) triggered by STOP, successful exit + I2C_ARBITRATION_LOST_INT_ENA | // (BIT(5)) cause fatal error exit + I2C_SLAVE_TRAN_COMP_INT_ENA | // (BIT(4)) unhandled + I2C_END_DETECT_INT_ENA | // (BIT(3)) refills cmd[] list + I2C_RXFIFO_OVF_INT_ENA | //(BIT(2)) unhandled + I2C_TXFIFO_EMPTY_INT_ENA | // (BIT(1)) triggers fillTxFifo() + I2C_RXFIFO_FULL_INT_ENA; // (BIT(0)) trigger emptyRxFifo() + + i2c->dev->int_ena.val = interruptsEnabled; + + if(!i2c->intr_handle) { // create ISR for either peripheral + // log_i("create ISR %d",i2c->num); + uint32_t ret = 0; + uint32_t flags = ESP_INTR_FLAG_IRAM | //< ISR can be called if cache is disabled + ESP_INTR_FLAG_LOWMED | //< Low and medium prio interrupts. These can be handled in C. + ESP_INTR_FLAG_SHARED; //< Reduce resource requirements, Share interrupts + + if(i2c->num) { + ret = esp_intr_alloc_intrstatus(ETS_I2C_EXT1_INTR_SOURCE, flags, (uint32_t)&i2c->dev->int_status.val, interruptsEnabled, &i2c_isr_handler_default,i2c, &i2c->intr_handle); + } else { + ret = esp_intr_alloc_intrstatus(ETS_I2C_EXT0_INTR_SOURCE, flags, (uint32_t)&i2c->dev->int_status.val, interruptsEnabled, &i2c_isr_handler_default,i2c, &i2c->intr_handle); + } + + if(ret!=ESP_OK) { + I2C_MUTEX_UNLOCK(); + return I2C_ERROR_MEMORY; + } + } + //hang until it completes. + + // how many ticks should it take to transfer totalBytes through the I2C hardware, + // add user supplied timeOutMillis to Calculated Value + + portTickType ticksTimeOut = ((totalBytes*10*1000)/(i2cGetFrequency(i2c))+timeOutMillis)/portTICK_PERIOD_MS; + + i2c->dev->ctr.trans_start=1; // go for it + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR + portTickType tBefore=xTaskGetTickCount(); +#endif + + // wait for ISR to complete the transfer, or until timeOut in case of bus fault, hardware problem + + uint32_t eBits = xEventGroupWaitBits(i2c->i2c_event,EVENT_DONE,pdFALSE,pdTRUE,ticksTimeOut); + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR + portTickType tAfter=xTaskGetTickCount(); +#endif + + + // if xEventGroupSetBitsFromISR() failed, the ISR could have succeeded but never been + // able to mark the success + + if(i2c->exitCode!=eBits) { // try to recover from O/S failure + // log_e("EventGroup Failed:%p!=%p",eBits,i2c->exitCode); + eBits=i2c->exitCode; + } + if((eBits&EVENT_ERROR)||(!(eBits & EVENT_DONE))){ // need accurate errorByteCnt for debug + i2c_update_error_byte_cnt(i2c); + } + + if(!(eBits==EVENT_DONE)&&(eBits&~(EVENT_ERROR_NAK|EVENT_ERROR_DATA_NAK|EVENT_ERROR|EVENT_DONE))) { // not only Done, therefore error, exclude ADDR NAK, DATA_NAK +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO + i2cDumpI2c(i2c); + i2cDumpInts(i2c->num); +#endif + } + + if(eBits&EVENT_DONE) { // no gross timeout + switch(i2c->error) { + case I2C_OK : + reason = I2C_ERROR_OK; + break; + case I2C_ERROR : + reason = I2C_ERROR_DEV; + break; + case I2C_ADDR_NAK: + reason = I2C_ERROR_ACK; + break; + case I2C_DATA_NAK: + reason = I2C_ERROR_ACK; + break; + case I2C_ARBITRATION: + reason = I2C_ERROR_BUS; + break; + case I2C_TIMEOUT: + reason = I2C_ERROR_TIMEOUT; + break; + default : + reason = I2C_ERROR_DEV; + } + } else { // GROSS timeout, shutdown ISR , report Timeout + i2c->stage = I2C_DONE; + i2c->dev->int_ena.val =0; + i2c->dev->int_clr.val = 0x1FFF; + i2c_update_error_byte_cnt(i2c); + if((i2c->errorByteCnt == 0)&&(i2c->errorQueue==0)) { // Bus Busy no bytes Moved + reason = I2C_ERROR_BUSY; + eBits = eBits | EVENT_ERROR_BUS_BUSY|EVENT_ERROR|EVENT_DONE; +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + //log_d(" Busy Timeout start=0x%x, end=0x%x, =%d, max=%d error=%d",tBefore,tAfter,(tAfter-tBefore),ticksTimeOut,i2c->error); + i2cDumpI2c(i2c); + i2cDumpInts(i2c->num); +#endif + } else { // just a timeout, some data made it out or in. + reason = I2C_ERROR_TIMEOUT; + eBits = eBits | EVENT_ERROR_TIMEOUT|EVENT_ERROR|EVENT_DONE; + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + //log_d(" Gross Timeout Dead start=0x%x, end=0x%x, =%d, max=%d error=%d",tBefore,tAfter,(tAfter-tBefore),ticksTimeOut,i2c->error); + i2cDumpI2c(i2c); + i2cDumpInts(i2c->num); +#endif + } + } + + /* offloading all EventGroups to dispatch, EventGroups in ISR is not always successful + 11/20/2017 + if error, need to trigger all succeeding dataQueue events with the EVENT_ERROR_PREV + 07/22/2018 + Need to use the queueEvent value to identify transaction blocks, if an error occurs, + all subsequent queue items with the same queueEvent value will receive the EVENT_ERROR_PREV. + But, ProcQue should re-queue queue items that have a different queueEvent value(different transaction) + This change will support multi-thread i2c usage. Use the queueEvent as the transaction event + identifier. + */ + uint32_t b = 0; + + while(b < i2c->queueCount) { + if(i2c->dq[b].ctrl.mode==1 && readCount) { + *readCount += i2c->dq[b].position; // number of data bytes received + } + if(b < i2c->queuePos) { // before any error + if(i2c->dq[b].queueEvent) { // this data queue element has an EventGroup + xEventGroupSetBits(i2c->dq[b].queueEvent,EVENT_DONE); + } + } else if(b == i2c->queuePos) { // last processed queue + if(i2c->dq[b].queueEvent) { // this data queue element has an EventGroup + xEventGroupSetBits(i2c->dq[b].queueEvent,eBits); + } + } else { // never processed queues + if(i2c->dq[b].queueEvent) { // this data queue element has an EventGroup + xEventGroupSetBits(i2c->dq[b].queueEvent,eBits|EVENT_ERROR_PREV); + } + } + b++; + } + if(i2c->debugFlags & 0x00ff0000) i2cTriggerDumps(i2c,(i2c->debugFlags>>16),"after ProcQueue"); + + I2C_MUTEX_UNLOCK(); + return reason; +} + +static void i2cReleaseISR(i2c_t * i2c) +{ + if(i2c->intr_handle) { + esp_intr_free(i2c->intr_handle); + i2c->intr_handle=NULL; + } +} + +static bool i2cCheckLineState(int8_t sda, int8_t scl){ + if(sda < 0 || scl < 0){ + return false;//return false since there is nothing to do + } + // if the bus is not 'clear' try the cycling SCL until SDA goes High or 9 cycles + digitalWrite(sda, HIGH); + digitalWrite(scl, HIGH); + pinMode(sda, PULLUP|OPEN_DRAIN|INPUT); + pinMode(scl, PULLUP|OPEN_DRAIN|OUTPUT); + + if(!digitalRead(sda) || !digitalRead(scl)) { // bus in busy state + //log_w("invalid state sda(%d)=%d, scl(%d)=%d", sda, digitalRead(sda), scl, digitalRead(scl)); + digitalWrite(scl, HIGH); + for(uint8_t a=0; a<9; a++) { + delayMicroseconds(5); + digitalWrite(scl, LOW); + delayMicroseconds(5); + digitalWrite(scl, HIGH); + if(digitalRead(sda)){ // bus recovered + //log_d("Recovered after %d Cycles",a+1); + break; + } + } + } + + if(!digitalRead(sda) || !digitalRead(scl)) { // bus in busy state + return false; // bus is busy + } + return true; +} + +i2c_err_t i2cAttachSCL(i2c_t * i2c, int8_t scl) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + digitalWrite(scl, HIGH); + pinMode(scl, OPEN_DRAIN | PULLUP | INPUT | OUTPUT); + pinMatrixOutAttach(scl, I2C_SCL_IDX(i2c->num), false, false); + pinMatrixInAttach(scl, I2C_SCL_IDX(i2c->num), false); + return I2C_ERROR_OK; +} + +i2c_err_t i2cDetachSCL(i2c_t * i2c, int8_t scl) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + pinMatrixOutDetach(scl, false, false); + pinMatrixInDetach(I2C_SCL_IDX(i2c->num), false, false); + pinMode(scl, INPUT | PULLUP); + return I2C_ERROR_OK; +} + +i2c_err_t i2cAttachSDA(i2c_t * i2c, int8_t sda) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + digitalWrite(sda, HIGH); + pinMode(sda, OPEN_DRAIN | PULLUP | INPUT | OUTPUT ); + pinMatrixOutAttach(sda, I2C_SDA_IDX(i2c->num), false, false); + pinMatrixInAttach(sda, I2C_SDA_IDX(i2c->num), false); + return I2C_ERROR_OK; +} + +i2c_err_t i2cDetachSDA(i2c_t * i2c, int8_t sda) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + pinMatrixOutDetach(sda, false, false); + pinMatrixInDetach(I2C_SDA_IDX(i2c->num), false, false); + pinMode(sda, INPUT | PULLUP); + return I2C_ERROR_OK; +} + +/* + * PUBLIC API + * */ +// 24Nov17 only supports Master Mode +i2c_t * i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t frequency) //before this is called, pins should be detached, else glitch +{ + //log_v("num=%d sda=%d scl=%d freq=%d",i2c_num, sda, scl, frequency); + if(i2c_num > 1) { + return NULL; + } + + i2c_t * i2c = &_i2c_bus_array[i2c_num]; + + if(i2c->sda >= 0){ + i2cDetachSDA(i2c, i2c->sda); + } + if(i2c->scl >= 0){ + i2cDetachSCL(i2c, i2c->scl); + } + i2c->sda = sda; + i2c->scl = scl; + +#if !CONFIG_DISABLE_HAL_LOCKS + if(i2c->lock == NULL) { + i2c->lock = xSemaphoreCreateMutex(); + if(i2c->lock == NULL) { + return NULL; + } + } +#endif + I2C_MUTEX_LOCK(); + + i2cReleaseISR(i2c); // ISR exists, release it before disabling hardware + + if(frequency == 0) {// don't change existing frequency + frequency = i2cGetFrequency(i2c); + if(frequency == 0) { + frequency = 100000L; // default to 100khz + } + } + + if(i2c_num == 0) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST); //reset hardware + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT0_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST);// release reset + } else { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST); //reset Hardware + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT1_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST); + } + i2c->dev->ctr.val = 0; + i2c->dev->ctr.ms_mode = 1; + i2c->dev->ctr.sda_force_out = 1 ; + i2c->dev->ctr.scl_force_out = 1 ; + i2c->dev->ctr.clk_en = 1; + + //the max clock number of receiving a data + i2c->dev->timeout.tout = 400000;//clocks max=1048575 + //disable apb nonfifo access + i2c->dev->fifo_conf.nonfifo_en = 0; + + i2c->dev->slave_addr.val = 0; + I2C_MUTEX_UNLOCK(); + + i2cSetFrequency(i2c, frequency); // reconfigure + + if(!i2cCheckLineState(i2c->sda, i2c->scl)){ + return NULL; + } + + if(i2c->sda >= 0){ + i2cAttachSDA(i2c, i2c->sda); + } + if(i2c->scl >= 0){ + i2cAttachSCL(i2c, i2c->scl); + } + return i2c; +} + +void i2cRelease(i2c_t *i2c) // release all resources, power down peripheral +{ + I2C_MUTEX_LOCK(); + + if(i2c->sda >= 0){ + i2cDetachSDA(i2c, i2c->sda); + } + if(i2c->scl >= 0){ + i2cDetachSCL(i2c, i2c->scl); + } + + i2cReleaseISR(i2c); + + if(i2c->i2c_event) { + vEventGroupDelete(i2c->i2c_event); + i2c->i2c_event = NULL; + } + + i2cFlush(i2c); + + // reset the I2C hardware and shut off the clock, power it down. + if(i2c->num == 0) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST); //reset hardware + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT0_CLK_EN); // shutdown hardware + } else { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST); //reset Hardware + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT1_CLK_EN); // shutdown Hardware + } + + I2C_MUTEX_UNLOCK(); +} + +i2c_err_t i2cFlush(i2c_t * i2c) +{ + if(i2c==NULL) { + return I2C_ERROR_DEV; + } + i2cTriggerDumps(i2c,i2c->debugFlags & 0xff, "FLUSH"); + + // need to grab a MUTEX for exclusive Queue, + // what out if ISR is running? + i2c_err_t rc=I2C_ERROR_OK; + if(i2c->dq!=NULL) { + // log_i("free"); + // what about EventHandle? + free(i2c->dq); + i2c->dq = NULL; + } + i2c->queueCount=0; + i2c->queuePos=0; + // release Mutex + return rc; +} + +i2c_err_t i2cWrite(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis){ + i2c_err_t last_error = i2cAddQueueWrite(i2c, address, buff, size, sendStop, NULL); + + if(last_error == I2C_ERROR_OK) { //queued + if(sendStop) { //now actually process the queued commands, including READs + last_error = i2cProcQueue(i2c, NULL, timeOutMillis); + if(last_error == I2C_ERROR_BUSY) { // try to clear the bus + if(i2cInit(i2c->num, i2c->sda, i2c->scl, 0)) { + last_error = i2cProcQueue(i2c, NULL, timeOutMillis); + } + } + i2cFlush(i2c); + } else { // stop not received, so wait for I2C stop, + last_error = I2C_ERROR_CONTINUE; + } + } + return last_error; +} + +i2c_err_t i2cRead(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis, uint32_t *readCount){ + i2c_err_t last_error=i2cAddQueueRead(i2c, address, buff, size, sendStop, NULL); + + if(last_error == I2C_ERROR_OK) { //queued + if(sendStop) { //now actually process the queued commands, including READs + last_error = i2cProcQueue(i2c, readCount, timeOutMillis); + if(last_error == I2C_ERROR_BUSY) { // try to clear the bus + if(i2cInit(i2c->num, i2c->sda, i2c->scl, 0)) { + last_error = i2cProcQueue(i2c, readCount, timeOutMillis); + } + } + i2cFlush(i2c); + } else { // stop not received, so wait for I2C stop, + last_error = I2C_ERROR_CONTINUE; + } + } + return last_error; +} + +i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + I2C_FIFO_CONF_t f; + + uint32_t period = (APB_CLK_FREQ/clk_speed) / 2; + uint32_t halfPeriod = period/2; + uint32_t quarterPeriod = period/4; + + I2C_MUTEX_LOCK(); + + // Adjust Fifo thresholds based on frequency + f.val = i2c->dev->fifo_conf.val; + uint32_t a = (clk_speed / 50000L )+1; + if (a > 24) a=24; + f.rx_fifo_full_thrhd = 32 - a; + f.tx_fifo_empty_thrhd = a; + i2c->dev->fifo_conf.val = f.val; // set thresholds + //log_v("Fifo threshold=%d",a); + + //the clock num during SCL is low level + i2c->dev->scl_low_period.period = period; + //the clock num during SCL is high level + i2c->dev->scl_high_period.period = period; + + //the clock num between the negedge of SDA and negedge of SCL for start mark + i2c->dev->scl_start_hold.time = halfPeriod; + //the clock num between the posedge of SCL and the negedge of SDA for restart mark + i2c->dev->scl_rstart_setup.time = halfPeriod; + + //the clock num after the STOP bit's posedge + i2c->dev->scl_stop_hold.time = halfPeriod; + //the clock num between the posedge of SCL and the posedge of SDA + i2c->dev->scl_stop_setup.time = halfPeriod; + + //the clock num I2C used to hold the data after the negedge of SCL. + i2c->dev->sda_hold.time = quarterPeriod; + //the clock num I2C used to sample data on SDA after the posedge of SCL + i2c->dev->sda_sample.time = quarterPeriod; + I2C_MUTEX_UNLOCK(); + return I2C_ERROR_OK; +} + +uint32_t i2cGetFrequency(i2c_t * i2c) +{ + if(i2c == NULL) { + return 0; + } + uint32_t result = 0; + uint32_t old_count = (i2c->dev->scl_low_period.period+i2c->dev->scl_high_period.period); + if(old_count>0) { + result = APB_CLK_FREQ / old_count; + } else { + result = 0; + } + return result; +} + + +uint32_t i2cDebug(i2c_t * i2c, uint32_t setBits, uint32_t resetBits){ + if(i2c != NULL) { + i2c->debugFlags = ((i2c->debugFlags | setBits) & ~resetBits); + return i2c->debugFlags; + } + return 0; + + } + +uint32_t i2cGetStatus(i2c_t * i2c){ + if(i2c != NULL){ + return i2c->dev->status_reg.val; + } + else return 0; +} +/* todo + 22JUL18 + need to add multi-thread capability, use dq.queueEvent as the group marker. When multiple threads + transactions are present in the same queue, and an error occurs, abort all succeeding unserviced transactions + with the same dq.queueEvent value. Succeeding unserviced transactions with different dq.queueEvent values + can be re-queued and processed independently. + 30JUL18 complete data only queue elements, this will allow transfers to use multiple data blocks, + */ + diff --git a/MCUME_esp32/espcastaway/components/Wire/esp32-hal-i2c.h b/MCUME_esp32/espcastaway/components/Wire/esp32-hal-i2c.h new file mode 100644 index 0000000..1a696ac --- /dev/null +++ b/MCUME_esp32/espcastaway/components/Wire/esp32-hal-i2c.h @@ -0,0 +1,82 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// modified Nov 2017 by Chuck Todd to support Interrupt Driven I/O + +#ifndef _ESP32_HAL_I2C_H_ +#define _ESP32_HAL_I2C_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/event_groups.h" + +// External Wire.h equivalent error Codes +typedef enum { + I2C_ERROR_OK=0, + I2C_ERROR_DEV, + I2C_ERROR_ACK, + I2C_ERROR_TIMEOUT, + I2C_ERROR_BUS, + I2C_ERROR_BUSY, + I2C_ERROR_MEMORY, + I2C_ERROR_CONTINUE, + I2C_ERROR_NO_BEGIN +} i2c_err_t; + +struct i2c_struct_t; +typedef struct i2c_struct_t i2c_t; + +i2c_t * i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t clk_speed); +void i2cRelease(i2c_t *i2c); // free ISR, Free DQ, Power off peripheral clock. Must call i2cInit() to recover +i2c_err_t i2cWrite(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis); +i2c_err_t i2cRead(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis, uint32_t *readCount); +i2c_err_t i2cFlush(i2c_t *i2c); +i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed); +uint32_t i2cGetFrequency(i2c_t * i2c); +uint32_t i2cGetStatus(i2c_t * i2c); // Status register of peripheral + +//Functions below should be used only if well understood +//Might be deprecated and removed in future +i2c_err_t i2cAttachSCL(i2c_t * i2c, int8_t scl); +i2c_err_t i2cDetachSCL(i2c_t * i2c, int8_t scl); +i2c_err_t i2cAttachSDA(i2c_t * i2c, int8_t sda); +i2c_err_t i2cDetachSDA(i2c_t * i2c, int8_t sda); + +//Stickbreakers ISR Support +i2c_err_t i2cProcQueue(i2c_t *i2c, uint32_t *readCount, uint16_t timeOutMillis); +i2c_err_t i2cAddQueueWrite(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen, bool SendStop, EventGroupHandle_t event); +i2c_err_t i2cAddQueueRead(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen, bool SendStop, EventGroupHandle_t event); + +//stickbreaker debug support +uint32_t i2cDebug(i2c_t *, uint32_t setBits, uint32_t resetBits); +// Debug actions have 3 currently defined locus +// 0xXX------ : at entry of ProcQueue +// 0x--XX---- : at exit of ProcQueue +// 0x------XX : at entry of Flush +// +// bit 0 causes DumpI2c to execute +// bit 1 causes DumpInts to execute +// bit 2 causes DumpCmdqueue to execute +// bit 3 causes DumpStatus to execute +// bit 4 causes DumpFifo to execute + +#ifdef __cplusplus +} +#endif + +#endif /* _ESP32_HAL_I2C_H_ */ diff --git a/MCUME_esp32/espcastaway/components/Wire/esp32-hal-matrix.c b/MCUME_esp32/espcastaway/components/Wire/esp32-hal-matrix.c new file mode 100644 index 0000000..93e8849 --- /dev/null +++ b/MCUME_esp32/espcastaway/components/Wire/esp32-hal-matrix.c @@ -0,0 +1,52 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include +#include +#include "esp32-hal-matrix.h" +#include "esp_attr.h" +#include "rom/gpio.h" + + + +#define MATRIX_DETACH_OUT_SIG 0x100 +#define MATRIX_DETACH_IN_LOW_PIN 0x30 +#define MATRIX_DETACH_IN_LOW_HIGH 0x38 + +void IRAM_ATTR pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable) +{ + gpio_matrix_out(pin, function, invertOut, invertEnable); +} + +void IRAM_ATTR pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable) +{ + gpio_matrix_out(pin, MATRIX_DETACH_OUT_SIG, invertOut, invertEnable); +} + +void IRAM_ATTR pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted) +{ + gpio_matrix_in(pin, signal, inverted); +} + +void IRAM_ATTR pinMatrixInDetach(uint8_t signal, bool high, bool inverted) +{ + gpio_matrix_in(high?MATRIX_DETACH_IN_LOW_HIGH:MATRIX_DETACH_IN_LOW_PIN, signal, inverted); +} +/* +void IRAM_ATTR intrMatrixAttach(uint32_t source, uint32_t inum){ + intr_matrix_set(PRO_CPU_NUM, source, inum); +} +*/ + diff --git a/MCUME_esp32/espcastaway/components/Wire/esp32-hal-matrix.h b/MCUME_esp32/espcastaway/components/Wire/esp32-hal-matrix.h new file mode 100644 index 0000000..7feefea --- /dev/null +++ b/MCUME_esp32/espcastaway/components/Wire/esp32-hal-matrix.h @@ -0,0 +1,35 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP32_HAL_MATRIX_H_ +#define _ESP32_HAL_MATRIX_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + +//#include "esp32-hal.h" +//#include "soc/gpio_sig_map.h" + +void pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable); +void pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable); +void pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted); +void pinMatrixInDetach(uint8_t signal, bool high, bool inverted); + +#ifdef __cplusplus +} +#endif + +#endif /* COMPONENTS_ARDUHAL_INCLUDE_ESP32_HAL_MATRIX_H_ */ diff --git a/MCUME_esp32/espcastaway/flashapp.sh b/MCUME_esp32/espcastaway/flashapp.sh new file mode 100755 index 0000000..9548e1f --- /dev/null +++ b/MCUME_esp32/espcastaway/flashapp.sh @@ -0,0 +1,3 @@ +#!/bin/bash +. ${IDF_PATH}/add_path.sh +esptool.py --chip esp32 --port "/dev/cu.SLAB_USBtoUART" --baud $((230400*4)) write_flash -fs 4MB 0x10000 ../espcastaway/build/espcastaway.bin diff --git a/MCUME_esp32/espcastaway/main/.DS_Store b/MCUME_esp32/espcastaway/main/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..dfa9a0bcbcbf07f7bb264ed93ddfdfdf40a51d1a GIT binary patch literal 6148 zcmeHK!A`*L310AGJoe_9i}Bcy8b5#^P^nfUw1^UJ$@(kl+b*WSqG^Pj2{3;WySH@E1`|0u1n#zi?P`QZ_P}x$qbPT$IYiU4Dkhjz{ z|4d#*(+1u`*>+w~--HT!rW`p3&Y*7;)ED5b==+#WRbP-->D$T+=#xP$?SKP3s}RjY zkCx2=bHE&^9N_gKLSu{-OOLX2AjuH`*g&@guK6s%HIZVhSbD@0g!839U+VOT;e0vz zBjv@4rAJ>*P7fbW-|X~+;^gfZKN32**rR20z#Le2VBg=idH=uIeEwfAvO9CY9Qaob zxJJ@Ty7(mBTWcT3du@bvg~q|W(xa3h>2@p^ycM6IN#I$;7rJI3-HfgP literal 0 HcmV?d00001 diff --git a/MCUME_esp32/espcastaway/main/68kfame/.DS_Store b/MCUME_esp32/espcastaway/main/68kfame/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..5008ddfcf53c02e82d7eee2e57c38e5672ef89f6 GIT binary patch literal 6148 zcmeH~Jr2S!425mzP>H1@V-^m;4Wg<&0T*E43hX&L&p$$qDprKhvt+--jT7}7np#A3 zem<@ulZcFPQ@L2!n>{z**++&mCkOWA81W14cNZlEfg7;MkzE(HCqgga^y>{tEnwC%0;vJ&^%eQ zLs35+`xjp>T0= 8) return disass_areg(spec & 0x7); + else return disass_dreg(spec); +} + +static void disass_reglist(char *buf, unsigned short reglist, int predecrement) +{ + int index = 0, len; + *buf = 0; + if (!predecrement) { + while (reglist) { + if (reglist & 0x1) { + strcat(buf, disass_reg(index)); + strcat(buf, "/"); + } + index++; + reglist = reglist >> 1; + } + } else { + while (reglist) { + if (reglist & 0x8000) { + strcat(buf, disass_reg(index)); + strcat(buf, "/"); + } + index++; + reglist = reglist << 1; + } + } + /* remove trailing / */ + len = strlen(buf); + if (len > 0) *(buf + len - 1) = 0; +} + +static int disass_count(unsigned char spec) +{ + if (spec == 0) return 8; + else return spec; +} + +/* +* return # of extension words used for addressing +*/ +static int disass_displacement(char *buf, unsigned short *inst_stream, char displacement) +{ + if (displacement == 0) { + sprintf(buf, "%04x", inst_stream[1]); + return 1; + } else if (displacement == -1) { + sprintf(buf, "%04x%04x", inst_stream[1], inst_stream[2]); + return 2; + } else { + sprintf(buf, "%02x", displacement); + return 0; + } +} + +/* +* return # of extension words used for addressing +*/ +static int disass_ea(char *buf, unsigned short *inst_stream, unsigned char mode, unsigned char spec, unsigned char size) +{ + switch(mode) { + case 0: + strcpy(buf, disass_dreg(spec)); + return 0; + case 1: + strcpy(buf, disass_areg(spec)); + return 0; + case 2: + sprintf(buf, "(%s)", disass_areg(spec)); + return 0; + case 3: + sprintf(buf, "(%s)+", disass_areg(spec)); + return 0; + case 4: + sprintf(buf, "-(%s)", disass_areg(spec)); + return 0; + case 5: + sprintf(buf, "%04x(%s)", inst_stream[1], disass_areg(spec)); + return 1; + case 6: // TODO: 680x0 full extension format + sprintf(buf, "(%02x(%s,%s.%c*%x)", + (char) inst_stream[1], disass_areg(spec), + disass_reg(inst_stream[1] >> 12), + (inst_stream[1] & 0x0800)?'L':'W', + 1 << ((inst_stream[1] & 0x0600) >> 9)); + return 1; + case 7: + switch(spec) { + case 0: + sprintf(buf, "%04x", inst_stream[1]); + return 1; + case 1: + sprintf(buf, "%04x%04x", inst_stream[1], inst_stream[2]); + return 2; + case 2: + sprintf(buf, "%04x(PC)", inst_stream[1]); + return 1; + case 3: // TODO: 680x0 full extension format + sprintf(buf, "(%02x(PC,%s.%c*%x)", + (char) inst_stream[1], + disass_reg(inst_stream[1] >> 12), + (inst_stream[1] & 0x0800)?'L':'W', + 1 << ((inst_stream[1] & 0x0600) >> 9)); + return 1; + case 4: + switch(size) { + case 0: + case 1: + sprintf(buf, "#%04x", inst_stream[1]); + return 1; + case 2: + sprintf(buf, "#%04x%04x", inst_stream[1], inst_stream[2]); + return 2; + case 3: + sprintf(buf, "???"); + return 0; + } + } + } + sprintf (buf, "???"); + return 0; +} + +void disassemble68k(char *buf, unsigned short *inst_stream) +{ + char src_ea_buf[80]; + char tgt_ea_buf[80]; + unsigned char src_mode = (inst_stream[0] & 0x0038) >> 3; + unsigned char src_spec = (inst_stream[0] & 0x0007); + unsigned char src_size = (inst_stream[0] & 0x00c0) >> 6; + unsigned char tgt_mode = (inst_stream[0] & 0x01c0) >> 6; + unsigned char tgt_spec = (inst_stream[0] & 0x0e00) >> 9; + unsigned char condition = (inst_stream[0] & 0x0f00) >> 8; + int wc; + switch (inst_stream[0] & 0xf000) { + case 0x0000: + // TODO: CAS2, CAS + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0]) { + case 0x003c: + sprintf(buf, "ORI.B #%02x,CCR", (char) inst_stream[1]); + return; + case 0x007c: + sprintf(buf, "ORI.W #%04x,SR", inst_stream[1]); + return; + case 0x013c: + sprintf(buf, "ANDI.B #%02x,CCR", (char) inst_stream[1]); + return; + case 0x017c: + sprintf(buf, "ANDI.W #%04x,SR", inst_stream[1]); + return; + case 0x0a3c: + sprintf(buf, "EORI.B #%02x,CCR", (char) inst_stream[1]); + return; + case 0x0a7c: + sprintf(buf, "EORI.W #%04x,SR", inst_stream[1]); + return; + } + switch (inst_stream[0] & 0x0fc0) { + case 0x0000: + sprintf(buf, "ORI.B #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0040: + sprintf(buf, "ORI.W #%04x,%s", inst_stream[1], src_ea_buf); + return; + case 0x0080: + sprintf(buf, "ORI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf); + return; + case 0x0200: + sprintf(buf, "ANDI.B #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0240: + sprintf(buf, "ANDI.W #%04x,%s", inst_stream[1], src_ea_buf); + return; + case 0x0280: + sprintf(buf, "ANDI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf); + return; + case 0x0400: + sprintf(buf, "SUBI.B #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0440: + sprintf(buf, "SUBI.W #%04x,%s", inst_stream[1], src_ea_buf); + return; + case 0x0480: + sprintf(buf, "SUBI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf); + return; + case 0x0600: + sprintf(buf, "ADDI.B #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0640: + sprintf(buf, "ADDI.W #%04x,%s", inst_stream[1], src_ea_buf); + return; + case 0x0680: + sprintf(buf, "ADDI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf); + return; + case 0x0800: + sprintf(buf, "BTST #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0840: + sprintf(buf, "BCHG #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0880: + sprintf(buf, "BCLR #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x08c0: + sprintf(buf, "BSET #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0a00: + sprintf(buf, "EORI.B #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0a40: + sprintf(buf, "EORI.W #%04x,%s", inst_stream[1], src_ea_buf); + return; + case 0x0a80: + sprintf(buf, "EORI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf); + return; + case 0x0c00: + sprintf(buf, "CMPI.B #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0c40: + sprintf(buf, "CMPI.W #%04x,%s", inst_stream[1], src_ea_buf); + return; + case 0x0c80: + sprintf(buf, "CMPI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf); + return; + case 0x0e00: + switch (inst_stream[1] & 0x0800) { + case 0x0000: sprintf(buf, "MOVES.B %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + case 0x0800: sprintf(buf, "MOVES.B %s,%s", disass_reg((inst_stream[1] >> 12) & 0xf), src_ea_buf); + return; + } + case 0x0e40: + switch (inst_stream[1] & 0x0800) { + case 0x0000: sprintf(buf, "MOVES.W %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + case 0x0800: sprintf(buf, "MOVES.W %s,%s", disass_reg((inst_stream[1] >> 12) & 0xf), src_ea_buf); + return; + } + case 0x0e80: + switch (inst_stream[1] & 0x0800) { + case 0x0000: sprintf(buf, "MOVES.L %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + case 0x0800: sprintf(buf, "MOVES.L %s,%s", disass_reg((inst_stream[1] >> 12) & 0xf), src_ea_buf); + return; + } + case 0x06c0: + switch (inst_stream[0] & 0x0030) { + case 0x0000: sprintf(buf, "RTM %s", disass_reg(inst_stream[0] & 0xf)); + return; + case 0x0030: sprintf(buf, "CALLM %s", src_ea_buf); + return; + } + case 0x00c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 0); + switch (inst_stream[1] & 0x0800) { + case 0x0000: sprintf(buf, "CMP2.B %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + case 0x0800: sprintf(buf, "CHK2.B %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + } + case 0x02c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + switch (inst_stream[1] & 0x0800) { + case 0x0000: sprintf(buf, "CMP2.W %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + case 0x0800: sprintf(buf, "CHK2.W %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + } + case 0x04c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2); + switch (inst_stream[1] & 0x0800) { + case 0x0000: sprintf(buf, "CMP2.L %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + case 0x0800: sprintf(buf, "CHK2.L %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + } + } + if (inst_stream[0] & 0x0100) { + if (src_mode == 1) { + switch (tgt_mode) { + case 0x0100: sprintf(buf, "MOVEP.W #%04x(%s),%s", inst_stream[1], disass_areg(src_spec), disass_dreg(tgt_spec)); + return; + case 0x0140: sprintf(buf, "MOVEP.L #%04x(%s),%s", inst_stream[1], disass_areg(src_spec), disass_dreg(tgt_spec)); + return; + case 0x0180: sprintf(buf, "MOVEP.W %s,#%04x(%s)", disass_dreg(tgt_spec), inst_stream[1], disass_areg(src_spec)); + return; + case 0x01c0: sprintf(buf, "MOVEP.L %s,#%04x(%s)", disass_dreg(tgt_spec), inst_stream[1], disass_areg(src_spec)); + return; + } + } + switch (inst_stream[0] & 0x0030) { + case 0x0000: sprintf(buf, "BTST %s,%s", disass_dreg(tgt_spec), src_ea_buf); + return; + case 0x0010: sprintf(buf, "BCHG %s,%s", disass_dreg(tgt_spec), src_ea_buf); + return; + case 0x0020: sprintf(buf, "BCLR %s,%s", disass_dreg(tgt_spec), src_ea_buf); + return; + case 0x0030: sprintf(buf, "BSET %s,%s", disass_dreg(tgt_spec), src_ea_buf); + return; + } + } + case 0x1000: /* Move Byte */ + wc = disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 0); + disass_ea(tgt_ea_buf, inst_stream + wc, tgt_mode, tgt_spec, 0); + sprintf(buf, "MOVE.B %s,%s", src_ea_buf, tgt_ea_buf); + return; + case 0x2000: /* Move Long */ + wc = disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2); + disass_ea(tgt_ea_buf, inst_stream + wc, tgt_mode, tgt_spec, 2); + sprintf(buf, "MOVE.L %s,%s", src_ea_buf, tgt_ea_buf); + return; + case 0x3000: /* Move Word */ + wc = disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + disass_ea(tgt_ea_buf, inst_stream + wc, tgt_mode, tgt_spec, 1); + sprintf(buf, "MOVE.W %s,%s", src_ea_buf, tgt_ea_buf); + return; + case 0x4000: /* Miscellaneous */ + // TODO: MULU.L, MULS.L, DIVU.L, DIVS.L, EXTB.L + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0xffc0) { + case 0x4000: + sprintf(buf, "NEGX.B %s", src_ea_buf); + return; + case 0x4040: + sprintf(buf, "NEGX.W %s", src_ea_buf); + return; + case 0x4080: + sprintf(buf, "NEGX.L %s", src_ea_buf); + return; + case 0x40c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "MOVE.W SR,%s", src_ea_buf); + return; + case 0x4200: + sprintf(buf, "CLR.B %s", src_ea_buf); + return; + case 0x4240: + sprintf(buf, "CLR.W %s", src_ea_buf); + return; + case 0x4280: + sprintf(buf, "CLR.L %s", src_ea_buf); + return; + case 0x42c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "MOVE.W CCR,%s", src_ea_buf); + return; + case 0x4400: + sprintf(buf, "NEG.B %s", src_ea_buf); + return; + case 0x4440: + sprintf(buf, "NEG.W %s", src_ea_buf); + return; + case 0x4480: + sprintf(buf, "NEG.L %s", src_ea_buf); + return; + case 0x44c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "MOVE.W %s,CCR", src_ea_buf); + return; + case 0x4600: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "NOT.B %s", src_ea_buf); + return; + case 0x4640: + sprintf(buf, "NOT.W %s", src_ea_buf); + return; + case 0x4680: + sprintf(buf, "NOT.L %s", src_ea_buf); + return; + case 0x46c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "MOVE.W %s,SR", src_ea_buf); + return; + case 0x4800: + if (src_mode == 1) { + sprintf(buf, "LINK.L #%04x%04x,%s", + inst_stream[1], inst_stream[2], disass_areg(src_spec)); + } else { + sprintf(buf, "NBCD %s", src_ea_buf); + } + return; + case 0x4840: + if (src_mode == 0) { + sprintf(buf, "SWAP.W %s", disass_dreg(src_spec)); + } else if (src_mode == 1) { + sprintf(buf, "BKPT #%x", src_spec); + } else { + sprintf(buf, "PEA %s", src_ea_buf); + } + return; + case 0x4880: + if (src_mode == 0) { + sprintf(buf, "EXT.W %s", disass_dreg(src_spec)); + } else { + disass_reglist(tgt_ea_buf, inst_stream[1], src_mode == 6); + disass_ea(src_ea_buf, inst_stream + 1, src_mode, src_spec, src_size); + sprintf(buf, "MOVEM.W %s,%s", tgt_ea_buf, src_ea_buf); + } + return; + case 0x48c0: + if (src_mode == 0) { + sprintf(buf, "EXT.L %s", disass_dreg(src_spec)); + } else { + disass_reglist(tgt_ea_buf, inst_stream[1], src_mode == 6); + disass_ea(src_ea_buf, inst_stream + 1, src_mode, src_spec, src_size); + sprintf(buf, "MOVEM.L %s,%s", tgt_ea_buf, src_ea_buf); + } + return; + case 0x4a00: + sprintf(buf, "TST.B %s", src_ea_buf); + return; + case 0x4a40: + sprintf(buf, "TST.W %s", src_ea_buf); + return; + case 0x4a80: + sprintf(buf, "TST.L %s", src_ea_buf); + return; + case 0x4ac0: + switch (inst_stream[0] & 0x003f) { + case 0x003a: + sprintf(buf, "BGND "); + return; + case 0x003c: + sprintf(buf, "ILLEGAL"); + return; + default: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 0); + sprintf(buf, "TAS %s", src_ea_buf); + return; + } + case 0x4c80: + if (src_mode == 0) { + } else { + disass_reglist(tgt_ea_buf, inst_stream[1], src_mode == 6); + disass_ea(src_ea_buf, inst_stream + 1, src_mode, src_spec, src_size); + sprintf(buf, "MOVEM.W %s,%s", src_ea_buf, tgt_ea_buf); + } + return; + case 0x4cc0: + if (src_mode == 0) { + } else { + disass_reglist(tgt_ea_buf, inst_stream[1], src_mode == 6); + disass_ea(src_ea_buf, inst_stream + 1, src_mode, src_spec, 2); + sprintf(buf, "MOVEM.L %s,%s", src_ea_buf, tgt_ea_buf); + } + return; + case 0x4e40: + switch(src_mode) { + case 0: + case 1: + sprintf(buf, "TRAP #%x", inst_stream[0] & 0xf); + return; + case 2: + sprintf(buf, "LINK #%4x,%s", inst_stream[1], disass_areg(src_spec)); + return; + case 3: + sprintf(buf, "UNLK %s", disass_areg(src_spec)); + return; + case 4: + sprintf(buf, "MOVE.L %s,USP", disass_areg(src_spec)); + return; + case 5: + sprintf(buf, "MOVE.L USP,%s", disass_areg(src_spec)); + return; + case 6: + switch(inst_stream[0]) { + case 0x4e70: + sprintf(buf, "RESET "); + return; + case 0x4e71: + sprintf(buf, "NOP "); + return; + case 0x4e72: + sprintf(buf, "STOP "); + return; + case 0x4e73: + sprintf(buf, "RTE "); + return; + case 0x4e74: + sprintf(buf, "RTD "); + return; + case 0x4e75: + sprintf(buf, "RTS "); + return; + case 0x4e76: + sprintf(buf, "TRAPV "); + return; + case 0x4e77: + sprintf(buf, "RTR "); + return; + } + case 7: + switch(inst_stream[0]) { + case 0x4e7a: + sprintf(buf, "MOVEC #%04x,%s", inst_stream[1] & 0xfff, disass_reg(inst_stream[1] >> 12)); + return; + case 0x4e7b: + sprintf(buf, "MOVEC #%s,%04x", disass_reg(inst_stream[1] >> 12), inst_stream[1] & 0xfff); + return; + } + } + sprintf(buf, "??? "); + return; + case 0x4e80: + sprintf(buf, "JSR %s", src_ea_buf); + return; + case 0x4ec0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2); + sprintf(buf, "JMP %s", src_ea_buf); + return; + } + switch (tgt_mode) { + case 4: + sprintf(buf, "CHK.L %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 6: + sprintf(buf, "CHK.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 7: + sprintf(buf, "LEA %s,%s", src_ea_buf, disass_areg(tgt_spec)); + return; + } + case 0x5000: /* ADDQ/SUBQ/Scc/DBcc/TRAPcc */ + // TODO: TRAPcc + wc = disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0x00c0) { + case 0x0000: + if (inst_stream[0] & 0x0100) { + sprintf(buf, "SUBQ.B #%x,%s", disass_count(tgt_spec), src_ea_buf); + } else { + sprintf(buf, "ADDQ.B #%x,%s", disass_count(tgt_spec), src_ea_buf); + } + return; + case 0x0040: + if (inst_stream[0] & 0x0100) { + sprintf(buf, "SUBQ.W #%x,%s", disass_count(tgt_spec), src_ea_buf); + } else { + sprintf(buf, "ADDQ.W #%x,%s", disass_count(tgt_spec), src_ea_buf); + } + return; + case 0x0080: + if (inst_stream[0] & 0x0100) { + sprintf(buf, "SUBQ.L #%x,%s", disass_count(tgt_spec), src_ea_buf); + } else { + sprintf(buf, "ADDQ.L #%x,%s", disass_count(tgt_spec), src_ea_buf); + } + return; + case 0x00c0: + if (src_mode == 1) { + disass_displacement(tgt_ea_buf, inst_stream + wc, 0); + sprintf(buf, "DB%s %s,%s", disass_cc(condition), tgt_ea_buf, disass_dreg(src_spec)); + } else { + sprintf(buf, "S%s %s", disass_cc(condition), src_ea_buf); + } + return; + } + case 0x6000: /* Bcc/BSR/BRA */ + disass_displacement(tgt_ea_buf, inst_stream, inst_stream[0]); + if ((inst_stream[0] & 0xff00) == 0x6000) { + sprintf(buf, "BRA %s", tgt_ea_buf); + } else if ((inst_stream[0] & 0xff00) == 0x6100) { + sprintf(buf, "BSR %s", tgt_ea_buf); + } else { + sprintf(buf, "B%s %s",disass_cc(condition), tgt_ea_buf); + } + return; + case 0x7000: /* MOVEQ */ + sprintf(buf, "MOVEQ.L #%02x,%s", (char) inst_stream[0], disass_dreg(tgt_spec)); + return; + case 0x8000: /* OR/DIV/SBCD */ + // TODO: PACK, UNPK + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0x01c0) { + case 0x0000: + sprintf(buf, "OR.B %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0040: + sprintf(buf, "OR.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0080: + sprintf(buf, "OR.L %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x00c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "DIVU.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0100: + if (src_mode == 0) { + sprintf(buf, "SBCD %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "SBCD -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "OR.B %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0140: + sprintf(buf, "OR.W %s,%s", disass_reg(tgt_spec), src_ea_buf); + return; + case 0x0180: + sprintf(buf, "OR.L %s,%s", disass_reg(tgt_spec), src_ea_buf); + return; + case 0x01c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "DIVS.W %s,%s", src_ea_buf, disass_reg(tgt_spec)); + return; + } + case 0x9000: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0x01c0) { + case 0x0000: + sprintf(buf, "SUB.B %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0040: + sprintf(buf, "SUB.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0080: + sprintf(buf, "SUB.L %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x00c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "SUBA.W %s,%s", src_ea_buf, disass_areg(tgt_spec)); + return; + case 0x0100: + if (src_mode == 0) { + sprintf(buf, "SUBX.B %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "SUBX.B -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "SUB.B %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0140: + if (src_mode == 0) { + sprintf(buf, "SUBX.W %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "SUBX.W -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "SUB.W %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0180: + if (src_mode == 0) { + sprintf(buf, "SUBX.L %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "SUBX.L -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "SUB.L %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x01c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2); + sprintf(buf, "SUBA.L %s,%s", src_ea_buf, disass_areg(tgt_spec)); + return; + } + case 0xb000: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0x01c0) { + case 0x0000: + sprintf(buf, "CMP.B %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0040: + sprintf(buf, "CMP.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0080: + sprintf(buf, "CMP.L %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x00c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "CMPA.W %s,%s", src_ea_buf, disass_areg(tgt_spec)); + return; + case 0x0100: + if (src_mode == 1) { + sprintf(buf, "CMPM.B (%s)+,(%s)+", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "EOR.B %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0140: + if (src_mode == 1) { + sprintf(buf, "CMPM.W (%s)+,(%s)+", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "EOR.W %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0180: + if (src_mode == 1) { + sprintf(buf, "CMPM.L (%s)+,(%s)+", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "EOR.L %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x01c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2); + sprintf(buf, "CMPA.L %s,%s", src_ea_buf, disass_areg(tgt_spec)); + return; + } + case 0xc000: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0x01c0) { + case 0x0000: + sprintf(buf, "AND.B %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0040: + sprintf(buf, "AND.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0080: + sprintf(buf, "AND.L %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x00c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "MULU.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0100: + if (src_mode == 0) { + sprintf(buf, "ABCD %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "ABCD -(%s),-(%s)", disass_areg(src_spec), disass_reg(tgt_spec)); + } else { + sprintf(buf, "AND.B %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0140: + if (src_mode == 0) { + sprintf(buf, "EXG %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "EXG %s,%s", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "AND.W %s,%s", disass_reg(tgt_spec), src_ea_buf); + } + return; + case 0x0180: + if (src_mode == 1) { + sprintf(buf, "EXG %s,%s", disass_dreg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "AND.L %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x01c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "MULS.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + } + case 0xd000: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0x01c0) { + case 0x0000: + sprintf(buf, "ADD.B %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0040: + sprintf(buf, "ADD.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0080: + sprintf(buf, "ADD.L %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x00c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "ADDA.W %s,%s", src_ea_buf, disass_areg(tgt_spec)); + return; + case 0x0100: + if (src_mode == 0) { + sprintf(buf, "ADDX.B %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 0x0008) { + sprintf(buf, "ADDX.B -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "ADD.B %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0140: + if (src_mode == 0) { + sprintf(buf, "ADDX.W %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "ADDX.W -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "ADD.W %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0180: + if (src_mode == 0) { + sprintf(buf, "ADDX.L %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "ADDX.L -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "ADD.L %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x01c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2); + sprintf(buf, "ADDA.L %s,%s", src_ea_buf, disass_areg(tgt_spec)); + return; + } + case 0xe000: + // TODO: BFTST, BFEXTU, BFCHG, BFEXTS, BFCLR, BFFFO, BFSET, BFINS + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0x07c0) { + case 0x00c0: + sprintf(buf, "ASR.B #1,%s", src_ea_buf); + return; + case 0x01c0: + sprintf(buf, "ASL.B #1,%s", src_ea_buf); + return; + case 0x02c0: + sprintf(buf, "LSR.B #1,%s", src_ea_buf); + return; + case 0x03c0: + sprintf(buf, "LSL.B #1,%s", src_ea_buf); + return; + case 0x04c0: + sprintf(buf, "ROXR.B #1,%s", src_ea_buf); + return; + case 0x05c0: + sprintf(buf, "ROXL.B #1,%s", src_ea_buf); + return; + case 0x06c0: + sprintf(buf, "ROR.B #1,%s", src_ea_buf); + return; + case 0x07c0: + sprintf(buf, "ROL.B #1,%s", src_ea_buf); + return; + } + switch (inst_stream[0] & 0x01f8) { + case 0x0000: + sprintf(buf, "ASR.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0008: + sprintf(buf, "LSR.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0010: + sprintf(buf, "ROXR.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0018: + sprintf(buf, "ROR.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0020: + sprintf(buf, "ASR.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0028: + sprintf(buf, "LSR.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0030: + sprintf(buf, "ROXR.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0038: + sprintf(buf, "ROR.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0040: + sprintf(buf, "ASR.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0048: + sprintf(buf, "LSR.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0050: + sprintf(buf, "ROXR.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0058: + sprintf(buf, "ROR.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0060: + sprintf(buf, "ASR.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0068: + sprintf(buf, "LSR.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0070: + sprintf(buf, "ROXR.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0078: + sprintf(buf, "ROR.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0080: + sprintf(buf, "ASR.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0088: + sprintf(buf, "LSR.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0090: + sprintf(buf, "ROXR.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0098: + sprintf(buf, "ROR.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x00a0: + sprintf(buf, "ASR.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x00a8: + sprintf(buf, "LSR.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x00b0: + sprintf(buf, "ROXR.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x00b8: + sprintf(buf, "ROR.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0100: + sprintf(buf, "ASL.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0108: + sprintf(buf, "LSL.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0110: + sprintf(buf, "ROXL.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0118: + sprintf(buf, "ROL.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0120: + sprintf(buf, "ASL.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0128: + sprintf(buf, "LSL.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0130: + sprintf(buf, "ROXL.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0138: + sprintf(buf, "ROL.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0140: + sprintf(buf, "ASL.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0148: + sprintf(buf, "LSL.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0150: + sprintf(buf, "ROXL.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0158: + sprintf(buf, "ROL.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0160: + sprintf(buf, "ASL.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0168: + sprintf(buf, "LSL.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0170: + sprintf(buf, "ROXL.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0178: + sprintf(buf, "ROL.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0180: + sprintf(buf, "ASL.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0188: + sprintf(buf, "LSL.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0190: + sprintf(buf, "ROXL.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0198: + sprintf(buf, "ROL.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x01a0: + sprintf(buf, "ASL.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x01a8: + sprintf(buf, "LSL.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x01b0: + sprintf(buf, "ROXL.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x01b8: + sprintf(buf, "ROL.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + } + } +} + + diff --git a/MCUME_esp32/espcastaway/main/68kfame/fame.h b/MCUME_esp32/espcastaway/main/68kfame/fame.h new file mode 100644 index 0000000..849b520 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68kfame/fame.h @@ -0,0 +1,190 @@ +/******************************************************************************/ +/* FAME Fast and Accurate Motorola 68000 Emulation Core */ +/* (c) 2002 Oscar Orallo Pelaez / Daniel Lancha Garcia */ +/* Version: 2.1 */ +/* Date: 11-26-2006 */ +/* See FAME.HTML for documentation and license information */ +/******************************************************************************/ + +#ifndef __FAME_H__ +#define __FAME_H__ + +#if defined(__cplusplus) && !defined(USE_FAME_CORE_C) +extern "C" { +#endif + +/************************************/ +/* General library defines */ +/************************************/ + +#ifndef M68K_OK + #define M68K_OK 0 +#endif + +#ifndef M68K_RUNNING + #define M68K_RUNNING 1 +#endif + +#ifndef M68K_NO_SUP_ADDR_SPACE + #define M68K_NO_SUP_ADDR_SPACE 2 +#endif + +#ifndef M68K_INV_REG + #define M68K_INV_REG -1 +#endif + +/* Hardware interrupt state */ + +#ifndef M68K_IRQ_LEVEL_ERROR + #define M68K_IRQ_LEVEL_ERROR -1 +#endif + +#ifndef M68K_IRQ_INV_PARAMS + #define M68K_IRQ_INV_PARAMS -2 +#endif + +/* Defines to specify hardware interrupt type */ + +#ifndef M68K_AUTOVECTORED_IRQ + #define M68K_AUTOVECTORED_IRQ -1 +#endif + +#ifndef M68K_SPURIOUS_IRQ + #define M68K_SPURIOUS_IRQ -2 +#endif + +/* Defines to specify address space */ + +#ifndef M68K_SUP_ADDR_SPACE + #define M68K_SUP_ADDR_SPACE 0 +#endif + +#ifndef M68K_USER_ADDR_SPACE + #define M68K_USER_ADDR_SPACE 2 +#endif + +#ifndef M68K_PROG_ADDR_SPACE + #define M68K_PROG_ADDR_SPACE 0 +#endif + +#ifndef M68K_DATA_ADDR_SPACE + #define M68K_DATA_ADDR_SPACE 1 +#endif + + +/*******************/ +/* Data definition */ +/*******************/ + +/* M68K registers */ +typedef enum +{ + M68K_REG_D0=0, + M68K_REG_D1, + M68K_REG_D2, + M68K_REG_D3, + M68K_REG_D4, + M68K_REG_D5, + M68K_REG_D6, + M68K_REG_D7, + M68K_REG_A0, + M68K_REG_A1, + M68K_REG_A2, + M68K_REG_A3, + M68K_REG_A4, + M68K_REG_A5, + M68K_REG_A6, + M68K_REG_A7, + M68K_REG_ASP, + M68K_REG_PC, + M68K_REG_SR +} m68k_register; + +/* The memory blocks must be in native (Motorola) format */ +typedef struct +{ + unsigned low_addr; + unsigned high_addr; + unsigned offset; +} M68K_PROGRAM; + +/* The memory blocks must be in native (Motorola) format */ +typedef struct +{ + unsigned low_addr; + unsigned high_addr; + void *mem_handler; + void *data; +} M68K_DATA; + +/* M68K CPU CONTEXT */ +typedef struct +{ + M68K_PROGRAM *fetch; + M68K_DATA *read_byte; + M68K_DATA *read_word; + M68K_DATA *write_byte; + M68K_DATA *write_word; + M68K_PROGRAM *sv_fetch; + M68K_DATA *sv_read_byte; + M68K_DATA *sv_read_word; + M68K_DATA *sv_write_byte; + M68K_DATA *sv_write_word; + M68K_PROGRAM *user_fetch; + M68K_DATA *user_read_byte; + M68K_DATA *user_read_word; + M68K_DATA *user_write_byte; + M68K_DATA *user_write_word; + void (*reset_handler)(void); + void (*iack_handler)(unsigned level); + unsigned * icust_handler; + unsigned dreg[8]; + unsigned areg[8]; + unsigned asp; + unsigned pc; + unsigned cycles_counter; + unsigned char interrupts[8]; + unsigned short sr; + unsigned short execinfo; +} M68K_CONTEXT; + + +/************************/ +/* Function definition */ +/************************/ + +/* General purpose functions */ +void m68k_init(void); +unsigned m68k_reset(void); +void m68k_emulate(int n); +unsigned m68k_get_pc(void); +unsigned m68k_get_cpu_state(void); +int m68k_fetch(unsigned address, unsigned memory_space); + +/* Interrupt handling functions */ +int m68k_raise_irq(int level, int vector); +int m68k_lower_irq(int level); +int m68k_get_irq_vector(int level); +int m68k_change_irq_vector(int level, int vector); + +/* CPU context handling functions */ +int m68k_get_context_size(void); +void m68k_get_context(void *context); +void m68k_set_context(void *context); +int m68k_get_register(m68k_register reg); +int m68k_set_register(m68k_register reg, unsigned value); + +/* Timing functions */ +unsigned m68k_get_cycles_counter(void); +unsigned m68k_trip_cycles_counter(void); +unsigned m68k_control_cycles_counter(int n); +void m68k_release_timeslice(void); +void m68k_stop_emulating(void); +void m68k_add_cycles(int cycles); +void m68k_release_cycles(int cycles); + +#if defined(__cplusplus) && !defined(USE_FAME_CORE_C) +} +#endif + +#endif diff --git a/MCUME_esp32/espcastaway/main/68kfame/famec.cpp b/MCUME_esp32/espcastaway/main/68kfame/famec.cpp new file mode 100644 index 0000000..ee7f7fe --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68kfame/famec.cpp @@ -0,0 +1,6052 @@ +/****************************************************************************/ +/* FAME (Fast and Accurate Motorola 68000 Emulation Library) */ +/* Emulador de 68000 en C */ +/* Autor: Oscar Orallo Pelaez */ +/* Fecha de comienzo: 03-10-2006 */ +/* Ultima actualizacion: 28-10-2009 */ +/* Based on the excellent FAMEC emulator by Stephane Dallongueville */ +/****************************************************************************/ + +#include +#include +#include +#include + +#ifdef _MSC_VER +/* Ignore unary minus applied to unsigned type */ +#pragma warning( disable : 4146 ) +#endif + +/* Options */ +/* + Do not use the following lines to enable/disable features + They are here as a reference only + Define them in your project as you need instead +*/ +/* #define FAME_INLINE_LOOP */ +/* #define FAME_IRQ_CLOCKING */ +/* #define FAME_CHECK_BRANCHES */ +/* #define FAME_DIRECT_MAPPING */ +/* #define FAME_EXTRA_INLINE */ +/* #define FAME_EMULATE_TRACE */ +/* #define FAME_BYPASS_TAS_WRITEBACK */ +/* #define FAME_ACCURATE_TIMING */ +/* #define FAME_GLOBAL_CONTEXT */ +/* #define FAME_DEBUG */ +/* #define FAME_GOTOS */ +/* #define FAME_BIG_ENDIAN */ + +#define FAME_SECURE_ALL_BANKS + +#ifndef FAME_ADDR_BITS +#define FAME_ADDR_BITS 24 +#endif + +#ifndef FAME_PC_BITS +#define FAME_PC_BITS 24 +#endif + +#ifndef FAME_FETCHBITS +#define FAME_FETCHBITS 12 +#endif + +#ifndef FAME_DATABITS +#define FAME_DATABITS 12 +#endif + +#ifndef FAME_PREFIX +#define FAME_PREFIX m68k +#endif + +/* Options */ + +#define CONCAT(P1,P2) P1##P2 +#define FAME_FNT(P,F) CONCAT(P,_##F) +#define FAME_DT(P,D) CONCAT(P,D) +#define FAME_API(F) FAME_FNT(FAME_PREFIX,F) +#define FAME_CONTEXT FAME_DT(FAME_PREFIX,context) + + +#ifndef INLINE +#define INLINE +#endif + +#ifndef FAME_EXTRA_INLINE +#define EXTRA_INLINE +#else +#define EXTRA_INLINE INLINE +#endif + +/* Return codes */ +#define M68K_OK 0 +#define M68K_RUNNING 1 +#define M68K_NO_SUP_ADDR_SPACE 2 +#define M68K_INV_REG -1 + +/* Hardware interrupt state */ +#define M68K_IRQ_LEVEL_ERROR -1 +#define M68K_IRQ_INV_PARAMS -2 + +/* Defines to specify hardware interrupt type */ +#define M68K_AUTOVECTORED_IRQ -1 +#define M68K_SPURIOUS_IRQ -2 + +/* Defines to specify address space */ +#define M68K_SUP_ADDR_SPACE 0 +#define M68K_USER_ADDR_SPACE 2 +#define M68K_PROG_ADDR_SPACE 0 +#define M68K_DATA_ADDR_SPACE 1 + +/******************************/ +/* 68K core types definitions */ +/******************************/ + +#if FAME_ADDR_BITS < 32 +#define M68K_ADDR_MASK ((1 << FAME_ADDR_BITS)-1) +#else +#define M68K_ADDR_MASK 0xFFFFFFFF +#endif + +#define M68K_FETCHSFT (FAME_ADDR_BITS - FAME_FETCHBITS) +#define M68K_FETCHBANK (1 << FAME_FETCHBITS) +#define M68K_FETCHMASK (M68K_FETCHBANK - 1) + +#define M68K_DATASFT (FAME_ADDR_BITS - FAME_DATABITS) +#define M68K_DATABANK (1 << FAME_DATABITS) +#define M68K_DATAMASK (M68K_DATABANK - 1) + +#define M68K_SR_C_SFT 8 +#define M68K_SR_V_SFT 7 +#define M68K_SR_Z_SFT 0 +#define M68K_SR_N_SFT 7 +#define M68K_SR_X_SFT 8 + +#define M68K_SR_S_SFT 13 +#define M68K_SR_T_SFT 15 + +#define M68K_SR_C (1 << M68K_SR_C_SFT) +#define M68K_SR_V (1 << M68K_SR_V_SFT) +#define M68K_SR_Z 0 +#define M68K_SR_N (1 << M68K_SR_N_SFT) +#define M68K_SR_X (1 << M68K_SR_X_SFT) + +#define M68K_SR_S (1 << M68K_SR_S_SFT) +#define M68K_SR_T (1 << M68K_SR_T_SFT) + +#define M68K_CCR_MASK 0x1F + +#ifdef FAME_IRQ_CLOCKING +#define INT_TIMING 44 +#else +#define INT_TIMING 0 +#endif + +#ifdef FAME_EMULATE_TRACE +#define M68K_SR_MASK (M68K_SR_T | M68K_SR_S | 0x0700 | M68K_CCR_MASK) +#else +#define M68K_SR_MASK (M68K_SR_S | 0x0700 | M68K_CCR_MASK) +#endif + +/* exception defines taken from musashi core */ +#define M68K_RESET_EX 1 +#define M68K_BUS_ERROR_EX 2 +#define M68K_ADDRESS_ERROR_EX 3 +#define M68K_ILLEGAL_INSTRUCTION_EX 4 +#define M68K_ZERO_DIVIDE_EX 5 +#define M68K_CHK_EX 6 +#define M68K_TRAPV_EX 7 +#define M68K_PRIVILEGE_VIOLATION_EX 8 +#define M68K_TRACE_EX 9 +#define M68K_1010_EX 10 +#define M68K_1111_EX 11 +#define M68K_FORMAT_ERROR_EX 14 +#define M68K_UNINITIALIZED_INTERRUPT_EX 15 +#define M68K_SPURIOUS_INTERRUPT_EX 24 +#define M68K_INTERRUPT_AUTOVECTOR_EX 24 +#define M68K_TRAP_BASE_EX 32 + +#define M68K_INT_ACK_AUTOVECTOR -1 + +/*#define M68K_RUNNING 0x01 */ +#define M68K_HALTED 0x80 +#define M68K_WAITING 0x04 +#define M68K_DISABLE 0x20 +/* #define M68K_FAULTED 0x40 */ +#define M68K_EMULATE_GROUP_0 0x02 +#define M68K_EMULATE_TRACE 0x08 +#define M68K_DO_TRACE 0x10 + +#ifdef FAME_LITTLE_ENDIAN +#ifdef FAME_BIG_ENDIAN +#undef FAME_BIG_ENDIAN +#endif +#else +#ifndef FAME_BIG_ENDIAN +#if defined(__hppa__) || \ + defined(__m68k__) || defined(mc68000) || defined(_M_M68K) || \ + (defined(__MIPS__) && defined(__MISPEB__)) || \ + defined(__ppc__) || defined(__POWERPC__) || defined(_M_PPC) || \ + defined(__sparc__) +#define FAME_BIG_ENDIAN +#else +#define FAME_LITTLE_ENDIAN +#endif +#endif +#endif + + +/* + internals core macros +*/ + +#define DREG(X) (FAME_CONTEXT.dreg[(X)].D) +#define DREGu32(X) (FAME_CONTEXT.dreg[(X)].D) +#define DREGs32(X) (FAME_CONTEXT.dreg[(X)].SD) +#define DREGu16(X) (FAME_CONTEXT.dreg[(X)].w.W) +#define DREGs16(X) (FAME_CONTEXT.dreg[(X)].sw.SW) +#define DREGu8(X) (FAME_CONTEXT.dreg[(X)].b.B) +#define DREGs8(X) (FAME_CONTEXT.dreg[(X)].sb.SB) + +#define AREG(X) (FAME_CONTEXT.areg[(X)].D) +#define AREGu32(X) (FAME_CONTEXT.areg[(X)].D) +#define AREGs32(X) (FAME_CONTEXT.areg[(X)].SD) +#define AREGu16(X) (FAME_CONTEXT.areg[(X)].w.W) +#define AREGs16(X) (FAME_CONTEXT.areg[(X)].sw.SW) + +#define ASP (FAME_CONTEXT.asp) + +#define LSL(A, C) ((A) << (C)) +#define LSR(A, C) ((A) >> (C)) + +#define LSR_32(A, C) ((C) < 32 ? (A) >> (C) : 0) +#define LSL_32(A, C) ((C) < 32 ? (A) << (C) : 0) + +#define ROL_8(A, C) (LSL(A, C) | LSR(A, 8-(C))) +#define ROL_9(A, C) (LSL(A, C) | LSR(A, 9-(C))) +#define ROL_16(A, C) (LSL(A, C) | LSR(A, 16-(C))) +#define ROL_17(A, C) (LSL(A, C) | LSR(A, 17-(C))) +#define ROL_32(A, C) (LSL_32(A, C) | LSR_32(A, 32-(C))) +#define ROL_33(A, C) (LSL_32(A, C) | LSR_32(A, 33-(C))) + +#define ROR_8(A, C) (LSR(A, C) | LSL(A, 8-(C))) +#define ROR_9(A, C) (LSR(A, C) | LSL(A, 9-(C))) +#define ROR_16(A, C) (LSR(A, C) | LSL(A, 16-(C))) +#define ROR_17(A, C) (LSR(A, C) | LSL(A, 17-(C))) +#define ROR_32(A, C) (LSR_32(A, C) | LSL_32(A, 32-(C))) +#define ROR_33(A, C) (LSR_32(A, C) | LSL_32(A, 33-(C))) + +/* Flag setup */ +#define SET_FLAGS_Z_VC0 \ + flag_C = 0; \ + flag_V = 0; \ + flag_NotZ = res; + +#define SET_FLAGS_NZ_VC0 \ + SET_FLAGS_Z_VC0 \ + flag_N = res; + +#define SET_FLAGS_DIV_ZERO \ + flag_V = 0; \ + flag_C = 0; + +#define SET_FLAGS_DIV_OVERFLOW \ + flag_C = 0; \ + flag_V = M68K_SR_V; \ + flag_N = M68K_SR_N; \ + /* Z flag is undefined on division overflow */ \ + /* but is set here to match FAME versions */ \ + flag_NotZ = 1; \ + + +#ifdef FAME_DEBUG +#define DEBUG_OPCODE(OP) printf(":Opcode %.4X\n",Opcode); +#else +#define DEBUG_OPCODE(OP) +#endif + +#ifdef FAME_GOTOS +#define NEXT \ + FETCH_WORD(Opcode); \ + DEBUG_OPCODE(Opcode) \ + goto *JumpTable[Opcode]; + +#ifdef FAME_INLINE_LOOP +#define RET(A) \ + io_cycle_counter -= (A); \ + if (io_cycle_counter <= 0) goto famec_Exec_End; \ + NEXT +#else +#define RET(A) \ + io_cycle_counter -= (A); \ + if (io_cycle_counter <= 0) goto famec_Exec_End; \ + goto famec_Exec; +#endif + +#define RET_STOP(C) \ + io_cycle_counter -= (C); \ + if (io_cycle_counter > 0) io_cycle_counter = 0; \ + goto famec_Exec_End; + +#else +//printf("%8x",PC); +//printf("=>%8x\n",Opcode); + +#define NEXT \ + do { \ + FETCH_WORD(Opcode); \ + DEBUG_OPCODE(Opcode) \ + JumpTable[Opcode](); \ + } while(io_cycle_counter>0); + +#ifdef FAME_INLINE_LOOP +#define RET(A) \ + io_cycle_counter -= (A); \ + if (io_cycle_counter > 0) \ + { \ + FETCH_WORD(Opcode); \ + DEBUG_OPCODE(Opcode) \ + JumpTable[Opcode](); \ + } \ + return; + +#else + +#define RET(A) \ + io_cycle_counter -= (A); \ + return; + +#endif + +#define RET_STOP(C) \ + io_cycle_counter -= (C); \ + if (io_cycle_counter > 0) io_cycle_counter = 0; \ + return; + +#endif + +#define M68K_PPL (FAME_CONTEXT.sr >> 8) & 7 + +#if FAME_PC_BITS == 32 + +#define UNBASED_PC PC + +#define READ_BASED_PC BasePC[(PC & M68K_ADDR_MASK) >> 1] + +#define READ_BASED_PC_IDX(IDX) BasePC[((PC & M68K_ADDR_MASK) >> 1) + IDX] + +#define SET_PC(A) \ + BasePC = (u16 *)Fetch[(((A) & M68K_ADDR_MASK) >> M68K_FETCHSFT) & M68K_FETCHMASK]; \ + PC = A; + +#define INC_PC(I) (PC += I) + +#else + +#define UNBASED_PC ((u32)PC - BasePC) + +#define READ_BASED_PC (*PC) + +#define READ_BASED_PC_IDX(IDX) PC[IDX] + +#define SET_PC(A) \ + BasePC = Fetch[((A) >> M68K_FETCHSFT) & M68K_FETCHMASK]; \ + PC = (u16*)(((A) & M68K_ADDR_MASK) + BasePC); + +#define INC_PC(I) (PC += (I) >> 1) + +#endif + +#define READ_BYTE_F(A, D) \ + D = Read_Byte(A) & 0xFF; + +#define READ_WORD_F(A, D) \ + D = Read_Word(A) & 0xFFFF; + +#define READ_LONG_F(A, D) \ + D = Read_Word((A)) << 16; \ + D |= Read_Word((A) + 2) & 0xFFFF; + +#define READ_LONG_DEC_F(A, D) \ + D = Read_Word((A) + 2) & 0xFFFF; \ + D |= Read_Word((A)) << 16; + +#define READSX_LONG_F(A, D) \ + D = Read_Word((A)) << 16; \ + D |= Read_Word((A) + 2) & 0xFFFF; + +#define WRITE_LONG_F(A, D) \ + Write_Word((A), (D) >> 16); \ + Write_Word((A) + 2, (D) & 0xFFFF); + +#define WRITE_LONG_DEC_F(A, D) \ + Write_Word((A) + 2, (D) & 0xFFFF); \ + Write_Word((A), (D) >> 16); + +#define FETCH_LONG(A) \ + (A) = READ_BASED_PC_IDX(1) | (READ_BASED_PC_IDX(0) << 16); \ + INC_PC(4); + +#define PUSH_32_F(D) \ + AREG(7) -= 4; \ + Write_Word(AREG(7), (D) >> 16); \ + Write_Word(AREG(7) + 2, (D) & 0xFFFF); + +#define POP_32_F(D) \ + D = Read_Word(AREG(7)) << 16; \ + D |= Read_Word(AREG(7) + 2) & 0xFFFF; \ + AREG(7) += 4; + +#define GET_SWORD \ + ((s16)READ_BASED_PC) + +#define FETCH_BYTE(A) \ + (A) = READ_BASED_PC & 0xFF; INC_PC(2); + +#define FETCH_SBYTE(A) \ + (A) = (s8)((READ_BASED_PC) & 0xFF); INC_PC(2); + +#define FETCH_WORD(A) \ + (A) = READ_BASED_PC; INC_PC(2); + +#define FETCH_SWORD(A) \ + (A) = (s16)READ_BASED_PC; INC_PC(2); + +#define DECODE_EXT_WORD \ + { \ + u32 ext = READ_BASED_PC; INC_PC(2); \ + adr += (s8)(ext); \ + if (ext & 0x0800) adr += DREGs32(ext >> 12); \ + else adr += DREGs16(ext >> 12); \ + } + +#define READSX_BYTE_F(A, D) \ + D = (s8)Read_Byte(A); + +#define READSX_WORD_F(A, D) \ + D = (s16)Read_Word(A); + + +#define WRITE_BYTE_F(A, D) \ + Write_Byte(A, D); + +#define WRITE_WORD_F(A, D) \ + Write_Word(A, D); + +#define PUSH_16_F(D) \ + Write_Word(AREG(7) -= 2, D); \ + +#define POP_16_F(D) \ + D = (u16)Read_Word(AREG(7)); \ + AREG(7) += 2; + +#define GET_CCR \ + (((flag_C >> (M68K_SR_C_SFT - 0)) & 1) | \ + ((flag_V >> (M68K_SR_V_SFT - 1)) & 2) | \ + (((!flag_NotZ) & 1) << 2) | \ + ((flag_N >> (M68K_SR_N_SFT - 3)) & 8) | \ + ((flag_X >> (M68K_SR_X_SFT - 4)) & 0x10)) + +#ifdef FAME_EMULATE_TRACE +#define GET_SR \ + ((flag_S << 0) | \ + (flag_I << 8) | \ + (flag_T ) | \ + GET_CCR) +#else +#define GET_SR \ + ((flag_S << 0) | \ + (flag_I << 8) | \ + GET_CCR) +#endif + +#define SET_CCR(A) \ + flag_C = (A) << (M68K_SR_C_SFT - 0); \ + flag_V = (A) << (M68K_SR_V_SFT - 1); \ + flag_NotZ = ~(A) & 4; \ + flag_N = (A) << (M68K_SR_N_SFT - 3); \ + flag_X = (A) << (M68K_SR_X_SFT - 4); + + +#ifdef FAME_EMULATE_TRACE +#define SET_SR(A) \ + SET_CCR(A) \ + flag_T = (A) & M68K_SR_T; \ + flag_S = (A) & M68K_SR_S; \ + flag_I = ((A) >> 8) & 7; +#else +#define SET_SR(A) \ + SET_CCR(A) \ + flag_S = (A) & M68K_SR_S; \ + flag_I = ((A) >> 8) & 7; +#endif + +#define CHECK_INT_TO_JUMP(CLK) \ + if (interrupt_chk()) \ + { \ + /* \ + si los ciclos restantes son menores o iguales \ + que los de la instruccion en curso, \ + no proceder a fijar el contador, pues cycles_needed \ + sera negativo, haciendo que el calculo de ciclos \ + ejecutados al final de emulate sea incorrecto \ + */ \ + if(io_cycle_counter > (CLK)) \ + { \ + cycles_needed=io_cycle_counter-(CLK); \ + io_cycle_counter=0; \ + } \ + } + +#define BANKEND_TAG ((u32)-1) + +#define SETUP_FETCH_BANK(FNT, BANK) \ + { \ + u32 i = 0; \ + while (BANK[i].low_addr != BANKEND_TAG) \ + { \ + FNT(BANK[i].low_addr, BANK[i].high_addr, BANK[i].offset); \ + i++; \ + } \ + } + +#define SETUP_DATA_BANK(FNT, BANK) \ + { \ + u32 i = 0; \ + while (BANK[i].low_addr != BANKEND_TAG) \ + { \ + FNT(BANK[i].low_addr, BANK[i].high_addr, BANK[i].mem_handler, BANK[i].data); \ + i++; \ + } \ + } + + +#ifdef FAME_CHECK_BRANCHES + +#ifdef FAME_GOTOS +#define CHECK_BRANCH_EXCEPTION_GOTO_END goto famec_Exec_End; +#else +#define CHECK_BRANCH_EXCEPTION_GOTO_END io_cycle_counter=0; return; +#endif + +#define CHECK_BRANCH_EXCEPTION(_PC_) \ + if ((_PC_)&1) \ + { \ + u32 pr_PC=UNBASED_PC; \ + FAME_CONTEXT.execinfo |= M68K_EMULATE_GROUP_0; \ + execute_exception_group_0(M68K_ADDRESS_ERROR_EX, 0, pr_PC, 0x12 ); \ + CHECK_BRANCH_EXCEPTION_GOTO_END \ + } +#else +#define CHECK_BRANCH_EXCEPTION(_PC_) +#endif + +#define BUILD_OPCODE_TABLE \ +{ \ + u32 i, j; \ + for(i = 0x0000; i <= 0xFFFF; i += 0x0001) \ + JumpTable[0x0000 + i] = CAST_OP(0x4AFC); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0000 + i] = CAST_OP(0x0000); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0010 + i] = CAST_OP(0x0010); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0018 + i] = CAST_OP(0x0018); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0020 + i] = CAST_OP(0x0020); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0028 + i] = CAST_OP(0x0028); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0030 + i] = CAST_OP(0x0030); \ + JumpTable[0x0038] = CAST_OP(0x0038); \ + JumpTable[0x0039] = CAST_OP(0x0039); \ + JumpTable[0x001F] = CAST_OP(0x001F); \ + JumpTable[0x0027] = CAST_OP(0x0027); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0040 + i] = CAST_OP(0x0040); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0050 + i] = CAST_OP(0x0050); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0058 + i] = CAST_OP(0x0058); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0060 + i] = CAST_OP(0x0060); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0068 + i] = CAST_OP(0x0068); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0070 + i] = CAST_OP(0x0070); \ + JumpTable[0x0078] = CAST_OP(0x0078); \ + JumpTable[0x0079] = CAST_OP(0x0079); \ + JumpTable[0x005F] = CAST_OP(0x005F); \ + JumpTable[0x0067] = CAST_OP(0x0067); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0080 + i] = CAST_OP(0x0080); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0090 + i] = CAST_OP(0x0090); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0098 + i] = CAST_OP(0x0098); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x00A0 + i] = CAST_OP(0x00A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x00A8 + i] = CAST_OP(0x00A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x00B0 + i] = CAST_OP(0x00B0); \ + JumpTable[0x00B8] = CAST_OP(0x00B8); \ + JumpTable[0x00B9] = CAST_OP(0x00B9); \ + JumpTable[0x009F] = CAST_OP(0x009F); \ + JumpTable[0x00A7] = CAST_OP(0x00A7); \ + JumpTable[0x003C] = CAST_OP(0x003C); \ + JumpTable[0x007C] = CAST_OP(0x007C); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0200 + i] = CAST_OP(0x0200); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0210 + i] = CAST_OP(0x0210); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0218 + i] = CAST_OP(0x0218); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0220 + i] = CAST_OP(0x0220); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0228 + i] = CAST_OP(0x0228); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0230 + i] = CAST_OP(0x0230); \ + JumpTable[0x0238] = CAST_OP(0x0238); \ + JumpTable[0x0239] = CAST_OP(0x0239); \ + JumpTable[0x021F] = CAST_OP(0x021F); \ + JumpTable[0x0227] = CAST_OP(0x0227); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0240 + i] = CAST_OP(0x0240); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0250 + i] = CAST_OP(0x0250); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0258 + i] = CAST_OP(0x0258); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0260 + i] = CAST_OP(0x0260); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0268 + i] = CAST_OP(0x0268); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0270 + i] = CAST_OP(0x0270); \ + JumpTable[0x0278] = CAST_OP(0x0278); \ + JumpTable[0x0279] = CAST_OP(0x0279); \ + JumpTable[0x025F] = CAST_OP(0x025F); \ + JumpTable[0x0267] = CAST_OP(0x0267); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0280 + i] = CAST_OP(0x0280); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0290 + i] = CAST_OP(0x0290); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0298 + i] = CAST_OP(0x0298); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x02A0 + i] = CAST_OP(0x02A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x02A8 + i] = CAST_OP(0x02A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x02B0 + i] = CAST_OP(0x02B0); \ + JumpTable[0x02B8] = CAST_OP(0x02B8); \ + JumpTable[0x02B9] = CAST_OP(0x02B9); \ + JumpTable[0x029F] = CAST_OP(0x029F); \ + JumpTable[0x02A7] = CAST_OP(0x02A7); \ + JumpTable[0x023C] = CAST_OP(0x023C); \ + JumpTable[0x027C] = CAST_OP(0x027C); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0A00 + i] = CAST_OP(0x0A00); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0A10 + i] = CAST_OP(0x0A10); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0A18 + i] = CAST_OP(0x0A18); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0A20 + i] = CAST_OP(0x0A20); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0A28 + i] = CAST_OP(0x0A28); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0A30 + i] = CAST_OP(0x0A30); \ + JumpTable[0x0A38] = CAST_OP(0x0A38); \ + JumpTable[0x0A39] = CAST_OP(0x0A39); \ + JumpTable[0x0A1F] = CAST_OP(0x0A1F); \ + JumpTable[0x0A27] = CAST_OP(0x0A27); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0A40 + i] = CAST_OP(0x0A40); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0A50 + i] = CAST_OP(0x0A50); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0A58 + i] = CAST_OP(0x0A58); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0A60 + i] = CAST_OP(0x0A60); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0A68 + i] = CAST_OP(0x0A68); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0A70 + i] = CAST_OP(0x0A70); \ + JumpTable[0x0A78] = CAST_OP(0x0A78); \ + JumpTable[0x0A79] = CAST_OP(0x0A79); \ + JumpTable[0x0A5F] = CAST_OP(0x0A5F); \ + JumpTable[0x0A67] = CAST_OP(0x0A67); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0A80 + i] = CAST_OP(0x0A80); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0A90 + i] = CAST_OP(0x0A90); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0A98 + i] = CAST_OP(0x0A98); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0AA0 + i] = CAST_OP(0x0AA0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0AA8 + i] = CAST_OP(0x0AA8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0AB0 + i] = CAST_OP(0x0AB0); \ + JumpTable[0x0AB8] = CAST_OP(0x0AB8); \ + JumpTable[0x0AB9] = CAST_OP(0x0AB9); \ + JumpTable[0x0A9F] = CAST_OP(0x0A9F); \ + JumpTable[0x0AA7] = CAST_OP(0x0AA7); \ + JumpTable[0x0A3C] = CAST_OP(0x0A3C); \ + JumpTable[0x0A7C] = CAST_OP(0x0A7C); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0400 + i] = CAST_OP(0x0400); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0410 + i] = CAST_OP(0x0410); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0418 + i] = CAST_OP(0x0418); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0420 + i] = CAST_OP(0x0420); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0428 + i] = CAST_OP(0x0428); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0430 + i] = CAST_OP(0x0430); \ + JumpTable[0x0438] = CAST_OP(0x0438); \ + JumpTable[0x0439] = CAST_OP(0x0439); \ + JumpTable[0x041F] = CAST_OP(0x041F); \ + JumpTable[0x0427] = CAST_OP(0x0427); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0440 + i] = CAST_OP(0x0440); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0450 + i] = CAST_OP(0x0450); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0458 + i] = CAST_OP(0x0458); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0460 + i] = CAST_OP(0x0460); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0468 + i] = CAST_OP(0x0468); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0470 + i] = CAST_OP(0x0470); \ + JumpTable[0x0478] = CAST_OP(0x0478); \ + JumpTable[0x0479] = CAST_OP(0x0479); \ + JumpTable[0x045F] = CAST_OP(0x045F); \ + JumpTable[0x0467] = CAST_OP(0x0467); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0480 + i] = CAST_OP(0x0480); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0490 + i] = CAST_OP(0x0490); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0498 + i] = CAST_OP(0x0498); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x04A0 + i] = CAST_OP(0x04A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x04A8 + i] = CAST_OP(0x04A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x04B0 + i] = CAST_OP(0x04B0); \ + JumpTable[0x04B8] = CAST_OP(0x04B8); \ + JumpTable[0x04B9] = CAST_OP(0x04B9); \ + JumpTable[0x049F] = CAST_OP(0x049F); \ + JumpTable[0x04A7] = CAST_OP(0x04A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0600 + i] = CAST_OP(0x0600); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0610 + i] = CAST_OP(0x0610); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0618 + i] = CAST_OP(0x0618); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0620 + i] = CAST_OP(0x0620); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0628 + i] = CAST_OP(0x0628); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0630 + i] = CAST_OP(0x0630); \ + JumpTable[0x0638] = CAST_OP(0x0638); \ + JumpTable[0x0639] = CAST_OP(0x0639); \ + JumpTable[0x061F] = CAST_OP(0x061F); \ + JumpTable[0x0627] = CAST_OP(0x0627); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0640 + i] = CAST_OP(0x0640); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0650 + i] = CAST_OP(0x0650); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0658 + i] = CAST_OP(0x0658); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0660 + i] = CAST_OP(0x0660); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0668 + i] = CAST_OP(0x0668); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0670 + i] = CAST_OP(0x0670); \ + JumpTable[0x0678] = CAST_OP(0x0678); \ + JumpTable[0x0679] = CAST_OP(0x0679); \ + JumpTable[0x065F] = CAST_OP(0x065F); \ + JumpTable[0x0667] = CAST_OP(0x0667); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0680 + i] = CAST_OP(0x0680); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0690 + i] = CAST_OP(0x0690); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0698 + i] = CAST_OP(0x0698); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x06A0 + i] = CAST_OP(0x06A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x06A8 + i] = CAST_OP(0x06A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x06B0 + i] = CAST_OP(0x06B0); \ + JumpTable[0x06B8] = CAST_OP(0x06B8); \ + JumpTable[0x06B9] = CAST_OP(0x06B9); \ + JumpTable[0x069F] = CAST_OP(0x069F); \ + JumpTable[0x06A7] = CAST_OP(0x06A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0C00 + i] = CAST_OP(0x0C00); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0C10 + i] = CAST_OP(0x0C10); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0C18 + i] = CAST_OP(0x0C18); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0C20 + i] = CAST_OP(0x0C20); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0C28 + i] = CAST_OP(0x0C28); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0C30 + i] = CAST_OP(0x0C30); \ + JumpTable[0x0C38] = CAST_OP(0x0C38); \ + JumpTable[0x0C39] = CAST_OP(0x0C39); \ + JumpTable[0x0C1F] = CAST_OP(0x0C1F); \ + JumpTable[0x0C27] = CAST_OP(0x0C27); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0C40 + i] = CAST_OP(0x0C40); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0C50 + i] = CAST_OP(0x0C50); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0C58 + i] = CAST_OP(0x0C58); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0C60 + i] = CAST_OP(0x0C60); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0C68 + i] = CAST_OP(0x0C68); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0C70 + i] = CAST_OP(0x0C70); \ + JumpTable[0x0C78] = CAST_OP(0x0C78); \ + JumpTable[0x0C79] = CAST_OP(0x0C79); \ + JumpTable[0x0C5F] = CAST_OP(0x0C5F); \ + JumpTable[0x0C67] = CAST_OP(0x0C67); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0C80 + i] = CAST_OP(0x0C80); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0C90 + i] = CAST_OP(0x0C90); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0C98 + i] = CAST_OP(0x0C98); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0CA0 + i] = CAST_OP(0x0CA0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0CA8 + i] = CAST_OP(0x0CA8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0CB0 + i] = CAST_OP(0x0CB0); \ + JumpTable[0x0CB8] = CAST_OP(0x0CB8); \ + JumpTable[0x0CB9] = CAST_OP(0x0CB9); \ + JumpTable[0x0C9F] = CAST_OP(0x0C9F); \ + JumpTable[0x0CA7] = CAST_OP(0x0CA7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0800 + i] = CAST_OP(0x0800); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0810 + i] = CAST_OP(0x0810); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0818 + i] = CAST_OP(0x0818); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0820 + i] = CAST_OP(0x0820); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0828 + i] = CAST_OP(0x0828); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0830 + i] = CAST_OP(0x0830); \ + JumpTable[0x0838] = CAST_OP(0x0838); \ + JumpTable[0x0839] = CAST_OP(0x0839); \ + JumpTable[0x083A] = CAST_OP(0x083A); \ + JumpTable[0x083B] = CAST_OP(0x083B); \ + JumpTable[0x081F] = CAST_OP(0x081F); \ + JumpTable[0x0827] = CAST_OP(0x0827); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0840 + i] = CAST_OP(0x0840); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0850 + i] = CAST_OP(0x0850); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0858 + i] = CAST_OP(0x0858); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0860 + i] = CAST_OP(0x0860); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0868 + i] = CAST_OP(0x0868); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0870 + i] = CAST_OP(0x0870); \ + JumpTable[0x0878] = CAST_OP(0x0878); \ + JumpTable[0x0879] = CAST_OP(0x0879); \ + JumpTable[0x085F] = CAST_OP(0x085F); \ + JumpTable[0x0867] = CAST_OP(0x0867); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0880 + i] = CAST_OP(0x0880); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x0890 + i] = CAST_OP(0x0890); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x0898 + i] = CAST_OP(0x0898); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x08A0 + i] = CAST_OP(0x08A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x08A8 + i] = CAST_OP(0x08A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x08B0 + i] = CAST_OP(0x08B0); \ + JumpTable[0x08B8] = CAST_OP(0x08B8); \ + JumpTable[0x08B9] = CAST_OP(0x08B9); \ + JumpTable[0x089F] = CAST_OP(0x089F); \ + JumpTable[0x08A7] = CAST_OP(0x08A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x08C0 + i] = CAST_OP(0x08C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x08D0 + i] = CAST_OP(0x08D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x08D8 + i] = CAST_OP(0x08D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x08E0 + i] = CAST_OP(0x08E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x08E8 + i] = CAST_OP(0x08E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x08F0 + i] = CAST_OP(0x08F0); \ + JumpTable[0x08F8] = CAST_OP(0x08F8); \ + JumpTable[0x08F9] = CAST_OP(0x08F9); \ + JumpTable[0x08DF] = CAST_OP(0x08DF); \ + JumpTable[0x08E7] = CAST_OP(0x08E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0100 + i + j] = CAST_OP(0x0100); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0110 + i + j] = CAST_OP(0x0110); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0118 + i + j] = CAST_OP(0x0118); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0120 + i + j] = CAST_OP(0x0120); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0128 + i + j] = CAST_OP(0x0128); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0130 + i + j] = CAST_OP(0x0130); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x0138 + i] = CAST_OP(0x0138); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x0139 + i] = CAST_OP(0x0139); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x013A + i] = CAST_OP(0x013A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x013B + i] = CAST_OP(0x013B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x013C + i] = CAST_OP(0x013C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x011F + i] = CAST_OP(0x011F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x0127 + i] = CAST_OP(0x0127); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0140 + i + j] = CAST_OP(0x0140); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0150 + i + j] = CAST_OP(0x0150); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0158 + i + j] = CAST_OP(0x0158); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0160 + i + j] = CAST_OP(0x0160); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0168 + i + j] = CAST_OP(0x0168); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0170 + i + j] = CAST_OP(0x0170); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x0178 + i] = CAST_OP(0x0178); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x0179 + i] = CAST_OP(0x0179); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x015F + i] = CAST_OP(0x015F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x0167 + i] = CAST_OP(0x0167); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0180 + i + j] = CAST_OP(0x0180); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0190 + i + j] = CAST_OP(0x0190); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0198 + i + j] = CAST_OP(0x0198); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x01A0 + i + j] = CAST_OP(0x01A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x01A8 + i + j] = CAST_OP(0x01A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x01B0 + i + j] = CAST_OP(0x01B0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x01B8 + i] = CAST_OP(0x01B8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x01B9 + i] = CAST_OP(0x01B9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x019F + i] = CAST_OP(0x019F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x01A7 + i] = CAST_OP(0x01A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x01C0 + i + j] = CAST_OP(0x01C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x01D0 + i + j] = CAST_OP(0x01D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x01D8 + i + j] = CAST_OP(0x01D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x01E0 + i + j] = CAST_OP(0x01E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x01E8 + i + j] = CAST_OP(0x01E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x01F0 + i + j] = CAST_OP(0x01F0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x01F8 + i] = CAST_OP(0x01F8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x01F9 + i] = CAST_OP(0x01F9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x01DF + i] = CAST_OP(0x01DF); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x01E7 + i] = CAST_OP(0x01E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0108 + i + j] = CAST_OP(0x0108); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0148 + i + j] = CAST_OP(0x0148); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x0188 + i + j] = CAST_OP(0x0188); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x01C8 + i + j] = CAST_OP(0x01C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1000 + i + j] = CAST_OP(0x1000); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1080 + i + j] = CAST_OP(0x1080); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x10C0 + i + j] = CAST_OP(0x10C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x1100 + i + j] = CAST_OP(0x1100); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1140 + i + j] = CAST_OP(0x1140); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1180 + i + j] = CAST_OP(0x1180); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x11C0 + i] = CAST_OP(0x11C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x13C0 + i] = CAST_OP(0x13C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x1EC0 + i] = CAST_OP(0x1EC0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x1F00 + i] = CAST_OP(0x1F00); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1008 + i + j] = CAST_OP(0x1008); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1088 + i + j] = CAST_OP(0x1088); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x10C8 + i + j] = CAST_OP(0x10C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x1108 + i + j] = CAST_OP(0x1108); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1148 + i + j] = CAST_OP(0x1148); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1188 + i + j] = CAST_OP(0x1188); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x11C8 + i] = CAST_OP(0x11C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x13C8 + i] = CAST_OP(0x13C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x1EC8 + i] = CAST_OP(0x1EC8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x1F08 + i] = CAST_OP(0x1F08); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1010 + i + j] = CAST_OP(0x1010); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1090 + i + j] = CAST_OP(0x1090); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x10D0 + i + j] = CAST_OP(0x10D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x1110 + i + j] = CAST_OP(0x1110); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1150 + i + j] = CAST_OP(0x1150); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1190 + i + j] = CAST_OP(0x1190); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x11D0 + i] = CAST_OP(0x11D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x13D0 + i] = CAST_OP(0x13D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x1ED0 + i] = CAST_OP(0x1ED0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x1F10 + i] = CAST_OP(0x1F10); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1018 + i + j] = CAST_OP(0x1018); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1098 + i + j] = CAST_OP(0x1098); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x10D8 + i + j] = CAST_OP(0x10D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x1118 + i + j] = CAST_OP(0x1118); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1158 + i + j] = CAST_OP(0x1158); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1198 + i + j] = CAST_OP(0x1198); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x11D8 + i] = CAST_OP(0x11D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x13D8 + i] = CAST_OP(0x13D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x1ED8 + i] = CAST_OP(0x1ED8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x1F18 + i] = CAST_OP(0x1F18); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1020 + i + j] = CAST_OP(0x1020); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x10A0 + i + j] = CAST_OP(0x10A0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x10E0 + i + j] = CAST_OP(0x10E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x1120 + i + j] = CAST_OP(0x1120); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1160 + i + j] = CAST_OP(0x1160); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x11A0 + i + j] = CAST_OP(0x11A0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x11E0 + i] = CAST_OP(0x11E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x13E0 + i] = CAST_OP(0x13E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x1EE0 + i] = CAST_OP(0x1EE0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x1F20 + i] = CAST_OP(0x1F20); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1028 + i + j] = CAST_OP(0x1028); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x10A8 + i + j] = CAST_OP(0x10A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x10E8 + i + j] = CAST_OP(0x10E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x1128 + i + j] = CAST_OP(0x1128); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1168 + i + j] = CAST_OP(0x1168); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x11A8 + i + j] = CAST_OP(0x11A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x11E8 + i] = CAST_OP(0x11E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x13E8 + i] = CAST_OP(0x13E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x1EE8 + i] = CAST_OP(0x1EE8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x1F28 + i] = CAST_OP(0x1F28); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1030 + i + j] = CAST_OP(0x1030); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x10B0 + i + j] = CAST_OP(0x10B0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x10F0 + i + j] = CAST_OP(0x10F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x1130 + i + j] = CAST_OP(0x1130); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x1170 + i + j] = CAST_OP(0x1170); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x11B0 + i + j] = CAST_OP(0x11B0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x11F0 + i] = CAST_OP(0x11F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x13F0 + i] = CAST_OP(0x13F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x1EF0 + i] = CAST_OP(0x1EF0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x1F30 + i] = CAST_OP(0x1F30); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x1038 + i] = CAST_OP(0x1038); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x10B8 + i] = CAST_OP(0x10B8); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x10F8 + i] = CAST_OP(0x10F8); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x1138 + i] = CAST_OP(0x1138); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x1178 + i] = CAST_OP(0x1178); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x11B8 + i] = CAST_OP(0x11B8); \ + JumpTable[0x11F8] = CAST_OP(0x11F8); \ + JumpTable[0x13F8] = CAST_OP(0x13F8); \ + JumpTable[0x1EF8] = CAST_OP(0x1EF8); \ + JumpTable[0x1F38] = CAST_OP(0x1F38); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x1039 + i] = CAST_OP(0x1039); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x10B9 + i] = CAST_OP(0x10B9); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x10F9 + i] = CAST_OP(0x10F9); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x1139 + i] = CAST_OP(0x1139); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x1179 + i] = CAST_OP(0x1179); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x11B9 + i] = CAST_OP(0x11B9); \ + JumpTable[0x11F9] = CAST_OP(0x11F9); \ + JumpTable[0x13F9] = CAST_OP(0x13F9); \ + JumpTable[0x1EF9] = CAST_OP(0x1EF9); \ + JumpTable[0x1F39] = CAST_OP(0x1F39); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x103A + i] = CAST_OP(0x103A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x10BA + i] = CAST_OP(0x10BA); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x10FA + i] = CAST_OP(0x10FA); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x113A + i] = CAST_OP(0x113A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x117A + i] = CAST_OP(0x117A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x11BA + i] = CAST_OP(0x11BA); \ + JumpTable[0x11FA] = CAST_OP(0x11FA); \ + JumpTable[0x13FA] = CAST_OP(0x13FA); \ + JumpTable[0x1EFA] = CAST_OP(0x1EFA); \ + JumpTable[0x1F3A] = CAST_OP(0x1F3A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x103B + i] = CAST_OP(0x103B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x10BB + i] = CAST_OP(0x10BB); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x10FB + i] = CAST_OP(0x10FB); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x113B + i] = CAST_OP(0x113B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x117B + i] = CAST_OP(0x117B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x11BB + i] = CAST_OP(0x11BB); \ + JumpTable[0x11FB] = CAST_OP(0x11FB); \ + JumpTable[0x13FB] = CAST_OP(0x13FB); \ + JumpTable[0x1EFB] = CAST_OP(0x1EFB); \ + JumpTable[0x1F3B] = CAST_OP(0x1F3B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x103C + i] = CAST_OP(0x103C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x10BC + i] = CAST_OP(0x10BC); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x10FC + i] = CAST_OP(0x10FC); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x113C + i] = CAST_OP(0x113C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x117C + i] = CAST_OP(0x117C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x11BC + i] = CAST_OP(0x11BC); \ + JumpTable[0x11FC] = CAST_OP(0x11FC); \ + JumpTable[0x13FC] = CAST_OP(0x13FC); \ + JumpTable[0x1EFC] = CAST_OP(0x1EFC); \ + JumpTable[0x1F3C] = CAST_OP(0x1F3C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x101F + i] = CAST_OP(0x101F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x109F + i] = CAST_OP(0x109F); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x10DF + i] = CAST_OP(0x10DF); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x111F + i] = CAST_OP(0x111F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x115F + i] = CAST_OP(0x115F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x119F + i] = CAST_OP(0x119F); \ + JumpTable[0x11DF] = CAST_OP(0x11DF); \ + JumpTable[0x13DF] = CAST_OP(0x13DF); \ + JumpTable[0x1EDF] = CAST_OP(0x1EDF); \ + JumpTable[0x1F1F] = CAST_OP(0x1F1F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x1027 + i] = CAST_OP(0x1027); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x10A7 + i] = CAST_OP(0x10A7); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x10E7 + i] = CAST_OP(0x10E7); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x1127 + i] = CAST_OP(0x1127); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x1167 + i] = CAST_OP(0x1167); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x11A7 + i] = CAST_OP(0x11A7); \ + JumpTable[0x11E7] = CAST_OP(0x11E7); \ + JumpTable[0x13E7] = CAST_OP(0x13E7); \ + JumpTable[0x1EE7] = CAST_OP(0x1EE7); \ + JumpTable[0x1F27] = CAST_OP(0x1F27); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2000 + i + j] = CAST_OP(0x2000); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2080 + i + j] = CAST_OP(0x2080); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x20C0 + i + j] = CAST_OP(0x20C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x2100 + i + j] = CAST_OP(0x2100); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2140 + i + j] = CAST_OP(0x2140); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2180 + i + j] = CAST_OP(0x2180); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x21C0 + i] = CAST_OP(0x21C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x23C0 + i] = CAST_OP(0x23C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x2EC0 + i] = CAST_OP(0x2EC0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x2F00 + i] = CAST_OP(0x2F00); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2008 + i + j] = CAST_OP(0x2008); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2088 + i + j] = CAST_OP(0x2088); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x20C8 + i + j] = CAST_OP(0x20C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x2108 + i + j] = CAST_OP(0x2108); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2148 + i + j] = CAST_OP(0x2148); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2188 + i + j] = CAST_OP(0x2188); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x21C8 + i] = CAST_OP(0x21C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x23C8 + i] = CAST_OP(0x23C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x2EC8 + i] = CAST_OP(0x2EC8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x2F08 + i] = CAST_OP(0x2F08); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2010 + i + j] = CAST_OP(0x2010); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2090 + i + j] = CAST_OP(0x2090); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x20D0 + i + j] = CAST_OP(0x20D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x2110 + i + j] = CAST_OP(0x2110); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2150 + i + j] = CAST_OP(0x2150); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2190 + i + j] = CAST_OP(0x2190); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x21D0 + i] = CAST_OP(0x21D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x23D0 + i] = CAST_OP(0x23D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x2ED0 + i] = CAST_OP(0x2ED0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x2F10 + i] = CAST_OP(0x2F10); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2018 + i + j] = CAST_OP(0x2018); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2098 + i + j] = CAST_OP(0x2098); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x20D8 + i + j] = CAST_OP(0x20D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x2118 + i + j] = CAST_OP(0x2118); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2158 + i + j] = CAST_OP(0x2158); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2198 + i + j] = CAST_OP(0x2198); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x21D8 + i] = CAST_OP(0x21D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x23D8 + i] = CAST_OP(0x23D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x2ED8 + i] = CAST_OP(0x2ED8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x2F18 + i] = CAST_OP(0x2F18); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2020 + i + j] = CAST_OP(0x2020); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x20A0 + i + j] = CAST_OP(0x20A0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x20E0 + i + j] = CAST_OP(0x20E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x2120 + i + j] = CAST_OP(0x2120); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2160 + i + j] = CAST_OP(0x2160); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x21A0 + i + j] = CAST_OP(0x21A0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x21E0 + i] = CAST_OP(0x21E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x23E0 + i] = CAST_OP(0x23E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x2EE0 + i] = CAST_OP(0x2EE0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x2F20 + i] = CAST_OP(0x2F20); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2028 + i + j] = CAST_OP(0x2028); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x20A8 + i + j] = CAST_OP(0x20A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x20E8 + i + j] = CAST_OP(0x20E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x2128 + i + j] = CAST_OP(0x2128); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2168 + i + j] = CAST_OP(0x2168); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x21A8 + i + j] = CAST_OP(0x21A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x21E8 + i] = CAST_OP(0x21E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x23E8 + i] = CAST_OP(0x23E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x2EE8 + i] = CAST_OP(0x2EE8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x2F28 + i] = CAST_OP(0x2F28); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2030 + i + j] = CAST_OP(0x2030); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x20B0 + i + j] = CAST_OP(0x20B0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x20F0 + i + j] = CAST_OP(0x20F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x2130 + i + j] = CAST_OP(0x2130); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2170 + i + j] = CAST_OP(0x2170); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x21B0 + i + j] = CAST_OP(0x21B0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x21F0 + i] = CAST_OP(0x21F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x23F0 + i] = CAST_OP(0x23F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x2EF0 + i] = CAST_OP(0x2EF0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x2F30 + i] = CAST_OP(0x2F30); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x2038 + i] = CAST_OP(0x2038); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x20B8 + i] = CAST_OP(0x20B8); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x20F8 + i] = CAST_OP(0x20F8); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x2138 + i] = CAST_OP(0x2138); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x2178 + i] = CAST_OP(0x2178); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x21B8 + i] = CAST_OP(0x21B8); \ + JumpTable[0x21F8] = CAST_OP(0x21F8); \ + JumpTable[0x23F8] = CAST_OP(0x23F8); \ + JumpTable[0x2EF8] = CAST_OP(0x2EF8); \ + JumpTable[0x2F38] = CAST_OP(0x2F38); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x2039 + i] = CAST_OP(0x2039); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x20B9 + i] = CAST_OP(0x20B9); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x20F9 + i] = CAST_OP(0x20F9); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x2139 + i] = CAST_OP(0x2139); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x2179 + i] = CAST_OP(0x2179); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x21B9 + i] = CAST_OP(0x21B9); \ + JumpTable[0x21F9] = CAST_OP(0x21F9); \ + JumpTable[0x23F9] = CAST_OP(0x23F9); \ + JumpTable[0x2EF9] = CAST_OP(0x2EF9); \ + JumpTable[0x2F39] = CAST_OP(0x2F39); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x203A + i] = CAST_OP(0x203A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x20BA + i] = CAST_OP(0x20BA); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x20FA + i] = CAST_OP(0x20FA); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x213A + i] = CAST_OP(0x213A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x217A + i] = CAST_OP(0x217A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x21BA + i] = CAST_OP(0x21BA); \ + JumpTable[0x21FA] = CAST_OP(0x21FA); \ + JumpTable[0x23FA] = CAST_OP(0x23FA); \ + JumpTable[0x2EFA] = CAST_OP(0x2EFA); \ + JumpTable[0x2F3A] = CAST_OP(0x2F3A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x203B + i] = CAST_OP(0x203B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x20BB + i] = CAST_OP(0x20BB); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x20FB + i] = CAST_OP(0x20FB); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x213B + i] = CAST_OP(0x213B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x217B + i] = CAST_OP(0x217B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x21BB + i] = CAST_OP(0x21BB); \ + JumpTable[0x21FB] = CAST_OP(0x21FB); \ + JumpTable[0x23FB] = CAST_OP(0x23FB); \ + JumpTable[0x2EFB] = CAST_OP(0x2EFB); \ + JumpTable[0x2F3B] = CAST_OP(0x2F3B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x203C + i] = CAST_OP(0x203C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x20BC + i] = CAST_OP(0x20BC); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x20FC + i] = CAST_OP(0x20FC); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x213C + i] = CAST_OP(0x213C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x217C + i] = CAST_OP(0x217C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x21BC + i] = CAST_OP(0x21BC); \ + JumpTable[0x21FC] = CAST_OP(0x21FC); \ + JumpTable[0x23FC] = CAST_OP(0x23FC); \ + JumpTable[0x2EFC] = CAST_OP(0x2EFC); \ + JumpTable[0x2F3C] = CAST_OP(0x2F3C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x201F + i] = CAST_OP(0x201F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x209F + i] = CAST_OP(0x209F); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x20DF + i] = CAST_OP(0x20DF); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x211F + i] = CAST_OP(0x211F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x215F + i] = CAST_OP(0x215F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x219F + i] = CAST_OP(0x219F); \ + JumpTable[0x21DF] = CAST_OP(0x21DF); \ + JumpTable[0x23DF] = CAST_OP(0x23DF); \ + JumpTable[0x2EDF] = CAST_OP(0x2EDF); \ + JumpTable[0x2F1F] = CAST_OP(0x2F1F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x2027 + i] = CAST_OP(0x2027); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x20A7 + i] = CAST_OP(0x20A7); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x20E7 + i] = CAST_OP(0x20E7); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x2127 + i] = CAST_OP(0x2127); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x2167 + i] = CAST_OP(0x2167); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x21A7 + i] = CAST_OP(0x21A7); \ + JumpTable[0x21E7] = CAST_OP(0x21E7); \ + JumpTable[0x23E7] = CAST_OP(0x23E7); \ + JumpTable[0x2EE7] = CAST_OP(0x2EE7); \ + JumpTable[0x2F27] = CAST_OP(0x2F27); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3000 + i + j] = CAST_OP(0x3000); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3080 + i + j] = CAST_OP(0x3080); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x30C0 + i + j] = CAST_OP(0x30C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x3100 + i + j] = CAST_OP(0x3100); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3140 + i + j] = CAST_OP(0x3140); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3180 + i + j] = CAST_OP(0x3180); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x31C0 + i] = CAST_OP(0x31C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x33C0 + i] = CAST_OP(0x33C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x3EC0 + i] = CAST_OP(0x3EC0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x3F00 + i] = CAST_OP(0x3F00); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3008 + i + j] = CAST_OP(0x3008); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3088 + i + j] = CAST_OP(0x3088); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x30C8 + i + j] = CAST_OP(0x30C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x3108 + i + j] = CAST_OP(0x3108); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3148 + i + j] = CAST_OP(0x3148); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3188 + i + j] = CAST_OP(0x3188); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x31C8 + i] = CAST_OP(0x31C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x33C8 + i] = CAST_OP(0x33C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x3EC8 + i] = CAST_OP(0x3EC8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x3F08 + i] = CAST_OP(0x3F08); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3010 + i + j] = CAST_OP(0x3010); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3090 + i + j] = CAST_OP(0x3090); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x30D0 + i + j] = CAST_OP(0x30D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x3110 + i + j] = CAST_OP(0x3110); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3150 + i + j] = CAST_OP(0x3150); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3190 + i + j] = CAST_OP(0x3190); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x31D0 + i] = CAST_OP(0x31D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x33D0 + i] = CAST_OP(0x33D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x3ED0 + i] = CAST_OP(0x3ED0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x3F10 + i] = CAST_OP(0x3F10); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3018 + i + j] = CAST_OP(0x3018); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3098 + i + j] = CAST_OP(0x3098); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x30D8 + i + j] = CAST_OP(0x30D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x3118 + i + j] = CAST_OP(0x3118); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3158 + i + j] = CAST_OP(0x3158); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3198 + i + j] = CAST_OP(0x3198); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x31D8 + i] = CAST_OP(0x31D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x33D8 + i] = CAST_OP(0x33D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x3ED8 + i] = CAST_OP(0x3ED8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x3F18 + i] = CAST_OP(0x3F18); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3020 + i + j] = CAST_OP(0x3020); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x30A0 + i + j] = CAST_OP(0x30A0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x30E0 + i + j] = CAST_OP(0x30E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x3120 + i + j] = CAST_OP(0x3120); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3160 + i + j] = CAST_OP(0x3160); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x31A0 + i + j] = CAST_OP(0x31A0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x31E0 + i] = CAST_OP(0x31E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x33E0 + i] = CAST_OP(0x33E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x3EE0 + i] = CAST_OP(0x3EE0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x3F20 + i] = CAST_OP(0x3F20); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3028 + i + j] = CAST_OP(0x3028); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x30A8 + i + j] = CAST_OP(0x30A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x30E8 + i + j] = CAST_OP(0x30E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x3128 + i + j] = CAST_OP(0x3128); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3168 + i + j] = CAST_OP(0x3168); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x31A8 + i + j] = CAST_OP(0x31A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x31E8 + i] = CAST_OP(0x31E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x33E8 + i] = CAST_OP(0x33E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x3EE8 + i] = CAST_OP(0x3EE8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x3F28 + i] = CAST_OP(0x3F28); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3030 + i + j] = CAST_OP(0x3030); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x30B0 + i + j] = CAST_OP(0x30B0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x30F0 + i + j] = CAST_OP(0x30F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x3130 + i + j] = CAST_OP(0x3130); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3170 + i + j] = CAST_OP(0x3170); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x31B0 + i + j] = CAST_OP(0x31B0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x31F0 + i] = CAST_OP(0x31F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x33F0 + i] = CAST_OP(0x33F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x3EF0 + i] = CAST_OP(0x3EF0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x3F30 + i] = CAST_OP(0x3F30); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x3038 + i] = CAST_OP(0x3038); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x30B8 + i] = CAST_OP(0x30B8); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x30F8 + i] = CAST_OP(0x30F8); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x3138 + i] = CAST_OP(0x3138); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x3178 + i] = CAST_OP(0x3178); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x31B8 + i] = CAST_OP(0x31B8); \ + JumpTable[0x31F8] = CAST_OP(0x31F8); \ + JumpTable[0x33F8] = CAST_OP(0x33F8); \ + JumpTable[0x3EF8] = CAST_OP(0x3EF8); \ + JumpTable[0x3F38] = CAST_OP(0x3F38); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x3039 + i] = CAST_OP(0x3039); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x30B9 + i] = CAST_OP(0x30B9); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x30F9 + i] = CAST_OP(0x30F9); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x3139 + i] = CAST_OP(0x3139); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x3179 + i] = CAST_OP(0x3179); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x31B9 + i] = CAST_OP(0x31B9); \ + JumpTable[0x31F9] = CAST_OP(0x31F9); \ + JumpTable[0x33F9] = CAST_OP(0x33F9); \ + JumpTable[0x3EF9] = CAST_OP(0x3EF9); \ + JumpTable[0x3F39] = CAST_OP(0x3F39); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x303A + i] = CAST_OP(0x303A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x30BA + i] = CAST_OP(0x30BA); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x30FA + i] = CAST_OP(0x30FA); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x313A + i] = CAST_OP(0x313A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x317A + i] = CAST_OP(0x317A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x31BA + i] = CAST_OP(0x31BA); \ + JumpTable[0x31FA] = CAST_OP(0x31FA); \ + JumpTable[0x33FA] = CAST_OP(0x33FA); \ + JumpTable[0x3EFA] = CAST_OP(0x3EFA); \ + JumpTable[0x3F3A] = CAST_OP(0x3F3A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x303B + i] = CAST_OP(0x303B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x30BB + i] = CAST_OP(0x30BB); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x30FB + i] = CAST_OP(0x30FB); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x313B + i] = CAST_OP(0x313B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x317B + i] = CAST_OP(0x317B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x31BB + i] = CAST_OP(0x31BB); \ + JumpTable[0x31FB] = CAST_OP(0x31FB); \ + JumpTable[0x33FB] = CAST_OP(0x33FB); \ + JumpTable[0x3EFB] = CAST_OP(0x3EFB); \ + JumpTable[0x3F3B] = CAST_OP(0x3F3B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x303C + i] = CAST_OP(0x303C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x30BC + i] = CAST_OP(0x30BC); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x30FC + i] = CAST_OP(0x30FC); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x313C + i] = CAST_OP(0x313C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x317C + i] = CAST_OP(0x317C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x31BC + i] = CAST_OP(0x31BC); \ + JumpTable[0x31FC] = CAST_OP(0x31FC); \ + JumpTable[0x33FC] = CAST_OP(0x33FC); \ + JumpTable[0x3EFC] = CAST_OP(0x3EFC); \ + JumpTable[0x3F3C] = CAST_OP(0x3F3C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x301F + i] = CAST_OP(0x301F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x309F + i] = CAST_OP(0x309F); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x30DF + i] = CAST_OP(0x30DF); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x311F + i] = CAST_OP(0x311F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x315F + i] = CAST_OP(0x315F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x319F + i] = CAST_OP(0x319F); \ + JumpTable[0x31DF] = CAST_OP(0x31DF); \ + JumpTable[0x33DF] = CAST_OP(0x33DF); \ + JumpTable[0x3EDF] = CAST_OP(0x3EDF); \ + JumpTable[0x3F1F] = CAST_OP(0x3F1F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x3027 + i] = CAST_OP(0x3027); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x30A7 + i] = CAST_OP(0x30A7); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x30E7 + i] = CAST_OP(0x30E7); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x3127 + i] = CAST_OP(0x3127); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x3167 + i] = CAST_OP(0x3167); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x31A7 + i] = CAST_OP(0x31A7); \ + JumpTable[0x31E7] = CAST_OP(0x31E7); \ + JumpTable[0x33E7] = CAST_OP(0x33E7); \ + JumpTable[0x3EE7] = CAST_OP(0x3EE7); \ + JumpTable[0x3F27] = CAST_OP(0x3F27); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2040 + i + j] = CAST_OP(0x2040); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2048 + i + j] = CAST_OP(0x2048); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2050 + i + j] = CAST_OP(0x2050); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2058 + i + j] = CAST_OP(0x2058); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2060 + i + j] = CAST_OP(0x2060); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2068 + i + j] = CAST_OP(0x2068); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x2070 + i + j] = CAST_OP(0x2070); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x2078 + i] = CAST_OP(0x2078); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x2079 + i] = CAST_OP(0x2079); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x207A + i] = CAST_OP(0x207A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x207B + i] = CAST_OP(0x207B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x207C + i] = CAST_OP(0x207C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x205F + i] = CAST_OP(0x205F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x2067 + i] = CAST_OP(0x2067); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3040 + i + j] = CAST_OP(0x3040); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3048 + i + j] = CAST_OP(0x3048); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3050 + i + j] = CAST_OP(0x3050); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3058 + i + j] = CAST_OP(0x3058); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3060 + i + j] = CAST_OP(0x3060); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3068 + i + j] = CAST_OP(0x3068); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x3070 + i + j] = CAST_OP(0x3070); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x3078 + i] = CAST_OP(0x3078); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x3079 + i] = CAST_OP(0x3079); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x307A + i] = CAST_OP(0x307A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x307B + i] = CAST_OP(0x307B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x307C + i] = CAST_OP(0x307C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x305F + i] = CAST_OP(0x305F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x3067 + i] = CAST_OP(0x3067); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4000 + i] = CAST_OP(0x4000); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4010 + i] = CAST_OP(0x4010); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4018 + i] = CAST_OP(0x4018); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4020 + i] = CAST_OP(0x4020); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4028 + i] = CAST_OP(0x4028); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4030 + i] = CAST_OP(0x4030); \ + JumpTable[0x4038] = CAST_OP(0x4038); \ + JumpTable[0x4039] = CAST_OP(0x4039); \ + JumpTable[0x401F] = CAST_OP(0x401F); \ + JumpTable[0x4027] = CAST_OP(0x4027); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4040 + i] = CAST_OP(0x4040); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4050 + i] = CAST_OP(0x4050); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4058 + i] = CAST_OP(0x4058); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4060 + i] = CAST_OP(0x4060); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4068 + i] = CAST_OP(0x4068); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4070 + i] = CAST_OP(0x4070); \ + JumpTable[0x4078] = CAST_OP(0x4078); \ + JumpTable[0x4079] = CAST_OP(0x4079); \ + JumpTable[0x405F] = CAST_OP(0x405F); \ + JumpTable[0x4067] = CAST_OP(0x4067); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4080 + i] = CAST_OP(0x4080); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4090 + i] = CAST_OP(0x4090); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4098 + i] = CAST_OP(0x4098); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x40A0 + i] = CAST_OP(0x40A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x40A8 + i] = CAST_OP(0x40A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x40B0 + i] = CAST_OP(0x40B0); \ + JumpTable[0x40B8] = CAST_OP(0x40B8); \ + JumpTable[0x40B9] = CAST_OP(0x40B9); \ + JumpTable[0x409F] = CAST_OP(0x409F); \ + JumpTable[0x40A7] = CAST_OP(0x40A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4200 + i] = CAST_OP(0x4200); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4210 + i] = CAST_OP(0x4210); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4218 + i] = CAST_OP(0x4218); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4220 + i] = CAST_OP(0x4220); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4228 + i] = CAST_OP(0x4228); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4230 + i] = CAST_OP(0x4230); \ + JumpTable[0x4238] = CAST_OP(0x4238); \ + JumpTable[0x4239] = CAST_OP(0x4239); \ + JumpTable[0x421F] = CAST_OP(0x421F); \ + JumpTable[0x4227] = CAST_OP(0x4227); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4240 + i] = CAST_OP(0x4240); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4250 + i] = CAST_OP(0x4250); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4258 + i] = CAST_OP(0x4258); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4260 + i] = CAST_OP(0x4260); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4268 + i] = CAST_OP(0x4268); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4270 + i] = CAST_OP(0x4270); \ + JumpTable[0x4278] = CAST_OP(0x4278); \ + JumpTable[0x4279] = CAST_OP(0x4279); \ + JumpTable[0x425F] = CAST_OP(0x425F); \ + JumpTable[0x4267] = CAST_OP(0x4267); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4280 + i] = CAST_OP(0x4280); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4290 + i] = CAST_OP(0x4290); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4298 + i] = CAST_OP(0x4298); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x42A0 + i] = CAST_OP(0x42A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x42A8 + i] = CAST_OP(0x42A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x42B0 + i] = CAST_OP(0x42B0); \ + JumpTable[0x42B8] = CAST_OP(0x42B8); \ + JumpTable[0x42B9] = CAST_OP(0x42B9); \ + JumpTable[0x429F] = CAST_OP(0x429F); \ + JumpTable[0x42A7] = CAST_OP(0x42A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4400 + i] = CAST_OP(0x4400); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4410 + i] = CAST_OP(0x4410); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4418 + i] = CAST_OP(0x4418); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4420 + i] = CAST_OP(0x4420); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4428 + i] = CAST_OP(0x4428); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4430 + i] = CAST_OP(0x4430); \ + JumpTable[0x4438] = CAST_OP(0x4438); \ + JumpTable[0x4439] = CAST_OP(0x4439); \ + JumpTable[0x441F] = CAST_OP(0x441F); \ + JumpTable[0x4427] = CAST_OP(0x4427); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4440 + i] = CAST_OP(0x4440); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4450 + i] = CAST_OP(0x4450); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4458 + i] = CAST_OP(0x4458); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4460 + i] = CAST_OP(0x4460); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4468 + i] = CAST_OP(0x4468); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4470 + i] = CAST_OP(0x4470); \ + JumpTable[0x4478] = CAST_OP(0x4478); \ + JumpTable[0x4479] = CAST_OP(0x4479); \ + JumpTable[0x445F] = CAST_OP(0x445F); \ + JumpTable[0x4467] = CAST_OP(0x4467); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4480 + i] = CAST_OP(0x4480); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4490 + i] = CAST_OP(0x4490); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4498 + i] = CAST_OP(0x4498); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x44A0 + i] = CAST_OP(0x44A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x44A8 + i] = CAST_OP(0x44A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x44B0 + i] = CAST_OP(0x44B0); \ + JumpTable[0x44B8] = CAST_OP(0x44B8); \ + JumpTable[0x44B9] = CAST_OP(0x44B9); \ + JumpTable[0x449F] = CAST_OP(0x449F); \ + JumpTable[0x44A7] = CAST_OP(0x44A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4600 + i] = CAST_OP(0x4600); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4610 + i] = CAST_OP(0x4610); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4618 + i] = CAST_OP(0x4618); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4620 + i] = CAST_OP(0x4620); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4628 + i] = CAST_OP(0x4628); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4630 + i] = CAST_OP(0x4630); \ + JumpTable[0x4638] = CAST_OP(0x4638); \ + JumpTable[0x4639] = CAST_OP(0x4639); \ + JumpTable[0x461F] = CAST_OP(0x461F); \ + JumpTable[0x4627] = CAST_OP(0x4627); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4640 + i] = CAST_OP(0x4640); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4650 + i] = CAST_OP(0x4650); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4658 + i] = CAST_OP(0x4658); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4660 + i] = CAST_OP(0x4660); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4668 + i] = CAST_OP(0x4668); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4670 + i] = CAST_OP(0x4670); \ + JumpTable[0x4678] = CAST_OP(0x4678); \ + JumpTable[0x4679] = CAST_OP(0x4679); \ + JumpTable[0x465F] = CAST_OP(0x465F); \ + JumpTable[0x4667] = CAST_OP(0x4667); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4680 + i] = CAST_OP(0x4680); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4690 + i] = CAST_OP(0x4690); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4698 + i] = CAST_OP(0x4698); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x46A0 + i] = CAST_OP(0x46A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x46A8 + i] = CAST_OP(0x46A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x46B0 + i] = CAST_OP(0x46B0); \ + JumpTable[0x46B8] = CAST_OP(0x46B8); \ + JumpTable[0x46B9] = CAST_OP(0x46B9); \ + JumpTable[0x469F] = CAST_OP(0x469F); \ + JumpTable[0x46A7] = CAST_OP(0x46A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x40C0 + i] = CAST_OP(0x40C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x40D0 + i] = CAST_OP(0x40D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x40D8 + i] = CAST_OP(0x40D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x40E0 + i] = CAST_OP(0x40E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x40E8 + i] = CAST_OP(0x40E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x40F0 + i] = CAST_OP(0x40F0); \ + JumpTable[0x40F8] = CAST_OP(0x40F8); \ + JumpTable[0x40F9] = CAST_OP(0x40F9); \ + JumpTable[0x40DF] = CAST_OP(0x40DF); \ + JumpTable[0x40E7] = CAST_OP(0x40E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x44C0 + i] = CAST_OP(0x44C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x44D0 + i] = CAST_OP(0x44D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x44D8 + i] = CAST_OP(0x44D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x44E0 + i] = CAST_OP(0x44E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x44E8 + i] = CAST_OP(0x44E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x44F0 + i] = CAST_OP(0x44F0); \ + JumpTable[0x44F8] = CAST_OP(0x44F8); \ + JumpTable[0x44F9] = CAST_OP(0x44F9); \ + JumpTable[0x44FA] = CAST_OP(0x44FA); \ + JumpTable[0x44FB] = CAST_OP(0x44FB); \ + JumpTable[0x44FC] = CAST_OP(0x44FC); \ + JumpTable[0x44DF] = CAST_OP(0x44DF); \ + JumpTable[0x44E7] = CAST_OP(0x44E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x46C0 + i] = CAST_OP(0x46C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x46D0 + i] = CAST_OP(0x46D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x46D8 + i] = CAST_OP(0x46D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x46E0 + i] = CAST_OP(0x46E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x46E8 + i] = CAST_OP(0x46E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x46F0 + i] = CAST_OP(0x46F0); \ + JumpTable[0x46F8] = CAST_OP(0x46F8); \ + JumpTable[0x46F9] = CAST_OP(0x46F9); \ + JumpTable[0x46FA] = CAST_OP(0x46FA); \ + JumpTable[0x46FB] = CAST_OP(0x46FB); \ + JumpTable[0x46FC] = CAST_OP(0x46FC); \ + JumpTable[0x46DF] = CAST_OP(0x46DF); \ + JumpTable[0x46E7] = CAST_OP(0x46E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4800 + i] = CAST_OP(0x4800); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4810 + i] = CAST_OP(0x4810); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4818 + i] = CAST_OP(0x4818); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4820 + i] = CAST_OP(0x4820); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4828 + i] = CAST_OP(0x4828); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4830 + i] = CAST_OP(0x4830); \ + JumpTable[0x4838] = CAST_OP(0x4838); \ + JumpTable[0x4839] = CAST_OP(0x4839); \ + JumpTable[0x481F] = CAST_OP(0x481F); \ + JumpTable[0x4827] = CAST_OP(0x4827); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4850 + i] = CAST_OP(0x4850); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4868 + i] = CAST_OP(0x4868); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4870 + i] = CAST_OP(0x4870); \ + JumpTable[0x4878] = CAST_OP(0x4878); \ + JumpTable[0x4879] = CAST_OP(0x4879); \ + JumpTable[0x487A] = CAST_OP(0x487A); \ + JumpTable[0x487B] = CAST_OP(0x487B); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4840 + i] = CAST_OP(0x4840); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4890 + i] = CAST_OP(0x4890); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x48A0 + i] = CAST_OP(0x48A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x48A8 + i] = CAST_OP(0x48A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x48B0 + i] = CAST_OP(0x48B0); \ + JumpTable[0x48B8] = CAST_OP(0x48B8); \ + JumpTable[0x48B9] = CAST_OP(0x48B9); \ + JumpTable[0x48A7] = CAST_OP(0x48A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x48D0 + i] = CAST_OP(0x48D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x48E0 + i] = CAST_OP(0x48E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x48E8 + i] = CAST_OP(0x48E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x48F0 + i] = CAST_OP(0x48F0); \ + JumpTable[0x48F8] = CAST_OP(0x48F8); \ + JumpTable[0x48F9] = CAST_OP(0x48F9); \ + JumpTable[0x48E7] = CAST_OP(0x48E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4880 + i] = CAST_OP(0x4880); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x48C0 + i] = CAST_OP(0x48C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4A00 + i] = CAST_OP(0x4A00); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4A10 + i] = CAST_OP(0x4A10); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4A18 + i] = CAST_OP(0x4A18); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4A20 + i] = CAST_OP(0x4A20); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4A28 + i] = CAST_OP(0x4A28); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4A30 + i] = CAST_OP(0x4A30); \ + JumpTable[0x4A38] = CAST_OP(0x4A38); \ + JumpTable[0x4A39] = CAST_OP(0x4A39); \ + JumpTable[0x4A1F] = CAST_OP(0x4A1F); \ + JumpTable[0x4A27] = CAST_OP(0x4A27); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4A40 + i] = CAST_OP(0x4A40); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4A50 + i] = CAST_OP(0x4A50); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4A58 + i] = CAST_OP(0x4A58); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4A60 + i] = CAST_OP(0x4A60); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4A68 + i] = CAST_OP(0x4A68); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4A70 + i] = CAST_OP(0x4A70); \ + JumpTable[0x4A78] = CAST_OP(0x4A78); \ + JumpTable[0x4A79] = CAST_OP(0x4A79); \ + JumpTable[0x4A5F] = CAST_OP(0x4A5F); \ + JumpTable[0x4A67] = CAST_OP(0x4A67); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4A80 + i] = CAST_OP(0x4A80); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4A90 + i] = CAST_OP(0x4A90); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4A98 + i] = CAST_OP(0x4A98); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4AA0 + i] = CAST_OP(0x4AA0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4AA8 + i] = CAST_OP(0x4AA8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4AB0 + i] = CAST_OP(0x4AB0); \ + JumpTable[0x4AB8] = CAST_OP(0x4AB8); \ + JumpTable[0x4AB9] = CAST_OP(0x4AB9); \ + JumpTable[0x4A9F] = CAST_OP(0x4A9F); \ + JumpTable[0x4AA7] = CAST_OP(0x4AA7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4AC0 + i] = CAST_OP(0x4AC0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4AD0 + i] = CAST_OP(0x4AD0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4AD8 + i] = CAST_OP(0x4AD8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4AE0 + i] = CAST_OP(0x4AE0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4AE8 + i] = CAST_OP(0x4AE8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4AF0 + i] = CAST_OP(0x4AF0); \ + JumpTable[0x4AF8] = CAST_OP(0x4AF8); \ + JumpTable[0x4AF9] = CAST_OP(0x4AF9); \ + JumpTable[0x4ADF] = CAST_OP(0x4ADF); \ + JumpTable[0x4AE7] = CAST_OP(0x4AE7); \ + JumpTable[0x4AFC] = CAST_OP(0x4AFC); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4C90 + i] = CAST_OP(0x4C90); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4C98 + i] = CAST_OP(0x4C98); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4CA8 + i] = CAST_OP(0x4CA8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4CB0 + i] = CAST_OP(0x4CB0); \ + JumpTable[0x4CB8] = CAST_OP(0x4CB8); \ + JumpTable[0x4CB9] = CAST_OP(0x4CB9); \ + JumpTable[0x4CBA] = CAST_OP(0x4CBA); \ + JumpTable[0x4CBB] = CAST_OP(0x4CBB); \ + JumpTable[0x4C9F] = CAST_OP(0x4C9F); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4CD0 + i] = CAST_OP(0x4CD0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x4CD8 + i] = CAST_OP(0x4CD8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4CE8 + i] = CAST_OP(0x4CE8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4CF0 + i] = CAST_OP(0x4CF0); \ + JumpTable[0x4CF8] = CAST_OP(0x4CF8); \ + JumpTable[0x4CF9] = CAST_OP(0x4CF9); \ + JumpTable[0x4CFA] = CAST_OP(0x4CFA); \ + JumpTable[0x4CFB] = CAST_OP(0x4CFB); \ + JumpTable[0x4CDF] = CAST_OP(0x4CDF); \ + for(i = 0x0000; i <= 0x000F; i += 0x0001) \ + JumpTable[0x4E40 + i] = CAST_OP(0x4E40); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4E50 + i] = CAST_OP(0x4E50); \ + JumpTable[0x4E57] = CAST_OP(0x4E57); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4E58 + i] = CAST_OP(0x4E58); \ + JumpTable[0x4E5F] = CAST_OP(0x4E5F); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4E60 + i] = CAST_OP(0x4E60); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4E68 + i] = CAST_OP(0x4E68); \ + JumpTable[0x4E70] = CAST_OP(0x4E70); \ + JumpTable[0x4E71] = CAST_OP(0x4E71); \ + JumpTable[0x4E72] = CAST_OP(0x4E72); \ + JumpTable[0x4E73] = CAST_OP(0x4E73); \ + JumpTable[0x4E75] = CAST_OP(0x4E75); \ + JumpTable[0x4E76] = CAST_OP(0x4E76); \ + JumpTable[0x4E77] = CAST_OP(0x4E77); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4E90 + i] = CAST_OP(0x4E90); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4EA8 + i] = CAST_OP(0x4EA8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4EB0 + i] = CAST_OP(0x4EB0); \ + JumpTable[0x4EB8] = CAST_OP(0x4EB8); \ + JumpTable[0x4EB9] = CAST_OP(0x4EB9); \ + JumpTable[0x4EBA] = CAST_OP(0x4EBA); \ + JumpTable[0x4EBB] = CAST_OP(0x4EBB); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4ED0 + i] = CAST_OP(0x4ED0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4EE8 + i] = CAST_OP(0x4EE8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x4EF0 + i] = CAST_OP(0x4EF0); \ + JumpTable[0x4EF8] = CAST_OP(0x4EF8); \ + JumpTable[0x4EF9] = CAST_OP(0x4EF9); \ + JumpTable[0x4EFA] = CAST_OP(0x4EFA); \ + JumpTable[0x4EFB] = CAST_OP(0x4EFB); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x4180 + i + j] = CAST_OP(0x4180); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x4190 + i + j] = CAST_OP(0x4190); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x4198 + i + j] = CAST_OP(0x4198); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x41A0 + i + j] = CAST_OP(0x41A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x41A8 + i + j] = CAST_OP(0x41A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x41B0 + i + j] = CAST_OP(0x41B0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x41B8 + i] = CAST_OP(0x41B8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x41B9 + i] = CAST_OP(0x41B9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x41BA + i] = CAST_OP(0x41BA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x41BB + i] = CAST_OP(0x41BB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x41BC + i] = CAST_OP(0x41BC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x419F + i] = CAST_OP(0x419F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x41A7 + i] = CAST_OP(0x41A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x41D0 + i + j] = CAST_OP(0x41D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x41E8 + i + j] = CAST_OP(0x41E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x41F0 + i + j] = CAST_OP(0x41F0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x41F8 + i] = CAST_OP(0x41F8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x41F9 + i] = CAST_OP(0x41F9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x41FA + i] = CAST_OP(0x41FA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x41FB + i] = CAST_OP(0x41FB); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x50C0 + i] = CAST_OP(0x50C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x51C0 + i] = CAST_OP(0x51C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x52C0 + i] = CAST_OP(0x52C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x53C0 + i] = CAST_OP(0x53C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x54C0 + i] = CAST_OP(0x54C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x55C0 + i] = CAST_OP(0x55C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x56C0 + i] = CAST_OP(0x56C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x57C0 + i] = CAST_OP(0x57C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x58C0 + i] = CAST_OP(0x58C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x59C0 + i] = CAST_OP(0x59C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5AC0 + i] = CAST_OP(0x5AC0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5BC0 + i] = CAST_OP(0x5BC0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5CC0 + i] = CAST_OP(0x5CC0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5DC0 + i] = CAST_OP(0x5DC0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5EC0 + i] = CAST_OP(0x5EC0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5FC0 + i] = CAST_OP(0x5FC0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x50D0 + i] = CAST_OP(0x50D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x51D0 + i] = CAST_OP(0x51D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x52D0 + i] = CAST_OP(0x52D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x53D0 + i] = CAST_OP(0x53D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x54D0 + i] = CAST_OP(0x54D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x55D0 + i] = CAST_OP(0x55D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x56D0 + i] = CAST_OP(0x56D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x57D0 + i] = CAST_OP(0x57D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x58D0 + i] = CAST_OP(0x58D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x59D0 + i] = CAST_OP(0x59D0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5AD0 + i] = CAST_OP(0x5AD0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5BD0 + i] = CAST_OP(0x5BD0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5CD0 + i] = CAST_OP(0x5CD0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5DD0 + i] = CAST_OP(0x5DD0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5ED0 + i] = CAST_OP(0x5ED0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5FD0 + i] = CAST_OP(0x5FD0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x50D8 + i] = CAST_OP(0x50D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x51D8 + i] = CAST_OP(0x51D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x52D8 + i] = CAST_OP(0x52D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x53D8 + i] = CAST_OP(0x53D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x54D8 + i] = CAST_OP(0x54D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x55D8 + i] = CAST_OP(0x55D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x56D8 + i] = CAST_OP(0x56D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x57D8 + i] = CAST_OP(0x57D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x58D8 + i] = CAST_OP(0x58D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x59D8 + i] = CAST_OP(0x59D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x5AD8 + i] = CAST_OP(0x5AD8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x5BD8 + i] = CAST_OP(0x5BD8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x5CD8 + i] = CAST_OP(0x5CD8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x5DD8 + i] = CAST_OP(0x5DD8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x5ED8 + i] = CAST_OP(0x5ED8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x5FD8 + i] = CAST_OP(0x5FD8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x50E0 + i] = CAST_OP(0x50E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x51E0 + i] = CAST_OP(0x51E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x52E0 + i] = CAST_OP(0x52E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x53E0 + i] = CAST_OP(0x53E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x54E0 + i] = CAST_OP(0x54E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x55E0 + i] = CAST_OP(0x55E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x56E0 + i] = CAST_OP(0x56E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x57E0 + i] = CAST_OP(0x57E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x58E0 + i] = CAST_OP(0x58E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x59E0 + i] = CAST_OP(0x59E0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x5AE0 + i] = CAST_OP(0x5AE0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x5BE0 + i] = CAST_OP(0x5BE0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x5CE0 + i] = CAST_OP(0x5CE0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x5DE0 + i] = CAST_OP(0x5DE0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x5EE0 + i] = CAST_OP(0x5EE0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x5FE0 + i] = CAST_OP(0x5FE0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x50E8 + i] = CAST_OP(0x50E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x51E8 + i] = CAST_OP(0x51E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x52E8 + i] = CAST_OP(0x52E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x53E8 + i] = CAST_OP(0x53E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x54E8 + i] = CAST_OP(0x54E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x55E8 + i] = CAST_OP(0x55E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x56E8 + i] = CAST_OP(0x56E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x57E8 + i] = CAST_OP(0x57E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x58E8 + i] = CAST_OP(0x58E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x59E8 + i] = CAST_OP(0x59E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5AE8 + i] = CAST_OP(0x5AE8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5BE8 + i] = CAST_OP(0x5BE8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5CE8 + i] = CAST_OP(0x5CE8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5DE8 + i] = CAST_OP(0x5DE8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5EE8 + i] = CAST_OP(0x5EE8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5FE8 + i] = CAST_OP(0x5FE8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x50F0 + i] = CAST_OP(0x50F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x51F0 + i] = CAST_OP(0x51F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x52F0 + i] = CAST_OP(0x52F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x53F0 + i] = CAST_OP(0x53F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x54F0 + i] = CAST_OP(0x54F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x55F0 + i] = CAST_OP(0x55F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x56F0 + i] = CAST_OP(0x56F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x57F0 + i] = CAST_OP(0x57F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x58F0 + i] = CAST_OP(0x58F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x59F0 + i] = CAST_OP(0x59F0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5AF0 + i] = CAST_OP(0x5AF0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5BF0 + i] = CAST_OP(0x5BF0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5CF0 + i] = CAST_OP(0x5CF0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5DF0 + i] = CAST_OP(0x5DF0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5EF0 + i] = CAST_OP(0x5EF0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5FF0 + i] = CAST_OP(0x5FF0); \ + JumpTable[0x50F8] = CAST_OP(0x50F8); \ + JumpTable[0x51F8] = CAST_OP(0x51F8); \ + JumpTable[0x52F8] = CAST_OP(0x52F8); \ + JumpTable[0x53F8] = CAST_OP(0x53F8); \ + JumpTable[0x54F8] = CAST_OP(0x54F8); \ + JumpTable[0x55F8] = CAST_OP(0x55F8); \ + JumpTable[0x56F8] = CAST_OP(0x56F8); \ + JumpTable[0x57F8] = CAST_OP(0x57F8); \ + JumpTable[0x58F8] = CAST_OP(0x58F8); \ + JumpTable[0x59F8] = CAST_OP(0x59F8); \ + JumpTable[0x5AF8] = CAST_OP(0x5AF8); \ + JumpTable[0x5BF8] = CAST_OP(0x5BF8); \ + JumpTable[0x5CF8] = CAST_OP(0x5CF8); \ + JumpTable[0x5DF8] = CAST_OP(0x5DF8); \ + JumpTable[0x5EF8] = CAST_OP(0x5EF8); \ + JumpTable[0x5FF8] = CAST_OP(0x5FF8); \ + JumpTable[0x50F9] = CAST_OP(0x50F9); \ + JumpTable[0x51F9] = CAST_OP(0x51F9); \ + JumpTable[0x52F9] = CAST_OP(0x52F9); \ + JumpTable[0x53F9] = CAST_OP(0x53F9); \ + JumpTable[0x54F9] = CAST_OP(0x54F9); \ + JumpTable[0x55F9] = CAST_OP(0x55F9); \ + JumpTable[0x56F9] = CAST_OP(0x56F9); \ + JumpTable[0x57F9] = CAST_OP(0x57F9); \ + JumpTable[0x58F9] = CAST_OP(0x58F9); \ + JumpTable[0x59F9] = CAST_OP(0x59F9); \ + JumpTable[0x5AF9] = CAST_OP(0x5AF9); \ + JumpTable[0x5BF9] = CAST_OP(0x5BF9); \ + JumpTable[0x5CF9] = CAST_OP(0x5CF9); \ + JumpTable[0x5DF9] = CAST_OP(0x5DF9); \ + JumpTable[0x5EF9] = CAST_OP(0x5EF9); \ + JumpTable[0x5FF9] = CAST_OP(0x5FF9); \ + JumpTable[0x50DF] = CAST_OP(0x50DF); \ + JumpTable[0x51DF] = CAST_OP(0x51DF); \ + JumpTable[0x52DF] = CAST_OP(0x52DF); \ + JumpTable[0x53DF] = CAST_OP(0x53DF); \ + JumpTable[0x54DF] = CAST_OP(0x54DF); \ + JumpTable[0x55DF] = CAST_OP(0x55DF); \ + JumpTable[0x56DF] = CAST_OP(0x56DF); \ + JumpTable[0x57DF] = CAST_OP(0x57DF); \ + JumpTable[0x58DF] = CAST_OP(0x58DF); \ + JumpTable[0x59DF] = CAST_OP(0x59DF); \ + JumpTable[0x5ADF] = CAST_OP(0x5ADF); \ + JumpTable[0x5BDF] = CAST_OP(0x5BDF); \ + JumpTable[0x5CDF] = CAST_OP(0x5CDF); \ + JumpTable[0x5DDF] = CAST_OP(0x5DDF); \ + JumpTable[0x5EDF] = CAST_OP(0x5EDF); \ + JumpTable[0x5FDF] = CAST_OP(0x5FDF); \ + JumpTable[0x50E7] = CAST_OP(0x50E7); \ + JumpTable[0x51E7] = CAST_OP(0x51E7); \ + JumpTable[0x52E7] = CAST_OP(0x52E7); \ + JumpTable[0x53E7] = CAST_OP(0x53E7); \ + JumpTable[0x54E7] = CAST_OP(0x54E7); \ + JumpTable[0x55E7] = CAST_OP(0x55E7); \ + JumpTable[0x56E7] = CAST_OP(0x56E7); \ + JumpTable[0x57E7] = CAST_OP(0x57E7); \ + JumpTable[0x58E7] = CAST_OP(0x58E7); \ + JumpTable[0x59E7] = CAST_OP(0x59E7); \ + JumpTable[0x5AE7] = CAST_OP(0x5AE7); \ + JumpTable[0x5BE7] = CAST_OP(0x5BE7); \ + JumpTable[0x5CE7] = CAST_OP(0x5CE7); \ + JumpTable[0x5DE7] = CAST_OP(0x5DE7); \ + JumpTable[0x5EE7] = CAST_OP(0x5EE7); \ + JumpTable[0x5FE7] = CAST_OP(0x5FE7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x50C8 + i] = CAST_OP(0x50C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x51C8 + i] = CAST_OP(0x51C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x52C8 + i] = CAST_OP(0x52C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x53C8 + i] = CAST_OP(0x53C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x54C8 + i] = CAST_OP(0x54C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x55C8 + i] = CAST_OP(0x55C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x56C8 + i] = CAST_OP(0x56C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x57C8 + i] = CAST_OP(0x57C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x58C8 + i] = CAST_OP(0x58C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x59C8 + i] = CAST_OP(0x59C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5AC8 + i] = CAST_OP(0x5AC8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5BC8 + i] = CAST_OP(0x5BC8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5CC8 + i] = CAST_OP(0x5CC8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5DC8 + i] = CAST_OP(0x5DC8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5EC8 + i] = CAST_OP(0x5EC8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0x5FC8 + i] = CAST_OP(0x5FC8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5000 + i + j] = CAST_OP(0x5000); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5010 + i + j] = CAST_OP(0x5010); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5018 + i + j] = CAST_OP(0x5018); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5020 + i + j] = CAST_OP(0x5020); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5028 + i + j] = CAST_OP(0x5028); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5030 + i + j] = CAST_OP(0x5030); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x5038 + i] = CAST_OP(0x5038); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x5039 + i] = CAST_OP(0x5039); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x501F + i] = CAST_OP(0x501F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x5027 + i] = CAST_OP(0x5027); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5040 + i + j] = CAST_OP(0x5040); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5048 + i + j] = CAST_OP(0x5048); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5050 + i + j] = CAST_OP(0x5050); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5058 + i + j] = CAST_OP(0x5058); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5060 + i + j] = CAST_OP(0x5060); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5068 + i + j] = CAST_OP(0x5068); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5070 + i + j] = CAST_OP(0x5070); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x5078 + i] = CAST_OP(0x5078); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x5079 + i] = CAST_OP(0x5079); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x505F + i] = CAST_OP(0x505F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x5067 + i] = CAST_OP(0x5067); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5080 + i + j] = CAST_OP(0x5080); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5088 + i + j] = CAST_OP(0x5088); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5090 + i + j] = CAST_OP(0x5090); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5098 + i + j] = CAST_OP(0x5098); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x50A0 + i + j] = CAST_OP(0x50A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x50A8 + i + j] = CAST_OP(0x50A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x50B0 + i + j] = CAST_OP(0x50B0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x50B8 + i] = CAST_OP(0x50B8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x50B9 + i] = CAST_OP(0x50B9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x509F + i] = CAST_OP(0x509F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x50A7 + i] = CAST_OP(0x50A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5100 + i + j] = CAST_OP(0x5100); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5110 + i + j] = CAST_OP(0x5110); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5118 + i + j] = CAST_OP(0x5118); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5120 + i + j] = CAST_OP(0x5120); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5128 + i + j] = CAST_OP(0x5128); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5130 + i + j] = CAST_OP(0x5130); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x5138 + i] = CAST_OP(0x5138); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x5139 + i] = CAST_OP(0x5139); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x511F + i] = CAST_OP(0x511F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x5127 + i] = CAST_OP(0x5127); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5140 + i + j] = CAST_OP(0x5140); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5148 + i + j] = CAST_OP(0x5148); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5150 + i + j] = CAST_OP(0x5150); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5158 + i + j] = CAST_OP(0x5158); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5160 + i + j] = CAST_OP(0x5160); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5168 + i + j] = CAST_OP(0x5168); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5170 + i + j] = CAST_OP(0x5170); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x5178 + i] = CAST_OP(0x5178); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x5179 + i] = CAST_OP(0x5179); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x515F + i] = CAST_OP(0x515F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x5167 + i] = CAST_OP(0x5167); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5180 + i + j] = CAST_OP(0x5180); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5188 + i + j] = CAST_OP(0x5188); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5190 + i + j] = CAST_OP(0x5190); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x5198 + i + j] = CAST_OP(0x5198); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x51A0 + i + j] = CAST_OP(0x51A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x51A8 + i + j] = CAST_OP(0x51A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x51B0 + i + j] = CAST_OP(0x51B0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x51B8 + i] = CAST_OP(0x51B8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x51B9 + i] = CAST_OP(0x51B9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x519F + i] = CAST_OP(0x519F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x51A7 + i] = CAST_OP(0x51A7); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6200 + i] = CAST_OP(0x6201); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6300 + i] = CAST_OP(0x6301); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6400 + i] = CAST_OP(0x6401); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6500 + i] = CAST_OP(0x6501); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6600 + i] = CAST_OP(0x6601); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6700 + i] = CAST_OP(0x6701); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6800 + i] = CAST_OP(0x6801); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6900 + i] = CAST_OP(0x6901); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6A00 + i] = CAST_OP(0x6A01); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6B00 + i] = CAST_OP(0x6B01); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6C00 + i] = CAST_OP(0x6C01); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6D00 + i] = CAST_OP(0x6D01); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6E00 + i] = CAST_OP(0x6E01); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6F00 + i] = CAST_OP(0x6F01); \ + JumpTable[0x6200] = CAST_OP(0x6200); \ + JumpTable[0x6300] = CAST_OP(0x6300); \ + JumpTable[0x6400] = CAST_OP(0x6400); \ + JumpTable[0x6500] = CAST_OP(0x6500); \ + JumpTable[0x6600] = CAST_OP(0x6600); \ + JumpTable[0x6700] = CAST_OP(0x6700); \ + JumpTable[0x6800] = CAST_OP(0x6800); \ + JumpTable[0x6900] = CAST_OP(0x6900); \ + JumpTable[0x6A00] = CAST_OP(0x6A00); \ + JumpTable[0x6B00] = CAST_OP(0x6B00); \ + JumpTable[0x6C00] = CAST_OP(0x6C00); \ + JumpTable[0x6D00] = CAST_OP(0x6D00); \ + JumpTable[0x6E00] = CAST_OP(0x6E00); \ + JumpTable[0x6F00] = CAST_OP(0x6F00); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6000 + i] = CAST_OP(0x6001); \ + JumpTable[0x6000] = CAST_OP(0x6000); \ + for(i = 0x0001; i <= 0x00FF; i += 0x0001) \ + JumpTable[0x6100 + i] = CAST_OP(0x6101); \ + JumpTable[0x6100] = CAST_OP(0x6100); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + for(j = 0x0000; j <= 0x00FF; j += 0x0001) \ + JumpTable[0x7000 + i + j] = CAST_OP(0x7000); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8000 + i + j] = CAST_OP(0x8000); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8010 + i + j] = CAST_OP(0x8010); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8018 + i + j] = CAST_OP(0x8018); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8020 + i + j] = CAST_OP(0x8020); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8028 + i + j] = CAST_OP(0x8028); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8030 + i + j] = CAST_OP(0x8030); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x8038 + i] = CAST_OP(0x8038); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x8039 + i] = CAST_OP(0x8039); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x803A + i] = CAST_OP(0x803A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x803B + i] = CAST_OP(0x803B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x803C + i] = CAST_OP(0x803C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x801F + i] = CAST_OP(0x801F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x8027 + i] = CAST_OP(0x8027); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8040 + i + j] = CAST_OP(0x8040); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8050 + i + j] = CAST_OP(0x8050); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8058 + i + j] = CAST_OP(0x8058); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8060 + i + j] = CAST_OP(0x8060); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8068 + i + j] = CAST_OP(0x8068); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8070 + i + j] = CAST_OP(0x8070); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x8078 + i] = CAST_OP(0x8078); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x8079 + i] = CAST_OP(0x8079); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x807A + i] = CAST_OP(0x807A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x807B + i] = CAST_OP(0x807B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x807C + i] = CAST_OP(0x807C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x805F + i] = CAST_OP(0x805F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x8067 + i] = CAST_OP(0x8067); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8080 + i + j] = CAST_OP(0x8080); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8090 + i + j] = CAST_OP(0x8090); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8098 + i + j] = CAST_OP(0x8098); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x80A0 + i + j] = CAST_OP(0x80A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x80A8 + i + j] = CAST_OP(0x80A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x80B0 + i + j] = CAST_OP(0x80B0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x80B8 + i] = CAST_OP(0x80B8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x80B9 + i] = CAST_OP(0x80B9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x80BA + i] = CAST_OP(0x80BA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x80BB + i] = CAST_OP(0x80BB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x80BC + i] = CAST_OP(0x80BC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x809F + i] = CAST_OP(0x809F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x80A7 + i] = CAST_OP(0x80A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8110 + i + j] = CAST_OP(0x8110); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8118 + i + j] = CAST_OP(0x8118); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8120 + i + j] = CAST_OP(0x8120); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8128 + i + j] = CAST_OP(0x8128); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8130 + i + j] = CAST_OP(0x8130); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x8138 + i] = CAST_OP(0x8138); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x8139 + i] = CAST_OP(0x8139); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x811F + i] = CAST_OP(0x811F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x8127 + i] = CAST_OP(0x8127); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8150 + i + j] = CAST_OP(0x8150); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8158 + i + j] = CAST_OP(0x8158); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8160 + i + j] = CAST_OP(0x8160); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8168 + i + j] = CAST_OP(0x8168); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8170 + i + j] = CAST_OP(0x8170); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x8178 + i] = CAST_OP(0x8178); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x8179 + i] = CAST_OP(0x8179); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x815F + i] = CAST_OP(0x815F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x8167 + i] = CAST_OP(0x8167); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8190 + i + j] = CAST_OP(0x8190); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8198 + i + j] = CAST_OP(0x8198); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x81A0 + i + j] = CAST_OP(0x81A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x81A8 + i + j] = CAST_OP(0x81A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x81B0 + i + j] = CAST_OP(0x81B0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x81B8 + i] = CAST_OP(0x81B8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x81B9 + i] = CAST_OP(0x81B9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x819F + i] = CAST_OP(0x819F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x81A7 + i] = CAST_OP(0x81A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x8100 + i + j] = CAST_OP(0x8100); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x8108 + i + j] = CAST_OP(0x8108); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x810F + i] = CAST_OP(0x810F); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x8F08 + i] = CAST_OP(0x8F08); \ + JumpTable[0x8F0F] = CAST_OP(0x8F0F); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x80C0 + i + j] = CAST_OP(0x80C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x80D0 + i + j] = CAST_OP(0x80D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x80D8 + i + j] = CAST_OP(0x80D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x80E0 + i + j] = CAST_OP(0x80E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x80E8 + i + j] = CAST_OP(0x80E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x80F0 + i + j] = CAST_OP(0x80F0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x80F8 + i] = CAST_OP(0x80F8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x80F9 + i] = CAST_OP(0x80F9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x80FA + i] = CAST_OP(0x80FA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x80FB + i] = CAST_OP(0x80FB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x80FC + i] = CAST_OP(0x80FC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x80DF + i] = CAST_OP(0x80DF); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x80E7 + i] = CAST_OP(0x80E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x81C0 + i + j] = CAST_OP(0x81C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x81D0 + i + j] = CAST_OP(0x81D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x81D8 + i + j] = CAST_OP(0x81D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x81E0 + i + j] = CAST_OP(0x81E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x81E8 + i + j] = CAST_OP(0x81E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x81F0 + i + j] = CAST_OP(0x81F0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x81F8 + i] = CAST_OP(0x81F8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x81F9 + i] = CAST_OP(0x81F9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x81FA + i] = CAST_OP(0x81FA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x81FB + i] = CAST_OP(0x81FB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x81FC + i] = CAST_OP(0x81FC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x81DF + i] = CAST_OP(0x81DF); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x81E7 + i] = CAST_OP(0x81E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9000 + i + j] = CAST_OP(0x9000); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9008 + i + j] = CAST_OP(0x9008); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9010 + i + j] = CAST_OP(0x9010); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9018 + i + j] = CAST_OP(0x9018); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9020 + i + j] = CAST_OP(0x9020); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9028 + i + j] = CAST_OP(0x9028); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9030 + i + j] = CAST_OP(0x9030); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x9038 + i] = CAST_OP(0x9038); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x9039 + i] = CAST_OP(0x9039); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x903A + i] = CAST_OP(0x903A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x903B + i] = CAST_OP(0x903B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x903C + i] = CAST_OP(0x903C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x901F + i] = CAST_OP(0x901F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x9027 + i] = CAST_OP(0x9027); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9040 + i + j] = CAST_OP(0x9040); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9048 + i + j] = CAST_OP(0x9048); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9050 + i + j] = CAST_OP(0x9050); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9058 + i + j] = CAST_OP(0x9058); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9060 + i + j] = CAST_OP(0x9060); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9068 + i + j] = CAST_OP(0x9068); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9070 + i + j] = CAST_OP(0x9070); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x9078 + i] = CAST_OP(0x9078); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x9079 + i] = CAST_OP(0x9079); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x907A + i] = CAST_OP(0x907A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x907B + i] = CAST_OP(0x907B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x907C + i] = CAST_OP(0x907C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x905F + i] = CAST_OP(0x905F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x9067 + i] = CAST_OP(0x9067); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9080 + i + j] = CAST_OP(0x9080); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9088 + i + j] = CAST_OP(0x9088); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9090 + i + j] = CAST_OP(0x9090); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9098 + i + j] = CAST_OP(0x9098); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x90A0 + i + j] = CAST_OP(0x90A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x90A8 + i + j] = CAST_OP(0x90A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x90B0 + i + j] = CAST_OP(0x90B0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x90B8 + i] = CAST_OP(0x90B8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x90B9 + i] = CAST_OP(0x90B9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x90BA + i] = CAST_OP(0x90BA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x90BB + i] = CAST_OP(0x90BB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x90BC + i] = CAST_OP(0x90BC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x909F + i] = CAST_OP(0x909F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x90A7 + i] = CAST_OP(0x90A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9110 + i + j] = CAST_OP(0x9110); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9118 + i + j] = CAST_OP(0x9118); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9120 + i + j] = CAST_OP(0x9120); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9128 + i + j] = CAST_OP(0x9128); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9130 + i + j] = CAST_OP(0x9130); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x9138 + i] = CAST_OP(0x9138); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x9139 + i] = CAST_OP(0x9139); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x911F + i] = CAST_OP(0x911F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x9127 + i] = CAST_OP(0x9127); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9150 + i + j] = CAST_OP(0x9150); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9158 + i + j] = CAST_OP(0x9158); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9160 + i + j] = CAST_OP(0x9160); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9168 + i + j] = CAST_OP(0x9168); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9170 + i + j] = CAST_OP(0x9170); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x9178 + i] = CAST_OP(0x9178); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x9179 + i] = CAST_OP(0x9179); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x915F + i] = CAST_OP(0x915F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x9167 + i] = CAST_OP(0x9167); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9190 + i + j] = CAST_OP(0x9190); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9198 + i + j] = CAST_OP(0x9198); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x91A0 + i + j] = CAST_OP(0x91A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x91A8 + i + j] = CAST_OP(0x91A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x91B0 + i + j] = CAST_OP(0x91B0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x91B8 + i] = CAST_OP(0x91B8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x91B9 + i] = CAST_OP(0x91B9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x919F + i] = CAST_OP(0x919F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x91A7 + i] = CAST_OP(0x91A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9100 + i + j] = CAST_OP(0x9100); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9140 + i + j] = CAST_OP(0x9140); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x9180 + i + j] = CAST_OP(0x9180); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x9108 + i + j] = CAST_OP(0x9108); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x9148 + i + j] = CAST_OP(0x9148); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0x9188 + i + j] = CAST_OP(0x9188); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x910F + i] = CAST_OP(0x910F); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x914F + i] = CAST_OP(0x914F); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0x918F + i] = CAST_OP(0x918F); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x9F08 + i] = CAST_OP(0x9F08); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x9F48 + i] = CAST_OP(0x9F48); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0x9F88 + i] = CAST_OP(0x9F88); \ + JumpTable[0x9F0F] = CAST_OP(0x9F0F); \ + JumpTable[0x9F4F] = CAST_OP(0x9F4F); \ + JumpTable[0x9F8F] = CAST_OP(0x9F8F); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x90C0 + i + j] = CAST_OP(0x90C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x90C8 + i + j] = CAST_OP(0x90C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x90D0 + i + j] = CAST_OP(0x90D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x90D8 + i + j] = CAST_OP(0x90D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x90E0 + i + j] = CAST_OP(0x90E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x90E8 + i + j] = CAST_OP(0x90E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x90F0 + i + j] = CAST_OP(0x90F0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x90F8 + i] = CAST_OP(0x90F8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x90F9 + i] = CAST_OP(0x90F9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x90FA + i] = CAST_OP(0x90FA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x90FB + i] = CAST_OP(0x90FB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x90FC + i] = CAST_OP(0x90FC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x90DF + i] = CAST_OP(0x90DF); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x90E7 + i] = CAST_OP(0x90E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x91C0 + i + j] = CAST_OP(0x91C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x91C8 + i + j] = CAST_OP(0x91C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x91D0 + i + j] = CAST_OP(0x91D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x91D8 + i + j] = CAST_OP(0x91D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x91E0 + i + j] = CAST_OP(0x91E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x91E8 + i + j] = CAST_OP(0x91E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0x91F0 + i + j] = CAST_OP(0x91F0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x91F8 + i] = CAST_OP(0x91F8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x91F9 + i] = CAST_OP(0x91F9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x91FA + i] = CAST_OP(0x91FA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x91FB + i] = CAST_OP(0x91FB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x91FC + i] = CAST_OP(0x91FC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x91DF + i] = CAST_OP(0x91DF); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0x91E7 + i] = CAST_OP(0x91E7); \ + for(i = 0x0000; i <= 0x0FFF; i += 0x0001) \ + JumpTable[0xA000 + i] = CAST_OP(0xA000); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB000 + i + j] = CAST_OP(0xB000); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB008 + i + j] = CAST_OP(0xB008); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB010 + i + j] = CAST_OP(0xB010); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB018 + i + j] = CAST_OP(0xB018); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB020 + i + j] = CAST_OP(0xB020); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB028 + i + j] = CAST_OP(0xB028); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB030 + i + j] = CAST_OP(0xB030); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB038 + i] = CAST_OP(0xB038); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB039 + i] = CAST_OP(0xB039); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB03A + i] = CAST_OP(0xB03A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB03B + i] = CAST_OP(0xB03B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB03C + i] = CAST_OP(0xB03C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB01F + i] = CAST_OP(0xB01F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB027 + i] = CAST_OP(0xB027); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB040 + i + j] = CAST_OP(0xB040); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB048 + i + j] = CAST_OP(0xB048); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB050 + i + j] = CAST_OP(0xB050); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB058 + i + j] = CAST_OP(0xB058); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB060 + i + j] = CAST_OP(0xB060); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB068 + i + j] = CAST_OP(0xB068); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB070 + i + j] = CAST_OP(0xB070); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB078 + i] = CAST_OP(0xB078); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB079 + i] = CAST_OP(0xB079); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB07A + i] = CAST_OP(0xB07A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB07B + i] = CAST_OP(0xB07B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB07C + i] = CAST_OP(0xB07C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB05F + i] = CAST_OP(0xB05F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB067 + i] = CAST_OP(0xB067); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB080 + i + j] = CAST_OP(0xB080); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB088 + i + j] = CAST_OP(0xB088); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB090 + i + j] = CAST_OP(0xB090); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB098 + i + j] = CAST_OP(0xB098); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB0A0 + i + j] = CAST_OP(0xB0A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB0A8 + i + j] = CAST_OP(0xB0A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB0B0 + i + j] = CAST_OP(0xB0B0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB0B8 + i] = CAST_OP(0xB0B8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB0B9 + i] = CAST_OP(0xB0B9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB0BA + i] = CAST_OP(0xB0BA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB0BB + i] = CAST_OP(0xB0BB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB0BC + i] = CAST_OP(0xB0BC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB09F + i] = CAST_OP(0xB09F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB0A7 + i] = CAST_OP(0xB0A7); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0xB108 + i + j] = CAST_OP(0xB108); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0xB148 + i + j] = CAST_OP(0xB148); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0xB188 + i + j] = CAST_OP(0xB188); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0xB10F + i] = CAST_OP(0xB10F); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0xB14F + i] = CAST_OP(0xB14F); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0xB18F + i] = CAST_OP(0xB18F); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xBF08 + i] = CAST_OP(0xBF08); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xBF48 + i] = CAST_OP(0xBF48); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xBF88 + i] = CAST_OP(0xBF88); \ + JumpTable[0xBF0F] = CAST_OP(0xBF0F); \ + JumpTable[0xBF4F] = CAST_OP(0xBF4F); \ + JumpTable[0xBF8F] = CAST_OP(0xBF8F); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB100 + i + j] = CAST_OP(0xB100); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB110 + i + j] = CAST_OP(0xB110); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB118 + i + j] = CAST_OP(0xB118); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB120 + i + j] = CAST_OP(0xB120); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB128 + i + j] = CAST_OP(0xB128); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB130 + i + j] = CAST_OP(0xB130); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB138 + i] = CAST_OP(0xB138); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB139 + i] = CAST_OP(0xB139); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB11F + i] = CAST_OP(0xB11F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB127 + i] = CAST_OP(0xB127); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB140 + i + j] = CAST_OP(0xB140); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB150 + i + j] = CAST_OP(0xB150); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB158 + i + j] = CAST_OP(0xB158); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB160 + i + j] = CAST_OP(0xB160); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB168 + i + j] = CAST_OP(0xB168); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB170 + i + j] = CAST_OP(0xB170); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB178 + i] = CAST_OP(0xB178); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB179 + i] = CAST_OP(0xB179); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB15F + i] = CAST_OP(0xB15F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB167 + i] = CAST_OP(0xB167); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB180 + i + j] = CAST_OP(0xB180); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB190 + i + j] = CAST_OP(0xB190); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB198 + i + j] = CAST_OP(0xB198); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB1A0 + i + j] = CAST_OP(0xB1A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB1A8 + i + j] = CAST_OP(0xB1A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB1B0 + i + j] = CAST_OP(0xB1B0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB1B8 + i] = CAST_OP(0xB1B8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB1B9 + i] = CAST_OP(0xB1B9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB19F + i] = CAST_OP(0xB19F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB1A7 + i] = CAST_OP(0xB1A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB0C0 + i + j] = CAST_OP(0xB0C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB0C8 + i + j] = CAST_OP(0xB0C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB0D0 + i + j] = CAST_OP(0xB0D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB0D8 + i + j] = CAST_OP(0xB0D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB0E0 + i + j] = CAST_OP(0xB0E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB0E8 + i + j] = CAST_OP(0xB0E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB0F0 + i + j] = CAST_OP(0xB0F0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB0F8 + i] = CAST_OP(0xB0F8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB0F9 + i] = CAST_OP(0xB0F9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB0FA + i] = CAST_OP(0xB0FA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB0FB + i] = CAST_OP(0xB0FB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB0FC + i] = CAST_OP(0xB0FC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB0DF + i] = CAST_OP(0xB0DF); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB0E7 + i] = CAST_OP(0xB0E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB1C0 + i + j] = CAST_OP(0xB1C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB1C8 + i + j] = CAST_OP(0xB1C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB1D0 + i + j] = CAST_OP(0xB1D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB1D8 + i + j] = CAST_OP(0xB1D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB1E0 + i + j] = CAST_OP(0xB1E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB1E8 + i + j] = CAST_OP(0xB1E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xB1F0 + i + j] = CAST_OP(0xB1F0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB1F8 + i] = CAST_OP(0xB1F8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB1F9 + i] = CAST_OP(0xB1F9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB1FA + i] = CAST_OP(0xB1FA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB1FB + i] = CAST_OP(0xB1FB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB1FC + i] = CAST_OP(0xB1FC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB1DF + i] = CAST_OP(0xB1DF); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xB1E7 + i] = CAST_OP(0xB1E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC000 + i + j] = CAST_OP(0xC000); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC010 + i + j] = CAST_OP(0xC010); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC018 + i + j] = CAST_OP(0xC018); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC020 + i + j] = CAST_OP(0xC020); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC028 + i + j] = CAST_OP(0xC028); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC030 + i + j] = CAST_OP(0xC030); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC038 + i] = CAST_OP(0xC038); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC039 + i] = CAST_OP(0xC039); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC03A + i] = CAST_OP(0xC03A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC03B + i] = CAST_OP(0xC03B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC03C + i] = CAST_OP(0xC03C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC01F + i] = CAST_OP(0xC01F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC027 + i] = CAST_OP(0xC027); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC040 + i + j] = CAST_OP(0xC040); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC050 + i + j] = CAST_OP(0xC050); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC058 + i + j] = CAST_OP(0xC058); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC060 + i + j] = CAST_OP(0xC060); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC068 + i + j] = CAST_OP(0xC068); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC070 + i + j] = CAST_OP(0xC070); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC078 + i] = CAST_OP(0xC078); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC079 + i] = CAST_OP(0xC079); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC07A + i] = CAST_OP(0xC07A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC07B + i] = CAST_OP(0xC07B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC07C + i] = CAST_OP(0xC07C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC05F + i] = CAST_OP(0xC05F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC067 + i] = CAST_OP(0xC067); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC080 + i + j] = CAST_OP(0xC080); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC090 + i + j] = CAST_OP(0xC090); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC098 + i + j] = CAST_OP(0xC098); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC0A0 + i + j] = CAST_OP(0xC0A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC0A8 + i + j] = CAST_OP(0xC0A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC0B0 + i + j] = CAST_OP(0xC0B0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC0B8 + i] = CAST_OP(0xC0B8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC0B9 + i] = CAST_OP(0xC0B9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC0BA + i] = CAST_OP(0xC0BA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC0BB + i] = CAST_OP(0xC0BB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC0BC + i] = CAST_OP(0xC0BC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC09F + i] = CAST_OP(0xC09F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC0A7 + i] = CAST_OP(0xC0A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC110 + i + j] = CAST_OP(0xC110); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC118 + i + j] = CAST_OP(0xC118); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC120 + i + j] = CAST_OP(0xC120); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC128 + i + j] = CAST_OP(0xC128); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC130 + i + j] = CAST_OP(0xC130); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC138 + i] = CAST_OP(0xC138); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC139 + i] = CAST_OP(0xC139); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC11F + i] = CAST_OP(0xC11F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC127 + i] = CAST_OP(0xC127); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC150 + i + j] = CAST_OP(0xC150); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC158 + i + j] = CAST_OP(0xC158); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC160 + i + j] = CAST_OP(0xC160); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC168 + i + j] = CAST_OP(0xC168); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC170 + i + j] = CAST_OP(0xC170); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC178 + i] = CAST_OP(0xC178); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC179 + i] = CAST_OP(0xC179); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC15F + i] = CAST_OP(0xC15F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC167 + i] = CAST_OP(0xC167); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC190 + i + j] = CAST_OP(0xC190); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC198 + i + j] = CAST_OP(0xC198); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC1A0 + i + j] = CAST_OP(0xC1A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC1A8 + i + j] = CAST_OP(0xC1A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC1B0 + i + j] = CAST_OP(0xC1B0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC1B8 + i] = CAST_OP(0xC1B8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC1B9 + i] = CAST_OP(0xC1B9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC19F + i] = CAST_OP(0xC19F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC1A7 + i] = CAST_OP(0xC1A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC100 + i + j] = CAST_OP(0xC100); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0xC108 + i + j] = CAST_OP(0xC108); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0xC10F + i] = CAST_OP(0xC10F); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xCF08 + i] = CAST_OP(0xCF08); \ + JumpTable[0xCF0F] = CAST_OP(0xCF0F); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC0C0 + i + j] = CAST_OP(0xC0C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC0D0 + i + j] = CAST_OP(0xC0D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC0D8 + i + j] = CAST_OP(0xC0D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC0E0 + i + j] = CAST_OP(0xC0E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC0E8 + i + j] = CAST_OP(0xC0E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC0F0 + i + j] = CAST_OP(0xC0F0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC0F8 + i] = CAST_OP(0xC0F8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC0F9 + i] = CAST_OP(0xC0F9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC0FA + i] = CAST_OP(0xC0FA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC0FB + i] = CAST_OP(0xC0FB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC0FC + i] = CAST_OP(0xC0FC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC0DF + i] = CAST_OP(0xC0DF); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC0E7 + i] = CAST_OP(0xC0E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC1C0 + i + j] = CAST_OP(0xC1C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC1D0 + i + j] = CAST_OP(0xC1D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC1D8 + i + j] = CAST_OP(0xC1D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC1E0 + i + j] = CAST_OP(0xC1E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC1E8 + i + j] = CAST_OP(0xC1E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC1F0 + i + j] = CAST_OP(0xC1F0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC1F8 + i] = CAST_OP(0xC1F8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC1F9 + i] = CAST_OP(0xC1F9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC1FA + i] = CAST_OP(0xC1FA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC1FB + i] = CAST_OP(0xC1FB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC1FC + i] = CAST_OP(0xC1FC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC1DF + i] = CAST_OP(0xC1DF); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xC1E7 + i] = CAST_OP(0xC1E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC140 + i + j] = CAST_OP(0xC140); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC148 + i + j] = CAST_OP(0xC148); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xC188 + i + j] = CAST_OP(0xC188); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD000 + i + j] = CAST_OP(0xD000); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD008 + i + j] = CAST_OP(0xD008); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD010 + i + j] = CAST_OP(0xD010); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD018 + i + j] = CAST_OP(0xD018); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD020 + i + j] = CAST_OP(0xD020); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD028 + i + j] = CAST_OP(0xD028); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD030 + i + j] = CAST_OP(0xD030); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD038 + i] = CAST_OP(0xD038); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD039 + i] = CAST_OP(0xD039); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD03A + i] = CAST_OP(0xD03A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD03B + i] = CAST_OP(0xD03B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD03C + i] = CAST_OP(0xD03C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD01F + i] = CAST_OP(0xD01F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD027 + i] = CAST_OP(0xD027); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD040 + i + j] = CAST_OP(0xD040); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD048 + i + j] = CAST_OP(0xD048); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD050 + i + j] = CAST_OP(0xD050); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD058 + i + j] = CAST_OP(0xD058); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD060 + i + j] = CAST_OP(0xD060); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD068 + i + j] = CAST_OP(0xD068); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD070 + i + j] = CAST_OP(0xD070); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD078 + i] = CAST_OP(0xD078); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD079 + i] = CAST_OP(0xD079); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD07A + i] = CAST_OP(0xD07A); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD07B + i] = CAST_OP(0xD07B); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD07C + i] = CAST_OP(0xD07C); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD05F + i] = CAST_OP(0xD05F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD067 + i] = CAST_OP(0xD067); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD080 + i + j] = CAST_OP(0xD080); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD088 + i + j] = CAST_OP(0xD088); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD090 + i + j] = CAST_OP(0xD090); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD098 + i + j] = CAST_OP(0xD098); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD0A0 + i + j] = CAST_OP(0xD0A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD0A8 + i + j] = CAST_OP(0xD0A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD0B0 + i + j] = CAST_OP(0xD0B0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD0B8 + i] = CAST_OP(0xD0B8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD0B9 + i] = CAST_OP(0xD0B9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD0BA + i] = CAST_OP(0xD0BA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD0BB + i] = CAST_OP(0xD0BB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD0BC + i] = CAST_OP(0xD0BC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD09F + i] = CAST_OP(0xD09F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD0A7 + i] = CAST_OP(0xD0A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD110 + i + j] = CAST_OP(0xD110); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD118 + i + j] = CAST_OP(0xD118); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD120 + i + j] = CAST_OP(0xD120); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD128 + i + j] = CAST_OP(0xD128); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD130 + i + j] = CAST_OP(0xD130); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD138 + i] = CAST_OP(0xD138); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD139 + i] = CAST_OP(0xD139); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD11F + i] = CAST_OP(0xD11F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD127 + i] = CAST_OP(0xD127); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD150 + i + j] = CAST_OP(0xD150); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD158 + i + j] = CAST_OP(0xD158); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD160 + i + j] = CAST_OP(0xD160); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD168 + i + j] = CAST_OP(0xD168); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD170 + i + j] = CAST_OP(0xD170); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD178 + i] = CAST_OP(0xD178); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD179 + i] = CAST_OP(0xD179); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD15F + i] = CAST_OP(0xD15F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD167 + i] = CAST_OP(0xD167); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD190 + i + j] = CAST_OP(0xD190); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD198 + i + j] = CAST_OP(0xD198); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD1A0 + i + j] = CAST_OP(0xD1A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD1A8 + i + j] = CAST_OP(0xD1A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD1B0 + i + j] = CAST_OP(0xD1B0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD1B8 + i] = CAST_OP(0xD1B8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD1B9 + i] = CAST_OP(0xD1B9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD19F + i] = CAST_OP(0xD19F); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD1A7 + i] = CAST_OP(0xD1A7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD100 + i + j] = CAST_OP(0xD100); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD140 + i + j] = CAST_OP(0xD140); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD180 + i + j] = CAST_OP(0xD180); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0xD108 + i + j] = CAST_OP(0xD108); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0xD148 + i + j] = CAST_OP(0xD148); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0C00; j += 0x0200) \ + JumpTable[0xD188 + i + j] = CAST_OP(0xD188); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0xD10F + i] = CAST_OP(0xD10F); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0xD14F + i] = CAST_OP(0xD14F); \ + for(i = 0x0000; i <= 0x0C00; i += 0x0200) \ + JumpTable[0xD18F + i] = CAST_OP(0xD18F); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xDF08 + i] = CAST_OP(0xDF08); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xDF48 + i] = CAST_OP(0xDF48); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xDF88 + i] = CAST_OP(0xDF88); \ + JumpTable[0xDF0F] = CAST_OP(0xDF0F); \ + JumpTable[0xDF4F] = CAST_OP(0xDF4F); \ + JumpTable[0xDF8F] = CAST_OP(0xDF8F); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD0C0 + i + j] = CAST_OP(0xD0C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD0C8 + i + j] = CAST_OP(0xD0C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD0D0 + i + j] = CAST_OP(0xD0D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD0D8 + i + j] = CAST_OP(0xD0D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD0E0 + i + j] = CAST_OP(0xD0E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD0E8 + i + j] = CAST_OP(0xD0E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD0F0 + i + j] = CAST_OP(0xD0F0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD0F8 + i] = CAST_OP(0xD0F8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD0F9 + i] = CAST_OP(0xD0F9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD0FA + i] = CAST_OP(0xD0FA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD0FB + i] = CAST_OP(0xD0FB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD0FC + i] = CAST_OP(0xD0FC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD0DF + i] = CAST_OP(0xD0DF); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD0E7 + i] = CAST_OP(0xD0E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD1C0 + i + j] = CAST_OP(0xD1C0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD1C8 + i + j] = CAST_OP(0xD1C8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD1D0 + i + j] = CAST_OP(0xD1D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD1D8 + i + j] = CAST_OP(0xD1D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD1E0 + i + j] = CAST_OP(0xD1E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD1E8 + i + j] = CAST_OP(0xD1E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xD1F0 + i + j] = CAST_OP(0xD1F0); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD1F8 + i] = CAST_OP(0xD1F8); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD1F9 + i] = CAST_OP(0xD1F9); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD1FA + i] = CAST_OP(0xD1FA); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD1FB + i] = CAST_OP(0xD1FB); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD1FC + i] = CAST_OP(0xD1FC); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD1DF + i] = CAST_OP(0xD1DF); \ + for(i = 0x0000; i <= 0x0E00; i += 0x0200) \ + JumpTable[0xD1E7 + i] = CAST_OP(0xD1E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE000 + i + j] = CAST_OP(0xE000); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE040 + i + j] = CAST_OP(0xE040); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE080 + i + j] = CAST_OP(0xE080); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE008 + i + j] = CAST_OP(0xE008); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE048 + i + j] = CAST_OP(0xE048); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE088 + i + j] = CAST_OP(0xE088); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE010 + i + j] = CAST_OP(0xE010); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE050 + i + j] = CAST_OP(0xE050); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE090 + i + j] = CAST_OP(0xE090); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE018 + i + j] = CAST_OP(0xE018); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE058 + i + j] = CAST_OP(0xE058); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE098 + i + j] = CAST_OP(0xE098); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE100 + i + j] = CAST_OP(0xE100); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE140 + i + j] = CAST_OP(0xE140); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE180 + i + j] = CAST_OP(0xE180); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE108 + i + j] = CAST_OP(0xE108); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE148 + i + j] = CAST_OP(0xE148); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE188 + i + j] = CAST_OP(0xE188); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE110 + i + j] = CAST_OP(0xE110); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE150 + i + j] = CAST_OP(0xE150); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE190 + i + j] = CAST_OP(0xE190); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE118 + i + j] = CAST_OP(0xE118); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE158 + i + j] = CAST_OP(0xE158); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE198 + i + j] = CAST_OP(0xE198); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE020 + i + j] = CAST_OP(0xE020); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE060 + i + j] = CAST_OP(0xE060); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE0A0 + i + j] = CAST_OP(0xE0A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE028 + i + j] = CAST_OP(0xE028); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE068 + i + j] = CAST_OP(0xE068); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE0A8 + i + j] = CAST_OP(0xE0A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE030 + i + j] = CAST_OP(0xE030); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE070 + i + j] = CAST_OP(0xE070); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE0B0 + i + j] = CAST_OP(0xE0B0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE038 + i + j] = CAST_OP(0xE038); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE078 + i + j] = CAST_OP(0xE078); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE0B8 + i + j] = CAST_OP(0xE0B8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE120 + i + j] = CAST_OP(0xE120); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE160 + i + j] = CAST_OP(0xE160); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE1A0 + i + j] = CAST_OP(0xE1A0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE128 + i + j] = CAST_OP(0xE128); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE168 + i + j] = CAST_OP(0xE168); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE1A8 + i + j] = CAST_OP(0xE1A8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE130 + i + j] = CAST_OP(0xE130); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE170 + i + j] = CAST_OP(0xE170); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE1B0 + i + j] = CAST_OP(0xE1B0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE138 + i + j] = CAST_OP(0xE138); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE178 + i + j] = CAST_OP(0xE178); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + for(j = 0x0000; j <= 0x0E00; j += 0x0200) \ + JumpTable[0xE1B8 + i + j] = CAST_OP(0xE1B8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE0D0 + i] = CAST_OP(0xE0D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE0D8 + i] = CAST_OP(0xE0D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE0E0 + i] =CAST_OP(0xE0E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE0E8 + i] = CAST_OP(0xE0E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE0F0 + i] = CAST_OP(0xE0F0); \ + JumpTable[0xE0F8] = CAST_OP(0xE0F8); \ + JumpTable[0xE0F9] = CAST_OP(0xE0F9); \ + JumpTable[0xE0DF] = CAST_OP(0xE0DF); \ + JumpTable[0xE0E7] = CAST_OP(0xE0E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE2D0 + i] = CAST_OP(0xE2D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE2D8 + i] = CAST_OP(0xE2D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE2E0 + i] = CAST_OP(0xE2E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE2E8 + i] = CAST_OP(0xE2E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE2F0 + i] = CAST_OP(0xE2F0); \ + JumpTable[0xE2F8] = CAST_OP(0xE2F8); \ + JumpTable[0xE2F9] = CAST_OP(0xE2F9); \ + JumpTable[0xE2DF] = CAST_OP(0xE2DF); \ + JumpTable[0xE2E7] = CAST_OP(0xE2E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE4D0 + i] = CAST_OP(0xE4D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE4D8 + i] = CAST_OP(0xE4D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE4E0 + i] = CAST_OP(0xE4E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE4E8 + i] = CAST_OP(0xE4E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE4F0 + i] = CAST_OP(0xE4F0); \ + JumpTable[0xE4F8] = CAST_OP(0xE4F8); \ + JumpTable[0xE4F9] = CAST_OP(0xE4F9); \ + JumpTable[0xE4DF] = CAST_OP(0xE4DF); \ + JumpTable[0xE4E7] = CAST_OP(0xE4E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE6D0 + i] = CAST_OP(0xE6D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE6D8 + i] = CAST_OP(0xE6D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE6E0 + i] = CAST_OP(0xE6E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE6E8 + i] = CAST_OP(0xE6E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE6F0 + i] = CAST_OP(0xE6F0); \ + JumpTable[0xE6F8] = CAST_OP(0xE6F8); \ + JumpTable[0xE6F9] = CAST_OP(0xE6F9); \ + JumpTable[0xE6DF] = CAST_OP(0xE6DF); \ + JumpTable[0xE6E7] = CAST_OP(0xE6E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE1D0 + i] = CAST_OP(0xE1D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE1D8 + i] = CAST_OP(0xE1D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE1E0 + i] = CAST_OP(0xE1E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE1E8 + i] = CAST_OP(0xE1E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE1F0 + i] = CAST_OP(0xE1F0); \ + JumpTable[0xE1F8] = CAST_OP(0xE1F8); \ + JumpTable[0xE1F9] = CAST_OP(0xE1F9); \ + JumpTable[0xE1DF] = CAST_OP(0xE1DF); \ + JumpTable[0xE1E7] = CAST_OP(0xE1E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE3D0 + i] = CAST_OP(0xE3D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE3D8 + i] = CAST_OP(0xE3D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE3E0 + i] = CAST_OP(0xE3E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE3E8 + i] = CAST_OP(0xE3E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE3F0 + i] = CAST_OP(0xE3F0); \ + JumpTable[0xE3F8] = CAST_OP(0xE3F8); \ + JumpTable[0xE3F9] = CAST_OP(0xE3F9); \ + JumpTable[0xE3DF] = CAST_OP(0xE3DF); \ + JumpTable[0xE3E7] = CAST_OP(0xE3E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE5D0 + i] = CAST_OP(0xE5D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE5D8 + i] = CAST_OP(0xE5D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE5E0 + i] = CAST_OP(0xE5E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE5E8 + i] = CAST_OP(0xE5E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE5F0 + i] = CAST_OP(0xE5F0); \ + JumpTable[0xE5F8] = CAST_OP(0xE5F8); \ + JumpTable[0xE5F9] = CAST_OP(0xE5F9); \ + JumpTable[0xE5DF] = CAST_OP(0xE5DF); \ + JumpTable[0xE5E7] = CAST_OP(0xE5E7); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE7D0 + i] = CAST_OP(0xE7D0); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE7D8 + i] = CAST_OP(0xE7D8); \ + for(i = 0x0000; i <= 0x0006; i += 0x0001) \ + JumpTable[0xE7E0 + i] = CAST_OP(0xE7E0); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE7E8 + i] = CAST_OP(0xE7E8); \ + for(i = 0x0000; i <= 0x0007; i += 0x0001) \ + JumpTable[0xE7F0 + i] = CAST_OP(0xE7F0); \ + JumpTable[0xE7F8] = CAST_OP(0xE7F8); \ + JumpTable[0xE7F9] = CAST_OP(0xE7F9); \ + JumpTable[0xE7DF] = CAST_OP(0xE7DF); \ + JumpTable[0xE7E7] = CAST_OP(0xE7E7); \ + for(i = 0x0000; i <= 0x0FFF; i += 0x0001) \ + JumpTable[0xF000 + i] = CAST_OP(0xF000); \ +} + +typedef unsigned char u8; +typedef signed char s8; +typedef unsigned short u16; +typedef signed short s16; +typedef unsigned int u32; +typedef signed int s32; + +#ifdef FAME_EMULATE_TRACE +static u32 flag_T; +#endif +static u32 flag_C; +static u32 flag_V; +static u32 flag_NotZ; +static u32 flag_N; +static u32 flag_X; /* 16 bytes aligned */ +static u32 flag_S; +static u32 flag_I; + +typedef union +{ +#ifndef FAME_BIG_ENDIAN + struct + { + u8 B,B1,B2,B3; + } b; + struct + { + s8 SB,SB1,SB2,SB3; + } sb; + struct + { + u16 W,W1; + } w; + struct + { + s16 SW,SW1; + } sw; +#else + struct + { + u8 B3,B2,B1,B; + } b; + struct + { + s8 SB3,SB2,SB1,SB; + } sb; + struct + { + u16 W1,W; + } w; + struct + { + s16 SW1,SW; + } sw; +#endif + u32 D; + s32 SD; +} famec_union32; + +/* M68K registers */ +typedef enum +{ + M68K_REG_D0=0, + M68K_REG_D1, + M68K_REG_D2, + M68K_REG_D3, + M68K_REG_D4, + M68K_REG_D5, + M68K_REG_D6, + M68K_REG_D7, + M68K_REG_A0, + M68K_REG_A1, + M68K_REG_A2, + M68K_REG_A3, + M68K_REG_A4, + M68K_REG_A5, + M68K_REG_A6, + M68K_REG_A7, + M68K_REG_ASP, + M68K_REG_PC, + M68K_REG_SR +} m68k_register; + + +/* The memory blocks must be in native (Motorola) format */ +typedef struct +{ + u32 low_addr; + u32 high_addr; + u32 offset; +} M68K_PROGRAM; + +/* The memory blocks must be in native (Motorola) format */ +typedef struct +{ + u32 low_addr; + u32 high_addr; + void *mem_handler; + void *data; +} M68K_DATA; + +/* M68K CPU CONTEXT */ +typedef struct +{ + M68K_PROGRAM *fetch; + M68K_DATA *read_byte; + M68K_DATA *read_word; + M68K_DATA *write_byte; + M68K_DATA *write_word; + M68K_PROGRAM *sv_fetch; + M68K_DATA *sv_read_byte; + M68K_DATA *sv_read_word; + M68K_DATA *sv_write_byte; + M68K_DATA *sv_write_word; + M68K_PROGRAM *user_fetch; + M68K_DATA *user_read_byte; + M68K_DATA *user_read_word; + M68K_DATA *user_write_byte; + M68K_DATA *user_write_word; + void (*reset_handler)(void); + void (*iack_handler)(u32 level); + u32 *icust_handler; + famec_union32 dreg[8]; + famec_union32 areg[8]; + u32 asp; + u32 pc; + u32 cycles_counter; + u8 interrupts[8]; + u16 sr; + u16 execinfo; +} M68K_CONTEXT; + + +/* Custom function handler */ +typedef void (*icust_handler_func)(u32 vector); + +/* + global variable +*/ + +/* Main CPU context */ +#ifdef FAME_GLOBAL_CONTEXT +M68K_CONTEXT FAME_CONTEXT; +s32 io_cycle_counter; +#else +static M68K_CONTEXT FAME_CONTEXT; +static s32 io_cycle_counter; +#endif + +static s32 cycles_needed=0; +static s32 cycles_to_do=0; +#if FAME_PC_BITS == 32 +static u32 PC; +static u16* BasePC; +#else +static u16 *PC; +static u32 BasePC; +#endif +static u32 Fetch[M68K_FETCHBANK]; + +/* Lookup IRQ level to attend */ +/* Indexed by interrupts[0] */ +static u8 irq_level_lookup[256] = +{ + 0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5, + 5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6, + 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6, + 6,6,6,6,6,6,6,6,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7, + 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7, + 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7, + 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7 +}; + +typedef u8 (*mem8_handler_func)(s32 address); +typedef u16 (*mem16_handler_func)(s32 address); +typedef u32 (*mem32_handler_func)(s32 address); +typedef void (*memw_handler_func)(s32 address, s32 data); + +#ifdef FAME_SECURE_ALL_BANKS +static unsigned char dummy_fetch[(1<> M68K_FETCHSFT) & M68K_FETCHMASK; + j = (0xFFFFFFFF >> M68K_FETCHSFT) & M68K_FETCHMASK; + while (i <= j) + { + Fetch[i] = ((u32)&dummy_fetch)-(i*(1<> M68K_FETCHSFT) & M68K_FETCHMASK; + j = (high_adr >> M68K_FETCHSFT) & M68K_FETCHMASK; + + while (i <= j) + Fetch[i++] = fetch_adr; +} + +#ifdef FAME_DIRECT_MAPPING + +static void famec_SetDummyData(void) +{ +#ifdef FAME_SECURE_ALL_BANKS + u32 i, j; + + i = (0 >> M68K_DATASFT) & M68K_DATAMASK; + j = (0xFFFFFFFF >> M68K_DATASFT) & M68K_DATAMASK; + + while (i <= j) + { + DataRB[i].mem_handler = DataRW[i].mem_handler = (void *)&dummy_read; + DataWB[i].mem_handler = DataWW[i].mem_handler = (void *)&dummy_write; + DataRB[i].data = DataRW[i].data = DataWB[i].data = DataWW[i].data = NULL; + i++; + } +#endif +} + +static void famec_SetDataRB(u32 low_adr, u32 high_adr, void *mh, void *dt) +{ + u32 i, j; + + i = (low_adr >> M68K_DATASFT) & M68K_DATAMASK; + j = (high_adr >> M68K_DATASFT) & M68K_DATAMASK; + + while (i <= j) + { + DataRB[i].mem_handler = mh; + DataRB[i++].data = dt; + } +} + +static void famec_SetDataRW(u32 low_adr, u32 high_adr, void *mh, void *dt) +{ + u32 i, j; + + i = (low_adr >> M68K_DATASFT) & M68K_DATAMASK; + j = (high_adr >> M68K_DATASFT) & M68K_DATAMASK; + + while (i <= j) + { + DataRW[i].mem_handler = mh; + DataRW[i++].data = dt; + } +} + +static void famec_SetDataWB(u32 low_adr, u32 high_adr, void *mh, void *dt) +{ + u32 i, j; + + i = (low_adr >> M68K_DATASFT) & M68K_DATAMASK; + j = (high_adr >> M68K_DATASFT) & M68K_DATAMASK; + + while (i <= j) + { + DataWB[i].mem_handler = mh; + DataWB[i++].data = dt; + } +} + +static void famec_SetDataWW(u32 low_adr, u32 high_adr, void *mh, void *dt) +{ + u32 i, j; + + i = (low_adr >> M68K_DATASFT) & M68K_DATAMASK; + j = (high_adr >> M68K_DATASFT) & M68K_DATAMASK; + + while (i <= j) + { + DataWW[i].mem_handler = mh; + DataWW[i++].data = dt; + } +} +#endif + +static void famec_SetBanks(void) +{ + famec_SetDummyFetch(); + + SETUP_FETCH_BANK(famec_SetFetch, FAME_CONTEXT.fetch) + +#ifdef FAME_DIRECT_MAPPING + famec_SetDummyData(); + + SETUP_DATA_BANK(famec_SetDataRB, FAME_CONTEXT.read_byte) + SETUP_DATA_BANK(famec_SetDataRW, FAME_CONTEXT.read_word) + SETUP_DATA_BANK(famec_SetDataWB, FAME_CONTEXT.write_byte) + SETUP_DATA_BANK(famec_SetDataWW, FAME_CONTEXT.write_word) +#endif +} + +#ifdef FAME_ACCURATE_TIMING +/* + Functions used to compute accurate opcode timing (MUL/DIV) +*/ + +static EXTRA_INLINE u8 bitset_count(u32 data) +{ + unsigned int const MASK1 = 0x55555555; + unsigned int const MASK2 = 0x33333333; + unsigned int const MASK4 = 0x0f0f0f0f; + unsigned int const MASK6 = 0x0000003f; + + unsigned int const w = (data & MASK1) + ((data >> 1) & MASK1); + unsigned int const x = (w & MASK2) + ((w >> 2) & MASK2); + unsigned int const y = ((x + (x >> 4)) & MASK4); + unsigned int const z = (y + (y >> 8)); + unsigned int const c = (z + (z >> 16)) & MASK6; + + return c; +} + +/* + DIVU + Unsigned division +*/ +static u32 getDivu68kCycles(u32 dividend, u16 divisor) +{ + u32 mcycles; + u32 hdivisor; + int i; + + if ( (u16) divisor == 0) + return 0; + + /* Overflow */ + if ( (dividend >> 16) >= divisor) + return (mcycles = 5) * 2; + + mcycles = 38; + hdivisor = ((u32) divisor) << 16; + + for ( i = 0; i < 15; i++) + { + u32 temp; + temp = dividend; + + dividend <<= 1; + + /* If carry from shift */ + if ( (int) temp < 0) + { + dividend -= hdivisor; + } + + else + { + mcycles += 2; + if ( dividend >= hdivisor) + { + dividend -= hdivisor; + mcycles--; + } + } + } + + return mcycles * 2; +} + +/* + DIVS + Signed division +*/ +static u32 getDivs68kCycles(s32 dividend, s16 divisor) +{ + u32 mcycles; + u32 aquot; + int i; + + if ( (s16) divisor == 0) + return 0; + + mcycles = 6; + + if ( dividend < 0) + mcycles++; + + /* Check for absolute overflow */ + if ( ((u32) abs( dividend) >> 16) >= (u16) abs( divisor)) + { + return (mcycles + 2) * 2; + } + + /* Absolute quotient */ + aquot = (u32) abs( dividend) / (u16) abs( divisor); + + mcycles += 55; + + if ( divisor >= 0) + { + if ( dividend >= 0) + mcycles--; + else + mcycles++; + } + + /* Count 15 msbits in absolute of quotient */ + + for ( i = 0; i < 15; i++) + { + if ( (s16) aquot >= 0) + mcycles++; + aquot <<= 1; + } + + return mcycles * 2; +} +#endif + +/* + Read / Write functions +*/ + +static EXTRA_INLINE u32 Read_Byte(u32 addr) +{ + u32 i=0; + s32 val; + + addr&=M68K_ADDR_MASK; +#ifdef FAME_DEBUG + printf("Reading byte from addr = 0x%08X\n",addr); +#endif + +#ifndef FAME_DIRECT_MAPPING + while ( ((FAME_CONTEXT.read_byte[i].low_addr > addr) || (FAME_CONTEXT.read_byte[i].high_addr < addr)) && (FAME_CONTEXT.read_byte[i].low_addr != BANKEND_TAG) ) + i++; + + if (FAME_CONTEXT.read_byte[i].low_addr == BANKEND_TAG) + return (u32)-1; +#else + i=addr>>M68K_DATASFT; +#endif + + if (DataRB[i].mem_handler) + val= (*((mem8_handler_func *)&DataRB[i].mem_handler))(addr); + else +#ifndef FAME_BIG_ENDIAN + val = *((u8 *)(((u32)DataRB[i].data) + (addr^1))); +#else + val = *((u8 *)(((u32)DataRB[i].data) + (addr))); +#endif + +#ifdef FAME_DEBUG + printf("Reading 0x%08X = 0x%04X...\n",addr,val); +#endif + + return val; +} + +static EXTRA_INLINE u32 Read_Word(u32 addr) +{ + u32 i=0; + s32 val; + + addr&=M68K_ADDR_MASK; +#ifdef FAME_DEBUG + printf("Reading from addr = 0x%08X\n",addr); +#endif + +#ifndef FAME_DIRECT_MAPPING + while ( ((FAME_CONTEXT.read_word[i].low_addr > addr) || (FAME_CONTEXT.read_word[i].high_addr < addr)) && (FAME_CONTEXT.read_word[i].low_addr != BANKEND_TAG) ) + i++; + + if (FAME_CONTEXT.read_word[i].low_addr == BANKEND_TAG) + return (u32)-1; +#else + i=addr>>M68K_DATASFT; +#endif + + if (DataRW[i].mem_handler) + val= (*((mem16_handler_func *)&DataRW[i].mem_handler))(addr); + else + val = *((u16 *)(((u32)DataRW[i].data) + addr)); + +#ifdef FAME_DEBUG + printf("Reading 0x%08X = 0x%04X...\n",addr,val); +#endif + + return val; +} + +static EXTRA_INLINE void Write_Byte(u32 addr, u32 data) +{ + u32 i=0; + + addr&=M68K_ADDR_MASK; +#ifdef FAME_DEBUG + printf("Writing byte 0x%08X = 0x%04X...\n",addr,data); +#endif + +#ifndef FAME_DIRECT_MAPPING + while ( ((FAME_CONTEXT.write_byte[i].low_addr > addr) || (FAME_CONTEXT.write_byte[i].high_addr < addr)) && (FAME_CONTEXT.write_byte[i].low_addr != BANKEND_TAG) ) + i++; + if (FAME_CONTEXT.write_byte[i].low_addr == BANKEND_TAG) + return; +#else + i=addr>>M68K_DATASFT; +#endif + + if (DataWB[i].mem_handler != NULL) + (*((memw_handler_func *)&DataWB[i].mem_handler))(addr,data); + else +#ifndef FAME_BIG_ENDIAN + *((u8 *)(((u32)DataWB[i].data)+ (addr^1))) = data; +#else + *((u8 *)(((u32)DataWB[i].data)+ (addr))) = data; +#endif +} + + +static EXTRA_INLINE void Write_Word(u32 addr, u32 data) +{ + u32 i=0; + + addr&=M68K_ADDR_MASK; +#ifdef FAME_DEBUG + printf("Writing 0x%08X = 0x%04X...\n",addr,data); +#endif + +#ifndef FAME_DIRECT_MAPPING + while ( ((FAME_CONTEXT.write_word[i].low_addr > addr) || (FAME_CONTEXT.write_word[i].high_addr < addr)) && (FAME_CONTEXT.write_word[i].low_addr != BANKEND_TAG) ) + i++; + if (FAME_CONTEXT.write_word[i].low_addr == BANKEND_TAG) + return; +#else + i=addr>>M68K_DATASFT; +#endif + + if (DataWW[i].mem_handler != NULL) + (*((memw_handler_func *)&DataWW[i].mem_handler))(addr,data); + else + *((u16 *)(((u32)DataWW[i].data) + addr)) = data; +} + +static u32 Opcode; + +/* + Chequea las interrupciones y las inicia +*/ +static EXTRA_INLINE s32 interrupt_chk(void) +{ + /* Bit 0 MUST be zero at all times */ + assert((FAME_CONTEXT.interrupts[0] & 1) == 0); + + if (FAME_CONTEXT.interrupts[0]) + { + /* There is a pending IRQ */ + const u8 irql = irq_level_lookup[FAME_CONTEXT.interrupts[0]]; + + if (irql == 7) /* NMI */ + return irql; + else if (irql > flag_I) + return irql; + } + +#ifdef FAME_EMULATE_TRACE + if (flag_T) + { + /* + FAME_CONTEXT.execinfo |= M68K_EMULATE_TRACE; + cycles_needed= io_cycle_counter; + io_cycle_counter=0; + */ + return -1; + } +#endif + return 0; +} + + +static EXTRA_INLINE void execute_exception(s32 vect) +{ + /* comprobar si hay tabla funciones manejadoras */ + if (FAME_CONTEXT.icust_handler && FAME_CONTEXT.icust_handler[vect]) + { + FAME_CONTEXT.sr = GET_SR; + FAME_CONTEXT.pc = UNBASED_PC; + (*(icust_handler_func*)&FAME_CONTEXT.icust_handler[vect])(vect); + } + else + { + u32 newPC; + u32 oldPC; + u32 oldSR = GET_SR; + + READ_LONG_F(vect * 4, newPC) + + /* swap A7 and USP */ + if (!flag_S) + { + u32 tmpSP; + + tmpSP = ASP; + ASP = AREG(7); + AREG(7) = tmpSP; + } + + oldPC = UNBASED_PC; + PUSH_32_F(oldPC) + PUSH_16_F(oldSR) + + /* adjust SR */ + flag_S = M68K_SR_S; + + SET_PC(newPC) + } + + io_cycle_counter -= exception_cycle_table[vect]; +} + +static EXTRA_INLINE void interrupt_attend(s32 line) +{ + /* al atender la IRQ, la CPU sale del estado parado */ + FAME_CONTEXT.execinfo &= ~M68K_HALTED; + + /* Desactivar interrupcion */ + FAME_CONTEXT.interrupts[0] &= ~(1 << ((u32)line)); + + execute_exception(FAME_CONTEXT.interrupts[(u32)line]); + + /* comprobar si hay rutina de acknowledge */ + if (FAME_CONTEXT.iack_handler != NULL) + FAME_CONTEXT.iack_handler(line); + + flag_I = (u32)line; +} + +/* Group 0 exceptions are not handled actually */ +static EXTRA_INLINE void execute_exception_group_0(s32 vect, u16 inst_reg, s32 addr, u16 spec_info) +{ + execute_exception(vect); + if (!(FAME_CONTEXT.icust_handler && FAME_CONTEXT.icust_handler[vect])) + { + PUSH_16_F(inst_reg); + PUSH_32_F(addr); + PUSH_16_F(spec_info); + } +} + +/* Performs the required actions to finish the emulate call */ +static EXTRA_INLINE void finish_emulate(const s32 cycles_to_add) +{ + FAME_CONTEXT.sr = GET_SR; + FAME_CONTEXT.pc = UNBASED_PC; + + FAME_CONTEXT.execinfo &= ~M68K_RUNNING; + + /* Actualizar contador de ciclos */ + FAME_CONTEXT.cycles_counter += cycles_to_add; + +#ifdef FAME_DEBUG + printf("<-PC=0x%08X (%p-%p)\n",UNBASED_PC,PC,BasePC); +#endif +} + +#ifndef FAME_GOTOS + +#define OPCODE(N_OP) static void OP_##N_OP(void) +#define CAST_OP(N_OP) (opcode_func)&OP_##N_OP +#include "famec_opcodes.h" +#else +#define OPCODE(N_OP) OP_##N_OP: +#define CAST_OP(N_OP) (opcode_func)&&OP_##N_OP +#endif + +//static opcode_func JumpTable[0x10000]; +#include "jumptable.h" + +/***********************/ +/* core main functions */ +/***********************/ + +/***************************************************************************/ +/* m68k_init() */ +/* Debe ser llamado para inicializar la tabla de saltos de instruccion */ +/* No recibe parametros y no devuelve nada */ +/***************************************************************************/ +void FAME_API(init)(void) +{ +#ifdef FAME_DEBUG + puts("Initializing FAME..."); +#endif + +#ifndef FAME_GOTOS + //BUILD_OPCODE_TABLE + initialised = 1; +#endif + +#ifdef FAME_DEBUG + puts("FAME initialized."); +#endif +} + +/******************************************************************************/ +/* m68k_reset() */ +/* Parametros: Ninguno */ +/* Retorno: Exito de la operacion */ +/* M68K_OK (0): La funcion se ha ejecutado satisfactoriamente */ +/* M68K_RUNNING (1): No se puede resetear porque la CPU esta en ejecucion */ +/* M68K_NO_SUP_ADDR_SPACE (2): No se puede resetear porque no hay mapa */ +/* de memoria supervisor de extraccion de opcodes */ +/******************************************************************************/ +u32 FAME_API(reset)(void) +{ +#ifndef FAME_GOTOS + assert(initialised); +#endif + + /* Si la CPU esta en ejecucion, salir con M68K_RUNNING */ + if (FAME_CONTEXT.execinfo & M68K_RUNNING) + return M68K_RUNNING; + + /* Si no hay mapa de memoria supervisor, salir con M68K_NO_SUP_ADDR_SPACE */ + if (!FAME_CONTEXT.sv_fetch) + return M68K_NO_SUP_ADDR_SPACE; + + FAME_CONTEXT.fetch = FAME_CONTEXT.sv_fetch; + FAME_CONTEXT.read_byte = FAME_CONTEXT.sv_read_byte; + FAME_CONTEXT.read_word = FAME_CONTEXT.sv_read_word; + FAME_CONTEXT.write_byte = FAME_CONTEXT.sv_write_byte; + FAME_CONTEXT.write_word = FAME_CONTEXT.sv_write_word; + + /* Resetear registros */ + memset(&FAME_CONTEXT.dreg[0], 0, 16*4); + + /* Resetear interrupts, execinfo y ASP */ + memset(&FAME_CONTEXT.interrupts[0], 0, 8); + FAME_CONTEXT.execinfo = 0; + ASP = 0; + + /* Fijar registro de estado */ + FAME_CONTEXT.sr = 0x2700; + + /* Obtener puntero de pila inicial y PC */ + READ_LONG_F(0, AREG(7)); + READ_LONG_F(4, FAME_CONTEXT.pc); + +#ifdef FAME_DEBUG + puts("Reset 68k done!\n"); + printf("PC = 0x%08X\n",FAME_CONTEXT.pc); +#endif + + return M68K_OK; +} + + +/******************************************************************************/ +/* m68k_raise_irq(level,vector) */ +/* Parametros: level = nivel de interrupcion */ +/* vector = puntero a la direccion de la rutina de atencion */ +/* -1 auto, -2 interrupcion espuria */ +/* Retorno: Exito de la operacion */ +/* 0 La interrupcion se ha habilitado satisfactoriamente */ +/* -1 No se ha podido habilitar porque ya existe otra interrupcion */ +/* en ese nivel. */ +/* -2 No se ha podido habilitar porque el vector no es valido o */ +/* el nivel es igual a 0. */ +/******************************************************************************/ +s32 FAME_API(raise_irq)(s32 level, s32 vector) +{ + /* Enmascarar nivel de interrupcion */ + level &=7; + + /* Nivel de interrupcion = 0 no es valido */ + if (!level) return M68K_IRQ_INV_PARAMS; + + /* Comprobar si existe una interrupcion activada en ese nivel */ + if (FAME_CONTEXT.interrupts[0] & (1 << level)) + return M68K_IRQ_LEVEL_ERROR; + + /* El vector de interrupcion no puede ser > 255 ni menor que -2 */ + if ((vector > 255) || (vector < M68K_SPURIOUS_IRQ)) + { + return M68K_IRQ_INV_PARAMS; + } + + /* Dar de alta la interrupcion en interrupts */ + FAME_CONTEXT.interrupts[0] |= (1 << level); + + switch (vector) + { + case M68K_SPURIOUS_IRQ: + FAME_CONTEXT.interrupts[level] = 0x18; + break; + case M68K_AUTOVECTORED_IRQ: + FAME_CONTEXT.interrupts[level] = level + 0x18; + break; + default: + FAME_CONTEXT.interrupts[level] = vector; + break; + } +#ifdef FAME_DEBUG + printf("RAISE interrupts[%i]=0x%X\n",level,FAME_CONTEXT.interrupts[level]); +#endif + + /* Testear si la CPU esta detenida (mediante STOP) */ + if (FAME_CONTEXT.execinfo & M68K_HALTED) + { + /* Si la IRQ es NMI o si supera la mascara de interrupcion, */ + /* salir de estado parado */ + if ((level == 7) || (level > ((FAME_CONTEXT.sr >> 8) & 0x7))) + { + FAME_CONTEXT.execinfo &= ~M68K_HALTED; + } + } + + return M68K_OK; +} + + +/******************************************************************************/ +/* m68k_lower_irq(level) */ +/* Parametros: Nivel de la interrupcion a retirar */ +/* Retorno: Exito de la operacion */ +/* 0 La interrupcion se ha retirado satisfactoriamente */ +/* -1 No se ha podido retirar porque esa interrupcion */ +/* no esta habilitada. */ +/* -2 No se ha podido retirar porque el nivel es 0 o mayor */ +/* o igual que 7 (no se puede retirar la NMI) */ +/******************************************************************************/ +s32 FAME_API(lower_irq)(s32 level) +{ + /* Enmascarar nivel de interrupcion */ + level &=7; + + /* Nivel de interrupcion = 0 no es valido */ + if (!level) return M68K_IRQ_INV_PARAMS; + + /* La interrupcion de nivel 7 (NMI) no se puede bajar */ + if (level > 6) + { + return M68K_IRQ_INV_PARAMS; + } + + /* Comprobar que la interrupcion este activada */ + if (FAME_CONTEXT.interrupts[0] & (1 << level)) + { + /* Dar de baja la interrupcion */ + FAME_CONTEXT.interrupts[0] &= ~(1 << level); + } + else + { + return M68K_IRQ_LEVEL_ERROR; + } + + return M68K_OK; +} + +/******************************************************************************/ +/* m68k_get_context_size */ +/* No recibe parametros */ +/* Retorno: Tamano del contexto en bytes */ +/******************************************************************************/ +s32 FAME_API(get_context_size)(void) +{ + return sizeof(M68K_CONTEXT); +} + +/***************************************************************************/ +/* m68k_get_context(address) */ +/* Parametro: Direccion del contexto */ +/* No retorna ningun valor */ +/***************************************************************************/ +void FAME_API(get_context)(void *context) +{ + memcpy(context,&FAME_CONTEXT,sizeof(M68K_CONTEXT)); +} + +/***************************************************************************/ +/* m68k_set_context(address) */ +/* Parametro: Direccion del contexto */ +/* No retorna ningun valor */ +/***************************************************************************/ +void FAME_API(set_context)(void *context) +{ + memcpy(&FAME_CONTEXT,context,sizeof(M68K_CONTEXT)); + famec_SetBanks(); +} + +/****************************************************************************/ +/* m68k_get_pc() */ +/* No recibe parametros */ +/* Retorna 68k PC */ +/****************************************************************************/ +u32 FAME_API(get_pc)(void) +{ + return (FAME_CONTEXT.execinfo & M68K_RUNNING) ? UNBASED_PC : FAME_CONTEXT.pc; +} + +/***************************************************************************/ +/* m68k_get_register(register) */ +/* Parametro: Registro a obtener valor (indice) */ +/* Retorno: Valor del registro requerido */ +/* Observacion: En caso de que el indice no sea correcto */ +/* la funcion devolvera -1 */ +/***************************************************************************/ +s32 FAME_API(get_register)(m68k_register reg) +{ + switch (reg) + { + case M68K_REG_D0: + case M68K_REG_D1: + case M68K_REG_D2: + case M68K_REG_D3: + case M68K_REG_D4: + case M68K_REG_D5: + case M68K_REG_D6: + case M68K_REG_D7: + return DREG(reg - M68K_REG_D0); + + case M68K_REG_A0: + case M68K_REG_A1: + case M68K_REG_A2: + case M68K_REG_A3: + case M68K_REG_A4: + case M68K_REG_A5: + case M68K_REG_A6: + case M68K_REG_A7: + return AREG(reg - M68K_REG_A0); + + case M68K_REG_ASP: + return ASP; + + case M68K_REG_PC: + return FAME_API(get_pc)(); + + case M68K_REG_SR: + return (FAME_CONTEXT.execinfo & M68K_RUNNING) ? GET_SR : FAME_CONTEXT.sr; + + default: + return M68K_INV_REG; + } +} + +/***********************************************************************/ +/* m68k_set_register(register,value) */ +/* Parametros: Registro (indice) y valor a asignar */ +/* Retorno: Exito de la operacion */ +/* 0 La operacion se ha realizado satisfactoriamente */ +/* 1 El indice del registro no es valido (fuera de limites) */ +/***********************************************************************/ +s32 FAME_API(set_register)(m68k_register reg, u32 value) +{ + switch (reg) + { + case M68K_REG_D0: + case M68K_REG_D1: + case M68K_REG_D2: + case M68K_REG_D3: + case M68K_REG_D4: + case M68K_REG_D5: + case M68K_REG_D6: + case M68K_REG_D7: + DREG(reg - M68K_REG_D0) = value; + break; + + case M68K_REG_A0: + case M68K_REG_A1: + case M68K_REG_A2: + case M68K_REG_A3: + case M68K_REG_A4: + case M68K_REG_A5: + case M68K_REG_A6: + case M68K_REG_A7: + AREG(reg - M68K_REG_A0) = value; + break; + + case M68K_REG_ASP: + ASP = value; + break; + + case M68K_REG_PC: + if (FAME_CONTEXT.execinfo & M68K_RUNNING) + { + SET_PC(value); + } + else + { + FAME_CONTEXT.pc = value; + } + break; + + case M68K_REG_SR: + if (FAME_CONTEXT.execinfo & M68K_RUNNING) + { + SET_SR(value); + } + else + { + FAME_CONTEXT.sr = value & 0xFFFF; + } + break; + + default: + return M68K_INV_REG; + } + + return M68K_OK; +} + +/*********************************************************/ +/* m68k_fetch(address,access_type) */ +/* Lee una palabra del espacio de memoria del 68k */ +/* Parametro: Direccion de la palabra y tipo de acceso */ +/* Retorno: La palabra o -1 en caso de dir. no valida */ +/*********************************************************/ +s32 FAME_API(fetch)(u32 addr, u32 memory_space) +{ + u32 i=0; + s32 val; + M68K_DATA *ds = NULL; + M68K_PROGRAM *ps = NULL; + + switch (memory_space & 2) + { + case M68K_SUP_ADDR_SPACE: + if ((memory_space & 1) == M68K_PROG_ADDR_SPACE) + ps = FAME_CONTEXT.sv_fetch; + else + ds = FAME_CONTEXT.sv_read_word; + break; + + case M68K_USER_ADDR_SPACE: + if ((memory_space & 1) == M68K_PROG_ADDR_SPACE) + ps = FAME_CONTEXT.user_fetch; + else + ds = FAME_CONTEXT.user_read_word; + break; + } + + if (ps == NULL) + { + while ( ((ds[i].low_addr > addr) || (ds[i].high_addr < addr)) && (ds[i].low_addr != BANKEND_TAG) ) + { +#ifdef FAME_DEBUG + printf("RW not found in %d region... 0x%08X - 0x%08X --> 0x%08X\n",i,ds[i].low_addr,ds[i].high_addr,addr); +#endif + + i++; + } + + if (ds[i].low_addr == BANKEND_TAG) + { + /* Error de BUS */ +#ifdef FAME_DEBUG + printf("ERROR de BUS en region %d...\n",i); +#endif + return -1; + } + else + { + if (ds[i].mem_handler != NULL) + { +#ifdef FAME_DEBUG + puts("Handled...\n"); +#endif + val= (*((mem16_handler_func *)&ds[i].mem_handler))(addr); + } + else + { +#ifdef FAME_DEBUG + printf("Ptr en region %d... addr: %p\n",i,ds[i].data); +#endif + val = *((u16 *)(((u32)ds[i].data) + addr)); +#ifdef FAME_DEBUG + puts("read"); +#endif + } + } + +#ifdef FAME_DEBUG + printf("Reading 0x%08X = 0x%04X...\n",addr,val); +#endif + } + else + { + u32 tmp=Fetch[((addr) >> M68K_FETCHSFT) & M68K_FETCHMASK]; + u16 *p= (u16*)(((addr) & M68K_ADDR_MASK) + (tmp)); + val = *p; +#ifdef FAME_DEBUG + printf("@%08X *%p=%04X\n",addr,p,val); +#endif + } + + return val; +} + +/******************************************************/ +/* m68k_get_cycles_counter() */ +/* Retorna el cycles_counter */ +/* Parametro: Ninguno */ +/* Retorno: cycles_counter */ +/******************************************************/ +u32 FAME_API(get_cycles_counter)(void) +{ + if (FAME_CONTEXT.execinfo & M68K_RUNNING) + return (cycles_to_do - io_cycle_counter) + FAME_CONTEXT.cycles_counter; + else + return FAME_CONTEXT.cycles_counter; +} + +/******************************************************/ +/* m68k_trip_cycles_counter() */ +/* Retorna el cycles_counter y lo reinicializa */ +/* Parametro: Ninguno */ +/* Retorno: cycles_counter */ +/******************************************************/ +u32 FAME_API(trip_cycles_counter)(void) +{ + s32 ret=FAME_CONTEXT.cycles_counter; + + if (FAME_CONTEXT.execinfo & M68K_RUNNING) + { + cycles_to_do-=io_cycle_counter; + io_cycle_counter=0; + } + io_cycle_counter=FAME_CONTEXT.cycles_counter=0; + return ret; +} + +/**********************************************************/ +/* m68k_control_cycles_counter(n) */ +/* Retorna el cycles_counter y lo reinicializa si */ +/* cycles_counter = n */ +/* Parametro: ciclos = n */ +/* Retorno: cycles_counter */ +/**********************************************************/ +u32 FAME_API(control_cycles_counter)(s32 cycles) +{ + return (cycles)?FAME_API(trip_cycles_counter)():FAME_API(get_cycles_counter)(); +} + +/******************************************************/ +/* m68k_release_timeslice() */ +/* Finaliza la ejecucion del micro */ +/* los ciclos sin ejecutar quedan en cycles_counter */ +/* Parametro: Ninguno */ +/* Retorno: Ninguno */ +/******************************************************/ +void FAME_API(release_timeslice)(void) +{ + if (FAME_CONTEXT.execinfo & M68K_RUNNING) + { + io_cycle_counter = 0; + } +} + +/******************************************************/ +/* m68k_stop_emulating() */ +/* Finaliza la ejecucion del micro si esta en */ +/* ejecucion. los ciclos ejecutados seran menos */ +/* de lo normal reflejando asi la salida */ +/* Parametro: Ninguno */ +/* Retorno: Ninguno */ +/******************************************************/ +void FAME_API(stop_emulating)(void) +{ + if (FAME_CONTEXT.execinfo & M68K_RUNNING) + { + /* + es necesario quitar los ciclos de cycles_counter + para que no sean vistos como ejecutados al final + de emulate, ya que stop_emulating incrementa + el contador con los ejecutados realmente, no los + ciclos requeridos por la llamada a emulate + */ + FAME_CONTEXT.cycles_counter -= io_cycle_counter; + io_cycle_counter = 0; + } +} + +/******************************************************/ +/* m68k_add_cycles() */ +/* Incrementa los ciclos de reloj a ejecutar por la */ +/* CPU en las llamadas a emulate */ +/* Parametro: Ninguno */ +/* Retorno: Ninguno */ +/******************************************************/ +void FAME_API(add_cycles)(s32 cycles) +{ + if (FAME_CONTEXT.execinfo & M68K_RUNNING) + { + /* + when the CPU is running, io_cycle_counter stores the remaining cycles to be run + therefore, we have to substract in order to "increment" the clock counter + */ + io_cycle_counter -= cycles; + } + else + { + FAME_CONTEXT.cycles_counter += cycles; + } +} + + +/******************************************************/ +/* m68k_release_cycles() */ +/* Decrementa los ciclos de reloj a ejecutar por la */ +/* CPU en las llamadas a emulate */ +/* Parametro: Ninguno */ +/* Retorno: Ninguno */ +/******************************************************/ +void FAME_API(release_cycles)(s32 cycles) +{ + if (FAME_CONTEXT.execinfo & M68K_RUNNING) + { + /* + when the CPU is running, io_cycle_counter stores the remaining cycles to be run + therefore, we have to add in order to "decrement" the clock counter + */ + io_cycle_counter += cycles; + } + else + { + FAME_CONTEXT.cycles_counter -= cycles; + } +} + +/*****************************************************************************/ +/* m68k_get_cpu_state() */ +/* No recibe parametros */ +/* Retorna el estado de la CPU */ +/*****************************************************************************/ +u32 FAME_API(get_cpu_state)(void) +{ + return FAME_CONTEXT.execinfo; +} + + +/* + main exec function +*/ + +/* + m68k_emulate() + Parametros: Numero de ciclos a ejecutar + Retorno: Exito de la operacion + 0 La operacion se ha realizado satisfactoriamente + -1 La CPU esta detenida debido a un ERROR DE BUS DOBLE (linea) + El PC ha salido de los limites (bucle no en linea) +*/ +u32 FAME_API(emulate)(s32 cycles) +{ +#ifdef FAME_GOTOS + if (!initialised) + { + //BUILD_OPCODE_TABLE + initialised = 1; + } +#else + assert(initialised); +#endif + +#ifdef FAME_DEBUG + printf("m68k_emulate(%d)\n",cycles); +#endif + +#if 0 + /* El bit M68K_FAULTED no esta actualmente en uso */ + /* Comprobar si la CPU esta detenida debido a un doble error de bus */ + if (FAME_CONTEXT.execinfo & M68K_FAULTED) return (u32)-1; +#endif + + /* Poner la CPU en estado de ejecucion */ + FAME_CONTEXT.execinfo |= M68K_RUNNING; + + /* Cache SR */ + SET_SR(FAME_CONTEXT.sr) + + /* Cache PPL */ + flag_I = M68K_PPL; + + /* Fijar PC */ + SET_PC(FAME_CONTEXT.pc) + +#ifdef FAME_DEBUG + printf("->PC=0x%08X (%p-%p)\n",UNBASED_PC,PC,BasePC); +#endif + + /* guardar ciclos de ejecucion solicitados */ + io_cycle_counter = cycles_to_do = cycles; + cycles_needed = 0; + +#ifdef FAME_EMULATE_TRACE + if (!(FAME_CONTEXT.execinfo & M68K_EMULATE_TRACE)) +#endif + { + s32 line = interrupt_chk(); + if (line > 0) + { + interrupt_attend(line); + +#ifdef FAME_IRQ_CLOCKING + if(io_cycle_counter <= 0) + { + finish_emulate(cycles_to_do - io_cycle_counter); + return M68K_OK; + } +#endif + } +#ifdef FAME_EMULATE_TRACE + else if (flag_T) + { + /* al atender la excepcion de traza, la CPU sale del estado parado */ + FAME_CONTEXT.execinfo &= ~M68K_HALTED; + + FAME_CONTEXT.execinfo |= M68K_EMULATE_TRACE; + cycles_needed= io_cycle_counter; + io_cycle_counter=0; + } +#endif + } + + /* Comprobar si la CPU esta parada */ + if (FAME_CONTEXT.execinfo & M68K_HALTED) + { + /* La CPU esta detenida mediante la instruccion STOP */ + /* Agregar ciclos de reloj requeridos */ + finish_emulate(cycles_to_do); + return M68K_OK; + } + +#ifdef FAME_GOTOS +famec_Exec: +#endif + +#ifdef FAME_DEBUG + printf("Antes de NEXT... PC = 0x%08X\n",UNBASED_PC); +#endif + + NEXT + +#ifdef FAME_GOTOS +#include "famec_opcodes.h" + +famec_Exec_End: +#endif + +#ifdef FAME_EMULATE_TRACE + if (FAME_CONTEXT.execinfo & M68K_EMULATE_TRACE) + { + io_cycle_counter= cycles_needed; + cycles_needed=0; + FAME_CONTEXT.execinfo &= ~M68K_EMULATE_TRACE; + FAME_CONTEXT.execinfo |= M68K_DO_TRACE; + execute_exception(M68K_TRACE_EX); + flag_T=0; + if (io_cycle_counter > 0) + { + NEXT + } + } + else +#endif + if (cycles_needed>0) + { + s32 line=interrupt_chk(); + io_cycle_counter= cycles_needed; + cycles_needed=0; + if (line>0) + { + interrupt_attend(line); + } +#ifdef FAME_EMULATE_TRACE + else + if (!(flag_T)) +#endif + if (io_cycle_counter > 0) + { + NEXT + } + } + + finish_emulate(cycles_to_do - io_cycle_counter); + return M68K_OK; +} diff --git a/MCUME_esp32/espcastaway/main/68kfame/famec_opcodes.h b/MCUME_esp32/espcastaway/main/68kfame/famec_opcodes.h new file mode 100644 index 0000000..50d11cf --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68kfame/famec_opcodes.h @@ -0,0 +1,33591 @@ +/* ORI */ +OPCODE(0x0000) +{ + u32 res; + u32 src; + + FETCH_BYTE(src); + res = DREGu8((Opcode >> 0) & 7); + res |= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 0) & 7) = res; + RET(8) +} + +/* ORI */ +OPCODE(0x0010) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ORI */ +OPCODE(0x0018) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ORI */ +OPCODE(0x0020) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ORI */ +OPCODE(0x0028) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* ORI */ +OPCODE(0x0030) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* ORI */ +OPCODE(0x0038) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* ORI */ +OPCODE(0x0039) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* ORI */ +OPCODE(0x001F) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ORI */ +OPCODE(0x0027) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ORI */ +OPCODE(0x0040) +{ + u32 res; + u32 src; + + FETCH_WORD(src); + res = DREGu16((Opcode >> 0) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 0) & 7) = res; + RET(8) +} + +/* ORI */ +OPCODE(0x0050) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ORI */ +OPCODE(0x0058) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ORI */ +OPCODE(0x0060) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ORI */ +OPCODE(0x0068) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ORI */ +OPCODE(0x0070) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(22) +} + +/* ORI */ +OPCODE(0x0078) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ORI */ +OPCODE(0x0079) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + FETCH_LONG(adr); + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(24) +} + +/* ORI */ +OPCODE(0x005F) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ORI */ +OPCODE(0x0067) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ORI */ +OPCODE(0x0080) +{ + u32 res; + u32 src; + + FETCH_LONG(src); + res = DREGu32((Opcode >> 0) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 0) & 7) = res; + RET(16) +} + +/* ORI */ +OPCODE(0x0090) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* ORI */ +OPCODE(0x0098) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* ORI */ +OPCODE(0x00A0) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* ORI */ +OPCODE(0x00A8) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(32) +} + +/* ORI */ +OPCODE(0x00B0) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(34) +} + +/* ORI */ +OPCODE(0x00B8) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(32) +} + +/* ORI */ +OPCODE(0x00B9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + FETCH_LONG(adr); + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(36) +} + +/* ORI */ +OPCODE(0x009F) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* ORI */ +OPCODE(0x00A7) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* ORICCR */ +OPCODE(0x003C) +{ + u32 res; + + FETCH_BYTE(res); + res &= M68K_CCR_MASK; + res |= GET_CCR; + SET_CCR(res) + RET(20) +} + +/* ORISR */ +OPCODE(0x007C) +{ + + if (flag_S) + { + u32 res; + FETCH_WORD(res); + res &= M68K_SR_MASK; + res |= GET_SR; + SET_SR(res) + CHECK_INT_TO_JUMP(20) + } + else + { + u32 newPC = UNBASED_PC; + SET_PC(newPC-2); + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(20) +} + +/* ANDI */ +OPCODE(0x0200) +{ + u32 res; + u32 src; + + FETCH_BYTE(src); + res = DREGu8((Opcode >> 0) & 7); + res &= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 0) & 7) = res; + RET(8) +} + +/* ANDI */ +OPCODE(0x0210) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ANDI */ +OPCODE(0x0218) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ANDI */ +OPCODE(0x0220) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ANDI */ +OPCODE(0x0228) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* ANDI */ +OPCODE(0x0230) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* ANDI */ +OPCODE(0x0238) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* ANDI */ +OPCODE(0x0239) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* ANDI */ +OPCODE(0x021F) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ANDI */ +OPCODE(0x0227) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ANDI */ +OPCODE(0x0240) +{ + u32 res; + u32 src; + + FETCH_WORD(src); + res = DREGu16((Opcode >> 0) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 0) & 7) = res; + RET(8) +} + +/* ANDI */ +OPCODE(0x0250) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ANDI */ +OPCODE(0x0258) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ANDI */ +OPCODE(0x0260) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ANDI */ +OPCODE(0x0268) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ANDI */ +OPCODE(0x0270) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(22) +} + +/* ANDI */ +OPCODE(0x0278) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ANDI */ +OPCODE(0x0279) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + FETCH_LONG(adr); + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(24) +} + +/* ANDI */ +OPCODE(0x025F) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ANDI */ +OPCODE(0x0267) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ANDI */ +OPCODE(0x0280) +{ + u32 res; + u32 src; + + FETCH_LONG(src); + res = DREGu32((Opcode >> 0) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 0) & 7) = res; + RET(14) +} + +/* ANDI */ +OPCODE(0x0290) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* ANDI */ +OPCODE(0x0298) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* ANDI */ +OPCODE(0x02A0) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* ANDI */ +OPCODE(0x02A8) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(32) +} + +/* ANDI */ +OPCODE(0x02B0) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(34) +} + +/* ANDI */ +OPCODE(0x02B8) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(32) +} + +/* ANDI */ +OPCODE(0x02B9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + FETCH_LONG(adr); + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(36) +} + +/* ANDI */ +OPCODE(0x029F) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* ANDI */ +OPCODE(0x02A7) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* ANDICCR */ +OPCODE(0x023C) +{ + u32 res; + + FETCH_BYTE(res); + res &= M68K_CCR_MASK; + res &= GET_CCR; + SET_CCR(res) + RET(20) +} + +/* ANDISR */ +OPCODE(0x027C) +{ + u32 res; + + if (flag_S) + { + FETCH_WORD(res); + res &= M68K_SR_MASK; + res &= GET_SR; + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(20) + } + else + { + u32 newPC = UNBASED_PC; + SET_PC(newPC-2); + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(20) +} + +/* EORI */ +OPCODE(0x0A00) +{ + u32 res; + u32 src; + + FETCH_BYTE(src); + res = DREGu8((Opcode >> 0) & 7); + res ^= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 0) & 7) = res; + RET(8) +} + +/* EORI */ +OPCODE(0x0A10) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* EORI */ +OPCODE(0x0A18) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* EORI */ +OPCODE(0x0A20) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* EORI */ +OPCODE(0x0A28) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* EORI */ +OPCODE(0x0A30) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* EORI */ +OPCODE(0x0A38) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* EORI */ +OPCODE(0x0A39) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* EORI */ +OPCODE(0x0A1F) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* EORI */ +OPCODE(0x0A27) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* EORI */ +OPCODE(0x0A40) +{ + u32 res; + u32 src; + + FETCH_WORD(src); + res = DREGu16((Opcode >> 0) & 7); + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 0) & 7) = res; + RET(8) +} + +/* EORI */ +OPCODE(0x0A50) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* EORI */ +OPCODE(0x0A58) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* EORI */ +OPCODE(0x0A60) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* EORI */ +OPCODE(0x0A68) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* EORI */ +OPCODE(0x0A70) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(22) +} + +/* EORI */ +OPCODE(0x0A78) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* EORI */ +OPCODE(0x0A79) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + FETCH_LONG(adr); + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(24) +} + +/* EORI */ +OPCODE(0x0A5F) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* EORI */ +OPCODE(0x0A67) +{ + u32 adr, res; + u32 src; + + FETCH_WORD(src); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* EORI */ +OPCODE(0x0A80) +{ + u32 res; + u32 src; + + FETCH_LONG(src); + res = DREGu32((Opcode >> 0) & 7); + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 0) & 7) = res; + RET(16) +} + +/* EORI */ +OPCODE(0x0A90) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* EORI */ +OPCODE(0x0A98) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* EORI */ +OPCODE(0x0AA0) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* EORI */ +OPCODE(0x0AA8) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(32) +} + +/* EORI */ +OPCODE(0x0AB0) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(34) +} + +/* EORI */ +OPCODE(0x0AB8) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(32) +} + +/* EORI */ +OPCODE(0x0AB9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + FETCH_LONG(adr); + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(36) +} + +/* EORI */ +OPCODE(0x0A9F) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* EORI */ +OPCODE(0x0AA7) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(src); + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* EORICCR */ +OPCODE(0x0A3C) +{ + u32 res; + + FETCH_BYTE(res); + res &= M68K_CCR_MASK; + res ^= GET_CCR; + SET_CCR(res) + RET(20) +} + +/* EORISR */ +OPCODE(0x0A7C) +{ + u32 res; + + if (flag_S) + { + FETCH_WORD(res); + res &= M68K_SR_MASK; + res ^= GET_SR; + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(20) + } + else + { + u32 newPC = UNBASED_PC; + SET_PC(newPC-2); + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(20) +} + +/* SUBI */ +OPCODE(0x0400) +{ + u32 res; + u32 src, dst; + + FETCH_BYTE(src); + dst = DREGu8((Opcode >> 0) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(8) +} + +/* SUBI */ +OPCODE(0x0410) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* SUBI */ +OPCODE(0x0418) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* SUBI */ +OPCODE(0x0420) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* SUBI */ +OPCODE(0x0428) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* SUBI */ +OPCODE(0x0430) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* SUBI */ +OPCODE(0x0438) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + FETCH_SWORD(adr); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* SUBI */ +OPCODE(0x0439) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + FETCH_LONG(adr); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* SUBI */ +OPCODE(0x041F) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* SUBI */ +OPCODE(0x0427) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* SUBI */ +OPCODE(0x0440) +{ + u32 res; + u32 src, dst; + + FETCH_WORD(src); + dst = DREGu16((Opcode >> 0) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(8) +} + +/* SUBI */ +OPCODE(0x0450) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* SUBI */ +OPCODE(0x0458) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* SUBI */ +OPCODE(0x0460) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* SUBI */ +OPCODE(0x0468) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* SUBI */ +OPCODE(0x0470) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(22) +} + +/* SUBI */ +OPCODE(0x0478) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + FETCH_SWORD(adr); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* SUBI */ +OPCODE(0x0479) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + FETCH_LONG(adr); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(24) +} + +/* SUBI */ +OPCODE(0x045F) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* SUBI */ +OPCODE(0x0467) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* SUBI */ +OPCODE(0x0480) +{ + u32 res; + u32 src, dst; + + FETCH_LONG(src); + dst = DREGu32((Opcode >> 0) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 0) & 7) = res; + RET(16) +} + +/* SUBI */ +OPCODE(0x0490) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* SUBI */ +OPCODE(0x0498) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* SUBI */ +OPCODE(0x04A0) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* SUBI */ +OPCODE(0x04A8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(32) +} + +/* SUBI */ +OPCODE(0x04B0) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(34) +} + +/* SUBI */ +OPCODE(0x04B8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + FETCH_SWORD(adr); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(32) +} + +/* SUBI */ +OPCODE(0x04B9) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + FETCH_LONG(adr); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(36) +} + +/* SUBI */ +OPCODE(0x049F) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* SUBI */ +OPCODE(0x04A7) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* ADDI */ +OPCODE(0x0600) +{ + u32 res; + u32 src, dst; + + FETCH_BYTE(src); + dst = DREGu8((Opcode >> 0) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(8) +} + +/* ADDI */ +OPCODE(0x0610) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ADDI */ +OPCODE(0x0618) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ADDI */ +OPCODE(0x0620) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ADDI */ +OPCODE(0x0628) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* ADDI */ +OPCODE(0x0630) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* ADDI */ +OPCODE(0x0638) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + FETCH_SWORD(adr); + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* ADDI */ +OPCODE(0x0639) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + FETCH_LONG(adr); + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* ADDI */ +OPCODE(0x061F) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ADDI */ +OPCODE(0x0627) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ADDI */ +OPCODE(0x0640) +{ + u32 res; + u32 src, dst; + + FETCH_WORD(src); + dst = DREGu16((Opcode >> 0) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(8) +} + +/* ADDI */ +OPCODE(0x0650) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ADDI */ +OPCODE(0x0658) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ADDI */ +OPCODE(0x0660) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ADDI */ +OPCODE(0x0668) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ADDI */ +OPCODE(0x0670) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(22) +} + +/* ADDI */ +OPCODE(0x0678) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + FETCH_SWORD(adr); + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ADDI */ +OPCODE(0x0679) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + FETCH_LONG(adr); + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(24) +} + +/* ADDI */ +OPCODE(0x065F) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ADDI */ +OPCODE(0x0667) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ADDI */ +OPCODE(0x0680) +{ + u32 res; + u32 src, dst; + + FETCH_LONG(src); + dst = DREGu32((Opcode >> 0) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 0) & 7) = res; + RET(16) +} + +/* ADDI */ +OPCODE(0x0690) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* ADDI */ +OPCODE(0x0698) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* ADDI */ +OPCODE(0x06A0) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* ADDI */ +OPCODE(0x06A8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(32) +} + +/* ADDI */ +OPCODE(0x06B0) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(34) +} + +/* ADDI */ +OPCODE(0x06B8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + FETCH_SWORD(adr); + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(32) +} + +/* ADDI */ +OPCODE(0x06B9) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + FETCH_LONG(adr); + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(36) +} + +/* ADDI */ +OPCODE(0x069F) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* ADDI */ +OPCODE(0x06A7) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* CMPI */ +OPCODE(0x0C00) +{ + u32 res; + u32 src, dst; + + FETCH_BYTE(src); + dst = DREGu8((Opcode >> 0) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(8) +} + +/* CMPI */ +OPCODE(0x0C10) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(12) +} + +/* CMPI */ +OPCODE(0x0C18) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(12) +} + +/* CMPI */ +OPCODE(0x0C20) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(14) +} + +/* CMPI */ +OPCODE(0x0C28) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(16) +} + +/* CMPI */ +OPCODE(0x0C30) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(18) +} + +/* CMPI */ +OPCODE(0x0C38) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + FETCH_SWORD(adr); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(16) +} + +/* CMPI */ +OPCODE(0x0C39) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + FETCH_LONG(adr); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(20) +} + +/* CMPI */ +OPCODE(0x0C1F) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(12) +} + +/* CMPI */ +OPCODE(0x0C27) +{ + u32 adr, res; + u32 src, dst; + + FETCH_BYTE(src); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(14) +} + +/* CMPI */ +OPCODE(0x0C40) +{ + u32 res; + u32 src, dst; + + FETCH_WORD(src); + dst = DREGu16((Opcode >> 0) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(8) +} + +/* CMPI */ +OPCODE(0x0C50) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(12) +} + +/* CMPI */ +OPCODE(0x0C58) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(12) +} + +/* CMPI */ +OPCODE(0x0C60) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(14) +} + +/* CMPI */ +OPCODE(0x0C68) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(16) +} + +/* CMPI */ +OPCODE(0x0C70) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(18) +} + +/* CMPI */ +OPCODE(0x0C78) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + FETCH_SWORD(adr); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(16) +} + +/* CMPI */ +OPCODE(0x0C79) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + FETCH_LONG(adr); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(20) +} + +/* CMPI */ +OPCODE(0x0C5F) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(12) +} + +/* CMPI */ +OPCODE(0x0C67) +{ + u32 adr, res; + u32 src, dst; + + FETCH_WORD(src); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(14) +} + +/* CMPI */ +OPCODE(0x0C80) +{ + u32 res; + u32 src, dst; + + FETCH_LONG(src); + dst = DREGu32((Opcode >> 0) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(14) +} + +/* CMPI */ +OPCODE(0x0C90) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(20) +} + +/* CMPI */ +OPCODE(0x0C98) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(20) +} + +/* CMPI */ +OPCODE(0x0CA0) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(22) +} + +/* CMPI */ +OPCODE(0x0CA8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(24) +} + +/* CMPI */ +OPCODE(0x0CB0) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(26) +} + +/* CMPI */ +OPCODE(0x0CB8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + FETCH_SWORD(adr); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(24) +} + +/* CMPI */ +OPCODE(0x0CB9) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + FETCH_LONG(adr); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(28) +} + +/* CMPI */ +OPCODE(0x0C9F) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(20) +} + +/* CMPI */ +OPCODE(0x0CA7) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(src); + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(22) +} + +/* BTSTn */ +OPCODE(0x0800) +{ + u32 res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 31); + res = DREGu32((Opcode >> 0) & 7); + flag_NotZ = res & src; + RET(10) +} + +/* BTSTn */ +OPCODE(0x0810) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(12) +} + +/* BTSTn */ +OPCODE(0x0818) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(12) +} + +/* BTSTn */ +OPCODE(0x0820) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(14) +} + +/* BTSTn */ +OPCODE(0x0828) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(16) +} + +/* BTSTn */ +OPCODE(0x0830) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(18) +} + +/* BTSTn */ +OPCODE(0x0838) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(16) +} + +/* BTSTn */ +OPCODE(0x0839) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(20) +} + +/* BTSTn */ +OPCODE(0x083A) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(16) +} + +/* BTSTn */ +OPCODE(0x083B) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(18) +} + +/* BTSTn */ +OPCODE(0x081F) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(12) +} + +/* BTSTn */ +OPCODE(0x0827) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(14) +} + +/* BCHGn */ +OPCODE(0x0840) +{ + u32 res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 31); + res = DREGu32((Opcode >> 0) & 7); + flag_NotZ = res & src; + res ^= src; + DREGu32((Opcode >> 0) & 7) = res; + RET(12) +} + +/* BCHGn */ +OPCODE(0x0850) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BCHGn */ +OPCODE(0x0858) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BCHGn */ +OPCODE(0x0860) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* BCHGn */ +OPCODE(0x0868) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* BCHGn */ +OPCODE(0x0870) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* BCHGn */ +OPCODE(0x0878) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* BCHGn */ +OPCODE(0x0879) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* BCHGn */ +OPCODE(0x085F) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BCHGn */ +OPCODE(0x0867) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* BCLRn */ +OPCODE(0x0880) +{ + u32 res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 31); + res = DREGu32((Opcode >> 0) & 7); + flag_NotZ = res & src; + res &= ~src; + DREGu32((Opcode >> 0) & 7) = res; + RET(14) +} + +/* BCLRn */ +OPCODE(0x0890) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BCLRn */ +OPCODE(0x0898) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BCLRn */ +OPCODE(0x08A0) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* BCLRn */ +OPCODE(0x08A8) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* BCLRn */ +OPCODE(0x08B0) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* BCLRn */ +OPCODE(0x08B8) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* BCLRn */ +OPCODE(0x08B9) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* BCLRn */ +OPCODE(0x089F) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BCLRn */ +OPCODE(0x08A7) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* BSETn */ +OPCODE(0x08C0) +{ + u32 res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 31); + res = DREGu32((Opcode >> 0) & 7); + flag_NotZ = res & src; + res |= src; + DREGu32((Opcode >> 0) & 7) = res; + RET(12) +} + +/* BSETn */ +OPCODE(0x08D0) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BSETn */ +OPCODE(0x08D8) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BSETn */ +OPCODE(0x08E0) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* BSETn */ +OPCODE(0x08E8) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* BSETn */ +OPCODE(0x08F0) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* BSETn */ +OPCODE(0x08F8) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* BSETn */ +OPCODE(0x08F9) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* BSETn */ +OPCODE(0x08DF) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BSETn */ +OPCODE(0x08E7) +{ + u32 adr, res; + u32 src; + + FETCH_BYTE(src); + src = 1 << (src & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* BTST */ +OPCODE(0x0100) +{ + u32 res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + src = 1 << (src & 31); + res = DREGu32((Opcode >> 0) & 7); + flag_NotZ = res & src; + RET(6) +} + +/* BTST */ +OPCODE(0x0110) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(8) +} + +/* BTST */ +OPCODE(0x0118) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(8) +} + +/* BTST */ +OPCODE(0x0120) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(10) +} + +/* BTST */ +OPCODE(0x0128) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(12) +} + +/* BTST */ +OPCODE(0x0130) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(14) +} + +/* BTST */ +OPCODE(0x0138) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(12) +} + +/* BTST */ +OPCODE(0x0139) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(16) +} + +/* BTST */ +OPCODE(0x013A) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(12) +} + +/* BTST */ +OPCODE(0x013B) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(14) +} + +/* BTST */ +OPCODE(0x013C) +{ + u32 res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + FETCH_BYTE(res); + flag_NotZ = res & src; + RET(8) +} + +/* BTST */ +OPCODE(0x011F) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(8) +} + +/* BTST */ +OPCODE(0x0127) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + RET(10) +} + +/* BCHG */ +OPCODE(0x0140) +{ + u32 res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + src = 1 << (src & 31); + res = DREGu32((Opcode >> 0) & 7); + flag_NotZ = res & src; + res ^= src; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) +} + +/* BCHG */ +OPCODE(0x0150) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* BCHG */ +OPCODE(0x0158) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* BCHG */ +OPCODE(0x0160) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* BCHG */ +OPCODE(0x0168) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BCHG */ +OPCODE(0x0170) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* BCHG */ +OPCODE(0x0178) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BCHG */ +OPCODE(0x0179) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* BCHG */ +OPCODE(0x015F) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* BCHG */ +OPCODE(0x0167) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* BCLR */ +OPCODE(0x0180) +{ + u32 res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + src = 1 << (src & 31); + res = DREGu32((Opcode >> 0) & 7); + flag_NotZ = res & src; + res &= ~src; + DREGu32((Opcode >> 0) & 7) = res; + RET(10) +} + +/* BCLR */ +OPCODE(0x0190) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* BCLR */ +OPCODE(0x0198) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* BCLR */ +OPCODE(0x01A0) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* BCLR */ +OPCODE(0x01A8) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BCLR */ +OPCODE(0x01B0) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* BCLR */ +OPCODE(0x01B8) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BCLR */ +OPCODE(0x01B9) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* BCLR */ +OPCODE(0x019F) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* BCLR */ +OPCODE(0x01A7) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* BSET */ +OPCODE(0x01C0) +{ + u32 res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + src = 1 << (src & 31); + res = DREGu32((Opcode >> 0) & 7); + flag_NotZ = res & src; + res |= src; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) +} + +/* BSET */ +OPCODE(0x01D0) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* BSET */ +OPCODE(0x01D8) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* BSET */ +OPCODE(0x01E0) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* BSET */ +OPCODE(0x01E8) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BSET */ +OPCODE(0x01F0) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* BSET */ +OPCODE(0x01F8) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* BSET */ +OPCODE(0x01F9) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* BSET */ +OPCODE(0x01DF) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* BSET */ +OPCODE(0x01E7) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + src = 1 << (src & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + flag_NotZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* MOVEPWaD */ +OPCODE(0x0108) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr + 0, res) + READ_BYTE_F(adr + 2, src) + DREGu16((Opcode >> 9) & 7) = (res << 8) | src; + RET(16) +} + +/* MOVEPLaD */ +OPCODE(0x0148) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res <<= 24; + adr += 2; + READ_BYTE_F(adr, src) + res |= src << 16; + adr += 2; + READ_BYTE_F(adr, src) + res |= src << 8; + adr += 2; + READ_BYTE_F(adr, src) + DREG((Opcode >> 9) & 7) = res | src; + RET(24) +} + +/* MOVEPWDa */ +OPCODE(0x0188) +{ + u32 adr, res; + + res = DREGu32((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + WRITE_BYTE_F(adr + 0, res >> 8) + WRITE_BYTE_F(adr + 2, res >> 0) + RET(16) +} + +/* MOVEPLDa */ +OPCODE(0x01C8) +{ + u32 adr, res; + + res = DREGu32((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + WRITE_BYTE_F(adr, res >> 24) + adr += 2; + WRITE_BYTE_F(adr, res >> 16) + adr += 2; + WRITE_BYTE_F(adr, res >> 8) + adr += 2; + WRITE_BYTE_F(adr, res >> 0) + RET(24) +} + +/* MOVEB */ +OPCODE(0x1000) +{ + u32 res; + + res = DREGu8((Opcode >> 0) & 7); + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(4) +} + +/* MOVEB */ +OPCODE(0x1080) +{ + u32 adr, res; + + res = DREGu8((Opcode >> 0) & 7); + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(8) +} + +/* MOVEB */ +OPCODE(0x10C0) +{ + u32 adr, res; + + res = DREGu8((Opcode >> 0) & 7); + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + WRITE_BYTE_F(adr, res) + RET(8) +} + +/* MOVEB */ +OPCODE(0x1100) +{ + u32 adr, res; + + res = DREGu8((Opcode >> 0) & 7); + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + WRITE_BYTE_F(adr, res) + RET(8) +} + +/* MOVEB */ +OPCODE(0x1140) +{ + u32 adr, res; + + res = DREGu8((Opcode >> 0) & 7); + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x1180) +{ + u32 adr, res; + + res = DREGu8((Opcode >> 0) & 7); + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* MOVEB */ +OPCODE(0x11C0) +{ + u32 adr, res; + + res = DREGu8((Opcode >> 0) & 7); + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x13C0) +{ + u32 adr, res; + + res = DREGu8((Opcode >> 0) & 7); + SET_FLAGS_NZ_VC0 + FETCH_LONG(adr); + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x1EC0) +{ + u32 adr, res; + + res = DREGu8((Opcode >> 0) & 7); + SET_FLAGS_NZ_VC0 + adr = AREG(7); + AREG(7) += 2; + WRITE_BYTE_F(adr, res) + RET(8) +} + +/* MOVEB */ +OPCODE(0x1F00) +{ + u32 adr, res; + + res = DREGu8((Opcode >> 0) & 7); + SET_FLAGS_NZ_VC0 + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_BYTE_F(adr, res) + RET(8) +} + +/* MOVEB */ +OPCODE(0x1008) +{ +#if 0 + /* can't read byte from Ax registers ! */ + m68kcontext.execinfo |= M68K_FAULTED; + io_cycle_counter = 0; + /* + goto famec_Exec_End; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + */ +#endif + RET(4) +} + +/* MOVEB */ +OPCODE(0x1088) +{ +#if 0 + /* can't read byte from Ax registers ! */ + m68kcontext.execinfo |= M68K_FAULTED; + io_cycle_counter = 0; + /* + goto famec_Exec_End; + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + */ +#endif + RET(8) +} + +/* MOVEB */ +OPCODE(0x10C8) +{ +#if 0 + /* can't read byte from Ax registers ! */ + m68kcontext.execinfo |= M68K_FAULTED; + io_cycle_counter = 0; + /* + goto famec_Exec_End; + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + WRITE_BYTE_F(adr, res) + */ +#endif + RET(8) +} + +/* MOVEB */ +OPCODE(0x1108) +{ +#if 0 + /* can't read byte from Ax registers ! */ + m68kcontext.execinfo |= M68K_FAULTED; + io_cycle_counter = 0; + /* + goto famec_Exec_End; + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + WRITE_BYTE_F(adr, res) + */ +#endif + RET(8) +} + +/* MOVEB */ +OPCODE(0x1148) +{ +#if 0 + /* can't read byte from Ax registers ! */ + m68kcontext.execinfo |= M68K_FAULTED; + io_cycle_counter = 0; + /* + goto famec_Exec_End; + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + */ +#endif + RET(12) +} + +/* MOVEB */ +OPCODE(0x1188) +{ +#if 0 + /* can't read byte from Ax registers ! */ + m68kcontext.execinfo |= M68K_FAULTED; + io_cycle_counter = 0; + /* + goto famec_Exec_End; + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + */ +#endif + RET(14) +} + +/* MOVEB */ +OPCODE(0x11C8) +{ +#if 0 + /* can't read byte from Ax registers ! */ + m68kcontext.execinfo |= M68K_FAULTED; + io_cycle_counter = 0; + /* + goto famec_Exec_End; + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + WRITE_BYTE_F(adr, res) + */ +#endif + RET(12) +} + +/* MOVEB */ +OPCODE(0x13C8) +{ +#if 0 + /* can't read byte from Ax registers ! */ + m68kcontext.execinfo |= M68K_FAULTED; + io_cycle_counter = 0; + /* + goto famec_Exec_End; + SET_FLAGS_NZ_VC0 + FETCH_LONG(adr); + WRITE_BYTE_F(adr, res) + */ +#endif + RET(16) +} + +/* MOVEB */ +OPCODE(0x1EC8) +{ +#if 0 + /* can't read byte from Ax registers ! */ + m68kcontext.execinfo |= M68K_FAULTED; + io_cycle_counter = 0; + /* + goto famec_Exec_End; + SET_FLAGS_NZ_VC0 + adr = AREG(7); + AREG(7) += 2; + WRITE_BYTE_F(adr, res) + */ +#endif + RET(8) +} + +/* MOVEB */ +OPCODE(0x1F08) +{ +#if 0 + /* can't read byte from Ax registers ! */ + m68kcontext.execinfo |= M68K_FAULTED; + io_cycle_counter = 0; + /* + goto famec_Exec_End; + SET_FLAGS_NZ_VC0 + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_BYTE_F(adr, res) + */ +#endif + RET(8) +} + +/* MOVEB */ +OPCODE(0x1010) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* MOVEB */ +OPCODE(0x1090) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x10D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x1110) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x1150) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x1190) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x11D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x13D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_LONG(adr); + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x1ED0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7); + AREG(7) += 2; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x1F10) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x1018) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* MOVEB */ +OPCODE(0x1098) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x10D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x1118) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x1158) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x1198) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x11D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x13D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_LONG(adr); + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x1ED8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7); + AREG(7) += 2; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x1F18) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x1020) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(10) +} + +/* MOVEB */ +OPCODE(0x10A0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* MOVEB */ +OPCODE(0x10E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* MOVEB */ +OPCODE(0x1120) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* MOVEB */ +OPCODE(0x1160) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x11A0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x11E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x13E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_LONG(adr); + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* MOVEB */ +OPCODE(0x1EE0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7); + AREG(7) += 2; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* MOVEB */ +OPCODE(0x1F20) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* MOVEB */ +OPCODE(0x1028) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEB */ +OPCODE(0x10A8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x10E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x1128) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x1168) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x11A8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* MOVEB */ +OPCODE(0x11E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x13E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_LONG(adr); + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* MOVEB */ +OPCODE(0x1EE8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7); + AREG(7) += 2; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x1F28) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x1030) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(14) +} + +/* MOVEB */ +OPCODE(0x10B0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x10F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x1130) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x1170) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* MOVEB */ +OPCODE(0x11B0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* MOVEB */ +OPCODE(0x11F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* MOVEB */ +OPCODE(0x13F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_LONG(adr); + WRITE_BYTE_F(adr, res) + RET(26) +} + +/* MOVEB */ +OPCODE(0x1EF0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7); + AREG(7) += 2; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x1F30) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x1038) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEB */ +OPCODE(0x10B8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x10F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x1138) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x1178) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x11B8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* MOVEB */ +OPCODE(0x11F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x13F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_LONG(adr); + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* MOVEB */ +OPCODE(0x1EF8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7); + AREG(7) += 2; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x1F38) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x1039) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(16) +} + +/* MOVEB */ +OPCODE(0x10B9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x10F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x1139) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x1179) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* MOVEB */ +OPCODE(0x11B9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + RET(26) +} + +/* MOVEB */ +OPCODE(0x11F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* MOVEB */ +OPCODE(0x13F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_LONG(adr); + WRITE_BYTE_F(adr, res) + RET(28) +} + +/* MOVEB */ +OPCODE(0x1EF9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7); + AREG(7) += 2; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x1F39) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x103A) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEB */ +OPCODE(0x10BA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x10FA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x113A) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x117A) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x11BA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* MOVEB */ +OPCODE(0x11FA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x13FA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_LONG(adr); + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* MOVEB */ +OPCODE(0x1EFA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7); + AREG(7) += 2; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x1F3A) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x103B) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(14) +} + +/* MOVEB */ +OPCODE(0x10BB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x10FB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x113B) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x117B) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* MOVEB */ +OPCODE(0x11BB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + RET(24) +} + +/* MOVEB */ +OPCODE(0x11FB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* MOVEB */ +OPCODE(0x13FB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_LONG(adr); + WRITE_BYTE_F(adr, res) + RET(26) +} + +/* MOVEB */ +OPCODE(0x1EFB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7); + AREG(7) += 2; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x1F3B) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x103C) +{ + u32 res; + + FETCH_BYTE(res); + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* MOVEB */ +OPCODE(0x10BC) +{ + u32 adr, res; + + FETCH_BYTE(res); + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x10FC) +{ + u32 adr, res; + + FETCH_BYTE(res); + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x113C) +{ + u32 adr, res; + + FETCH_BYTE(res); + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x117C) +{ + u32 adr, res; + + FETCH_BYTE(res); + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x11BC) +{ + u32 adr, res; + + FETCH_BYTE(res); + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x11FC) +{ + u32 adr, res; + + FETCH_BYTE(res); + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x13FC) +{ + u32 adr, res; + + FETCH_BYTE(res); + SET_FLAGS_NZ_VC0 + FETCH_LONG(adr); + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x1EFC) +{ + u32 adr, res; + + FETCH_BYTE(res); + SET_FLAGS_NZ_VC0 + adr = AREG(7); + AREG(7) += 2; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x1F3C) +{ + u32 adr, res; + + FETCH_BYTE(res); + SET_FLAGS_NZ_VC0 + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x101F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* MOVEB */ +OPCODE(0x109F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x10DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x111F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x115F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x119F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x11DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* MOVEB */ +OPCODE(0x13DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_LONG(adr); + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x1EDF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7); + AREG(7) += 2; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x1F1F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* MOVEB */ +OPCODE(0x1027) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(10) +} + +/* MOVEB */ +OPCODE(0x10A7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* MOVEB */ +OPCODE(0x10E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* MOVEB */ +OPCODE(0x1127) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* MOVEB */ +OPCODE(0x1167) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x11A7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* MOVEB */ +OPCODE(0x11E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_SWORD(adr); + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MOVEB */ +OPCODE(0x13E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + FETCH_LONG(adr); + WRITE_BYTE_F(adr, res) + RET(22) +} + +/* MOVEB */ +OPCODE(0x1EE7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7); + AREG(7) += 2; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* MOVEB */ +OPCODE(0x1F27) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* MOVEL */ +OPCODE(0x2000) +{ + u32 res; + + res = DREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(4) +} + +/* MOVEL */ +OPCODE(0x2080) +{ + u32 adr, res; + + res = DREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(12) +} + +/* MOVEL */ +OPCODE(0x20C0) +{ + u32 adr, res; + + res = DREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + WRITE_LONG_F(adr, res) + RET(12) +} + +/* MOVEL */ +OPCODE(0x2100) +{ + u32 adr, res; + + res = DREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(12) +} + +/* MOVEL */ +OPCODE(0x2140) +{ + u32 adr, res; + + res = DREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(16) +} + +/* MOVEL */ +OPCODE(0x2180) +{ + u32 adr, res; + + res = DREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + RET(18) +} + +/* MOVEL */ +OPCODE(0x21C0) +{ + u32 adr, res; + + res = DREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + WRITE_LONG_F(adr, res) + RET(16) +} + +/* MOVEL */ +OPCODE(0x23C0) +{ + u32 adr, res; + + res = DREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_LONG(adr); + WRITE_LONG_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x2EC0) +{ + u32 adr, res; + + res = DREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7); + AREG(7) += 4; + WRITE_LONG_F(adr, res) + RET(12) +} + +/* MOVEL */ +OPCODE(0x2F00) +{ + u32 adr, res; + + res = DREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7) - 4; + AREG(7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(12) +} + +/* MOVEL */ +OPCODE(0x2008) +{ + u32 res; + + res = AREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(4) +} + +/* MOVEL */ +OPCODE(0x2088) +{ + u32 adr, res; + + res = AREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(12) +} + +/* MOVEL */ +OPCODE(0x20C8) +{ + u32 adr, res; + + res = AREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + WRITE_LONG_F(adr, res) + RET(12) +} + +/* MOVEL */ +OPCODE(0x2108) +{ + u32 adr, res; + + res = AREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(12) +} + +/* MOVEL */ +OPCODE(0x2148) +{ + u32 adr, res; + + res = AREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(16) +} + +/* MOVEL */ +OPCODE(0x2188) +{ + u32 adr, res; + + res = AREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + RET(18) +} + +/* MOVEL */ +OPCODE(0x21C8) +{ + u32 adr, res; + + res = AREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + WRITE_LONG_F(adr, res) + RET(16) +} + +/* MOVEL */ +OPCODE(0x23C8) +{ + u32 adr, res; + + res = AREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_LONG(adr); + WRITE_LONG_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x2EC8) +{ + u32 adr, res; + + res = AREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7); + AREG(7) += 4; + WRITE_LONG_F(adr, res) + RET(12) +} + +/* MOVEL */ +OPCODE(0x2F08) +{ + u32 adr, res; + + res = AREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7) - 4; + AREG(7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(12) +} + +/* MOVEL */ +OPCODE(0x2010) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEL */ +OPCODE(0x2090) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x20D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x2110) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x2150) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x2190) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x21D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x23D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_LONG(adr); + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x2ED0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7); + AREG(7) += 4; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x2F10) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7) - 4; + AREG(7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x2018) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEL */ +OPCODE(0x2098) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x20D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x2118) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x2158) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x2198) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x21D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x23D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_LONG(adr); + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x2ED8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7); + AREG(7) += 4; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x2F18) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7) - 4; + AREG(7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x2020) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(14) +} + +/* MOVEL */ +OPCODE(0x20A0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(22) +} + +/* MOVEL */ +OPCODE(0x20E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* MOVEL */ +OPCODE(0x2120) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(22) +} + +/* MOVEL */ +OPCODE(0x2160) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x21A0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x21E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + WRITE_LONG_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x23E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_LONG(adr); + WRITE_LONG_F(adr, res) + RET(30) +} + +/* MOVEL */ +OPCODE(0x2EE0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7); + AREG(7) += 4; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* MOVEL */ +OPCODE(0x2F20) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7) - 4; + AREG(7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(22) +} + +/* MOVEL */ +OPCODE(0x2028) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* MOVEL */ +OPCODE(0x20A8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x20E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x2128) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x2168) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x21A8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + RET(30) +} + +/* MOVEL */ +OPCODE(0x21E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x23E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_LONG(adr); + WRITE_LONG_F(adr, res) + RET(32) +} + +/* MOVEL */ +OPCODE(0x2EE8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7); + AREG(7) += 4; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x2F28) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7) - 4; + AREG(7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x2030) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(18) +} + +/* MOVEL */ +OPCODE(0x20B0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x20F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + WRITE_LONG_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x2130) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x2170) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(30) +} + +/* MOVEL */ +OPCODE(0x21B0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + RET(32) +} + +/* MOVEL */ +OPCODE(0x21F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + WRITE_LONG_F(adr, res) + RET(30) +} + +/* MOVEL */ +OPCODE(0x23F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_LONG(adr); + WRITE_LONG_F(adr, res) + RET(34) +} + +/* MOVEL */ +OPCODE(0x2EF0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7); + AREG(7) += 4; + WRITE_LONG_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x2F30) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7) - 4; + AREG(7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x2038) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* MOVEL */ +OPCODE(0x20B8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x20F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x2138) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x2178) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x21B8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + RET(30) +} + +/* MOVEL */ +OPCODE(0x21F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x23F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_LONG(adr); + WRITE_LONG_F(adr, res) + RET(32) +} + +/* MOVEL */ +OPCODE(0x2EF8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7); + AREG(7) += 4; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x2F38) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7) - 4; + AREG(7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x2039) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(20) +} + +/* MOVEL */ +OPCODE(0x20B9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x20F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x2139) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x2179) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(32) +} + +/* MOVEL */ +OPCODE(0x21B9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + RET(34) +} + +/* MOVEL */ +OPCODE(0x21F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + WRITE_LONG_F(adr, res) + RET(32) +} + +/* MOVEL */ +OPCODE(0x23F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_LONG(adr); + WRITE_LONG_F(adr, res) + RET(36) +} + +/* MOVEL */ +OPCODE(0x2EF9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7); + AREG(7) += 4; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x2F39) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7) - 4; + AREG(7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x203A) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* MOVEL */ +OPCODE(0x20BA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x20FA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x213A) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x217A) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x21BA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + RET(30) +} + +/* MOVEL */ +OPCODE(0x21FA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x23FA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_LONG(adr); + WRITE_LONG_F(adr, res) + RET(32) +} + +/* MOVEL */ +OPCODE(0x2EFA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7); + AREG(7) += 4; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x2F3A) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7) - 4; + AREG(7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x203B) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(18) +} + +/* MOVEL */ +OPCODE(0x20BB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x20FB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + WRITE_LONG_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x213B) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x217B) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(30) +} + +/* MOVEL */ +OPCODE(0x21BB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + RET(32) +} + +/* MOVEL */ +OPCODE(0x21FB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + WRITE_LONG_F(adr, res) + RET(30) +} + +/* MOVEL */ +OPCODE(0x23FB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_LONG(adr); + WRITE_LONG_F(adr, res) + RET(34) +} + +/* MOVEL */ +OPCODE(0x2EFB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7); + AREG(7) += 4; + WRITE_LONG_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x2F3B) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7) - 4; + AREG(7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x203C) +{ + u32 res; + + FETCH_LONG(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEL */ +OPCODE(0x20BC) +{ + u32 adr, res; + + FETCH_LONG(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x20FC) +{ + u32 adr, res; + + FETCH_LONG(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x213C) +{ + u32 adr, res; + + FETCH_LONG(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x217C) +{ + u32 adr, res; + + FETCH_LONG(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x21BC) +{ + u32 adr, res; + + FETCH_LONG(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x21FC) +{ + u32 adr, res; + + FETCH_LONG(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x23FC) +{ + u32 adr, res; + + FETCH_LONG(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_LONG(adr); + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x2EFC) +{ + u32 adr, res; + + FETCH_LONG(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7); + AREG(7) += 4; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x2F3C) +{ + u32 adr, res; + + FETCH_LONG(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7) - 4; + AREG(7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x201F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEL */ +OPCODE(0x209F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x20DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x211F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x215F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x219F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x21DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + WRITE_LONG_F(adr, res) + RET(24) +} + +/* MOVEL */ +OPCODE(0x23DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_LONG(adr); + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x2EDF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7); + AREG(7) += 4; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x2F1F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7) - 4; + AREG(7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(20) +} + +/* MOVEL */ +OPCODE(0x2027) +{ + u32 adr, res; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(14) +} + +/* MOVEL */ +OPCODE(0x20A7) +{ + u32 adr, res; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(22) +} + +/* MOVEL */ +OPCODE(0x20E7) +{ + u32 adr, res; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* MOVEL */ +OPCODE(0x2127) +{ + u32 adr, res; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(22) +} + +/* MOVEL */ +OPCODE(0x2167) +{ + u32 adr, res; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_LONG_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x21A7) +{ + u32 adr, res; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + RET(28) +} + +/* MOVEL */ +OPCODE(0x21E7) +{ + u32 adr, res; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_SWORD(adr); + WRITE_LONG_F(adr, res) + RET(26) +} + +/* MOVEL */ +OPCODE(0x23E7) +{ + u32 adr, res; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + FETCH_LONG(adr); + WRITE_LONG_F(adr, res) + RET(30) +} + +/* MOVEL */ +OPCODE(0x2EE7) +{ + u32 adr, res; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7); + AREG(7) += 4; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* MOVEL */ +OPCODE(0x2F27) +{ + u32 adr, res; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + adr = AREG(7) - 4; + AREG(7) = adr; + WRITE_LONG_DEC_F(adr, res) + RET(22) +} + +/* MOVEAL */ +OPCODE(0x2040) +{ + u32 res; + + res = (s32)DREGs32((Opcode >> 0) & 7); + AREG((Opcode >> 9) & 7) = res; + RET(4) +} + +/* MOVEAL */ +OPCODE(0x2048) +{ + u32 res; + + res = (s32)AREGs32((Opcode >> 0) & 7); + AREG((Opcode >> 9) & 7) = res; + RET(4) +} + +/* MOVEAL */ +OPCODE(0x2050) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READSX_LONG_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEAL */ +OPCODE(0x2058) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READSX_LONG_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEAL */ +OPCODE(0x2060) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READSX_LONG_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(14) +} + +/* MOVEAL */ +OPCODE(0x2068) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READSX_LONG_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* MOVEAL */ +OPCODE(0x2070) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READSX_LONG_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(18) +} + +/* MOVEAL */ +OPCODE(0x2078) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READSX_LONG_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* MOVEAL */ +OPCODE(0x2079) +{ + u32 adr, res; + + FETCH_LONG(adr); + READSX_LONG_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(20) +} + +/* MOVEAL */ +OPCODE(0x207A) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READSX_LONG_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* MOVEAL */ +OPCODE(0x207B) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READSX_LONG_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(18) +} + +/* MOVEAL */ +OPCODE(0x207C) +{ + u32 res; + + FETCH_LONG(res); + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEAL */ +OPCODE(0x205F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 4; + READSX_LONG_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEAL */ +OPCODE(0x2067) +{ + u32 adr, res; + + adr = AREG(7) - 4; + AREG(7) = adr; + READSX_LONG_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(14) +} + +/* MOVEW */ +OPCODE(0x3000) +{ + u32 res; + + res = DREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(4) +} + +/* MOVEW */ +OPCODE(0x3080) +{ + u32 adr, res; + + res = DREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(8) +} + +/* MOVEW */ +OPCODE(0x30C0) +{ + u32 adr, res; + + res = DREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(8) +} + +/* MOVEW */ +OPCODE(0x3100) +{ + u32 adr, res; + + res = DREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(8) +} + +/* MOVEW */ +OPCODE(0x3140) +{ + u32 adr, res; + + res = DREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x3180) +{ + u32 adr, res; + + res = DREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(14) +} + +/* MOVEW */ +OPCODE(0x31C0) +{ + u32 adr, res; + + res = DREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x33C0) +{ + u32 adr, res; + + res = DREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x3EC0) +{ + u32 adr, res; + + res = DREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(8) +} + +/* MOVEW */ +OPCODE(0x3F00) +{ + u32 adr, res; + + res = DREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(8) +} + +/* MOVEW */ +OPCODE(0x3008) +{ + u32 res; + + res = AREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(4) +} + +/* MOVEW */ +OPCODE(0x3088) +{ + u32 adr, res; + + res = AREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(8) +} + +/* MOVEW */ +OPCODE(0x30C8) +{ + u32 adr, res; + + res = AREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(8) +} + +/* MOVEW */ +OPCODE(0x3108) +{ + u32 adr, res; + + res = AREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(8) +} + +/* MOVEW */ +OPCODE(0x3148) +{ + u32 adr, res; + + res = AREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x3188) +{ + u32 adr, res; + + res = AREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(14) +} + +/* MOVEW */ +OPCODE(0x31C8) +{ + u32 adr, res; + + res = AREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x33C8) +{ + u32 adr, res; + + res = AREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x3EC8) +{ + u32 adr, res; + + res = AREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(8) +} + +/* MOVEW */ +OPCODE(0x3F08) +{ + u32 adr, res; + + res = AREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(8) +} + +/* MOVEW */ +OPCODE(0x3010) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* MOVEW */ +OPCODE(0x3090) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x30D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x3110) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x3150) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x3190) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x31D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x33D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x3ED0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x3F10) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x3018) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* MOVEW */ +OPCODE(0x3098) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x30D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x3118) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x3158) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x3198) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x31D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x33D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x3ED8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x3F18) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x3020) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(10) +} + +/* MOVEW */ +OPCODE(0x30A0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(14) +} + +/* MOVEW */ +OPCODE(0x30E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* MOVEW */ +OPCODE(0x3120) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* MOVEW */ +OPCODE(0x3160) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x31A0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x31E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x33E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(22) +} + +/* MOVEW */ +OPCODE(0x3EE0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* MOVEW */ +OPCODE(0x3F20) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* MOVEW */ +OPCODE(0x3028) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEW */ +OPCODE(0x30A8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x30E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x3128) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x3168) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x31A8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(22) +} + +/* MOVEW */ +OPCODE(0x31E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x33E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(24) +} + +/* MOVEW */ +OPCODE(0x3EE8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x3F28) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x3030) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(14) +} + +/* MOVEW */ +OPCODE(0x30B0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x30F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x3130) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x3170) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(22) +} + +/* MOVEW */ +OPCODE(0x31B0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(24) +} + +/* MOVEW */ +OPCODE(0x31F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(22) +} + +/* MOVEW */ +OPCODE(0x33F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(26) +} + +/* MOVEW */ +OPCODE(0x3EF0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x3F30) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x3038) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEW */ +OPCODE(0x30B8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x30F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x3138) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x3178) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x31B8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(22) +} + +/* MOVEW */ +OPCODE(0x31F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x33F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(24) +} + +/* MOVEW */ +OPCODE(0x3EF8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x3F38) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x3039) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(16) +} + +/* MOVEW */ +OPCODE(0x30B9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x30F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x3139) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x3179) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(24) +} + +/* MOVEW */ +OPCODE(0x31B9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(26) +} + +/* MOVEW */ +OPCODE(0x31F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(24) +} + +/* MOVEW */ +OPCODE(0x33F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(28) +} + +/* MOVEW */ +OPCODE(0x3EF9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x3F39) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x303A) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEW */ +OPCODE(0x30BA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x30FA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x313A) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x317A) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x31BA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(22) +} + +/* MOVEW */ +OPCODE(0x31FA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x33FA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(24) +} + +/* MOVEW */ +OPCODE(0x3EFA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x3F3A) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x303B) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(14) +} + +/* MOVEW */ +OPCODE(0x30BB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x30FB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x313B) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x317B) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(22) +} + +/* MOVEW */ +OPCODE(0x31BB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(24) +} + +/* MOVEW */ +OPCODE(0x31FB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(22) +} + +/* MOVEW */ +OPCODE(0x33FB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(26) +} + +/* MOVEW */ +OPCODE(0x3EFB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x3F3B) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x303C) +{ + u32 res; + + FETCH_WORD(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* MOVEW */ +OPCODE(0x30BC) +{ + u32 adr, res; + + FETCH_WORD(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x30FC) +{ + u32 adr, res; + + FETCH_WORD(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x313C) +{ + u32 adr, res; + + FETCH_WORD(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x317C) +{ + u32 adr, res; + + FETCH_WORD(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x31BC) +{ + u32 adr, res; + + FETCH_WORD(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x31FC) +{ + u32 adr, res; + + FETCH_WORD(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x33FC) +{ + u32 adr, res; + + FETCH_WORD(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x3EFC) +{ + u32 adr, res; + + FETCH_WORD(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x3F3C) +{ + u32 adr, res; + + FETCH_WORD(res); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x301F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* MOVEW */ +OPCODE(0x309F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x30DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x311F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x315F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x319F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x31DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVEW */ +OPCODE(0x33DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x3EDF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x3F1F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVEW */ +OPCODE(0x3027) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(10) +} + +/* MOVEW */ +OPCODE(0x30A7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(14) +} + +/* MOVEW */ +OPCODE(0x30E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* MOVEW */ +OPCODE(0x3127) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* MOVEW */ +OPCODE(0x3167) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 9) & 7); + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x31A7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG((Opcode >> 9) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVEW */ +OPCODE(0x31E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVEW */ +OPCODE(0x33E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(22) +} + +/* MOVEW */ +OPCODE(0x3EE7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* MOVEW */ +OPCODE(0x3F27) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* MOVEAW */ +OPCODE(0x3040) +{ + u32 res; + + res = (s32)DREGs16((Opcode >> 0) & 7); + AREG((Opcode >> 9) & 7) = res; + RET(4) +} + +/* MOVEAW */ +OPCODE(0x3048) +{ + u32 res; + + res = (s32)AREGs16((Opcode >> 0) & 7); + AREG((Opcode >> 9) & 7) = res; + RET(4) +} + +/* MOVEAW */ +OPCODE(0x3050) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READSX_WORD_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* MOVEAW */ +OPCODE(0x3058) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READSX_WORD_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* MOVEAW */ +OPCODE(0x3060) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READSX_WORD_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(10) +} + +/* MOVEAW */ +OPCODE(0x3068) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READSX_WORD_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEAW */ +OPCODE(0x3070) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READSX_WORD_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(14) +} + +/* MOVEAW */ +OPCODE(0x3078) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READSX_WORD_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEAW */ +OPCODE(0x3079) +{ + u32 adr, res; + + FETCH_LONG(adr); + READSX_WORD_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* MOVEAW */ +OPCODE(0x307A) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READSX_WORD_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* MOVEAW */ +OPCODE(0x307B) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READSX_WORD_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(14) +} + +/* MOVEAW */ +OPCODE(0x307C) +{ + u32 res; + + FETCH_SWORD(res); + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* MOVEAW */ +OPCODE(0x305F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READSX_WORD_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* MOVEAW */ +OPCODE(0x3067) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READSX_WORD_F(adr, res) + AREG((Opcode >> 9) & 7) = res; + RET(10) +} + +/* NEGX */ +OPCODE(0x4000) +{ + u32 res; + u32 src; + + src = DREGu8((Opcode >> 0) & 7); + res = -src - ((flag_X >> 8) & 1); + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ |= res & 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* NEGX */ +OPCODE(0x4010) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* NEGX */ +OPCODE(0x4018) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* NEGX */ +OPCODE(0x4020) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* NEGX */ +OPCODE(0x4028) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* NEGX */ +OPCODE(0x4030) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* NEGX */ +OPCODE(0x4038) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* NEGX */ +OPCODE(0x4039) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_BYTE_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* NEGX */ +OPCODE(0x401F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* NEGX */ +OPCODE(0x4027) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* NEGX */ +OPCODE(0x4040) +{ + u32 res; + u32 src; + + src = DREGu16((Opcode >> 0) & 7); + res = -src - ((flag_X >> 8) & 1); + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(4) +} + +/* NEGX */ +OPCODE(0x4050) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* NEGX */ +OPCODE(0x4058) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* NEGX */ +OPCODE(0x4060) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* NEGX */ +OPCODE(0x4068) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* NEGX */ +OPCODE(0x4070) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* NEGX */ +OPCODE(0x4078) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* NEGX */ +OPCODE(0x4079) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* NEGX */ +OPCODE(0x405F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* NEGX */ +OPCODE(0x4067) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* NEGX */ +OPCODE(0x4080) +{ + u32 res; + u32 src; + + src = DREGu32((Opcode >> 0) & 7); + res = -src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_V = (res & src) >> 24; + flag_X = flag_C = (res?1:0)<<8; + /* flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; */ + flag_N = res >> 24; + DREGu32((Opcode >> 0) & 7) = res; + RET(6) +} + +/* NEGX */ +OPCODE(0x4090) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_V = (res & src) >> 24; + flag_X = flag_C = (res?1:0)<<8; + /* flag_X = flag_C = ((src & res & 1) | (src >> 1) | (res >> 1)) >> 23; */ + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* NEGX */ +OPCODE(0x4098) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_V = (res & src) >> 24; + flag_X = flag_C = (res?1:0)<<8; + /* flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; */ + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* NEGX */ +OPCODE(0x40A0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_V = (res & src) >> 24; + flag_X = flag_C = (res?1:0)<<8; + /* flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; */ + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* NEGX */ +OPCODE(0x40A8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_V = (res & src) >> 24; + flag_X = flag_C = (res?1:0)<<8; + /* flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; */ + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* NEGX */ +OPCODE(0x40B0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_V = (res & src) >> 24; + flag_X = flag_C = (res?1:0)<<8; + /* flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; */ + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(26) +} + +/* NEGX */ +OPCODE(0x40B8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_LONG_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_V = (res & src) >> 24; + flag_X = flag_C = (res?1:0)<<8; + /* flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; */ + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* NEGX */ +OPCODE(0x40B9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_LONG_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_V = (res & src) >> 24; + flag_X = flag_C = (res?1:0)<<8; + /* flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; */ + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* NEGX */ +OPCODE(0x409F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_V = (res & src) >> 24; + flag_X = flag_C = (res?1:0)<<8; + /* flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; */ + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* NEGX */ +OPCODE(0x40A7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, src) + res = -src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_V = (res & src) >> 24; + flag_X = flag_C = (res?1:0)<<8; + /* flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; */ + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* CLR */ +OPCODE(0x4200) +{ + u32 res; + + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* CLR */ +OPCODE(0x4210) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* CLR */ +OPCODE(0x4218) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* CLR */ +OPCODE(0x4220) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* CLR */ +OPCODE(0x4228) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* CLR */ +OPCODE(0x4230) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* CLR */ +OPCODE(0x4238) +{ + u32 adr, res; + + FETCH_SWORD(adr); + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* CLR */ +OPCODE(0x4239) +{ + u32 adr, res; + + FETCH_LONG(adr); + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* CLR */ +OPCODE(0x421F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* CLR */ +OPCODE(0x4227) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* CLR */ +OPCODE(0x4240) +{ + u32 res; + + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + DREGu16((Opcode >> 0) & 7) = res; + RET(4) +} + +/* CLR */ +OPCODE(0x4250) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* CLR */ +OPCODE(0x4258) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* CLR */ +OPCODE(0x4260) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* CLR */ +OPCODE(0x4268) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* CLR */ +OPCODE(0x4270) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* CLR */ +OPCODE(0x4278) +{ + u32 adr, res; + + FETCH_SWORD(adr); + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* CLR */ +OPCODE(0x4279) +{ + u32 adr, res; + + FETCH_LONG(adr); + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* CLR */ +OPCODE(0x425F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* CLR */ +OPCODE(0x4267) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* CLR */ +OPCODE(0x4280) +{ + u32 res; + + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + DREGu32((Opcode >> 0) & 7) = res; + RET(6) +} + +/* CLR */ +OPCODE(0x4290) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_LONG_F(adr, res) + RET(12) +} + +/* CLR */ +OPCODE(0x4298) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_LONG_F(adr, res) + RET(12) +} + +/* CLR */ +OPCODE(0x42A0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_LONG_F(adr, res) + RET(12) +} + +/* CLR */ +OPCODE(0x42A8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_LONG_F(adr, res) + RET(12) +} + +/* CLR */ +OPCODE(0x42B0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_LONG_F(adr, res) + RET(12) +} + +/* CLR */ +OPCODE(0x42B8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_LONG_F(adr, res) + RET(12) +} + +/* CLR */ +OPCODE(0x42B9) +{ + u32 adr, res; + + FETCH_LONG(adr); + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_LONG_F(adr, res) + RET(12) +} + +/* CLR */ +OPCODE(0x429F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 4; + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_LONG_F(adr, res) + RET(12) +} + +/* CLR */ +OPCODE(0x42A7) +{ + u32 adr, res; + + adr = AREG(7) - 4; + AREG(7) = adr; + res = 0; + flag_N = flag_NotZ = flag_V = flag_C = 0; + WRITE_LONG_F(adr, res) + RET(12) +} + +/* NEG */ +OPCODE(0x4400) +{ + u32 res; + u32 src; + + src = DREGu8((Opcode >> 0) & 7); + res = -src; + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* NEG */ +OPCODE(0x4410) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + res = -src; + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* NEG */ +OPCODE(0x4418) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, src) + res = -src; + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* NEG */ +OPCODE(0x4420) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + res = -src; + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* NEG */ +OPCODE(0x4428) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + res = -src; + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* NEG */ +OPCODE(0x4430) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, src) + res = -src; + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* NEG */ +OPCODE(0x4438) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, src) + res = -src; + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* NEG */ +OPCODE(0x4439) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_BYTE_F(adr, src) + res = -src; + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* NEG */ +OPCODE(0x441F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, src) + res = -src; + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* NEG */ +OPCODE(0x4427) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + res = -src; + flag_V = res & src; + flag_N = flag_X = flag_C = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* NEG */ +OPCODE(0x4440) +{ + u32 res; + u32 src; + + src = DREGu16((Opcode >> 0) & 7); + res = -src; + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(4) +} + +/* NEG */ +OPCODE(0x4450) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + res = -src; + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* NEG */ +OPCODE(0x4458) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + res = -src; + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* NEG */ +OPCODE(0x4460) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + res = -src; + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* NEG */ +OPCODE(0x4468) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + res = -src; + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* NEG */ +OPCODE(0x4470) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + res = -src; + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* NEG */ +OPCODE(0x4478) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + res = -src; + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* NEG */ +OPCODE(0x4479) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + res = -src; + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* NEG */ +OPCODE(0x445F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + res = -src; + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* NEG */ +OPCODE(0x4467) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + res = -src; + flag_V = (res & src) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* NEG */ +OPCODE(0x4480) +{ + u32 res; + u32 src; + + src = DREGu32((Opcode >> 0) & 7); + res = -src; + flag_NotZ = res; + flag_V = (res & src) >> 24; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_N = res >> 24; + DREGu32((Opcode >> 0) & 7) = res; + RET(6) +} + +/* NEG */ +OPCODE(0x4490) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + res = -src; + flag_NotZ = res; + flag_V = (res & src) >> 24; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* NEG */ +OPCODE(0x4498) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, src) + res = -src; + flag_NotZ = res; + flag_V = (res & src) >> 24; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* NEG */ +OPCODE(0x44A0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, src) + res = -src; + flag_NotZ = res; + flag_V = (res & src) >> 24; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* NEG */ +OPCODE(0x44A8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + res = -src; + flag_NotZ = res; + flag_V = (res & src) >> 24; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* NEG */ +OPCODE(0x44B0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, src) + res = -src; + flag_NotZ = res; + flag_V = (res & src) >> 24; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(26) +} + +/* NEG */ +OPCODE(0x44B8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_LONG_F(adr, src) + res = -src; + flag_NotZ = res; + flag_V = (res & src) >> 24; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* NEG */ +OPCODE(0x44B9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_LONG_F(adr, src) + res = -src; + flag_NotZ = res; + flag_V = (res & src) >> 24; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* NEG */ +OPCODE(0x449F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, src) + res = -src; + flag_NotZ = res; + flag_V = (res & src) >> 24; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* NEG */ +OPCODE(0x44A7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, src) + res = -src; + flag_NotZ = res; + flag_V = (res & src) >> 24; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* NOT */ +OPCODE(0x4600) +{ + u32 res; + u32 src; + + src = DREGu8((Opcode >> 0) & 7); + res = ~src; + flag_C = 0; + flag_V = 0; + flag_N = res; + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* NOT */ +OPCODE(0x4610) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_N = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* NOT */ +OPCODE(0x4618) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_N = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* NOT */ +OPCODE(0x4620) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_N = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* NOT */ +OPCODE(0x4628) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_N = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* NOT */ +OPCODE(0x4630) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_N = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* NOT */ +OPCODE(0x4638) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_N = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* NOT */ +OPCODE(0x4639) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_BYTE_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_N = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* NOT */ +OPCODE(0x461F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_N = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* NOT */ +OPCODE(0x4627) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_N = res; + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* NOT */ +OPCODE(0x4640) +{ + u32 res; + u32 src; + + src = DREGu16((Opcode >> 0) & 7); + res = ~src; + flag_C = 0; + flag_V = 0; + flag_NotZ = res & 0xFFFF; + flag_N = res >> 8; + DREGu16((Opcode >> 0) & 7) = res; + RET(4) +} + +/* NOT */ +OPCODE(0x4650) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_NotZ = res & 0xFFFF; + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* NOT */ +OPCODE(0x4658) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_NotZ = res & 0xFFFF; + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* NOT */ +OPCODE(0x4660) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_NotZ = res & 0xFFFF; + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* NOT */ +OPCODE(0x4668) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_NotZ = res & 0xFFFF; + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* NOT */ +OPCODE(0x4670) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_NotZ = res & 0xFFFF; + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* NOT */ +OPCODE(0x4678) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_NotZ = res & 0xFFFF; + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* NOT */ +OPCODE(0x4679) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_NotZ = res & 0xFFFF; + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* NOT */ +OPCODE(0x465F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_NotZ = res & 0xFFFF; + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* NOT */ +OPCODE(0x4667) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + res = ~src; + flag_C = 0; + flag_V = 0; + flag_NotZ = res & 0xFFFF; + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* NOT */ +OPCODE(0x4680) +{ + u32 res; + u32 src; + + src = DREGu32((Opcode >> 0) & 7); + res = ~src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 0) & 7) = res; + RET(6) +} + +/* NOT */ +OPCODE(0x4690) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + res = ~src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* NOT */ +OPCODE(0x4698) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, src) + res = ~src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* NOT */ +OPCODE(0x46A0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, src) + res = ~src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* NOT */ +OPCODE(0x46A8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + res = ~src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* NOT */ +OPCODE(0x46B0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, src) + res = ~src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(26) +} + +/* NOT */ +OPCODE(0x46B8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_LONG_F(adr, src) + res = ~src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* NOT */ +OPCODE(0x46B9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_LONG_F(adr, src) + res = ~src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* NOT */ +OPCODE(0x469F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, src) + res = ~src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* NOT */ +OPCODE(0x46A7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, src) + res = ~src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* MOVESRa */ +OPCODE(0x40C0) +{ + u32 res; + + res = GET_SR; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) +} + +/* MOVESRa */ +OPCODE(0x40D0) +{ + u32 adr, res; + + res = GET_SR; + adr = AREG((Opcode >> 0) & 7); + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVESRa */ +OPCODE(0x40D8) +{ + u32 adr, res; + + res = GET_SR; + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVESRa */ +OPCODE(0x40E0) +{ + u32 adr, res; + + res = GET_SR; + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* MOVESRa */ +OPCODE(0x40E8) +{ + u32 adr, res; + + res = GET_SR; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVESRa */ +OPCODE(0x40F0) +{ + u32 adr, res; + + res = GET_SR; + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + RET(18) +} + +/* MOVESRa */ +OPCODE(0x40F8) +{ + u32 adr, res; + + res = GET_SR; + FETCH_SWORD(adr); + WRITE_WORD_F(adr, res) + RET(16) +} + +/* MOVESRa */ +OPCODE(0x40F9) +{ + u32 adr, res; + + res = GET_SR; + FETCH_LONG(adr); + WRITE_WORD_F(adr, res) + RET(20) +} + +/* MOVESRa */ +OPCODE(0x40DF) +{ + u32 adr, res; + + res = GET_SR; + adr = AREG(7); + AREG(7) += 2; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* MOVESRa */ +OPCODE(0x40E7) +{ + u32 adr, res; + + res = GET_SR; + adr = AREG(7) - 2; + AREG(7) = adr; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* MOVEaCCR */ +OPCODE(0x44C0) +{ + u32 res; + + res = DREGu16((Opcode >> 0) & 7); + SET_CCR(res) + RET(12) +} + +/* MOVEaCCR */ +OPCODE(0x44D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_CCR(res) + RET(16) +} + +/* MOVEaCCR */ +OPCODE(0x44D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + SET_CCR(res) + RET(16) +} + +/* MOVEaCCR */ +OPCODE(0x44E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + SET_CCR(res) + RET(18) +} + +/* MOVEaCCR */ +OPCODE(0x44E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_CCR(res) + RET(20) +} + +/* MOVEaCCR */ +OPCODE(0x44F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_CCR(res) + RET(22) +} + +/* MOVEaCCR */ +OPCODE(0x44F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + SET_CCR(res) + RET(20) +} + +/* MOVEaCCR */ +OPCODE(0x44F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_WORD_F(adr, res) + SET_CCR(res) + RET(24) +} + +/* MOVEaCCR */ +OPCODE(0x44FA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, res) + SET_CCR(res) + RET(20) +} + +/* MOVEaCCR */ +OPCODE(0x44FB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_CCR(res) + RET(22) +} + +/* MOVEaCCR */ +OPCODE(0x44FC) +{ + u32 res; + + FETCH_WORD(res); + SET_CCR(res) + RET(16) +} + +/* MOVEaCCR */ +OPCODE(0x44DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + SET_CCR(res) + RET(16) +} + +/* MOVEaCCR */ +OPCODE(0x44E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + SET_CCR(res) + RET(18) +} + +/* MOVEaSR */ +OPCODE(0x46C0) +{ + u32 res; + + if (flag_S) + { + res = DREGu16((Opcode >> 0) & 7); + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(12) + } + else + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(12) +} + +/* MOVEaSR */ +OPCODE(0x46D0) +{ + u32 adr, res; + + if (flag_S) + { + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(16) + } + else + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(16) +} + +/* MOVEaSR */ +OPCODE(0x46D8) +{ + u32 adr, res; + + if (flag_S) + { + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(16) + } + else + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(16) +} + +/* MOVEaSR */ +OPCODE(0x46E0) +{ + u32 adr, res; + + if (flag_S) + { + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(18) + } + else + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(18) +} + +/* MOVEaSR */ +OPCODE(0x46E8) +{ + u32 adr, res; + + if (flag_S) + { + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(20) + } + else + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(20) +} + +/* MOVEaSR */ +OPCODE(0x46F0) +{ + u32 adr, res; + + if (flag_S) + { + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(22) + } + else + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(22) +} + + +/* MOVEaSR */ +OPCODE(0x46F8) +{ + u32 adr, res; + + if (flag_S) + { + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(20) + } + else + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(20) +} + +/* MOVEaSR */ +OPCODE(0x46F9) +{ + u32 adr, res; + + if (flag_S) + { + FETCH_LONG(adr); + READ_WORD_F(adr, res) + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(24) + } + else + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(24) +} + +/* MOVEaSR */ +OPCODE(0x46FA) +{ + u32 adr, res; + + if (flag_S) + { + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, res) + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(24) + } + else + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(20) +} + +/* MOVEaSR */ +OPCODE(0x46FB) +{ + u32 adr, res; + + if (flag_S) + { + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(22) + } + else + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(22) +} + +/* MOVEaSR */ +OPCODE(0x46FC) +{ + u32 res; + + if (flag_S) + { + FETCH_WORD(res); + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(16) + } + else + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(16) +} + +/* MOVEaSR */ +OPCODE(0x46DF) +{ + u32 adr, res; + + if (flag_S) + { + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(16) + } + else + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(16) +} + +/* MOVEaSR */ +OPCODE(0x46E7) +{ + u32 adr, res; + + if (flag_S) + { + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + CHECK_INT_TO_JUMP(18) + } + else + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + RET(18) +} + +/* NBCD */ +OPCODE(0x4800) +{ + u32 res; + + res = DREGu8((Opcode >> 0) & 7); + res = 0x9a - res - ((flag_X >> M68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + flag_NotZ |= res; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_N = res; + RET(6) +} + +/* NBCD */ +OPCODE(0x4810) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res = 0x9a - res - ((flag_X >> M68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + flag_NotZ |= res; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_N = res; + RET(12) +} + +/* NBCD */ +OPCODE(0x4818) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + res = 0x9a - res - ((flag_X >> M68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + flag_NotZ |= res; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_N = res; + RET(12) +} + +/* NBCD */ +OPCODE(0x4820) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + res = 0x9a - res - ((flag_X >> M68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + flag_NotZ |= res; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_N = res; + RET(14) +} + +/* NBCD */ +OPCODE(0x4828) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res = 0x9a - res - ((flag_X >> M68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + flag_NotZ |= res; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_N = res; + RET(16) +} + +/* NBCD */ +OPCODE(0x4830) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + res = 0x9a - res - ((flag_X >> M68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + flag_NotZ |= res; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_N = res; + RET(18) +} + +/* NBCD */ +OPCODE(0x4838) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + res = 0x9a - res - ((flag_X >> M68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + flag_NotZ |= res; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_N = res; + RET(16) +} + +/* NBCD */ +OPCODE(0x4839) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + res = 0x9a - res - ((flag_X >> M68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + flag_NotZ |= res; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_N = res; + RET(20) +} + +/* NBCD */ +OPCODE(0x481F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + res = 0x9a - res - ((flag_X >> M68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + flag_NotZ |= res; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_N = res; + RET(12) +} + +/* NBCD */ +OPCODE(0x4827) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + res = 0x9a - res - ((flag_X >> M68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + flag_NotZ |= res; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_N = res; + RET(14) +} + +/* PEA */ +OPCODE(0x4850) +{ + u32 adr; + + adr = AREG((Opcode >> 0) & 7); + PUSH_32_F(adr) + RET(12) +} + +/* PEA */ +OPCODE(0x4868) +{ + u32 adr; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + PUSH_32_F(adr) + RET(16) +} + +/* PEA */ +OPCODE(0x4870) +{ + u32 adr; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + PUSH_32_F(adr) + RET(20) +} + +/* PEA */ +OPCODE(0x4878) +{ + u32 adr; + + FETCH_SWORD(adr); + PUSH_32_F(adr) + RET(16) +} + +/* PEA */ +OPCODE(0x4879) +{ + u32 adr; + + FETCH_LONG(adr); + PUSH_32_F(adr) + RET(20) +} + +/* PEA */ +OPCODE(0x487A) +{ + u32 adr; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + PUSH_32_F(adr) + RET(16) +} + +/* PEA */ +OPCODE(0x487B) +{ + u32 adr; + + adr = UNBASED_PC; + DECODE_EXT_WORD + PUSH_32_F(adr) + RET(20) +} + +/* SWAP */ +OPCODE(0x4840) +{ + u32 res; + + res = DREGu32((Opcode >> 0) & 7); + res = (res >> 16) | (res << 16); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 0) & 7) = res; + RET(4) +} + +/* MOVEMRa */ +OPCODE(0x4890) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + adr = AREG((Opcode >> 0) & 7); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + WRITE_WORD_F(adr, *psrc) + adr += 2; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(8) +} + +/* MOVEMRa */ +OPCODE(0x48A0) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + adr = AREG((Opcode >> 0) & 7); + psrc = &AREGu32(7); + dst = adr; + do + { + if (res & 1) + { + adr -= 2; + WRITE_WORD_F(adr, *psrc) + } + psrc--; + } + while (res >>= 1); + AREG((Opcode >> 0) & 7) = adr; + io_cycle_counter -= (dst - adr) * 2; + RET(8) +} + +/* MOVEMRa */ +OPCODE(0x48A8) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + WRITE_WORD_F(adr, *psrc) + adr += 2; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(12) +} + +/* MOVEMRa */ +OPCODE(0x48B0) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + WRITE_WORD_F(adr, *psrc) + adr += 2; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(14) +} + +/* MOVEMRa */ +OPCODE(0x48B8) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + FETCH_SWORD(adr); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + WRITE_WORD_F(adr, *psrc) + adr += 2; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(12) +} + +/* MOVEMRa */ +OPCODE(0x48B9) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + FETCH_LONG(adr); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + WRITE_WORD_F(adr, *psrc) + adr += 2; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(16) +} + +/* MOVEMRa */ +OPCODE(0x48A7) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + adr = AREG(7); + psrc = &AREGu32(7); + dst = adr; + do + { + if (res & 1) + { + adr -= 2; + WRITE_WORD_F(adr, *psrc) + } + psrc--; + } + while (res >>= 1); + AREG(7) = adr; + io_cycle_counter -= (dst - adr) * 2; + RET(8) +} + +/* MOVEMRa */ +OPCODE(0x48D0) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + adr = AREG((Opcode >> 0) & 7); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + WRITE_LONG_F(adr, *psrc) + adr += 4; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(8) +} + +/* MOVEMRa */ +OPCODE(0x48E0) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + adr = AREG((Opcode >> 0) & 7); + psrc = &AREGu32(7); + dst = adr; + do + { + if (res & 1) + { + adr -= 4; + WRITE_LONG_DEC_F(adr, *psrc) + } + psrc--; + } + while (res >>= 1); + AREG((Opcode >> 0) & 7) = adr; + io_cycle_counter -= (dst - adr) * 2; + RET(8) +} + +/* MOVEMRa */ +OPCODE(0x48E8) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + WRITE_LONG_F(adr, *psrc) + adr += 4; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(12) +} + +/* MOVEMRa */ +OPCODE(0x48F0) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + WRITE_LONG_F(adr, *psrc) + adr += 4; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(14) +} + +/* MOVEMRa */ +OPCODE(0x48F8) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + FETCH_SWORD(adr); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + WRITE_LONG_F(adr, *psrc) + adr += 4; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(12) +} + +/* MOVEMRa */ +OPCODE(0x48F9) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + FETCH_LONG(adr); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + WRITE_LONG_F(adr, *psrc) + adr += 4; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(16) +} + +/* MOVEMRa */ +OPCODE(0x48E7) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + adr = AREG(7); + psrc = &AREGu32(7); + dst = adr; + do + { + if (res & 1) + { + adr -= 4; + WRITE_LONG_DEC_F(adr, *psrc) + } + psrc--; + } + while (res >>= 1); + AREG(7) = adr; + io_cycle_counter -= (dst - adr) * 2; + RET(8) +} + +/* EXT */ +OPCODE(0x4880) +{ + u32 res; + + res = (s32)DREGs8((Opcode >> 0) & 7); + SET_FLAGS_NZ_VC0 + DREGu16((Opcode >> 0) & 7) = res; + RET(4) +} + +/* EXT */ +OPCODE(0x48C0) +{ + u32 res; + + res = (s32)DREGs16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu32((Opcode >> 0) & 7) = res; + RET(4) +} + +/* TST */ +OPCODE(0x4A00) +{ + u32 res; + + res = DREGu8((Opcode >> 0) & 7); + SET_FLAGS_NZ_VC0 + RET(4) +} + +/* TST */ +OPCODE(0x4A10) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + RET(8) +} + +/* TST */ +OPCODE(0x4A18) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + RET(8) +} + +/* TST */ +OPCODE(0x4A20) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + RET(10) +} + +/* TST */ +OPCODE(0x4A28) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + RET(12) +} + +/* TST */ +OPCODE(0x4A30) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + RET(14) +} + +/* TST */ +OPCODE(0x4A38) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + RET(12) +} + +/* TST */ +OPCODE(0x4A39) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + RET(16) +} + +/* TST */ +OPCODE(0x4A1F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + RET(8) +} + +/* TST */ +OPCODE(0x4A27) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 + RET(10) +} + +/* TST */ +OPCODE(0x4A40) +{ + u32 res; + + res = DREGu16((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + RET(4) +} + +/* TST */ +OPCODE(0x4A50) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + RET(8) +} + +/* TST */ +OPCODE(0x4A58) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + RET(8) +} + +/* TST */ +OPCODE(0x4A60) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + RET(10) +} + +/* TST */ +OPCODE(0x4A68) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + RET(12) +} + +/* TST */ +OPCODE(0x4A70) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + RET(14) +} + +/* TST */ +OPCODE(0x4A78) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + RET(12) +} + +/* TST */ +OPCODE(0x4A79) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + RET(16) +} + +/* TST */ +OPCODE(0x4A5F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + RET(8) +} + +/* TST */ +OPCODE(0x4A67) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + RET(10) +} + +/* TST */ +OPCODE(0x4A80) +{ + u32 res; + + res = DREGu32((Opcode >> 0) & 7); + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + RET(4) +} + +/* TST */ +OPCODE(0x4A90) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + RET(12) +} + +/* TST */ +OPCODE(0x4A98) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + RET(12) +} + +/* TST */ +OPCODE(0x4AA0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + RET(14) +} + +/* TST */ +OPCODE(0x4AA8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + RET(16) +} + +/* TST */ +OPCODE(0x4AB0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + RET(18) +} + +/* TST */ +OPCODE(0x4AB8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + RET(16) +} + +/* TST */ +OPCODE(0x4AB9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + RET(20) +} + +/* TST */ +OPCODE(0x4A9F) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + RET(12) +} + +/* TST */ +OPCODE(0x4AA7) +{ + u32 adr, res; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + RET(14) +} + +/* TAS */ +OPCODE(0x4AC0) +{ + u32 res; + + res = DREGu8((Opcode >> 0) & 7); + SET_FLAGS_NZ_VC0 + res |= 0x80; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* TAS */ +OPCODE(0x4AD0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 +#ifndef FAME_BYPASS_TAS_WRITEBACK + WRITE_BYTE_F(adr, res|0x80) +#endif + RET(18) +} + +/* TAS */ +OPCODE(0x4AD8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 +#ifndef FAME_BYPASS_TAS_WRITEBACK + WRITE_BYTE_F(adr, res|0x80) +#endif + RET(18) +} + +/* TAS */ +OPCODE(0x4AE0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 +#ifndef FAME_BYPASS_TAS_WRITEBACK + WRITE_BYTE_F(adr, res|0x80) +#endif + RET(20) +} + +/* TAS */ +OPCODE(0x4AE8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 +#ifndef FAME_BYPASS_TAS_WRITEBACK + WRITE_BYTE_F(adr, res|0x80) +#endif + RET(22) +} + +/* TAS */ +OPCODE(0x4AF0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 +#ifndef FAME_BYPASS_TAS_WRITEBACK + WRITE_BYTE_F(adr, res|0x80) +#endif + RET(24) +} + +/* TAS */ +OPCODE(0x4AF8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 +#ifndef FAME_BYPASS_TAS_WRITEBACK + WRITE_BYTE_F(adr, res|0x80) +#endif + RET(22) +} + +/* TAS */ +OPCODE(0x4AF9) +{ + u32 adr, res; + + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 +#ifndef FAME_BYPASS_TAS_WRITEBACK + WRITE_BYTE_F(adr, res|0x80) +#endif + RET(26) +} + +/* TAS */ +OPCODE(0x4ADF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 +#ifndef FAME_BYPASS_TAS_WRITEBACK + WRITE_BYTE_F(adr, res|0x80) +#endif + RET(18) +} + +/* TAS */ +OPCODE(0x4AE7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + SET_FLAGS_NZ_VC0 +#ifndef FAME_BYPASS_TAS_WRITEBACK + WRITE_BYTE_F(adr, res|0x80) +#endif + RET(20) +} + +/* ILLEGAL */ +OPCODE(0x4AFC) +{ + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_ILLEGAL_INSTRUCTION_EX); + RET(0) +} + +/* ILLEGAL A000-AFFF */ +OPCODE(0xA000) +{ + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_1010_EX); + RET(0) +} + +/* ILLEGAL F000-FFFF */ +OPCODE(0xF000) +{ + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_1111_EX); + RET(0) +} + +/* MOVEMaR */ +OPCODE(0x4C90) +{ + u32 adr, res; + u32 dst; + + s32 *psrc; + + FETCH_WORD(res); + adr = AREG((Opcode >> 0) & 7); + psrc = &DREGs32(0); + dst = adr; + do + { + if (res & 1) + { + READSX_WORD_F(adr, *psrc) + adr += 2; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(12) +} + +/* MOVEMaR */ +OPCODE(0x4C98) +{ + u32 adr, res; + u32 dst; + + s32 *psrc; + + FETCH_WORD(res); + adr = AREG((Opcode >> 0) & 7); + psrc = &DREGs32(0); + dst = adr; + do + { + if (res & 1) + { + READSX_WORD_F(adr, *psrc) + adr += 2; + } + psrc++; + } + while (res >>= 1); + AREG((Opcode >> 0) & 7) = adr; + io_cycle_counter -= (adr - dst) * 2; + RET(12) +} + +/* MOVEMaR */ +OPCODE(0x4CA8) +{ + u32 adr, res; + u32 dst; + + s32 *psrc; + + FETCH_WORD(res); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + psrc = &DREGs32(0); + dst = adr; + do + { + if (res & 1) + { + READSX_WORD_F(adr, *psrc) + adr += 2; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(16) +} + +/* MOVEMaR */ +OPCODE(0x4CB0) +{ + u32 adr, res; + u32 dst; + + s32 *psrc; + + FETCH_WORD(res); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + psrc = &DREGs32(0); + dst = adr; + do + { + if (res & 1) + { + READSX_WORD_F(adr, *psrc) + adr += 2; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(18) +} + +/* MOVEMaR */ +OPCODE(0x4CB8) +{ + u32 adr, res; + u32 dst; + + s32 *psrc; + + FETCH_WORD(res); + FETCH_SWORD(adr); + psrc = &DREGs32(0); + dst = adr; + do + { + if (res & 1) + { + READSX_WORD_F(adr, *psrc) + adr += 2; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(16) +} + +/* MOVEMaR */ +OPCODE(0x4CB9) +{ + u32 adr, res; + u32 dst; + + s32 *psrc; + + FETCH_WORD(res); + FETCH_LONG(adr); + psrc = &DREGs32(0); + dst = adr; + do + { + if (res & 1) + { + READSX_WORD_F(adr, *psrc) + adr += 2; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(20) +} + +/* MOVEMaR */ +OPCODE(0x4CBA) +{ + u32 adr, res; + u32 dst; + + s32 *psrc; + + FETCH_WORD(res); + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + psrc = &DREGs32(0); + dst = adr; + do + { + if (res & 1) + { + READSX_WORD_F(adr, *psrc) + adr += 2; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(16) +} + +/* MOVEMaR */ +OPCODE(0x4CBB) +{ + u32 adr, res; + u32 dst; + + s32 *psrc; + + FETCH_WORD(res); + adr = UNBASED_PC; + DECODE_EXT_WORD + psrc = &DREGs32(0); + dst = adr; + do + { + if (res & 1) + { + READSX_WORD_F(adr, *psrc) + adr += 2; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(18) +} + +/* MOVEMaR */ +OPCODE(0x4C9F) +{ + u32 adr, res; + u32 dst; + + s32 *psrc; + + FETCH_WORD(res); + adr = AREG(7); + psrc = &DREGs32(0); + dst = adr; + do + { + if (res & 1) + { + READSX_WORD_F(adr, *psrc) + adr += 2; + } + psrc++; + } + while (res >>= 1); + AREG(7) = adr; + io_cycle_counter -= (adr - dst) * 2; + RET(12) +} + +/* MOVEMaR */ +OPCODE(0x4CD0) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + adr = AREG((Opcode >> 0) & 7); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + READ_LONG_F(adr, *psrc) + adr += 4; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(12) +} + +/* MOVEMaR */ +OPCODE(0x4CD8) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + adr = AREG((Opcode >> 0) & 7); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + READ_LONG_F(adr, *psrc) + adr += 4; + } + psrc++; + } + while (res >>= 1); + AREG((Opcode >> 0) & 7) = adr; + io_cycle_counter -= (adr - dst) * 2; + RET(12) +} + +/* MOVEMaR */ +OPCODE(0x4CE8) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + READ_LONG_F(adr, *psrc) + adr += 4; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(16) +} + +/* MOVEMaR */ +OPCODE(0x4CF0) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + READ_LONG_F(adr, *psrc) + adr += 4; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(18) +} + +/* MOVEMaR */ +OPCODE(0x4CF8) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + FETCH_SWORD(adr); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + READ_LONG_F(adr, *psrc) + adr += 4; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(16) +} + +/* MOVEMaR */ +OPCODE(0x4CF9) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + FETCH_LONG(adr); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + READ_LONG_F(adr, *psrc) + adr += 4; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(20) +} + +/* MOVEMaR */ +OPCODE(0x4CFA) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + READ_LONG_F(adr, *psrc) + adr += 4; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(16) +} + +/* MOVEMaR */ +OPCODE(0x4CFB) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + adr = UNBASED_PC; + DECODE_EXT_WORD + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + READ_LONG_F(adr, *psrc) + adr += 4; + } + psrc++; + } + while (res >>= 1); + io_cycle_counter -= (adr - dst) * 2; + RET(18) +} + +/* MOVEMaR */ +OPCODE(0x4CDF) +{ + u32 adr, res; + u32 dst; + + u32 *psrc; + + FETCH_WORD(res); + adr = AREG(7); + psrc = &DREGu32(0); + dst = adr; + do + { + if (res & 1) + { + READ_LONG_F(adr, *psrc) + adr += 4; + } + psrc++; + } + while (res >>= 1); + AREG(7) = adr; + io_cycle_counter -= (adr - dst) * 2; + RET(12) +} + +/* TRAP */ +OPCODE(0x4E40) +{ + execute_exception(M68K_TRAP_BASE_EX + (Opcode & 0xF)); + RET(4) +} + +/* LINK */ +OPCODE(0x4E50) +{ + u32 res; + + res = AREGu32((Opcode >> 0) & 7); + PUSH_32_F(res) + res = AREG(7); + AREG((Opcode >> 0) & 7) = res; + FETCH_SWORD(res); + AREG(7) += res; + RET(16) +} + +/* LINKA7 */ +OPCODE(0x4E57) +{ + u32 res; + + AREG(7) -= 4; + WRITE_LONG_DEC_F(AREG(7), AREG(7)) + FETCH_SWORD(res); + AREG(7) += res; + RET(16) +} + +/* ULNK */ +OPCODE(0x4E58) +{ + u32 res; + u32 src; + + src = AREGu32((Opcode >> 0) & 7); + AREG(7) = src + 4; + READ_LONG_F(src, res) + AREG((Opcode >> 0) & 7) = res; + RET(12) +} + +/* ULNKA7 */ +OPCODE(0x4E5F) +{ + + READ_LONG_F(AREG(7), AREG(7)) + RET(12) +} + +/* MOVEAUSP */ +OPCODE(0x4E60) +{ + u32 res; + + if (!flag_S) + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + res = AREGu32((Opcode >> 0) & 7); + ASP = res; + RET(4) +} + +/* MOVEUSPA */ +OPCODE(0x4E68) +{ + u32 res; + + if (!flag_S) + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + res = ASP; + AREG((Opcode >> 0) & 7) = res; + RET(4) +} + +/* RESET */ +OPCODE(0x4E70) +{ + + if (!flag_S) + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + if (FAME_CONTEXT.reset_handler) + (*FAME_CONTEXT.reset_handler)(); + /* CPU->Reset_CallBack(); */ + RET(132) +} + +/* NOP */ +OPCODE(0x4E71) +{ + + RET(4) +} + +/* STOP */ +OPCODE(0x4E72) +{ + u32 res; + + if (!flag_S) + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + FETCH_WORD(res); + res &= M68K_SR_MASK; + SET_SR(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + FAME_CONTEXT.execinfo |= M68K_HALTED; + CHECK_INT_TO_JUMP(4) + RET_STOP(4) +} + +/* RTE */ +OPCODE(0x4E73) +{ + u32 res; + + if (!flag_S) + { + u32 oldPC=UNBASED_PC; + SET_PC(oldPC-2) + execute_exception(M68K_PRIVILEGE_VIOLATION_EX); + RET(4) + } + POP_16_F(res) + SET_SR(res) + POP_32_F(res) + SET_PC(res) + if (!flag_S) + { + res = AREG(7); + AREG(7) = ASP; + ASP = res; + } + FAME_CONTEXT.execinfo &= ~(M68K_EMULATE_GROUP_0|M68K_EMULATE_TRACE|M68K_DO_TRACE); + CHECK_INT_TO_JUMP(20) + RET(20) +} + +/* RTS */ +OPCODE(0x4E75) +{ + u32 res; + + POP_32_F(res) + SET_PC(res) + CHECK_BRANCH_EXCEPTION(res) + RET(16) +} + +/* TRAPV */ +OPCODE(0x4E76) +{ + if (flag_V & 0x80) + execute_exception(M68K_TRAPV_EX); + RET(4) +} + +/* RTR */ +OPCODE(0x4E77) +{ + u32 res; + + POP_16_F(res) + SET_CCR(res) + POP_32_F(res) + SET_PC(res) + CHECK_BRANCH_EXCEPTION(res) + RET(20) +} + +/* JSR */ +OPCODE(0x4E90) +{ + u32 adr; + + adr = AREG((Opcode >> 0) & 7); + { + u32 oldPC; + + oldPC = UNBASED_PC; + PUSH_32_F(oldPC) + } + SET_PC(adr) + CHECK_BRANCH_EXCEPTION(adr) + RET(16) +} + +/* JSR */ +OPCODE(0x4EA8) +{ + u32 adr; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + { + u32 oldPC; + + oldPC = UNBASED_PC; + PUSH_32_F(oldPC) + } + SET_PC(adr) + CHECK_BRANCH_EXCEPTION(adr) + RET(18) +} + +/* JSR */ +OPCODE(0x4EB0) +{ + u32 adr; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + { + u32 oldPC; + + oldPC = UNBASED_PC; + PUSH_32_F(oldPC) + } + SET_PC(adr) + CHECK_BRANCH_EXCEPTION(adr) + RET(22) +} + +/* JSR */ +OPCODE(0x4EB8) +{ + u32 adr; + + FETCH_SWORD(adr); + { + u32 oldPC; + + oldPC = UNBASED_PC; + PUSH_32_F(oldPC) + } + SET_PC(adr) + CHECK_BRANCH_EXCEPTION(adr) + RET(18) +} + +/* JSR */ +OPCODE(0x4EB9) +{ + u32 adr; + + FETCH_LONG(adr); + { + u32 oldPC; + + oldPC = UNBASED_PC; + PUSH_32_F(oldPC) + } + SET_PC(adr) + CHECK_BRANCH_EXCEPTION(adr) + RET(20) +} + +/* JSR */ +OPCODE(0x4EBA) +{ + u32 adr; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + { + u32 oldPC; + + oldPC = UNBASED_PC; + PUSH_32_F(oldPC) + } + SET_PC(adr) + CHECK_BRANCH_EXCEPTION(adr) + RET(18) +} + +/* JSR */ +OPCODE(0x4EBB) +{ + u32 adr; + + adr = UNBASED_PC; + DECODE_EXT_WORD + { + u32 oldPC; + + oldPC = UNBASED_PC; + PUSH_32_F(oldPC) + } + SET_PC(adr) + CHECK_BRANCH_EXCEPTION(adr) + RET(22) +} + +/* JMP */ +OPCODE(0x4ED0) +{ + u32 adr; + + adr = AREG((Opcode >> 0) & 7); + SET_PC(adr) + CHECK_BRANCH_EXCEPTION(adr) + RET(8) +} + +/* JMP */ +OPCODE(0x4EE8) +{ + u32 adr; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + SET_PC(adr) + CHECK_BRANCH_EXCEPTION(adr) + RET(10) +} + +/* JMP */ +OPCODE(0x4EF0) +{ + u32 adr; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + SET_PC(adr) + CHECK_BRANCH_EXCEPTION(adr) + RET(14) +} + +/* JMP */ +OPCODE(0x4EF8) +{ + u32 adr; + + FETCH_SWORD(adr); + SET_PC(adr) + CHECK_BRANCH_EXCEPTION(adr) + RET(10) +} + +/* JMP */ +OPCODE(0x4EF9) +{ + u32 adr; + + FETCH_LONG(adr); + SET_PC(adr) + CHECK_BRANCH_EXCEPTION(adr) + RET(12) +} + +/* JMP */ +OPCODE(0x4EFA) +{ + u32 adr; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + SET_PC(adr) + CHECK_BRANCH_EXCEPTION(adr) + RET(10) +} + +/* JMP */ +OPCODE(0x4EFB) +{ + u32 adr; + + adr = UNBASED_PC; + DECODE_EXT_WORD + SET_PC(adr) + CHECK_BRANCH_EXCEPTION(adr) + RET(14) +} + +/* CHK */ +OPCODE(0x4180) +{ + u32 res; + u32 src; + + src = DREGu16((Opcode >> 0) & 7); + res = DREGu16((Opcode >> 9) & 7); + if (((s32)res < 0) || (res > src)) + { + flag_N = res >> 8; + execute_exception(M68K_CHK_EX); + } + RET(10) +} + +/* CHK */ +OPCODE(0x4190) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + if (((s32)res < 0) || (res > src)) + { + flag_N = res >> 8; + execute_exception(M68K_CHK_EX); + } + RET(14) +} + +/* CHK */ +OPCODE(0x4198) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + if (((s32)res < 0) || (res > src)) + { + flag_N = res >> 8; + execute_exception(M68K_CHK_EX); + } + RET(14) +} + +/* CHK */ +OPCODE(0x41A0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + if (((s32)res < 0) || (res > src)) + { + flag_N = res >> 8; + execute_exception(M68K_CHK_EX); + } + RET(16) +} + +/* CHK */ +OPCODE(0x41A8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + if (((s32)res < 0) || (res > src)) + { + flag_N = res >> 8; + execute_exception(M68K_CHK_EX); + } + RET(18) +} + +/* CHK */ +OPCODE(0x41B0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + if (((s32)res < 0) || (res > src)) + { + flag_N = res >> 8; + execute_exception(M68K_CHK_EX); + } + RET(20) +} + +/* CHK */ +OPCODE(0x41B8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + if (((s32)res < 0) || (res > src)) + { + flag_N = res >> 8; + execute_exception(M68K_CHK_EX); + } + RET(18) +} + +/* CHK */ +OPCODE(0x41B9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + if (((s32)res < 0) || (res > src)) + { + flag_N = res >> 8; + execute_exception(M68K_CHK_EX); + } + RET(22) +} + +/* CHK */ +OPCODE(0x41BA) +{ + u32 adr, res; + u32 src; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + if (((s32)res < 0) || (res > src)) + { + flag_N = res >> 8; + execute_exception(M68K_CHK_EX); + } + RET(18) +} + +/* CHK */ +OPCODE(0x41BB) +{ + u32 adr, res; + u32 src; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + if (((s32)res < 0) || (res > src)) + { + flag_N = res >> 8; + execute_exception(M68K_CHK_EX); + } + RET(20) +} + +/* CHK */ +OPCODE(0x41BC) +{ + u32 res; + u32 src; + + FETCH_WORD(src); + res = DREGu16((Opcode >> 9) & 7); + if (((s32)res < 0) || (res > src)) + { + flag_N = res >> 8; + execute_exception(M68K_CHK_EX); + } + RET(14) +} + +/* CHK */ +OPCODE(0x419F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + if (((s32)res < 0) || (res > src)) + { + flag_N = res >> 8; + execute_exception(M68K_CHK_EX); + } + RET(14) +} + +/* CHK */ +OPCODE(0x41A7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + if (((s32)res < 0) || (res > src)) + { + flag_N = res >> 8; + execute_exception(M68K_CHK_EX); + } + RET(16) +} + +/* LEA */ +OPCODE(0x41D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + res = adr; + AREG((Opcode >> 9) & 7) = res; + RET(4) +} + +/* LEA */ +OPCODE(0x41E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + res = adr; + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* LEA */ +OPCODE(0x41F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + res = adr; + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* LEA */ +OPCODE(0x41F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + res = adr; + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* LEA */ +OPCODE(0x41F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + res = adr; + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* LEA */ +OPCODE(0x41FA) +{ + u32 adr, res; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + res = adr; + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* LEA */ +OPCODE(0x41FB) +{ + u32 adr, res; + + adr = UNBASED_PC; + DECODE_EXT_WORD + res = adr; + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* STCC */ +OPCODE(0x50C0) +{ + u32 res; + + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) +} + +/* STCC */ +OPCODE(0x51C0) +{ + u32 res; + + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x52C0) +{ + u32 res; + + if (flag_NotZ && (!(flag_C & 0x100))) + { + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x53C0) +{ + u32 res; + + if ((!flag_NotZ) || (flag_C & 0x100)) + { + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x54C0) +{ + u32 res; + + if (!(flag_C & 0x100)) + { + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x55C0) +{ + u32 res; + + if (flag_C & 0x100) + { + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x56C0) +{ + u32 res; + + if (flag_NotZ) + { + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x57C0) +{ + u32 res; + + if (!flag_NotZ) + { + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x58C0) +{ + u32 res; + + if (!(flag_V & 0x80)) + { + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x59C0) +{ + u32 res; + + if (flag_V & 0x80) + { + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x5AC0) +{ + u32 res; + + if (!(flag_N & 0x80)) + { + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x5BC0) +{ + u32 res; + + if (flag_N & 0x80) + { + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x5CC0) +{ + u32 res; + + if (!((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x5DC0) +{ + u32 res; + + if ((flag_N ^ flag_V) & 0x80) + { + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x5EC0) +{ + u32 res; + + if (flag_NotZ && (!((flag_N ^ flag_V) & 0x80))) + { + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x5FC0) +{ + u32 res; + + if ((!flag_NotZ) || ((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* STCC */ +OPCODE(0x50D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x51D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x52D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + if (flag_NotZ && (!(flag_C & 0x100))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x53D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + if ((!flag_NotZ) || (flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x54D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + if (!(flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x55D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + if (flag_C & 0x100) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x56D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + if (flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x57D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + if (!flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x58D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + if (!(flag_V & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x59D0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + if (flag_V & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5AD0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + if (!(flag_N & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5BD0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + if (flag_N & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5CD0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + if (!((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5DD0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + if ((flag_N ^ flag_V) & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5ED0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + if (flag_NotZ && (!((flag_N ^ flag_V) & 0x80))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5FD0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + if ((!flag_NotZ) || ((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x50D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x51D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x52D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + if (flag_NotZ && (!(flag_C & 0x100))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x53D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + if ((!flag_NotZ) || (flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x54D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + if (!(flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x55D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + if (flag_C & 0x100) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x56D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + if (flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x57D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + if (!flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x58D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + if (!(flag_V & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x59D8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + if (flag_V & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5AD8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + if (!(flag_N & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5BD8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + if (flag_N & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5CD8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + if (!((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5DD8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + if ((flag_N ^ flag_V) & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5ED8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + if (flag_NotZ && (!((flag_N ^ flag_V) & 0x80))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5FD8) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + if ((!flag_NotZ) || ((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x50E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x51E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x52E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + if (flag_NotZ && (!(flag_C & 0x100))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x53E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + if ((!flag_NotZ) || (flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x54E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + if (!(flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x55E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + if (flag_C & 0x100) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x56E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + if (flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x57E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + if (!flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x58E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + if (!(flag_V & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x59E0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + if (flag_V & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x5AE0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + if (!(flag_N & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x5BE0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + if (flag_N & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x5CE0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + if (!((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x5DE0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + if ((flag_N ^ flag_V) & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x5EE0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + if (flag_NotZ && (!((flag_N ^ flag_V) & 0x80))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x5FE0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + if ((!flag_NotZ) || ((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x50E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x51E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x52E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + if (flag_NotZ && (!(flag_C & 0x100))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x53E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + if ((!flag_NotZ) || (flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x54E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + if (!(flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x55E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + if (flag_C & 0x100) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x56E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + if (flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x57E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + if (!flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x58E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + if (!(flag_V & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x59E8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + if (flag_V & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x5AE8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + if (!(flag_N & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x5BE8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + if (flag_N & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x5CE8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + if (!((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x5DE8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + if ((flag_N ^ flag_V) & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x5EE8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + if (flag_NotZ && (!((flag_N ^ flag_V) & 0x80))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x5FE8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + if ((!flag_NotZ) || ((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x50F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x51F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x52F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + if (flag_NotZ && (!(flag_C & 0x100))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x53F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + if ((!flag_NotZ) || (flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x54F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + if (!(flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x55F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + if (flag_C & 0x100) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x56F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + if (flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x57F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + if (!flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x58F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + if (!(flag_V & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x59F0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + if (flag_V & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x5AF0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + if (!(flag_N & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x5BF0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + if (flag_N & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x5CF0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + if (!((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x5DF0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + if ((flag_N ^ flag_V) & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x5EF0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + if (flag_NotZ && (!((flag_N ^ flag_V) & 0x80))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x5FF0) +{ + u32 adr, res; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + if ((!flag_NotZ) || ((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* STCC */ +OPCODE(0x50F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x51F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x52F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + if (flag_NotZ && (!(flag_C & 0x100))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x53F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + if ((!flag_NotZ) || (flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x54F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + if (!(flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x55F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + if (flag_C & 0x100) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x56F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + if (flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x57F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + if (!flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x58F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + if (!(flag_V & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x59F8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + if (flag_V & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x5AF8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + if (!(flag_N & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x5BF8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + if (flag_N & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x5CF8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + if (!((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x5DF8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + if ((flag_N ^ flag_V) & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x5EF8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + if (flag_NotZ && (!((flag_N ^ flag_V) & 0x80))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x5FF8) +{ + u32 adr, res; + + FETCH_SWORD(adr); + if ((!flag_NotZ) || ((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* STCC */ +OPCODE(0x50F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x51F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x52F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + if (flag_NotZ && (!(flag_C & 0x100))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x53F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + if ((!flag_NotZ) || (flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x54F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + if (!(flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x55F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + if (flag_C & 0x100) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x56F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + if (flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x57F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + if (!flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x58F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + if (!(flag_V & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x59F9) +{ + u32 adr, res; + + FETCH_LONG(adr); + if (flag_V & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x5AF9) +{ + u32 adr, res; + + FETCH_LONG(adr); + if (!(flag_N & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x5BF9) +{ + u32 adr, res; + + FETCH_LONG(adr); + if (flag_N & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x5CF9) +{ + u32 adr, res; + + FETCH_LONG(adr); + if (!((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x5DF9) +{ + u32 adr, res; + + FETCH_LONG(adr); + if ((flag_N ^ flag_V) & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x5EF9) +{ + u32 adr, res; + + FETCH_LONG(adr); + if (flag_NotZ && (!((flag_N ^ flag_V) & 0x80))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x5FF9) +{ + u32 adr, res; + + FETCH_LONG(adr); + if ((!flag_NotZ) || ((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* STCC */ +OPCODE(0x50DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x51DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x52DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + if (flag_NotZ && (!(flag_C & 0x100))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x53DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + if ((!flag_NotZ) || (flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x54DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + if (!(flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x55DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + if (flag_C & 0x100) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x56DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + if (flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x57DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + if (!flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x58DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + if (!(flag_V & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x59DF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + if (flag_V & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5ADF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + if (!(flag_N & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5BDF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + if (flag_N & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5CDF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + if (!((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5DDF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + if ((flag_N ^ flag_V) & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5EDF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + if (flag_NotZ && (!((flag_N ^ flag_V) & 0x80))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x5FDF) +{ + u32 adr, res; + + adr = AREG(7); + AREG(7) += 2; + if ((!flag_NotZ) || ((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* STCC */ +OPCODE(0x50E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x51E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x52E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + if (flag_NotZ && (!(flag_C & 0x100))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x53E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + if ((!flag_NotZ) || (flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x54E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + if (!(flag_C & 0x100)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x55E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + if (flag_C & 0x100) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x56E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + if (flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x57E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + if (!flag_NotZ) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x58E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + if (!(flag_V & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x59E7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + if (flag_V & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x5AE7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + if (!(flag_N & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x5BE7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + if (flag_N & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x5CE7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + if (!((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x5DE7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + if ((flag_N ^ flag_V) & 0x80) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x5EE7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + if (flag_NotZ && (!((flag_N ^ flag_V) & 0x80))) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* STCC */ +OPCODE(0x5FE7) +{ + u32 adr, res; + + adr = AREG(7) - 2; + AREG(7) = adr; + if ((!flag_NotZ) || ((flag_N ^ flag_V) & 0x80)) + { + res = 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) + } + res = 0; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* DBCC */ +OPCODE(0x50C8) +{ + + INC_PC(2); + RET(12) +} + +/* DBCC */ +OPCODE(0x51C8) +{ + u32 res; + + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(14) +} + +/* DBCC */ +OPCODE(0x52C8) +{ + u32 res; + + if ((!flag_NotZ) || (flag_C & 0x100)) + { + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + } + else + { + INC_PC(2); + RET(12) + } + INC_PC(2); + RET(14) +} + +/* DBCC */ +OPCODE(0x53C8) +{ + u32 res; + + if (flag_NotZ && (!(flag_C & 0x100))) + { + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + } + else + { + INC_PC(2); + RET(12) + } + INC_PC(2); + RET(14) +} + +/* DBCC */ +OPCODE(0x54C8) +{ + u32 res; + + if (flag_C & 0x100) + { + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + } + else + { + INC_PC(2); + RET(12) + } + INC_PC(2); + RET(14) +} + +/* DBCC */ +OPCODE(0x55C8) +{ + u32 res; + + if (!(flag_C & 0x100)) + { + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + } + else + { + INC_PC(2); + RET(12) + } + INC_PC(2); + RET(14) +} + +/* DBCC */ +OPCODE(0x56C8) +{ + u32 res; + + if (!flag_NotZ) + { + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + } + else + { + INC_PC(2); + RET(12) + } + INC_PC(2); + RET(14) +} + +/* DBCC */ +OPCODE(0x57C8) +{ + u32 res; + + if (flag_NotZ) + { + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + } + else + { + INC_PC(2); + RET(12) + } + INC_PC(2); + RET(14) +} + +/* DBCC */ +OPCODE(0x58C8) +{ + u32 res; + + if (flag_V & 0x80) + { + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + } + else + { + INC_PC(2); + RET(12) + } + INC_PC(2); + RET(14) +} + +/* DBCC */ +OPCODE(0x59C8) +{ + u32 res; + + if (!(flag_V & 0x80)) + { + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + } + else + { + INC_PC(2); + RET(12) + } + INC_PC(2); + RET(14) +} + +/* DBCC */ +OPCODE(0x5AC8) +{ + u32 res; + + if (flag_N & 0x80) + { + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + } + else + { + INC_PC(2); + RET(12) + } + INC_PC(2); + RET(14) +} + +/* DBCC */ +OPCODE(0x5BC8) +{ + u32 res; + + if (!(flag_N & 0x80)) + { + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + } + else + { + INC_PC(2); + RET(12) + } + INC_PC(2); + RET(14) +} + +/* DBCC */ +OPCODE(0x5CC8) +{ + u32 res; + + if ((flag_N ^ flag_V) & 0x80) + { + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + } + else + { + INC_PC(2); + RET(12) + } + INC_PC(2); + RET(14) +} + +/* DBCC */ +OPCODE(0x5DC8) +{ + u32 res; + + if (!((flag_N ^ flag_V) & 0x80)) + { + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + } + else + { + INC_PC(2); + RET(12) + } + INC_PC(2); + RET(14) +} + +/* DBCC */ +OPCODE(0x5EC8) +{ + u32 res; + + if ((!flag_NotZ) || ((flag_N ^ flag_V) & 0x80)) + { + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + } + else + { + INC_PC(2); + RET(12) + } + INC_PC(2); + RET(14) +} + +/* DBCC */ +OPCODE(0x5FC8) +{ + u32 res; + + if (flag_NotZ && (!((flag_N ^ flag_V) & 0x80))) + { + res = DREGu16((Opcode >> 0) & 7); + res--; + DREGu16((Opcode >> 0) & 7) = res; + if ((s32)res != -1) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + } + else + { + INC_PC(2); + RET(12) + } + INC_PC(2); + RET(14) +} + +/* ADDQ */ +OPCODE(0x5000) +{ + u32 res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = DREGu8((Opcode >> 0) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* ADDQ */ +OPCODE(0x5010) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* ADDQ */ +OPCODE(0x5018) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* ADDQ */ +OPCODE(0x5020) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* ADDQ */ +OPCODE(0x5028) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ADDQ */ +OPCODE(0x5030) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ADDQ */ +OPCODE(0x5038) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_SWORD(adr); + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ADDQ */ +OPCODE(0x5039) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_LONG(adr); + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* ADDQ */ +OPCODE(0x501F) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* ADDQ */ +OPCODE(0x5027) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* ADDQ */ +OPCODE(0x5040) +{ + u32 res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = DREGu16((Opcode >> 0) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(4) +} + +/* ADDQ */ +OPCODE(0x5048) +{ + u32 res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = AREGu32((Opcode >> 0) & 7); + res = dst + src; + AREG((Opcode >> 0) & 7) = res; + RET(4) +} + +/* ADDQ */ +OPCODE(0x5050) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ADDQ */ +OPCODE(0x5058) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ADDQ */ +OPCODE(0x5060) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ADDQ */ +OPCODE(0x5068) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ADDQ */ +OPCODE(0x5070) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ADDQ */ +OPCODE(0x5078) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_SWORD(adr); + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ADDQ */ +OPCODE(0x5079) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_LONG(adr); + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ADDQ */ +OPCODE(0x505F) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ADDQ */ +OPCODE(0x5067) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ADDQ */ +OPCODE(0x5080) +{ + u32 res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = DREGu32((Opcode >> 0) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) +} + +/* ADDQ */ +OPCODE(0x5088) +{ + u32 res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = AREGu32((Opcode >> 0) & 7); + res = dst + src; + AREG((Opcode >> 0) & 7) = res; + RET(8) +} + +/* ADDQ */ +OPCODE(0x5090) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* ADDQ */ +OPCODE(0x5098) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* ADDQ */ +OPCODE(0x50A0) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* ADDQ */ +OPCODE(0x50A8) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* ADDQ */ +OPCODE(0x50B0) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(26) +} + +/* ADDQ */ +OPCODE(0x50B8) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_SWORD(adr); + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* ADDQ */ +OPCODE(0x50B9) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_LONG(adr); + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* ADDQ */ +OPCODE(0x509F) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* ADDQ */ +OPCODE(0x50A7) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* SUBQ */ +OPCODE(0x5100) +{ + u32 res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = DREGu8((Opcode >> 0) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* SUBQ */ +OPCODE(0x5110) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* SUBQ */ +OPCODE(0x5118) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* SUBQ */ +OPCODE(0x5120) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* SUBQ */ +OPCODE(0x5128) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* SUBQ */ +OPCODE(0x5130) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* SUBQ */ +OPCODE(0x5138) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_SWORD(adr); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* SUBQ */ +OPCODE(0x5139) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_LONG(adr); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* SUBQ */ +OPCODE(0x511F) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* SUBQ */ +OPCODE(0x5127) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* SUBQ */ +OPCODE(0x5140) +{ + u32 res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = DREGu16((Opcode >> 0) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(4) +} + +/* SUBQ */ +OPCODE(0x5148) +{ + u32 res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = AREGu32((Opcode >> 0) & 7); + res = dst - src; + AREG((Opcode >> 0) & 7) = res; + RET(8) +} + +/* SUBQ */ +OPCODE(0x5150) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* SUBQ */ +OPCODE(0x5158) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* SUBQ */ +OPCODE(0x5160) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* SUBQ */ +OPCODE(0x5168) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* SUBQ */ +OPCODE(0x5170) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* SUBQ */ +OPCODE(0x5178) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_SWORD(adr); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* SUBQ */ +OPCODE(0x5179) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_LONG(adr); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* SUBQ */ +OPCODE(0x515F) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* SUBQ */ +OPCODE(0x5167) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* SUBQ */ +OPCODE(0x5180) +{ + u32 res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = DREGu32((Opcode >> 0) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) +} + +/* SUBQ */ +OPCODE(0x5188) +{ + u32 res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = AREGu32((Opcode >> 0) & 7); + res = dst - src; + AREG((Opcode >> 0) & 7) = res; + RET(8) +} + +/* SUBQ */ +OPCODE(0x5190) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* SUBQ */ +OPCODE(0x5198) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* SUBQ */ +OPCODE(0x51A0) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* SUBQ */ +OPCODE(0x51A8) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* SUBQ */ +OPCODE(0x51B0) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(26) +} + +/* SUBQ */ +OPCODE(0x51B8) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_SWORD(adr); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* SUBQ */ +OPCODE(0x51B9) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + FETCH_LONG(adr); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* SUBQ */ +OPCODE(0x519F) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* SUBQ */ +OPCODE(0x51A7) +{ + u32 adr, res; + u32 src, dst; + + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* BCC */ +OPCODE(0x6201) +{ + + if (flag_NotZ && (!(flag_C & 0x100))) + { + INC_PC((s8)(Opcode & 0xFE)); + io_cycle_counter -= 2; + } + RET(8) +} + +/* BCC */ +OPCODE(0x6301) +{ + + if ((!flag_NotZ) || (flag_C & 0x100)) + { + INC_PC((s8)(Opcode & 0xFE)); + io_cycle_counter -= 2; + } + RET(8) +} + +/* BCC */ +OPCODE(0x6401) +{ + + if (!(flag_C & 0x100)) + { + INC_PC((s8)(Opcode & 0xFE)); + io_cycle_counter -= 2; + } + RET(8) +} + +/* BCC */ +OPCODE(0x6501) +{ + + if (flag_C & 0x100) + { + INC_PC((s8)(Opcode & 0xFE)); + io_cycle_counter -= 2; + } + RET(8) +} + +/* BCC */ +OPCODE(0x6601) +{ + + if (flag_NotZ) + { + INC_PC((s8)(Opcode & 0xFE)); + io_cycle_counter -= 2; + } + RET(8) +} + +/* BCC */ +OPCODE(0x6701) +{ + + if (!flag_NotZ) + { + INC_PC((s8)(Opcode & 0xFE)); + io_cycle_counter -= 2; + } + RET(8) +} + +/* BCC */ +OPCODE(0x6801) +{ + + if (!(flag_V & 0x80)) + { + INC_PC((s8)(Opcode & 0xFE)); + io_cycle_counter -= 2; + } + RET(8) +} + +/* BCC */ +OPCODE(0x6901) +{ + + if (flag_V & 0x80) + { + INC_PC((s8)(Opcode & 0xFE)); + io_cycle_counter -= 2; + } + RET(8) +} + +/* BCC */ +OPCODE(0x6A01) +{ + + if (!(flag_N & 0x80)) + { + INC_PC((s8)(Opcode & 0xFE)); + io_cycle_counter -= 2; + } + RET(8) +} + +/* BCC */ +OPCODE(0x6B01) +{ + + if (flag_N & 0x80) + { + INC_PC((s8)(Opcode & 0xFE)); + io_cycle_counter -= 2; + } + RET(8) +} + +/* BCC */ +OPCODE(0x6C01) +{ + + if (!((flag_N ^ flag_V) & 0x80)) + { + INC_PC((s8)(Opcode & 0xFE)); + io_cycle_counter -= 2; + } + RET(8) +} + +/* BCC */ +OPCODE(0x6D01) +{ + + if ((flag_N ^ flag_V) & 0x80) + { + INC_PC((s8)(Opcode & 0xFE)); + io_cycle_counter -= 2; + } + RET(8) +} + +/* BCC */ +OPCODE(0x6E01) +{ + + if (flag_NotZ && (!((flag_N ^ flag_V) & 0x80))) + { + INC_PC((s8)(Opcode & 0xFE)); + io_cycle_counter -= 2; + } + RET(8) +} + +/* BCC */ +OPCODE(0x6F01) +{ + + if ((!flag_NotZ) || ((flag_N ^ flag_V) & 0x80)) + { + INC_PC((s8)(Opcode & 0xFE)); + io_cycle_counter -= 2; + } + RET(8) +} + +/* BCC16 */ +OPCODE(0x6200) +{ + + if (flag_NotZ && (!(flag_C & 0x100))) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(12) +} + +/* BCC16 */ +OPCODE(0x6300) +{ + + if ((!flag_NotZ) || (flag_C & 0x100)) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(12) +} + +/* BCC16 */ +OPCODE(0x6400) +{ + + if (!(flag_C & 0x100)) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(12) +} + +/* BCC16 */ +OPCODE(0x6500) +{ + + if (flag_C & 0x100) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(12) +} + +/* BCC16 */ +OPCODE(0x6600) +{ + + if (flag_NotZ) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(12) +} + +/* BCC16 */ +OPCODE(0x6700) +{ + + if (!flag_NotZ) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(12) +} + +/* BCC16 */ +OPCODE(0x6800) +{ + + if (!(flag_V & 0x80)) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(12) +} + +/* BCC16 */ +OPCODE(0x6900) +{ + + if (flag_V & 0x80) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(12) +} + +/* BCC16 */ +OPCODE(0x6A00) +{ + + if (!(flag_N & 0x80)) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(12) +} + +/* BCC16 */ +OPCODE(0x6B00) +{ + + if (flag_N & 0x80) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(12) +} + +/* BCC16 */ +OPCODE(0x6C00) +{ + + if (!((flag_N ^ flag_V) & 0x80)) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(12) +} + +/* BCC16 */ +OPCODE(0x6D00) +{ + + if ((flag_N ^ flag_V) & 0x80) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(12) +} + +/* BCC16 */ +OPCODE(0x6E00) +{ + + if (flag_NotZ && (!((flag_N ^ flag_V) & 0x80))) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(12) +} + +/* BCC16 */ +OPCODE(0x6F00) +{ + + if ((!flag_NotZ) || ((flag_N ^ flag_V) & 0x80)) + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + RET(10) + } + INC_PC(2); + RET(12) +} + +/* BRA */ +OPCODE(0x6001) +{ +#ifdef FAME_CHECK_BRANCHES + u32 newPC = UNBASED_PC; + s8 offs=Opcode; + newPC += offs; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(offs) +#else + INC_PC((s8)(Opcode & 0xFE)); +#endif + RET(10) +} + +/* BRA16 */ +OPCODE(0x6000) +{ + + { + u32 newPC; + + newPC = UNBASED_PC; + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + } + RET(10) +} + +/* BSR */ +OPCODE(0x6101) +{ + u32 oldPC; + + + oldPC = UNBASED_PC; + PUSH_32_F(oldPC) +#ifdef FAME_CHECK_BRANCHES + { + s8 offs; + offs = Opcode; + oldPC += offs; + SET_PC(oldPC); + CHECK_BRANCH_EXCEPTION(offs) + } +#else + INC_PC((s8)(Opcode & 0xFE)); +#endif + RET(18) +} + +/* BSR16 */ +OPCODE(0x6100) +{ + + { + u32 oldPC, newPC; + + newPC = UNBASED_PC; + oldPC = newPC + 2; + PUSH_32_F(oldPC) + newPC += GET_SWORD; + SET_PC(newPC); + CHECK_BRANCH_EXCEPTION(newPC) + } + RET(18) +} + +/* MOVEQ */ +OPCODE(0x7000) +{ + u32 res; + + res = (s32)(s8)Opcode; + flag_C = flag_V = 0; + flag_N = flag_NotZ = res; + DREGu32((Opcode >> 9) & 7) = res; + RET(4) +} + +/* ORaD */ +OPCODE(0x8000) +{ + u32 res; + u32 src; + + src = DREGu8((Opcode >> 0) & 7); + res = DREGu8((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(4) +} + +/* ORaD */ +OPCODE(0x8010) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ORaD */ +OPCODE(0x8018) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ORaD */ +OPCODE(0x8020) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(10) +} + +/* ORaD */ +OPCODE(0x8028) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ORaD */ +OPCODE(0x8030) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ORaD */ +OPCODE(0x8038) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ORaD */ +OPCODE(0x8039) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ORaD */ +OPCODE(0x803A) +{ + u32 adr, res; + u32 src; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ORaD */ +OPCODE(0x803B) +{ + u32 adr, res; + u32 src; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ORaD */ +OPCODE(0x803C) +{ + u32 res; + u32 src; + + FETCH_BYTE(src); + res = DREGu8((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ORaD */ +OPCODE(0x801F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ORaD */ +OPCODE(0x8027) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(10) +} + +/* ORaD */ +OPCODE(0x8040) +{ + u32 res; + u32 src; + + src = DREGu16((Opcode >> 0) & 7); + res = DREGu16((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(4) +} + +/* ORaD */ +OPCODE(0x8050) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ORaD */ +OPCODE(0x8058) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ORaD */ +OPCODE(0x8060) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(10) +} + +/* ORaD */ +OPCODE(0x8068) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ORaD */ +OPCODE(0x8070) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ORaD */ +OPCODE(0x8078) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ORaD */ +OPCODE(0x8079) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ORaD */ +OPCODE(0x807A) +{ + u32 adr, res; + u32 src; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ORaD */ +OPCODE(0x807B) +{ + u32 adr, res; + u32 src; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ORaD */ +OPCODE(0x807C) +{ + u32 res; + u32 src; + + FETCH_WORD(src); + res = DREGu16((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ORaD */ +OPCODE(0x805F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ORaD */ +OPCODE(0x8067) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(10) +} + +/* ORaD */ +OPCODE(0x8080) +{ + u32 res; + u32 src; + + src = DREGu32((Opcode >> 0) & 7); + res = DREGu32((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ORaD */ +OPCODE(0x8090) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ORaD */ +OPCODE(0x8098) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ORaD */ +OPCODE(0x80A0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ORaD */ +OPCODE(0x80A8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(18) +} + +/* ORaD */ +OPCODE(0x80B0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(20) +} + +/* ORaD */ +OPCODE(0x80B8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(18) +} + +/* ORaD */ +OPCODE(0x80B9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(22) +} + +/* ORaD */ +OPCODE(0x80BA) +{ + u32 adr, res; + u32 src; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(18) +} + +/* ORaD */ +OPCODE(0x80BB) +{ + u32 adr, res; + u32 src; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(20) +} + +/* ORaD */ +OPCODE(0x80BC) +{ + u32 res; + u32 src; + + FETCH_LONG(src); + res = DREGu32((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ORaD */ +OPCODE(0x809F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ORaD */ +OPCODE(0x80A7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ORDa */ +OPCODE(0x8110) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* ORDa */ +OPCODE(0x8118) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* ORDa */ +OPCODE(0x8120) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* ORDa */ +OPCODE(0x8128) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ORDa */ +OPCODE(0x8130) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ORDa */ +OPCODE(0x8138) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ORDa */ +OPCODE(0x8139) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* ORDa */ +OPCODE(0x811F) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* ORDa */ +OPCODE(0x8127) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + res |= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* ORDa */ +OPCODE(0x8150) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ORDa */ +OPCODE(0x8158) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ORDa */ +OPCODE(0x8160) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ORDa */ +OPCODE(0x8168) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ORDa */ +OPCODE(0x8170) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ORDa */ +OPCODE(0x8178) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ORDa */ +OPCODE(0x8179) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ORDa */ +OPCODE(0x815F) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ORDa */ +OPCODE(0x8167) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ORDa */ +OPCODE(0x8190) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* ORDa */ +OPCODE(0x8198) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* ORDa */ +OPCODE(0x81A0) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* ORDa */ +OPCODE(0x81A8) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* ORDa */ +OPCODE(0x81B0) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(26) +} + +/* ORDa */ +OPCODE(0x81B8) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* ORDa */ +OPCODE(0x81B9) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* ORDa */ +OPCODE(0x819F) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* ORDa */ +OPCODE(0x81A7) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + res |= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* SBCD */ +OPCODE(0x8100) +{ + u32 res; + u32 src, dst; + + src = DREGu8((Opcode >> 0) & 7); + dst = DREGu8((Opcode >> 9) & 7); + res = (dst & 0xF) - (src & 0xF) - ((flag_X >> M68K_SR_X_SFT) & 1); + if (res > 9) res -= 6; + res += (dst & 0xF0) - (src & 0xF0); + if (res > 0x99) + { + res += 0xA0; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_NotZ |= res & 0xFF; + flag_N = res; + DREGu8((Opcode >> 9) & 7) = res; + RET(6) +} + +/* SBCDM */ +OPCODE(0x8108) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) - (src & 0xF) - ((flag_X >> M68K_SR_X_SFT) & 1); + if (res > 9) res -= 6; + res += (dst & 0xF0) - (src & 0xF0); + if (res > 0x99) + { + res += 0xA0; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_NotZ |= res & 0xFF; + flag_N = res; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* SBCD7M */ +OPCODE(0x810F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) - (src & 0xF) - ((flag_X >> M68K_SR_X_SFT) & 1); + if (res > 9) res -= 6; + res += (dst & 0xF0) - (src & 0xF0); + if (res > 0x99) + { + res += 0xA0; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_NotZ |= res & 0xFF; + flag_N = res; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* SBCDM7 */ +OPCODE(0x8F08) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) - (src & 0xF) - ((flag_X >> M68K_SR_X_SFT) & 1); + if (res > 9) res -= 6; + res += (dst & 0xF0) - (src & 0xF0); + if (res > 0x99) + { + res += 0xA0; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_NotZ |= res & 0xFF; + flag_N = res; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* SBCD7M7 */ +OPCODE(0x8F0F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) - (src & 0xF) - ((flag_X >> M68K_SR_X_SFT) & 1); + if (res > 9) res -= 6; + res += (dst & 0xF0) - (src & 0xF0); + if (res > 0x99) + { + res += 0xA0; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_NotZ |= res & 0xFF; + flag_N = res; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* DIVU */ +OPCODE(0x80C0) +{ + u32 res; + u32 src, dst; + const u32 main_ea_cycles = 0; + + src = DREGu16((Opcode >> 0) & 7); + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + SET_FLAGS_DIV_OVERFLOW + RET(main_ea_cycles + 10) + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivu68kCycles(dst, src)) +#else + RET(106) +#endif +} + +/* DIVU */ +OPCODE(0x80D0) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 4; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + SET_FLAGS_DIV_OVERFLOW + RET(main_ea_cycles + 10) + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivu68kCycles(dst, src)) +#else + RET(110) +#endif +} + +/* DIVU */ +OPCODE(0x80D8) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 4; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + SET_FLAGS_DIV_OVERFLOW + RET(main_ea_cycles + 10) + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivu68kCycles(dst, src)) +#else + RET(110) +#endif +} + +/* DIVU */ +OPCODE(0x80E0) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 6; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + SET_FLAGS_DIV_OVERFLOW + RET(main_ea_cycles + 10) + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivu68kCycles(dst, src)) +#else + RET(112) +#endif +} + +/* DIVU */ +OPCODE(0x80E8) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 8; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + SET_FLAGS_DIV_OVERFLOW + RET(main_ea_cycles + 10) + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivu68kCycles(dst, src)) +#else + RET(114) +#endif +} + +/* DIVU */ +OPCODE(0x80F0) +{ + u32 adr, res; + u32 src, dst; + u32 main_ea_cycles = 10; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + SET_FLAGS_DIV_OVERFLOW + RET(main_ea_cycles + 10) + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivu68kCycles(dst, src)) +#else + RET(116) +#endif +} + +/* DIVU */ +OPCODE(0x80F8) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 8; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + SET_FLAGS_DIV_OVERFLOW + RET(main_ea_cycles + 10) + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivu68kCycles(dst, src)) +#else + RET(114) +#endif +} + +/* DIVU */ +OPCODE(0x80F9) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 12; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + SET_FLAGS_DIV_OVERFLOW + RET(main_ea_cycles + 10) + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivu68kCycles(dst, src)) +#else + RET(118) +#endif +} + +/* DIVU */ +OPCODE(0x80FA) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 8; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + SET_FLAGS_DIV_OVERFLOW + RET(main_ea_cycles + 10) + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivu68kCycles(dst, src)) +#else + RET(114) +#endif +} + +/* DIVU */ +OPCODE(0x80FB) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 10; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + SET_FLAGS_DIV_OVERFLOW + RET(main_ea_cycles + 10) + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivu68kCycles(dst, src)) +#else + RET(116) +#endif +} + +/* DIVU */ +OPCODE(0x80FC) +{ + u32 res; + u32 src, dst; + const u32 main_ea_cycles = 4; + + FETCH_WORD(src); + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + SET_FLAGS_DIV_OVERFLOW + RET(main_ea_cycles + 10) + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivu68kCycles(dst, src)) +#else + RET(110) +#endif +} + +/* DIVU */ +OPCODE(0x80DF) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 4; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + SET_FLAGS_DIV_OVERFLOW + RET(main_ea_cycles + 10) + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivu68kCycles(dst, src)) +#else + RET(110) +#endif +} + +/* DIVU */ +OPCODE(0x80E7) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 6; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + SET_FLAGS_DIV_OVERFLOW + RET(main_ea_cycles + 10) + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivu68kCycles(dst, src)) +#else + RET(112) +#endif +} + +/* DIVS */ +OPCODE(0x81C0) +{ + u32 res; + u32 src, dst; + const u32 main_ea_cycles = 0; + + src = (s32)DREGs16((Opcode >> 0) & 7); + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + if ((dst == 0x80000000) && (src == (u32)-1)) + { + flag_NotZ = flag_N = 0; + flag_V = flag_C = 0; + res = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(50) +#endif + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + SET_FLAGS_DIV_OVERFLOW +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + 16 + ((dst & 0x80000000)?2:0)) +#else + RET(main_ea_cycles + 17) +#endif + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(139) +#endif +} + +/* DIVS */ +OPCODE(0x81D0) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 4; + + adr = AREG((Opcode >> 0) & 7); + READSX_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + if ((dst == 0x80000000) && (src == (u32)-1)) + { + flag_NotZ = flag_N = 0; + flag_V = flag_C = 0; + res = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(54) +#endif + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + SET_FLAGS_DIV_OVERFLOW +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + 16 + ((dst & 0x80000000)?2:0)) +#else + RET(main_ea_cycles + 17) +#endif + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(143) +#endif +} + +/* DIVS */ +OPCODE(0x81D8) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 4; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READSX_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + if ((dst == 0x80000000) && (src == (u32)-1)) + { + flag_NotZ = flag_N = 0; + flag_V = flag_C = 0; + res = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(54) +#endif + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + SET_FLAGS_DIV_OVERFLOW +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + 16 + ((dst & 0x80000000)?2:0)) +#else + RET(main_ea_cycles + 17) +#endif + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(143) +#endif +} + +/* DIVS */ +OPCODE(0x81E0) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 6; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READSX_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + if ((dst == 0x80000000) && (src == (u32)-1)) + { + flag_NotZ = flag_N = 0; + flag_V = flag_C = 0; + res = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(56) +#endif + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + SET_FLAGS_DIV_OVERFLOW +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + 16 + ((dst & 0x80000000)?2:0)) +#else + RET(main_ea_cycles + 17) +#endif + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(145) +#endif +} + +/* DIVS */ +OPCODE(0x81E8) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 8; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READSX_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + if ((dst == 0x80000000) && (src == (u32)-1)) + { + flag_NotZ = flag_N = 0; + flag_V = flag_C = 0; + res = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + RET(getDivs68kCycles(dst, src)) +#else + RET(58) +#endif + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + SET_FLAGS_DIV_OVERFLOW +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + 16 + ((dst & 0x80000000)?2:0)) +#else + RET(main_ea_cycles + 17) +#endif + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(147) +#endif +} + +/* DIVS */ +OPCODE(0x81F0) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 10; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READSX_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + if ((dst == 0x80000000) && (src == (u32)-1)) + { + flag_NotZ = flag_N = 0; + flag_V = flag_C = 0; + res = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(60) +#endif + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + SET_FLAGS_DIV_OVERFLOW +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + 16 + ((dst & 0x80000000)?2:0)) +#else + RET(main_ea_cycles + 17) +#endif + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(149) +#endif +} + +/* DIVS */ +OPCODE(0x81F8) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 8; + + FETCH_SWORD(adr); + READSX_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + if ((dst == 0x80000000) && (src == (u32)-1)) + { + flag_NotZ = flag_N = 0; + flag_V = flag_C = 0; + res = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(58) +#endif + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + SET_FLAGS_DIV_OVERFLOW +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + 16 + ((dst & 0x80000000)?2:0)) +#else + RET(main_ea_cycles + 17) +#endif + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(147) +#endif +} + +/* DIVS */ +OPCODE(0x81F9) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 12; + + FETCH_LONG(adr); + READSX_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + if ((dst == 0x80000000) && (src == (u32)-1)) + { + flag_NotZ = flag_N = 0; + flag_V = flag_C = 0; + res = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(62) +#endif + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + SET_FLAGS_DIV_OVERFLOW +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + 16 + ((dst & 0x80000000)?2:0)) +#else + RET(main_ea_cycles + 17) +#endif + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(151) +#endif +} + +/* DIVS */ +OPCODE(0x81FA) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 8; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READSX_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + if ((dst == 0x80000000) && (src == (u32)-1)) + { + flag_NotZ = flag_N = 0; + flag_V = flag_C = 0; + res = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(58) +#endif + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + SET_FLAGS_DIV_OVERFLOW +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + 16 + ((dst & 0x80000000)?2:0)) +#else + RET(main_ea_cycles + 17) +#endif + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(147) +#endif +} + +/* DIVS */ +OPCODE(0x81FB) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 10; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READSX_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + if ((dst == 0x80000000) && (src == (u32)-1)) + { + flag_NotZ = flag_N = 0; + flag_V = flag_C = 0; + res = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(60) +#endif + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + SET_FLAGS_DIV_OVERFLOW +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + 16 + ((dst & 0x80000000)?2:0)) +#else + RET(main_ea_cycles + 17) +#endif + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(149) +#endif +} + +/* DIVS */ +OPCODE(0x81FC) +{ + u32 res; + u32 src, dst; + const u32 main_ea_cycles = 4; + + FETCH_SWORD(src); + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + if ((dst == 0x80000000) && (src == (u32)-1)) + { + flag_NotZ = flag_N = 0; + flag_V = flag_C = 0; + res = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(54) +#endif + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + SET_FLAGS_DIV_OVERFLOW +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + 16 + ((dst & 0x80000000)?2:0)) +#else + RET(main_ea_cycles + 17) +#endif + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(143) +#endif +} + +/* DIVS */ +OPCODE(0x81DF) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 4; + + adr = AREG(7); + AREG(7) += 2; + READSX_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + if ((dst == 0x80000000) && (src == (u32)-1)) + { + flag_NotZ = flag_N = 0; + flag_V = flag_C = 0; + res = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(54) +#endif + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + SET_FLAGS_DIV_OVERFLOW +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + 16 + ((dst & 0x80000000)?2:0)) +#else + RET(main_ea_cycles + 17) +#endif + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(143) +#endif +} + +/* DIVS */ +OPCODE(0x81E7) +{ + u32 adr, res; + u32 src, dst; + const u32 main_ea_cycles = 6; + + adr = AREG(7) - 2; + AREG(7) = adr; + READSX_WORD_F(adr, src) + if (src == 0) + { + SET_FLAGS_DIV_ZERO + execute_exception(M68K_ZERO_DIVIDE_EX); + RET(main_ea_cycles) + } + dst = DREGu32((Opcode >> 9) & 7); + if ((dst == 0x80000000) && (src == (u32)-1)) + { + flag_NotZ = flag_N = 0; + flag_V = flag_C = 0; + res = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(56) +#endif + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + SET_FLAGS_DIV_OVERFLOW +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + 16 + ((dst & 0x80000000)?2:0)) +#else + RET(main_ea_cycles + 17) +#endif + } + q &= 0x0000FFFF; + flag_NotZ = q; + flag_N = q >> 8; + flag_V = flag_C = 0; + res = q | (r << 16); + DREGu32((Opcode >> 9) & 7) = res; + } +#ifdef FAME_ACCURATE_TIMING + RET(main_ea_cycles + getDivs68kCycles(dst, src)) +#else + RET(145) +#endif +} + +/* SUBaD */ +OPCODE(0x9000) +{ + u32 res; + u32 src, dst; + + src = DREGu8((Opcode >> 0) & 7); + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(4) +} + +/* SUBaD */ +OPCODE(0x9008) +{ +#if 0 + /* can't read byte from Ax registers ! */ + m68kcontext.execinfo |= M68K_FAULTED; + io_cycle_counter = 0; + /* + goto famec_Exec_End; + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + */ +#endif + RET(4) +} + +/* SUBaD */ +OPCODE(0x9010) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBaD */ +OPCODE(0x9018) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBaD */ +OPCODE(0x9020) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(10) +} + +/* SUBaD */ +OPCODE(0x9028) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* SUBaD */ +OPCODE(0x9030) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(14) +} + +/* SUBaD */ +OPCODE(0x9038) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* SUBaD */ +OPCODE(0x9039) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(16) +} + +/* SUBaD */ +OPCODE(0x903A) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* SUBaD */ +OPCODE(0x903B) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(14) +} + +/* SUBaD */ +OPCODE(0x903C) +{ + u32 res; + u32 src, dst; + + FETCH_BYTE(src); + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBaD */ +OPCODE(0x901F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBaD */ +OPCODE(0x9027) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(10) +} + +/* SUBaD */ +OPCODE(0x9040) +{ + u32 res; + u32 src, dst; + + src = DREGu16((Opcode >> 0) & 7); + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(4) +} + +/* SUBaD */ +OPCODE(0x9048) +{ + u32 res; + u32 src, dst; + + src = AREGu16((Opcode >> 0) & 7); + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(4) +} + +/* SUBaD */ +OPCODE(0x9050) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBaD */ +OPCODE(0x9058) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBaD */ +OPCODE(0x9060) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(10) +} + +/* SUBaD */ +OPCODE(0x9068) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* SUBaD */ +OPCODE(0x9070) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(14) +} + +/* SUBaD */ +OPCODE(0x9078) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* SUBaD */ +OPCODE(0x9079) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(16) +} + +/* SUBaD */ +OPCODE(0x907A) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* SUBaD */ +OPCODE(0x907B) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(14) +} + +/* SUBaD */ +OPCODE(0x907C) +{ + u32 res; + u32 src, dst; + + FETCH_WORD(src); + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBaD */ +OPCODE(0x905F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBaD */ +OPCODE(0x9067) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(10) +} + +/* SUBaD */ +OPCODE(0x9080) +{ + u32 res; + u32 src, dst; + + src = DREGu32((Opcode >> 0) & 7); + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBaD */ +OPCODE(0x9088) +{ + u32 res; + u32 src, dst; + + src = AREGu32((Opcode >> 0) & 7); + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBaD */ +OPCODE(0x9090) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(14) +} + +/* SUBaD */ +OPCODE(0x9098) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(14) +} + +/* SUBaD */ +OPCODE(0x90A0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* SUBaD */ +OPCODE(0x90A8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(18) +} + +/* SUBaD */ +OPCODE(0x90B0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(20) +} + +/* SUBaD */ +OPCODE(0x90B8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(18) +} + +/* SUBaD */ +OPCODE(0x90B9) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(22) +} + +/* SUBaD */ +OPCODE(0x90BA) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(18) +} + +/* SUBaD */ +OPCODE(0x90BB) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(20) +} + +/* SUBaD */ +OPCODE(0x90BC) +{ + u32 res; + u32 src, dst; + + FETCH_LONG(src); + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* SUBaD */ +OPCODE(0x909F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(14) +} + +/* SUBaD */ +OPCODE(0x90A7) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* SUBDa */ +OPCODE(0x9110) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* SUBDa */ +OPCODE(0x9118) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* SUBDa */ +OPCODE(0x9120) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* SUBDa */ +OPCODE(0x9128) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* SUBDa */ +OPCODE(0x9130) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* SUBDa */ +OPCODE(0x9138) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* SUBDa */ +OPCODE(0x9139) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* SUBDa */ +OPCODE(0x911F) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* SUBDa */ +OPCODE(0x9127) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* SUBDa */ +OPCODE(0x9150) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* SUBDa */ +OPCODE(0x9158) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* SUBDa */ +OPCODE(0x9160) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* SUBDa */ +OPCODE(0x9168) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* SUBDa */ +OPCODE(0x9170) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* SUBDa */ +OPCODE(0x9178) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* SUBDa */ +OPCODE(0x9179) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* SUBDa */ +OPCODE(0x915F) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* SUBDa */ +OPCODE(0x9167) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* SUBDa */ +OPCODE(0x9190) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* SUBDa */ +OPCODE(0x9198) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* SUBDa */ +OPCODE(0x91A0) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* SUBDa */ +OPCODE(0x91A8) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* SUBDa */ +OPCODE(0x91B0) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(26) +} + +/* SUBDa */ +OPCODE(0x91B8) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* SUBDa */ +OPCODE(0x91B9) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* SUBDa */ +OPCODE(0x919F) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* SUBDa */ +OPCODE(0x91A7) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* SUBX */ +OPCODE(0x9100) +{ + u32 res; + u32 src, dst; + + src = DREGu8((Opcode >> 0) & 7); + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src - ((flag_X >> 8) & 1); + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ |= res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(4) +} + +/* SUBX */ +OPCODE(0x9140) +{ + u32 res; + u32 src, dst; + + src = DREGu16((Opcode >> 0) & 7); + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src - ((flag_X >> 8) & 1); + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(4) +} + +/* SUBX */ +OPCODE(0x9180) +{ + u32 res; + u32 src, dst; + + src = DREGu32((Opcode >> 0) & 7); + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBXM */ +OPCODE(0x9108) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + READ_BYTE_F(adr, dst) + res = dst - src - ((flag_X >> 8) & 1); + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* SUBXM */ +OPCODE(0x9148) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + READ_WORD_F(adr, dst) + res = dst - src - ((flag_X >> 8) & 1); + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* SUBXM */ +OPCODE(0x9188) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + READ_LONG_F(adr, dst) + res = dst - src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* SUBX7M */ +OPCODE(0x910F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + READ_BYTE_F(adr, dst) + res = dst - src - ((flag_X >> 8) & 1); + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* SUBX7M */ +OPCODE(0x914F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + READ_WORD_F(adr, dst) + res = dst - src - ((flag_X >> 8) & 1); + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* SUBX7M */ +OPCODE(0x918F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + READ_LONG_F(adr, dst) + res = dst - src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* SUBXM7 */ +OPCODE(0x9F08) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = dst - src - ((flag_X >> 8) & 1); + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* SUBXM7 */ +OPCODE(0x9F48) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, dst) + res = dst - src - ((flag_X >> 8) & 1); + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* SUBXM7 */ +OPCODE(0x9F88) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, src) + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, dst) + res = dst - src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* SUBX7M7 */ +OPCODE(0x9F0F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = dst - src - ((flag_X >> 8) & 1); + flag_N = flag_X = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* SUBX7M7 */ +OPCODE(0x9F4F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, dst) + res = dst - src - ((flag_X >> 8) & 1); + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* SUBX7M7 */ +OPCODE(0x9F8F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, src) + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, dst) + res = dst - src - ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_X = flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* SUBA */ +OPCODE(0x90C0) +{ + u32 res; + u32 src, dst; + + src = (s32)DREGs16((Opcode >> 0) & 7); + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBA */ +OPCODE(0x90C8) +{ + u32 res; + u32 src, dst; + + src = (s32)AREGs16((Opcode >> 0) & 7); + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBA */ +OPCODE(0x90D0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* SUBA */ +OPCODE(0x90D8) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* SUBA */ +OPCODE(0x90E0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(14) +} + +/* SUBA */ +OPCODE(0x90E8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* SUBA */ +OPCODE(0x90F0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(18) +} + +/* SUBA */ +OPCODE(0x90F8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* SUBA */ +OPCODE(0x90F9) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(20) +} + +/* SUBA */ +OPCODE(0x90FA) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* SUBA */ +OPCODE(0x90FB) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(18) +} + +/* SUBA */ +OPCODE(0x90FC) +{ + u32 res; + u32 src, dst; + + FETCH_SWORD(src); + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* SUBA */ +OPCODE(0x90DF) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 2; + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* SUBA */ +OPCODE(0x90E7) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(14) +} + +/* SUBA */ +OPCODE(0x91C0) +{ + u32 res; + u32 src, dst; + + src = (s32)DREGs32((Opcode >> 0) & 7); + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBA */ +OPCODE(0x91C8) +{ + u32 res; + u32 src, dst; + + src = (s32)AREGs32((Opcode >> 0) & 7); + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* SUBA */ +OPCODE(0x91D0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(14) +} + +/* SUBA */ +OPCODE(0x91D8) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(14) +} + +/* SUBA */ +OPCODE(0x91E0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* SUBA */ +OPCODE(0x91E8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(18) +} + +/* SUBA */ +OPCODE(0x91F0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(20) +} + +/* SUBA */ +OPCODE(0x91F8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(18) +} + +/* SUBA */ +OPCODE(0x91F9) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(22) +} + +/* SUBA */ +OPCODE(0x91FA) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(18) +} + +/* SUBA */ +OPCODE(0x91FB) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(20) +} + +/* SUBA */ +OPCODE(0x91FC) +{ + u32 res; + u32 src, dst; + + FETCH_LONG(src); + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* SUBA */ +OPCODE(0x91DF) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 4; + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(14) +} + +/* SUBA */ +OPCODE(0x91E7) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 4; + AREG(7) = adr; + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* CMP */ +OPCODE(0xB000) +{ + u32 res; + u32 src, dst; + + src = DREGu8((Opcode >> 0) & 7); + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(4) +} + +/* CMP */ +OPCODE(0xB008) +{ +#if 0 + /* can't read byte from Ax registers ! */ + m68kcontext.execinfo |= M68K_FAULTED; + io_cycle_counter = 0; + /* + goto famec_Exec_End; + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + */ +#endif + RET(4) +} + +/* CMP */ +OPCODE(0xB010) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(8) +} + +/* CMP */ +OPCODE(0xB018) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(8) +} + +/* CMP */ +OPCODE(0xB020) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(10) +} + +/* CMP */ +OPCODE(0xB028) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(12) +} + +/* CMP */ +OPCODE(0xB030) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(14) +} + +/* CMP */ +OPCODE(0xB038) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(12) +} + +/* CMP */ +OPCODE(0xB039) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(16) +} + +/* CMP */ +OPCODE(0xB03A) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(12) +} + +/* CMP */ +OPCODE(0xB03B) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(14) +} + +/* CMP */ +OPCODE(0xB03C) +{ + u32 res; + u32 src, dst; + + FETCH_BYTE(src); + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(8) +} + +/* CMP */ +OPCODE(0xB01F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(8) +} + +/* CMP */ +OPCODE(0xB027) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(10) +} + +/* CMP */ +OPCODE(0xB040) +{ + u32 res; + u32 src, dst; + + src = DREGu16((Opcode >> 0) & 7); + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(4) +} + +/* CMP */ +OPCODE(0xB048) +{ + u32 res; + u32 src, dst; + + src = AREGu16((Opcode >> 0) & 7); + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(4) +} + +/* CMP */ +OPCODE(0xB050) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(8) +} + +/* CMP */ +OPCODE(0xB058) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(8) +} + +/* CMP */ +OPCODE(0xB060) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(10) +} + +/* CMP */ +OPCODE(0xB068) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(12) +} + +/* CMP */ +OPCODE(0xB070) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(14) +} + +/* CMP */ +OPCODE(0xB078) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(12) +} + +/* CMP */ +OPCODE(0xB079) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(16) +} + +/* CMP */ +OPCODE(0xB07A) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(12) +} + +/* CMP */ +OPCODE(0xB07B) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(14) +} + +/* CMP */ +OPCODE(0xB07C) +{ + u32 res; + u32 src, dst; + + FETCH_WORD(src); + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(8) +} + +/* CMP */ +OPCODE(0xB05F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(8) +} + +/* CMP */ +OPCODE(0xB067) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(10) +} + +/* CMP */ +OPCODE(0xB080) +{ + u32 res; + u32 src, dst; + + src = DREGu32((Opcode >> 0) & 7); + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(6) +} + +/* CMP */ +OPCODE(0xB088) +{ + u32 res; + u32 src, dst; + + src = AREGu32((Opcode >> 0) & 7); + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(6) +} + +/* CMP */ +OPCODE(0xB090) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(14) +} + +/* CMP */ +OPCODE(0xB098) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(14) +} + +/* CMP */ +OPCODE(0xB0A0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(16) +} + +/* CMP */ +OPCODE(0xB0A8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(18) +} + +/* CMP */ +OPCODE(0xB0B0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(20) +} + +/* CMP */ +OPCODE(0xB0B8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(18) +} + +/* CMP */ +OPCODE(0xB0B9) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(22) +} + +/* CMP */ +OPCODE(0xB0BA) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(18) +} + +/* CMP */ +OPCODE(0xB0BB) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(20) +} + +/* CMP */ +OPCODE(0xB0BC) +{ + u32 res; + u32 src, dst; + + FETCH_LONG(src); + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(14) +} + +/* CMP */ +OPCODE(0xB09F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(14) +} + +/* CMP */ +OPCODE(0xB0A7) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(16) +} + +/* CMPM */ +OPCODE(0xB108) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, src) + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(12) +} + +/* CMPM */ +OPCODE(0xB148) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(12) +} + +/* CMPM */ +OPCODE(0xB188) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, src) + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(20) +} + +/* CMP7M */ +OPCODE(0xB10F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, src) + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 1; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(12) +} + +/* CMP7M */ +OPCODE(0xB14F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 2; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(12) +} + +/* CMP7M */ +OPCODE(0xB18F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, src) + adr = AREG((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) += 4; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(20) +} + +/* CMPM7 */ +OPCODE(0xBF08) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, src) + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(12) +} + +/* CMPM7 */ +OPCODE(0xBF48) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(12) +} + +/* CMPM7 */ +OPCODE(0xBF88) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, src) + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(20) +} + +/* CMP7M7 */ +OPCODE(0xBF0F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, src) + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, dst) + res = dst - src; + flag_N = flag_C = res; + flag_V = (src ^ dst) & (res ^ dst); + flag_NotZ = res & 0xFF; + RET(12) +} + +/* CMP7M7 */ +OPCODE(0xBF4F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, dst) + res = dst - src; + flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + flag_N = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + RET(12) +} + +/* CMP7M7 */ +OPCODE(0xBF8F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, src) + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, dst) + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(20) +} + +/* EORDa */ +OPCODE(0xB100) +{ + u32 res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + res = DREGu8((Opcode >> 0) & 7); + res ^= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 0) & 7) = res; + RET(4) +} + +/* EORDa */ +OPCODE(0xB110) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* EORDa */ +OPCODE(0xB118) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* EORDa */ +OPCODE(0xB120) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* EORDa */ +OPCODE(0xB128) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* EORDa */ +OPCODE(0xB130) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* EORDa */ +OPCODE(0xB138) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* EORDa */ +OPCODE(0xB139) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* EORDa */ +OPCODE(0xB11F) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* EORDa */ +OPCODE(0xB127) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + res ^= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* EORDa */ +OPCODE(0xB140) +{ + u32 res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + res = DREGu16((Opcode >> 0) & 7); + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 0) & 7) = res; + RET(4) +} + +/* EORDa */ +OPCODE(0xB150) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* EORDa */ +OPCODE(0xB158) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* EORDa */ +OPCODE(0xB160) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* EORDa */ +OPCODE(0xB168) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* EORDa */ +OPCODE(0xB170) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* EORDa */ +OPCODE(0xB178) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* EORDa */ +OPCODE(0xB179) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* EORDa */ +OPCODE(0xB15F) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* EORDa */ +OPCODE(0xB167) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* EORDa */ +OPCODE(0xB180) +{ + u32 res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + res = DREGu32((Opcode >> 0) & 7); + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) +} + +/* EORDa */ +OPCODE(0xB190) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* EORDa */ +OPCODE(0xB198) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* EORDa */ +OPCODE(0xB1A0) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* EORDa */ +OPCODE(0xB1A8) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* EORDa */ +OPCODE(0xB1B0) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(26) +} + +/* EORDa */ +OPCODE(0xB1B8) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* EORDa */ +OPCODE(0xB1B9) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* EORDa */ +OPCODE(0xB19F) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* EORDa */ +OPCODE(0xB1A7) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + res ^= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* CMPA */ +OPCODE(0xB0C0) +{ + u32 res; + u32 src, dst; + + src = (s32)DREGs16((Opcode >> 0) & 7); + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(6) +} + +/* CMPA */ +OPCODE(0xB0C8) +{ + u32 res; + u32 src, dst; + + src = (s32)AREGs16((Opcode >> 0) & 7); + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(6) +} + +/* CMPA */ +OPCODE(0xB0D0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(10) +} + +/* CMPA */ +OPCODE(0xB0D8) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(10) +} + +/* CMPA */ +OPCODE(0xB0E0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(12) +} + +/* CMPA */ +OPCODE(0xB0E8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(14) +} + +/* CMPA */ +OPCODE(0xB0F0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(16) +} + +/* CMPA */ +OPCODE(0xB0F8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(14) +} + +/* CMPA */ +OPCODE(0xB0F9) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(18) +} + +/* CMPA */ +OPCODE(0xB0FA) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(14) +} + +/* CMPA */ +OPCODE(0xB0FB) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(16) +} + +/* CMPA */ +OPCODE(0xB0FC) +{ + u32 res; + u32 src, dst; + + FETCH_SWORD(src); + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(10) +} + +/* CMPA */ +OPCODE(0xB0DF) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 2; + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(10) +} + +/* CMPA */ +OPCODE(0xB0E7) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(12) +} + +/* CMPA */ +OPCODE(0xB1C0) +{ + u32 res; + u32 src, dst; + + src = (s32)DREGs32((Opcode >> 0) & 7); + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(6) +} + +/* CMPA */ +OPCODE(0xB1C8) +{ + u32 res; + u32 src, dst; + + src = (s32)AREGs32((Opcode >> 0) & 7); + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(6) +} + +/* CMPA */ +OPCODE(0xB1D0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(14) +} + +/* CMPA */ +OPCODE(0xB1D8) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(14) +} + +/* CMPA */ +OPCODE(0xB1E0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(16) +} + +/* CMPA */ +OPCODE(0xB1E8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(18) +} + +/* CMPA */ +OPCODE(0xB1F0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(20) +} + +/* CMPA */ +OPCODE(0xB1F8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(18) +} + +/* CMPA */ +OPCODE(0xB1F9) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(22) +} + +/* CMPA */ +OPCODE(0xB1FA) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(18) +} + +/* CMPA */ +OPCODE(0xB1FB) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(20) +} + +/* CMPA */ +OPCODE(0xB1FC) +{ + u32 res; + u32 src, dst; + + FETCH_LONG(src); + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(14) +} + +/* CMPA */ +OPCODE(0xB1DF) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 4; + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(14) +} + +/* CMPA */ +OPCODE(0xB1E7) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 4; + AREG(7) = adr; + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst - src; + flag_NotZ = res; + flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + flag_N = res >> 24; + RET(16) +} + +/* ANDaD */ +OPCODE(0xC000) +{ + u32 res; + u32 src; + + src = DREGu8((Opcode >> 0) & 7); + res = DREGu8((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(4) +} + +/* ANDaD */ +OPCODE(0xC010) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ANDaD */ +OPCODE(0xC018) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ANDaD */ +OPCODE(0xC020) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(10) +} + +/* ANDaD */ +OPCODE(0xC028) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ANDaD */ +OPCODE(0xC030) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ANDaD */ +OPCODE(0xC038) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ANDaD */ +OPCODE(0xC039) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ANDaD */ +OPCODE(0xC03A) +{ + u32 adr, res; + u32 src; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ANDaD */ +OPCODE(0xC03B) +{ + u32 adr, res; + u32 src; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ANDaD */ +OPCODE(0xC03C) +{ + u32 res; + u32 src; + + FETCH_BYTE(src); + res = DREGu8((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ANDaD */ +OPCODE(0xC01F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ANDaD */ +OPCODE(0xC027) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + res = DREGu8((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_NZ_VC0 + DREGu8((Opcode >> 9) & 7) = res; + RET(10) +} + +/* ANDaD */ +OPCODE(0xC040) +{ + u32 res; + u32 src; + + src = DREGu16((Opcode >> 0) & 7); + res = DREGu16((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(4) +} + +/* ANDaD */ +OPCODE(0xC050) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ANDaD */ +OPCODE(0xC058) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ANDaD */ +OPCODE(0xC060) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(10) +} + +/* ANDaD */ +OPCODE(0xC068) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ANDaD */ +OPCODE(0xC070) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ANDaD */ +OPCODE(0xC078) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ANDaD */ +OPCODE(0xC079) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ANDaD */ +OPCODE(0xC07A) +{ + u32 adr, res; + u32 src; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ANDaD */ +OPCODE(0xC07B) +{ + u32 adr, res; + u32 src; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ANDaD */ +OPCODE(0xC07C) +{ + u32 res; + u32 src; + + FETCH_WORD(src); + res = DREGu16((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ANDaD */ +OPCODE(0xC05F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ANDaD */ +OPCODE(0xC067) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + DREGu16((Opcode >> 9) & 7) = res; + RET(10) +} + +/* ANDaD */ +OPCODE(0xC080) +{ + u32 res; + u32 src; + + src = DREGu32((Opcode >> 0) & 7); + res = DREGu32((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ANDaD */ +OPCODE(0xC090) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ANDaD */ +OPCODE(0xC098) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ANDaD */ +OPCODE(0xC0A0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ANDaD */ +OPCODE(0xC0A8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(18) +} + +/* ANDaD */ +OPCODE(0xC0B0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(20) +} + +/* ANDaD */ +OPCODE(0xC0B8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(18) +} + +/* ANDaD */ +OPCODE(0xC0B9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(22) +} + +/* ANDaD */ +OPCODE(0xC0BA) +{ + u32 adr, res; + u32 src; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(18) +} + +/* ANDaD */ +OPCODE(0xC0BB) +{ + u32 adr, res; + u32 src; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(20) +} + +/* ANDaD */ +OPCODE(0xC0BC) +{ + u32 res; + u32 src; + + FETCH_LONG(src); + res = DREGu32((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ANDaD */ +OPCODE(0xC09F) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ANDaD */ +OPCODE(0xC0A7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, src) + res = DREGu32((Opcode >> 9) & 7); + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ANDDa */ +OPCODE(0xC110) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* ANDDa */ +OPCODE(0xC118) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* ANDDa */ +OPCODE(0xC120) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* ANDDa */ +OPCODE(0xC128) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ANDDa */ +OPCODE(0xC130) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ANDDa */ +OPCODE(0xC138) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ANDDa */ +OPCODE(0xC139) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* ANDDa */ +OPCODE(0xC11F) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* ANDDa */ +OPCODE(0xC127) +{ + u32 adr, res; + u32 src; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, res) + res &= src; + SET_FLAGS_NZ_VC0 + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* ANDDa */ +OPCODE(0xC150) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ANDDa */ +OPCODE(0xC158) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ANDDa */ +OPCODE(0xC160) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ANDDa */ +OPCODE(0xC168) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ANDDa */ +OPCODE(0xC170) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ANDDa */ +OPCODE(0xC178) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ANDDa */ +OPCODE(0xC179) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ANDDa */ +OPCODE(0xC15F) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ANDDa */ +OPCODE(0xC167) +{ + u32 adr, res; + u32 src; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 8; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ANDDa */ +OPCODE(0xC190) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* ANDDa */ +OPCODE(0xC198) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* ANDDa */ +OPCODE(0xC1A0) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* ANDDa */ +OPCODE(0xC1A8) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* ANDDa */ +OPCODE(0xC1B0) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(26) +} + +/* ANDDa */ +OPCODE(0xC1B8) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* ANDDa */ +OPCODE(0xC1B9) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* ANDDa */ +OPCODE(0xC19F) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* ANDDa */ +OPCODE(0xC1A7) +{ + u32 adr, res; + u32 src; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, res) + res &= src; + SET_FLAGS_Z_VC0 + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* ABCD */ +OPCODE(0xC100) +{ + u32 res; + u32 src, dst; + + src = DREGu8((Opcode >> 0) & 7); + dst = DREGu8((Opcode >> 9) & 7); + res = (dst & 0xF) + (src & 0xF) + ((flag_X >> M68K_SR_X_SFT) & 1); + if (res > 9) res += 6; + res += (dst & 0xF0) + (src & 0xF0); + if (res > 0x99) + { + res -= 0xA0; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_NotZ |= res & 0xFF; + flag_N = res; + DREGu8((Opcode >> 9) & 7) = res; + RET(6) +} + +/* ABCDM */ +OPCODE(0xC108) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) + (src & 0xF) + ((flag_X >> M68K_SR_X_SFT) & 1); + if (res > 9) res += 6; + res += (dst & 0xF0) + (src & 0xF0); + if (res > 0x99) + { + res -= 0xA0; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_NotZ |= res & 0xFF; + flag_N = res; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ABCD7M */ +OPCODE(0xC10F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) + (src & 0xF) + ((flag_X >> M68K_SR_X_SFT) & 1); + if (res > 9) res += 6; + res += (dst & 0xF0) + (src & 0xF0); + if (res > 0x99) + { + res -= 0xA0; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_NotZ |= res & 0xFF; + flag_N = res; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ABCDM7 */ +OPCODE(0xCF08) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) + (src & 0xF) + ((flag_X >> M68K_SR_X_SFT) & 1); + if (res > 9) res += 6; + res += (dst & 0xF0) + (src & 0xF0); + if (res > 0x99) + { + res -= 0xA0; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_NotZ |= res & 0xFF; + flag_N = res; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ABCD7M7 */ +OPCODE(0xCF0F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) + (src & 0xF) + ((flag_X >> M68K_SR_X_SFT) & 1); + if (res > 9) res += 6; + res += (dst & 0xF0) + (src & 0xF0); + if (res > 0x99) + { + res -= 0xA0; + flag_X = flag_C = M68K_SR_C; + } + else flag_X = flag_C = 0; + flag_NotZ |= res & 0xFF; + flag_N = res; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* MULU */ +OPCODE(0xC0C0) +{ + u32 res; + u32 src; + + src = DREGu16((Opcode >> 0) & 7); + res = DREGu16((Opcode >> 9) & 7); + res *= src; + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src & 0xFFFF) * 2; + RET(38) +#else + RET(16 + 38) +#endif +} + +/* MULU */ +OPCODE(0xC0D0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res *= src; + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src & 0xFFFF) * 2; + RET(42) +#else + RET(16 + 42) +#endif +} + +/* MULU */ +OPCODE(0xC0D8) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res *= src; + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src & 0xFFFF) * 2; + RET(42) +#else + RET(16 + 42) +#endif +} + +/* MULU */ +OPCODE(0xC0E0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res *= src; + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src & 0xFFFF) * 2; + RET(44) +#else + RET(16 + 44) +#endif +} + +/* MULU */ +OPCODE(0xC0E8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res *= src; + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src & 0xFFFF) * 2; + RET(46) +#else + RET(16 + 46) +#endif +} + +/* MULU */ +OPCODE(0xC0F0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res *= src; + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src & 0xFFFF) * 2; + RET(48) +#else + RET(16 + 48) +#endif +} + +/* MULU */ +OPCODE(0xC0F8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res *= src; + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src & 0xFFFF) * 2; + RET(46) +#else + RET(16 + 46) +#endif +} + +/* MULU */ +OPCODE(0xC0F9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res *= src; + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src & 0xFFFF) * 2; + RET(50) +#else + RET(16 + 50) +#endif +} + +/* MULU */ +OPCODE(0xC0FA) +{ + u32 adr, res; + u32 src; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res *= src; + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src & 0xFFFF) * 2; + RET(46) +#else + RET(16 + 46) +#endif +} + +/* MULU */ +OPCODE(0xC0FB) +{ + u32 adr, res; + u32 src; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res *= src; + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src & 0xFFFF) * 2; + RET(48) +#else + RET(16 + 48) +#endif +} + +/* MULU */ +OPCODE(0xC0FC) +{ + u32 res; + u32 src; + + FETCH_WORD(src); + res = DREGu16((Opcode >> 9) & 7); + res *= src; + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src & 0xFFFF) * 2; + RET(42) +#else + RET(16 + 42) +#endif +} + +/* MULU */ +OPCODE(0xC0DF) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res *= src; + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src & 0xFFFF) * 2; + RET(42) +#else + RET(16 + 42) +#endif +} + +/* MULU */ +OPCODE(0xC0E7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + res = DREGu16((Opcode >> 9) & 7); + res *= src; + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src & 0xFFFF) * 2; + RET(44) +#else + RET(16 + 44) +#endif +} + +/* MULS */ +OPCODE(0xC1C0) +{ + u32 res; + u32 src; + + src = (s32)DREGs16((Opcode >> 0) & 7); + res = (s32)DREGs16((Opcode >> 9) & 7); + res = ((s32)res) * ((s32)src); + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src ^ (src << 1)) * 2; + RET(38) +#else + RET(8 + 38) +#endif +} + +/* MULS */ +OPCODE(0xC1D0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READSX_WORD_F(adr, src) + res = (s32)DREGs16((Opcode >> 9) & 7); + res = ((s32)res) * ((s32)src); + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src ^ (src << 1)) * 2; + RET(42) +#else + RET(8 + 42) +#endif +} + +/* MULS */ +OPCODE(0xC1D8) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READSX_WORD_F(adr, src) + res = (s32)DREGs16((Opcode >> 9) & 7); + res = ((s32)res) * ((s32)src); + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src ^ (src << 1)) * 2; + RET(42) +#else + RET(8 + 42) +#endif +} + +/* MULS */ +OPCODE(0xC1E0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READSX_WORD_F(adr, src) + res = (s32)DREGs16((Opcode >> 9) & 7); + res = ((s32)res) * ((s32)src); + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src ^ (src << 1)) * 2; + RET(44) +#else + RET(8 + 44) +#endif +} + +/* MULS */ +OPCODE(0xC1E8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READSX_WORD_F(adr, src) + res = (s32)DREGs16((Opcode >> 9) & 7); + res = ((s32)res) * ((s32)src); + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src ^ (src << 1)) * 2; + RET(46) +#else + RET(8 + 46) +#endif +} + +/* MULS */ +OPCODE(0xC1F0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READSX_WORD_F(adr, src) + res = (s32)DREGs16((Opcode >> 9) & 7); + res = ((s32)res) * ((s32)src); + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src ^ (src << 1)) * 2; + RET(48) +#else + RET(8 + 48) +#endif +} + +/* MULS */ +OPCODE(0xC1F8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READSX_WORD_F(adr, src) + res = (s32)DREGs16((Opcode >> 9) & 7); + res = ((s32)res) * ((s32)src); + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src ^ (src << 1)) * 2; + RET(46) +#else + RET(8 + 46) +#endif +} + +/* MULS */ +OPCODE(0xC1F9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READSX_WORD_F(adr, src) + res = (s32)DREGs16((Opcode >> 9) & 7); + res = ((s32)res) * ((s32)src); + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src ^ (src << 1)) * 2; + RET(50) +#else + RET(8 + 50) +#endif +} + +/* MULS */ +OPCODE(0xC1FA) +{ + u32 adr, res; + u32 src; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READSX_WORD_F(adr, src) + res = (s32)DREGs16((Opcode >> 9) & 7); + res = ((s32)res) * ((s32)src); + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src ^ (src << 1)) * 2; + RET(46) +#else + RET(8 + 46) +#endif +} + +/* MULS */ +OPCODE(0xC1FB) +{ + u32 adr, res; + u32 src; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READSX_WORD_F(adr, src) + res = (s32)DREGs16((Opcode >> 9) & 7); + res = ((s32)res) * ((s32)src); + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src ^ (src << 1)) * 2; + RET(48) +#else + RET(8 + 48) +#endif +} + +/* MULS */ +OPCODE(0xC1FC) +{ + u32 res; + u32 src; + + FETCH_SWORD(src); + res = (s32)DREGs16((Opcode >> 9) & 7); + res = ((s32)res) * ((s32)src); + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src ^ (src << 1)) * 2; + RET(42) +#else + RET(8 + 42) +#endif +} + +/* MULS */ +OPCODE(0xC1DF) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READSX_WORD_F(adr, src) + res = (s32)DREGs16((Opcode >> 9) & 7); + res = ((s32)res) * ((s32)src); + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src ^ (src << 1)) * 2; + RET(42) +#else + RET(8 + 42) +#endif +} + +/* MULS */ +OPCODE(0xC1E7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READSX_WORD_F(adr, src) + res = (s32)DREGs16((Opcode >> 9) & 7); + res = ((s32)res) * ((s32)src); + flag_N = res >> 24; + flag_NotZ = res; + flag_V = flag_C = 0; + DREGu32((Opcode >> 9) & 7) = res; +#ifdef FAME_ACCURATE_TIMING + /* count bits set in the memory operand */ + io_cycle_counter -= bitset_count(src ^ (src << 1)) * 2; + RET(44) +#else + RET(8 + 44) +#endif +} + +/* EXGDD */ +OPCODE(0xC140) +{ + u32 res; + u32 src; + + res = DREGu32((Opcode >> 0) & 7); + src = DREGu32((Opcode >> 9) & 7); + DREGu32((Opcode >> 9) & 7) = res; + res = src; + DREGu32((Opcode >> 0) & 7) = res; + RET(6) +} + +/* EXGAA */ +OPCODE(0xC148) +{ + u32 res; + u32 src; + + res = AREGu32((Opcode >> 0) & 7); + src = AREGu32((Opcode >> 9) & 7); + AREG((Opcode >> 9) & 7) = res; + res = src; + AREG((Opcode >> 0) & 7) = res; + RET(6) +} + +/* EXGAD */ +OPCODE(0xC188) +{ + u32 res; + u32 src; + + res = AREGu32((Opcode >> 0) & 7); + src = DREGu32((Opcode >> 9) & 7); + DREGu32((Opcode >> 9) & 7) = res; + res = src; + AREG((Opcode >> 0) & 7) = res; + RET(6) +} + +/* ADDaD */ +OPCODE(0xD000) +{ + u32 res; + u32 src, dst; + + src = DREGu8((Opcode >> 0) & 7); + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(4) +} + +/* ADDaD */ +OPCODE(0xD008) +{ +#if 0 + /* can't read byte from Ax registers ! */ + m68kcontext.execinfo |= M68K_FAULTED; + io_cycle_counter = 0; + /* + goto famec_Exec_End; + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + */ +#endif + RET(4) +} + +/* ADDaD */ +OPCODE(0xD010) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDaD */ +OPCODE(0xD018) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDaD */ +OPCODE(0xD020) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(10) +} + +/* ADDaD */ +OPCODE(0xD028) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ADDaD */ +OPCODE(0xD030) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ADDaD */ +OPCODE(0xD038) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ADDaD */ +OPCODE(0xD039) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ADDaD */ +OPCODE(0xD03A) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ADDaD */ +OPCODE(0xD03B) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ADDaD */ +OPCODE(0xD03C) +{ + u32 res; + u32 src, dst; + + FETCH_BYTE(src); + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDaD */ +OPCODE(0xD01F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDaD */ +OPCODE(0xD027) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(10) +} + +/* ADDaD */ +OPCODE(0xD040) +{ + u32 res; + u32 src, dst; + + src = DREGu16((Opcode >> 0) & 7); + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(4) +} + +/* ADDaD */ +OPCODE(0xD048) +{ + u32 res; + u32 src, dst; + + src = AREGu16((Opcode >> 0) & 7); + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(4) +} + +/* ADDaD */ +OPCODE(0xD050) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDaD */ +OPCODE(0xD058) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDaD */ +OPCODE(0xD060) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(10) +} + +/* ADDaD */ +OPCODE(0xD068) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ADDaD */ +OPCODE(0xD070) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ADDaD */ +OPCODE(0xD078) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ADDaD */ +OPCODE(0xD079) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ADDaD */ +OPCODE(0xD07A) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ADDaD */ +OPCODE(0xD07B) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ADDaD */ +OPCODE(0xD07C) +{ + u32 res; + u32 src, dst; + + FETCH_WORD(src); + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDaD */ +OPCODE(0xD05F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDaD */ +OPCODE(0xD067) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(10) +} + +/* ADDaD */ +OPCODE(0xD080) +{ + u32 res; + u32 src, dst; + + src = DREGu32((Opcode >> 0) & 7); + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDaD */ +OPCODE(0xD088) +{ + u32 res; + u32 src, dst; + + src = AREGu32((Opcode >> 0) & 7); + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDaD */ +OPCODE(0xD090) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ADDaD */ +OPCODE(0xD098) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ADDaD */ +OPCODE(0xD0A0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ADDaD */ +OPCODE(0xD0A8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(18) +} + +/* ADDaD */ +OPCODE(0xD0B0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(20) +} + +/* ADDaD */ +OPCODE(0xD0B8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(18) +} + +/* ADDaD */ +OPCODE(0xD0B9) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(22) +} + +/* ADDaD */ +OPCODE(0xD0BA) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(18) +} + +/* ADDaD */ +OPCODE(0xD0BB) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(20) +} + +/* ADDaD */ +OPCODE(0xD0BC) +{ + u32 res; + u32 src, dst; + + FETCH_LONG(src); + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ADDaD */ +OPCODE(0xD09F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ADDaD */ +OPCODE(0xD0A7) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, src) + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ADDDa */ +OPCODE(0xD110) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* ADDDa */ +OPCODE(0xD118) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 1; + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* ADDDa */ +OPCODE(0xD120) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* ADDDa */ +OPCODE(0xD128) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ADDDa */ +OPCODE(0xD130) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ADDDa */ +OPCODE(0xD138) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(16) +} + +/* ADDDa */ +OPCODE(0xD139) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(20) +} + +/* ADDDa */ +OPCODE(0xD11F) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 2; + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(12) +} + +/* ADDDa */ +OPCODE(0xD127) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu8((Opcode >> 9) & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = dst + src; + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(14) +} + +/* ADDDa */ +OPCODE(0xD150) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ADDDa */ +OPCODE(0xD158) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ADDDa */ +OPCODE(0xD160) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ADDDa */ +OPCODE(0xD168) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ADDDa */ +OPCODE(0xD170) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ADDDa */ +OPCODE(0xD178) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ADDDa */ +OPCODE(0xD179) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ADDDa */ +OPCODE(0xD15F) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ADDDa */ +OPCODE(0xD167) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu16((Opcode >> 9) & 7); + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, dst) + res = dst + src; + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ADDDa */ +OPCODE(0xD190) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* ADDDa */ +OPCODE(0xD198) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* ADDDa */ +OPCODE(0xD1A0) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* ADDDa */ +OPCODE(0xD1A8) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* ADDDa */ +OPCODE(0xD1B0) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(26) +} + +/* ADDDa */ +OPCODE(0xD1B8) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_SWORD(adr); + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(24) +} + +/* ADDDa */ +OPCODE(0xD1B9) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + FETCH_LONG(adr); + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(28) +} + +/* ADDDa */ +OPCODE(0xD19F) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG(7); + AREG(7) += 4; + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(20) +} + +/* ADDDa */ +OPCODE(0xD1A7) +{ + u32 adr, res; + u32 src, dst; + + src = DREGu32((Opcode >> 9) & 7); + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, dst) + res = dst + src; + flag_NotZ = res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(22) +} + +/* ADDX */ +OPCODE(0xD100) +{ + u32 res; + u32 src, dst; + + src = DREGu8((Opcode >> 0) & 7); + dst = DREGu8((Opcode >> 9) & 7); + res = dst + src + ((flag_X >> 8) & 1); + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ |= res & 0xFF; + DREGu8((Opcode >> 9) & 7) = res; + RET(4) +} + +/* ADDX */ +OPCODE(0xD140) +{ + u32 res; + u32 src, dst; + + src = DREGu16((Opcode >> 0) & 7); + dst = DREGu16((Opcode >> 9) & 7); + res = dst + src + ((flag_X >> 8) & 1); + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + DREGu16((Opcode >> 9) & 7) = res; + RET(4) +} + +/* ADDX */ +OPCODE(0xD180) +{ + u32 res; + u32 src, dst; + + src = DREGu32((Opcode >> 0) & 7); + dst = DREGu32((Opcode >> 9) & 7); + res = dst + src + ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + DREGu32((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDXM */ +OPCODE(0xD108) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + READ_BYTE_F(adr, dst) + res = dst + src + ((flag_X >> 8) & 1); + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ADDXM */ +OPCODE(0xD148) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + READ_WORD_F(adr, dst) + res = dst + src + ((flag_X >> 8) & 1); + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ADDXM */ +OPCODE(0xD188) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + READ_LONG_F(adr, dst) + res = dst + src + ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* ADDX7M */ +OPCODE(0xD10F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 1; + AREG((Opcode >> 9) & 7) = adr; + READ_BYTE_F(adr, dst) + res = dst + src + ((flag_X >> 8) & 1); + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ADDX7M */ +OPCODE(0xD14F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 2; + AREG((Opcode >> 9) & 7) = adr; + READ_WORD_F(adr, dst) + res = dst + src + ((flag_X >> 8) & 1); + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ADDX7M */ +OPCODE(0xD18F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, src) + adr = AREG((Opcode >> 9) & 7) - 4; + AREG((Opcode >> 9) & 7) = adr; + READ_LONG_F(adr, dst) + res = dst + src + ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* ADDXM7 */ +OPCODE(0xDF08) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 1; + AREG((Opcode >> 0) & 7) = adr; + READ_BYTE_F(adr, src) + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = dst + src + ((flag_X >> 8) & 1); + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ADDXM7 */ +OPCODE(0xDF48) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, dst) + res = dst + src + ((flag_X >> 8) & 1); + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ADDXM7 */ +OPCODE(0xDF88) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READ_LONG_F(adr, src) + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, dst) + res = dst + src + ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* ADDX7M7 */ +OPCODE(0xDF0F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, src) + adr = AREG(7) - 2; + AREG(7) = adr; + READ_BYTE_F(adr, dst) + res = dst + src + ((flag_X >> 8) & 1); + flag_N = flag_X = flag_C = res; + flag_V = (src ^ res) & (dst ^ res); + flag_NotZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + RET(18) +} + +/* ADDX7M7 */ +OPCODE(0xDF4F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, dst) + res = dst + src + ((flag_X >> 8) & 1); + flag_V = ((src ^ res) & (dst ^ res)) >> 8; + flag_N = flag_X = flag_C = res >> 8; + flag_NotZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ADDX7M7 */ +OPCODE(0xDF8F) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, src) + adr = AREG(7) - 4; + AREG(7) = adr; + READ_LONG_F(adr, dst) + res = dst + src + ((flag_X >> 8) & 1); + flag_NotZ |= res; + flag_X = flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + flag_V = ((src ^ res) & (dst ^ res)) >> 24; + flag_N = res >> 24; + WRITE_LONG_F(adr, res) + RET(30) +} + +/* ADDA */ +OPCODE(0xD0C0) +{ + u32 res; + u32 src, dst; + + src = (s32)DREGs16((Opcode >> 0) & 7); + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDA */ +OPCODE(0xD0C8) +{ + u32 res; + u32 src, dst; + + src = (s32)AREGs16((Opcode >> 0) & 7); + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDA */ +OPCODE(0xD0D0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ADDA */ +OPCODE(0xD0D8) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ADDA */ +OPCODE(0xD0E0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ADDA */ +OPCODE(0xD0E8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ADDA */ +OPCODE(0xD0F0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(18) +} + +/* ADDA */ +OPCODE(0xD0F8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ADDA */ +OPCODE(0xD0F9) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(20) +} + +/* ADDA */ +OPCODE(0xD0FA) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ADDA */ +OPCODE(0xD0FB) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(18) +} + +/* ADDA */ +OPCODE(0xD0FC) +{ + u32 res; + u32 src, dst; + + FETCH_SWORD(src); + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ADDA */ +OPCODE(0xD0DF) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 2; + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(12) +} + +/* ADDA */ +OPCODE(0xD0E7) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 2; + AREG(7) = adr; + READSX_WORD_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ADDA */ +OPCODE(0xD1C0) +{ + u32 res; + u32 src, dst; + + src = (s32)DREGs32((Opcode >> 0) & 7); + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDA */ +OPCODE(0xD1C8) +{ + u32 res; + u32 src, dst; + + src = (s32)AREGs32((Opcode >> 0) & 7); + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(8) +} + +/* ADDA */ +OPCODE(0xD1D0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ADDA */ +OPCODE(0xD1D8) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 4; + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ADDA */ +OPCODE(0xD1E0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7) - 4; + AREG((Opcode >> 0) & 7) = adr; + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ADDA */ +OPCODE(0xD1E8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(18) +} + +/* ADDA */ +OPCODE(0xD1F0) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(20) +} + +/* ADDA */ +OPCODE(0xD1F8) +{ + u32 adr, res; + u32 src, dst; + + FETCH_SWORD(adr); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(18) +} + +/* ADDA */ +OPCODE(0xD1F9) +{ + u32 adr, res; + u32 src, dst; + + FETCH_LONG(adr); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(22) +} + +/* ADDA */ +OPCODE(0xD1FA) +{ + u32 adr, res; + u32 src, dst; + + adr = GET_SWORD + UNBASED_PC; + INC_PC(2); + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(18) +} + +/* ADDA */ +OPCODE(0xD1FB) +{ + u32 adr, res; + u32 src, dst; + + adr = UNBASED_PC; + DECODE_EXT_WORD + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(20) +} + +/* ADDA */ +OPCODE(0xD1FC) +{ + u32 res; + u32 src, dst; + + FETCH_LONG(src); + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ADDA */ +OPCODE(0xD1DF) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7); + AREG(7) += 4; + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(14) +} + +/* ADDA */ +OPCODE(0xD1E7) +{ + u32 adr, res; + u32 src, dst; + + adr = AREG(7) - 4; + AREG(7) = adr; + READSX_LONG_F(adr, src) + dst = AREGu32((Opcode >> 9) & 7); + res = dst + src; + AREG((Opcode >> 9) & 7) = res; + RET(16) +} + +/* ASRk */ +OPCODE(0xE000) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = (s32)DREGs8((Opcode >> 0) & 7); + flag_V = 0; + flag_X = flag_C = src << ((M68K_SR_C_SFT + 1) - sft); + res = ((s32)src) >> sft; + flag_N = res >> 0; + flag_NotZ = res; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) +} + +/* ASRk */ +OPCODE(0xE040) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = (s32)DREGs16((Opcode >> 0) & 7); + flag_V = 0; + flag_X = flag_C = src << ((M68K_SR_C_SFT + 1) - sft); + res = ((s32)src) >> sft; + flag_N = res >> 8; + flag_NotZ = res; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) +} + +/* ASRk */ +OPCODE(0xE080) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = (s32)DREGs32((Opcode >> 0) & 7); + flag_V = 0; + flag_X = flag_C = src << ((M68K_SR_C_SFT + 1) - sft); + res = ((s32)src) >> sft; + flag_N = res >> 24; + flag_NotZ = res; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) +} + +/* LSRk */ +OPCODE(0xE008) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu8((Opcode >> 0) & 7); + flag_N = flag_V = 0; + flag_X = flag_C = src << ((M68K_SR_C_SFT + 1) - sft); + res = src >> sft; + flag_NotZ = res; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) +} + +/* LSRk */ +OPCODE(0xE048) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu16((Opcode >> 0) & 7); + flag_N = flag_V = 0; + flag_X = flag_C = src << ((M68K_SR_C_SFT + 1) - sft); + res = src >> sft; + flag_NotZ = res; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) +} + +/* LSRk */ +OPCODE(0xE088) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu32((Opcode >> 0) & 7); + flag_N = flag_V = 0; + flag_X = flag_C = src << ((M68K_SR_C_SFT + 1) - sft); + res = src >> sft; + flag_NotZ = res; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) +} + +/* ROXRk */ +OPCODE(0xE010) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu8((Opcode >> 0) & 7); + src |= (flag_X & M68K_SR_X) << 0; + res = (src >> sft) | (src << (9 - sft)); + flag_X = flag_C = res >> 0; + flag_V = 0; + flag_N = res >> 0; + flag_NotZ = res & 0x000000FF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) +} + +/* ROXRk */ +OPCODE(0xE050) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu16((Opcode >> 0) & 7); + src |= (flag_X & M68K_SR_X) << 8; + res = (src >> sft) | (src << (17 - sft)); + flag_X = flag_C = res >> 8; + flag_V = 0; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) +} + +/* ROXRk */ +OPCODE(0xE090) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu32((Opcode >> 0) & 7); + flag_C = src << ((M68K_SR_C_SFT + 1) - sft); + if (sft == 1) res = (src >> 1) | ((flag_X & M68K_SR_X) << (32 - (M68K_SR_X_SFT + 1))); + else res = (src >> sft) | (src << (33 - sft)) | ((flag_X & M68K_SR_X) << (32 - (M68K_SR_X_SFT + sft))); + flag_X = flag_C; + flag_V = 0; + flag_N = res >> 24; + flag_NotZ = res; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) +} + +/* RORk */ +OPCODE(0xE018) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu8((Opcode >> 0) & 7); + flag_V = 0; + flag_C = src << ((M68K_SR_C_SFT + 1) - sft); + res = (src >> sft) | (src << (8 - sft)); + flag_N = res >> 0; + flag_NotZ = res & 0x000000FF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) +} + +/* RORk */ +OPCODE(0xE058) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu16((Opcode >> 0) & 7); + flag_V = 0; + flag_C = src << ((M68K_SR_C_SFT + 1) - sft); + res = (src >> sft) | (src << (16 - sft)); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) +} + +/* RORk */ +OPCODE(0xE098) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu32((Opcode >> 0) & 7); + flag_V = 0; + flag_C = src << ((M68K_SR_C_SFT + 1) - sft); + res = (src >> sft) | (src << (32 - sft)); + flag_N = res >> 24; + flag_NotZ = res; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) +} + +/* ASLk */ +OPCODE(0xE100) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu8((Opcode >> 0) & 7); + if (sft < 8) + { + flag_X = flag_C = src << (0 + sft); + res = src << sft; + flag_N = res >> 0; + flag_NotZ = res & 0x000000FF; + DREGu8((Opcode >> 0) & 7) = res; + flag_V = 0; + if ((sft > 7) && (src)) flag_V = M68K_SR_V; + else + { + u32 msk = (((s32)0x80000000) >> (sft + 24)) & 0x000000FF; + src &= msk; + if ((src) && (src != msk)) flag_V = M68K_SR_V; + } + RET(6) + } + + if (src) flag_V = M68K_SR_V; + else flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + flag_N = 0; + flag_NotZ = 0; + RET(6) +} + +/* ASLk */ +OPCODE(0xE140) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu16((Opcode >> 0) & 7); + flag_X = flag_C = src >> (8 - sft); + res = src << sft; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + DREGu16((Opcode >> 0) & 7) = res; + flag_V = 0; + { + u32 msk = (((s32)0x80000000) >> (sft + 16)) & 0x0000FFFF; + src &= msk; + if ((src) && (src != msk)) flag_V = M68K_SR_V; + } + RET(6) +} + +/* ASLk */ +OPCODE(0xE180) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu32((Opcode >> 0) & 7); + flag_X = flag_C = src >> (24 - sft); + res = src << sft; + flag_N = res >> 24; + flag_NotZ = res & 0xFFFFFFFF; + DREGu32((Opcode >> 0) & 7) = res; + flag_V = 0; + { + u32 msk = (((s32)0x80000000) >> (sft + 0)) & 0xFFFFFFFF; + src &= msk; + if ((src) && (src != msk)) flag_V = M68K_SR_V; + } + RET(8) +} + +/* LSLk */ +OPCODE(0xE108) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu8((Opcode >> 0) & 7); + flag_V = 0; + flag_X = flag_C = src << (0 + sft); + res = src << sft; + flag_N = res >> 0; + flag_NotZ = res & 0x000000FF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) +} + +/* LSLk */ +OPCODE(0xE148) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu16((Opcode >> 0) & 7); + flag_V = 0; + flag_X = flag_C = src >> (8 - sft); + res = src << sft; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) +} + +/* LSLk */ +OPCODE(0xE188) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu32((Opcode >> 0) & 7); + flag_V = 0; + flag_X = flag_C = src >> (24 - sft); + res = src << sft; + flag_N = res >> 24; + flag_NotZ = res & 0xFFFFFFFF; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) +} + +/* ROXLk */ +OPCODE(0xE110) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu8((Opcode >> 0) & 7); + src |= (flag_X & M68K_SR_X) << 0; + res = (src << sft) | (src >> (9 - sft)); + flag_X = flag_C = res >> 0; + flag_V = 0; + flag_N = res >> 0; + flag_NotZ = res & 0x000000FF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) +} + +/* ROXLk */ +OPCODE(0xE150) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu16((Opcode >> 0) & 7); + src |= (flag_X & M68K_SR_X) << 8; + res = (src << sft) | (src >> (17 - sft)); + flag_X = flag_C = res >> 8; + flag_V = 0; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) +} + +/* ROXLk */ +OPCODE(0xE190) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu32((Opcode >> 0) & 7); + flag_C = src >> ((32 - M68K_SR_C_SFT) - sft); + if (sft == 1) res = (src << 1) | ((flag_X & M68K_SR_X) >> ((M68K_SR_X_SFT + 1) - 1)); + else res = (src << sft) | (src >> (33 - sft)) | ((flag_X & M68K_SR_X) >> ((M68K_SR_X_SFT + 1) - sft)); + flag_X = flag_C; + flag_V = 0; + flag_N = res >> 24; + flag_NotZ = res; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) +} + +/* ROLk */ +OPCODE(0xE118) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu8((Opcode >> 0) & 7); + flag_V = 0; + flag_C = src << (0 + sft); + res = (src << sft) | (src >> (8 - sft)); + flag_N = res >> 0; + flag_NotZ = res & 0x000000FF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) +} + +/* ROLk */ +OPCODE(0xE158) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu16((Opcode >> 0) & 7); + flag_V = 0; + flag_C = src >> (8 - sft); + res = (src << sft) | (src >> (16 - sft)); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) +} + +/* ROLk */ +OPCODE(0xE198) +{ + u32 res; + u32 src; + + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + io_cycle_counter -= sft * 2; + src = DREGu32((Opcode >> 0) & 7); + flag_V = 0; + flag_C = src >> (24 - sft); + res = (src << sft) | (src >> (32 - sft)); + flag_N = res >> 24; + flag_NotZ = res; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) +} + +/* ASRD */ +OPCODE(0xE020) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = (s32)DREGs8((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft < 8) + { + flag_V = 0; + flag_X = flag_C = src << ((M68K_SR_C_SFT + 1) - sft); + res = ((s32)src) >> sft; + flag_N = res >> 0; + flag_NotZ = res; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + + if (src & (1 << 7)) + { + flag_N = M68K_SR_N; + flag_NotZ = 1; + flag_V = 0; + flag_C = M68K_SR_C; + flag_X = M68K_SR_X; + res = 0x000000FF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_N = 0; + flag_NotZ = 0; + flag_V = 0; + flag_C = 0; + flag_X = 0; + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 0; + flag_NotZ = src; + RET(6) +} + +/* ASRD */ +OPCODE(0xE060) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = (s32)DREGs16((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft < 16) + { + flag_V = 0; + flag_X = flag_C = (src >> (sft - 1)) << M68K_SR_C_SFT; + res = ((s32)src) >> sft; + flag_N = res >> 8; + flag_NotZ = res; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) + } + + if (src & (1 << 15)) + { + flag_N = M68K_SR_N; + flag_NotZ = 1; + flag_V = 0; + flag_C = M68K_SR_C; + flag_X = M68K_SR_X; + res = 0x0000FFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_N = 0; + flag_NotZ = 0; + flag_V = 0; + flag_C = 0; + flag_X = 0; + res = 0; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 8; + flag_NotZ = src; + RET(6) +} + +/* ASRD */ +OPCODE(0xE0A0) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = (s32)DREGs32((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft < 32) + { + flag_V = 0; + flag_X = flag_C = (src >> (sft - 1)) << M68K_SR_C_SFT; + res = ((s32)src) >> sft; + flag_N = res >> 24; + flag_NotZ = res; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) + } + + if (src & (1 << 31)) + { + flag_N = M68K_SR_N; + flag_NotZ = 1; + flag_V = 0; + flag_C = M68K_SR_C; + flag_X = M68K_SR_X; + res = 0xFFFFFFFF; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) + } + + flag_N = 0; + flag_NotZ = 0; + flag_V = 0; + flag_C = 0; + flag_X = 0; + res = 0; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 24; + flag_NotZ = src; + RET(8) +} + +/* LSRD */ +OPCODE(0xE028) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu8((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft <= 8) + { + flag_N = flag_V = 0; + flag_X = flag_C = src << ((M68K_SR_C_SFT + 1) - sft); + res = src >> sft; + flag_NotZ = res; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_X = flag_C = 0; + flag_N = 0; + flag_NotZ = 0; + flag_V = 0; + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 0; + flag_NotZ = src; + RET(6) +} + +/* LSRD */ +OPCODE(0xE068) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu16((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft <= 16) + { + flag_N = flag_V = 0; + flag_X = flag_C = (src >> (sft - 1)) << M68K_SR_C_SFT; + res = src >> sft; + flag_NotZ = res; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_X = flag_C = 0; + flag_N = 0; + flag_NotZ = 0; + flag_V = 0; + res = 0; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 8; + flag_NotZ = src; + RET(6) +} + +/* LSRD */ +OPCODE(0xE0A8) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu32((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft < 32) + { + flag_N = flag_V = 0; + flag_X = flag_C = (src >> (sft - 1)) << M68K_SR_C_SFT; + res = src >> sft; + flag_NotZ = res; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) + } + + if (sft == 32) flag_C = src >> (31 - M68K_SR_C_SFT); + else flag_C = 0; + flag_X = flag_C; + flag_N = 0; + flag_NotZ = 0; + flag_V = 0; + res = 0; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 24; + flag_NotZ = src; + RET(8) +} + +/* ROXRD */ +OPCODE(0xE030) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu8((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + sft %= 9; + + src |= (flag_X & M68K_SR_X) << 0; + res = (src >> sft) | (src << (9 - sft)); + flag_X = flag_C = res >> 0; + flag_V = 0; + flag_N = res >> 0; + flag_NotZ = res & 0x000000FF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_V = 0; + flag_C = flag_X; + flag_N = src >> 0; + flag_NotZ = src; + RET(6) +} + +/* ROXRD */ +OPCODE(0xE070) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu16((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + sft %= 17; + + src |= (flag_X & M68K_SR_X) << 8; + res = (src >> sft) | (src << (17 - sft)); + flag_X = flag_C = res >> 8; + flag_V = 0; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_V = 0; + flag_C = flag_X; + flag_N = src >> 8; + flag_NotZ = src; + RET(6) +} + +/* ROXRD */ +OPCODE(0xE0B0) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu32((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + sft %= 33; + + if (sft != 0) + { + if (sft == 1) + res = (src >> 1) | ((flag_X & M68K_SR_X) << (32 - (M68K_SR_X_SFT + 1))); + else + res = (src >> sft) | (src << (33 - sft)) | (((flag_X & M68K_SR_X) << (32 - (M68K_SR_X_SFT + 1))) >> (sft - 1)); + + flag_X = ((src >> (sft - 1)) & 1) << M68K_SR_X_SFT; + } + else res = src; + flag_C = flag_X; + flag_V = 0; + flag_N = res >> 24; + flag_NotZ = res; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) + } + + flag_V = 0; + flag_C = flag_X; + flag_N = src >> 24; + flag_NotZ = src; + RET(8) +} + +/* RORD */ +OPCODE(0xE038) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu8((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + sft &= 0x07; + + flag_C = src << (M68K_SR_C_SFT - ((sft - 1) & 7)); + res = (src >> sft) | (src << (8 - sft)); + flag_V = 0; + flag_N = res >> 0; + flag_NotZ = res & 0x000000FF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 0; + flag_NotZ = src; + RET(6) +} + +/* RORD */ +OPCODE(0xE078) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu16((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + sft &= 0x0F; + + flag_C = (src >> ((sft - 1) & 15)) << M68K_SR_C_SFT; + res = (src >> sft) | (src << (16 - sft)); + flag_V = 0; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 8; + flag_NotZ = src; + RET(6) +} + +/* RORD */ +OPCODE(0xE0B8) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu32((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + sft &= 0x1F; + + flag_C = (src >> ((sft - 1) & 31)) << M68K_SR_C_SFT; + res = (src >> sft) | (src << (32 - sft)); + flag_V = 0; + flag_N = res >> 24; + flag_NotZ = res; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 24; + flag_NotZ = src; + RET(8) +} + +/* ASLD */ +OPCODE(0xE120) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu8((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft < 8) + { + flag_X = flag_C = (src << sft) >> 0; + res = (src << sft) & 0x000000FF; + flag_N = res >> 0; + flag_NotZ = res; + DREGu8((Opcode >> 0) & 7) = res; + flag_V = 0; + { + u32 msk = (((s32)0x80000000) >> (sft + 24)) & 0x000000FF; + src &= msk; + if ((src) && (src != msk)) flag_V = M68K_SR_V; + } + RET(6) + } + + if (sft == 256) flag_C = src << M68K_SR_C_SFT; + else flag_C = 0; + flag_X = flag_C; + if (src) flag_V = M68K_SR_V; + else flag_V = 0; + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + flag_N = 0; + flag_NotZ = 0; + RET(6) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 0; + flag_NotZ = src; + RET(6) +} + +/* ASLD */ +OPCODE(0xE160) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu16((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft < 16) + { + flag_X = flag_C = (src << sft) >> 8; + res = (src << sft) & 0x0000FFFF; + flag_N = res >> 8; + flag_NotZ = res; + DREGu16((Opcode >> 0) & 7) = res; + flag_V = 0; + { + u32 msk = (((s32)0x80000000) >> (sft + 16)) & 0x0000FFFF; + src &= msk; + if ((src) && (src != msk)) flag_V = M68K_SR_V; + } + RET(6) + } + + if (sft == 65536) flag_C = src << M68K_SR_C_SFT; + else flag_C = 0; + flag_X = flag_C; + if (src) flag_V = M68K_SR_V; + else flag_V = 0; + res = 0; + DREGu16((Opcode >> 0) & 7) = res; + flag_N = 0; + flag_NotZ = 0; + RET(6) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 8; + flag_NotZ = src; + RET(6) +} + +/* ASLD */ +OPCODE(0xE1A0) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu32((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft < 32) + { + flag_X = flag_C = (src >> (32 - sft)) << M68K_SR_C_SFT; + res = src << sft; + flag_N = res >> 24; + flag_NotZ = res; + DREGu32((Opcode >> 0) & 7) = res; + flag_V = 0; + { + u32 msk = (((s32)0x80000000) >> (sft + 0)) & 0xFFFFFFFF; + src &= msk; + if ((src) && (src != msk)) flag_V = M68K_SR_V; + } + RET(8) + } + + if (sft == 0) flag_C = src << M68K_SR_C_SFT; + else flag_C = 0; + flag_X = flag_C; + if (src) flag_V = M68K_SR_V; + else flag_V = 0; + res = 0; + DREGu32((Opcode >> 0) & 7) = res; + flag_N = 0; + flag_NotZ = 0; + RET(8) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 24; + flag_NotZ = src; + RET(8) +} + +/* LSLD */ +OPCODE(0xE128) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu8((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft <= 8) + { + flag_X = flag_C = (src << sft) >> 0; + res = (src << sft) & 0x000000FF; + flag_V = 0; + flag_N = res >> 0; + flag_NotZ = res; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_X = flag_C = 0; + flag_N = 0; + flag_NotZ = 0; + flag_V = 0; + res = 0; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 0; + flag_NotZ = src; + RET(6) +} + +/* LSLD */ +OPCODE(0xE168) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu16((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft <= 16) + { + flag_X = flag_C = (src << sft) >> 8; + res = (src << sft) & 0x0000FFFF; + flag_V = 0; + flag_N = res >> 8; + flag_NotZ = res; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_X = flag_C = 0; + flag_N = 0; + flag_NotZ = 0; + flag_V = 0; + res = 0; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 8; + flag_NotZ = src; + RET(6) +} + +/* LSLD */ +OPCODE(0xE1A8) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu32((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft < 32) + { + flag_X = flag_C = (src >> (32 - sft)) << M68K_SR_C_SFT; + res = src << sft; + flag_V = 0; + flag_N = res >> 24; + flag_NotZ = res; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) + } + + if (sft == 32) flag_C = src << M68K_SR_C_SFT; + else flag_C = 0; + flag_X = flag_C; + flag_N = 0; + flag_NotZ = 0; + flag_V = 0; + res = 0; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 24; + flag_NotZ = src; + RET(8) +} + +/* ROXLD */ +OPCODE(0xE130) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu8((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + sft %= 9; + + src |= (flag_X & M68K_SR_X) << 0; + res = (src << sft) | (src >> (9 - sft)); + flag_X = flag_C = res >> 0; + flag_V = 0; + flag_N = res >> 0; + flag_NotZ = res & 0x000000FF; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_V = 0; + flag_C = flag_X; + flag_N = src >> 0; + flag_NotZ = src; + RET(6) +} + +/* ROXLD */ +OPCODE(0xE170) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu16((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + sft %= 17; + + src |= (flag_X & M68K_SR_X) << 8; + res = (src << sft) | (src >> (17 - sft)); + flag_X = flag_C = res >> 8; + flag_V = 0; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_V = 0; + flag_C = flag_X; + flag_N = src >> 8; + flag_NotZ = src; + RET(6) +} + +/* ROXLD */ +OPCODE(0xE1B0) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu32((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + sft %= 33; + + if (sft != 0) + { + if (sft == 1) res = (src << 1) | ((flag_X >> ((M68K_SR_X_SFT + 1) - 1)) & 1); + else res = (src << sft) | (src >> (33 - sft)) | (((flag_X >> ((M68K_SR_X_SFT + 1) - 1)) & 1) << (sft - 1)); + flag_X = (src >> (32 - sft)) << M68K_SR_X_SFT; + } + else res = src; + flag_C = flag_X; + flag_V = 0; + flag_N = res >> 24; + flag_NotZ = res; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) + } + + flag_V = 0; + flag_C = flag_X; + flag_N = src >> 24; + flag_NotZ = src; + RET(8) +} + +/* ROLD */ +OPCODE(0xE138) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu8((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft &= 0x07) + { + flag_C = (src << sft) >> 0; + res = ((src << sft) | (src >> (8 - sft))) & 0x000000FF; + flag_V = 0; + flag_N = res >> 0; + flag_NotZ = res; + DREGu8((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_V = 0; + flag_C = src << M68K_SR_C_SFT; + flag_N = src >> 0; + flag_NotZ = src; + RET(6) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 0; + flag_NotZ = src; + RET(6) +} + +/* ROLD */ +OPCODE(0xE178) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu16((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft &= 0x0F) + { + flag_C = (src << sft) >> 8; + res = ((src << sft) | (src >> (16 - sft))) & 0x0000FFFF; + flag_V = 0; + flag_N = res >> 8; + flag_NotZ = res; + DREGu16((Opcode >> 0) & 7) = res; + RET(6) + } + + flag_V = 0; + flag_C = src << M68K_SR_C_SFT; + flag_N = src >> 8; + flag_NotZ = src; + RET(6) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 8; + flag_NotZ = src; + RET(6) +} + +/* ROLD */ +OPCODE(0xE1B8) +{ + u32 res; + u32 src; + + u32 sft; + + sft = DREG((Opcode >> 9) & 7) & 0x3F; + src = DREGu32((Opcode >> 0) & 7); + if (sft) + { + io_cycle_counter -= sft * 2; + if (sft &= 0x1F) + { + flag_C = (src >> (32 - sft)) << M68K_SR_C_SFT; + res = (src << sft) | (src >> (32 - sft)); + flag_V = 0; + flag_N = res >> 24; + flag_NotZ = res; + DREGu32((Opcode >> 0) & 7) = res; + RET(8) + } + + flag_V = 0; + flag_C = src << M68K_SR_C_SFT; + flag_N = src >> 24; + flag_NotZ = src; + RET(8) + } + + flag_V = 0; + flag_C = 0; + flag_N = src >> 24; + flag_NotZ = src; + RET(8) +} + +/* ASR */ +OPCODE(0xE0D0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ASR */ +OPCODE(0xE0D8) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ASR */ +OPCODE(0xE0E0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ASR */ +OPCODE(0xE0E8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ASR */ +OPCODE(0xE0F0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ASR */ +OPCODE(0xE0F8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ASR */ +OPCODE(0xE0F9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ASR */ +OPCODE(0xE0DF) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ASR */ +OPCODE(0xE0E7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* LSR */ +OPCODE(0xE2D0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_N = flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = src >> 1; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* LSR */ +OPCODE(0xE2D8) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + flag_N = flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = src >> 1; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* LSR */ +OPCODE(0xE2E0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + flag_N = flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = src >> 1; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* LSR */ +OPCODE(0xE2E8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_N = flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = src >> 1; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* LSR */ +OPCODE(0xE2F0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + flag_N = flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = src >> 1; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* LSR */ +OPCODE(0xE2F8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + flag_N = flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = src >> 1; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* LSR */ +OPCODE(0xE2F9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + flag_N = flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = src >> 1; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* LSR */ +OPCODE(0xE2DF) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + flag_N = flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = src >> 1; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* LSR */ +OPCODE(0xE2E7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + flag_N = flag_V = 0; + flag_X = flag_C = src << M68K_SR_C_SFT; + res = src >> 1; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ROXR */ +OPCODE(0xE4D0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_V = 0; + res = (src >> 1) | ((flag_X & M68K_SR_X) << 7); + flag_C = flag_X = src << M68K_SR_C_SFT; + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ROXR */ +OPCODE(0xE4D8) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + flag_V = 0; + res = (src >> 1) | ((flag_X & M68K_SR_X) << 7); + flag_C = flag_X = src << M68K_SR_C_SFT; + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ROXR */ +OPCODE(0xE4E0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + flag_V = 0; + res = (src >> 1) | ((flag_X & M68K_SR_X) << 7); + flag_C = flag_X = src << M68K_SR_C_SFT; + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ROXR */ +OPCODE(0xE4E8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_V = 0; + res = (src >> 1) | ((flag_X & M68K_SR_X) << 7); + flag_C = flag_X = src << M68K_SR_C_SFT; + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ROXR */ +OPCODE(0xE4F0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + flag_V = 0; + res = (src >> 1) | ((flag_X & M68K_SR_X) << 7); + flag_C = flag_X = src << M68K_SR_C_SFT; + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ROXR */ +OPCODE(0xE4F8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + flag_V = 0; + res = (src >> 1) | ((flag_X & M68K_SR_X) << 7); + flag_C = flag_X = src << M68K_SR_C_SFT; + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ROXR */ +OPCODE(0xE4F9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + flag_V = 0; + res = (src >> 1) | ((flag_X & M68K_SR_X) << 7); + flag_C = flag_X = src << M68K_SR_C_SFT; + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ROXR */ +OPCODE(0xE4DF) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + flag_V = 0; + res = (src >> 1) | ((flag_X & M68K_SR_X) << 7); + flag_C = flag_X = src << M68K_SR_C_SFT; + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ROXR */ +OPCODE(0xE4E7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + flag_V = 0; + res = (src >> 1) | ((flag_X & M68K_SR_X) << 7); + flag_C = flag_X = src << M68K_SR_C_SFT; + flag_N = res >> 8; + flag_NotZ = res; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ROR */ +OPCODE(0xE6D0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ROR */ +OPCODE(0xE6D8) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ROR */ +OPCODE(0xE6E0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ROR */ +OPCODE(0xE6E8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ROR */ +OPCODE(0xE6F0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ROR */ +OPCODE(0xE6F8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ROR */ +OPCODE(0xE6F9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ROR */ +OPCODE(0xE6DF) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ROR */ +OPCODE(0xE6E7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src << M68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ASL */ +OPCODE(0xE1D0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_X = flag_C = src >> 7; + res = src << 1; + flag_V = (src ^ res) >> 8; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ASL */ +OPCODE(0xE1D8) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + flag_X = flag_C = src >> 7; + res = src << 1; + flag_V = (src ^ res) >> 8; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ASL */ +OPCODE(0xE1E0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + flag_X = flag_C = src >> 7; + res = src << 1; + flag_V = (src ^ res) >> 8; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ASL */ +OPCODE(0xE1E8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_X = flag_C = src >> 7; + res = src << 1; + flag_V = (src ^ res) >> 8; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ASL */ +OPCODE(0xE1F0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + flag_X = flag_C = src >> 7; + res = src << 1; + flag_V = (src ^ res) >> 8; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ASL */ +OPCODE(0xE1F8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + flag_X = flag_C = src >> 7; + res = src << 1; + flag_V = (src ^ res) >> 8; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ASL */ +OPCODE(0xE1F9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + flag_X = flag_C = src >> 7; + res = src << 1; + flag_V = (src ^ res) >> 8; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ASL */ +OPCODE(0xE1DF) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + flag_X = flag_C = src >> 7; + res = src << 1; + flag_V = (src ^ res) >> 8; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ASL */ +OPCODE(0xE1E7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + flag_X = flag_C = src >> 7; + res = src << 1; + flag_V = (src ^ res) >> 8; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* LSL */ +OPCODE(0xE3D0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src >> 7; + res = src << 1; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* LSL */ +OPCODE(0xE3D8) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src >> 7; + res = src << 1; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* LSL */ +OPCODE(0xE3E0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src >> 7; + res = src << 1; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* LSL */ +OPCODE(0xE3E8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src >> 7; + res = src << 1; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* LSL */ +OPCODE(0xE3F0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src >> 7; + res = src << 1; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* LSL */ +OPCODE(0xE3F8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src >> 7; + res = src << 1; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* LSL */ +OPCODE(0xE3F9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src >> 7; + res = src << 1; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* LSL */ +OPCODE(0xE3DF) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src >> 7; + res = src << 1; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* LSL */ +OPCODE(0xE3E7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + flag_V = 0; + flag_X = flag_C = src >> 7; + res = src << 1; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ROXL */ +OPCODE(0xE5D0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_V = 0; + res = (src << 1) | ((flag_X & M68K_SR_X) >> 8); + flag_X = flag_C = src >> 7; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ROXL */ +OPCODE(0xE5D8) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + flag_V = 0; + res = (src << 1) | ((flag_X & M68K_SR_X) >> 8); + flag_X = flag_C = src >> 7; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ROXL */ +OPCODE(0xE5E0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + flag_V = 0; + res = (src << 1) | ((flag_X & M68K_SR_X) >> 8); + flag_X = flag_C = src >> 7; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ROXL */ +OPCODE(0xE5E8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_V = 0; + res = (src << 1) | ((flag_X & M68K_SR_X) >> 8); + flag_X = flag_C = src >> 7; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ROXL */ +OPCODE(0xE5F0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + flag_V = 0; + res = (src << 1) | ((flag_X & M68K_SR_X) >> 8); + flag_X = flag_C = src >> 7; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ROXL */ +OPCODE(0xE5F8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + flag_V = 0; + res = (src << 1) | ((flag_X & M68K_SR_X) >> 8); + flag_X = flag_C = src >> 7; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ROXL */ +OPCODE(0xE5F9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + flag_V = 0; + res = (src << 1) | ((flag_X & M68K_SR_X) >> 8); + flag_X = flag_C = src >> 7; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ROXL */ +OPCODE(0xE5DF) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + flag_V = 0; + res = (src << 1) | ((flag_X & M68K_SR_X) >> 8); + flag_X = flag_C = src >> 7; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ROXL */ +OPCODE(0xE5E7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + flag_V = 0; + res = (src << 1) | ((flag_X & M68K_SR_X) >> 8); + flag_X = flag_C = src >> 7; + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ROL */ +OPCODE(0xE7D0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src >> 7; + res = (src << 1) | (src >> 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ROL */ +OPCODE(0xE7D8) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + AREG((Opcode >> 0) & 7) += 2; + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src >> 7; + res = (src << 1) | (src >> 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ROL */ +OPCODE(0xE7E0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7) - 2; + AREG((Opcode >> 0) & 7) = adr; + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src >> 7; + res = (src << 1) | (src >> 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(14) +} + +/* ROL */ +OPCODE(0xE7E8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + adr += AREG((Opcode >> 0) & 7); + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src >> 7; + res = (src << 1) | (src >> 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ROL */ +OPCODE(0xE7F0) +{ + u32 adr, res; + u32 src; + + adr = AREG((Opcode >> 0) & 7); + DECODE_EXT_WORD + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src >> 7; + res = (src << 1) | (src >> 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(18) +} + +/* ROL */ +OPCODE(0xE7F8) +{ + u32 adr, res; + u32 src; + + FETCH_SWORD(adr); + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src >> 7; + res = (src << 1) | (src >> 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(16) +} + +/* ROL */ +OPCODE(0xE7F9) +{ + u32 adr, res; + u32 src; + + FETCH_LONG(adr); + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src >> 7; + res = (src << 1) | (src >> 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(20) +} + +/* ROL */ +OPCODE(0xE7DF) +{ + u32 adr, res; + u32 src; + + adr = AREG(7); + AREG(7) += 2; + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src >> 7; + res = (src << 1) | (src >> 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(12) +} + +/* ROL */ +OPCODE(0xE7E7) +{ + u32 adr, res; + u32 src; + + adr = AREG(7) - 2; + AREG(7) = adr; + READ_WORD_F(adr, src) + flag_V = 0; + flag_C = src >> 7; + res = (src << 1) | (src >> 15); + flag_N = res >> 8; + flag_NotZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + RET(14) +} diff --git a/MCUME_esp32/espcastaway/main/68kfame/jumptable.h b/MCUME_esp32/espcastaway/main/68kfame/jumptable.h new file mode 100644 index 0000000..fb04515 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68kfame/jumptable.h @@ -0,0 +1,4098 @@ +static const opcode_func JumpTable[0x10000] = { +CAST_OP(0x0000),CAST_OP(0x0000),CAST_OP(0x0000),CAST_OP(0x0000),CAST_OP(0x0000),CAST_OP(0x0000),CAST_OP(0x0000),CAST_OP(0x0000),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x0010),CAST_OP(0x0010),CAST_OP(0x0010),CAST_OP(0x0010),CAST_OP(0x0010),CAST_OP(0x0010),CAST_OP(0x0010),CAST_OP(0x0010),CAST_OP(0x0018),CAST_OP(0x0018),CAST_OP(0x0018),CAST_OP(0x0018),CAST_OP(0x0018),CAST_OP(0x0018),CAST_OP(0x0018),CAST_OP(0x001F), +CAST_OP(0x0020),CAST_OP(0x0020),CAST_OP(0x0020),CAST_OP(0x0020),CAST_OP(0x0020),CAST_OP(0x0020),CAST_OP(0x0020),CAST_OP(0x0027),CAST_OP(0x0028),CAST_OP(0x0028),CAST_OP(0x0028),CAST_OP(0x0028),CAST_OP(0x0028),CAST_OP(0x0028),CAST_OP(0x0028),CAST_OP(0x0028), +CAST_OP(0x0030),CAST_OP(0x0030),CAST_OP(0x0030),CAST_OP(0x0030),CAST_OP(0x0030),CAST_OP(0x0030),CAST_OP(0x0030),CAST_OP(0x0030),CAST_OP(0x0038),CAST_OP(0x0039),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x003C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x0040),CAST_OP(0x0040),CAST_OP(0x0040),CAST_OP(0x0040),CAST_OP(0x0040),CAST_OP(0x0040),CAST_OP(0x0040),CAST_OP(0x0040),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x0050),CAST_OP(0x0050),CAST_OP(0x0050),CAST_OP(0x0050),CAST_OP(0x0050),CAST_OP(0x0050),CAST_OP(0x0050),CAST_OP(0x0050),CAST_OP(0x0058),CAST_OP(0x0058),CAST_OP(0x0058),CAST_OP(0x0058),CAST_OP(0x0058),CAST_OP(0x0058),CAST_OP(0x0058),CAST_OP(0x005F), +CAST_OP(0x0060),CAST_OP(0x0060),CAST_OP(0x0060),CAST_OP(0x0060),CAST_OP(0x0060),CAST_OP(0x0060),CAST_OP(0x0060),CAST_OP(0x0067),CAST_OP(0x0068),CAST_OP(0x0068),CAST_OP(0x0068),CAST_OP(0x0068),CAST_OP(0x0068),CAST_OP(0x0068),CAST_OP(0x0068),CAST_OP(0x0068), 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+CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000),CAST_OP(0xA000), +CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008), +CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB01F), +CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB027),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028), +CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB038),CAST_OP(0xB039),CAST_OP(0xB03A),CAST_OP(0xB03B),CAST_OP(0xB03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048), +CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB05F), +CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB067),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068), +CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB078),CAST_OP(0xB079),CAST_OP(0xB07A),CAST_OP(0xB07B),CAST_OP(0xB07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088), +CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB09F), +CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A7),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8), +CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B8),CAST_OP(0xB0B9),CAST_OP(0xB0BA),CAST_OP(0xB0BB),CAST_OP(0xB0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8), +CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0DF), +CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E7),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8), +CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F8),CAST_OP(0xB0F9),CAST_OP(0xB0FA),CAST_OP(0xB0FB),CAST_OP(0xB0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB10F), +CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB11F), +CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB127),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128), +CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB138),CAST_OP(0xB139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB14F), +CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB15F), +CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB167),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168), +CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB178),CAST_OP(0xB179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB18F), +CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB19F), +CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A7),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8), +CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B8),CAST_OP(0xB1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8), +CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1DF), +CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E7),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8), +CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F8),CAST_OP(0xB1F9),CAST_OP(0xB1FA),CAST_OP(0xB1FB),CAST_OP(0xB1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008), +CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB01F), +CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB027),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028), +CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB038),CAST_OP(0xB039),CAST_OP(0xB03A),CAST_OP(0xB03B),CAST_OP(0xB03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048), +CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB05F), +CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB067),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068), +CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB078),CAST_OP(0xB079),CAST_OP(0xB07A),CAST_OP(0xB07B),CAST_OP(0xB07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088), +CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB09F), +CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A7),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8), +CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B8),CAST_OP(0xB0B9),CAST_OP(0xB0BA),CAST_OP(0xB0BB),CAST_OP(0xB0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8), +CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0DF), +CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E7),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8), +CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F8),CAST_OP(0xB0F9),CAST_OP(0xB0FA),CAST_OP(0xB0FB),CAST_OP(0xB0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB10F), +CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB11F), +CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB127),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128), +CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB138),CAST_OP(0xB139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB14F), +CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB15F), +CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB167),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168), +CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB178),CAST_OP(0xB179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB18F), +CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB19F), +CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A7),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8), +CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B8),CAST_OP(0xB1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8), +CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1DF), +CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E7),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8), +CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F8),CAST_OP(0xB1F9),CAST_OP(0xB1FA),CAST_OP(0xB1FB),CAST_OP(0xB1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008), +CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB01F), +CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB027),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028), +CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB038),CAST_OP(0xB039),CAST_OP(0xB03A),CAST_OP(0xB03B),CAST_OP(0xB03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048), +CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB05F), +CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB067),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068), +CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB078),CAST_OP(0xB079),CAST_OP(0xB07A),CAST_OP(0xB07B),CAST_OP(0xB07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088), +CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB09F), +CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A7),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8), +CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B8),CAST_OP(0xB0B9),CAST_OP(0xB0BA),CAST_OP(0xB0BB),CAST_OP(0xB0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8), +CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0DF), +CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E7),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8), +CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F8),CAST_OP(0xB0F9),CAST_OP(0xB0FA),CAST_OP(0xB0FB),CAST_OP(0xB0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB10F), +CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB11F), +CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB127),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128), +CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB138),CAST_OP(0xB139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB14F), +CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB15F), +CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB167),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168), +CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB178),CAST_OP(0xB179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB18F), +CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB19F), +CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A7),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8), +CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B8),CAST_OP(0xB1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8), +CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1DF), +CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E7),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8), +CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F8),CAST_OP(0xB1F9),CAST_OP(0xB1FA),CAST_OP(0xB1FB),CAST_OP(0xB1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008), +CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB01F), +CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB027),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028), +CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB038),CAST_OP(0xB039),CAST_OP(0xB03A),CAST_OP(0xB03B),CAST_OP(0xB03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048), +CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB05F), +CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB067),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068), +CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB078),CAST_OP(0xB079),CAST_OP(0xB07A),CAST_OP(0xB07B),CAST_OP(0xB07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088), +CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB09F), +CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A7),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8), +CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B8),CAST_OP(0xB0B9),CAST_OP(0xB0BA),CAST_OP(0xB0BB),CAST_OP(0xB0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8), +CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0DF), +CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E7),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8), +CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F8),CAST_OP(0xB0F9),CAST_OP(0xB0FA),CAST_OP(0xB0FB),CAST_OP(0xB0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB10F), +CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB11F), +CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB127),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128), +CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB138),CAST_OP(0xB139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB14F), +CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB15F), +CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB167),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168), +CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB178),CAST_OP(0xB179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB18F), +CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB19F), +CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A7),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8), +CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B8),CAST_OP(0xB1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8), +CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1DF), +CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E7),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8), +CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F8),CAST_OP(0xB1F9),CAST_OP(0xB1FA),CAST_OP(0xB1FB),CAST_OP(0xB1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008), +CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB01F), +CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB027),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028), +CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB038),CAST_OP(0xB039),CAST_OP(0xB03A),CAST_OP(0xB03B),CAST_OP(0xB03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048), +CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB05F), +CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB067),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068), +CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB078),CAST_OP(0xB079),CAST_OP(0xB07A),CAST_OP(0xB07B),CAST_OP(0xB07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088), +CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB09F), +CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A7),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8), +CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B8),CAST_OP(0xB0B9),CAST_OP(0xB0BA),CAST_OP(0xB0BB),CAST_OP(0xB0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8), +CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0DF), +CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E7),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8), +CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F8),CAST_OP(0xB0F9),CAST_OP(0xB0FA),CAST_OP(0xB0FB),CAST_OP(0xB0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB10F), +CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB11F), +CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB127),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128), +CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB138),CAST_OP(0xB139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB14F), +CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB15F), +CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB167),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168), +CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB178),CAST_OP(0xB179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB18F), +CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB19F), +CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A7),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8), +CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B8),CAST_OP(0xB1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8), +CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1DF), +CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E7),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8), +CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F8),CAST_OP(0xB1F9),CAST_OP(0xB1FA),CAST_OP(0xB1FB),CAST_OP(0xB1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008), +CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB01F), +CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB027),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028), +CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB038),CAST_OP(0xB039),CAST_OP(0xB03A),CAST_OP(0xB03B),CAST_OP(0xB03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048), +CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB05F), +CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB067),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068), +CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB078),CAST_OP(0xB079),CAST_OP(0xB07A),CAST_OP(0xB07B),CAST_OP(0xB07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088), +CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB09F), +CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A7),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8), +CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B8),CAST_OP(0xB0B9),CAST_OP(0xB0BA),CAST_OP(0xB0BB),CAST_OP(0xB0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8), +CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0DF), +CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E7),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8), +CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F8),CAST_OP(0xB0F9),CAST_OP(0xB0FA),CAST_OP(0xB0FB),CAST_OP(0xB0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB10F), +CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB11F), +CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB127),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128), +CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB138),CAST_OP(0xB139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB14F), +CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB15F), +CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB167),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168), +CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB178),CAST_OP(0xB179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB18F), +CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB19F), +CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A7),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8), +CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B8),CAST_OP(0xB1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8), +CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1DF), +CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E7),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8), +CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F8),CAST_OP(0xB1F9),CAST_OP(0xB1FA),CAST_OP(0xB1FB),CAST_OP(0xB1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008), +CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB01F), +CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB027),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028), +CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB038),CAST_OP(0xB039),CAST_OP(0xB03A),CAST_OP(0xB03B),CAST_OP(0xB03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048), +CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB05F), +CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB067),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068), +CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB078),CAST_OP(0xB079),CAST_OP(0xB07A),CAST_OP(0xB07B),CAST_OP(0xB07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088), +CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB09F), +CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A7),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8), +CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B8),CAST_OP(0xB0B9),CAST_OP(0xB0BA),CAST_OP(0xB0BB),CAST_OP(0xB0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8), +CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0DF), +CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E7),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8), +CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F8),CAST_OP(0xB0F9),CAST_OP(0xB0FA),CAST_OP(0xB0FB),CAST_OP(0xB0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB108),CAST_OP(0xB10F), +CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB11F), +CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB127),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128), +CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB138),CAST_OP(0xB139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB148),CAST_OP(0xB14F), +CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB15F), +CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB167),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168), +CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB178),CAST_OP(0xB179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB188),CAST_OP(0xB18F), +CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB19F), +CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A7),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8), +CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B8),CAST_OP(0xB1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8), +CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1DF), +CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E7),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8), +CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F8),CAST_OP(0xB1F9),CAST_OP(0xB1FA),CAST_OP(0xB1FB),CAST_OP(0xB1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB000),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008),CAST_OP(0xB008), +CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB010),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB018),CAST_OP(0xB01F), +CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB020),CAST_OP(0xB027),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028),CAST_OP(0xB028), +CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB030),CAST_OP(0xB038),CAST_OP(0xB039),CAST_OP(0xB03A),CAST_OP(0xB03B),CAST_OP(0xB03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB040),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048),CAST_OP(0xB048), +CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB050),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB058),CAST_OP(0xB05F), +CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB060),CAST_OP(0xB067),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068),CAST_OP(0xB068), +CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB070),CAST_OP(0xB078),CAST_OP(0xB079),CAST_OP(0xB07A),CAST_OP(0xB07B),CAST_OP(0xB07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB080),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088),CAST_OP(0xB088), +CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB090),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB098),CAST_OP(0xB09F), +CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A0),CAST_OP(0xB0A7),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8),CAST_OP(0xB0A8), +CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B0),CAST_OP(0xB0B8),CAST_OP(0xB0B9),CAST_OP(0xB0BA),CAST_OP(0xB0BB),CAST_OP(0xB0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C0),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8),CAST_OP(0xB0C8), +CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D0),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0D8),CAST_OP(0xB0DF), +CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E0),CAST_OP(0xB0E7),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8),CAST_OP(0xB0E8), +CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F0),CAST_OP(0xB0F8),CAST_OP(0xB0F9),CAST_OP(0xB0FA),CAST_OP(0xB0FB),CAST_OP(0xB0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xB100),CAST_OP(0xBF08),CAST_OP(0xBF08),CAST_OP(0xBF08),CAST_OP(0xBF08),CAST_OP(0xBF08),CAST_OP(0xBF08),CAST_OP(0xBF08),CAST_OP(0xBF0F), +CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB110),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB118),CAST_OP(0xB11F), +CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB120),CAST_OP(0xB127),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128),CAST_OP(0xB128), +CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB130),CAST_OP(0xB138),CAST_OP(0xB139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xB140),CAST_OP(0xBF48),CAST_OP(0xBF48),CAST_OP(0xBF48),CAST_OP(0xBF48),CAST_OP(0xBF48),CAST_OP(0xBF48),CAST_OP(0xBF48),CAST_OP(0xBF4F), +CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB150),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB158),CAST_OP(0xB15F), +CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB160),CAST_OP(0xB167),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168),CAST_OP(0xB168), +CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB170),CAST_OP(0xB178),CAST_OP(0xB179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xB180),CAST_OP(0xBF88),CAST_OP(0xBF88),CAST_OP(0xBF88),CAST_OP(0xBF88),CAST_OP(0xBF88),CAST_OP(0xBF88),CAST_OP(0xBF88),CAST_OP(0xBF8F), +CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB190),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB198),CAST_OP(0xB19F), +CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A0),CAST_OP(0xB1A7),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8),CAST_OP(0xB1A8), +CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B0),CAST_OP(0xB1B8),CAST_OP(0xB1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C0),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8),CAST_OP(0xB1C8), +CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D0),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1D8),CAST_OP(0xB1DF), +CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E0),CAST_OP(0xB1E7),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8),CAST_OP(0xB1E8), +CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F0),CAST_OP(0xB1F8),CAST_OP(0xB1F9),CAST_OP(0xB1FA),CAST_OP(0xB1FB),CAST_OP(0xB1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC01F), +CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC027),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028), +CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC038),CAST_OP(0xC039),CAST_OP(0xC03A),CAST_OP(0xC03B),CAST_OP(0xC03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC05F), +CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC067),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068), +CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC078),CAST_OP(0xC079),CAST_OP(0xC07A),CAST_OP(0xC07B),CAST_OP(0xC07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC09F), +CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A7),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8), +CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B8),CAST_OP(0xC0B9),CAST_OP(0xC0BA),CAST_OP(0xC0BB),CAST_OP(0xC0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0DF), +CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E7),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8), +CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F8),CAST_OP(0xC0F9),CAST_OP(0xC0FA),CAST_OP(0xC0FB),CAST_OP(0xC0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC10F), +CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC11F), +CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC127),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128), +CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC138),CAST_OP(0xC139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148), +CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC15F), +CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC167),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168), +CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC178),CAST_OP(0xC179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188), +CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC19F), +CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A7),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8), +CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B8),CAST_OP(0xC1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1DF), +CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E7),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8), +CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F8),CAST_OP(0xC1F9),CAST_OP(0xC1FA),CAST_OP(0xC1FB),CAST_OP(0xC1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC01F), +CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC027),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028), +CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC038),CAST_OP(0xC039),CAST_OP(0xC03A),CAST_OP(0xC03B),CAST_OP(0xC03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC05F), +CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC067),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068), +CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC078),CAST_OP(0xC079),CAST_OP(0xC07A),CAST_OP(0xC07B),CAST_OP(0xC07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC09F), +CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A7),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8), +CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B8),CAST_OP(0xC0B9),CAST_OP(0xC0BA),CAST_OP(0xC0BB),CAST_OP(0xC0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0DF), +CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E7),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8), +CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F8),CAST_OP(0xC0F9),CAST_OP(0xC0FA),CAST_OP(0xC0FB),CAST_OP(0xC0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC10F), +CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC11F), +CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC127),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128), +CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC138),CAST_OP(0xC139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148), +CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC15F), +CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC167),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168), +CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC178),CAST_OP(0xC179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188), +CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC19F), +CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A7),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8), +CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B8),CAST_OP(0xC1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1DF), +CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E7),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8), +CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F8),CAST_OP(0xC1F9),CAST_OP(0xC1FA),CAST_OP(0xC1FB),CAST_OP(0xC1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC01F), +CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC027),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028), +CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC038),CAST_OP(0xC039),CAST_OP(0xC03A),CAST_OP(0xC03B),CAST_OP(0xC03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC05F), +CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC067),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068), +CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC078),CAST_OP(0xC079),CAST_OP(0xC07A),CAST_OP(0xC07B),CAST_OP(0xC07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC09F), +CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A7),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8), +CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B8),CAST_OP(0xC0B9),CAST_OP(0xC0BA),CAST_OP(0xC0BB),CAST_OP(0xC0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0DF), +CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E7),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8), +CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F8),CAST_OP(0xC0F9),CAST_OP(0xC0FA),CAST_OP(0xC0FB),CAST_OP(0xC0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC10F), +CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC11F), +CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC127),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128), +CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC138),CAST_OP(0xC139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148), +CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC15F), +CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC167),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168), +CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC178),CAST_OP(0xC179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188), +CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC19F), +CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A7),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8), +CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B8),CAST_OP(0xC1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1DF), +CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E7),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8), +CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F8),CAST_OP(0xC1F9),CAST_OP(0xC1FA),CAST_OP(0xC1FB),CAST_OP(0xC1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC01F), +CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC027),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028), +CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC038),CAST_OP(0xC039),CAST_OP(0xC03A),CAST_OP(0xC03B),CAST_OP(0xC03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC05F), +CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC067),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068), +CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC078),CAST_OP(0xC079),CAST_OP(0xC07A),CAST_OP(0xC07B),CAST_OP(0xC07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC09F), +CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A7),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8), +CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B8),CAST_OP(0xC0B9),CAST_OP(0xC0BA),CAST_OP(0xC0BB),CAST_OP(0xC0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0DF), +CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E7),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8), +CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F8),CAST_OP(0xC0F9),CAST_OP(0xC0FA),CAST_OP(0xC0FB),CAST_OP(0xC0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC10F), +CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC11F), +CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC127),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128), +CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC138),CAST_OP(0xC139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148), +CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC15F), +CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC167),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168), +CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC178),CAST_OP(0xC179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188), +CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC19F), +CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A7),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8), +CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B8),CAST_OP(0xC1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1DF), +CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E7),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8), +CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F8),CAST_OP(0xC1F9),CAST_OP(0xC1FA),CAST_OP(0xC1FB),CAST_OP(0xC1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC01F), +CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC027),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028), +CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC038),CAST_OP(0xC039),CAST_OP(0xC03A),CAST_OP(0xC03B),CAST_OP(0xC03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC05F), +CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC067),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068), +CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC078),CAST_OP(0xC079),CAST_OP(0xC07A),CAST_OP(0xC07B),CAST_OP(0xC07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC09F), +CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A7),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8), +CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B8),CAST_OP(0xC0B9),CAST_OP(0xC0BA),CAST_OP(0xC0BB),CAST_OP(0xC0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0DF), +CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E7),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8), +CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F8),CAST_OP(0xC0F9),CAST_OP(0xC0FA),CAST_OP(0xC0FB),CAST_OP(0xC0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC10F), +CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC11F), +CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC127),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128), +CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC138),CAST_OP(0xC139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148), +CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC15F), +CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC167),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168), +CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC178),CAST_OP(0xC179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188), +CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC19F), +CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A7),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8), +CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B8),CAST_OP(0xC1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1DF), +CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E7),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8), +CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F8),CAST_OP(0xC1F9),CAST_OP(0xC1FA),CAST_OP(0xC1FB),CAST_OP(0xC1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC01F), +CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC027),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028), +CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC038),CAST_OP(0xC039),CAST_OP(0xC03A),CAST_OP(0xC03B),CAST_OP(0xC03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC05F), +CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC067),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068), +CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC078),CAST_OP(0xC079),CAST_OP(0xC07A),CAST_OP(0xC07B),CAST_OP(0xC07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC09F), +CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A7),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8), +CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B8),CAST_OP(0xC0B9),CAST_OP(0xC0BA),CAST_OP(0xC0BB),CAST_OP(0xC0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0DF), +CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E7),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8), +CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F8),CAST_OP(0xC0F9),CAST_OP(0xC0FA),CAST_OP(0xC0FB),CAST_OP(0xC0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC10F), +CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC11F), +CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC127),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128), +CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC138),CAST_OP(0xC139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148), +CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC15F), +CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC167),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168), +CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC178),CAST_OP(0xC179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188), +CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC19F), +CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A7),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8), +CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B8),CAST_OP(0xC1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1DF), +CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E7),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8), +CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F8),CAST_OP(0xC1F9),CAST_OP(0xC1FA),CAST_OP(0xC1FB),CAST_OP(0xC1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC01F), +CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC027),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028), +CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC038),CAST_OP(0xC039),CAST_OP(0xC03A),CAST_OP(0xC03B),CAST_OP(0xC03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC05F), +CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC067),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068), +CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC078),CAST_OP(0xC079),CAST_OP(0xC07A),CAST_OP(0xC07B),CAST_OP(0xC07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC09F), +CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A7),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8), +CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B8),CAST_OP(0xC0B9),CAST_OP(0xC0BA),CAST_OP(0xC0BB),CAST_OP(0xC0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0DF), +CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E7),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8), +CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F8),CAST_OP(0xC0F9),CAST_OP(0xC0FA),CAST_OP(0xC0FB),CAST_OP(0xC0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC108),CAST_OP(0xC10F), +CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC11F), +CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC127),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128), +CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC138),CAST_OP(0xC139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148), +CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC15F), +CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC167),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168), +CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC178),CAST_OP(0xC179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188), +CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC19F), +CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A7),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8), +CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B8),CAST_OP(0xC1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1DF), +CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E7),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8), +CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F8),CAST_OP(0xC1F9),CAST_OP(0xC1FA),CAST_OP(0xC1FB),CAST_OP(0xC1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0xC000),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC010),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC018),CAST_OP(0xC01F), +CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC020),CAST_OP(0xC027),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028),CAST_OP(0xC028), +CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC030),CAST_OP(0xC038),CAST_OP(0xC039),CAST_OP(0xC03A),CAST_OP(0xC03B),CAST_OP(0xC03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0xC040),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC050),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC058),CAST_OP(0xC05F), +CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC060),CAST_OP(0xC067),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068),CAST_OP(0xC068), +CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC070),CAST_OP(0xC078),CAST_OP(0xC079),CAST_OP(0xC07A),CAST_OP(0xC07B),CAST_OP(0xC07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0xC080),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC090),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC098),CAST_OP(0xC09F), +CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A0),CAST_OP(0xC0A7),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8),CAST_OP(0xC0A8), +CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B0),CAST_OP(0xC0B8),CAST_OP(0xC0B9),CAST_OP(0xC0BA),CAST_OP(0xC0BB),CAST_OP(0xC0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0xC0C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D0),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0D8),CAST_OP(0xC0DF), +CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E0),CAST_OP(0xC0E7),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8),CAST_OP(0xC0E8), +CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F0),CAST_OP(0xC0F8),CAST_OP(0xC0F9),CAST_OP(0xC0FA),CAST_OP(0xC0FB),CAST_OP(0xC0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xC100),CAST_OP(0xCF08),CAST_OP(0xCF08),CAST_OP(0xCF08),CAST_OP(0xCF08),CAST_OP(0xCF08),CAST_OP(0xCF08),CAST_OP(0xCF08),CAST_OP(0xCF0F), +CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC110),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC118),CAST_OP(0xC11F), +CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC120),CAST_OP(0xC127),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128),CAST_OP(0xC128), +CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC130),CAST_OP(0xC138),CAST_OP(0xC139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC140),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148),CAST_OP(0xC148), +CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC150),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC158),CAST_OP(0xC15F), +CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC160),CAST_OP(0xC167),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168),CAST_OP(0xC168), +CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC170),CAST_OP(0xC178),CAST_OP(0xC179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188),CAST_OP(0xC188), +CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC190),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC198),CAST_OP(0xC19F), +CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A0),CAST_OP(0xC1A7),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8),CAST_OP(0xC1A8), +CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B0),CAST_OP(0xC1B8),CAST_OP(0xC1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0xC1C0),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D0),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1D8),CAST_OP(0xC1DF), +CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E0),CAST_OP(0xC1E7),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8),CAST_OP(0xC1E8), +CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F0),CAST_OP(0xC1F8),CAST_OP(0xC1F9),CAST_OP(0xC1FA),CAST_OP(0xC1FB),CAST_OP(0xC1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008), +CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD01F), +CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD027),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028), +CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD038),CAST_OP(0xD039),CAST_OP(0xD03A),CAST_OP(0xD03B),CAST_OP(0xD03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048), +CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD05F), +CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD067),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068), +CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD078),CAST_OP(0xD079),CAST_OP(0xD07A),CAST_OP(0xD07B),CAST_OP(0xD07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088), +CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD09F), +CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A7),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8), +CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B8),CAST_OP(0xD0B9),CAST_OP(0xD0BA),CAST_OP(0xD0BB),CAST_OP(0xD0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8), +CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0DF), +CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E7),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8), +CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F8),CAST_OP(0xD0F9),CAST_OP(0xD0FA),CAST_OP(0xD0FB),CAST_OP(0xD0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD10F), +CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD11F), +CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD127),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128), +CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD138),CAST_OP(0xD139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD14F), +CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD15F), +CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD167),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168), +CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD178),CAST_OP(0xD179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD18F), +CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD19F), +CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A7),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8), +CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B8),CAST_OP(0xD1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8), +CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1DF), +CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E7),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8), +CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F8),CAST_OP(0xD1F9),CAST_OP(0xD1FA),CAST_OP(0xD1FB),CAST_OP(0xD1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008), +CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD01F), +CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD027),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028), +CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD038),CAST_OP(0xD039),CAST_OP(0xD03A),CAST_OP(0xD03B),CAST_OP(0xD03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048), +CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD05F), +CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD067),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068), +CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD078),CAST_OP(0xD079),CAST_OP(0xD07A),CAST_OP(0xD07B),CAST_OP(0xD07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088), +CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD09F), +CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A7),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8), +CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B8),CAST_OP(0xD0B9),CAST_OP(0xD0BA),CAST_OP(0xD0BB),CAST_OP(0xD0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8), +CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0DF), +CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E7),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8), +CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F8),CAST_OP(0xD0F9),CAST_OP(0xD0FA),CAST_OP(0xD0FB),CAST_OP(0xD0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD10F), +CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD11F), +CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD127),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128), +CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD138),CAST_OP(0xD139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD14F), +CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD15F), +CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD167),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168), +CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD178),CAST_OP(0xD179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD18F), +CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD19F), +CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A7),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8), +CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B8),CAST_OP(0xD1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8), +CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1DF), +CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E7),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8), +CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F8),CAST_OP(0xD1F9),CAST_OP(0xD1FA),CAST_OP(0xD1FB),CAST_OP(0xD1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008), +CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD01F), +CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD027),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028), +CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD038),CAST_OP(0xD039),CAST_OP(0xD03A),CAST_OP(0xD03B),CAST_OP(0xD03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048), +CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD05F), +CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD067),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068), +CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD078),CAST_OP(0xD079),CAST_OP(0xD07A),CAST_OP(0xD07B),CAST_OP(0xD07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088), +CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD09F), +CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A7),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8), +CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B8),CAST_OP(0xD0B9),CAST_OP(0xD0BA),CAST_OP(0xD0BB),CAST_OP(0xD0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8), +CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0DF), +CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E7),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8), +CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F8),CAST_OP(0xD0F9),CAST_OP(0xD0FA),CAST_OP(0xD0FB),CAST_OP(0xD0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD10F), +CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD11F), +CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD127),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128), +CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD138),CAST_OP(0xD139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD14F), +CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD15F), +CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD167),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168), +CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD178),CAST_OP(0xD179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD18F), +CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD19F), +CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A7),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8), +CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B8),CAST_OP(0xD1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8), +CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1DF), +CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E7),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8), +CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F8),CAST_OP(0xD1F9),CAST_OP(0xD1FA),CAST_OP(0xD1FB),CAST_OP(0xD1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008), +CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD01F), +CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD027),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028), +CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD038),CAST_OP(0xD039),CAST_OP(0xD03A),CAST_OP(0xD03B),CAST_OP(0xD03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048), +CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD05F), +CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD067),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068), +CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD078),CAST_OP(0xD079),CAST_OP(0xD07A),CAST_OP(0xD07B),CAST_OP(0xD07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088), +CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD09F), +CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A7),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8), +CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B8),CAST_OP(0xD0B9),CAST_OP(0xD0BA),CAST_OP(0xD0BB),CAST_OP(0xD0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8), +CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0DF), +CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E7),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8), +CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F8),CAST_OP(0xD0F9),CAST_OP(0xD0FA),CAST_OP(0xD0FB),CAST_OP(0xD0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD10F), +CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD11F), +CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD127),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128), +CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD138),CAST_OP(0xD139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD14F), +CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD15F), +CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD167),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168), +CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD178),CAST_OP(0xD179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD18F), +CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD19F), +CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A7),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8), +CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B8),CAST_OP(0xD1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8), +CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1DF), +CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E7),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8), +CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F8),CAST_OP(0xD1F9),CAST_OP(0xD1FA),CAST_OP(0xD1FB),CAST_OP(0xD1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008), +CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD01F), +CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD027),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028), +CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD038),CAST_OP(0xD039),CAST_OP(0xD03A),CAST_OP(0xD03B),CAST_OP(0xD03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048), +CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD05F), +CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD067),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068), +CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD078),CAST_OP(0xD079),CAST_OP(0xD07A),CAST_OP(0xD07B),CAST_OP(0xD07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088), +CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD09F), +CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A7),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8), +CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B8),CAST_OP(0xD0B9),CAST_OP(0xD0BA),CAST_OP(0xD0BB),CAST_OP(0xD0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8), +CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0DF), +CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E7),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8), +CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F8),CAST_OP(0xD0F9),CAST_OP(0xD0FA),CAST_OP(0xD0FB),CAST_OP(0xD0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD10F), +CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD11F), +CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD127),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128), +CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD138),CAST_OP(0xD139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD14F), +CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD15F), +CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD167),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168), +CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD178),CAST_OP(0xD179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD18F), +CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD19F), +CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A7),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8), +CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B8),CAST_OP(0xD1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8), +CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1DF), +CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E7),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8), +CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F8),CAST_OP(0xD1F9),CAST_OP(0xD1FA),CAST_OP(0xD1FB),CAST_OP(0xD1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008), +CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD01F), +CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD027),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028), +CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD038),CAST_OP(0xD039),CAST_OP(0xD03A),CAST_OP(0xD03B),CAST_OP(0xD03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048), +CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD05F), +CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD067),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068), +CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD078),CAST_OP(0xD079),CAST_OP(0xD07A),CAST_OP(0xD07B),CAST_OP(0xD07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088), +CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD09F), +CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A7),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8), +CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B8),CAST_OP(0xD0B9),CAST_OP(0xD0BA),CAST_OP(0xD0BB),CAST_OP(0xD0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8), +CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0DF), +CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E7),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8), +CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F8),CAST_OP(0xD0F9),CAST_OP(0xD0FA),CAST_OP(0xD0FB),CAST_OP(0xD0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD10F), +CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD11F), +CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD127),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128), +CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD138),CAST_OP(0xD139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD14F), +CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD15F), +CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD167),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168), +CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD178),CAST_OP(0xD179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD18F), +CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD19F), +CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A7),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8), +CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B8),CAST_OP(0xD1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8), +CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1DF), +CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E7),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8), +CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F8),CAST_OP(0xD1F9),CAST_OP(0xD1FA),CAST_OP(0xD1FB),CAST_OP(0xD1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008), +CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD01F), +CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD027),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028), +CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD038),CAST_OP(0xD039),CAST_OP(0xD03A),CAST_OP(0xD03B),CAST_OP(0xD03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048), +CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD05F), +CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD067),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068), +CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD078),CAST_OP(0xD079),CAST_OP(0xD07A),CAST_OP(0xD07B),CAST_OP(0xD07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088), +CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD09F), +CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A7),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8), +CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B8),CAST_OP(0xD0B9),CAST_OP(0xD0BA),CAST_OP(0xD0BB),CAST_OP(0xD0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8), +CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0DF), +CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E7),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8), +CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F8),CAST_OP(0xD0F9),CAST_OP(0xD0FA),CAST_OP(0xD0FB),CAST_OP(0xD0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD108),CAST_OP(0xD10F), +CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD11F), +CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD127),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128), +CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD138),CAST_OP(0xD139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD148),CAST_OP(0xD14F), +CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD15F), +CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD167),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168), +CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD178),CAST_OP(0xD179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD188),CAST_OP(0xD18F), +CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD19F), +CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A7),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8), +CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B8),CAST_OP(0xD1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8), +CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1DF), +CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E7),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8), +CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F8),CAST_OP(0xD1F9),CAST_OP(0xD1FA),CAST_OP(0xD1FB),CAST_OP(0xD1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD000),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008),CAST_OP(0xD008), +CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD010),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD018),CAST_OP(0xD01F), +CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD020),CAST_OP(0xD027),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028),CAST_OP(0xD028), +CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD030),CAST_OP(0xD038),CAST_OP(0xD039),CAST_OP(0xD03A),CAST_OP(0xD03B),CAST_OP(0xD03C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD040),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048),CAST_OP(0xD048), +CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD050),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD058),CAST_OP(0xD05F), +CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD060),CAST_OP(0xD067),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068),CAST_OP(0xD068), +CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD070),CAST_OP(0xD078),CAST_OP(0xD079),CAST_OP(0xD07A),CAST_OP(0xD07B),CAST_OP(0xD07C),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD080),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088),CAST_OP(0xD088), +CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD090),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD098),CAST_OP(0xD09F), +CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A0),CAST_OP(0xD0A7),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8),CAST_OP(0xD0A8), +CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B0),CAST_OP(0xD0B8),CAST_OP(0xD0B9),CAST_OP(0xD0BA),CAST_OP(0xD0BB),CAST_OP(0xD0BC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C0),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8),CAST_OP(0xD0C8), +CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D0),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0D8),CAST_OP(0xD0DF), +CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E0),CAST_OP(0xD0E7),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8),CAST_OP(0xD0E8), +CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F0),CAST_OP(0xD0F8),CAST_OP(0xD0F9),CAST_OP(0xD0FA),CAST_OP(0xD0FB),CAST_OP(0xD0FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xD100),CAST_OP(0xDF08),CAST_OP(0xDF08),CAST_OP(0xDF08),CAST_OP(0xDF08),CAST_OP(0xDF08),CAST_OP(0xDF08),CAST_OP(0xDF08),CAST_OP(0xDF0F), +CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD110),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD118),CAST_OP(0xD11F), +CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD120),CAST_OP(0xD127),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128),CAST_OP(0xD128), +CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD130),CAST_OP(0xD138),CAST_OP(0xD139),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xD140),CAST_OP(0xDF48),CAST_OP(0xDF48),CAST_OP(0xDF48),CAST_OP(0xDF48),CAST_OP(0xDF48),CAST_OP(0xDF48),CAST_OP(0xDF48),CAST_OP(0xDF4F), +CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD150),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD158),CAST_OP(0xD15F), +CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD160),CAST_OP(0xD167),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168),CAST_OP(0xD168), +CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD170),CAST_OP(0xD178),CAST_OP(0xD179),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xD180),CAST_OP(0xDF88),CAST_OP(0xDF88),CAST_OP(0xDF88),CAST_OP(0xDF88),CAST_OP(0xDF88),CAST_OP(0xDF88),CAST_OP(0xDF88),CAST_OP(0xDF8F), +CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD190),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD198),CAST_OP(0xD19F), +CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A0),CAST_OP(0xD1A7),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8),CAST_OP(0xD1A8), +CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B0),CAST_OP(0xD1B8),CAST_OP(0xD1B9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C0),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8),CAST_OP(0xD1C8), +CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D0),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1D8),CAST_OP(0xD1DF), +CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E0),CAST_OP(0xD1E7),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8),CAST_OP(0xD1E8), +CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F0),CAST_OP(0xD1F8),CAST_OP(0xD1F9),CAST_OP(0xD1FA),CAST_OP(0xD1FB),CAST_OP(0xD1FC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008), +CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018), +CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028), +CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038), +CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048), +CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058), +CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068), +CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078), +CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088), +CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098), +CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8), +CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE0D0),CAST_OP(0xE0D0),CAST_OP(0xE0D0),CAST_OP(0xE0D0),CAST_OP(0xE0D0),CAST_OP(0xE0D0),CAST_OP(0xE0D0),CAST_OP(0xE0D0),CAST_OP(0xE0D8),CAST_OP(0xE0D8),CAST_OP(0xE0D8),CAST_OP(0xE0D8),CAST_OP(0xE0D8),CAST_OP(0xE0D8),CAST_OP(0xE0D8),CAST_OP(0xE0DF), +CAST_OP(0xE0E0),CAST_OP(0xE0E0),CAST_OP(0xE0E0),CAST_OP(0xE0E0),CAST_OP(0xE0E0),CAST_OP(0xE0E0),CAST_OP(0xE0E0),CAST_OP(0xE0E7),CAST_OP(0xE0E8),CAST_OP(0xE0E8),CAST_OP(0xE0E8),CAST_OP(0xE0E8),CAST_OP(0xE0E8),CAST_OP(0xE0E8),CAST_OP(0xE0E8),CAST_OP(0xE0E8), +CAST_OP(0xE0F0),CAST_OP(0xE0F0),CAST_OP(0xE0F0),CAST_OP(0xE0F0),CAST_OP(0xE0F0),CAST_OP(0xE0F0),CAST_OP(0xE0F0),CAST_OP(0xE0F0),CAST_OP(0xE0F8),CAST_OP(0xE0F9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108), +CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118), +CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128), +CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138), +CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148), +CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158), +CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168), +CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178), +CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188), +CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198), +CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8), +CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE1D0),CAST_OP(0xE1D0),CAST_OP(0xE1D0),CAST_OP(0xE1D0),CAST_OP(0xE1D0),CAST_OP(0xE1D0),CAST_OP(0xE1D0),CAST_OP(0xE1D0),CAST_OP(0xE1D8),CAST_OP(0xE1D8),CAST_OP(0xE1D8),CAST_OP(0xE1D8),CAST_OP(0xE1D8),CAST_OP(0xE1D8),CAST_OP(0xE1D8),CAST_OP(0xE1DF), +CAST_OP(0xE1E0),CAST_OP(0xE1E0),CAST_OP(0xE1E0),CAST_OP(0xE1E0),CAST_OP(0xE1E0),CAST_OP(0xE1E0),CAST_OP(0xE1E0),CAST_OP(0xE1E7),CAST_OP(0xE1E8),CAST_OP(0xE1E8),CAST_OP(0xE1E8),CAST_OP(0xE1E8),CAST_OP(0xE1E8),CAST_OP(0xE1E8),CAST_OP(0xE1E8),CAST_OP(0xE1E8), +CAST_OP(0xE1F0),CAST_OP(0xE1F0),CAST_OP(0xE1F0),CAST_OP(0xE1F0),CAST_OP(0xE1F0),CAST_OP(0xE1F0),CAST_OP(0xE1F0),CAST_OP(0xE1F0),CAST_OP(0xE1F8),CAST_OP(0xE1F9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008), +CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018), +CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028), +CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038), +CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048), +CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058), +CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068), +CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078), +CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088), +CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098), +CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8), +CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE2D0),CAST_OP(0xE2D0),CAST_OP(0xE2D0),CAST_OP(0xE2D0),CAST_OP(0xE2D0),CAST_OP(0xE2D0),CAST_OP(0xE2D0),CAST_OP(0xE2D0),CAST_OP(0xE2D8),CAST_OP(0xE2D8),CAST_OP(0xE2D8),CAST_OP(0xE2D8),CAST_OP(0xE2D8),CAST_OP(0xE2D8),CAST_OP(0xE2D8),CAST_OP(0xE2DF), +CAST_OP(0xE2E0),CAST_OP(0xE2E0),CAST_OP(0xE2E0),CAST_OP(0xE2E0),CAST_OP(0xE2E0),CAST_OP(0xE2E0),CAST_OP(0xE2E0),CAST_OP(0xE2E7),CAST_OP(0xE2E8),CAST_OP(0xE2E8),CAST_OP(0xE2E8),CAST_OP(0xE2E8),CAST_OP(0xE2E8),CAST_OP(0xE2E8),CAST_OP(0xE2E8),CAST_OP(0xE2E8), +CAST_OP(0xE2F0),CAST_OP(0xE2F0),CAST_OP(0xE2F0),CAST_OP(0xE2F0),CAST_OP(0xE2F0),CAST_OP(0xE2F0),CAST_OP(0xE2F0),CAST_OP(0xE2F0),CAST_OP(0xE2F8),CAST_OP(0xE2F9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108), +CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118), +CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128), +CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138), +CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148), +CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158), +CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168), +CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178), +CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188), +CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198), +CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8), +CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE3D0),CAST_OP(0xE3D0),CAST_OP(0xE3D0),CAST_OP(0xE3D0),CAST_OP(0xE3D0),CAST_OP(0xE3D0),CAST_OP(0xE3D0),CAST_OP(0xE3D0),CAST_OP(0xE3D8),CAST_OP(0xE3D8),CAST_OP(0xE3D8),CAST_OP(0xE3D8),CAST_OP(0xE3D8),CAST_OP(0xE3D8),CAST_OP(0xE3D8),CAST_OP(0xE3DF), +CAST_OP(0xE3E0),CAST_OP(0xE3E0),CAST_OP(0xE3E0),CAST_OP(0xE3E0),CAST_OP(0xE3E0),CAST_OP(0xE3E0),CAST_OP(0xE3E0),CAST_OP(0xE3E7),CAST_OP(0xE3E8),CAST_OP(0xE3E8),CAST_OP(0xE3E8),CAST_OP(0xE3E8),CAST_OP(0xE3E8),CAST_OP(0xE3E8),CAST_OP(0xE3E8),CAST_OP(0xE3E8), +CAST_OP(0xE3F0),CAST_OP(0xE3F0),CAST_OP(0xE3F0),CAST_OP(0xE3F0),CAST_OP(0xE3F0),CAST_OP(0xE3F0),CAST_OP(0xE3F0),CAST_OP(0xE3F0),CAST_OP(0xE3F8),CAST_OP(0xE3F9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008), +CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018), +CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028), +CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038), +CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048), +CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058), +CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068), +CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078), +CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088), +CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098), +CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8), +CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE4D0),CAST_OP(0xE4D0),CAST_OP(0xE4D0),CAST_OP(0xE4D0),CAST_OP(0xE4D0),CAST_OP(0xE4D0),CAST_OP(0xE4D0),CAST_OP(0xE4D0),CAST_OP(0xE4D8),CAST_OP(0xE4D8),CAST_OP(0xE4D8),CAST_OP(0xE4D8),CAST_OP(0xE4D8),CAST_OP(0xE4D8),CAST_OP(0xE4D8),CAST_OP(0xE4DF), +CAST_OP(0xE4E0),CAST_OP(0xE4E0),CAST_OP(0xE4E0),CAST_OP(0xE4E0),CAST_OP(0xE4E0),CAST_OP(0xE4E0),CAST_OP(0xE4E0),CAST_OP(0xE4E7),CAST_OP(0xE4E8),CAST_OP(0xE4E8),CAST_OP(0xE4E8),CAST_OP(0xE4E8),CAST_OP(0xE4E8),CAST_OP(0xE4E8),CAST_OP(0xE4E8),CAST_OP(0xE4E8), +CAST_OP(0xE4F0),CAST_OP(0xE4F0),CAST_OP(0xE4F0),CAST_OP(0xE4F0),CAST_OP(0xE4F0),CAST_OP(0xE4F0),CAST_OP(0xE4F0),CAST_OP(0xE4F0),CAST_OP(0xE4F8),CAST_OP(0xE4F9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108), +CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118), +CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128), +CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138), +CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148), +CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158), +CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168), +CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178), +CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188), +CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198), +CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8), +CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE5D0),CAST_OP(0xE5D0),CAST_OP(0xE5D0),CAST_OP(0xE5D0),CAST_OP(0xE5D0),CAST_OP(0xE5D0),CAST_OP(0xE5D0),CAST_OP(0xE5D0),CAST_OP(0xE5D8),CAST_OP(0xE5D8),CAST_OP(0xE5D8),CAST_OP(0xE5D8),CAST_OP(0xE5D8),CAST_OP(0xE5D8),CAST_OP(0xE5D8),CAST_OP(0xE5DF), +CAST_OP(0xE5E0),CAST_OP(0xE5E0),CAST_OP(0xE5E0),CAST_OP(0xE5E0),CAST_OP(0xE5E0),CAST_OP(0xE5E0),CAST_OP(0xE5E0),CAST_OP(0xE5E7),CAST_OP(0xE5E8),CAST_OP(0xE5E8),CAST_OP(0xE5E8),CAST_OP(0xE5E8),CAST_OP(0xE5E8),CAST_OP(0xE5E8),CAST_OP(0xE5E8),CAST_OP(0xE5E8), +CAST_OP(0xE5F0),CAST_OP(0xE5F0),CAST_OP(0xE5F0),CAST_OP(0xE5F0),CAST_OP(0xE5F0),CAST_OP(0xE5F0),CAST_OP(0xE5F0),CAST_OP(0xE5F0),CAST_OP(0xE5F8),CAST_OP(0xE5F9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008), +CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018), +CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028), +CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038), +CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048), +CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058), +CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068), +CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078), +CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088), +CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098), +CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8), +CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE6D0),CAST_OP(0xE6D0),CAST_OP(0xE6D0),CAST_OP(0xE6D0),CAST_OP(0xE6D0),CAST_OP(0xE6D0),CAST_OP(0xE6D0),CAST_OP(0xE6D0),CAST_OP(0xE6D8),CAST_OP(0xE6D8),CAST_OP(0xE6D8),CAST_OP(0xE6D8),CAST_OP(0xE6D8),CAST_OP(0xE6D8),CAST_OP(0xE6D8),CAST_OP(0xE6DF), +CAST_OP(0xE6E0),CAST_OP(0xE6E0),CAST_OP(0xE6E0),CAST_OP(0xE6E0),CAST_OP(0xE6E0),CAST_OP(0xE6E0),CAST_OP(0xE6E0),CAST_OP(0xE6E7),CAST_OP(0xE6E8),CAST_OP(0xE6E8),CAST_OP(0xE6E8),CAST_OP(0xE6E8),CAST_OP(0xE6E8),CAST_OP(0xE6E8),CAST_OP(0xE6E8),CAST_OP(0xE6E8), +CAST_OP(0xE6F0),CAST_OP(0xE6F0),CAST_OP(0xE6F0),CAST_OP(0xE6F0),CAST_OP(0xE6F0),CAST_OP(0xE6F0),CAST_OP(0xE6F0),CAST_OP(0xE6F0),CAST_OP(0xE6F8),CAST_OP(0xE6F9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108), +CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118), +CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128), +CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138), +CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148), +CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158), +CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168), +CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178), +CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188), +CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198), +CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8), +CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE7D0),CAST_OP(0xE7D0),CAST_OP(0xE7D0),CAST_OP(0xE7D0),CAST_OP(0xE7D0),CAST_OP(0xE7D0),CAST_OP(0xE7D0),CAST_OP(0xE7D0),CAST_OP(0xE7D8),CAST_OP(0xE7D8),CAST_OP(0xE7D8),CAST_OP(0xE7D8),CAST_OP(0xE7D8),CAST_OP(0xE7D8),CAST_OP(0xE7D8),CAST_OP(0xE7DF), +CAST_OP(0xE7E0),CAST_OP(0xE7E0),CAST_OP(0xE7E0),CAST_OP(0xE7E0),CAST_OP(0xE7E0),CAST_OP(0xE7E0),CAST_OP(0xE7E0),CAST_OP(0xE7E7),CAST_OP(0xE7E8),CAST_OP(0xE7E8),CAST_OP(0xE7E8),CAST_OP(0xE7E8),CAST_OP(0xE7E8),CAST_OP(0xE7E8),CAST_OP(0xE7E8),CAST_OP(0xE7E8), +CAST_OP(0xE7F0),CAST_OP(0xE7F0),CAST_OP(0xE7F0),CAST_OP(0xE7F0),CAST_OP(0xE7F0),CAST_OP(0xE7F0),CAST_OP(0xE7F0),CAST_OP(0xE7F0),CAST_OP(0xE7F8),CAST_OP(0xE7F9),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008), +CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018), +CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028), +CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038), +CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048), +CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058), +CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068), +CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078), +CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088), +CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098), +CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8), +CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108), +CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118), +CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128), +CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138), +CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148), +CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158), +CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168), +CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178), +CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188), +CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198), +CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8), +CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008), +CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018), +CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028), +CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038), +CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048), +CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058), +CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068), +CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078), +CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088), +CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098), +CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8), +CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108), +CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118), +CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128), +CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138), +CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148), +CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158), +CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168), +CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178), +CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188), +CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198), +CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8), +CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008), +CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018), +CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028), +CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038), +CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048), +CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058), +CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068), +CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078), +CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088), +CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098), +CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8), +CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108), +CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118), +CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128), +CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138), +CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148), +CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158), +CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168), +CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178), +CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188), +CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198), +CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8), +CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE000),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008),CAST_OP(0xE008), +CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE010),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018),CAST_OP(0xE018), +CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE020),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028),CAST_OP(0xE028), +CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE030),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038),CAST_OP(0xE038), +CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE040),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048),CAST_OP(0xE048), +CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE050),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058),CAST_OP(0xE058), +CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE060),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068),CAST_OP(0xE068), +CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE070),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078),CAST_OP(0xE078), +CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE080),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088),CAST_OP(0xE088), +CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE090),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098),CAST_OP(0xE098), +CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A0),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8),CAST_OP(0xE0A8), +CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B0),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8),CAST_OP(0xE0B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE100),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108),CAST_OP(0xE108), +CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE110),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118),CAST_OP(0xE118), +CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE120),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128),CAST_OP(0xE128), +CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE130),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138),CAST_OP(0xE138), +CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE140),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148),CAST_OP(0xE148), +CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE150),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158),CAST_OP(0xE158), +CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE160),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168),CAST_OP(0xE168), +CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE170),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178),CAST_OP(0xE178), +CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE180),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188),CAST_OP(0xE188), +CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE190),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198),CAST_OP(0xE198), +CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A0),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8),CAST_OP(0xE1A8), +CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B0),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8),CAST_OP(0xE1B8), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC),CAST_OP(0x4AFC), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), 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+CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000),CAST_OP(0xF000), +}; diff --git a/MCUME_esp32/espcastaway/main/68kfame/m68k_intrf.cpp b/MCUME_esp32/espcastaway/main/68kfame/m68k_intrf.cpp new file mode 100644 index 0000000..3424f8b --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68kfame/m68k_intrf.cpp @@ -0,0 +1,322 @@ +#include +#include +#include + +#include "dcastaway.h" +#include "mem.h" +#include "st.h" +#include "config.h" + +#include "m68k_intrf.h" + +#ifdef DEBUG_FAME +FILE *fame_debug_file=stdout; +unsigned fame_debug_count=0; +#ifdef DEBUG_FAME_START +int fame_debug_output=0; +#else +int fame_debug_output=1; +#endif +#endif + +#ifdef DEBUG_FAME +#include "dis.h" +#endif + +void SetMemBB(unsigned long address, unsigned char value); +void SetMemWW(unsigned long address, unsigned short value); + +char GetMemB(unsigned long address); +short GetMemW(unsigned long address); +long GetMemL(unsigned long address); +void SetMemB(unsigned long address, unsigned char value); +void SetMemW(unsigned long address, unsigned short value); +void SetMemL(unsigned long address, unsigned long value); + + +#if defined(FAME_SINGLE_MEMORY) && defined(DEBUG_FAME) + +static char MyGetMemB(unsigned long address) +{ + char ret; + + if (fame_debug_output) + { fprintf(fame_debug_file,"GetMemB(0x%.6X)",address); DEBUG_FAME_FFLUSH; } + + ret=GetMemB(address); + + if (fame_debug_output) + { fprintf(fame_debug_file," = 0x%.2X\n",ret); DEBUG_FAME_FFLUSH; } + + return ret; +} + +static short MyGetMemW(unsigned long address) +{ + short ret; + + if (fame_debug_output) + { fprintf(fame_debug_file,"GetMemW(0x%.6X)",address); DEBUG_FAME_FFLUSH; } + + ret=GetMemW(address); + + if (fame_debug_output) + { fprintf(fame_debug_file," = 0x%.4X\n",ret); DEBUG_FAME_FFLUSH; } + + return ret; +} + +static void MySetMemB(unsigned long address, unsigned value) +{ + value&=0xff; + if (fame_debug_output) + { fprintf(fame_debug_file,"SetMemB(0x%.6X,0x%.2X)",address,value); DEBUG_FAME_FFLUSH; } + + SetMemB(address,value); + + if (fame_debug_output) + { fputs(fame_debug_file,"."); DEBUG_FAME_FFLUSH; } +} + +static void MySetMemW(unsigned long address, unsigned value) +{ + value&=0xffff; + if (fame_debug_output) + { fprintf(fame_debug_file,"SetMemW(0x%.6X,0x%.4X)",address,value); DEBUG_FAME_FFLUSH; } + + SetMemW(address,value); + + if (fame_debug_output) + { fputs(".",fame_debug_file); DEBUG_FAME_FFLUSH; } +} + +#else + +#define MyGetMemW GetMemW +#define MyGetMemB GetMemB +#define MySetMemW SetMemW +#define MySetMemB SetMemB + +#endif + +#ifndef USE_FAME_CORE +int recalc_int=1; //0; +#endif +int in_fame_core=0; +int number_exg0_fame=0; +static unsigned addr_exg0_fame=0; +static unsigned pc_exg0_fame=0; +static unsigned sr_exg0_fame=0; +static int rw_exg0_fame=0; +static unsigned long exaddress=0x12345678; + +void HWReset(void) +{ + m68k_reset(); + exaddress=0x12345678; +} + +static int inexec=0; + +void ExceptionGroup0_execute(void) +{ + short context = 0; + +#ifdef DEBUG_FAME + if (fame_debug_output) + { fputs("ExceptionGroup0_execute",fame_debug_file); DEBUG_FAME_FFLUSH; } +#endif + + M68KCONTEXT.execinfo&=0x7F; + + if ((!((exaddress+1!=addr_exg0_fame)&&(exaddress+2!=addr_exg0_fame)&&(exaddress+3!=addr_exg0_fame))) || (!inexec)) + { + if (!inexec) + m68k_reset(); + return; + } + inexec=0; + + context |= 0x8; + if (rw_exg0_fame) + context |= 0x10; + if (GetS()) + context |= 0x4; + if (rw_exg0_fame && addr_exg0_fame == pc_exg0_fame) + context |= 0x2; + else + context |= 0x1; + + M68KCONTEXT.sr |= (1<<13); + M68KCONTEXT.sr &= ~(1<<15); + + M68KCONTEXT.areg[7]-=14; + SetMemW(M68KCONTEXT.areg[7], context); + SetMemL(M68KCONTEXT.areg[7] + 2, addr_exg0_fame); + SetMemW(M68KCONTEXT.areg[7] + 6, GetMemW(pc_exg0_fame)); + SetMemW(M68KCONTEXT.areg[7] + 8, sr_exg0_fame); + SetMemL(M68KCONTEXT.areg[7] + 10, pc_exg0_fame); + + M68KCONTEXT.pc=GetMemL((long)number_exg0_fame * 4); + + exaddress=addr_exg0_fame; + number_exg0_fame=0; +} + +void ExceptionGroup0( + int number, /* trap number */ + unsigned long address, /* fault address */ + int rw) /* read = true, write = false */ +{ +#ifdef DEBUG_FAME + if (fame_debug_output) + { fprintf(fame_debug_file,"ExceptionGroup0(%i,0x%X,%i)\n",number,address,rw); DEBUG_FAME_FFLUSH; } +#endif + if ((exaddress+1!=address)&&(exaddress+2!=address)&&(exaddress+3!=address)&&(!inexec)){ + inexec=1; + number_exg0_fame=number; + addr_exg0_fame=address; + rw_exg0_fame=rw; + pc_exg0_fame=M68KCONTEXT.pc; + sr_exg0_fame=M68KCONTEXT.sr; + if (!in_fame_core) + ExceptionGroup0_execute(); + else + IO_CYCLE=0; + } +} + + +static M68K_CONTEXT context; + +static M68K_PROGRAM program[]= { + {0, MEMSIZE-1, (unsigned)membase}, + {MEMSIZE, (MEMSIZE*2)-1, ((unsigned)membase)-MEMSIZE}, + {MEMSIZE*2, (MEMSIZE*3)-1, ((unsigned)membase)-(MEMSIZE*2)}, +#if MEMSIZE*4 <= ROMBASE2 + {MEMSIZE*3, (MEMSIZE*4)-1, ((unsigned)membase)-(MEMSIZE*3)}, +#if MEMSIZE*5 <= ROMBASE2 + {MEMSIZE*4, (MEMSIZE*5)-1, ((unsigned)membase)-(MEMSIZE*4)}, +#if MEMSIZE*6 <= ROMBASE2 + {MEMSIZE*5, (MEMSIZE*6)-1, ((unsigned)membase)-(MEMSIZE*5)}, +#if MEMSIZE*7 <= ROMBASE2 + {MEMSIZE*6, (MEMSIZE*7)-1, ((unsigned)membase)-(MEMSIZE*6)}, +#if MEMSIZE*8 <= ROMBASE2 + {MEMSIZE*7, (MEMSIZE*8)-1, ((unsigned)membase)-(MEMSIZE*7)}, +#if MEMSIZE*9 <= ROMBASE2 + {MEMSIZE*8, (MEMSIZE*9)-1, ((unsigned)membase)-(MEMSIZE*8)}, +#if MEMSIZE*10 <= ROMBASE2 + {MEMSIZE*9, (MEMSIZE*10)-1, ((unsigned)membase)-(MEMSIZE*9)}, +#if MEMSIZE*11 <= ROMBASE2 + {MEMSIZE*10, (MEMSIZE*11)-1, ((unsigned)membase)-(MEMSIZE*10)}, +#if MEMSIZE*12 <= ROMBASE2 + {MEMSIZE*11, (MEMSIZE*12)-1, ((unsigned)membase)-(MEMSIZE*11)}, +#if MEMSIZE*13 <= ROMBASE2 + {MEMSIZE*12, (MEMSIZE*13)-1, ((unsigned)membase)-(MEMSIZE*12)}, +#if MEMSIZE*14 <= ROMBASE2 + {MEMSIZE*13, (MEMSIZE*14)-1, ((unsigned)membase)-(MEMSIZE*13)}, +#if MEMSIZE*15 <= ROMBASE2 + {MEMSIZE*14, (MEMSIZE*15)-1, ((unsigned)membase)-(MEMSIZE*14)}, +#if MEMSIZE*16 <= ROMBASE2 + {MEMSIZE*15, (MEMSIZE*16)-1, ((unsigned)membase)-(MEMSIZE*15)}, +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif + {ROMBASE2, (IOBASE-1), (unsigned)rombase}, + {IOBASE, 0x00FFFFFF, (unsigned)rombase}, + {(unsigned)-1,(unsigned)-1,(unsigned)NULL} +}; + +#ifndef FAME_SINGLE_MEMORY +static M68K_DATA read8[] = { + {0, MEMSIZE-1, NULL, (void *)membase}, + {MEMSIZE, (ROMBASE2)-1, (void *)GetMemB, NULL}, + {ROMBASE2, IOBASE-1, NULL, (void *)rombase}, + {IOBASE, 0x00FFFFFF, (void *)DoIORB, NULL}, + {(unsigned)-1,(unsigned)-1,NULL,NULL} +}; + +static M68K_DATA read16[] = { + {0, MEMSIZE-1, NULL, (void *)membase}, + {MEMSIZE, (ROMBASE2)-1, (void *)GetMemW, NULL}, + {ROMBASE2, IOBASE-1, NULL, (void *)rombase}, + {IOBASE, 0x00FFFFFF, (void *)DoIORW, NULL}, + {(unsigned)-1,(unsigned)-1,NULL,NULL} +}; + +static M68K_DATA write8[] = { +// {0, MEMSIZE-1, NULL, (void *)membase}, + {0, MEMSIZE-1, (void *)SetMemBB, NULL}, + {MEMSIZE, (IOBASE)-1, (void *)SetMemB, NULL}, + {IOBASE, 0x00FFFFFF, (void *)DoIOWB, NULL}, + {(unsigned)-1,(unsigned)-1,NULL,NULL} +}; + +static M68K_DATA write16[] = { +// {0, MEMSIZE-1, NULL, (void *)membase}, + {0, MEMSIZE-1, (void *)SetMemWW, NULL}, + {MEMSIZE, (IOBASE)-1, (void *)SetMemW, NULL}, + {IOBASE, 0x00FFFFFF, (void *)DoIOWW, NULL}, + {(unsigned)-1,(unsigned)-1,NULL,NULL} +}; + +#else + +static M68K_DATA read8[] = { + { 0, 0xFFFFFF, (void *)MyGetMemB, NULL }, + {(unsigned)-1,(unsigned)-1,NULL,NULL} +}; + +static M68K_DATA read16[] = { + { 0, 0xFFFFFF, (void *)MyGetMemW, NULL }, + {(unsigned)-1,(unsigned)-1,NULL,NULL} +}; + +static M68K_DATA write8[] = { + { 0, 0xFFFFFF, (void *)MySetMemB, NULL }, + {(unsigned)-1,(unsigned)-1,NULL,NULL} +}; + +static M68K_DATA write16[] = { + { 0, 0xFFFFFF, (void *)MySetMemW, NULL }, + {(unsigned)-1,(unsigned)-1,NULL,NULL} +}; + +#endif + +void initialize_memmap(void) +{ + int i; + memset(&context,0,sizeof(M68K_CONTEXT)); + context.fetch=context.sv_fetch=context.user_fetch=(M68K_PROGRAM*)&program; + context.read_byte=context.sv_read_byte=context.user_read_byte=(M68K_DATA*)&read8; + context.read_word=context.sv_read_word=context.user_read_word=(M68K_DATA*)&read16; + context.write_byte=context.sv_write_byte=context.user_write_byte=(M68K_DATA*)&write8; + context.write_word=context.sv_write_word=context.user_write_word=(M68K_DATA*)&write16; + for(i=0;program[i].low_addr != ((unsigned)-1);i++) +{ + if (program[i].low_addr >= ROMBASE2) + program[i].offset= (((unsigned)rombase)+ROMBASE2)-program[i].low_addr; + else + program[i].offset= ((unsigned)membase) - (i*MEMSIZE); +} + +#ifndef FAME_SINGLE_MEMORY + read8[0].data=read16[0].data=write8[0].data=write16[0].data=(void *)((unsigned)membase); + read8[2].data=read16[2].data=(void *)((unsigned)rombase); +#endif + + m68k_init(); + m68k_set_context(&context); + m68k_reset(); +} diff --git a/MCUME_esp32/espcastaway/main/68kfame/m68k_intrf.h b/MCUME_esp32/espcastaway/main/68kfame/m68k_intrf.h new file mode 100644 index 0000000..03da072 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68kfame/m68k_intrf.h @@ -0,0 +1,232 @@ +#include +#include +#include "config.h" +#include "dcastaway.h" + +extern int waitstate; + +#ifndef USE_FAME_CORE + +#include "castaway/68000.h" +#include "castaway/op68k.h" + +extern unsigned IO_CYCLE; + +static __inline__ unsigned long cpu_loop(unsigned slice) { + +extern unsigned long (*jmp_table[8192])(operin); + +#define initialize_memmap() + //printf("%8x =>%8x\n",pc,myinst); + +#define cpuinst \ + address = pc&MEMADDRMASK; \ + if (address=ROMBASE2) myinst=biginst=ReadSL(myrombase+address); \ + else { HWReset(); return slice-IO_CYCLE; } \ + pc+=2; \ + IO_CYCLE-=(*jmp_table[(myinst<<16)>>19])(reg); + + register unsigned long *p_reg=(unsigned long *)®[0]; + register unsigned long address; + register int8 *mymembase=membase; + register int8 *myrombase=rombase; + register uint32 myinst; + IO_CYCLE=slice; + //Execute 10 instructions + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + return slice-IO_CYCLE; +#undef cpuinst +} + + +#else + +#include "fame.h" + + +#if defined(DREAMCAST) || defined(USE_FAME_CORE_C) +#define M68KCONTEXT m68kcontext +#define IO_CYCLE io_cycle_counter +#else +#define M68KCONTEXT _m68kcontext +#define IO_CYCLE __io_cycle_counter +#endif + +extern unsigned IO_CYCLE; + +//extern struct M68K_CONTEXT M68KCONTEXT; +extern M68K_CONTEXT M68KCONTEXT; +extern int recalc_int; +extern void SetMemW(unsigned long address, unsigned short value); +extern void HWReset(void); + +#define GetS() ((M68KCONTEXT.sr >> 13) & 1) +#define GetFC2() GetS() +#define GetI() ((M68KCONTEXT.sr >> 8) & 7) +#ifdef DEBUG_FAME +#define Interrupt(NUM,LEV) \ +{ \ + extern int fame_debug_output; \ + extern FILE *fame_debug_file; \ + if (fame_debug_output) \ + { fprintf(fame_debug_file,"Interrupt(%i,%i)\n",(NUM),(LEV)); DEBUG_FAME_FFLUSH; } \ + m68k_lower_irq((LEV)); \ + m68k_raise_irq((LEV),(NUM)); \ +} +#else +#define Interrupt(NUM,LEV) \ +{ \ + M68KCONTEXT.interrupts[0] |= (1 << (LEV)); \ + M68KCONTEXT.interrupts[(LEV)]=(NUM); \ + M68KCONTEXT.execinfo &= 0x7F; \ +} +#endif + +#define ClearInterrupt(LEV) M68KCONTEXT.interrupts[0] &= ~(1 << (LEV)) + + +#define MEMADDRMASK 0x00ffffffl +#define MEMADDRMASKS 0x00fffffel +#define MEMIDXSHIFT 11 +#define MEMADDRSIZE (MEMADDRMASK + 1) +#define AUTOINT2 26 +#define AUTOINT4 28 +#define BUSERR 2 +#define ADDRESSERR 3 + +char GetMemB(unsigned long address); +short GetMemW(unsigned long address); +void initialize_memmap(void); +void ExceptionGroup0( int, unsigned long, int); +void ExceptionGroup0_execute(void); + + +#ifdef DEBUG_FAME +static char dis_msg[96]; +static unsigned short dis_buf[10]; +void disassemble68k(char *buf, unsigned short *inst_stream); +static __inline__ unsigned long cpu_loop(unsigned slice) +{ + unsigned i; + extern int number_exg0_fame; + extern int in_fame_core; + extern unsigned fame_debug_count; + extern int fame_debug_output; + extern FILE *fame_debug_file; + +#ifdef DEBUG_FAME_START + if (fame_debug_count>=((unsigned)(DEBUG_FAME_START))) + fame_debug_output=1; + else { + unsigned long cycles_actual=M68KCONTEXT.cycles_counter; + short lastint=M68KCONTEXT.sr&0x700; + + in_fame_core=1; + m68k_emulate(slice); + in_fame_core=0; + + fprintf(fame_debug_file,"SLICE(%u) %u (%u) ret=%u (%x %x)\n",slice,fame_debug_count,slice,M68KCONTEXT.cycles_counter-cycles_actual,M68KCONTEXT.execinfo&0x80,M68KCONTEXT.interrupts[0]); + fame_debug_count++; + + if (number_exg0_fame) + ExceptionGroup0_execute(); + + if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700))) + M68KCONTEXT.execinfo&=0x7f; + + return (M68KCONTEXT.cycles_counter-cycles_actual); + } + + if (fame_debug_output) + fprintf(fame_debug_file,"SLICE(%u) %u (%u)\n",slice,fame_debug_count,slice); +#endif + + in_fame_core=1; + unsigned long cycles_actual=M68KCONTEXT.cycles_counter; + short lastint=M68KCONTEXT.sr&0x700; + while(M68KCONTEXT.cycles_counter-cycles_actual((unsigned)(DEBUG_FAME_STOP))) + { +#ifdef DEBUG_FAME_FILE + extern FILE *fame_debug_file; + if (fame_debug_file) + fclose(fame_debug_file); + fame_debug_file=NULL; +#endif + free(malloc(24*1024*1024)); exit(0); } +#endif + if (number_exg0_fame) + { + ExceptionGroup0_execute(); + number_exg0_fame=0; + } + if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700))) + M68KCONTEXT.execinfo&=0x7f; + return (M68KCONTEXT.cycles_counter-cycles_actual); +} + +#else +static __inline__ unsigned long cpu_loop(unsigned slice) +{ + extern int in_fame_core; + extern int number_exg0_fame; + + unsigned long cycles_actual=M68KCONTEXT.cycles_counter; + short lastint=M68KCONTEXT.sr&0x700; + + in_fame_core=1; + m68k_emulate(slice); + in_fame_core=0; + + if (number_exg0_fame) + ExceptionGroup0_execute(); + + if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700))) + M68KCONTEXT.execinfo&=0x7f; + + return (M68KCONTEXT.cycles_counter-cycles_actual); +} +#endif + + +#endif diff --git a/MCUME_esp32/espcastaway/main/68korig/68000.cpp b/MCUME_esp32/espcastaway/main/68korig/68000.cpp new file mode 100755 index 0000000..2953eed --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/68000.cpp @@ -0,0 +1,275 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* 68000.c - 68000 emulator jump table and misc subroutines +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 09.06.2002 JH Use of mmap for memory access discontinued +* 12.06.2002 JH Correct bus error/address error exception stack frame +* 13.06.2002 JH Merged in Martin's BCD implementation (untested), +* completed jump table. STOP is now the only +* unimplemented instruction. +* 14.06.2002 JH Implemented STOP, shutdown CPU after multiple bus errors. +* Removed inst parameter from CPU opcode functions. +* 19.06.2002 JH CPURun() returns # of executed instructions. +* 20.06.2002 JH added yet another SR implementation variant. +* 02.07.2002 JH Support different CPU types. Removed MOVE CCR, from +* 68000 jump table. +* 20.08.2002 JH Fixed CPU shutdown. +* 27.08.2002 JH Bugfix: S and T flag incorrectly reported for group 0 exceptions +* Implemented additional 68010 registers and instructions. +* 31.08.2002 JH Implemented M68010 exception stack frames. +* 08.10.2002 JH Implemented Trace exception +*/ +static char sccsid[] = "$Id: 68000.c,v 1.18 2002/10/10 19:52:11 jhoenig Exp $"; +#include "config.h" + +#include +#include +#include +#include "68000.h" +#include "mem.h" +#include "st.h" +#include "op68k.h" +#include "proto.h" +#include "operin.h" + + +#if (CPU_TYPE == 68000 || CPU_TYPE == 68008) +#include "op68000.h" +#elif (CPU_TYPE == 68010) // broken +#include "op68010.h" +#endif +extern int disass; +unsigned long reg[23]; +unsigned long dfc, sfc, vbr; +#define biginst reg[18] +#define pc reg[19] +#define usp reg[20] +#define ssp reg[21] +#define recalc_int reg[22] + + +extern void StartDisass(); +unsigned short SaveWordTrc; +unsigned char GetTrc; +unsigned short int0=0; +unsigned long exaddress=0x12345678; +int intmask, intpri; +char cpu_state; +unsigned cpu_type; +volatile unsigned cpu_count; + +jmp_buf trap_buf; + + +unsigned short GetSRB(void) +{ + uint32 cvnz=reg[16]; //-------c-------v-------n-------z + uint32 stx=reg[17]; //---------------s-------t-------x + uint32 sr=(cvnz>>24)+(cvnz>>15)+(cvnz<<2)+(cvnz>>5)+(stx<<4); + return sr&(unsigned short)0xff; +} + +unsigned short GetSRW(void) +{ + uint32 cvnz=reg[16]; //-------c-------v-------n-------z + uint32 stx=reg[17]; //---------------s-------t-------x + uint32 sr=(cvnz>>24)+(cvnz>>15)+(cvnz<<2)+(cvnz>>5)+(stx<<4); + uint32 sr2=(stx<<7)+(stx>>3)+(intmask<<8); + return (sr&(unsigned short)0xff)+(sr2&(unsigned short)0xff00); +} + + +void SetSRB(unsigned long sr) +{ + uint32 cvnz=((sr&1)<<24)+((sr&2)<<15)+((sr&4)>>2)+((sr&8)<<5); + reg[16]=cvnz; + SetX(sr&0x10); +} + +void SetSRW(unsigned long sr) +{ + uint32 cvnz=((sr&1)<<24)+((sr&2)<<15)+((sr&4)>>2)+((sr&8)<<5); + reg[16]=cvnz; + SetX (sr&0x10); + SetI ((sr&0x700)>>8); + SetS (sr&0x2000); + SetT (sr&0x8000); +} + +void ExceptionGroup0( + int number, + unsigned long address, + int ReadWrite) +{ + short sr = GetSRW(), context = 0; +#ifdef DEBUG + ON_TRAP(number); + assert(cpu_state != -3); +#endif + if ((exaddress+1!=address)&&(exaddress+2!=address)&&(exaddress+3!=address)){ + if (cpu_state == 0) { + cpu_state = -3; + longjmp(trap_buf, 1); + } +#if CPU_TYPE == 68000 + else if (cpu_state > 0) { + context |= 0x8; + } + if (ReadWrite) context |= 0x10; +#else + if (ReadWrite) context |= 0x100; +#endif + if (GetS()) context |= 0x4; + if (ReadWrite && address == pc) context |= 0x2; + else context |= 0x1; + cpu_state = 0; /* begin group 0 exception processing */ + SetS (1); + SetT (0); +#if CPU_TYPE == 68010 + reg[15] -= 44; /* Rerun info */ + reg[15] -= 4; SetMemL(reg[15], address); /* fault address */ + reg[15] -= 2; SetMemW(reg[15], context); + reg[15] -= 2; SetMemW(reg[15], 0x8000 | (number * 4)); + reg[15] -= 4; SetMemL(reg[15], GetPC()); + reg[15] -= 2; SetMemW(reg[15], sr); +#else + reg[15] = reg[15] - 14; + SetMemW(reg[15], context); + SetMemL(reg[15] + 2, address); + SetMemW(reg[15] + 6, (uint16)biginst); + SetMemW(reg[15] + 8, sr); + SetMemL(reg[15] + 10, GetPC()); +#endif + + SetPC (GetMemL ((long) number * 4) + vbr); + /* end exception processing */ + cpu_state = -1; + exaddress=address; + + } + int0=1; +} + +void ExceptionGroup1(int number) +{ + + uint32 sp, newpc=pc; + short sr = GetSRW(); + + if (number!=TRAPV) newpc-=2; + SetS(1); + SetT(0); + sp=reg[15]; + sp-=4; SetMemL(sp, newpc); + sp-=2; SetMemW(sp, sr); + reg[15]=sp; + SetPC (GetMemL(number*4+vbr)); + int0=1; +} + +void Interrupt(int number, int level) +{ + uint32 sp; + short sr = GetSRW(); + SetI(level); SetS(1); SetT(0); + sp=reg[15]; + sp-=4; SetMemL(sp, GetPC()); + sp-=2; SetMemW(sp, sr); + reg[15]=sp; + SetPC (GetMemL(number*4+vbr)); +} + +void ExceptionGroup2(int number) +{ + uint32 sp; + short sr = GetSRW(); + SetS(1); SetT(0); + sp=reg[15]; + sp-=4; SetMemL(sp, GetPC()); + sp-=2; SetMemW(sp, sr); + reg[15]=sp; + SetPC (GetMemL(number*4+vbr)); +} + +unsigned long Trace() +{ + uint32 sp; + short sr; + register unsigned long cycleco=0; + register unsigned long address,timeinst; + register int8 *mymembase=membase; + register int8 *myrombase=rombase; + register uint32 myinst; + address = pc&MEMADDRMASK; + // disass=1; + int0=0; + if (address=ROMBASE) myinst=biginst=ReadSL(myrombase+address); + else { ExceptionGroup1(ADDRESSERR); return cycleco; } +#ifdef DISASS + if (disass==1) StoreTrace(); +#endif + pc+=2; + cycleco+=(*jmp_table[(myinst<<16)>>19])(reg); + + if (!int0){ + sr = GetSRW(); + SetS(1); SetT(0); + sp=reg[15]; + sp-=4; SetMemL(sp, GetPC()); + sp-=2; SetMemW(sp, sr); + reg[15]=sp; + SetPC (GetMemL(TRACE*4+vbr)); + return cycleco; + } + return 0; + +} + + +unsigned long IllIns(operin) +{ + ExceptionGroup1(ILLINSTR); + return 0; +} + +unsigned long Line_A(operin) +{ + ExceptionGroup1(LINE_A); + return 0; +} + +unsigned long Line_F(operin) +{ + ExceptionGroup1(LINE_F); + return 0; +} + +unsigned long Stop(void) +{ + if (!GetS()) + ExceptionGroup1(PRIV); + SetSRW(GetMPCW()); + pc += 2; + cpu_state = -2; /* stopped */ + //longjmp(trap_buf, 1); + return 0; +} + +void HWReset(void) +{ + reg[15] = GetMemL (0l); + SetPC(GetMemL (4l)); + SetI(7); + SetT(0); + SetS(1); + cpu_state = -1; /* running */ + cpu_type = CPU_TYPE; +} diff --git a/MCUME_esp32/espcastaway/main/68korig/68000.h b/MCUME_esp32/espcastaway/main/68korig/68000.h new file mode 100755 index 0000000..730b83e --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/68000.h @@ -0,0 +1,187 @@ +/* + * Castaway + * (C) 1994 - 2002 Martin Doering, Joachim Hoenig + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ +#ifndef _68000H +#define _68000H + +#include "config.h" // wg. define +#include "operin.h" + +/* + * Supported CPU types + * CPU CPU_TYPE + * MC68000 68000 + * MC68008 68000 + * MC68EC000 not supported (yet) + * MC68010 68010 + * MC68020 68020 + * MC68EC020 not supported (yet) + * MC68030 not supported (yet) + * MC68EC030 not supported (yet) + * MC68040 not supported (yet) + * MC68EC040 not supported (yet) + * CPU32 not supported (yet) + */ +#define CPU_TYPE 68000 + +/* + * Exception vector numbers (trap numbers). + */ +#define RESET 0 +#define BUSERR 2 +#define ADDRESSERR 3 +#define ILLINSTR 4 +#define DIVZ 5 +#define TRAPCHK 6 +#define TRAPV 7 +#define PRIV 8 +#define TRACE 9 +#define LINE_A 10 +#define LINE_F 11 +#if CPU_TYPE != 68000 +#define FORMATERR 14 +#endif +#define AUTOINT1 25 +#define AUTOINT2 26 +#define AUTOINT3 27 +#define AUTOINT4 28 +#define AUTOINT5 29 +#define AUTOINT6 30 +#define AUTOINT7 31 +#define TRAP0 32 + 0 +#define TRAP1 32 + 1 +#define TRAP2 32 + 2 +#define TRAP3 32 + 3 +#define TRAP4 32 + 4 +#define TRAP5 32 + 5 +#define TRAP6 32 + 6 +#define TRAP7 32 + 7 +#define TRAP8 32 + 8 +#define TRAP9 32 + 9 +#define TRAP10 32 + 10 +#define TRAP11 32 + 11 +#define TRAP12 32 + 12 +#define TRAP13 32 + 13 +#define TRAP14 32 + 14 +#define TRAP15 32 + 15 + +/* Group 0 exceptions (address error / bus error) */ +extern void ExceptionGroup0( + int number, /* trap number */ + unsigned long address, /* fault address */ + int ReadWrite); /* read = true, write = false */ +/* Group 1 exceptions: illegal instruction, privilege violation, interrupts */ +extern void ExceptionGroup1(int number); +extern void Interrupt(int number, int level); +/* Group 2 exceptions: traps, divide by zero */ +extern void ExceptionGroup2(int number); + +extern void HWReset(void); /* Reset */ +extern unsigned long IllIns(operin); /* Illegal instruction */ +extern unsigned long Line_A(operin); /* Axxx instruction opcode */ +extern unsigned long Line_F(operin); /* Fxxx instruction opcode */ +extern unsigned long Stop(void); /* Stop instruction */ + +extern unsigned char tracemode; //For Trace Switching +extern unsigned short SaveWordTrc; +extern unsigned char GetTrc; + +/* + * CPU Registers + * + * WARNING: + * Never access registers directly from outside the emulator. + * The internal representation of registers may change. + */ +/* Data and address registers are stored in native byte order. + * register numbering: 0=d0, 1=d1, ..., 8=a0, 9=a1, ... 15=a7 */ +extern unsigned long reg[23]; +#define biginst reg[18] +#define pc reg[19] +#define usp reg[20] +#define ssp reg[21] +#define recalc_int reg[22] + + +#define ins7 (biginst & 7) +#define ins15 (biginst & 15) + +/* 68010 registers */ +extern unsigned long dfc, sfc, vbr; +/* 68020 registers */ +extern unsigned long caar, cacr, isp, msp; + +extern int intmask; +extern char cpu_state; /* 0, 1, 2 while processing exceptions, + * -1 executing, -2 stopped, -3 shutdown */ +extern unsigned cpu_type; /* 68000, 68010 */ + +/* + * Interrupts + * + * The state of interrupt lines IPL0-IPL2 is stored in the variable + * intpri. The emulator acknowledges interrupts by calling QueryIRQ(). + * It expects the interrupt vector number to be returned. + * WARNING: + * Never update intpri asynchronously. Use the CPUEvent() function + * to force CPURun() to return before updating intpri. + */ +extern int intpri; +extern int QueryIRQ(int level); /* get interrupt vector number */ + +#define GetS() *(((int8*)reg)+70) +#define GetFC2() GetS() +#define GetFC1() address == pc +#define GetFC0() address != pc +#define GetFC() (((GetFC2() << 1) | GetFC1()) << 1) | GetFC0() + +/* + * memory access jump tables + */ +#define MEMADDRMASK 0x00ffffffl +#define MEMADDRMASKS 0x00fffffel +#define MEMIDXSHIFT 11 +#define MEMADDRSIZE (MEMADDRMASK + 1) +#define MEMTABLESIZE (MEMADDRSIZE >> MEMIDXSHIFT) +#define MEMBANKSIZE (MEMADDRSIZE / MEMTABLESIZE) +#define MEMBANKMASK (MEMBANKSIZE - 1) + +/* Fetch byte from address */ +char GetMemB(unsigned long address); +short GetMemW(unsigned long address); +long GetMemL(unsigned long address); +void SetMemB (unsigned long address, unsigned char value); +void SetMemW(unsigned long address, unsigned short value); +void SetMemL(unsigned long address, unsigned long value); +#ifdef DEBUG +extern int stop_on; +extern int verb_on; +/* go to sleep (gives debugger a chance to attach) */ +void DebugStop(void); +#ifdef TRACEBACK +/* + * execution trace + */ +struct state { + uint32 reg[16]; + uint32 stack[8]; + uint32 pc, usp, ssp; + uint16 inst[5]; + uint16 sr; + +}; +extern int hide_supervisor; +extern unsigned long instcnt; +extern int tbi; +extern struct state traceback[TRACEBACK]; +extern int trace_on; +/* print execution trace of last TRACEBACK instructions and sleep */ +void TraceStop(void); +#endif +#endif +#endif + diff --git a/MCUME_esp32/espcastaway/main/68korig/component.mk b/MCUME_esp32/espcastaway/main/68korig/component.mk new file mode 100755 index 0000000..270bfd9 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/component.mk @@ -0,0 +1,14 @@ +# +# Component Makefile +# +# This Makefile can be left empty. By default, it will take the sources in the +# src/ directory, compile them and link them into lib(subdirectory_name).a +# in the build directory. This behaviour is entirely configurable, +# please read the ESP-IDF documents if you need to do this. +# + +COMPONENT_ADD_INCLUDEDIRS := . .. +COMPONENT_SRCDIRS := . + +CPPFLAGS += -DNO_SOUND #-DEMULATED_JOYSTICK -DUSE_SHORT_SLICE -DUSE_DOUBLE_BUFFER +CPPFLAGS += -fpermissive -O3 -ffast-math diff --git a/MCUME_esp32/espcastaway/main/68korig/m68k_intrf.h b/MCUME_esp32/espcastaway/main/68korig/m68k_intrf.h new file mode 100755 index 0000000..677969e --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/m68k_intrf.h @@ -0,0 +1,231 @@ +#include +#include +#include "config.h" +#include "dcastaway.h" + +extern int waitstate; + +#ifndef USE_FAME_CORE + +#include "68000.h" +#include "op68k.h" + +extern unsigned IO_CYCLE; + +static __inline__ unsigned long cpu_loop(unsigned slice) { + +extern const unsigned long (*jmp_table[8192])(operin); + +#define initialize_memmap() + +#define cpuinst \ + address = pc&MEMADDRMASK; \ + if (address=ROMBASE2) myinst=biginst=ReadSL(myrombase+address); \ + else { HWReset(); return slice-IO_CYCLE; } \ + pc+=2; \ + IO_CYCLE-=(*jmp_table[(myinst<<16)>>19])(reg); + + register unsigned long *p_reg=(unsigned long *)®[0]; + register unsigned long address; + register int8 *mymembase=membase; + register int8 *myrombase=rombase; + register uint32 myinst; + IO_CYCLE=slice; + //Execute 10 instructions + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + return slice-IO_CYCLE; +#undef cpuinst +} + + +#else + +#include "fame.h" + + +#if defined(DREAMCAST) || defined(USE_FAME_CORE_C) +#define M68KCONTEXT m68kcontext +#define IO_CYCLE io_cycle_counter +#else +#define M68KCONTEXT _m68kcontext +#define IO_CYCLE __io_cycle_counter +#endif + +extern unsigned IO_CYCLE; + +//extern struct M68K_CONTEXT M68KCONTEXT; +extern M68K_CONTEXT M68KCONTEXT; +extern int recalc_int; +extern void SetMemW(unsigned long address, unsigned short value); +extern void HWReset(void); + +#define GetS() ((M68KCONTEXT.sr >> 13) & 1) +#define GetFC2() GetS() +#define GetI() ((M68KCONTEXT.sr >> 8) & 7) +#ifdef DEBUG_FAME +#define Interrupt(NUM,LEV) \ +{ \ + extern int fame_debug_output; \ + extern FILE *fame_debug_file; \ + if (fame_debug_output) \ + { fprintf(fame_debug_file,"Interrupt(%i,%i)\n",(NUM),(LEV)); DEBUG_FAME_FFLUSH; } \ + m68k_lower_irq((LEV)); \ + m68k_raise_irq((LEV),(NUM)); \ +} +#else +#define Interrupt(NUM,LEV) \ +{ \ + M68KCONTEXT.interrupts[0] |= (1 << (LEV)); \ + M68KCONTEXT.interrupts[(LEV)]=(NUM); \ + M68KCONTEXT.execinfo &= 0x7F; \ +} +#endif + +#define ClearInterrupt(LEV) M68KCONTEXT.interrupts[0] &= ~(1 << (LEV)) + + +#define MEMADDRMASK 0x00ffffffl +#define MEMADDRMASKS 0x00fffffel +#define MEMIDXSHIFT 11 +#define MEMADDRSIZE (MEMADDRMASK + 1) +#define AUTOINT2 26 +#define AUTOINT4 28 +#define BUSERR 2 +#define ADDRESSERR 3 + +char GetMemB(unsigned long address); +short GetMemW(unsigned long address); +void initialize_memmap(void); +void ExceptionGroup0( int, unsigned long, int); +void ExceptionGroup0_execute(void); + + +#ifdef DEBUG_FAME +static char dis_msg[96]; +static unsigned short dis_buf[10]; +void disassemble68k(char *buf, unsigned short *inst_stream); +static __inline__ unsigned long cpu_loop(unsigned slice) +{ + unsigned i; + extern int number_exg0_fame; + extern int in_fame_core; + extern unsigned fame_debug_count; + extern int fame_debug_output; + extern FILE *fame_debug_file; + +#ifdef DEBUG_FAME_START + if (fame_debug_count>=((unsigned)(DEBUG_FAME_START))) + fame_debug_output=1; + else { + unsigned long cycles_actual=M68KCONTEXT.cycles_counter; + short lastint=M68KCONTEXT.sr&0x700; + + in_fame_core=1; + m68k_emulate(slice); + in_fame_core=0; + + fprintf(fame_debug_file,"SLICE(%u) %u (%u) ret=%u (%x %x)\n",slice,fame_debug_count,slice,M68KCONTEXT.cycles_counter-cycles_actual,M68KCONTEXT.execinfo&0x80,M68KCONTEXT.interrupts[0]); + fame_debug_count++; + + if (number_exg0_fame) + ExceptionGroup0_execute(); + + if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700))) + M68KCONTEXT.execinfo&=0x7f; + + return (M68KCONTEXT.cycles_counter-cycles_actual); + } + + if (fame_debug_output) + fprintf(fame_debug_file,"SLICE(%u) %u (%u)\n",slice,fame_debug_count,slice); +#endif + + in_fame_core=1; + unsigned long cycles_actual=M68KCONTEXT.cycles_counter; + short lastint=M68KCONTEXT.sr&0x700; + while(M68KCONTEXT.cycles_counter-cycles_actual((unsigned)(DEBUG_FAME_STOP))) + { +#ifdef DEBUG_FAME_FILE + extern FILE *fame_debug_file; + if (fame_debug_file) + fclose(fame_debug_file); + fame_debug_file=NULL; +#endif + free(malloc(24*1024*1024)); exit(0); } +#endif + if (number_exg0_fame) + { + ExceptionGroup0_execute(); + number_exg0_fame=0; + } + if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700))) + M68KCONTEXT.execinfo&=0x7f; + return (M68KCONTEXT.cycles_counter-cycles_actual); +} + +#else +static __inline__ unsigned long cpu_loop(unsigned slice) +{ + extern int in_fame_core; + extern int number_exg0_fame; + + unsigned long cycles_actual=M68KCONTEXT.cycles_counter; + short lastint=M68KCONTEXT.sr&0x700; + + in_fame_core=1; + m68k_emulate(slice); + in_fame_core=0; + + if (number_exg0_fame) + ExceptionGroup0_execute(); + + if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700))) + M68KCONTEXT.execinfo&=0x7f; + + return (M68KCONTEXT.cycles_counter-cycles_actual); +} +#endif + + +#endif diff --git a/MCUME_esp32/espcastaway/main/68korig/op68000.h b/MCUME_esp32/espcastaway/main/68korig/op68000.h new file mode 100755 index 0000000..098fd46 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/op68000.h @@ -0,0 +1,1066 @@ +#include "operin.h" + +/* + * Castaway + * (C) 1994 - 2002 Martin Doering, Joachim Hoenig + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ +const unsigned long (*jmp_table[8192])(operin) = { + /* 0000 */ + Op0000, IllIns, Op0010, Op0018, Op0020, Op0028, Op0030, Op0038, + Op0040, IllIns, Op0050, Op0058, Op0060, Op0068, Op0070, Op0078, + Op0080, IllIns, Op0090, Op0098, Op00a0, Op00a8, Op00b0, Op00b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0100, Op0108, Op0110, Op0118, Op0120, Op0128, Op0130, Op0138, + Op0140, Op0148, Op0150, Op0158, Op0160, Op0168, Op0170, Op0178, + Op0180, Op0188, Op0190, Op0198, Op01a0, Op01a8, Op01b0, Op01b8, + Op01c0, Op01c8, Op01d0, Op01d8, Op01e0, Op01e8, Op01f0, Op01f8, + Op0200, IllIns, Op0210, Op0218, Op0220, Op0228, Op0230, Op0238, + Op0240, IllIns, Op0250, Op0258, Op0260, Op0268, Op0270, Op0278, + Op0280, IllIns, Op0290, Op0298, Op02a0, Op02a8, Op02b0, Op02b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0300, Op0308, Op0310, Op0318, Op0320, Op0328, Op0330, Op0338, + Op0340, Op0348, Op0350, Op0358, Op0360, Op0368, Op0370, Op0378, + Op0380, Op0388, Op0390, Op0398, Op03a0, Op03a8, Op03b0, Op03b8, + Op03c0, Op03c8, Op03d0, Op03d8, Op03e0, Op03e8, Op03f0, Op03f8, + Op0400, IllIns, Op0410, Op0418, Op0420, Op0428, Op0430, Op0438, + Op0440, IllIns, Op0450, Op0458, Op0460, Op0468, Op0470, Op0478, + Op0480, IllIns, Op0490, Op0498, Op04a0, Op04a8, Op04b0, Op04b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0500, Op0508, Op0510, Op0518, Op0520, Op0528, Op0530, Op0538, + Op0540, Op0548, Op0550, Op0558, Op0560, Op0568, Op0570, Op0578, + Op0580, Op0588, Op0590, Op0598, Op05a0, Op05a8, Op05b0, Op05b8, + Op05c0, Op05c8, Op05d0, Op05d8, Op05e0, Op05e8, Op05f0, Op05f8, + Op0600, IllIns, Op0610, Op0618, Op0620, Op0628, Op0630, Op0638, + Op0640, IllIns, Op0650, Op0658, Op0660, Op0668, Op0670, Op0678, + Op0680, IllIns, Op0690, Op0698, Op06a0, Op06a8, Op06b0, Op06b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0700, Op0708, Op0710, Op0718, Op0720, Op0728, Op0730, Op0738, + Op0740, Op0748, Op0750, Op0758, Op0760, Op0768, Op0770, Op0778, + Op0780, Op0788, Op0790, Op0798, Op07a0, Op07a8, Op07b0, Op07b8, + Op07c0, Op07c8, Op07d0, Op07d8, Op07e0, Op07e8, Op07f0, Op07f8, + Op0800, IllIns, Op0810, Op0818, Op0820, Op0828, Op0830, Op0838, + Op0840, IllIns, Op0850, Op0858, Op0860, Op0868, Op0870, Op0878, + Op0880, IllIns, Op0890, Op0898, Op08a0, Op08a8, Op08b0, Op08b8, + Op08c0, IllIns, Op08d0, Op08d8, Op08e0, Op08e8, Op08f0, Op08f8, + Op0900, Op0908, Op0910, Op0918, Op0920, Op0928, Op0930, Op0938, + Op0940, Op0948, Op0950, Op0958, Op0960, Op0968, Op0970, Op0978, + Op0980, Op0988, Op0990, Op0998, Op09a0, Op09a8, Op09b0, Op09b8, + Op09c0, Op09c8, Op09d0, Op09d8, Op09e0, Op09e8, Op09f0, Op09f8, + Op0a00, IllIns, Op0a10, Op0a18, Op0a20, Op0a28, Op0a30, Op0a38, + Op0a40, IllIns, Op0a50, Op0a58, Op0a60, Op0a68, Op0a70, Op0a78, + Op0a80, IllIns, Op0a90, Op0a98, Op0aa0, Op0aa8, Op0ab0, Op0ab8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0b00, Op0b08, Op0b10, Op0b18, Op0b20, Op0b28, Op0b30, Op0b38, + Op0b40, Op0b48, Op0b50, Op0b58, Op0b60, Op0b68, Op0b70, Op0b78, + Op0b80, Op0b88, Op0b90, Op0b98, Op0ba0, Op0ba8, Op0bb0, Op0bb8, + Op0bc0, Op0bc8, Op0bd0, Op0bd8, Op0be0, Op0be8, Op0bf0, Op0bf8, + Op0c00, IllIns, Op0c10, Op0c18, Op0c20, Op0c28, Op0c30, Op0c38, + Op0c40, IllIns, Op0c50, Op0c58, Op0c60, Op0c68, Op0c70, Op0c78, + Op0c80, IllIns, Op0c90, Op0c98, Op0ca0, Op0ca8, Op0cb0, Op0cb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0d00, Op0d08, Op0d10, Op0d18, Op0d20, Op0d28, Op0d30, Op0d38, + Op0d40, Op0d48, Op0d50, Op0d58, Op0d60, Op0d68, Op0d70, Op0d78, + Op0d80, Op0d88, Op0d90, Op0d98, Op0da0, Op0da8, Op0db0, Op0db8, + Op0dc0, Op0dc8, Op0dd0, Op0dd8, Op0de0, Op0de8, Op0df0, Op0df8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0f00, Op0f08, Op0f10, Op0f18, Op0f20, Op0f28, Op0f30, Op0f38, + Op0f40, Op0f48, Op0f50, Op0f58, Op0f60, Op0f68, Op0f70, Op0f78, + Op0f80, Op0f88, Op0f90, Op0f98, Op0fa0, Op0fa8, Op0fb0, Op0fb8, + Op0fc0, Op0fc8, Op0fd0, Op0fd8, Op0fe0, Op0fe8, Op0ff0, Op0ff8, + + /* 1000 */ + Op1000, IllIns, Op1010, Op1018, Op1020, Op1028, Op1030, Op1038, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1080, IllIns, Op1090, Op1098, Op10a0, Op10a8, Op10b0, Op10b8, + Op10c0, IllIns, Op10d0, Op10d8, Op10e0, Op10e8, Op10f0, Op10f8, + Op1100, IllIns, Op1110, Op1118, Op1120, Op1128, Op1130, Op1138, + Op1140, IllIns, Op1150, Op1158, Op1160, Op1168, Op1170, Op1178, + Op1180, IllIns, Op1190, Op1198, Op11a0, Op11a8, Op11b0, Op11b8, + Op11c0, IllIns, Op11d0, Op11d8, Op11e0, Op11e8, Op11f0, Op11f8, + Op1200, IllIns, Op1210, Op1218, Op1220, Op1228, Op1230, Op1238, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1280, IllIns, Op1290, Op1298, Op12a0, Op12a8, Op12b0, Op12b8, + Op12c0, IllIns, Op12d0, Op12d8, Op12e0, Op12e8, Op12f0, Op12f8, + Op1300, IllIns, Op1310, Op1318, Op1320, Op1328, Op1330, Op1338, + Op1340, IllIns, Op1350, Op1358, Op1360, Op1368, Op1370, Op1378, + Op1380, IllIns, Op1390, Op1398, Op13a0, Op13a8, Op13b0, Op13b8, + Op13c0, IllIns, Op13d0, Op13d8, Op13e0, Op13e8, Op13f0, Op13f8, + Op1400, IllIns, Op1410, Op1418, Op1420, Op1428, Op1430, Op1438, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1480, IllIns, Op1490, Op1498, Op14a0, Op14a8, Op14b0, Op14b8, + Op14c0, IllIns, Op14d0, Op14d8, Op14e0, Op14e8, Op14f0, Op14f8, + Op1500, IllIns, Op1510, Op1518, Op1520, Op1528, Op1530, Op1538, + Op1540, IllIns, Op1550, Op1558, Op1560, Op1568, Op1570, Op1578, + Op1580, IllIns, Op1590, Op1598, Op15a0, Op15a8, Op15b0, Op15b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1600, IllIns, Op1610, Op1618, Op1620, Op1628, Op1630, Op1638, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1680, IllIns, Op1690, Op1698, Op16a0, Op16a8, Op16b0, Op16b8, + Op16c0, IllIns, Op16d0, Op16d8, Op16e0, Op16e8, Op16f0, Op16f8, + Op1700, IllIns, Op1710, Op1718, Op1720, Op1728, Op1730, Op1738, + Op1740, IllIns, Op1750, Op1758, Op1760, Op1768, Op1770, Op1778, + Op1780, IllIns, Op1790, Op1798, Op17a0, Op17a8, Op17b0, Op17b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1800, IllIns, Op1810, Op1818, Op1820, Op1828, Op1830, Op1838, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1880, IllIns, Op1890, Op1898, Op18a0, Op18a8, Op18b0, Op18b8, + Op18c0, IllIns, Op18d0, Op18d8, Op18e0, Op18e8, Op18f0, Op18f8, + Op1900, IllIns, Op1910, Op1918, Op1920, Op1928, Op1930, Op1938, + Op1940, IllIns, Op1950, Op1958, Op1960, Op1968, Op1970, Op1978, + Op1980, IllIns, Op1990, Op1998, Op19a0, Op19a8, Op19b0, Op19b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1a00, IllIns, Op1a10, Op1a18, Op1a20, Op1a28, Op1a30, Op1a38, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1a80, IllIns, Op1a90, Op1a98, Op1aa0, Op1aa8, Op1ab0, Op1ab8, + Op1ac0, IllIns, Op1ad0, Op1ad8, Op1ae0, Op1ae8, Op1af0, Op1af8, + Op1b00, IllIns, Op1b10, Op1b18, Op1b20, Op1b28, Op1b30, Op1b38, + Op1b40, IllIns, Op1b50, Op1b58, Op1b60, Op1b68, Op1b70, Op1b78, + Op1b80, IllIns, Op1b90, Op1b98, Op1ba0, Op1ba8, Op1bb0, Op1bb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1c00, IllIns, Op1c10, Op1c18, Op1c20, Op1c28, Op1c30, Op1c38, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1c80, IllIns, Op1c90, Op1c98, Op1ca0, Op1ca8, Op1cb0, Op1cb8, + Op1cc0, IllIns, Op1cd0, Op1cd8, Op1ce0, Op1ce8, Op1cf0, Op1cf8, + Op1d00, IllIns, Op1d10, Op1d18, Op1d20, Op1d28, Op1d30, Op1d38, + Op1d40, IllIns, Op1d50, Op1d58, Op1d60, Op1d68, Op1d70, Op1d78, + Op1d80, IllIns, Op1d90, Op1d98, Op1da0, Op1da8, Op1db0, Op1db8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1e00, IllIns, Op1e10, Op1e18, Op1e20, Op1e28, Op1e30, Op1e38, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1e80, IllIns, Op1e90, Op1e98, Op1ea0, Op1ea8, Op1eb0, Op1eb8, + Op1ec0, IllIns, Op1ed0, Op1ed8, Op1ee0, Op1ee8, Op1ef0, Op1ef8, + Op1f00, IllIns, Op1f10, Op1f18, Op1f20, Op1f28, Op1f30, Op1f38, + Op1f40, IllIns, Op1f50, Op1f58, Op1f60, Op1f68, Op1f70, Op1f78, + Op1f80, IllIns, Op1f90, Op1f98, Op1fa0, Op1fa8, Op1fb0, Op1fb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 2000 */ + Op2000, Op2008, Op2010, Op2018, Op2020, Op2028, Op2030, Op2038, + Op2040, Op2048, Op2050, Op2058, Op2060, Op2068, Op2070, Op2078, + Op2080, Op2088, Op2090, Op2098, Op20a0, Op20a8, Op20b0, Op20b8, + Op20c0, Op20c8, Op20d0, Op20d8, Op20e0, Op20e8, Op20f0, Op20f8, + Op2100, Op2108, Op2110, Op2118, Op2120, Op2128, Op2130, Op2138, + Op2140, Op2148, Op2150, Op2158, Op2160, Op2168, Op2170, Op2178, + Op2180, Op2188, Op2190, Op2198, Op21a0, Op21a8, Op21b0, Op21b8, + Op21c0, Op21c8, Op21d0, Op21d8, Op21e0, Op21e8, Op21f0, Op21f8, + Op2200, Op2208, Op2210, Op2218, Op2220, Op2228, Op2230, Op2238, + Op2240, Op2248, Op2250, Op2258, Op2260, Op2268, Op2270, Op2278, + Op2280, Op2288, Op2290, Op2298, Op22a0, Op22a8, Op22b0, Op22b8, + Op22c0, Op22c8, Op22d0, Op22d8, Op22e0, Op22e8, Op22f0, Op22f8, + Op2300, Op2308, Op2310, Op2318, Op2320, Op2328, Op2330, Op2338, + Op2340, Op2348, Op2350, Op2358, Op2360, Op2368, Op2370, Op2378, + Op2380, Op2388, Op2390, Op2398, Op23a0, Op23a8, Op23b0, Op23b8, + Op23c0, Op23c8, Op23d0, Op23d8, Op23e0, Op23e8, Op23f0, Op23f8, + Op2400, Op2408, Op2410, Op2418, Op2420, Op2428, Op2430, Op2438, + Op2440, Op2448, Op2450, Op2458, Op2460, Op2468, Op2470, Op2478, + Op2480, Op2488, Op2490, Op2498, Op24a0, Op24a8, Op24b0, Op24b8, + Op24c0, Op24c8, Op24d0, Op24d8, Op24e0, Op24e8, Op24f0, Op24f8, + Op2500, Op2508, Op2510, Op2518, Op2520, Op2528, Op2530, Op2538, + Op2540, Op2548, Op2550, Op2558, Op2560, Op2568, Op2570, Op2578, + Op2580, Op2588, Op2590, Op2598, Op25a0, Op25a8, Op25b0, Op25b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2600, Op2608, Op2610, Op2618, Op2620, Op2628, Op2630, Op2638, + Op2640, Op2648, Op2650, Op2658, Op2660, Op2668, Op2670, Op2678, + Op2680, Op2688, Op2690, Op2698, Op26a0, Op26a8, Op26b0, Op26b8, + Op26c0, Op26c8, Op26d0, Op26d8, Op26e0, Op26e8, Op26f0, Op26f8, + Op2700, Op2708, Op2710, Op2718, Op2720, Op2728, Op2730, Op2738, + Op2740, Op2748, Op2750, Op2758, Op2760, Op2768, Op2770, Op2778, + Op2780, Op2788, Op2790, Op2798, Op27a0, Op27a8, Op27b0, Op27b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2800, Op2808, Op2810, Op2818, Op2820, Op2828, Op2830, Op2838, + Op2840, Op2848, Op2850, Op2858, Op2860, Op2868, Op2870, Op2878, + Op2880, Op2888, Op2890, Op2898, Op28a0, Op28a8, Op28b0, Op28b8, + Op28c0, Op28c8, Op28d0, Op28d8, Op28e0, Op28e8, Op28f0, Op28f8, + Op2900, Op2908, Op2910, Op2918, Op2920, Op2928, Op2930, Op2938, + Op2940, Op2948, Op2950, Op2958, Op2960, Op2968, Op2970, Op2978, + Op2980, Op2988, Op2990, Op2998, Op29a0, Op29a8, Op29b0, Op29b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2a00, Op2a08, Op2a10, Op2a18, Op2a20, Op2a28, Op2a30, Op2a38, + Op2a40, Op2a48, Op2a50, Op2a58, Op2a60, Op2a68, Op2a70, Op2a78, + Op2a80, Op2a88, Op2a90, Op2a98, Op2aa0, Op2aa8, Op2ab0, Op2ab8, + Op2ac0, Op2ac8, Op2ad0, Op2ad8, Op2ae0, Op2ae8, Op2af0, Op2af8, + Op2b00, Op2b08, Op2b10, Op2b18, Op2b20, Op2b28, Op2b30, Op2b38, + Op2b40, Op2b48, Op2b50, Op2b58, Op2b60, Op2b68, Op2b70, Op2b78, + Op2b80, Op2b88, Op2b90, Op2b98, Op2ba0, Op2ba8, Op2bb0, Op2bb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2c00, Op2c08, Op2c10, Op2c18, Op2c20, Op2c28, Op2c30, Op2c38, + Op2c40, Op2c48, Op2c50, Op2c58, Op2c60, Op2c68, Op2c70, Op2c78, + Op2c80, Op2c88, Op2c90, Op2c98, Op2ca0, Op2ca8, Op2cb0, Op2cb8, + Op2cc0, Op2cc8, Op2cd0, Op2cd8, Op2ce0, Op2ce8, Op2cf0, Op2cf8, + Op2d00, Op2d08, Op2d10, Op2d18, Op2d20, Op2d28, Op2d30, Op2d38, + Op2d40, Op2d48, Op2d50, Op2d58, Op2d60, Op2d68, Op2d70, Op2d78, + Op2d80, Op2d88, Op2d90, Op2d98, Op2da0, Op2da8, Op2db0, Op2db8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2e00, Op2e08, Op2e10, Op2e18, Op2e20, Op2e28, Op2e30, Op2e38, + Op2e40, Op2e48, Op2e50, Op2e58, Op2e60, Op2e68, Op2e70, Op2e78, + Op2e80, Op2e88, Op2e90, Op2e98, Op2ea0, Op2ea8, Op2eb0, Op2eb8, + Op2ec0, Op2ec8, Op2ed0, Op2ed8, Op2ee0, Op2ee8, Op2ef0, Op2ef8, + Op2f00, Op2f08, Op2f10, Op2f18, Op2f20, Op2f28, Op2f30, Op2f38, + Op2f40, Op2f48, Op2f50, Op2f58, Op2f60, Op2f68, Op2f70, Op2f78, + Op2f80, Op2f88, Op2f90, Op2f98, Op2fa0, Op2fa8, Op2fb0, Op2fb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 3000 */ + Op3000, Op3008, Op3010, Op3018, Op3020, Op3028, Op3030, Op3038, + Op3040, Op3048, Op3050, Op3058, Op3060, Op3068, Op3070, Op3078, + Op3080, Op3088, Op3090, Op3098, Op30a0, Op30a8, Op30b0, Op30b8, + Op30c0, Op30c8, Op30d0, Op30d8, Op30e0, Op30e8, Op30f0, Op30f8, + Op3100, Op3108, Op3110, Op3118, Op3120, Op3128, Op3130, Op3138, + Op3140, Op3148, Op3150, Op3158, Op3160, Op3168, Op3170, Op3178, + Op3180, Op3188, Op3190, Op3198, Op31a0, Op31a8, Op31b0, Op31b8, + Op31c0, Op31c8, Op31d0, Op31d8, Op31e0, Op31e8, Op31f0, Op31f8, + Op3200, Op3208, Op3210, Op3218, Op3220, Op3228, Op3230, Op3238, + Op3240, Op3248, Op3250, Op3258, Op3260, Op3268, Op3270, Op3278, + Op3280, Op3288, Op3290, Op3298, Op32a0, Op32a8, Op32b0, Op32b8, + Op32c0, Op32c8, Op32d0, Op32d8, Op32e0, Op32e8, Op32f0, Op32f8, + Op3300, Op3308, Op3310, Op3318, Op3320, Op3328, Op3330, Op3338, + Op3340, Op3348, Op3350, Op3358, Op3360, Op3368, Op3370, Op3378, + Op3380, Op3388, Op3390, Op3398, Op33a0, Op33a8, Op33b0, Op33b8, + Op33c0, Op33c8, Op33d0, Op33d8, Op33e0, Op33e8, Op33f0, Op33f8, + Op3400, Op3408, Op3410, Op3418, Op3420, Op3428, Op3430, Op3438, + Op3440, Op3448, Op3450, Op3458, Op3460, Op3468, Op3470, Op3478, + Op3480, Op3488, Op3490, Op3498, Op34a0, Op34a8, Op34b0, Op34b8, + Op34c0, Op34c8, Op34d0, Op34d8, Op34e0, Op34e8, Op34f0, Op34f8, + Op3500, Op3508, Op3510, Op3518, Op3520, Op3528, Op3530, Op3538, + Op3540, Op3548, Op3550, Op3558, Op3560, Op3568, Op3570, Op3578, + Op3580, Op3588, Op3590, Op3598, Op35a0, Op35a8, Op35b0, Op35b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3600, Op3608, Op3610, Op3618, Op3620, Op3628, Op3630, Op3638, + Op3640, Op3648, Op3650, Op3658, Op3660, Op3668, Op3670, Op3678, + Op3680, Op3688, Op3690, Op3698, Op36a0, Op36a8, Op36b0, Op36b8, + Op36c0, Op36c8, Op36d0, Op36d8, Op36e0, Op36e8, Op36f0, Op36f8, + Op3700, Op3708, Op3710, Op3718, Op3720, Op3728, Op3730, Op3738, + Op3740, Op3748, Op3750, Op3758, Op3760, Op3768, Op3770, Op3778, + Op3780, Op3788, Op3790, Op3798, Op37a0, Op37a8, Op37b0, Op37b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3800, Op3808, Op3810, Op3818, Op3820, Op3828, Op3830, Op3838, + Op3840, Op3848, Op3850, Op3858, Op3860, Op3868, Op3870, Op3878, + Op3880, Op3888, Op3890, Op3898, Op38a0, Op38a8, Op38b0, Op38b8, + Op38c0, Op38c8, Op38d0, Op38d8, Op38e0, Op38e8, Op38f0, Op38f8, + Op3900, Op3908, Op3910, Op3918, Op3920, Op3928, Op3930, Op3938, + Op3940, Op3948, Op3950, Op3958, Op3960, Op3968, Op3970, Op3978, + Op3980, Op3988, Op3990, Op3998, Op39a0, Op39a8, Op39b0, Op39b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3a00, Op3a08, Op3a10, Op3a18, Op3a20, Op3a28, Op3a30, Op3a38, + Op3a40, Op3a48, Op3a50, Op3a58, Op3a60, Op3a68, Op3a70, Op3a78, + Op3a80, Op3a88, Op3a90, Op3a98, Op3aa0, Op3aa8, Op3ab0, Op3ab8, + Op3ac0, Op3ac8, Op3ad0, Op3ad8, Op3ae0, Op3ae8, Op3af0, Op3af8, + Op3b00, Op3b08, Op3b10, Op3b18, Op3b20, Op3b28, Op3b30, Op3b38, + Op3b40, Op3b48, Op3b50, Op3b58, Op3b60, Op3b68, Op3b70, Op3b78, + Op3b80, Op3b88, Op3b90, Op3b98, Op3ba0, Op3ba8, Op3bb0, Op3bb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3c00, Op3c08, Op3c10, Op3c18, Op3c20, Op3c28, Op3c30, Op3c38, + Op3c40, Op3c48, Op3c50, Op3c58, Op3c60, Op3c68, Op3c70, Op3c78, + Op3c80, Op3c88, Op3c90, Op3c98, Op3ca0, Op3ca8, Op3cb0, Op3cb8, + Op3cc0, Op3cc8, Op3cd0, Op3cd8, Op3ce0, Op3ce8, Op3cf0, Op3cf8, + Op3d00, Op3d08, Op3d10, Op3d18, Op3d20, Op3d28, Op3d30, Op3d38, + Op3d40, Op3d48, Op3d50, Op3d58, Op3d60, Op3d68, Op3d70, Op3d78, + Op3d80, Op3d88, Op3d90, Op3d98, Op3da0, Op3da8, Op3db0, Op3db8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3e00, Op3e08, Op3e10, Op3e18, Op3e20, Op3e28, Op3e30, Op3e38, + Op3e40, Op3e48, Op3e50, Op3e58, Op3e60, Op3e68, Op3e70, Op3e78, + Op3e80, Op3e88, Op3e90, Op3e98, Op3ea0, Op3ea8, Op3eb0, Op3eb8, + Op3ec0, Op3ec8, Op3ed0, Op3ed8, Op3ee0, Op3ee8, Op3ef0, Op3ef8, + Op3f00, Op3f08, Op3f10, Op3f18, Op3f20, Op3f28, Op3f30, Op3f38, + Op3f40, Op3f48, Op3f50, Op3f58, Op3f60, Op3f68, Op3f70, Op3f78, + Op3f80, Op3f88, Op3f90, Op3f98, Op3fa0, Op3fa8, Op3fb0, Op3fb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 4000 */ + Op4000, IllIns, Op4010, Op4018, Op4020, Op4028, Op4030, Op4038, + Op4040, IllIns, Op4050, Op4058, Op4060, Op4068, Op4070, Op4078, + Op4080, IllIns, Op4090, Op4098, Op40a0, Op40a8, Op40b0, Op40b8, + Op40c0, IllIns, Op40d0, Op40d8, Op40e0, Op40e8, Op40f0, Op40f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4180, IllIns, Op4190, Op4198, Op41a0, Op41a8, Op41b0, Op41b8, + IllIns, IllIns, Op41d0, IllIns, IllIns, Op41e8, Op41f0, Op41f8, + Op4200, IllIns, Op4210, Op4218, Op4220, Op4228, Op4230, Op4238, + Op4240, IllIns, Op4250, Op4258, Op4260, Op4268, Op4270, Op4278, + Op4280, IllIns, Op4290, Op4298, Op42a0, Op42a8, Op42b0, Op42b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4380, IllIns, Op4390, Op4398, Op43a0, Op43a8, Op43b0, Op43b8, + IllIns, IllIns, Op43d0, IllIns, IllIns, Op43e8, Op43f0, Op43f8, + Op4400, IllIns, Op4410, Op4418, Op4420, Op4428, Op4430, Op4438, + Op4440, IllIns, Op4450, Op4458, Op4460, Op4468, Op4470, Op4478, + Op4480, IllIns, Op4490, Op4498, Op44a0, Op44a8, Op44b0, Op44b8, + Op44c0, IllIns, Op44d0, Op44d8, Op44e0, Op44e8, Op44f0, Op44f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4580, IllIns, Op4590, Op4598, Op45a0, Op45a8, Op45b0, Op45b8, + IllIns, IllIns, Op45d0, IllIns, IllIns, Op45e8, Op45f0, Op45f8, + Op4600, IllIns, Op4610, Op4618, Op4620, Op4628, Op4630, Op4638, + Op4640, IllIns, Op4650, Op4658, Op4660, Op4668, Op4670, Op4678, + Op4680, IllIns, Op4690, Op4698, Op46a0, Op46a8, Op46b0, Op46b8, + Op46c0, IllIns, Op46d0, Op46d8, Op46e0, Op46e8, Op46f0, Op46f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4780, IllIns, Op4790, Op4798, Op47a0, Op47a8, Op47b0, Op47b8, + IllIns, IllIns, Op47d0, IllIns, IllIns, Op47e8, Op47f0, Op47f8, + Op4800, IllIns, Op4810, Op4818, Op4820, Op4828, Op4830, Op4838, + Op4840, IllIns, Op4850, IllIns, IllIns, Op4868, Op4870, Op4878, + Op4880, IllIns, Op4890, IllIns, Op48a0, Op48a8, Op48b0, Op48b8, + Op48c0, IllIns, Op48d0, IllIns, Op48e0, Op48e8, Op48f0, Op48f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4980, IllIns, Op4990, Op4998, Op49a0, Op49a8, Op49b0, Op49b8, + IllIns, IllIns, Op49d0, IllIns, IllIns, Op49e8, Op49f0, Op49f8, + Op4a00, IllIns, Op4a10, Op4a18, Op4a20, Op4a28, Op4a30, Op4a38, + Op4a40, IllIns, Op4a50, Op4a58, Op4a60, Op4a68, Op4a70, Op4a78, + Op4a80, IllIns, Op4a90, Op4a98, Op4aa0, Op4aa8, Op4ab0, Op4ab8, + Op4ac0, IllIns, Op4ad0, Op4ad8, Op4ae0, Op4ae8, Op4af0, Op4af8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4b80, IllIns, Op4b90, Op4b98, Op4ba0, Op4ba8, Op4bb0, Op4bb8, + IllIns, IllIns, Op4bd0, IllIns, IllIns, Op4be8, Op4bf0, Op4bf8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, Op4c90, Op4c98, IllIns, Op4ca8, Op4cb0, Op4cb8, + IllIns, IllIns, Op4cd0, Op4cd8, IllIns, Op4ce8, Op4cf0, Op4cf8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4d80, IllIns, Op4d90, Op4d98, Op4da0, Op4da8, Op4db0, Op4db8, + IllIns, IllIns, Op4dd0, IllIns, IllIns, Op4de8, Op4df0, Op4df8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, // Special Instruction to Switch Trace mode + Op4e40, Op4e40, Op4e50, Op4e58, Op4e60, Op4e68, Op4e70, IllIns, + IllIns, IllIns, Op4e90, IllIns, IllIns, Op4ea8, Op4eb0, Op4eb8, + IllIns, IllIns, Op4ed0, IllIns, IllIns, Op4ee8, Op4ef0, Op4ef8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4f80, IllIns, Op4f90, Op4f98, Op4fa0, Op4fa8, Op4fb0, Op4fb8, + IllIns, IllIns, Op4fd0, IllIns, IllIns, Op4fe8, Op4ff0, Op4ff8, + + /* 5000 */ + Op5000, IllIns, Op5010, Op5018, Op5020, Op5028, Op5030, Op5038, + Op5040, Op5048, Op5050, Op5058, Op5060, Op5068, Op5070, Op5078, + Op5080, Op5088, Op5090, Op5098, Op50a0, Op50a8, Op50b0, Op50b8, + Op50c0, Op50c8, Op50d0, Op50d8, Op50e0, Op50e8, Op50f0, Op50f8, + Op5100, IllIns, Op5110, Op5118, Op5120, Op5128, Op5130, Op5138, + Op5140, Op5148, Op5150, Op5158, Op5160, Op5168, Op5170, Op5178, + Op5180, Op5188, Op5190, Op5198, Op51a0, Op51a8, Op51b0, Op51b8, + Op51c0, Op51c8, Op51d0, Op51d8, Op51e0, Op51e8, Op51f0, Op51f8, + Op5200, IllIns, Op5210, Op5218, Op5220, Op5228, Op5230, Op5238, + Op5240, Op5248, Op5250, Op5258, Op5260, Op5268, Op5270, Op5278, + Op5280, Op5288, Op5290, Op5298, Op52a0, Op52a8, Op52b0, Op52b8, + Op52c0, Op52c8, Op52d0, Op52d8, Op52e0, Op52e8, Op52f0, Op52f8, + Op5300, IllIns, Op5310, Op5318, Op5320, Op5328, Op5330, Op5338, + Op5340, Op5348, Op5350, Op5358, Op5360, Op5368, Op5370, Op5378, + Op5380, Op5388, Op5390, Op5398, Op53a0, Op53a8, Op53b0, Op53b8, + Op53c0, Op53c8, Op53d0, Op53d8, Op53e0, Op53e8, Op53f0, Op53f8, + Op5400, IllIns, Op5410, Op5418, Op5420, Op5428, Op5430, Op5438, + Op5440, Op5448, Op5450, Op5458, Op5460, Op5468, Op5470, Op5478, + Op5480, Op5488, Op5490, Op5498, Op54a0, Op54a8, Op54b0, Op54b8, + Op54c0, Op54c8, Op54d0, Op54d8, Op54e0, Op54e8, Op54f0, Op54f8, + Op5500, IllIns, Op5510, Op5518, Op5520, Op5528, Op5530, Op5538, + Op5540, Op5548, Op5550, Op5558, Op5560, Op5568, Op5570, Op5578, + Op5580, Op5588, Op5590, Op5598, Op55a0, Op55a8, Op55b0, Op55b8, + Op55c0, Op55c8, Op55d0, Op55d8, Op55e0, Op55e8, Op55f0, Op55f8, + Op5600, IllIns, Op5610, Op5618, Op5620, Op5628, Op5630, Op5638, + Op5640, Op5648, Op5650, Op5658, Op5660, Op5668, Op5670, Op5678, + Op5680, Op5688, Op5690, Op5698, Op56a0, Op56a8, Op56b0, Op56b8, + Op56c0, Op56c8, Op56d0, Op56d8, Op56e0, Op56e8, Op56f0, Op56f8, + Op5700, IllIns, Op5710, Op5718, Op5720, Op5728, Op5730, Op5738, + Op5740, Op5748, Op5750, Op5758, Op5760, Op5768, Op5770, Op5778, + Op5780, Op5788, Op5790, Op5798, Op57a0, Op57a8, Op57b0, Op57b8, + Op57c0, Op57c8, Op57d0, Op57d8, Op57e0, Op57e8, Op57f0, Op57f8, + Op5800, IllIns, Op5810, Op5818, Op5820, Op5828, Op5830, Op5838, + Op5840, Op5848, Op5850, Op5858, Op5860, Op5868, Op5870, Op5878, + Op5880, Op5888, Op5890, Op5898, Op58a0, Op58a8, Op58b0, Op58b8, + Op58c0, Op58c8, Op58d0, Op58d8, Op58e0, Op58e8, Op58f0, Op58f8, + Op5900, IllIns, Op5910, Op5918, Op5920, Op5928, Op5930, Op5938, + Op5940, Op5948, Op5950, Op5958, Op5960, Op5968, Op5970, Op5978, + Op5980, Op5988, Op5990, Op5998, Op59a0, Op59a8, Op59b0, Op59b8, + Op59c0, Op59c8, Op59d0, Op59d8, Op59e0, Op59e8, Op59f0, Op59f8, + Op5a00, IllIns, Op5a10, Op5a18, Op5a20, Op5a28, Op5a30, Op5a38, + Op5a40, Op5a48, Op5a50, Op5a58, Op5a60, Op5a68, Op5a70, Op5a78, + Op5a80, Op5a88, Op5a90, Op5a98, Op5aa0, Op5aa8, Op5ab0, Op5ab8, + Op5ac0, Op5ac8, Op5ad0, Op5ad8, Op5ae0, Op5ae8, Op5af0, Op5af8, + Op5b00, IllIns, Op5b10, Op5b18, Op5b20, Op5b28, Op5b30, Op5b38, + Op5b40, Op5b48, Op5b50, Op5b58, Op5b60, Op5b68, Op5b70, Op5b78, + Op5b80, Op5b88, Op5b90, Op5b98, Op5ba0, Op5ba8, Op5bb0, Op5bb8, + Op5bc0, Op5bc8, Op5bd0, Op5bd8, Op5be0, Op5be8, Op5bf0, Op5bf8, + Op5c00, IllIns, Op5c10, Op5c18, Op5c20, Op5c28, Op5c30, Op5c38, + Op5c40, Op5c48, Op5c50, Op5c58, Op5c60, Op5c68, Op5c70, Op5c78, + Op5c80, Op5c88, Op5c90, Op5c98, Op5ca0, Op5ca8, Op5cb0, Op5cb8, + Op5cc0, Op5cc8, Op5cd0, Op5cd8, Op5ce0, Op5ce8, Op5cf0, Op5cf8, + Op5d00, IllIns, Op5d10, Op5d18, Op5d20, Op5d28, Op5d30, Op5d38, + Op5d40, Op5d48, Op5d50, Op5d58, Op5d60, Op5d68, Op5d70, Op5d78, + Op5d80, Op5d88, Op5d90, Op5d98, Op5da0, Op5da8, Op5db0, Op5db8, + Op5dc0, Op5dc8, Op5dd0, Op5dd8, Op5de0, Op5de8, Op5df0, Op5df8, + Op5e00, IllIns, Op5e10, Op5e18, Op5e20, Op5e28, Op5e30, Op5e38, + Op5e40, Op5e48, Op5e50, Op5e58, Op5e60, Op5e68, Op5e70, Op5e78, + Op5e80, Op5e88, Op5e90, Op5e98, Op5ea0, Op5ea8, Op5eb0, Op5eb8, + Op5ec0, Op5ec8, Op5ed0, Op5ed8, Op5ee0, Op5ee8, Op5ef0, Op5ef8, + Op5f00, IllIns, Op5f10, Op5f18, Op5f20, Op5f28, Op5f30, Op5f38, + Op5f40, Op5f48, Op5f50, Op5f58, Op5f60, Op5f68, Op5f70, Op5f78, + Op5f80, Op5f88, Op5f90, Op5f98, Op5fa0, Op5fa8, Op5fb0, Op5fb8, + Op5fc0, Op5fc8, Op5fd0, Op5fd8, Op5fe0, Op5fe8, Op5ff0, Op5ff8, + + /* 6000 */ + Op6000, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6100, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6200, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6300, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6400, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6500, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6600, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6700, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6800, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6900, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6a00, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6b00, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6c00, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6d00, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6e00, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6f00, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + + /* 7000 */ + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 8000 */ + Op8000, IllIns, Op8010, Op8018, Op8020, Op8028, Op8030, Op8038, + Op8040, IllIns, Op8050, Op8058, Op8060, Op8068, Op8070, Op8078, + Op8080, IllIns, Op8090, Op8098, Op80a0, Op80a8, Op80b0, Op80b8, + Op80c0, IllIns, Op80d0, Op80d8, Op80e0, Op80e8, Op80f0, Op80f8, + Op8100, Op8108, Op8110, Op8118, Op8120, Op8128, Op8130, Op8138, + IllIns, IllIns, Op8150, Op8158, Op8160, Op8168, Op8170, Op8178, + IllIns, IllIns, Op8190, Op8198, Op81a0, Op81a8, Op81b0, Op81b8, + Op81c0, IllIns, Op81d0, Op81d8, Op81e0, Op81e8, Op81f0, Op81f8, + Op8200, IllIns, Op8210, Op8218, Op8220, Op8228, Op8230, Op8238, + Op8240, IllIns, Op8250, Op8258, Op8260, Op8268, Op8270, Op8278, + Op8280, IllIns, Op8290, Op8298, Op82a0, Op82a8, Op82b0, Op82b8, + Op82c0, IllIns, Op82d0, Op82d8, Op82e0, Op82e8, Op82f0, Op82f8, + Op8300, Op8308, Op8310, Op8318, Op8320, Op8328, Op8330, Op8338, + IllIns, IllIns, Op8350, Op8358, Op8360, Op8368, Op8370, Op8378, + IllIns, IllIns, Op8390, Op8398, Op83a0, Op83a8, Op83b0, Op83b8, + Op83c0, IllIns, Op83d0, Op83d8, Op83e0, Op83e8, Op83f0, Op83f8, + Op8400, IllIns, Op8410, Op8418, Op8420, Op8428, Op8430, Op8438, + Op8440, IllIns, Op8450, Op8458, Op8460, Op8468, Op8470, Op8478, + Op8480, IllIns, Op8490, Op8498, Op84a0, Op84a8, Op84b0, Op84b8, + Op84c0, IllIns, Op84d0, Op84d8, Op84e0, Op84e8, Op84f0, Op84f8, + Op8500, Op8508, Op8510, Op8518, Op8520, Op8528, Op8530, Op8538, + IllIns, IllIns, Op8550, Op8558, Op8560, Op8568, Op8570, Op8578, + IllIns, IllIns, Op8590, Op8598, Op85a0, Op85a8, Op85b0, Op85b8, + Op85c0, IllIns, Op85d0, Op85d8, Op85e0, Op85e8, Op85f0, Op85f8, + Op8600, IllIns, Op8610, Op8618, Op8620, Op8628, Op8630, Op8638, + Op8640, IllIns, Op8650, Op8658, Op8660, Op8668, Op8670, Op8678, + Op8680, IllIns, Op8690, Op8698, Op86a0, Op86a8, Op86b0, Op86b8, + Op86c0, IllIns, Op86d0, Op86d8, Op86e0, Op86e8, Op86f0, Op86f8, + Op8700, Op8708, Op8710, Op8718, Op8720, Op8728, Op8730, Op8738, + IllIns, IllIns, Op8750, Op8758, Op8760, Op8768, Op8770, Op8778, + IllIns, IllIns, Op8790, Op8798, Op87a0, Op87a8, Op87b0, Op87b8, + Op87c0, IllIns, Op87d0, Op87d8, Op87e0, Op87e8, Op87f0, Op87f8, + Op8800, IllIns, Op8810, Op8818, Op8820, Op8828, Op8830, Op8838, + Op8840, IllIns, Op8850, Op8858, Op8860, Op8868, Op8870, Op8878, + Op8880, IllIns, Op8890, Op8898, Op88a0, Op88a8, Op88b0, Op88b8, + Op88c0, IllIns, Op88d0, Op88d8, Op88e0, Op88e8, Op88f0, Op88f8, + Op8900, Op8908, Op8910, Op8918, Op8920, Op8928, Op8930, Op8938, + IllIns, IllIns, Op8950, Op8958, Op8960, Op8968, Op8970, Op8978, + IllIns, IllIns, Op8990, Op8998, Op89a0, Op89a8, Op89b0, Op89b8, + Op89c0, IllIns, Op89d0, Op89d8, Op89e0, Op89e8, Op89f0, Op89f8, + Op8a00, IllIns, Op8a10, Op8a18, Op8a20, Op8a28, Op8a30, Op8a38, + Op8a40, IllIns, Op8a50, Op8a58, Op8a60, Op8a68, Op8a70, Op8a78, + Op8a80, IllIns, Op8a90, Op8a98, Op8aa0, Op8aa8, Op8ab0, Op8ab8, + Op8ac0, IllIns, Op8ad0, Op8ad8, Op8ae0, Op8ae8, Op8af0, Op8af8, + Op8b00, Op8b08, Op8b10, Op8b18, Op8b20, Op8b28, Op8b30, Op8b38, + IllIns, IllIns, Op8b50, Op8b58, Op8b60, Op8b68, Op8b70, Op8b78, + IllIns, IllIns, Op8b90, Op8b98, Op8ba0, Op8ba8, Op8bb0, Op8bb8, + Op8bc0, IllIns, Op8bd0, Op8bd8, Op8be0, Op8be8, Op8bf0, Op8bf8, + Op8c00, IllIns, Op8c10, Op8c18, Op8c20, Op8c28, Op8c30, Op8c38, + Op8c40, IllIns, Op8c50, Op8c58, Op8c60, Op8c68, Op8c70, Op8c78, + Op8c80, IllIns, Op8c90, Op8c98, Op8ca0, Op8ca8, Op8cb0, Op8cb8, + Op8cc0, IllIns, Op8cd0, Op8cd8, Op8ce0, Op8ce8, Op8cf0, Op8cf8, + Op8d00, Op8d08, Op8d10, Op8d18, Op8d20, Op8d28, Op8d30, Op8d38, + IllIns, IllIns, Op8d50, Op8d58, Op8d60, Op8d68, Op8d70, Op8d78, + IllIns, IllIns, Op8d90, Op8d98, Op8da0, Op8da8, Op8db0, Op8db8, + Op8dc0, IllIns, Op8dd0, Op8dd8, Op8de0, Op8de8, Op8df0, Op8df8, + Op8e00, IllIns, Op8e10, Op8e18, Op8e20, Op8e28, Op8e30, Op8e38, + Op8e40, IllIns, Op8e50, Op8e58, Op8e60, Op8e68, Op8e70, Op8e78, + Op8e80, IllIns, Op8e90, Op8e98, Op8ea0, Op8ea8, Op8eb0, Op8eb8, + Op8ec0, IllIns, Op8ed0, Op8ed8, Op8ee0, Op8ee8, Op8ef0, Op8ef8, + Op8f00, Op8f08, Op8f10, Op8f18, Op8f20, Op8f28, Op8f30, Op8f38, + IllIns, IllIns, Op8f50, Op8f58, Op8f60, Op8f68, Op8f70, Op8f78, + IllIns, IllIns, Op8f90, Op8f98, Op8fa0, Op8fa8, Op8fb0, Op8fb8, + Op8fc0, IllIns, Op8fd0, Op8fd8, Op8fe0, Op8fe8, Op8ff0, Op8ff8, + + /* 9000 */ + Op9000, IllIns, Op9010, Op9018, Op9020, Op9028, Op9030, Op9038, + Op9040, Op9048, Op9050, Op9058, Op9060, Op9068, Op9070, Op9078, + Op9080, Op9088, Op9090, Op9098, Op90a0, Op90a8, Op90b0, Op90b8, + Op90c0, Op90c8, Op90d0, Op90d8, Op90e0, Op90e8, Op90f0, Op90f8, + Op9100, Op9108, Op9110, Op9118, Op9120, Op9128, Op9130, Op9138, + Op9140, Op9148, Op9150, Op9158, Op9160, Op9168, Op9170, Op9178, + Op9180, Op9188, Op9190, Op9198, Op91a0, Op91a8, Op91b0, Op91b8, + Op91c0, Op91c8, Op91d0, Op91d8, Op91e0, Op91e8, Op91f0, Op91f8, + Op9200, IllIns, Op9210, Op9218, Op9220, Op9228, Op9230, Op9238, + Op9240, Op9248, Op9250, Op9258, Op9260, Op9268, Op9270, Op9278, + Op9280, Op9288, Op9290, Op9298, Op92a0, Op92a8, Op92b0, Op92b8, + Op92c0, Op92c8, Op92d0, Op92d8, Op92e0, Op92e8, Op92f0, Op92f8, + Op9300, Op9308, Op9310, Op9318, Op9320, Op9328, Op9330, Op9338, + Op9340, Op9348, Op9350, Op9358, Op9360, Op9368, Op9370, Op9378, + Op9380, Op9388, Op9390, Op9398, Op93a0, Op93a8, Op93b0, Op93b8, + Op93c0, Op93c8, Op93d0, Op93d8, Op93e0, Op93e8, Op93f0, Op93f8, + Op9400, IllIns, Op9410, Op9418, Op9420, Op9428, Op9430, Op9438, + Op9440, Op9448, Op9450, Op9458, Op9460, Op9468, Op9470, Op9478, + Op9480, Op9488, Op9490, Op9498, Op94a0, Op94a8, Op94b0, Op94b8, + Op94c0, Op94c8, Op94d0, Op94d8, Op94e0, Op94e8, Op94f0, Op94f8, + Op9500, Op9508, Op9510, Op9518, Op9520, Op9528, Op9530, Op9538, + Op9540, Op9548, Op9550, Op9558, Op9560, Op9568, Op9570, Op9578, + Op9580, Op9588, Op9590, Op9598, Op95a0, Op95a8, Op95b0, Op95b8, + Op95c0, Op95c8, Op95d0, Op95d8, Op95e0, Op95e8, Op95f0, Op95f8, + Op9600, IllIns, Op9610, Op9618, Op9620, Op9628, Op9630, Op9638, + Op9640, Op9648, Op9650, Op9658, Op9660, Op9668, Op9670, Op9678, + Op9680, Op9688, Op9690, Op9698, Op96a0, Op96a8, Op96b0, Op96b8, + Op96c0, Op96c8, Op96d0, Op96d8, Op96e0, Op96e8, Op96f0, Op96f8, + Op9700, Op9708, Op9710, Op9718, Op9720, Op9728, Op9730, Op9738, + Op9740, Op9748, Op9750, Op9758, Op9760, Op9768, Op9770, Op9778, + Op9780, Op9788, Op9790, Op9798, Op97a0, Op97a8, Op97b0, Op97b8, + Op97c0, Op97c8, Op97d0, Op97d8, Op97e0, Op97e8, Op97f0, Op97f8, + Op9800, IllIns, Op9810, Op9818, Op9820, Op9828, Op9830, Op9838, + Op9840, Op9848, Op9850, Op9858, Op9860, Op9868, Op9870, Op9878, + Op9880, Op9888, Op9890, Op9898, Op98a0, Op98a8, Op98b0, Op98b8, + Op98c0, Op98c8, Op98d0, Op98d8, Op98e0, Op98e8, Op98f0, Op98f8, + Op9900, Op9908, Op9910, Op9918, Op9920, Op9928, Op9930, Op9938, + Op9940, Op9948, Op9950, Op9958, Op9960, Op9968, Op9970, Op9978, + Op9980, Op9988, Op9990, Op9998, Op99a0, Op99a8, Op99b0, Op99b8, + Op99c0, Op99c8, Op99d0, Op99d8, Op99e0, Op99e8, Op99f0, Op99f8, + Op9a00, IllIns, Op9a10, Op9a18, Op9a20, Op9a28, Op9a30, Op9a38, + Op9a40, Op9a48, Op9a50, Op9a58, Op9a60, Op9a68, Op9a70, Op9a78, + Op9a80, Op9a88, Op9a90, Op9a98, Op9aa0, Op9aa8, Op9ab0, Op9ab8, + Op9ac0, Op9ac8, Op9ad0, Op9ad8, Op9ae0, Op9ae8, Op9af0, Op9af8, + Op9b00, Op9b08, Op9b10, Op9b18, Op9b20, Op9b28, Op9b30, Op9b38, + Op9b40, Op9b48, Op9b50, Op9b58, Op9b60, Op9b68, Op9b70, Op9b78, + Op9b80, Op9b88, Op9b90, Op9b98, Op9ba0, Op9ba8, Op9bb0, Op9bb8, + Op9bc0, Op9bc8, Op9bd0, Op9bd8, Op9be0, Op9be8, Op9bf0, Op9bf8, + Op9c00, IllIns, Op9c10, Op9c18, Op9c20, Op9c28, Op9c30, Op9c38, + Op9c40, Op9c48, Op9c50, Op9c58, Op9c60, Op9c68, Op9c70, Op9c78, + Op9c80, Op9c88, Op9c90, Op9c98, Op9ca0, Op9ca8, Op9cb0, Op9cb8, + Op9cc0, Op9cc8, Op9cd0, Op9cd8, Op9ce0, Op9ce8, Op9cf0, Op9cf8, + Op9d00, Op9d08, Op9d10, Op9d18, Op9d20, Op9d28, Op9d30, Op9d38, + Op9d40, Op9d48, Op9d50, Op9d58, Op9d60, Op9d68, Op9d70, Op9d78, + Op9d80, Op9d88, Op9d90, Op9d98, Op9da0, Op9da8, Op9db0, Op9db8, + Op9dc0, Op9dc8, Op9dd0, Op9dd8, Op9de0, Op9de8, Op9df0, Op9df8, + Op9e00, IllIns, Op9e10, Op9e18, Op9e20, Op9e28, Op9e30, Op9e38, + Op9e40, Op9e48, Op9e50, Op9e58, Op9e60, Op9e68, Op9e70, Op9e78, + Op9e80, Op9e88, Op9e90, Op9e98, Op9ea0, Op9ea8, Op9eb0, Op9eb8, + Op9ec0, Op9ec8, Op9ed0, Op9ed8, Op9ee0, Op9ee8, Op9ef0, Op9ef8, + Op9f00, Op9f08, Op9f10, Op9f18, Op9f20, Op9f28, Op9f30, Op9f38, + Op9f40, Op9f48, Op9f50, Op9f58, Op9f60, Op9f68, Op9f70, Op9f78, + Op9f80, Op9f88, Op9f90, Op9f98, Op9fa0, Op9fa8, Op9fb0, Op9fb8, + Op9fc0, Op9fc8, Op9fd0, Op9fd8, Op9fe0, Op9fe8, Op9ff0, Op9ff8, + + /* A000 */ + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + + /* B000 */ + Opb000, IllIns, Opb010, Opb018, Opb020, Opb028, Opb030, Opb038, + Opb040, Opb048, Opb050, Opb058, Opb060, Opb068, Opb070, Opb078, + Opb080, Opb088, Opb090, Opb098, Opb0a0, Opb0a8, Opb0b0, Opb0b8, + Opb0c0, Opb0c8, Opb0d0, Opb0d8, Opb0e0, Opb0e8, Opb0f0, Opb0f8, + Opb100, Opb108, Opb110, Opb118, Opb120, Opb128, Opb130, Opb138, + Opb140, Opb148, Opb150, Opb158, Opb160, Opb168, Opb170, Opb178, + Opb180, Opb188, Opb190, Opb198, Opb1a0, Opb1a8, Opb1b0, Opb1b8, + Opb1c0, Opb1c8, Opb1d0, Opb1d8, Opb1e0, Opb1e8, Opb1f0, Opb1f8, + Opb200, IllIns, Opb210, Opb218, Opb220, Opb228, Opb230, Opb238, + Opb240, Opb248, Opb250, Opb258, Opb260, Opb268, Opb270, Opb278, + Opb280, Opb288, Opb290, Opb298, Opb2a0, Opb2a8, Opb2b0, Opb2b8, + Opb2c0, Opb2c8, Opb2d0, Opb2d8, Opb2e0, Opb2e8, Opb2f0, Opb2f8, + Opb300, Opb308, Opb310, Opb318, Opb320, Opb328, Opb330, Opb338, + Opb340, Opb348, Opb350, Opb358, Opb360, Opb368, Opb370, Opb378, + Opb380, Opb388, Opb390, Opb398, Opb3a0, Opb3a8, Opb3b0, Opb3b8, + Opb3c0, Opb3c8, Opb3d0, Opb3d8, Opb3e0, Opb3e8, Opb3f0, Opb3f8, + Opb400, IllIns, Opb410, Opb418, Opb420, Opb428, Opb430, Opb438, + Opb440, Opb448, Opb450, Opb458, Opb460, Opb468, Opb470, Opb478, + Opb480, Opb488, Opb490, Opb498, Opb4a0, Opb4a8, Opb4b0, Opb4b8, + Opb4c0, Opb4c8, Opb4d0, Opb4d8, Opb4e0, Opb4e8, Opb4f0, Opb4f8, + Opb500, Opb508, Opb510, Opb518, Opb520, Opb528, Opb530, Opb538, + Opb540, Opb548, Opb550, Opb558, Opb560, Opb568, Opb570, Opb578, + Opb580, Opb588, Opb590, Opb598, Opb5a0, Opb5a8, Opb5b0, Opb5b8, + Opb5c0, Opb5c8, Opb5d0, Opb5d8, Opb5e0, Opb5e8, Opb5f0, Opb5f8, + Opb600, IllIns, Opb610, Opb618, Opb620, Opb628, Opb630, Opb638, + Opb640, Opb648, Opb650, Opb658, Opb660, Opb668, Opb670, Opb678, + Opb680, Opb688, Opb690, Opb698, Opb6a0, Opb6a8, Opb6b0, Opb6b8, + Opb6c0, Opb6c8, Opb6d0, Opb6d8, Opb6e0, Opb6e8, Opb6f0, Opb6f8, + Opb700, Opb708, Opb710, Opb718, Opb720, Opb728, Opb730, Opb738, + Opb740, Opb748, Opb750, Opb758, Opb760, Opb768, Opb770, Opb778, + Opb780, Opb788, Opb790, Opb798, Opb7a0, Opb7a8, Opb7b0, Opb7b8, + Opb7c0, Opb7c8, Opb7d0, Opb7d8, Opb7e0, Opb7e8, Opb7f0, Opb7f8, + Opb800, IllIns, Opb810, Opb818, Opb820, Opb828, Opb830, Opb838, + Opb840, Opb848, Opb850, Opb858, Opb860, Opb868, Opb870, Opb878, + Opb880, Opb888, Opb890, Opb898, Opb8a0, Opb8a8, Opb8b0, Opb8b8, + Opb8c0, Opb8c8, Opb8d0, Opb8d8, Opb8e0, Opb8e8, Opb8f0, Opb8f8, + Opb900, Opb908, Opb910, Opb918, Opb920, Opb928, Opb930, Opb938, + Opb940, Opb948, Opb950, Opb958, Opb960, Opb968, Opb970, Opb978, + Opb980, Opb988, Opb990, Opb998, Opb9a0, Opb9a8, Opb9b0, Opb9b8, + Opb9c0, Opb9c8, Opb9d0, Opb9d8, Opb9e0, Opb9e8, Opb9f0, Opb9f8, + Opba00, IllIns, Opba10, Opba18, Opba20, Opba28, Opba30, Opba38, + Opba40, Opba48, Opba50, Opba58, Opba60, Opba68, Opba70, Opba78, + Opba80, Opba88, Opba90, Opba98, Opbaa0, Opbaa8, Opbab0, Opbab8, + Opbac0, Opbac8, Opbad0, Opbad8, Opbae0, Opbae8, Opbaf0, Opbaf8, + Opbb00, Opbb08, Opbb10, Opbb18, Opbb20, Opbb28, Opbb30, Opbb38, + Opbb40, Opbb48, Opbb50, Opbb58, Opbb60, Opbb68, Opbb70, Opbb78, + Opbb80, Opbb88, Opbb90, Opbb98, Opbba0, Opbba8, Opbbb0, Opbbb8, + Opbbc0, Opbbc8, Opbbd0, Opbbd8, Opbbe0, Opbbe8, Opbbf0, Opbbf8, + Opbc00, IllIns, Opbc10, Opbc18, Opbc20, Opbc28, Opbc30, Opbc38, + Opbc40, Opbc48, Opbc50, Opbc58, Opbc60, Opbc68, Opbc70, Opbc78, + Opbc80, Opbc88, Opbc90, Opbc98, Opbca0, Opbca8, Opbcb0, Opbcb8, + Opbcc0, Opbcc8, Opbcd0, Opbcd8, Opbce0, Opbce8, Opbcf0, Opbcf8, + Opbd00, Opbd08, Opbd10, Opbd18, Opbd20, Opbd28, Opbd30, Opbd38, + Opbd40, Opbd48, Opbd50, Opbd58, Opbd60, Opbd68, Opbd70, Opbd78, + Opbd80, Opbd88, Opbd90, Opbd98, Opbda0, Opbda8, Opbdb0, Opbdb8, + Opbdc0, Opbdc8, Opbdd0, Opbdd8, Opbde0, Opbde8, Opbdf0, Opbdf8, + Opbe00, IllIns, Opbe10, Opbe18, Opbe20, Opbe28, Opbe30, Opbe38, + Opbe40, Opbe48, Opbe50, Opbe58, Opbe60, Opbe68, Opbe70, Opbe78, + Opbe80, Opbe88, Opbe90, Opbe98, Opbea0, Opbea8, Opbeb0, Opbeb8, + Opbec0, Opbec8, Opbed0, Opbed8, Opbee0, Opbee8, Opbef0, Opbef8, + Opbf00, Opbf08, Opbf10, Opbf18, Opbf20, Opbf28, Opbf30, Opbf38, + Opbf40, Opbf48, Opbf50, Opbf58, Opbf60, Opbf68, Opbf70, Opbf78, + Opbf80, Opbf88, Opbf90, Opbf98, Opbfa0, Opbfa8, Opbfb0, Opbfb8, + Opbfc0, Opbfc8, Opbfd0, Opbfd8, Opbfe0, Opbfe8, Opbff0, Opbff8, + + /* C000 */ + Opc000, IllIns, Opc010, Opc018, Opc020, Opc028, Opc030, Opc038, + Opc040, IllIns, Opc050, Opc058, Opc060, Opc068, Opc070, Opc078, + Opc080, IllIns, Opc090, Opc098, Opc0a0, Opc0a8, Opc0b0, Opc0b8, + Opc0c0, IllIns, Opc0d0, Opc0d8, Opc0e0, Opc0e8, Opc0f0, Opc0f8, + Opc100, Opc108, Opc110, Opc118, Opc120, Opc128, Opc130, Opc138, + Opc140, Opc148, Opc150, Opc158, Opc160, Opc168, Opc170, Opc178, + IllIns, Opc188, Opc190, Opc198, Opc1a0, Opc1a8, Opc1b0, Opc1b8, + Opc1c0, IllIns, Opc1d0, Opc1d8, Opc1e0, Opc1e8, Opc1f0, Opc1f8, + Opc200, IllIns, Opc210, Opc218, Opc220, Opc228, Opc230, Opc238, + Opc240, IllIns, Opc250, Opc258, Opc260, Opc268, Opc270, Opc278, + Opc280, IllIns, Opc290, Opc298, Opc2a0, Opc2a8, Opc2b0, Opc2b8, + Opc2c0, IllIns, Opc2d0, Opc2d8, Opc2e0, Opc2e8, Opc2f0, Opc2f8, + Opc300, Opc308, Opc310, Opc318, Opc320, Opc328, Opc330, Opc338, + Opc340, Opc348, Opc350, Opc358, Opc360, Opc368, Opc370, Opc378, + IllIns, Opc388, Opc390, Opc398, Opc3a0, Opc3a8, Opc3b0, Opc3b8, + Opc3c0, IllIns, Opc3d0, Opc3d8, Opc3e0, Opc3e8, Opc3f0, Opc3f8, + Opc400, IllIns, Opc410, Opc418, Opc420, Opc428, Opc430, Opc438, + Opc440, IllIns, Opc450, Opc458, Opc460, Opc468, Opc470, Opc478, + Opc480, IllIns, Opc490, Opc498, Opc4a0, Opc4a8, Opc4b0, Opc4b8, + Opc4c0, IllIns, Opc4d0, Opc4d8, Opc4e0, Opc4e8, Opc4f0, Opc4f8, + Opc500, Opc508, Opc510, Opc518, Opc520, Opc528, Opc530, Opc538, + Opc540, Opc548, Opc550, Opc558, Opc560, Opc568, Opc570, Opc578, + IllIns, Opc588, Opc590, Opc598, Opc5a0, Opc5a8, Opc5b0, Opc5b8, + Opc5c0, IllIns, Opc5d0, Opc5d8, Opc5e0, Opc5e8, Opc5f0, Opc5f8, + Opc600, IllIns, Opc610, Opc618, Opc620, Opc628, Opc630, Opc638, + Opc640, IllIns, Opc650, Opc658, Opc660, Opc668, Opc670, Opc678, + Opc680, IllIns, Opc690, Opc698, Opc6a0, Opc6a8, Opc6b0, Opc6b8, + Opc6c0, IllIns, Opc6d0, Opc6d8, Opc6e0, Opc6e8, Opc6f0, Opc6f8, + Opc700, Opc708, Opc710, Opc718, Opc720, Opc728, Opc730, Opc738, + Opc740, Opc748, Opc750, Opc758, Opc760, Opc768, Opc770, Opc778, + IllIns, Opc788, Opc790, Opc798, Opc7a0, Opc7a8, Opc7b0, Opc7b8, + Opc7c0, IllIns, Opc7d0, Opc7d8, Opc7e0, Opc7e8, Opc7f0, Opc7f8, + Opc800, IllIns, Opc810, Opc818, Opc820, Opc828, Opc830, Opc838, + Opc840, IllIns, Opc850, Opc858, Opc860, Opc868, Opc870, Opc878, + Opc880, IllIns, Opc890, Opc898, Opc8a0, Opc8a8, Opc8b0, Opc8b8, + Opc8c0, IllIns, Opc8d0, Opc8d8, Opc8e0, Opc8e8, Opc8f0, Opc8f8, + Opc900, Opc908, Opc910, Opc918, Opc920, Opc928, Opc930, Opc938, + Opc940, Opc948, Opc950, Opc958, Opc960, Opc968, Opc970, Opc978, + IllIns, Opc988, Opc990, Opc998, Opc9a0, Opc9a8, Opc9b0, Opc9b8, + Opc9c0, IllIns, Opc9d0, Opc9d8, Opc9e0, Opc9e8, Opc9f0, Opc9f8, + Opca00, IllIns, Opca10, Opca18, Opca20, Opca28, Opca30, Opca38, + Opca40, IllIns, Opca50, Opca58, Opca60, Opca68, Opca70, Opca78, + Opca80, IllIns, Opca90, Opca98, Opcaa0, Opcaa8, Opcab0, Opcab8, + Opcac0, IllIns, Opcad0, Opcad8, Opcae0, Opcae8, Opcaf0, Opcaf8, + Opcb00, Opcb08, Opcb10, Opcb18, Opcb20, Opcb28, Opcb30, Opcb38, + Opcb40, Opcb48, Opcb50, Opcb58, Opcb60, Opcb68, Opcb70, Opcb78, + IllIns, Opcb88, Opcb90, Opcb98, Opcba0, Opcba8, Opcbb0, Opcbb8, + Opcbc0, IllIns, Opcbd0, Opcbd8, Opcbe0, Opcbe8, Opcbf0, Opcbf8, + Opcc00, IllIns, Opcc10, Opcc18, Opcc20, Opcc28, Opcc30, Opcc38, + Opcc40, IllIns, Opcc50, Opcc58, Opcc60, Opcc68, Opcc70, Opcc78, + Opcc80, IllIns, Opcc90, Opcc98, Opcca0, Opcca8, Opccb0, Opccb8, + Opccc0, IllIns, Opccd0, Opccd8, Opcce0, Opcce8, Opccf0, Opccf8, + Opcd00, Opcd08, Opcd10, Opcd18, Opcd20, Opcd28, Opcd30, Opcd38, + Opcd40, Opcd48, Opcd50, Opcd58, Opcd60, Opcd68, Opcd70, Opcd78, + IllIns, Opcd88, Opcd90, Opcd98, Opcda0, Opcda8, Opcdb0, Opcdb8, + Opcdc0, IllIns, Opcdd0, Opcdd8, Opcde0, Opcde8, Opcdf0, Opcdf8, + Opce00, IllIns, Opce10, Opce18, Opce20, Opce28, Opce30, Opce38, + Opce40, IllIns, Opce50, Opce58, Opce60, Opce68, Opce70, Opce78, + Opce80, IllIns, Opce90, Opce98, Opcea0, Opcea8, Opceb0, Opceb8, + Opcec0, IllIns, Opced0, Opced8, Opcee0, Opcee8, Opcef0, Opcef8, + Opcf00, Opcf08, Opcf10, Opcf18, Opcf20, Opcf28, Opcf30, Opcf38, + Opcf40, Opcf48, Opcf50, Opcf58, Opcf60, Opcf68, Opcf70, Opcf78, + IllIns, Opcf88, Opcf90, Opcf98, Opcfa0, Opcfa8, Opcfb0, Opcfb8, + Opcfc0, IllIns, Opcfd0, Opcfd8, Opcfe0, Opcfe8, Opcff0, Opcff8, + + /* D000 */ + Opd000, IllIns, Opd010, Opd018, Opd020, Opd028, Opd030, Opd038, + Opd040, Opd048, Opd050, Opd058, Opd060, Opd068, Opd070, Opd078, + Opd080, Opd088, Opd090, Opd098, Opd0a0, Opd0a8, Opd0b0, Opd0b8, + Opd0c0, Opd0c8, Opd0d0, Opd0d8, Opd0e0, Opd0e8, Opd0f0, Opd0f8, + Opd100, Opd108, Opd110, Opd118, Opd120, Opd128, Opd130, Opd138, + Opd140, Opd148, Opd150, Opd158, Opd160, Opd168, Opd170, Opd178, + Opd180, Opd188, Opd190, Opd198, Opd1a0, Opd1a8, Opd1b0, Opd1b8, + Opd1c0, Opd1c8, Opd1d0, Opd1d8, Opd1e0, Opd1e8, Opd1f0, Opd1f8, + Opd200, IllIns, Opd210, Opd218, Opd220, Opd228, Opd230, Opd238, + Opd240, Opd248, Opd250, Opd258, Opd260, Opd268, Opd270, Opd278, + Opd280, Opd288, Opd290, Opd298, Opd2a0, Opd2a8, Opd2b0, Opd2b8, + Opd2c0, Opd2c8, Opd2d0, Opd2d8, Opd2e0, Opd2e8, Opd2f0, Opd2f8, + Opd300, Opd308, Opd310, Opd318, Opd320, Opd328, Opd330, Opd338, + Opd340, Opd348, Opd350, Opd358, Opd360, Opd368, Opd370, Opd378, + Opd380, Opd388, Opd390, Opd398, Opd3a0, Opd3a8, Opd3b0, Opd3b8, + Opd3c0, Opd3c8, Opd3d0, Opd3d8, Opd3e0, Opd3e8, Opd3f0, Opd3f8, + Opd400, IllIns, Opd410, Opd418, Opd420, Opd428, Opd430, Opd438, + Opd440, Opd448, Opd450, Opd458, Opd460, Opd468, Opd470, Opd478, + Opd480, Opd488, Opd490, Opd498, Opd4a0, Opd4a8, Opd4b0, Opd4b8, + Opd4c0, Opd4c8, Opd4d0, Opd4d8, Opd4e0, Opd4e8, Opd4f0, Opd4f8, + Opd500, Opd508, Opd510, Opd518, Opd520, Opd528, Opd530, Opd538, + Opd540, Opd548, Opd550, Opd558, Opd560, Opd568, Opd570, Opd578, + Opd580, Opd588, Opd590, Opd598, Opd5a0, Opd5a8, Opd5b0, Opd5b8, + Opd5c0, Opd5c8, Opd5d0, Opd5d8, Opd5e0, Opd5e8, Opd5f0, Opd5f8, + Opd600, IllIns, Opd610, Opd618, Opd620, Opd628, Opd630, Opd638, + Opd640, Opd648, Opd650, Opd658, Opd660, Opd668, Opd670, Opd678, + Opd680, Opd688, Opd690, Opd698, Opd6a0, Opd6a8, Opd6b0, Opd6b8, + Opd6c0, Opd6c8, Opd6d0, Opd6d8, Opd6e0, Opd6e8, Opd6f0, Opd6f8, + Opd700, Opd708, Opd710, Opd718, Opd720, Opd728, Opd730, Opd738, + Opd740, Opd748, Opd750, Opd758, Opd760, Opd768, Opd770, Opd778, + Opd780, Opd788, Opd790, Opd798, Opd7a0, Opd7a8, Opd7b0, Opd7b8, + Opd7c0, Opd7c8, Opd7d0, Opd7d8, Opd7e0, Opd7e8, Opd7f0, Opd7f8, + Opd800, IllIns, Opd810, Opd818, Opd820, Opd828, Opd830, Opd838, + Opd840, Opd848, Opd850, Opd858, Opd860, Opd868, Opd870, Opd878, + Opd880, Opd888, Opd890, Opd898, Opd8a0, Opd8a8, Opd8b0, Opd8b8, + Opd8c0, Opd8c8, Opd8d0, Opd8d8, Opd8e0, Opd8e8, Opd8f0, Opd8f8, + Opd900, Opd908, Opd910, Opd918, Opd920, Opd928, Opd930, Opd938, + Opd940, Opd948, Opd950, Opd958, Opd960, Opd968, Opd970, Opd978, + Opd980, Opd988, Opd990, Opd998, Opd9a0, Opd9a8, Opd9b0, Opd9b8, + Opd9c0, Opd9c8, Opd9d0, Opd9d8, Opd9e0, Opd9e8, Opd9f0, Opd9f8, + Opda00, IllIns, Opda10, Opda18, Opda20, Opda28, Opda30, Opda38, + Opda40, Opda48, Opda50, Opda58, Opda60, Opda68, Opda70, Opda78, + Opda80, Opda88, Opda90, Opda98, Opdaa0, Opdaa8, Opdab0, Opdab8, + Opdac0, Opdac8, Opdad0, Opdad8, Opdae0, Opdae8, Opdaf0, Opdaf8, + Opdb00, Opdb08, Opdb10, Opdb18, Opdb20, Opdb28, Opdb30, Opdb38, + Opdb40, Opdb48, Opdb50, Opdb58, Opdb60, Opdb68, Opdb70, Opdb78, + Opdb80, Opdb88, Opdb90, Opdb98, Opdba0, Opdba8, Opdbb0, Opdbb8, + Opdbc0, Opdbc8, Opdbd0, Opdbd8, Opdbe0, Opdbe8, Opdbf0, Opdbf8, + Opdc00, IllIns, Opdc10, Opdc18, Opdc20, Opdc28, Opdc30, Opdc38, + Opdc40, Opdc48, Opdc50, Opdc58, Opdc60, Opdc68, Opdc70, Opdc78, + Opdc80, Opdc88, Opdc90, Opdc98, Opdca0, Opdca8, Opdcb0, Opdcb8, + Opdcc0, Opdcc8, Opdcd0, Opdcd8, Opdce0, Opdce8, Opdcf0, Opdcf8, + Opdd00, Opdd08, Opdd10, Opdd18, Opdd20, Opdd28, Opdd30, Opdd38, + Opdd40, Opdd48, Opdd50, Opdd58, Opdd60, Opdd68, Opdd70, Opdd78, + Opdd80, Opdd88, Opdd90, Opdd98, Opdda0, Opdda8, Opddb0, Opddb8, + Opddc0, Opddc8, Opddd0, Opddd8, Opdde0, Opdde8, Opddf0, Opddf8, + Opde00, IllIns, Opde10, Opde18, Opde20, Opde28, Opde30, Opde38, + Opde40, Opde48, Opde50, Opde58, Opde60, Opde68, Opde70, Opde78, + Opde80, Opde88, Opde90, Opde98, Opdea0, Opdea8, Opdeb0, Opdeb8, + Opdec0, Opdec8, Opded0, Opded8, Opdee0, Opdee8, Opdef0, Opdef8, + Opdf00, Opdf08, Opdf10, Opdf18, Opdf20, Opdf28, Opdf30, Opdf38, + Opdf40, Opdf48, Opdf50, Opdf58, Opdf60, Opdf68, Opdf70, Opdf78, + Opdf80, Opdf88, Opdf90, Opdf98, Opdfa0, Opdfa8, Opdfb0, Opdfb8, + Opdfc0, Opdfc8, Opdfd0, Opdfd8, Opdfe0, Opdfe8, Opdff0, Opdff8, + + /* E000 */ + Ope000, Ope008, Ope010, Ope018, Ope020, Ope028, Ope030, Ope038, + Ope040, Ope048, Ope050, Ope058, Ope060, Ope068, Ope070, Ope078, + Ope080, Ope088, Ope090, Ope098, Ope0a0, Ope0a8, Ope0b0, Ope0b8, + IllIns, IllIns, Ope0d0, Ope0d8, Ope0e0, Ope0e8, Ope0f0, Ope0f8, + Ope100, Ope108, Ope110, Ope118, Ope120, Ope128, Ope130, Ope138, + Ope140, Ope148, Ope150, Ope158, Ope160, Ope168, Ope170, Ope178, + Ope180, Ope188, Ope190, Ope198, Ope1a0, Ope1a8, Ope1b0, Ope1b8, + IllIns, IllIns, Ope1d0, Ope1d8, Ope1e0, Ope1e8, Ope1f0, Ope1f8, + Ope200, Ope208, Ope210, Ope218, Ope220, Ope228, Ope230, Ope238, + Ope240, Ope248, Ope250, Ope258, Ope260, Ope268, Ope270, Ope278, + Ope280, Ope288, Ope290, Ope298, Ope2a0, Ope2a8, Ope2b0, Ope2b8, + IllIns, IllIns, Ope2d0, Ope2d8, Ope2e0, Ope2e8, Ope2f0, Ope2f8, + Ope300, Ope308, Ope310, Ope318, Ope320, Ope328, Ope330, Ope338, + Ope340, Ope348, Ope350, Ope358, Ope360, Ope368, Ope370, Ope378, + Ope380, Ope388, Ope390, Ope398, Ope3a0, Ope3a8, Ope3b0, Ope3b8, + IllIns, IllIns, Ope3d0, Ope3d8, Ope3e0, Ope3e8, Ope3f0, Ope3f8, + Ope400, Ope408, Ope410, Ope418, Ope420, Ope428, Ope430, Ope438, + Ope440, Ope448, Ope450, Ope458, Ope460, Ope468, Ope470, Ope478, + Ope480, Ope488, Ope490, Ope498, Ope4a0, Ope4a8, Ope4b0, Ope4b8, + IllIns, IllIns, Ope4d0, Ope4d8, Ope4e0, Ope4e8, Ope4f0, Ope4f8, + Ope500, Ope508, Ope510, Ope518, Ope520, Ope528, Ope530, Ope538, + Ope540, Ope548, Ope550, Ope558, Ope560, Ope568, Ope570, Ope578, + Ope580, Ope588, Ope590, Ope598, Ope5a0, Ope5a8, Ope5b0, Ope5b8, + IllIns, IllIns, Ope5d0, Ope5d8, Ope5e0, Ope5e8, Ope5f0, Ope5f8, + Ope600, Ope608, Ope610, Ope618, Ope620, Ope628, Ope630, Ope638, + Ope640, Ope648, Ope650, Ope658, Ope660, Ope668, Ope670, Ope678, + Ope680, Ope688, Ope690, Ope698, Ope6a0, Ope6a8, Ope6b0, Ope6b8, + IllIns, IllIns, Ope6d0, Ope6d8, Ope6e0, Ope6e8, Ope6f0, Ope6f8, + Ope700, Ope708, Ope710, Ope718, Ope720, Ope728, Ope730, Ope738, + Ope740, Ope748, Ope750, Ope758, Ope760, Ope768, Ope770, Ope778, + Ope780, Ope788, Ope790, Ope798, Ope7a0, Ope7a8, Ope7b0, Ope7b8, + IllIns, IllIns, Ope7d0, Ope7d8, Ope7e0, Ope7e8, Ope7f0, Ope7f8, + Ope800, Ope808, Ope810, Ope818, Ope820, Ope828, Ope830, Ope838, + Ope840, Ope848, Ope850, Ope858, Ope860, Ope868, Ope870, Ope878, + Ope880, Ope888, Ope890, Ope898, Ope8a0, Ope8a8, Ope8b0, Ope8b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Ope900, Ope908, Ope910, Ope918, Ope920, Ope928, Ope930, Ope938, + Ope940, Ope948, Ope950, Ope958, Ope960, Ope968, Ope970, Ope978, + Ope980, Ope988, Ope990, Ope998, Ope9a0, Ope9a8, Ope9b0, Ope9b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opea00, Opea08, Opea10, Opea18, Opea20, Opea28, Opea30, Opea38, + Opea40, Opea48, Opea50, Opea58, Opea60, Opea68, Opea70, Opea78, + Opea80, Opea88, Opea90, Opea98, Opeaa0, Opeaa8, Opeab0, Opeab8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opeb00, Opeb08, Opeb10, Opeb18, Opeb20, Opeb28, Opeb30, Opeb38, + Opeb40, Opeb48, Opeb50, Opeb58, Opeb60, Opeb68, Opeb70, Opeb78, + Opeb80, Opeb88, Opeb90, Opeb98, Opeba0, Opeba8, Opebb0, Opebb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opec00, Opec08, Opec10, Opec18, Opec20, Opec28, Opec30, Opec38, + Opec40, Opec48, Opec50, Opec58, Opec60, Opec68, Opec70, Opec78, + Opec80, Opec88, Opec90, Opec98, Opeca0, Opeca8, Opecb0, Opecb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Oped00, Oped08, Oped10, Oped18, Oped20, Oped28, Oped30, Oped38, + Oped40, Oped48, Oped50, Oped58, Oped60, Oped68, Oped70, Oped78, + Oped80, Oped88, Oped90, Oped98, Opeda0, Opeda8, Opedb0, Opedb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opee00, Opee08, Opee10, Opee18, Opee20, Opee28, Opee30, Opee38, + Opee40, Opee48, Opee50, Opee58, Opee60, Opee68, Opee70, Opee78, + Opee80, Opee88, Opee90, Opee98, Opeea0, Opeea8, Opeeb0, Opeeb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opef00, Opef08, Opef10, Opef18, Opef20, Opef28, Opef30, Opef38, + Opef40, Opef48, Opef50, Opef58, Opef60, Opef68, Opef70, Opef78, + Opef80, Opef88, Opef90, Opef98, Opefa0, Opefa8, Opefb0, Opefb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* F000 */ + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F +}; diff --git a/MCUME_esp32/espcastaway/main/68korig/op68010.h b/MCUME_esp32/espcastaway/main/68korig/op68010.h new file mode 100755 index 0000000..abdb521 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/op68010.h @@ -0,0 +1,1066 @@ +#include "operin.h" + +/* + * Castaway + * (C) 1994 - 2002 Martin Doering, Joachim Hoenig + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ +const unsigned long (*jmp_table[8192])(operin) = { + /* 0000 */ + Op0000, IllIns, Op0010, Op0018, Op0020, Op0028, Op0030, Op0038, + Op0040, IllIns, Op0050, Op0058, Op0060, Op0068, Op0070, Op0078, + Op0080, IllIns, Op0090, Op0098, Op00a0, Op00a8, Op00b0, Op00b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0100, Op0108, Op0110, Op0118, Op0120, Op0128, Op0130, Op0138, + Op0140, Op0148, Op0150, Op0158, Op0160, Op0168, Op0170, Op0178, + Op0180, Op0188, Op0190, Op0198, Op01a0, Op01a8, Op01b0, Op01b8, + Op01c0, Op01c8, Op01d0, Op01d8, Op01e0, Op01e8, Op01f0, Op01f8, + Op0200, IllIns, Op0210, Op0218, Op0220, Op0228, Op0230, Op0238, + Op0240, IllIns, Op0250, Op0258, Op0260, Op0268, Op0270, Op0278, + Op0280, IllIns, Op0290, Op0298, Op02a0, Op02a8, Op02b0, Op02b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0300, Op0308, Op0310, Op0318, Op0320, Op0328, Op0330, Op0338, + Op0340, Op0348, Op0350, Op0358, Op0360, Op0368, Op0370, Op0378, + Op0380, Op0388, Op0390, Op0398, Op03a0, Op03a8, Op03b0, Op03b8, + Op03c0, Op03c8, Op03d0, Op03d8, Op03e0, Op03e8, Op03f0, Op03f8, + Op0400, IllIns, Op0410, Op0418, Op0420, Op0428, Op0430, Op0438, + Op0440, IllIns, Op0450, Op0458, Op0460, Op0468, Op0470, Op0478, + Op0480, IllIns, Op0490, Op0498, Op04a0, Op04a8, Op04b0, Op04b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0500, Op0508, Op0510, Op0518, Op0520, Op0528, Op0530, Op0538, + Op0540, Op0548, Op0550, Op0558, Op0560, Op0568, Op0570, Op0578, + Op0580, Op0588, Op0590, Op0598, Op05a0, Op05a8, Op05b0, Op05b8, + Op05c0, Op05c8, Op05d0, Op05d8, Op05e0, Op05e8, Op05f0, Op05f8, + Op0600, IllIns, Op0610, Op0618, Op0620, Op0628, Op0630, Op0638, + Op0640, IllIns, Op0650, Op0658, Op0660, Op0668, Op0670, Op0678, + Op0680, IllIns, Op0690, Op0698, Op06a0, Op06a8, Op06b0, Op06b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0700, Op0708, Op0710, Op0718, Op0720, Op0728, Op0730, Op0738, + Op0740, Op0748, Op0750, Op0758, Op0760, Op0768, Op0770, Op0778, + Op0780, Op0788, Op0790, Op0798, Op07a0, Op07a8, Op07b0, Op07b8, + Op07c0, Op07c8, Op07d0, Op07d8, Op07e0, Op07e8, Op07f0, Op07f8, + Op0800, IllIns, Op0810, Op0818, Op0820, Op0828, Op0830, Op0838, + Op0840, IllIns, Op0850, Op0858, Op0860, Op0868, Op0870, Op0878, + Op0880, IllIns, Op0890, Op0898, Op08a0, Op08a8, Op08b0, Op08b8, + Op08c0, IllIns, Op08d0, Op08d8, Op08e0, Op08e8, Op08f0, Op08f8, + Op0900, Op0908, Op0910, Op0918, Op0920, Op0928, Op0930, Op0938, + Op0940, Op0948, Op0950, Op0958, Op0960, Op0968, Op0970, Op0978, + Op0980, Op0988, Op0990, Op0998, Op09a0, Op09a8, Op09b0, Op09b8, + Op09c0, Op09c8, Op09d0, Op09d8, Op09e0, Op09e8, Op09f0, Op09f8, + Op0a00, IllIns, Op0a10, Op0a18, Op0a20, Op0a28, Op0a30, Op0a38, + Op0a40, IllIns, Op0a50, Op0a58, Op0a60, Op0a68, Op0a70, Op0a78, + Op0a80, IllIns, Op0a90, Op0a98, Op0aa0, Op0aa8, Op0ab0, Op0ab8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0b00, Op0b08, Op0b10, Op0b18, Op0b20, Op0b28, Op0b30, Op0b38, + Op0b40, Op0b48, Op0b50, Op0b58, Op0b60, Op0b68, Op0b70, Op0b78, + Op0b80, Op0b88, Op0b90, Op0b98, Op0ba0, Op0ba8, Op0bb0, Op0bb8, + Op0bc0, Op0bc8, Op0bd0, Op0bd8, Op0be0, Op0be8, Op0bf0, Op0bf8, + Op0c00, IllIns, Op0c10, Op0c18, Op0c20, Op0c28, Op0c30, Op0c38, + Op0c40, IllIns, Op0c50, Op0c58, Op0c60, Op0c68, Op0c70, Op0c78, + Op0c80, IllIns, Op0c90, Op0c98, Op0ca0, Op0ca8, Op0cb0, Op0cb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0d00, Op0d08, Op0d10, Op0d18, Op0d20, Op0d28, Op0d30, Op0d38, + Op0d40, Op0d48, Op0d50, Op0d58, Op0d60, Op0d68, Op0d70, Op0d78, + Op0d80, Op0d88, Op0d90, Op0d98, Op0da0, Op0da8, Op0db0, Op0db8, + Op0dc0, Op0dc8, Op0dd0, Op0dd8, Op0de0, Op0de8, Op0df0, Op0df8, + IllIns, IllIns, Op0e10, Op0e18, Op0e20, Op0e28, Op0e30, Op0e38, + IllIns, IllIns, Op0e50, Op0e58, Op0e60, Op0e68, Op0e70, Op0e78, + IllIns, IllIns, Op0e90, Op0e98, Op0ea0, Op0ea8, Op0eb0, Op0eb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0f00, Op0f08, Op0f10, Op0f18, Op0f20, Op0f28, Op0f30, Op0f38, + Op0f40, Op0f48, Op0f50, Op0f58, Op0f60, Op0f68, Op0f70, Op0f78, + Op0f80, Op0f88, Op0f90, Op0f98, Op0fa0, Op0fa8, Op0fb0, Op0fb8, + Op0fc0, Op0fc8, Op0fd0, Op0fd8, Op0fe0, Op0fe8, Op0ff0, Op0ff8, + + /* 1000 */ + Op1000, IllIns, Op1010, Op1018, Op1020, Op1028, Op1030, Op1038, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1080, IllIns, Op1090, Op1098, Op10a0, Op10a8, Op10b0, Op10b8, + Op10c0, IllIns, Op10d0, Op10d8, Op10e0, Op10e8, Op10f0, Op10f8, + Op1100, IllIns, Op1110, Op1118, Op1120, Op1128, Op1130, Op1138, + Op1140, IllIns, Op1150, Op1158, Op1160, Op1168, Op1170, Op1178, + Op1180, IllIns, Op1190, Op1198, Op11a0, Op11a8, Op11b0, Op11b8, + Op11c0, IllIns, Op11d0, Op11d8, Op11e0, Op11e8, Op11f0, Op11f8, + Op1200, IllIns, Op1210, Op1218, Op1220, Op1228, Op1230, Op1238, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1280, IllIns, Op1290, Op1298, Op12a0, Op12a8, Op12b0, Op12b8, + Op12c0, IllIns, Op12d0, Op12d8, Op12e0, Op12e8, Op12f0, Op12f8, + Op1300, IllIns, Op1310, Op1318, Op1320, Op1328, Op1330, Op1338, + Op1340, IllIns, Op1350, Op1358, Op1360, Op1368, Op1370, Op1378, + Op1380, IllIns, Op1390, Op1398, Op13a0, Op13a8, Op13b0, Op13b8, + Op13c0, IllIns, Op13d0, Op13d8, Op13e0, Op13e8, Op13f0, Op13f8, + Op1400, IllIns, Op1410, Op1418, Op1420, Op1428, Op1430, Op1438, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1480, IllIns, Op1490, Op1498, Op14a0, Op14a8, Op14b0, Op14b8, + Op14c0, IllIns, Op14d0, Op14d8, Op14e0, Op14e8, Op14f0, Op14f8, + Op1500, IllIns, Op1510, Op1518, Op1520, Op1528, Op1530, Op1538, + Op1540, IllIns, Op1550, Op1558, Op1560, Op1568, Op1570, Op1578, + Op1580, IllIns, Op1590, Op1598, Op15a0, Op15a8, Op15b0, Op15b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1600, IllIns, Op1610, Op1618, Op1620, Op1628, Op1630, Op1638, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1680, IllIns, Op1690, Op1698, Op16a0, Op16a8, Op16b0, Op16b8, + Op16c0, IllIns, Op16d0, Op16d8, Op16e0, Op16e8, Op16f0, Op16f8, + Op1700, IllIns, Op1710, Op1718, Op1720, Op1728, Op1730, Op1738, + Op1740, IllIns, Op1750, Op1758, Op1760, Op1768, Op1770, Op1778, + Op1780, IllIns, Op1790, Op1798, Op17a0, Op17a8, Op17b0, Op17b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1800, IllIns, Op1810, Op1818, Op1820, Op1828, Op1830, Op1838, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1880, IllIns, Op1890, Op1898, Op18a0, Op18a8, Op18b0, Op18b8, + Op18c0, IllIns, Op18d0, Op18d8, Op18e0, Op18e8, Op18f0, Op18f8, + Op1900, IllIns, Op1910, Op1918, Op1920, Op1928, Op1930, Op1938, + Op1940, IllIns, Op1950, Op1958, Op1960, Op1968, Op1970, Op1978, + Op1980, IllIns, Op1990, Op1998, Op19a0, Op19a8, Op19b0, Op19b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1a00, IllIns, Op1a10, Op1a18, Op1a20, Op1a28, Op1a30, Op1a38, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1a80, IllIns, Op1a90, Op1a98, Op1aa0, Op1aa8, Op1ab0, Op1ab8, + Op1ac0, IllIns, Op1ad0, Op1ad8, Op1ae0, Op1ae8, Op1af0, Op1af8, + Op1b00, IllIns, Op1b10, Op1b18, Op1b20, Op1b28, Op1b30, Op1b38, + Op1b40, IllIns, Op1b50, Op1b58, Op1b60, Op1b68, Op1b70, Op1b78, + Op1b80, IllIns, Op1b90, Op1b98, Op1ba0, Op1ba8, Op1bb0, Op1bb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1c00, IllIns, Op1c10, Op1c18, Op1c20, Op1c28, Op1c30, Op1c38, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1c80, IllIns, Op1c90, Op1c98, Op1ca0, Op1ca8, Op1cb0, Op1cb8, + Op1cc0, IllIns, Op1cd0, Op1cd8, Op1ce0, Op1ce8, Op1cf0, Op1cf8, + Op1d00, IllIns, Op1d10, Op1d18, Op1d20, Op1d28, Op1d30, Op1d38, + Op1d40, IllIns, Op1d50, Op1d58, Op1d60, Op1d68, Op1d70, Op1d78, + Op1d80, IllIns, Op1d90, Op1d98, Op1da0, Op1da8, Op1db0, Op1db8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1e00, IllIns, Op1e10, Op1e18, Op1e20, Op1e28, Op1e30, Op1e38, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1e80, IllIns, Op1e90, Op1e98, Op1ea0, Op1ea8, Op1eb0, Op1eb8, + Op1ec0, IllIns, Op1ed0, Op1ed8, Op1ee0, Op1ee8, Op1ef0, Op1ef8, + Op1f00, IllIns, Op1f10, Op1f18, Op1f20, Op1f28, Op1f30, Op1f38, + Op1f40, IllIns, Op1f50, Op1f58, Op1f60, Op1f68, Op1f70, Op1f78, + Op1f80, IllIns, Op1f90, Op1f98, Op1fa0, Op1fa8, Op1fb0, Op1fb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 2000 */ + Op2000, Op2008, Op2010, Op2018, Op2020, Op2028, Op2030, Op2038, + Op2040, Op2048, Op2050, Op2058, Op2060, Op2068, Op2070, Op2078, + Op2080, Op2088, Op2090, Op2098, Op20a0, Op20a8, Op20b0, Op20b8, + Op20c0, Op20c8, Op20d0, Op20d8, Op20e0, Op20e8, Op20f0, Op20f8, + Op2100, Op2108, Op2110, Op2118, Op2120, Op2128, Op2130, Op2138, + Op2140, Op2148, Op2150, Op2158, Op2160, Op2168, Op2170, Op2178, + Op2180, Op2188, Op2190, Op2198, Op21a0, Op21a8, Op21b0, Op21b8, + Op21c0, Op21c8, Op21d0, Op21d8, Op21e0, Op21e8, Op21f0, Op21f8, + Op2200, Op2208, Op2210, Op2218, Op2220, Op2228, Op2230, Op2238, + Op2240, Op2248, Op2250, Op2258, Op2260, Op2268, Op2270, Op2278, + Op2280, Op2288, Op2290, Op2298, Op22a0, Op22a8, Op22b0, Op22b8, + Op22c0, Op22c8, Op22d0, Op22d8, Op22e0, Op22e8, Op22f0, Op22f8, + Op2300, Op2308, Op2310, Op2318, Op2320, Op2328, Op2330, Op2338, + Op2340, Op2348, Op2350, Op2358, Op2360, Op2368, Op2370, Op2378, + Op2380, Op2388, Op2390, Op2398, Op23a0, Op23a8, Op23b0, Op23b8, + Op23c0, Op23c8, Op23d0, Op23d8, Op23e0, Op23e8, Op23f0, Op23f8, + Op2400, Op2408, Op2410, Op2418, Op2420, Op2428, Op2430, Op2438, + Op2440, Op2448, Op2450, Op2458, Op2460, Op2468, Op2470, Op2478, + Op2480, Op2488, Op2490, Op2498, Op24a0, Op24a8, Op24b0, Op24b8, + Op24c0, Op24c8, Op24d0, Op24d8, Op24e0, Op24e8, Op24f0, Op24f8, + Op2500, Op2508, Op2510, Op2518, Op2520, Op2528, Op2530, Op2538, + Op2540, Op2548, Op2550, Op2558, Op2560, Op2568, Op2570, Op2578, + Op2580, Op2588, Op2590, Op2598, Op25a0, Op25a8, Op25b0, Op25b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2600, Op2608, Op2610, Op2618, Op2620, Op2628, Op2630, Op2638, + Op2640, Op2648, Op2650, Op2658, Op2660, Op2668, Op2670, Op2678, + Op2680, Op2688, Op2690, Op2698, Op26a0, Op26a8, Op26b0, Op26b8, + Op26c0, Op26c8, Op26d0, Op26d8, Op26e0, Op26e8, Op26f0, Op26f8, + Op2700, Op2708, Op2710, Op2718, Op2720, Op2728, Op2730, Op2738, + Op2740, Op2748, Op2750, Op2758, Op2760, Op2768, Op2770, Op2778, + Op2780, Op2788, Op2790, Op2798, Op27a0, Op27a8, Op27b0, Op27b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2800, Op2808, Op2810, Op2818, Op2820, Op2828, Op2830, Op2838, + Op2840, Op2848, Op2850, Op2858, Op2860, Op2868, Op2870, Op2878, + Op2880, Op2888, Op2890, Op2898, Op28a0, Op28a8, Op28b0, Op28b8, + Op28c0, Op28c8, Op28d0, Op28d8, Op28e0, Op28e8, Op28f0, Op28f8, + Op2900, Op2908, Op2910, Op2918, Op2920, Op2928, Op2930, Op2938, + Op2940, Op2948, Op2950, Op2958, Op2960, Op2968, Op2970, Op2978, + Op2980, Op2988, Op2990, Op2998, Op29a0, Op29a8, Op29b0, Op29b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2a00, Op2a08, Op2a10, Op2a18, Op2a20, Op2a28, Op2a30, Op2a38, + Op2a40, Op2a48, Op2a50, Op2a58, Op2a60, Op2a68, Op2a70, Op2a78, + Op2a80, Op2a88, Op2a90, Op2a98, Op2aa0, Op2aa8, Op2ab0, Op2ab8, + Op2ac0, Op2ac8, Op2ad0, Op2ad8, Op2ae0, Op2ae8, Op2af0, Op2af8, + Op2b00, Op2b08, Op2b10, Op2b18, Op2b20, Op2b28, Op2b30, Op2b38, + Op2b40, Op2b48, Op2b50, Op2b58, Op2b60, Op2b68, Op2b70, Op2b78, + Op2b80, Op2b88, Op2b90, Op2b98, Op2ba0, Op2ba8, Op2bb0, Op2bb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2c00, Op2c08, Op2c10, Op2c18, Op2c20, Op2c28, Op2c30, Op2c38, + Op2c40, Op2c48, Op2c50, Op2c58, Op2c60, Op2c68, Op2c70, Op2c78, + Op2c80, Op2c88, Op2c90, Op2c98, Op2ca0, Op2ca8, Op2cb0, Op2cb8, + Op2cc0, Op2cc8, Op2cd0, Op2cd8, Op2ce0, Op2ce8, Op2cf0, Op2cf8, + Op2d00, Op2d08, Op2d10, Op2d18, Op2d20, Op2d28, Op2d30, Op2d38, + Op2d40, Op2d48, Op2d50, Op2d58, Op2d60, Op2d68, Op2d70, Op2d78, + Op2d80, Op2d88, Op2d90, Op2d98, Op2da0, Op2da8, Op2db0, Op2db8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2e00, Op2e08, Op2e10, Op2e18, Op2e20, Op2e28, Op2e30, Op2e38, + Op2e40, Op2e48, Op2e50, Op2e58, Op2e60, Op2e68, Op2e70, Op2e78, + Op2e80, Op2e88, Op2e90, Op2e98, Op2ea0, Op2ea8, Op2eb0, Op2eb8, + Op2ec0, Op2ec8, Op2ed0, Op2ed8, Op2ee0, Op2ee8, Op2ef0, Op2ef8, + Op2f00, Op2f08, Op2f10, Op2f18, Op2f20, Op2f28, Op2f30, Op2f38, + Op2f40, Op2f48, Op2f50, Op2f58, Op2f60, Op2f68, Op2f70, Op2f78, + Op2f80, Op2f88, Op2f90, Op2f98, Op2fa0, Op2fa8, Op2fb0, Op2fb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 3000 */ + Op3000, Op3008, Op3010, Op3018, Op3020, Op3028, Op3030, Op3038, + Op3040, Op3048, Op3050, Op3058, Op3060, Op3068, Op3070, Op3078, + Op3080, Op3088, Op3090, Op3098, Op30a0, Op30a8, Op30b0, Op30b8, + Op30c0, Op30c8, Op30d0, Op30d8, Op30e0, Op30e8, Op30f0, Op30f8, + Op3100, Op3108, Op3110, Op3118, Op3120, Op3128, Op3130, Op3138, + Op3140, Op3148, Op3150, Op3158, Op3160, Op3168, Op3170, Op3178, + Op3180, Op3188, Op3190, Op3198, Op31a0, Op31a8, Op31b0, Op31b8, + Op31c0, Op31c8, Op31d0, Op31d8, Op31e0, Op31e8, Op31f0, Op31f8, + Op3200, Op3208, Op3210, Op3218, Op3220, Op3228, Op3230, Op3238, + Op3240, Op3248, Op3250, Op3258, Op3260, Op3268, Op3270, Op3278, + Op3280, Op3288, Op3290, Op3298, Op32a0, Op32a8, Op32b0, Op32b8, + Op32c0, Op32c8, Op32d0, Op32d8, Op32e0, Op32e8, Op32f0, Op32f8, + Op3300, Op3308, Op3310, Op3318, Op3320, Op3328, Op3330, Op3338, + Op3340, Op3348, Op3350, Op3358, Op3360, Op3368, Op3370, Op3378, + Op3380, Op3388, Op3390, Op3398, Op33a0, Op33a8, Op33b0, Op33b8, + Op33c0, Op33c8, Op33d0, Op33d8, Op33e0, Op33e8, Op33f0, Op33f8, + Op3400, Op3408, Op3410, Op3418, Op3420, Op3428, Op3430, Op3438, + Op3440, Op3448, Op3450, Op3458, Op3460, Op3468, Op3470, Op3478, + Op3480, Op3488, Op3490, Op3498, Op34a0, Op34a8, Op34b0, Op34b8, + Op34c0, Op34c8, Op34d0, Op34d8, Op34e0, Op34e8, Op34f0, Op34f8, + Op3500, Op3508, Op3510, Op3518, Op3520, Op3528, Op3530, Op3538, + Op3540, Op3548, Op3550, Op3558, Op3560, Op3568, Op3570, Op3578, + Op3580, Op3588, Op3590, Op3598, Op35a0, Op35a8, Op35b0, Op35b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3600, Op3608, Op3610, Op3618, Op3620, Op3628, Op3630, Op3638, + Op3640, Op3648, Op3650, Op3658, Op3660, Op3668, Op3670, Op3678, + Op3680, Op3688, Op3690, Op3698, Op36a0, Op36a8, Op36b0, Op36b8, + Op36c0, Op36c8, Op36d0, Op36d8, Op36e0, Op36e8, Op36f0, Op36f8, + Op3700, Op3708, Op3710, Op3718, Op3720, Op3728, Op3730, Op3738, + Op3740, Op3748, Op3750, Op3758, Op3760, Op3768, Op3770, Op3778, + Op3780, Op3788, Op3790, Op3798, Op37a0, Op37a8, Op37b0, Op37b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3800, Op3808, Op3810, Op3818, Op3820, Op3828, Op3830, Op3838, + Op3840, Op3848, Op3850, Op3858, Op3860, Op3868, Op3870, Op3878, + Op3880, Op3888, Op3890, Op3898, Op38a0, Op38a8, Op38b0, Op38b8, + Op38c0, Op38c8, Op38d0, Op38d8, Op38e0, Op38e8, Op38f0, Op38f8, + Op3900, Op3908, Op3910, Op3918, Op3920, Op3928, Op3930, Op3938, + Op3940, Op3948, Op3950, Op3958, Op3960, Op3968, Op3970, Op3978, + Op3980, Op3988, Op3990, Op3998, Op39a0, Op39a8, Op39b0, Op39b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3a00, Op3a08, Op3a10, Op3a18, Op3a20, Op3a28, Op3a30, Op3a38, + Op3a40, Op3a48, Op3a50, Op3a58, Op3a60, Op3a68, Op3a70, Op3a78, + Op3a80, Op3a88, Op3a90, Op3a98, Op3aa0, Op3aa8, Op3ab0, Op3ab8, + Op3ac0, Op3ac8, Op3ad0, Op3ad8, Op3ae0, Op3ae8, Op3af0, Op3af8, + Op3b00, Op3b08, Op3b10, Op3b18, Op3b20, Op3b28, Op3b30, Op3b38, + Op3b40, Op3b48, Op3b50, Op3b58, Op3b60, Op3b68, Op3b70, Op3b78, + Op3b80, Op3b88, Op3b90, Op3b98, Op3ba0, Op3ba8, Op3bb0, Op3bb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3c00, Op3c08, Op3c10, Op3c18, Op3c20, Op3c28, Op3c30, Op3c38, + Op3c40, Op3c48, Op3c50, Op3c58, Op3c60, Op3c68, Op3c70, Op3c78, + Op3c80, Op3c88, Op3c90, Op3c98, Op3ca0, Op3ca8, Op3cb0, Op3cb8, + Op3cc0, Op3cc8, Op3cd0, Op3cd8, Op3ce0, Op3ce8, Op3cf0, Op3cf8, + Op3d00, Op3d08, Op3d10, Op3d18, Op3d20, Op3d28, Op3d30, Op3d38, + Op3d40, Op3d48, Op3d50, Op3d58, Op3d60, Op3d68, Op3d70, Op3d78, + Op3d80, Op3d88, Op3d90, Op3d98, Op3da0, Op3da8, Op3db0, Op3db8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3e00, Op3e08, Op3e10, Op3e18, Op3e20, Op3e28, Op3e30, Op3e38, + Op3e40, Op3e48, Op3e50, Op3e58, Op3e60, Op3e68, Op3e70, Op3e78, + Op3e80, Op3e88, Op3e90, Op3e98, Op3ea0, Op3ea8, Op3eb0, Op3eb8, + Op3ec0, Op3ec8, Op3ed0, Op3ed8, Op3ee0, Op3ee8, Op3ef0, Op3ef8, + Op3f00, Op3f08, Op3f10, Op3f18, Op3f20, Op3f28, Op3f30, Op3f38, + Op3f40, Op3f48, Op3f50, Op3f58, Op3f60, Op3f68, Op3f70, Op3f78, + Op3f80, Op3f88, Op3f90, Op3f98, Op3fa0, Op3fa8, Op3fb0, Op3fb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 4000 */ + Op4000, IllIns, Op4010, Op4018, Op4020, Op4028, Op4030, Op4038, + Op4040, IllIns, Op4050, Op4058, Op4060, Op4068, Op4070, Op4078, + Op4080, IllIns, Op4090, Op4098, Op40a0, Op40a8, Op40b0, Op40b8, + Op40c0, IllIns, Op40d0, Op40d8, Op40e0, Op40e8, Op40f0, Op40f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4180, IllIns, Op4190, Op4198, Op41a0, Op41a8, Op41b0, Op41b8, + IllIns, IllIns, Op41d0, IllIns, IllIns, Op41e8, Op41f0, Op41f8, + Op4200, IllIns, Op4210, Op4218, Op4220, Op4228, Op4230, Op4238, + Op4240, IllIns, Op4250, Op4258, Op4260, Op4268, Op4270, Op4278, + Op4280, IllIns, Op4290, Op4298, Op42a0, Op42a8, Op42b0, Op42b8, + Op42c0, IllIns, Op42d0, Op42d8, Op42e0, Op42e8, Op42f0, Op42f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4380, IllIns, Op4390, Op4398, Op43a0, Op43a8, Op43b0, Op43b8, + IllIns, IllIns, Op43d0, IllIns, IllIns, Op43e8, Op43f0, Op43f8, + Op4400, IllIns, Op4410, Op4418, Op4420, Op4428, Op4430, Op4438, + Op4440, IllIns, Op4450, Op4458, Op4460, Op4468, Op4470, Op4478, + Op4480, IllIns, Op4490, Op4498, Op44a0, Op44a8, Op44b0, Op44b8, + Op44c0, IllIns, Op44d0, Op44d8, Op44e0, Op44e8, Op44f0, Op44f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4580, IllIns, Op4590, Op4598, Op45a0, Op45a8, Op45b0, Op45b8, + IllIns, IllIns, Op45d0, IllIns, IllIns, Op45e8, Op45f0, Op45f8, + Op4600, IllIns, Op4610, Op4618, Op4620, Op4628, Op4630, Op4638, + Op4640, IllIns, Op4650, Op4658, Op4660, Op4668, Op4670, Op4678, + Op4680, IllIns, Op4690, Op4698, Op46a0, Op46a8, Op46b0, Op46b8, + Op46c0, IllIns, Op46d0, Op46d8, Op46e0, Op46e8, Op46f0, Op46f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4780, IllIns, Op4790, Op4798, Op47a0, Op47a8, Op47b0, Op47b8, + IllIns, IllIns, Op47d0, IllIns, IllIns, Op47e8, Op47f0, Op47f8, + Op4800, IllIns, Op4810, Op4818, Op4820, Op4828, Op4830, Op4838, + Op4840, Op4848, Op4850, IllIns, IllIns, Op4868, Op4870, Op4878, + Op4880, IllIns, Op4890, IllIns, Op48a0, Op48a8, Op48b0, Op48b8, + Op48c0, IllIns, Op48d0, IllIns, Op48e0, Op48e8, Op48f0, Op48f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4980, IllIns, Op4990, Op4998, Op49a0, Op49a8, Op49b0, Op49b8, + IllIns, IllIns, Op49d0, IllIns, IllIns, Op49e8, Op49f0, Op49f8, + Op4a00, IllIns, Op4a10, Op4a18, Op4a20, Op4a28, Op4a30, Op4a38, + Op4a40, IllIns, Op4a50, Op4a58, Op4a60, Op4a68, Op4a70, Op4a78, + Op4a80, IllIns, Op4a90, Op4a98, Op4aa0, Op4aa8, Op4ab0, Op4ab8, + Op4ac0, IllIns, Op4ad0, Op4ad8, Op4ae0, Op4ae8, Op4af0, Op4af8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4b80, IllIns, Op4b90, Op4b98, Op4ba0, Op4ba8, Op4bb0, Op4bb8, + IllIns, IllIns, Op4bd0, IllIns, IllIns, Op4be8, Op4bf0, Op4bf8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, Op4c90, Op4c98, IllIns, Op4ca8, Op4cb8, Op4cb8, + IllIns, IllIns, Op4cd0, Op4cd8, IllIns, Op4ce8, Op4cf0, Op4cf8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4d80, IllIns, Op4d90, Op4d98, Op4da0, Op4da8, Op4db0, Op4db8, + IllIns, IllIns, Op4dd0, IllIns, IllIns, Op4de8, Op4df0, Op4df8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4e40, Op4e40, Op4e50, Op4e58, Op4e60, Op4e68, Op4e70, Op4e78, + IllIns, IllIns, Op4e90, IllIns, IllIns, Op4ea8, Op4eb0, Op4eb8, + IllIns, IllIns, Op4ed0, IllIns, IllIns, Op4ee8, Op4ef0, Op4ef8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4f80, IllIns, Op4f90, Op4f98, Op4fa0, Op4fa8, Op4fb0, Op4fb8, + IllIns, IllIns, Op4fd0, IllIns, IllIns, Op4fe8, Op4ff0, Op4ff8, + + /* 5000 */ + Op5000, IllIns, Op5010, Op5018, Op5020, Op5028, Op5030, Op5038, + Op5040, Op5048, Op5050, Op5058, Op5060, Op5068, Op5070, Op5078, + Op5080, Op5088, Op5090, Op5098, Op50a0, Op50a8, Op50b0, Op50b8, + Op50c0, Op50c8, Op50d0, Op50d8, Op50e0, Op50e8, Op50f0, Op50f8, + Op5100, IllIns, Op5110, Op5118, Op5120, Op5128, Op5130, Op5138, + Op5140, Op5148, Op5150, Op5158, Op5160, Op5168, Op5170, Op5178, + Op5180, Op5188, Op5190, Op5198, Op51a0, Op51a8, Op51b0, Op51b8, + Op51c0, Op51c8, Op51d0, Op51d8, Op51e0, Op51e8, Op51f0, Op51f8, + Op5200, IllIns, Op5210, Op5218, Op5220, Op5228, Op5230, Op5238, + Op5240, Op5248, Op5250, Op5258, Op5260, Op5268, Op5270, Op5278, + Op5280, Op5288, Op5290, Op5298, Op52a0, Op52a8, Op52b0, Op52b8, + Op52c0, Op52c8, Op52d0, Op52d8, Op52e0, Op52e8, Op52f0, Op52f8, + Op5300, IllIns, Op5310, Op5318, Op5320, Op5328, Op5330, Op5338, + Op5340, Op5348, Op5350, Op5358, Op5360, Op5368, Op5370, Op5378, + Op5380, Op5388, Op5390, Op5398, Op53a0, Op53a8, Op53b0, Op53b8, + Op53c0, Op53c8, Op53d0, Op53d8, Op53e0, Op53e8, Op53f0, Op53f8, + Op5400, IllIns, Op5410, Op5418, Op5420, Op5428, Op5430, Op5438, + Op5440, Op5448, Op5450, Op5458, Op5460, Op5468, Op5470, Op5478, + Op5480, Op5488, Op5490, Op5498, Op54a0, Op54a8, Op54b0, Op54b8, + Op54c0, Op54c8, Op54d0, Op54d8, Op54e0, Op54e8, Op54f0, Op54f8, + Op5500, IllIns, Op5510, Op5518, Op5520, Op5528, Op5530, Op5538, + Op5540, Op5548, Op5550, Op5558, Op5560, Op5568, Op5570, Op5578, + Op5580, Op5588, Op5590, Op5598, Op55a0, Op55a8, Op55b0, Op55b8, + Op55c0, Op55c8, Op55d0, Op55d8, Op55e0, Op55e8, Op55f0, Op55f8, + Op5600, IllIns, Op5610, Op5618, Op5620, Op5628, Op5630, Op5638, + Op5640, Op5648, Op5650, Op5658, Op5660, Op5668, Op5670, Op5678, + Op5680, Op5688, Op5690, Op5698, Op56a0, Op56a8, Op56b0, Op56b8, + Op56c0, Op56c8, Op56d0, Op56d8, Op56e0, Op56e8, Op56f0, Op56f8, + Op5700, IllIns, Op5710, Op5718, Op5720, Op5728, Op5730, Op5738, + Op5740, Op5748, Op5750, Op5758, Op5760, Op5768, Op5770, Op5778, + Op5780, Op5788, Op5790, Op5798, Op57a0, Op57a8, Op57b0, Op57b8, + Op57c0, Op57c8, Op57d0, Op57d8, Op57e0, Op57e8, Op57f0, Op57f8, + Op5800, IllIns, Op5810, Op5818, Op5820, Op5828, Op5830, Op5838, + Op5840, Op5848, Op5850, Op5858, Op5860, Op5868, Op5870, Op5878, + Op5880, Op5888, Op5890, Op5898, Op58a0, Op58a8, Op58b0, Op58b8, + Op58c0, Op58c8, Op58d0, Op58d8, Op58e0, Op58e8, Op58f0, Op58f8, + Op5900, IllIns, Op5910, Op5918, Op5920, Op5928, Op5930, Op5938, + Op5940, Op5948, Op5950, Op5958, Op5960, Op5968, Op5970, Op5978, + Op5980, Op5988, Op5990, Op5998, Op59a0, Op59a8, Op59b0, Op59b8, + Op59c0, Op59c8, Op59d0, Op59d8, Op59e0, Op59e8, Op59f0, Op59f8, + Op5a00, IllIns, Op5a10, Op5a18, Op5a20, Op5a28, Op5a30, Op5a38, + Op5a40, Op5a48, Op5a50, Op5a58, Op5a60, Op5a68, Op5a70, Op5a78, + Op5a80, Op5a88, Op5a90, Op5a98, Op5aa0, Op5aa8, Op5ab0, Op5ab8, + Op5ac0, Op5ac8, Op5ad0, Op5ad8, Op5ae0, Op5ae8, Op5af0, Op5af8, + Op5b00, IllIns, Op5b10, Op5b18, Op5b20, Op5b28, Op5b30, Op5b38, + Op5b40, Op5b48, Op5b50, Op5b58, Op5b60, Op5b68, Op5b70, Op5b78, + Op5b80, Op5b88, Op5b90, Op5b98, Op5ba0, Op5ba8, Op5bb0, Op5bb8, + Op5bc0, Op5bc8, Op5bd0, Op5bd8, Op5be0, Op5be8, Op5bf0, Op5bf8, + Op5c00, IllIns, Op5c10, Op5c18, Op5c20, Op5c28, Op5c30, Op5c38, + Op5c40, Op5c48, Op5c50, Op5c58, Op5c60, Op5c68, Op5c70, Op5c78, + Op5c80, Op5c88, Op5c90, Op5c98, Op5ca0, Op5ca8, Op5cb0, Op5cb8, + Op5cc0, Op5cc8, Op5cd0, Op5cd8, Op5ce0, Op5ce8, Op5cf0, Op5cf8, + Op5d00, IllIns, Op5d10, Op5d18, Op5d20, Op5d28, Op5d30, Op5d38, + Op5d40, Op5d48, Op5d50, Op5d58, Op5d60, Op5d68, Op5d70, Op5d78, + Op5d80, Op5d88, Op5d90, Op5d98, Op5da0, Op5da8, Op5db0, Op5db8, + Op5dc0, Op5dc8, Op5dd0, Op5dd8, Op5de0, Op5de8, Op5df0, Op5df8, + Op5e00, IllIns, Op5e10, Op5e18, Op5e20, Op5e28, Op5e30, Op5e38, + Op5e40, Op5e48, Op5e50, Op5e58, Op5e60, Op5e68, Op5e70, Op5e78, + Op5e80, Op5e88, Op5e90, Op5e98, Op5ea0, Op5ea8, Op5eb0, Op5eb8, + Op5ec0, Op5ec8, Op5ed0, Op5ed8, Op5ee0, Op5ee8, Op5ef0, Op5ef8, + Op5f00, IllIns, Op5f10, Op5f18, Op5f20, Op5f28, Op5f30, Op5f38, + Op5f40, Op5f48, Op5f50, Op5f58, Op5f60, Op5f68, Op5f70, Op5f78, + Op5f80, Op5f88, Op5f90, Op5f98, Op5fa0, Op5fa8, Op5fb0, Op5fb8, + Op5fc0, Op5fc8, Op5fd0, Op5fd8, Op5fe0, Op5fe8, Op5ff0, Op5ff8, + + /* 6000 */ + Op6000, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6100, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6200, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6300, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6400, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6500, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6600, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6700, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6800, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6900, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6a00, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6b00, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6c00, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6d00, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6e00, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6f00, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + + /* 7000 */ + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 8000 */ + Op8000, IllIns, Op8010, Op8018, Op8020, Op8028, Op8030, Op8038, + Op8040, IllIns, Op8050, Op8058, Op8060, Op8068, Op8070, Op8078, + Op8080, IllIns, Op8090, Op8098, Op80a0, Op80a8, Op80b0, Op80b8, + Op80c0, IllIns, Op80d0, Op80d8, Op80e0, Op80e8, Op80f0, Op80f8, + Op8100, Op8108, Op8110, Op8118, Op8120, Op8128, Op8130, Op8138, + IllIns, IllIns, Op8150, Op8158, Op8160, Op8168, Op8170, Op8178, + IllIns, IllIns, Op8190, Op8198, Op81a0, Op81a8, Op81b0, Op81b8, + Op81c0, IllIns, Op81d0, Op81d8, Op81e0, Op81e8, Op81f0, Op81f8, + Op8200, IllIns, Op8210, Op8218, Op8220, Op8228, Op8230, Op8238, + Op8240, IllIns, Op8250, Op8258, Op8260, Op8268, Op8270, Op8278, + Op8280, IllIns, Op8290, Op8298, Op82a0, Op82a8, Op82b0, Op82b8, + Op82c0, IllIns, Op82d0, Op82d8, Op82e0, Op82e8, Op82f0, Op82f8, + Op8300, Op8308, Op8310, Op8318, Op8320, Op8328, Op8330, Op8338, + IllIns, IllIns, Op8350, Op8358, Op8360, Op8368, Op8370, Op8378, + IllIns, IllIns, Op8390, Op8398, Op83a0, Op83a8, Op83b0, Op83b8, + Op83c0, IllIns, Op83d0, Op83d8, Op83e0, Op83e8, Op83f0, Op83f8, + Op8400, IllIns, Op8410, Op8418, Op8420, Op8428, Op8430, Op8438, + Op8440, IllIns, Op8450, Op8458, Op8460, Op8468, Op8470, Op8478, + Op8480, IllIns, Op8490, Op8498, Op84a0, Op84a8, Op84b0, Op84b8, + Op84c0, IllIns, Op84d0, Op84d8, Op84e0, Op84e8, Op84f0, Op84f8, + Op8500, Op8508, Op8510, Op8518, Op8520, Op8528, Op8530, Op8538, + IllIns, IllIns, Op8550, Op8558, Op8560, Op8568, Op8570, Op8578, + IllIns, IllIns, Op8590, Op8598, Op85a0, Op85a8, Op85b0, Op85b8, + Op85c0, IllIns, Op85d0, Op85d8, Op85e0, Op85e8, Op85f0, Op85f8, + Op8600, IllIns, Op8610, Op8618, Op8620, Op8628, Op8630, Op8638, + Op8640, IllIns, Op8650, Op8658, Op8660, Op8668, Op8670, Op8678, + Op8680, IllIns, Op8690, Op8698, Op86a0, Op86a8, Op86b0, Op86b8, + Op86c0, IllIns, Op86d0, Op86d8, Op86e0, Op86e8, Op86f0, Op86f8, + Op8700, Op8708, Op8710, Op8718, Op8720, Op8728, Op8730, Op8738, + IllIns, IllIns, Op8750, Op8758, Op8760, Op8768, Op8770, Op8778, + IllIns, IllIns, Op8790, Op8798, Op87a0, Op87a8, Op87b0, Op87b8, + Op87c0, IllIns, Op87d0, Op87d8, Op87e0, Op87e8, Op87f0, Op87f8, + Op8800, IllIns, Op8810, Op8818, Op8820, Op8828, Op8830, Op8838, + Op8840, IllIns, Op8850, Op8858, Op8860, Op8868, Op8870, Op8878, + Op8880, IllIns, Op8890, Op8898, Op88a0, Op88a8, Op88b0, Op88b8, + Op88c0, IllIns, Op88d0, Op88d8, Op88e0, Op88e8, Op88f0, Op88f8, + Op8900, Op8908, Op8910, Op8918, Op8920, Op8928, Op8930, Op8938, + IllIns, IllIns, Op8950, Op8958, Op8960, Op8968, Op8970, Op8978, + IllIns, IllIns, Op8990, Op8998, Op89a0, Op89a8, Op89b0, Op89b8, + Op89c0, IllIns, Op89d0, Op89d8, Op89e0, Op89e8, Op89f0, Op89f8, + Op8a00, IllIns, Op8a10, Op8a18, Op8a20, Op8a28, Op8a30, Op8a38, + Op8a40, IllIns, Op8a50, Op8a58, Op8a60, Op8a68, Op8a70, Op8a78, + Op8a80, IllIns, Op8a90, Op8a98, Op8aa0, Op8aa8, Op8ab0, Op8ab8, + Op8ac0, IllIns, Op8ad0, Op8ad8, Op8ae0, Op8ae8, Op8af0, Op8af8, + Op8b00, Op8b08, Op8b10, Op8b18, Op8b20, Op8b28, Op8b30, Op8b38, + IllIns, IllIns, Op8b50, Op8b58, Op8b60, Op8b68, Op8b70, Op8b78, + IllIns, IllIns, Op8b90, Op8b98, Op8ba0, Op8ba8, Op8bb0, Op8bb8, + Op8bc0, IllIns, Op8bd0, Op8bd8, Op8be0, Op8be8, Op8bf0, Op8bf8, + Op8c00, IllIns, Op8c10, Op8c18, Op8c20, Op8c28, Op8c30, Op8c38, + Op8c40, IllIns, Op8c50, Op8c58, Op8c60, Op8c68, Op8c70, Op8c78, + Op8c80, IllIns, Op8c90, Op8c98, Op8ca0, Op8ca8, Op8cb0, Op8cb8, + Op8cc0, IllIns, Op8cd0, Op8cd8, Op8ce0, Op8ce8, Op8cf0, Op8cf8, + Op8d00, Op8d08, Op8d10, Op8d18, Op8d20, Op8d28, Op8d30, Op8d38, + IllIns, IllIns, Op8d50, Op8d58, Op8d60, Op8d68, Op8d70, Op8d78, + IllIns, IllIns, Op8d90, Op8d98, Op8da0, Op8da8, Op8db0, Op8db8, + Op8dc0, IllIns, Op8dd0, Op8dd8, Op8de0, Op8de8, Op8df0, Op8df8, + Op8e00, IllIns, Op8e10, Op8e18, Op8e20, Op8e28, Op8e30, Op8e38, + Op8e40, IllIns, Op8e50, Op8e58, Op8e60, Op8e68, Op8e70, Op8e78, + Op8e80, IllIns, Op8e90, Op8e98, Op8ea0, Op8ea8, Op8eb0, Op8eb8, + Op8ec0, IllIns, Op8ed0, Op8ed8, Op8ee0, Op8ee8, Op8ef0, Op8ef8, + Op8f00, Op8f08, Op8f10, Op8f18, Op8f20, Op8f28, Op8f30, Op8f38, + IllIns, IllIns, Op8f50, Op8f58, Op8f60, Op8f68, Op8f70, Op8f78, + IllIns, IllIns, Op8f90, Op8f98, Op8fa0, Op8fa8, Op8fb0, Op8fb8, + Op8fc0, IllIns, Op8fd0, Op8fd8, Op8fe0, Op8fe8, Op8ff0, Op8ff8, + + /* 9000 */ + Op9000, IllIns, Op9010, Op9018, Op9020, Op9028, Op9030, Op9038, + Op9040, Op9048, Op9050, Op9058, Op9060, Op9068, Op9070, Op9078, + Op9080, Op9088, Op9090, Op9098, Op90a0, Op90a8, Op90b0, Op90b8, + Op90c0, Op90c8, Op90d0, Op90d8, Op90e0, Op90e8, Op90f0, Op90f8, + Op9100, Op9108, Op9110, Op9118, Op9120, Op9128, Op9130, Op9138, + Op9140, Op9148, Op9150, Op9158, Op9160, Op9168, Op9170, Op9178, + Op9180, Op9188, Op9190, Op9198, Op91a0, Op91a8, Op91b0, Op91b8, + Op91c0, Op91c8, Op91d0, Op91d8, Op91e0, Op91e8, Op91f0, Op91f8, + Op9200, IllIns, Op9210, Op9218, Op9220, Op9228, Op9230, Op9238, + Op9240, Op9248, Op9250, Op9258, Op9260, Op9268, Op9270, Op9278, + Op9280, Op9288, Op9290, Op9298, Op92a0, Op92a8, Op92b0, Op92b8, + Op92c0, Op92c8, Op92d0, Op92d8, Op92e0, Op92e8, Op92f0, Op92f8, + Op9300, Op9308, Op9310, Op9318, Op9320, Op9328, Op9330, Op9338, + Op9340, Op9348, Op9350, Op9358, Op9360, Op9368, Op9370, Op9378, + Op9380, Op9388, Op9390, Op9398, Op93a0, Op93a8, Op93b0, Op93b8, + Op93c0, Op93c8, Op93d0, Op93d8, Op93e0, Op93e8, Op93f0, Op93f8, + Op9400, IllIns, Op9410, Op9418, Op9420, Op9428, Op9430, Op9438, + Op9440, Op9448, Op9450, Op9458, Op9460, Op9468, Op9470, Op9478, + Op9480, Op9488, Op9490, Op9498, Op94a0, Op94a8, Op94b0, Op94b8, + Op94c0, Op94c8, Op94d0, Op94d8, Op94e0, Op94e8, Op94f0, Op94f8, + Op9500, Op9508, Op9510, Op9518, Op9520, Op9528, Op9530, Op9538, + Op9540, Op9548, Op9550, Op9558, Op9560, Op9568, Op9570, Op9578, + Op9580, Op9588, Op9590, Op9598, Op95a0, Op95a8, Op95b0, Op95b8, + Op95c0, Op95c8, Op95d0, Op95d8, Op95e0, Op95e8, Op95f0, Op95f8, + Op9600, IllIns, Op9610, Op9618, Op9620, Op9628, Op9630, Op9638, + Op9640, Op9648, Op9650, Op9658, Op9660, Op9668, Op9670, Op9678, + Op9680, Op9688, Op9690, Op9698, Op96a0, Op96a8, Op96b0, Op96b8, + Op96c0, Op96c8, Op96d0, Op96d8, Op96e0, Op96e8, Op96f0, Op96f8, + Op9700, Op9708, Op9710, Op9718, Op9720, Op9728, Op9730, Op9738, + Op9740, Op9748, Op9750, Op9758, Op9760, Op9768, Op9770, Op9778, + Op9780, Op9788, Op9790, Op9798, Op97a0, Op97a8, Op97b0, Op97b8, + Op97c0, Op97c8, Op97d0, Op97d8, Op97e0, Op97e8, Op97f0, Op97f8, + Op9800, IllIns, Op9810, Op9818, Op9820, Op9828, Op9830, Op9838, + Op9840, Op9848, Op9850, Op9858, Op9860, Op9868, Op9870, Op9878, + Op9880, Op9888, Op9890, Op9898, Op98a0, Op98a8, Op98b0, Op98b8, + Op98c0, Op98c8, Op98d0, Op98d8, Op98e0, Op98e8, Op98f0, Op98f8, + Op9900, Op9908, Op9910, Op9918, Op9920, Op9928, Op9930, Op9938, + Op9940, Op9948, Op9950, Op9958, Op9960, Op9968, Op9970, Op9978, + Op9980, Op9988, Op9990, Op9998, Op99a0, Op99a8, Op99b0, Op99b8, + Op99c0, Op99c8, Op99d0, Op99d8, Op99e0, Op99e8, Op99f0, Op99f8, + Op9a00, IllIns, Op9a10, Op9a18, Op9a20, Op9a28, Op9a30, Op9a38, + Op9a40, Op9a48, Op9a50, Op9a58, Op9a60, Op9a68, Op9a70, Op9a78, + Op9a80, Op9a88, Op9a90, Op9a98, Op9aa0, Op9aa8, Op9ab0, Op9ab8, + Op9ac0, Op9ac8, Op9ad0, Op9ad8, Op9ae0, Op9ae8, Op9af0, Op9af8, + Op9b00, Op9b08, Op9b10, Op9b18, Op9b20, Op9b28, Op9b30, Op9b38, + Op9b40, Op9b48, Op9b50, Op9b58, Op9b60, Op9b68, Op9b70, Op9b78, + Op9b80, Op9b88, Op9b90, Op9b98, Op9ba0, Op9ba8, Op9bb0, Op9bb8, + Op9bc0, Op9bc8, Op9bd0, Op9bd8, Op9be0, Op9be8, Op9bf0, Op9bf8, + Op9c00, IllIns, Op9c10, Op9c18, Op9c20, Op9c28, Op9c30, Op9c38, + Op9c40, Op9c48, Op9c50, Op9c58, Op9c60, Op9c68, Op9c70, Op9c78, + Op9c80, Op9c88, Op9c90, Op9c98, Op9ca0, Op9ca8, Op9cb0, Op9cb8, + Op9cc0, Op9cc8, Op9cd0, Op9cd8, Op9ce0, Op9ce8, Op9cf0, Op9cf8, + Op9d00, Op9d08, Op9d10, Op9d18, Op9d20, Op9d28, Op9d30, Op9d38, + Op9d40, Op9d48, Op9d50, Op9d58, Op9d60, Op9d68, Op9d70, Op9d78, + Op9d80, Op9d88, Op9d90, Op9d98, Op9da0, Op9da8, Op9db0, Op9db8, + Op9dc0, Op9dc8, Op9dd0, Op9dd8, Op9de0, Op9de8, Op9df0, Op9df8, + Op9e00, IllIns, Op9e10, Op9e18, Op9e20, Op9e28, Op9e30, Op9e38, + Op9e40, Op9e48, Op9e50, Op9e58, Op9e60, Op9e68, Op9e70, Op9e78, + Op9e80, Op9e88, Op9e90, Op9e98, Op9ea0, Op9ea8, Op9eb0, Op9eb8, + Op9ec0, Op9ec8, Op9ed0, Op9ed8, Op9ee0, Op9ee8, Op9ef0, Op9ef8, + Op9f00, Op9f08, Op9f10, Op9f18, Op9f20, Op9f28, Op9f30, Op9f38, + Op9f40, Op9f48, Op9f50, Op9f58, Op9f60, Op9f68, Op9f70, Op9f78, + Op9f80, Op9f88, Op9f90, Op9f98, Op9fa0, Op9fa8, Op9fb0, Op9fb8, + Op9fc0, Op9fc8, Op9fd0, Op9fd8, Op9fe0, Op9fe8, Op9ff0, Op9ff8, + + /* A000 */ + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + + /* B000 */ + Opb000, IllIns, Opb010, Opb018, Opb020, Opb028, Opb030, Opb038, + Opb040, Opb048, Opb050, Opb058, Opb060, Opb068, Opb070, Opb078, + Opb080, Opb088, Opb090, Opb098, Opb0a0, Opb0a8, Opb0b0, Opb0b8, + Opb0c0, Opb0c8, Opb0d0, Opb0d8, Opb0e0, Opb0e8, Opb0f0, Opb0f8, + Opb100, Opb108, Opb110, Opb118, Opb120, Opb128, Opb130, Opb138, + Opb140, Opb148, Opb150, Opb158, Opb160, Opb168, Opb170, Opb178, + Opb180, Opb188, Opb190, Opb198, Opb1a0, Opb1a8, Opb1b0, Opb1b8, + Opb1c0, Opb1c8, Opb1d0, Opb1d8, Opb1e0, Opb1e8, Opb1f0, Opb1f8, + Opb200, IllIns, Opb210, Opb218, Opb220, Opb228, Opb230, Opb238, + Opb240, Opb248, Opb250, Opb258, Opb260, Opb268, Opb270, Opb278, + Opb280, Opb288, Opb290, Opb298, Opb2a0, Opb2a8, Opb2b0, Opb2b8, + Opb2c0, Opb2c8, Opb2d0, Opb2d8, Opb2e0, Opb2e8, Opb2f0, Opb2f8, + Opb300, Opb308, Opb310, Opb318, Opb320, Opb328, Opb330, Opb338, + Opb340, Opb348, Opb350, Opb358, Opb360, Opb368, Opb370, Opb378, + Opb380, Opb388, Opb390, Opb398, Opb3a0, Opb3a8, Opb3b0, Opb3b8, + Opb3c0, Opb3c8, Opb3d0, Opb3d8, Opb3e0, Opb3e8, Opb3f0, Opb3f8, + Opb400, IllIns, Opb410, Opb418, Opb420, Opb428, Opb430, Opb438, + Opb440, Opb448, Opb450, Opb458, Opb460, Opb468, Opb470, Opb478, + Opb480, Opb488, Opb490, Opb498, Opb4a0, Opb4a8, Opb4b0, Opb4b8, + Opb4c0, Opb4c8, Opb4d0, Opb4d8, Opb4e0, Opb4e8, Opb4f0, Opb4f8, + Opb500, Opb508, Opb510, Opb518, Opb520, Opb528, Opb530, Opb538, + Opb540, Opb548, Opb550, Opb558, Opb560, Opb568, Opb570, Opb578, + Opb580, Opb588, Opb590, Opb598, Opb5a0, Opb5a8, Opb5b0, Opb5b8, + Opb5c0, Opb5c8, Opb5d0, Opb5d8, Opb5e0, Opb5e8, Opb5f0, Opb5f8, + Opb600, IllIns, Opb610, Opb618, Opb620, Opb628, Opb630, Opb638, + Opb640, Opb648, Opb650, Opb658, Opb660, Opb668, Opb670, Opb678, + Opb680, Opb688, Opb690, Opb698, Opb6a0, Opb6a8, Opb6b0, Opb6b8, + Opb6c0, Opb6c8, Opb6d0, Opb6d8, Opb6e0, Opb6e8, Opb6f0, Opb6f8, + Opb700, Opb708, Opb710, Opb718, Opb720, Opb728, Opb730, Opb738, + Opb740, Opb748, Opb750, Opb758, Opb760, Opb768, Opb770, Opb778, + Opb780, Opb788, Opb790, Opb798, Opb7a0, Opb7a8, Opb7b0, Opb7b8, + Opb7c0, Opb7c8, Opb7d0, Opb7d8, Opb7e0, Opb7e8, Opb7f0, Opb7f8, + Opb800, IllIns, Opb810, Opb818, Opb820, Opb828, Opb830, Opb838, + Opb840, Opb848, Opb850, Opb858, Opb860, Opb868, Opb870, Opb878, + Opb880, Opb888, Opb890, Opb898, Opb8a0, Opb8a8, Opb8b0, Opb8b8, + Opb8c0, Opb8c8, Opb8d0, Opb8d8, Opb8e0, Opb8e8, Opb8f0, Opb8f8, + Opb900, Opb908, Opb910, Opb918, Opb920, Opb928, Opb930, Opb938, + Opb940, Opb948, Opb950, Opb958, Opb960, Opb968, Opb970, Opb978, + Opb980, Opb988, Opb990, Opb998, Opb9a0, Opb9a8, Opb9b0, Opb9b8, + Opb9c0, Opb9c8, Opb9d0, Opb9d8, Opb9e0, Opb9e8, Opb9f0, Opb9f8, + Opba00, IllIns, Opba10, Opba18, Opba20, Opba28, Opba30, Opba38, + Opba40, Opba48, Opba50, Opba58, Opba60, Opba68, Opba70, Opba78, + Opba80, Opba88, Opba90, Opba98, Opbaa0, Opbaa8, Opbab0, Opbab8, + Opbac0, Opbac8, Opbad0, Opbad8, Opbae0, Opbae8, Opbaf0, Opbaf8, + Opbb00, Opbb08, Opbb10, Opbb18, Opbb20, Opbb28, Opbb30, Opbb38, + Opbb40, Opbb48, Opbb50, Opbb58, Opbb60, Opbb68, Opbb70, Opbb78, + Opbb80, Opbb88, Opbb90, Opbb98, Opbba0, Opbba8, Opbbb0, Opbbb8, + Opbbc0, Opbbc8, Opbbd0, Opbbd8, Opbbe0, Opbbe8, Opbbf0, Opbbf8, + Opbc00, IllIns, Opbc10, Opbc18, Opbc20, Opbc28, Opbc30, Opbc38, + Opbc40, Opbc48, Opbc50, Opbc58, Opbc60, Opbc68, Opbc70, Opbc78, + Opbc80, Opbc88, Opbc90, Opbc98, Opbca0, Opbca8, Opbcb0, Opbcb8, + Opbcc0, Opbcc8, Opbcd0, Opbcd8, Opbce0, Opbce8, Opbcf0, Opbcf8, + Opbd00, Opbd08, Opbd10, Opbd18, Opbd20, Opbd28, Opbd30, Opbd38, + Opbd40, Opbd48, Opbd50, Opbd58, Opbd60, Opbd68, Opbd70, Opbd78, + Opbd80, Opbd88, Opbd90, Opbd98, Opbda0, Opbda8, Opbdb0, Opbdb8, + Opbdc0, Opbdc8, Opbdd0, Opbdd8, Opbde0, Opbde8, Opbdf0, Opbdf8, + Opbe00, IllIns, Opbe10, Opbe18, Opbe20, Opbe28, Opbe30, Opbe38, + Opbe40, Opbe48, Opbe50, Opbe58, Opbe60, Opbe68, Opbe70, Opbe78, + Opbe80, Opbe88, Opbe90, Opbe98, Opbea0, Opbea8, Opbeb0, Opbeb8, + Opbec0, Opbec8, Opbed0, Opbed8, Opbee0, Opbee8, Opbef0, Opbef8, + Opbf00, Opbf08, Opbf10, Opbf18, Opbf20, Opbf28, Opbf30, Opbf38, + Opbf40, Opbf48, Opbf50, Opbf58, Opbf60, Opbf68, Opbf70, Opbf78, + Opbf80, Opbf88, Opbf90, Opbf98, Opbfa0, Opbfa8, Opbfb0, Opbfb8, + Opbfc0, Opbfc8, Opbfd0, Opbfd8, Opbfe0, Opbfe8, Opbff0, Opbff8, + + /* C000 */ + Opc000, IllIns, Opc010, Opc018, Opc020, Opc028, Opc030, Opc038, + Opc040, IllIns, Opc050, Opc058, Opc060, Opc068, Opc070, Opc078, + Opc080, IllIns, Opc090, Opc098, Opc0a0, Opc0a8, Opc0b0, Opc0b8, + Opc0c0, IllIns, Opc0d0, Opc0d8, Opc0e0, Opc0e8, Opc0f0, Opc0f8, + Opc100, Opc108, Opc110, Opc118, Opc120, Opc128, Opc130, Opc138, + Opc140, Opc148, Opc150, Opc158, Opc160, Opc168, Opc170, Opc178, + IllIns, Opc188, Opc190, Opc198, Opc1a0, Opc1a8, Opc1b0, Opc1b8, + Opc1c0, IllIns, Opc1d0, Opc1d8, Opc1e0, Opc1e8, Opc1f0, Opc1f8, + Opc200, IllIns, Opc210, Opc218, Opc220, Opc228, Opc230, Opc238, + Opc240, IllIns, Opc250, Opc258, Opc260, Opc268, Opc270, Opc278, + Opc280, IllIns, Opc290, Opc298, Opc2a0, Opc2a8, Opc2b0, Opc2b8, + Opc2c0, IllIns, Opc2d0, Opc2d8, Opc2e0, Opc2e8, Opc2f0, Opc2f8, + Opc300, Opc308, Opc310, Opc318, Opc320, Opc328, Opc330, Opc338, + Opc340, Opc348, Opc350, Opc358, Opc360, Opc368, Opc370, Opc378, + IllIns, Opc388, Opc390, Opc398, Opc3a0, Opc3a8, Opc3b0, Opc3b8, + Opc3c0, IllIns, Opc3d0, Opc3d8, Opc3e0, Opc3e8, Opc3f0, Opc3f8, + Opc400, IllIns, Opc410, Opc418, Opc420, Opc428, Opc430, Opc438, + Opc440, IllIns, Opc450, Opc458, Opc460, Opc468, Opc470, Opc478, + Opc480, IllIns, Opc490, Opc498, Opc4a0, Opc4a8, Opc4b0, Opc4b8, + Opc4c0, IllIns, Opc4d0, Opc4d8, Opc4e0, Opc4e8, Opc4f0, Opc4f8, + Opc500, Opc508, Opc510, Opc518, Opc520, Opc528, Opc530, Opc538, + Opc540, Opc548, Opc550, Opc558, Opc560, Opc568, Opc570, Opc578, + IllIns, Opc588, Opc590, Opc598, Opc5a0, Opc5a8, Opc5b0, Opc5b8, + Opc5c0, IllIns, Opc5d0, Opc5d8, Opc5e0, Opc5e8, Opc5f0, Opc5f8, + Opc600, IllIns, Opc610, Opc618, Opc620, Opc628, Opc630, Opc638, + Opc640, IllIns, Opc650, Opc658, Opc660, Opc668, Opc670, Opc678, + Opc680, IllIns, Opc690, Opc698, Opc6a0, Opc6a8, Opc6b0, Opc6b8, + Opc6c0, IllIns, Opc6d0, Opc6d8, Opc6e0, Opc6e8, Opc6f0, Opc6f8, + Opc700, Opc708, Opc710, Opc718, Opc720, Opc728, Opc730, Opc738, + Opc740, Opc748, Opc750, Opc758, Opc760, Opc768, Opc770, Opc778, + IllIns, Opc788, Opc790, Opc798, Opc7a0, Opc7a8, Opc7b0, Opc7b8, + Opc7c0, IllIns, Opc7d0, Opc7d8, Opc7e0, Opc7e8, Opc7f0, Opc7f8, + Opc800, IllIns, Opc810, Opc818, Opc820, Opc828, Opc830, Opc838, + Opc840, IllIns, Opc850, Opc858, Opc860, Opc868, Opc870, Opc878, + Opc880, IllIns, Opc890, Opc898, Opc8a0, Opc8a8, Opc8b0, Opc8b8, + Opc8c0, IllIns, Opc8d0, Opc8d8, Opc8e0, Opc8e8, Opc8f0, Opc8f8, + Opc900, Opc908, Opc910, Opc918, Opc920, Opc928, Opc930, Opc938, + Opc940, Opc948, Opc950, Opc958, Opc960, Opc968, Opc970, Opc978, + IllIns, Opc988, Opc990, Opc998, Opc9a0, Opc9a8, Opc9b0, Opc9b8, + Opc9c0, IllIns, Opc9d0, Opc9d8, Opc9e0, Opc9e8, Opc9f0, Opc9f8, + Opca00, IllIns, Opca10, Opca18, Opca20, Opca28, Opca30, Opca38, + Opca40, IllIns, Opca50, Opca58, Opca60, Opca68, Opca70, Opca78, + Opca80, IllIns, Opca90, Opca98, Opcaa0, Opcaa8, Opcab0, Opcab8, + Opcac0, IllIns, Opcad0, Opcad8, Opcae0, Opcae8, Opcaf0, Opcaf8, + Opcb00, Opcb08, Opcb10, Opcb18, Opcb20, Opcb28, Opcb30, Opcb38, + Opcb40, Opcb48, Opcb50, Opcb58, Opcb60, Opcb68, Opcb70, Opcb78, + IllIns, Opcb88, Opcb90, Opcb98, Opcba0, Opcba8, Opcbb0, Opcbb8, + Opcbc0, IllIns, Opcbd0, Opcbd8, Opcbe0, Opcbe8, Opcbf0, Opcbf8, + Opcc00, IllIns, Opcc10, Opcc18, Opcc20, Opcc28, Opcc30, Opcc38, + Opcc40, IllIns, Opcc50, Opcc58, Opcc60, Opcc68, Opcc70, Opcc78, + Opcc80, IllIns, Opcc90, Opcc98, Opcca0, Opcca8, Opccb0, Opccb8, + Opccc0, IllIns, Opccd0, Opccd8, Opcce0, Opcce8, Opccf0, Opccf8, + Opcd00, Opcd08, Opcd10, Opcd18, Opcd20, Opcd28, Opcd30, Opcd38, + Opcd40, Opcd48, Opcd50, Opcd58, Opcd60, Opcd68, Opcd70, Opcd78, + IllIns, Opcd88, Opcd90, Opcd98, Opcda0, Opcda8, Opcdb0, Opcdb8, + Opcdc0, IllIns, Opcdd0, Opcdd8, Opcde0, Opcde8, Opcdf0, Opcdf8, + Opce00, IllIns, Opce10, Opce18, Opce20, Opce28, Opce30, Opce38, + Opce40, IllIns, Opce50, Opce58, Opce60, Opce68, Opce70, Opce78, + Opce80, IllIns, Opce90, Opce98, Opcea0, Opcea8, Opceb0, Opceb8, + Opcec0, IllIns, Opced0, Opced8, Opcee0, Opcee8, Opcef0, Opcef8, + Opcf00, Opcf08, Opcf10, Opcf18, Opcf20, Opcf28, Opcf30, Opcf38, + Opcf40, Opcf48, Opcf50, Opcf58, Opcf60, Opcf68, Opcf70, Opcf78, + IllIns, Opcf88, Opcf90, Opcf98, Opcfa0, Opcfa8, Opcfb0, Opcfb8, + Opcfc0, IllIns, Opcfd0, Opcfd8, Opcfe0, Opcfe8, Opcff0, Opcff8, + + /* D000 */ + Opd000, IllIns, Opd010, Opd018, Opd020, Opd028, Opd030, Opd038, + Opd040, Opd048, Opd050, Opd058, Opd060, Opd068, Opd070, Opd078, + Opd080, Opd088, Opd090, Opd098, Opd0a0, Opd0a8, Opd0b0, Opd0b8, + Opd0c0, Opd0c8, Opd0d0, Opd0d8, Opd0e0, Opd0e8, Opd0f0, Opd0f8, + Opd100, Opd108, Opd110, Opd118, Opd120, Opd128, Opd130, Opd138, + Opd140, Opd148, Opd150, Opd158, Opd160, Opd168, Opd170, Opd178, + Opd180, Opd188, Opd190, Opd198, Opd1a0, Opd1a8, Opd1b0, Opd1b8, + Opd1c0, Opd1c8, Opd1d0, Opd1d8, Opd1e0, Opd1e8, Opd1f0, Opd1f8, + Opd200, IllIns, Opd210, Opd218, Opd220, Opd228, Opd230, Opd238, + Opd240, Opd248, Opd250, Opd258, Opd260, Opd268, Opd270, Opd278, + Opd280, Opd288, Opd290, Opd298, Opd2a0, Opd2a8, Opd2b0, Opd2b8, + Opd2c0, Opd2c8, Opd2d0, Opd2d8, Opd2e0, Opd2e8, Opd2f0, Opd2f8, + Opd300, Opd308, Opd310, Opd318, Opd320, Opd328, Opd330, Opd338, + Opd340, Opd348, Opd350, Opd358, Opd360, Opd368, Opd370, Opd378, + Opd380, Opd388, Opd390, Opd398, Opd3a0, Opd3a8, Opd3b0, Opd3b8, + Opd3c0, Opd3c8, Opd3d0, Opd3d8, Opd3e0, Opd3e8, Opd3f0, Opd3f8, + Opd400, IllIns, Opd410, Opd418, Opd420, Opd428, Opd430, Opd438, + Opd440, Opd448, Opd450, Opd458, Opd460, Opd468, Opd470, Opd478, + Opd480, Opd488, Opd490, Opd498, Opd4a0, Opd4a8, Opd4b0, Opd4b8, + Opd4c0, Opd4c8, Opd4d0, Opd4d8, Opd4e0, Opd4e8, Opd4f0, Opd4f8, + Opd500, Opd508, Opd510, Opd518, Opd520, Opd528, Opd530, Opd538, + Opd540, Opd548, Opd550, Opd558, Opd560, Opd568, Opd570, Opd578, + Opd580, Opd588, Opd590, Opd598, Opd5a0, Opd5a8, Opd5b0, Opd5b8, + Opd5c0, Opd5c8, Opd5d0, Opd5d8, Opd5e0, Opd5e8, Opd5f0, Opd5f8, + Opd600, IllIns, Opd610, Opd618, Opd620, Opd628, Opd630, Opd638, + Opd640, Opd648, Opd650, Opd658, Opd660, Opd668, Opd670, Opd678, + Opd680, Opd688, Opd690, Opd698, Opd6a0, Opd6a8, Opd6b0, Opd6b8, + Opd6c0, Opd6c8, Opd6d0, Opd6d8, Opd6e0, Opd6e8, Opd6f0, Opd6f8, + Opd700, Opd708, Opd710, Opd718, Opd720, Opd728, Opd730, Opd738, + Opd740, Opd748, Opd750, Opd758, Opd760, Opd768, Opd770, Opd778, + Opd780, Opd788, Opd790, Opd798, Opd7a0, Opd7a8, Opd7b0, Opd7b8, + Opd7c0, Opd7c8, Opd7d0, Opd7d8, Opd7e0, Opd7e8, Opd7f0, Opd7f8, + Opd800, IllIns, Opd810, Opd818, Opd820, Opd828, Opd830, Opd838, + Opd840, Opd848, Opd850, Opd858, Opd860, Opd868, Opd870, Opd878, + Opd880, Opd888, Opd890, Opd898, Opd8a0, Opd8a8, Opd8b0, Opd8b8, + Opd8c0, Opd8c8, Opd8d0, Opd8d8, Opd8e0, Opd8e8, Opd8f0, Opd8f8, + Opd900, Opd908, Opd910, Opd918, Opd920, Opd928, Opd930, Opd938, + Opd940, Opd948, Opd950, Opd958, Opd960, Opd968, Opd970, Opd978, + Opd980, Opd988, Opd990, Opd998, Opd9a0, Opd9a8, Opd9b0, Opd9b8, + Opd9c0, Opd9c8, Opd9d0, Opd9d8, Opd9e0, Opd9e8, Opd9f0, Opd9f8, + Opda00, IllIns, Opda10, Opda18, Opda20, Opda28, Opda30, Opda38, + Opda40, Opda48, Opda50, Opda58, Opda60, Opda68, Opda70, Opda78, + Opda80, Opda88, Opda90, Opda98, Opdaa0, Opdaa8, Opdab0, Opdab8, + Opdac0, Opdac8, Opdad0, Opdad8, Opdae0, Opdae8, Opdaf0, Opdaf8, + Opdb00, Opdb08, Opdb10, Opdb18, Opdb20, Opdb28, Opdb30, Opdb38, + Opdb40, Opdb48, Opdb50, Opdb58, Opdb60, Opdb68, Opdb70, Opdb78, + Opdb80, Opdb88, Opdb90, Opdb98, Opdba0, Opdba8, Opdbb0, Opdbb8, + Opdbc0, Opdbc8, Opdbd0, Opdbd8, Opdbe0, Opdbe8, Opdbf0, Opdbf8, + Opdc00, IllIns, Opdc10, Opdc18, Opdc20, Opdc28, Opdc30, Opdc38, + Opdc40, Opdc48, Opdc50, Opdc58, Opdc60, Opdc68, Opdc70, Opdc78, + Opdc80, Opdc88, Opdc90, Opdc98, Opdca0, Opdca8, Opdcb0, Opdcb8, + Opdcc0, Opdcc8, Opdcd0, Opdcd8, Opdce0, Opdce8, Opdcf0, Opdcf8, + Opdd00, Opdd08, Opdd10, Opdd18, Opdd20, Opdd28, Opdd30, Opdd38, + Opdd40, Opdd48, Opdd50, Opdd58, Opdd60, Opdd68, Opdd70, Opdd78, + Opdd80, Opdd88, Opdd90, Opdd98, Opdda0, Opdda8, Opddb0, Opddb8, + Opddc0, Opddc8, Opddd0, Opddd8, Opdde0, Opdde8, Opddf0, Opddf8, + Opde00, IllIns, Opde10, Opde18, Opde20, Opde28, Opde30, Opde38, + Opde40, Opde48, Opde50, Opde58, Opde60, Opde68, Opde70, Opde78, + Opde80, Opde88, Opde90, Opde98, Opdea0, Opdea8, Opdeb0, Opdeb8, + Opdec0, Opdec8, Opded0, Opded8, Opdee0, Opdee8, Opdef0, Opdef8, + Opdf00, Opdf08, Opdf10, Opdf18, Opdf20, Opdf28, Opdf30, Opdf38, + Opdf40, Opdf48, Opdf50, Opdf58, Opdf60, Opdf68, Opdf70, Opdf78, + Opdf80, Opdf88, Opdf90, Opdf98, Opdfa0, Opdfa8, Opdfb0, Opdfb8, + Opdfc0, Opdfc8, Opdfd0, Opdfd8, Opdfe0, Opdfe8, Opdff0, Opdff8, + + /* E000 */ + Ope000, Ope008, Ope010, Ope018, Ope020, Ope028, Ope030, Ope038, + Ope040, Ope048, Ope050, Ope058, Ope060, Ope068, Ope070, Ope078, + Ope080, Ope088, Ope090, Ope098, Ope0a0, Ope0a8, Ope0b0, Ope0b8, + IllIns, IllIns, Ope0d0, Ope0d8, Ope0e0, Ope0e8, Ope0f0, Ope0f8, + Ope100, Ope108, Ope110, Ope118, Ope120, Ope128, Ope130, Ope138, + Ope140, Ope148, Ope150, Ope158, Ope160, Ope168, Ope170, Ope178, + Ope180, Ope188, Ope190, Ope198, Ope1a0, Ope1a8, Ope1b0, Ope1b8, + IllIns, IllIns, Ope1d0, Ope1d8, Ope1e0, Ope1e8, Ope1f0, Ope1f8, + Ope200, Ope208, Ope210, Ope218, Ope220, Ope228, Ope230, Ope238, + Ope240, Ope248, Ope250, Ope258, Ope260, Ope268, Ope270, Ope278, + Ope280, Ope288, Ope290, Ope298, Ope2a0, Ope2a8, Ope2b0, Ope2b8, + IllIns, IllIns, Ope2d0, Ope2d8, Ope2e0, Ope2e8, Ope2f0, Ope2f8, + Ope300, Ope308, Ope310, Ope318, Ope320, Ope328, Ope330, Ope338, + Ope340, Ope348, Ope350, Ope358, Ope360, Ope368, Ope370, Ope378, + Ope380, Ope388, Ope390, Ope398, Ope3a0, Ope3a8, Ope3b0, Ope3b8, + IllIns, IllIns, Ope3d0, Ope3d8, Ope3e0, Ope3e8, Ope3f0, Ope3f8, + Ope400, Ope408, Ope410, Ope418, Ope420, Ope428, Ope430, Ope438, + Ope440, Ope448, Ope450, Ope458, Ope460, Ope468, Ope470, Ope478, + Ope480, Ope488, Ope490, Ope498, Ope4a0, Ope4a8, Ope4b0, Ope4b8, + IllIns, IllIns, Ope4d0, Ope4d8, Ope4e0, Ope4e8, Ope4f0, Ope4f8, + Ope500, Ope508, Ope510, Ope518, Ope520, Ope528, Ope530, Ope538, + Ope540, Ope548, Ope550, Ope558, Ope560, Ope568, Ope570, Ope578, + Ope580, Ope588, Ope590, Ope598, Ope5a0, Ope5a8, Ope5b0, Ope5b8, + IllIns, IllIns, Ope5d0, Ope5d8, Ope5e0, Ope5e8, Ope5f0, Ope5f8, + Ope600, Ope608, Ope610, Ope618, Ope620, Ope628, Ope630, Ope638, + Ope640, Ope648, Ope650, Ope658, Ope660, Ope668, Ope670, Ope678, + Ope680, Ope688, Ope690, Ope698, Ope6a0, Ope6a8, Ope6b0, Ope6b8, + IllIns, IllIns, Ope6d0, Ope6d8, Ope6e0, Ope6e8, Ope6f0, Ope6f8, + Ope700, Ope708, Ope710, Ope718, Ope720, Ope728, Ope730, Ope738, + Ope740, Ope748, Ope750, Ope758, Ope760, Ope768, Ope770, Ope778, + Ope780, Ope788, Ope790, Ope798, Ope7a0, Ope7a8, Ope7b0, Ope7b8, + IllIns, IllIns, Ope7d0, Ope7d8, Ope7e0, Ope7e8, Ope7f0, Ope7f8, + Ope800, Ope808, Ope810, Ope818, Ope820, Ope828, Ope830, Ope838, + Ope840, Ope848, Ope850, Ope858, Ope860, Ope868, Ope870, Ope878, + Ope880, Ope888, Ope890, Ope898, Ope8a0, Ope8a8, Ope8b0, Ope8b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Ope900, Ope908, Ope910, Ope918, Ope920, Ope928, Ope930, Ope938, + Ope940, Ope948, Ope950, Ope958, Ope960, Ope968, Ope970, Ope978, + Ope980, Ope988, Ope990, Ope998, Ope9a0, Ope9a8, Ope9b0, Ope9b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opea00, Opea08, Opea10, Opea18, Opea20, Opea28, Opea30, Opea38, + Opea40, Opea48, Opea50, Opea58, Opea60, Opea68, Opea70, Opea78, + Opea80, Opea88, Opea90, Opea98, Opeaa0, Opeaa8, Opeab0, Opeab8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opeb00, Opeb08, Opeb10, Opeb18, Opeb20, Opeb28, Opeb30, Opeb38, + Opeb40, Opeb48, Opeb50, Opeb58, Opeb60, Opeb68, Opeb70, Opeb78, + Opeb80, Opeb88, Opeb90, Opeb98, Opeba0, Opeba8, Opebb0, Opebb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opec00, Opec08, Opec10, Opec18, Opec20, Opec28, Opec30, Opec38, + Opec40, Opec48, Opec50, Opec58, Opec60, Opec68, Opec70, Opec78, + Opec80, Opec88, Opec90, Opec98, Opeca0, Opeca8, Opecb0, Opecb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Oped00, Oped08, Oped10, Oped18, Oped20, Oped28, Oped30, Oped38, + Oped40, Oped48, Oped50, Oped58, Oped60, Oped68, Oped70, Oped78, + Oped80, Oped88, Oped90, Oped98, Opeda0, Opeda8, Opedb0, Opedb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opee00, Opee08, Opee10, Opee18, Opee20, Opee28, Opee30, Opee38, + Opee40, Opee48, Opee50, Opee58, Opee60, Opee68, Opee70, Opee78, + Opee80, Opee88, Opee90, Opee98, Opeea0, Opeea8, Opeeb0, Opeeb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opef00, Opef08, Opef10, Opef18, Opef20, Opef28, Opef30, Opef38, + Opef40, Opef48, Opef50, Opef58, Opef60, Opef68, Opef70, Opef78, + Opef80, Opef88, Opef90, Opef98, Opefa0, Opefa8, Opefb0, Opefb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* F000 */ + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F +}; diff --git a/MCUME_esp32/espcastaway/main/68korig/op68k.h b/MCUME_esp32/espcastaway/main/68korig/op68k.h new file mode 100755 index 0000000..436f6af --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/op68k.h @@ -0,0 +1,577 @@ +/* + * Castaway + * (C) 1994 - 2002 Martin Doering, Joachim Hoenig + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ +#ifndef OP68KH +#define OP68KH + +#include "config.h" +#include "operin.h" + +extern short GetMemWpc(unsigned long address); +extern long GetMemLpc(unsigned long address); +extern void SetMemPL(unsigned long address, unsigned long value); +extern void SetMemPW(unsigned long address, unsigned long value); + + +/* + * Status Register Access + */ +//AG: Changed to yet another SR implementation which is faster +//Note this code is little endian dependant and will need changing for big endian machines + +//reg[16]=ZNVC +//reg[17]=XTS- +//reg[18]=inst + +#define Zflag 0x1 +#define Nflag 0x100 +#define Vflag 0x10000 +#define Cflag 0x1000000 + +#define SetC(flag) if (flag) *(((int8*)reg)+67)=1; else *(((int8*)reg)+67)=0; +#define SetV(flag) if (flag) *(((int8*)reg)+66)=1; else *(((int8*)reg)+66)=0; +#define SetX(flag) if (flag) *(((int8*)reg)+68)=1; else *(((int8*)reg)+68)=0; +#define SetT(flag) if (flag) *(((int8*)reg)+69)=1; else *(((int8*)reg)+69)=0; +#define SetZ(flag) if (flag) *(((int8*)reg)+64)=1; else *(((int8*)reg)+64)=0; +#define SetZI(flag) if (flag) *(((int8*)reg)+64)=0; else *(((int8*)reg)+64)=1; +#define SetN(flag) if (flag) *(((int8*)reg)+65)=1; else *(((int8*)reg)+65)=0; +#define SetXC(flag) if (flag) *(((int8*)reg)+68)=*(((int8*)reg)+67)=1; else *(((int8*)reg)+68)=*(((int8*)reg)+67)=0; + +#define ForceX(flag) *(((int8*)reg)+68)=flag; +#define ForceC(flag) *(((int8*)reg)+67)=flag; +#define ForceV(flag) *(((int8*)reg)+66)=flag; +#define ForceZ(flag) *(((int8*)reg)+64)=flag; +#define ForceCVNZ(operand) reg[16]=operand; + +#define ZeroZ(flag) if (flag) *(((int8*)reg)+64)=0; + +#define SetNZ(operand) \ + if (operand==0) *(((int16*)reg)+32)=0x1; \ + else if (operand<0) *(((int16*)reg)+32)=0x100; \ + else *(((int16*)reg)+32)=0; + +#define SetI(imask) intmask=(imask); recalc_int=1; + +#define SetS(flag) \ + if (*(((int8*)reg)+70)) ssp=reg[15]; else usp=reg[15]; \ + if (flag) {*(((int8*)reg)+70)=1; reg[15]=ssp;} else {*(((int8*)reg)+70)=0; reg[15]=usp;} + +#define ClrCVSetNZ(operand) \ + if (operand==0) reg[16]=0x1; \ + else if (operand<0) reg[16]=0x100; \ + else reg[16]=0; + +#define GetC() *(((int8*)reg)+67) +#define GetV() *(((int8*)reg)+66) +#define GetZ() *(((int8*)reg)+64) +#define GetN() *(((int8*)reg)+65) +#define GetX() *(((int8*)reg)+68) +#define GetI() intmask +#define GetS() *(((int8*)reg)+70) +#define GetT() *(((int8*)reg)+69) + +//------------------------------- + +extern uint16 GetSRB(void); +extern uint16 GetSRW(void); +extern void SetSRB(unsigned long); +extern void SetSRW(unsigned long); + + +/* + * Other Register Access + */ +#define GetPC() pc +#define SetPC(addr) pc = addr + +#define FastMPCB() (char)(biginst>>16) +#define FastMPCW() (((int32)biginst)>>16) +#define FastMPCW32() (biginst>>16) + +#define GetMPCB() GetMemBpc (pc + 1) +#define GetMPCW() GetMemWpc (pc) +#define GetMPCL() GetMemLpc (pc) + +#define IncMPCB(var) {register uint32 regpc=pc; pc=regpc+2; var=GetMemBpc (regpc+1);} +#define IncMPCW(var) {register uint32 regpc=pc; pc=regpc+2; var=GetMemWpc (regpc);} +#define IncMPCL(var) {register uint32 regpc=pc; pc=regpc+4; var=GetMemLpc (regpc);} + +#define GetRegB(regno) (int8) reg[regno] +#define GetRegW(regno) (int16) reg[regno] +#define GetRegL(regno) (int32) reg[regno] + +#define GetARegW(regno) (int16) reg[regno+8] +#define GetARegL(regno) (int32) reg[regno+8] + +#ifndef USE_LITTLE_ENDIAN /* USE_BIG_ENDIAN */ +#define SetRegB(regno, value) *(((int8 *) ®[regno]) + 3) = value +#define SetRegW(regno, value) *(((int16 *) ®[regno]) + 1) = value +#define SetARegW(regno, value) *(((int16 *) ®[regno+8]) + 1) = value +#else /* USE_LITTLE_ENDIAN */ +#define SetRegB(regno, value) *((int8 *) ®[regno]) = value +#define SetRegW(regno, value) *((int16 *) ®[regno]) = value +#define SetARegW(regno, value) *((int16 *) ®[regno+8]) = value +#endif +#define SetRegL(regno, value) reg[regno] = value +#define SetARegL(regno, value) reg[regno+8] = value + + + +/* + * Addressing modes (target) + */ +/* d, a, ain, aip, mai, dai, aix, imm, (eaw,ear,eac) */ +#define CN(address,spec) +#define Cs(address,spec) address=spec; +#define Cd(address,spec) address=spec; +#define Ca(address,spec) address=8+spec; +#define Cain(address,spec) address=reg[spec+8]; +#define CaipW(address,spec) address=reg[spec+8]; reg[spec+8]=address+2; +#define CaipL(address,spec) address=reg[spec+8]; reg[spec+8]=address+4; +#define CmaiW(address,spec) address=reg[spec+8]; address-=2; reg[spec+8]=address; +#define CmaiL(address,spec) address=reg[spec+8]; address-=4; reg[spec+8]=address; +#define Cdai(address,spec) IncMPCW(address); address+=reg[spec+8]; +#define Caix(address,spec) { register uint16 mod = GetMPCW(); pc += 2; address = reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)); } +#define CaipB(address,spec) address=reg[spec+8]; if (spec==7) reg[spec+8]=address+2; else reg[spec+8]=address+1; +#define CaipB15(address,spec) address=reg[spec+8]; reg[spec+8]=address+2; + +#define CmaiB(address,spec) address=reg[spec+8]; if (spec==7) address-=2; else address--; reg[spec+8]=address; +#define CmaiB15(address,spec) address=reg[spec+8]; address-=2; reg[spec+8]=address; + +#define Ceaw(address, spec) \ +switch (spec) {\ +case 0x0:\ + IncMPCW(address);\ + break;\ +case 0x1:\ + IncMPCL(address);\ + cycles += 4;\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + address = 0;\ + break;\ +} +#define Cear(address,spec) \ +{ register uint16 mod;\ + register uint32 regpc=pc;\ +switch (spec) {\ +case 0x0:\ + pc=regpc+2;\ + address = GetMemWpc(regpc);\ + break;\ +case 0x1:\ + pc=regpc+4;\ + address = GetMemLpc(regpc);\ + cycles += 4;\ + break;\ +case 0x2:\ + pc=regpc+2;\ + address = regpc + GetMemWpc(regpc);\ + break;\ +case 0x3:\ + pc=regpc+2;\ + mod = GetMemWpc(regpc);\ + address = regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12));\ + cycles += 2;\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + address = 0;\ + break;\ +}} + +//Faster version of effective address macros +//Only use these when the pc hasn't been advanced by an earlier macro +#define Fdai(address,spec) address=FastMPCW()+reg[spec+8]; pc+=2; +#define Faix(address,spec) {register uint32 mod=FastMPCW32(); pc += 2; address = reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)); } +#define Feaw(address, spec) \ +switch (spec) {\ +case 0x0:\ + address=FastMPCW(); pc+=2;\ + break;\ +case 0x1:\ + IncMPCL(address);\ + cycles += 4;\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + address = 0;\ + break;\ +} +#define Fear(address,spec) \ +{ register uint32 mod;\ + register uint32 regpc=pc;\ +switch (spec) {\ +case 0x0:\ + pc=regpc+2;\ + address = FastMPCW();\ + break;\ +case 0x1:\ + pc=regpc+4;\ + address = GetMemLpc(regpc);\ + cycles += 4;\ + break;\ +case 0x2:\ + pc=regpc+2;\ + address = regpc + FastMPCW();\ + break;\ +case 0x3:\ + pc=regpc+2;\ + mod = FastMPCW32();\ + address = regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12));\ + cycles += 2;\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + address = 0;\ + break;\ +}} + + + +/* + * Operand types: B byte, W word, L long, R regno, A address + */ +#define DN(name) +#define DB(name) register int8 name; +#define DW(name) register int16 name; +#define DL(name) register int32 name; +#define DR(name) register uint16 name; +#define DA(name) register int32 name; + + +/* + * target macros + */ +#define GRB(regno, name) name = GetRegB (regno); +#define GRW(regno, name) name = GetRegW (regno); +#define GRL(regno, name) name = GetRegL (regno); +#define SRB(regno, name) SetRegB (regno, name); +#define SRW(regno, name) SetRegW (regno, name); +#define SRL(regno, name) SetRegL (regno, name); +#define GMB(address, name) name = GetMemB (address); +#define GMW(address, name) name = GetMemW (address); +#define GML(address, name) name = GetMemL (address); +#define GN(address, name) +#define SMB(address, name) SetMemB (address, name); +#define SMW(address, name) SetMemW (address, name); +#define SML(address, name) SetMemL (address, name); +#define SN(address, name) +#define GCB(dummy, name) name = GetSRB (); +#define GCW(dummy, name) name = GetSRW (); +#define SCB(dummy, name) SetSRB (name); +#define SCW(dummy, name) SetSRW (name); +#define GPW(address, name) \ + name = GetMemB(address);\ + name <<= 8;\ + name |= (uint8) GetMemB(address + 2); +#define GPL(address, name) \ + name = GetMemB(address);\ + name <<= 8;\ + name |= (uint8) GetMemB(address + 2);\ + name <<= 8;\ + name |= (uint8) GetMemB(address + 4);\ + name <<= 8;\ + name |= (uint8) GetMemB(address + 6); +#define SPW(address, name) \ + SetMemPW(address, name); +#define SPL(address, name) \ + SetMemPL(address, name); + + +/* + * source macros + */ +#define SdaiPW(var,spec) {uint32 a; Cdai(a,spec); var = GPW(a,var);} +#define SdaiPL(var,spec) {uint32 a; Cdai(a,spec); var = GPL(a,var);} +#define SNN(var,spec) +#define SNQ(var, dummy) var = (int8) biginst; +#define ScB(var,spec) var = GetSRB(); +#define ScW(var,spec) var = GetSRW(); +#define Ss(var,spec) var = spec; +#define SimmB(var,spec) var=FastMPCB(); pc+=2; +#define SimmW(var,spec) var=FastMPCW(); pc+=2; +#define SimmL(var,spec) IncMPCL(var); +#define SdB(var,spec) var = GetRegB (spec); +#define SdW(var,spec) var = GetRegW (spec); +#define SdL(var,spec) var = GetRegL (spec); +#define SaW(var,spec) var = GetARegW (spec); +#define SaL(var,spec) var = GetARegL (spec); +#define SainB(var,spec) var = GetMemB (reg[spec+8]); +#define SainW(var,spec) var = GetMemW (reg[spec+8]); +#define SainL(var,spec) var = GetMemL (reg[spec+8]); +#define SainA(var,spec) var = (reg[spec+8]); +#define SaipW(var,spec) {register uint32 myadr=reg[spec+8]; reg[spec+8]=myadr+2; var=GetMemW(myadr);} +#define SaipL(var,spec) {register uint32 myadr=reg[spec+8]; reg[spec+8]=myadr+4; var=GetMemL(myadr);} +#define SmaiW(var,spec) {register uint32 myadr=reg[spec+8]; myadr-=2; reg[spec+8]=myadr; var=GetMemW(myadr);} +#define SmaiL(var,spec) {register uint32 myadr=reg[spec+8]; myadr-=4; reg[spec+8]=myadr; var=GetMemL(myadr);} +#define SdaiB(var,spec) var = GetMemB(reg[spec+8]+FastMPCW()); pc+=2; +#define SdaiW(var,spec) var = GetMemW(reg[spec+8]+FastMPCW()); pc+=2; +#define SdaiL(var,spec) var = GetMemL(reg[spec+8]+FastMPCW()); pc+=2; +#define SdaiA(var,spec) var = reg[spec+8]+FastMPCW(); pc+=2; +#define SaixB(var,spec) {register uint32 mod=FastMPCW32(); pc+=2; var = GetMemB(reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));}; +#define SaixW(var,spec) {register uint32 mod=FastMPCW32(); pc+=2; var = GetMemW(reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));}; +#define SaixL(var,spec) {register uint32 mod=FastMPCW32(); pc+=2; var = GetMemL(reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));}; +#define SaixA(var,spec) {register uint32 mod=FastMPCW32(); pc+=2; var = (reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));}; +#define SaipB(var,spec) {register uint32 myadr=reg[spec+8]; if (spec==7) reg[spec+8]=myadr+2; else reg[spec+8]=myadr+1; var=GetMemB(myadr);} +#define SmaiB(var,spec) {register uint32 myadr=reg[spec+8]; if (spec==7) myadr-=2; else myadr--; reg[spec+8]=myadr; var=GetMemB(myadr);} + +#define SearB(var,spec) \ +{ register uint32 mod;\ + register uint32 regpc=pc;\ +switch (spec) {\ +case 0x0:\ + pc=regpc+2;\ + var = GetMemB (FastMPCW());\ + cycles += 4;\ + break;\ +case 0x1:\ + pc=regpc+4;\ + var = GetMemB (GetMemLpc(regpc));\ + cycles += 8;\ + break;\ +case 0x2:\ + pc=regpc+2;\ + var = GetMemB (regpc+FastMPCW());\ + cycles += 4;\ + break;\ +case 0x3:\ + pc=regpc+2;\ + mod = FastMPCW32();\ + var = GetMemB (regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));\ + cycles += 6;\ + break;\ +case 0x4:\ + pc=regpc+2;\ + var = FastMPCB();\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + var = 0;\ + break;\ +}} +#define SearW(var,spec) \ +{ register uint32 mod;\ + register uint32 regpc=pc;\ +switch (spec) {\ +case 0x0:\ + pc=regpc+2;\ + var = GetMemW (FastMPCW());\ + cycles += 4;\ + break;\ +case 0x1:\ + pc=regpc+4;\ + var = GetMemW (GetMemLpc(regpc));\ + cycles += 8;\ + break;\ +case 0x2:\ + pc=regpc+2;\ + var = GetMemW (regpc+FastMPCW());\ + cycles += 4;\ + break;\ +case 0x3:\ + pc=regpc+2;\ + mod = FastMPCW32();\ + var = GetMemW (regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));\ + cycles += 6;\ + break;\ +case 0x4:\ + pc=regpc+2;\ + var = FastMPCW();\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + var = 0;\ + break;\ +}} +#define SearL(var,spec) \ +{ register uint32 mod;\ + register uint32 regpc=pc;\ +switch (spec) {\ +case 0x0:\ + pc=regpc+2;\ + var = GetMemL (FastMPCW());\ + cycles += 4;\ + break;\ +case 0x1:\ + pc=regpc+4;\ + var = GetMemL (GetMemLpc(regpc));\ + cycles += 8;\ + break;\ +case 0x2:\ + pc=regpc+2;\ + var = GetMemL (regpc+FastMPCW());\ + cycles += 4;\ + break;\ +case 0x3:\ + pc=regpc+2;\ + mod = FastMPCW32();\ + var = GetMemL (regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));\ + cycles += 6;\ + break;\ +case 0x4:\ + pc=regpc+4;\ + var = GetMemLpc(regpc);\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + var = 0;\ + break;\ +}} +#define SearA(var,spec) \ +{ register uint32 mod;\ + register uint32 regpc=pc;\ +switch (spec) {\ +case 0x0:\ + pc=regpc+2;\ + var = FastMPCW();\ + break;\ +case 0x1:\ + pc=regpc+4;\ + var = GetMemLpc(regpc);\ + cycles += 4;\ + break;\ +case 0x2:\ + pc=regpc+2;\ + var = regpc+FastMPCW();\ + break;\ +case 0x3:\ + pc=regpc+2;\ + mod = FastMPCW32();\ + var = regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12));\ + cycles += 2;\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + var = 0;\ + break;\ +}} + +/* + * Condition-Code queries + */ +#define CCt 0xff +#define CCf 0x00 +#define CChi (!GetC() && !GetZ()) +#define CCls (GetC() || GetZ()) +#define CCcc !GetC() +#define CCcs GetC() +#define CCne !GetZ() +#define CCeq GetZ() +#define CCvc !GetV() +#define CCvs GetV() +#define CCpl !GetN() +#define CCmi GetN() +#define CCge !(GetN() ^ GetV()) +#define CClt (GetN() ^ GetV()) +#define CCgt (!(GetN() ^ GetV()) && !GetZ()) +#define CCle ((GetN() ^ GetV()) || GetZ()) + +/* + * Oper arguments: + * Code Opcode + * Op(target,source) Macro used to execute operation + * DeclS(name) Macro to declare source (such as DB, DW or DL, or + DN=no source, DA=address, DR=register number) + * GetS(var,spec) Macro to fetch source, with addressing mode evaluation. + SNN = no fetch + SNQ = used in MOVEQ + ScB = condition code register + ScW = status register word (s-flag not checked) + Ss = source equals source specifier (spec1) + SaW, SaL = get # data register value + SdB, SdW, SdL = get data register value + SainB, SainW, SainL = (A) + SainA = (LEA only) + SaixB, SaixW, SaixL = (d8,A,X<>) + SaixA = (LEA only) + SdaiB, SdaiW, SdaiL = d16(A) + SdaiA = (LEA only) + SaipB, SaipW, SaipL = (A)+ + SmaiB, SmaiW, SmaiL = -(A) + SimmB, SimmW, SimmL = immediate + SdaiPW, SdaiPL = used in MOVEP + SearB, SearW, SearL = other addressing modes + SearA = (LEA only) + * spec1 source specifier, usually the data or address register number. + * DeclT(name) Macro to declare target (such as DB, DW or DL, or + DN=no target, DA=address, DR=register number) + * DeclEA2(name) Macro to declare target address (typically DA, DR, or DN) + * CalcEA2(address,spec) Macro to calculate address, with addressing mode evaluation. + CN = no address + Cs = equals target specifier (spec2) + Cd = equals target specifier (spec2) (data register number) + Ca = equals target specifier (spec2) + 8 (address register number) + Cain = (A) + Caix = (d8,A,X<>) + Cdai = d16(A) + CaipB, CaipW, CaipL = (A)+, + CaipB15 = stack pointer only + CmaiB, CmaiW, CmaiL = -(A) + CmaiB15 = stack pointer only + Ceaw = other addressing modes (if target is modified) + Cear = other addressing modes (if target is not modified) + * spec2 target specifier, usually the data or address register number. + * GetEA2(address,name) Macro to get target value + GCB = get condition code + GCW = get status (s-flag not checked) + GN = no read + GMB, GMW, GML = read from memory + GPW, GPL = (MOVEP) + GRB, GRW, GRL = read from register + * SetEA2(address,name) Macro to set target value + SCB = set condition code + SCW = set status (s-flag not checked) + SN = no write + SMB, SMW, SML = write to memory + SPW, SPL = (MOVEP) + SRB, SRW, SRL = write to register + */ + +#if (!defined(DEBUG) || !defined(INTERNALTRACE)) +#define Oper(Code, Op, DeclS, GetS, spec1, DeclT, DeclEA2, CalcEA2, spec2, GetEA2, SetEA2, rval)\ +unsigned long Code(operin)\ +{\ + register unsigned long cycles=0;\ + DeclS (source)\ + DeclT (target)\ + DeclEA2 (address2)\ + GetS (source, spec1)\ + CalcEA2 (address2, spec2)\ + GetEA2 (address2, target)\ + Op (target, source)\ + SetEA2 (address2, target)\ + return rval; \ +} +#else +/* quick'n dirty debug hack */ +#undef DN +#define DN(name) int name; +#define Oper(Code, Op, DeclS, GetS, spec1, DeclT, DeclEA2, CalcEA2, spec2, GetEA2, SetEA2, rval)\ +unsigned long Code(operin)\ +{\ + register unsigned long cycles=0;\ + DeclS (source)\ + DeclT (target)\ + DeclEA2 (address2)\ + source = 0; \ + target = 0; \ + address2 = 0; \ + GetS (source, spec1)\ + CalcEA2 (address2, spec2)\ + GetEA2 (address2, target)\ + traceback[tbi].address = address2; \ + traceback[tbi].source = source; \ + traceback[tbi].target = target; \ + Op (target, source)\ + traceback[tbi].result = target; \ + SetEA2 (address2, target)\ + return rval; \ +} +#endif +#endif diff --git a/MCUME_esp32/espcastaway/main/68korig/op68kadd.cpp b/MCUME_esp32/espcastaway/main/68korig/op68kadd.cpp new file mode 100755 index 0000000..a000189 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/op68kadd.cpp @@ -0,0 +1,809 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - 68k add instructions +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 10.07.2002 JH Fixed Z-Flag for ADDX +* 08.10.2002 JH Fixed Z-Flag for ADD.B 0x80+0x80 and Add.W 0x8000+0x8000. +*/ +#ifndef PROTOH +static char sccsid[] = "$Id: op68kadd.c,v 1.3 2002/10/08 00:18:02 jhoenig Exp $"; +#include "68000.h" +#include "op68k.h" + +/* +* Opfuncs. +*/ + +#define DoAddB(target,source) \ +{register int32 tgt,cvnz=0;\ + tgt = target + source;\ + if ((uint32) source > (uint32) ~target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\ + target = tgt;\ + if (tgt!=target) cvnz+=Vflag;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoAddW(target,source) \ +{register int32 tgt,cvnz=0;\ + tgt = target + source;\ + if ((uint32) source > (uint32) ~target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\ + target = tgt;\ + if (tgt!=target) cvnz+=Vflag;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoAddL(target,source) \ + /* Overflow precondition: source has same sign */\ +{register int32 precon=(target>>31)-(source>>31),cvnz=0;\ + if ((uint32) source > (uint32) ~target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\ + target += source;\ + /* target and source now have different sign: overflow! */\ + if (precon==0 && (target>>31)!=(source>>31)) cvnz+=Vflag;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoAdda(target,source) target += source; + +#define DoAddx(target,source) \ + /* Overflow precondition: source has same sign */\ +{register int32 precon=(target>>31)-(source>>31);\ + if (GetX ()) {\ + SetXC ((uint32) source >= (uint32) ~target);\ + target += source + 1;\ + } else {\ + SetXC ((uint32) source > (uint32) ~target);\ + target += source;\ +}\ + /* target and source now have different sign: overflow! */\ + SetV(precon==0 && (target>>31)!=(source>>31));\ + ZeroZ(target!=0);\ +SetN(target < 0);}; + +#endif + +Oper (Opd000, DoAddB, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4) +Oper (Opd010, DoAddB, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Opd018, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Opd020, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Opd028, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Opd030, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SRB, 16) +Oper (Opd038, DoAddB, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opd040, DoAddW, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Opd048, DoAddW, DW, SaW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Opd050, DoAddW, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Opd058, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Opd060, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Opd068, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Opd070, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SRW, 16) +Oper (Opd078, DoAddW, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opd080, DoAddL, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Opd088, DoAddL, DL, SaL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Opd090, DoAddL, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Opd098, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Opd0a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Opd0a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Opd0b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Opd0b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opd0c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Opd0c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Opd0d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 0, GRL, SRL, 12) +Oper (Opd0d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 0, GRL, SRL, 12) +Oper (Opd0e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Opd0e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Opd0f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 0, GRL, SRL, 20) +Oper (Opd0f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 0, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opd100, DoAddx, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4) +Oper (Opd108, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 0, GMB, SMB, 20) +Oper (Opd110, DoAddB, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opd118, DoAddB, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opd120, DoAddB, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opd128, DoAddB, DB, SdB, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opd130, DoAddB, DB, SdB, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opd138, DoAddB, DB, SdB, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opd140, DoAddx, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Opd148, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 0, GMW, SMW, 20) +Oper (Opd150, DoAddW, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opd158, DoAddW, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opd160, DoAddW, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opd168, DoAddW, DW, SdW, 0, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opd170, DoAddW, DW, SdW, 0, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opd178, DoAddW, DW, SdW, 0, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opd180, DoAddx, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Opd188, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 0, GML, SML, 32) +Oper (Opd190, DoAddL, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opd198, DoAddL, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opd1a0, DoAddL, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opd1a8, DoAddL, DL, SdL, 0, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opd1b0, DoAddL, DL, SdL, 0, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opd1b8, DoAddL, DL, SdL, 0, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opd1c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Opd1c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Opd1d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Opd1d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Opd1e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Opd1e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 0, GRL, SRL, 20) +Oper (Opd1f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 0, GRL, SRL, 20) +Oper (Opd1f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 0, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opd200, DoAddB, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4) +Oper (Opd210, DoAddB, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Opd218, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Opd220, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Opd228, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Opd230, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SRB, 16) +Oper (Opd238, DoAddB, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opd240, DoAddW, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Opd248, DoAddW, DW, SaW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Opd250, DoAddW, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Opd258, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Opd260, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Opd268, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Opd270, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SRW, 16) +Oper (Opd278, DoAddW, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opd280, DoAddL, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Opd288, DoAddL, DL, SaL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Opd290, DoAddL, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Opd298, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Opd2a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Opd2a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Opd2b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Opd2b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opd2c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Opd2c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Opd2d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 1, GRL, SRL, 12) +Oper (Opd2d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 1, GRL, SRL, 12) +Oper (Opd2e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Opd2e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Opd2f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 1, GRL, SRL, 20) +Oper (Opd2f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 1, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opd300, DoAddx, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4) +Oper (Opd308, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 1, GMB, SMB, 20) +Oper (Opd310, DoAddB, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opd318, DoAddB, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opd320, DoAddB, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opd328, DoAddB, DB, SdB, 1, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opd330, DoAddB, DB, SdB, 1, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opd338, DoAddB, DB, SdB, 1, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opd340, DoAddx, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Opd348, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 1, GMW, SMW, 20) +Oper (Opd350, DoAddW, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opd358, DoAddW, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opd360, DoAddW, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opd368, DoAddW, DW, SdW, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opd370, DoAddW, DW, SdW, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opd378, DoAddW, DW, SdW, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opd380, DoAddx, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Opd388, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 1, GML, SML, 32) +Oper (Opd390, DoAddL, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opd398, DoAddL, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opd3a0, DoAddL, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opd3a8, DoAddL, DL, SdL, 1, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opd3b0, DoAddL, DL, SdL, 1, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opd3b8, DoAddL, DL, SdL, 1, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opd3c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Opd3c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Opd3d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Opd3d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Opd3e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Opd3e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 1, GRL, SRL, 20) +Oper (Opd3f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 1, GRL, SRL, 20) +Oper (Opd3f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 1, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opd400, DoAddB, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4) +Oper (Opd410, DoAddB, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Opd418, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Opd420, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Opd428, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Opd430, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SRB, 16) +Oper (Opd438, DoAddB, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opd440, DoAddW, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Opd448, DoAddW, DW, SaW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Opd450, DoAddW, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Opd458, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Opd460, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Opd468, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Opd470, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SRW, 16) +Oper (Opd478, DoAddW, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opd480, DoAddL, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Opd488, DoAddL, DL, SaL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Opd490, DoAddL, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Opd498, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Opd4a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Opd4a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Opd4b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Opd4b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opd4c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Opd4c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Opd4d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 2, GRL, SRL, 12) +Oper (Opd4d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 2, GRL, SRL, 12) +Oper (Opd4e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Opd4e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Opd4f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 2, GRL, SRL, 20) +Oper (Opd4f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 2, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opd500, DoAddx, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4) +Oper (Opd508, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 2, GMB, SMB, 20) +Oper (Opd510, DoAddB, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opd518, DoAddB, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opd520, DoAddB, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opd528, DoAddB, DB, SdB, 2, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opd530, DoAddB, DB, SdB, 2, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opd538, DoAddB, DB, SdB, 2, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opd540, DoAddx, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Opd548, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 2, GMW, SMW, 20) +Oper (Opd550, DoAddW, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opd558, DoAddW, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opd560, DoAddW, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opd568, DoAddW, DW, SdW, 2, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opd570, DoAddW, DW, SdW, 2, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opd578, DoAddW, DW, SdW, 2, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opd580, DoAddx, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Opd588, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 2, GML, SML, 32) +Oper (Opd590, DoAddL, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opd598, DoAddL, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opd5a0, DoAddL, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opd5a8, DoAddL, DL, SdL, 2, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opd5b0, DoAddL, DL, SdL, 2, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opd5b8, DoAddL, DL, SdL, 2, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opd5c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Opd5c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Opd5d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Opd5d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Opd5e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Opd5e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 2, GRL, SRL, 20) +Oper (Opd5f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 2, GRL, SRL, 20) +Oper (Opd5f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 2, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opd600, DoAddB, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4) +Oper (Opd610, DoAddB, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Opd618, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Opd620, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Opd628, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Opd630, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SRB, 16) +Oper (Opd638, DoAddB, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opd640, DoAddW, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Opd648, DoAddW, DW, SaW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Opd650, DoAddW, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Opd658, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Opd660, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Opd668, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Opd670, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SRW, 16) +Oper (Opd678, DoAddW, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opd680, DoAddL, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Opd688, DoAddL, DL, SaL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Opd690, DoAddL, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Opd698, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Opd6a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Opd6a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Opd6b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Opd6b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opd6c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Opd6c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Opd6d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 3, GRL, SRL, 12) +Oper (Opd6d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 3, GRL, SRL, 12) +Oper (Opd6e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Opd6e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Opd6f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 3, GRL, SRL, 20) +Oper (Opd6f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 3, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opd700, DoAddx, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4) +Oper (Opd708, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 3, GMB, SMB, 20) +Oper (Opd710, DoAddB, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opd718, DoAddB, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opd720, DoAddB, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opd728, DoAddB, DB, SdB, 3, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opd730, DoAddB, DB, SdB, 3, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opd738, DoAddB, DB, SdB, 3, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opd740, DoAddx, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Opd748, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 3, GMW, SMW, 20) +Oper (Opd750, DoAddW, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opd758, DoAddW, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opd760, DoAddW, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opd768, DoAddW, DW, SdW, 3, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opd770, DoAddW, DW, SdW, 3, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opd778, DoAddW, DW, SdW, 3, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opd780, DoAddx, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Opd788, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 3, GML, SML, 32) +Oper (Opd790, DoAddL, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opd798, DoAddL, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opd7a0, DoAddL, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opd7a8, DoAddL, DL, SdL, 3, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opd7b0, DoAddL, DL, SdL, 3, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opd7b8, DoAddL, DL, SdL, 3, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opd7c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Opd7c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Opd7d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Opd7d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Opd7e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Opd7e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 3, GRL, SRL, 20) +Oper (Opd7f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 3, GRL, SRL, 20) +Oper (Opd7f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 3, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opd800, DoAddB, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4) +Oper (Opd810, DoAddB, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Opd818, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Opd820, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Opd828, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Opd830, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SRB, 16) +Oper (Opd838, DoAddB, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opd840, DoAddW, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Opd848, DoAddW, DW, SaW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Opd850, DoAddW, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Opd858, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Opd860, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Opd868, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Opd870, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SRW, 16) +Oper (Opd878, DoAddW, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opd880, DoAddL, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Opd888, DoAddL, DL, SaL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Opd890, DoAddL, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Opd898, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Opd8a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Opd8a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Opd8b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Opd8b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opd8c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Opd8c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Opd8d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 4, GRL, SRL, 12) +Oper (Opd8d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 4, GRL, SRL, 12) +Oper (Opd8e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Opd8e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Opd8f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 4, GRL, SRL, 20) +Oper (Opd8f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 4, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opd900, DoAddx, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4) +Oper (Opd908, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 4, GMB, SMB, 20) +Oper (Opd910, DoAddB, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opd918, DoAddB, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opd920, DoAddB, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opd928, DoAddB, DB, SdB, 4, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opd930, DoAddB, DB, SdB, 4, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opd938, DoAddB, DB, SdB, 4, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opd940, DoAddx, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Opd948, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 4, GMW, SMW, 20) +Oper (Opd950, DoAddW, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opd958, DoAddW, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opd960, DoAddW, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opd968, DoAddW, DW, SdW, 4, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opd970, DoAddW, DW, SdW, 4, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opd978, DoAddW, DW, SdW, 4, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opd980, DoAddx, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Opd988, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 4, GML, SML, 32) +Oper (Opd990, DoAddL, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opd998, DoAddL, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opd9a0, DoAddL, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opd9a8, DoAddL, DL, SdL, 4, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opd9b0, DoAddL, DL, SdL, 4, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opd9b8, DoAddL, DL, SdL, 4, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opd9c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Opd9c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Opd9d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Opd9d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Opd9e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Opd9e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 4, GRL, SRL, 20) +Oper (Opd9f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 4, GRL, SRL, 20) +Oper (Opd9f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 4, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opda00, DoAddB, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4) +Oper (Opda10, DoAddB, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Opda18, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Opda20, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Opda28, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Opda30, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SRB, 16) +Oper (Opda38, DoAddB, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opda40, DoAddW, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Opda48, DoAddW, DW, SaW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Opda50, DoAddW, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Opda58, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Opda60, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Opda68, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Opda70, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SRW, 16) +Oper (Opda78, DoAddW, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opda80, DoAddL, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Opda88, DoAddL, DL, SaL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Opda90, DoAddL, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Opda98, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Opdaa0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Opdaa8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Opdab0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Opdab8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opdac0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Opdac8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Opdad0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 5, GRL, SRL, 12) +Oper (Opdad8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 5, GRL, SRL, 12) +Oper (Opdae0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Opdae8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Opdaf0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 5, GRL, SRL, 20) +Oper (Opdaf8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 5, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opdb00, DoAddx, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4) +Oper (Opdb08, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 5, GMB, SMB, 20) +Oper (Opdb10, DoAddB, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opdb18, DoAddB, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opdb20, DoAddB, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opdb28, DoAddB, DB, SdB, 5, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opdb30, DoAddB, DB, SdB, 5, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opdb38, DoAddB, DB, SdB, 5, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opdb40, DoAddx, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Opdb48, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 5, GMW, SMW, 20) +Oper (Opdb50, DoAddW, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opdb58, DoAddW, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opdb60, DoAddW, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opdb68, DoAddW, DW, SdW, 5, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opdb70, DoAddW, DW, SdW, 5, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opdb78, DoAddW, DW, SdW, 5, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opdb80, DoAddx, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Opdb88, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 5, GML, SML, 32) +Oper (Opdb90, DoAddL, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opdb98, DoAddL, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opdba0, DoAddL, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opdba8, DoAddL, DL, SdL, 5, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opdbb0, DoAddL, DL, SdL, 5, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opdbb8, DoAddL, DL, SdL, 5, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opdbc0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Opdbc8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Opdbd0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Opdbd8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Opdbe0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Opdbe8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 5, GRL, SRL, 20) +Oper (Opdbf0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 5, GRL, SRL, 20) +Oper (Opdbf8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 5, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opdc00, DoAddB, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4) +Oper (Opdc10, DoAddB, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Opdc18, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Opdc20, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Opdc28, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Opdc30, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SRB, 16) +Oper (Opdc38, DoAddB, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opdc40, DoAddW, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Opdc48, DoAddW, DW, SaW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Opdc50, DoAddW, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Opdc58, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Opdc60, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Opdc68, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Opdc70, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SRW, 16) +Oper (Opdc78, DoAddW, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opdc80, DoAddL, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Opdc88, DoAddL, DL, SaL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Opdc90, DoAddL, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Opdc98, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Opdca0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Opdca8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Opdcb0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Opdcb8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opdcc0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Opdcc8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Opdcd0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 6, GRL, SRL, 12) +Oper (Opdcd8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 6, GRL, SRL, 12) +Oper (Opdce0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Opdce8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Opdcf0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 6, GRL, SRL, 20) +Oper (Opdcf8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 6, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opdd00, DoAddx, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4) +Oper (Opdd08, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 6, GMB, SMB, 20) +Oper (Opdd10, DoAddB, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opdd18, DoAddB, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opdd20, DoAddB, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opdd28, DoAddB, DB, SdB, 6, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opdd30, DoAddB, DB, SdB, 6, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opdd38, DoAddB, DB, SdB, 6, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opdd40, DoAddx, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Opdd48, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 6, GMW, SMW, 20) +Oper (Opdd50, DoAddW, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opdd58, DoAddW, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opdd60, DoAddW, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opdd68, DoAddW, DW, SdW, 6, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opdd70, DoAddW, DW, SdW, 6, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opdd78, DoAddW, DW, SdW, 6, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opdd80, DoAddx, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Opdd88, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 6, GML, SML, 32) +Oper (Opdd90, DoAddL, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opdd98, DoAddL, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opdda0, DoAddL, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opdda8, DoAddL, DL, SdL, 6, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opddb0, DoAddL, DL, SdL, 6, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opddb8, DoAddL, DL, SdL, 6, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opddc0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Opddc8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Opddd0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Opddd8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Opdde0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Opdde8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 6, GRL, SRL, 20) +Oper (Opddf0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 6, GRL, SRL, 20) +Oper (Opddf8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 6, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opde00, DoAddB, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4) +Oper (Opde10, DoAddB, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Opde18, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Opde20, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Opde28, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Opde30, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SRB, 16) +Oper (Opde38, DoAddB, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opde40, DoAddW, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Opde48, DoAddW, DW, SaW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Opde50, DoAddW, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Opde58, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Opde60, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Opde68, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Opde70, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SRW, 16) +Oper (Opde78, DoAddW, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opde80, DoAddL, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Opde88, DoAddL, DL, SaL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Opde90, DoAddL, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Opde98, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Opdea0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Opdea8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Opdeb0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Opdeb8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opdec0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Opdec8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Opded0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 7, GRL, SRL, 12) +Oper (Opded8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 7, GRL, SRL, 12) +Oper (Opdee0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Opdee8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Opdef0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 7, GRL, SRL, 20) +Oper (Opdef8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 7, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opdf00, DoAddx, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4) +Oper (Opdf08, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB15, 7, GMB, SMB, 20) +Oper (Opdf10, DoAddB, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opdf18, DoAddB, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opdf20, DoAddB, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opdf28, DoAddB, DB, SdB, 7, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opdf30, DoAddB, DB, SdB, 7, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opdf38, DoAddB, DB, SdB, 7, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opdf40, DoAddx, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Opdf48, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 7, GMW, SMW, 20) +Oper (Opdf50, DoAddW, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opdf58, DoAddW, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opdf60, DoAddW, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opdf68, DoAddW, DW, SdW, 7, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opdf70, DoAddW, DW, SdW, 7, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opdf78, DoAddW, DW, SdW, 7, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opdf80, DoAddx, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Opdf88, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 7, GML, SML, 32) +Oper (Opdf90, DoAddL, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opdf98, DoAddL, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opdfa0, DoAddL, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opdfa8, DoAddL, DL, SdL, 7, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opdfb0, DoAddL, DL, SdL, 7, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opdfb8, DoAddL, DL, SdL, 7, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opdfc0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Opdfc8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Opdfd0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Opdfd8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Opdfe0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Opdfe8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 7, GRL, SRL, 20) +Oper (Opdff0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 7, GRL, SRL, 20) +Oper (Opdff8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 7, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op0600, DoAddB, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8) +Oper (Op0610, DoAddB, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op0618, DoAddB, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op0620, DoAddB, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op0628, DoAddB, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op0630, DoAddB, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +Oper (Op0638, DoAddB, DB, SimmB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+23)&0xfffffffc) +Oper (Op0640, DoAddW, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8) +Oper (Op0650, DoAddW, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16) +Oper (Op0658, DoAddW, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16) +Oper (Op0660, DoAddW, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20) +Oper (Op0668, DoAddW, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20) +Oper (Op0670, DoAddW, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24) +Oper (Op0678, DoAddW, DW, SimmW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+23)&0xfffffffc) +Oper (Op0680, DoAddL, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16) +Oper (Op0690, DoAddL, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28) +Oper (Op0698, DoAddL, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28) +Oper (Op06a0, DoAddL, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32) +Oper (Op06a8, DoAddL, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32) +Oper (Op06b0, DoAddL, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36) +Oper (Op06b8, DoAddL, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc) + +Oper (Op5000, DoAddB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5010, DoAddB, DB, Ss, 8, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5018, DoAddB, DB, Ss, 8, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5020, DoAddB, DB, Ss, 8, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5028, DoAddB, DB, Ss, 8, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5030, DoAddB, DB, Ss, 8, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5038, DoAddB, DB, Ss, 8, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5040, DoAddW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5048, DoAdda, DL, Ss, 8, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5050, DoAddW, DW, Ss, 8, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5058, DoAddW, DW, Ss, 8, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5060, DoAddW, DW, Ss, 8, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5068, DoAddW, DW, Ss, 8, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5070, DoAddW, DW, Ss, 8, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5078, DoAddW, DW, Ss, 8, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5080, DoAddL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5088, DoAdda, DL, Ss, 8, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5090, DoAddL, DL, Ss, 8, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5098, DoAddL, DL, Ss, 8, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op50a0, DoAddL, DL, Ss, 8, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op50a8, DoAddL, DL, Ss, 8, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op50b0, DoAddL, DL, Ss, 8, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op50b8, DoAddL, DL, Ss, 8, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5200, DoAddB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5210, DoAddB, DB, Ss, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5218, DoAddB, DB, Ss, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5220, DoAddB, DB, Ss, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5228, DoAddB, DB, Ss, 1, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5230, DoAddB, DB, Ss, 1, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5238, DoAddB, DB, Ss, 1, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5240, DoAddW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5248, DoAdda, DL, Ss, 1, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5250, DoAddW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5258, DoAddW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5260, DoAddW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5268, DoAddW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5270, DoAddW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5278, DoAddW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5280, DoAddL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5288, DoAdda, DL, Ss, 1, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5290, DoAddL, DL, Ss, 1, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5298, DoAddL, DL, Ss, 1, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op52a0, DoAddL, DL, Ss, 1, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op52a8, DoAddL, DL, Ss, 1, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op52b0, DoAddL, DL, Ss, 1, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op52b8, DoAddL, DL, Ss, 1, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5400, DoAddB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5410, DoAddB, DB, Ss, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5418, DoAddB, DB, Ss, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5420, DoAddB, DB, Ss, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5428, DoAddB, DB, Ss, 2, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5430, DoAddB, DB, Ss, 2, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5438, DoAddB, DB, Ss, 2, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5440, DoAddW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5448, DoAdda, DL, Ss, 2, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5450, DoAddW, DW, Ss, 2, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5458, DoAddW, DW, Ss, 2, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5460, DoAddW, DW, Ss, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5468, DoAddW, DW, Ss, 2, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5470, DoAddW, DW, Ss, 2, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5478, DoAddW, DW, Ss, 2, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5480, DoAddL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5488, DoAdda, DL, Ss, 2, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5490, DoAddL, DL, Ss, 2, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5498, DoAddL, DL, Ss, 2, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op54a0, DoAddL, DL, Ss, 2, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op54a8, DoAddL, DL, Ss, 2, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op54b0, DoAddL, DL, Ss, 2, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op54b8, DoAddL, DL, Ss, 2, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5600, DoAddB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5610, DoAddB, DB, Ss, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5618, DoAddB, DB, Ss, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5620, DoAddB, DB, Ss, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5628, DoAddB, DB, Ss, 3, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5630, DoAddB, DB, Ss, 3, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5638, DoAddB, DB, Ss, 3, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5640, DoAddW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5648, DoAdda, DL, Ss, 3, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5650, DoAddW, DW, Ss, 3, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5658, DoAddW, DW, Ss, 3, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5660, DoAddW, DW, Ss, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5668, DoAddW, DW, Ss, 3, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5670, DoAddW, DW, Ss, 3, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5678, DoAddW, DW, Ss, 3, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5680, DoAddL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5688, DoAdda, DL, Ss, 3, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5690, DoAddL, DL, Ss, 3, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5698, DoAddL, DL, Ss, 3, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op56a0, DoAddL, DL, Ss, 3, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op56a8, DoAddL, DL, Ss, 3, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op56b0, DoAddL, DL, Ss, 3, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op56b8, DoAddL, DL, Ss, 3, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5800, DoAddB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5810, DoAddB, DB, Ss, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5818, DoAddB, DB, Ss, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5820, DoAddB, DB, Ss, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5828, DoAddB, DB, Ss, 4, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5830, DoAddB, DB, Ss, 4, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5838, DoAddB, DB, Ss, 4, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5840, DoAddW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5848, DoAdda, DL, Ss, 4, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5850, DoAddW, DW, Ss, 4, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5858, DoAddW, DW, Ss, 4, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5860, DoAddW, DW, Ss, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5868, DoAddW, DW, Ss, 4, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5870, DoAddW, DW, Ss, 4, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5878, DoAddW, DW, Ss, 4, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5880, DoAddL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5888, DoAdda, DL, Ss, 4, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5890, DoAddL, DL, Ss, 4, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5898, DoAddL, DL, Ss, 4, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op58a0, DoAddL, DL, Ss, 4, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op58a8, DoAddL, DL, Ss, 4, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op58b0, DoAddL, DL, Ss, 4, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op58b8, DoAddL, DL, Ss, 4, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5a00, DoAddB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5a10, DoAddB, DB, Ss, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5a18, DoAddB, DB, Ss, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5a20, DoAddB, DB, Ss, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5a28, DoAddB, DB, Ss, 5, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5a30, DoAddB, DB, Ss, 5, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5a38, DoAddB, DB, Ss, 5, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5a40, DoAddW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5a48, DoAdda, DL, Ss, 5, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5a50, DoAddW, DW, Ss, 5, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5a58, DoAddW, DW, Ss, 5, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5a60, DoAddW, DW, Ss, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5a68, DoAddW, DW, Ss, 5, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5a70, DoAddW, DW, Ss, 5, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5a78, DoAddW, DW, Ss, 5, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5a80, DoAddL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5a88, DoAdda, DL, Ss, 5, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5a90, DoAddL, DL, Ss, 5, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5a98, DoAddL, DL, Ss, 5, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op5aa0, DoAddL, DL, Ss, 5, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op5aa8, DoAddL, DL, Ss, 5, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op5ab0, DoAddL, DL, Ss, 5, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op5ab8, DoAddL, DL, Ss, 5, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5c00, DoAddB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5c10, DoAddB, DB, Ss, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5c18, DoAddB, DB, Ss, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5c20, DoAddB, DB, Ss, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5c28, DoAddB, DB, Ss, 6, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5c30, DoAddB, DB, Ss, 6, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5c38, DoAddB, DB, Ss, 6, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5c40, DoAddW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5c48, DoAdda, DL, Ss, 6, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5c50, DoAddW, DW, Ss, 6, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5c58, DoAddW, DW, Ss, 6, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5c60, DoAddW, DW, Ss, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5c68, DoAddW, DW, Ss, 6, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5c70, DoAddW, DW, Ss, 6, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5c78, DoAddW, DW, Ss, 6, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5c80, DoAddL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5c88, DoAdda, DL, Ss, 6, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5c90, DoAddL, DL, Ss, 6, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5c98, DoAddL, DL, Ss, 6, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op5ca0, DoAddL, DL, Ss, 6, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op5ca8, DoAddL, DL, Ss, 6, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op5cb0, DoAddL, DL, Ss, 6, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op5cb8, DoAddL, DL, Ss, 6, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5e00, DoAddB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5e10, DoAddB, DB, Ss, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5e18, DoAddB, DB, Ss, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5e20, DoAddB, DB, Ss, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5e28, DoAddB, DB, Ss, 7, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5e30, DoAddB, DB, Ss, 7, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5e38, DoAddB, DB, Ss, 7, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5e40, DoAddW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5e48, DoAdda, DL, Ss, 7, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5e50, DoAddW, DW, Ss, 7, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5e58, DoAddW, DW, Ss, 7, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5e60, DoAddW, DW, Ss, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5e68, DoAddW, DW, Ss, 7, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5e70, DoAddW, DW, Ss, 7, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5e78, DoAddW, DW, Ss, 7, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5e80, DoAddL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5e88, DoAdda, DL, Ss, 7, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5e90, DoAddL, DL, Ss, 7, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5e98, DoAddL, DL, Ss, 7, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op5ea0, DoAddL, DL, Ss, 7, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op5ea8, DoAddL, DL, Ss, 7, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op5eb0, DoAddL, DL, Ss, 7, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op5eb8, DoAddL, DL, Ss, 7, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) diff --git a/MCUME_esp32/espcastaway/main/68korig/op68karith.cpp b/MCUME_esp32/espcastaway/main/68korig/op68karith.cpp new file mode 100755 index 0000000..0b86d91 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/op68karith.cpp @@ -0,0 +1,844 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - 68k arithmetic instructions +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 12.06.2002 JH Correct bus error/address error exception stack frame +* 13.06.2002 JH Merged in Martin's BCD implementation (untested), +* completed jump table. STOP is now the only +* unimplemented instruction. +* 08.10.2002 JH Fixed Z-Flag for ADD.B 0x80+0x80 and Add.W 0x8000+0x8000. +*/ +#ifndef PROTOH +static char sccsid[] = "$Id: op68karith.c,v 1.5 2002/10/08 00:18:02 jhoenig Exp $"; +#include "68000.h" +#include "op68k.h" + +#include + +/* +* Opfuncs. +*/ + +#define DoCmpB(target,source) \ +{register int32 tgt,cvnz=0; register int8 tgt8;\ + tgt = target - source;\ + if ((uint32) source > (uint32) target) cvnz+=Cflag;\ + tgt8=tgt;\ + if (tgt!=tgt8) cvnz+=Vflag;\ + if (tgt8==0) cvnz+=Zflag;\ + else if (tgt8<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoCmpW(target,source) \ +{register int32 tgt,cvnz=0; register int16 tgt16;\ + tgt = target - source;\ + if ((uint32) source > (uint32) target) cvnz+=Cflag;\ + tgt16=tgt;\ + if (tgt!=tgt16) cvnz+=Vflag;\ + if (tgt16==0) cvnz+=Zflag;\ + else if (tgt16<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoCmpL(target,source) \ + /* Overflow precondition: source has different sign */\ +{register int32 precon=(target>>31)-(source>>31),cvnz=0;\ + if ((uint32) source > (uint32) target) cvnz+=Cflag;\ + target -= source;\ + /* target and source now have same sign: overflow! */\ + if (precon && (target>>31)==(source>>31)) cvnz+=Vflag;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoCmpa(target,source) DoCmpL(target,source) +#define DoCmpm(target,source) DoCmpL(target,source) + + +#define DoDivs(target,source) \ + if (source == 0) {\ + ExceptionGroup2(DIVZ);\ + } else {\ + int16 quot, rest;\ + if ((target / source) > 32767 || (target / source) < -32768) {\ + ForceV (1);\ + ForceC (0);\ + } else {\ + rest = target % source;\ + quot = target / source;\ + target = (rest << 16) | (uint16) quot;\ + ClrCVSetNZ ((int16) target);\ +}\ +} + +#define DoDivu(target,source) \ + if (source == 0) {\ + ExceptionGroup2(DIVZ);\ + } else {\ + uint16 quot, rest;\ + if (((uint32) target / (uint16) source) & 0xffff0000) {\ + ForceV (1);\ + ForceC (0);\ + } else {\ + rest = (uint32) target % (uint16) source;\ + quot = (uint32) target / (uint16) source;\ + target = (rest << 16) | quot;\ + ClrCVSetNZ ((int16) target);\ +}\ +} + +#define DoMuls(target,source) \ + target = ((int16) target * source);\ +ClrCVSetNZ (target); + +#define DoMulu(target,source) \ + target = ((uint16) target * (uint16) source);\ +ClrCVSetNZ (target); + +//#define DoSuba(target,source) target -= source; + +/* +#define DoSubx(target,source) \ +// Overflow precondition: source has different sign \ +SetV ((target < 0) != (source < 0));\ +if (GetX ()) {\ +SetXC ((uint32) source >= (uint32) target);\ +target -= source;\ +target -= 1;\ +} else {\ +SetXC ((uint32) source > (uint32) target);\ +target -= source;\ +}\ +//target and source now have same sign: overflow! +SetV (GetV() && (target<0) == (source<0));\ +SetNZ (target); +*/ + +/* BCD all totally untested (MAD) */ + +#define DoNBCD(target, source) \ +{ register uint32 lo = (target & 0xF) + GetX();\ + register uint32 hi = (target & 0xF0);\ + if (lo>10) {lo=20-lo; hi+=0x20;}\ + else if (lo>0) {lo=10-lo; hi+=0x10;}\ + if (hi>0xa0) {hi=0x140-hi; ForceX(1); ForceC(1);}\ + else if (hi>0) {hi=0xa0-hi; ForceX(1); ForceC(1);}\ + else {ForceC(0); ForceX(0);}\ + target=hi+lo;\ + if (target!=0) ForceZ(0);\ +}; + +#define DoABCD(target, source) \ + { register int32 tgt; \ + tgt = (source & 0xF) + (target & 0xF) + GetX(); \ + if(tgt >= 0xA) \ + tgt += 0x6; \ + tgt += (source & 0xF0) + (target & 0xF0); \ + if(tgt >= 0xA0) \ + tgt += 0x60; \ + SetXC (tgt & 0xFF00); \ + tgt &= 0xFF; \ + SetZ(tgt == 0); \ + target = tgt; \ + }; + +#define DoSBCD(target, source) \ + { register int32 tgt, hi; \ + tgt = (target & 0xF) - (source & 0xF) - GetX(); \ + hi = (target & 0xF0) - (source & 0xF0); \ + if(tgt < 0) { \ + tgt += 10; \ + hi -= 0x10; \ + } \ + if(hi < 0) { \ + hi -= 0x60; \ + } \ + tgt += hi; \ + SetXC (tgt & 0xFF00); \ + tgt &= 0xFF; \ + SetZ(tgt == 0); \ + target = tgt; \ + }; + +#endif + +Oper (Opc0c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 0, GRL, SRL, 72) +Oper (Opc0d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 0, GRL, SRL, 76) +Oper (Opc0d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 0, GRL, SRL, 76) +Oper (Opc0e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 76) +Oper (Opc0e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 80) +Oper (Opc0f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 0, GRL, SRL, 80) +Oper (Opc0f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc1c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 0, GRL, SRL, 72) +Oper (Opc1d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 0, GRL, SRL, 76) +Oper (Opc1d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 0, GRL, SRL, 76) +Oper (Opc1e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 76) +Oper (Opc1e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 80) +Oper (Opc1f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 0, GRL, SRL, 80) +Oper (Opc1f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc2c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 1, GRL, SRL, 72) +Oper (Opc2d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 1, GRL, SRL, 76) +Oper (Opc2d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 1, GRL, SRL, 76) +Oper (Opc2e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 76) +Oper (Opc2e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 80) +Oper (Opc2f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 1, GRL, SRL, 80) +Oper (Opc2f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc3c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 1, GRL, SRL, 72) +Oper (Opc3d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 1, GRL, SRL, 76) +Oper (Opc3d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 1, GRL, SRL, 76) +Oper (Opc3e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 76) +Oper (Opc3e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 80) +Oper (Opc3f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 1, GRL, SRL, 80) +Oper (Opc3f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc4c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 2, GRL, SRL, 72) +Oper (Opc4d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 2, GRL, SRL, 76) +Oper (Opc4d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 2, GRL, SRL, 76) +Oper (Opc4e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 76) +Oper (Opc4e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 80) +Oper (Opc4f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 2, GRL, SRL, 80) +Oper (Opc4f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc5c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 2, GRL, SRL, 72) +Oper (Opc5d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 2, GRL, SRL, 76) +Oper (Opc5d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 2, GRL, SRL, 76) +Oper (Opc5e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 76) +Oper (Opc5e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 80) +Oper (Opc5f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 2, GRL, SRL, 80) +Oper (Opc5f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc6c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 3, GRL, SRL, 72) +Oper (Opc6d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 3, GRL, SRL, 76) +Oper (Opc6d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 3, GRL, SRL, 76) +Oper (Opc6e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 76) +Oper (Opc6e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 80) +Oper (Opc6f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 3, GRL, SRL, 80) +Oper (Opc6f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc7c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 3, GRL, SRL, 72) +Oper (Opc7d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 3, GRL, SRL, 76) +Oper (Opc7d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 3, GRL, SRL, 76) +Oper (Opc7e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 76) +Oper (Opc7e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 80) +Oper (Opc7f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 3, GRL, SRL, 80) +Oper (Opc7f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc8c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 4, GRL, SRL, 72) +Oper (Opc8d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 4, GRL, SRL, 76) +Oper (Opc8d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 4, GRL, SRL, 76) +Oper (Opc8e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 76) +Oper (Opc8e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 80) +Oper (Opc8f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 4, GRL, SRL, 80) +Oper (Opc8f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc9c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 4, GRL, SRL, 72) +Oper (Opc9d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 4, GRL, SRL, 76) +Oper (Opc9d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 4, GRL, SRL, 76) +Oper (Opc9e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 76) +Oper (Opc9e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 80) +Oper (Opc9f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 4, GRL, SRL, 80) +Oper (Opc9f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opcac0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 5, GRL, SRL, 72) +Oper (Opcad0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 5, GRL, SRL, 76) +Oper (Opcad8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 5, GRL, SRL, 76) +Oper (Opcae0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 76) +Oper (Opcae8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 80) +Oper (Opcaf0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 5, GRL, SRL, 80) +Oper (Opcaf8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opcbc0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 5, GRL, SRL, 72) +Oper (Opcbd0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 5, GRL, SRL, 76) +Oper (Opcbd8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 5, GRL, SRL, 76) +Oper (Opcbe0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 76) +Oper (Opcbe8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 80) +Oper (Opcbf0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 5, GRL, SRL, 80) +Oper (Opcbf8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opccc0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 6, GRL, SRL, 72) +Oper (Opccd0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 6, GRL, SRL, 76) +Oper (Opccd8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 6, GRL, SRL, 76) +Oper (Opcce0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 76) +Oper (Opcce8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 80) +Oper (Opccf0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 6, GRL, SRL, 80) +Oper (Opccf8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opcdc0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 6, GRL, SRL, 72) +Oper (Opcdd0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 6, GRL, SRL, 76) +Oper (Opcdd8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 6, GRL, SRL, 76) +Oper (Opcde0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 76) +Oper (Opcde8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 80) +Oper (Opcdf0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 6, GRL, SRL, 80) +Oper (Opcdf8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opcec0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 7, GRL, SRL, 72) +Oper (Opced0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 7, GRL, SRL, 76) +Oper (Opced8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 7, GRL, SRL, 76) +Oper (Opcee0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 76) +Oper (Opcee8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 80) +Oper (Opcef0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 7, GRL, SRL, 80) +Oper (Opcef8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opcfc0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 7, GRL, SRL, 72) +Oper (Opcfd0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 7, GRL, SRL, 76) +Oper (Opcfd8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 7, GRL, SRL, 76) +Oper (Opcfe0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 76) +Oper (Opcfe8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 80) +Oper (Opcff0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 7, GRL, SRL, 80) +Oper (Opcff8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opb000, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SN, 4) +Oper (Opb010, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SN, 8) +Oper (Opb018, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SN, 8) +Oper (Opb020, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SN, 12) +Oper (Opb028, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SN, 12) +Oper (Opb030, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SN, 16) +Oper (Opb038, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opb040, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SN, 4) +Oper (Opb048, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 0, GRW, SN, 4) +Oper (Opb050, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SN, 8) +Oper (Opb058, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SN, 8) +Oper (Opb060, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SN, 12) +Oper (Opb068, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SN, 12) +Oper (Opb070, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SN, 16) +Oper (Opb078, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opb080, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SN, 8) +Oper (Opb088, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 0, GRL, SN, 8) +Oper (Opb090, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SN, 16) +Oper (Opb098, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SN, 16) +Oper (Opb0a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SN, 16) +Oper (Opb0a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SN, 20) +Oper (Opb0b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SN, 20) +Oper (Opb0b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opb0c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 0, GRL, SN, 8) +Oper (Opb0c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 0, GRL, SN, 8) +Oper (Opb0d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 0, GRL, SN, 12) +Oper (Opb0d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 0, GRL, SN, 12) +Oper (Opb0e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 0, GRL, SN, 12) +Oper (Opb0e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 0, GRL, SN, 16) +Oper (Opb0f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 0, GRL, SN, 16) +Oper (Opb0f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 0, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opb108, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 0, GMB, SN, 12) +Oper (Opb148, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 0, GMW, SN, 12) +Oper (Opb188, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 0, GML, SN, 20) +Oper (Opb1c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 0, GRL, SN, 8) +Oper (Opb1c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 0, GRL, SN, 8) +Oper (Opb1d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 0, GRL, SN, 16) +Oper (Opb1d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 0, GRL, SN, 16) +Oper (Opb1e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 0, GRL, SN, 16) +Oper (Opb1e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 0, GRL, SN, 20) +Oper (Opb1f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 0, GRL, SN, 20) +Oper (Opb1f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 0, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Opb200, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SN, 4) +Oper (Opb210, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SN, 8) +Oper (Opb218, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SN, 8) +Oper (Opb220, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SN, 12) +Oper (Opb228, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SN, 12) +Oper (Opb230, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SN, 16) +Oper (Opb238, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opb240, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SN, 4) +Oper (Opb248, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 1, GRW, SN, 4) +Oper (Opb250, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SN, 8) +Oper (Opb258, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SN, 8) +Oper (Opb260, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SN, 12) +Oper (Opb268, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SN, 12) +Oper (Opb270, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SN, 16) +Oper (Opb278, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opb280, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SN, 8) +Oper (Opb288, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 1, GRL, SN, 8) +Oper (Opb290, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SN, 16) +Oper (Opb298, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SN, 16) +Oper (Opb2a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SN, 16) +Oper (Opb2a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SN, 20) +Oper (Opb2b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SN, 20) +Oper (Opb2b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opb2c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 1, GRL, SN, 8) +Oper (Opb2c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 1, GRL, SN, 8) +Oper (Opb2d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 1, GRL, SN, 12) +Oper (Opb2d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 1, GRL, SN, 12) +Oper (Opb2e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 1, GRL, SN, 12) +Oper (Opb2e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 1, GRL, SN, 16) +Oper (Opb2f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 1, GRL, SN, 16) +Oper (Opb2f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 1, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opb308, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 1, GMB, SN, 12) +Oper (Opb348, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 1, GMW, SN, 12) +Oper (Opb388, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 1, GML, SN, 20) +Oper (Opb3c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 1, GRL, SN, 8) +Oper (Opb3c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 1, GRL, SN, 8) +Oper (Opb3d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 1, GRL, SN, 16) +Oper (Opb3d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 1, GRL, SN, 16) +Oper (Opb3e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 1, GRL, SN, 16) +Oper (Opb3e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 1, GRL, SN, 20) +Oper (Opb3f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 1, GRL, SN, 20) +Oper (Opb3f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 1, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Opb400, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SN, 4) +Oper (Opb410, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SN, 8) +Oper (Opb418, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SN, 8) +Oper (Opb420, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SN, 12) +Oper (Opb428, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SN, 12) +Oper (Opb430, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SN, 16) +Oper (Opb438, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opb440, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SN, 4) +Oper (Opb448, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 2, GRW, SN, 4) +Oper (Opb450, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SN, 8) +Oper (Opb458, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SN, 8) +Oper (Opb460, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SN, 12) +Oper (Opb468, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SN, 12) +Oper (Opb470, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SN, 16) +Oper (Opb478, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opb480, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SN, 8) +Oper (Opb488, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 2, GRL, SN, 8) +Oper (Opb490, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SN, 16) +Oper (Opb498, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SN, 16) +Oper (Opb4a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SN, 16) +Oper (Opb4a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SN, 20) +Oper (Opb4b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SN, 20) +Oper (Opb4b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opb4c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 2, GRL, SN, 8) +Oper (Opb4c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 2, GRL, SN, 8) +Oper (Opb4d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 2, GRL, SN, 12) +Oper (Opb4d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 2, GRL, SN, 12) +Oper (Opb4e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 2, GRL, SN, 12) +Oper (Opb4e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 2, GRL, SN, 16) +Oper (Opb4f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 2, GRL, SN, 16) +Oper (Opb4f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 2, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opb508, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 2, GMB, SN, 12) +Oper (Opb548, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 2, GMW, SN, 12) +Oper (Opb588, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 2, GML, SN, 20) +Oper (Opb5c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 2, GRL, SN, 8) +Oper (Opb5c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 2, GRL, SN, 8) +Oper (Opb5d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 2, GRL, SN, 16) +Oper (Opb5d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 2, GRL, SN, 16) +Oper (Opb5e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 2, GRL, SN, 16) +Oper (Opb5e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 2, GRL, SN, 20) +Oper (Opb5f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 2, GRL, SN, 20) +Oper (Opb5f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 2, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Opb600, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SN, 4) +Oper (Opb610, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SN, 8) +Oper (Opb618, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SN, 8) +Oper (Opb620, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SN, 12) +Oper (Opb628, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SN, 12) +Oper (Opb630, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SN, 16) +Oper (Opb638, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opb640, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SN, 4) +Oper (Opb648, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 3, GRW, SN, 4) +Oper (Opb650, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SN, 8) +Oper (Opb658, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SN, 8) +Oper (Opb660, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SN, 12) +Oper (Opb668, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SN, 12) +Oper (Opb670, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SN, 16) +Oper (Opb678, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opb680, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SN, 8) +Oper (Opb688, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 3, GRL, SN, 8) +Oper (Opb690, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SN, 16) +Oper (Opb698, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SN, 16) +Oper (Opb6a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SN, 16) +Oper (Opb6a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SN, 20) +Oper (Opb6b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SN, 20) +Oper (Opb6b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opb6c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 3, GRL, SN, 8) +Oper (Opb6c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 3, GRL, SN, 8) +Oper (Opb6d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 3, GRL, SN, 12) +Oper (Opb6d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 3, GRL, SN, 12) +Oper (Opb6e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 3, GRL, SN, 12) +Oper (Opb6e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 3, GRL, SN, 16) +Oper (Opb6f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 3, GRL, SN, 16) +Oper (Opb6f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 3, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opb708, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 3, GMB, SN, 12) +Oper (Opb748, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 3, GMW, SN, 12) +Oper (Opb788, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 3, GML, SN, 20) +Oper (Opb7c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 3, GRL, SN, 8) +Oper (Opb7c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 3, GRL, SN, 8) +Oper (Opb7d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 3, GRL, SN, 16) +Oper (Opb7d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 3, GRL, SN, 16) +Oper (Opb7e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 3, GRL, SN, 16) +Oper (Opb7e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 3, GRL, SN, 20) +Oper (Opb7f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 3, GRL, SN, 20) +Oper (Opb7f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 3, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Opb800, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SN, 4) +Oper (Opb810, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SN, 8) +Oper (Opb818, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SN, 8) +Oper (Opb820, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SN, 12) +Oper (Opb828, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SN, 12) +Oper (Opb830, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SN, 16) +Oper (Opb838, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opb840, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SN, 4) +Oper (Opb848, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 4, GRW, SN, 4) +Oper (Opb850, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SN, 8) +Oper (Opb858, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SN, 8) +Oper (Opb860, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SN, 12) +Oper (Opb868, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SN, 12) +Oper (Opb870, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SN, 16) +Oper (Opb878, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opb880, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SN, 8) +Oper (Opb888, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 4, GRL, SN, 8) +Oper (Opb890, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SN, 16) +Oper (Opb898, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SN, 16) +Oper (Opb8a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SN, 16) +Oper (Opb8a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SN, 20) +Oper (Opb8b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SN, 20) +Oper (Opb8b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opb8c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 4, GRL, SN, 8) +Oper (Opb8c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 4, GRL, SN, 8) +Oper (Opb8d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 4, GRL, SN, 12) +Oper (Opb8d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 4, GRL, SN, 12) +Oper (Opb8e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 4, GRL, SN, 12) +Oper (Opb8e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 4, GRL, SN, 16) +Oper (Opb8f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 4, GRL, SN, 16) +Oper (Opb8f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 4, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opb908, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 4, GMB, SN, 12) +Oper (Opb948, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 4, GMW, SN, 12) +Oper (Opb988, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 4, GML, SN, 20) +Oper (Opb9c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 4, GRL, SN, 8) +Oper (Opb9c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 4, GRL, SN, 8) +Oper (Opb9d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 4, GRL, SN, 16) +Oper (Opb9d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 4, GRL, SN, 16) +Oper (Opb9e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 4, GRL, SN, 16) +Oper (Opb9e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 4, GRL, SN, 20) +Oper (Opb9f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 4, GRL, SN, 20) +Oper (Opb9f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 4, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Opba00, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SN, 4) +Oper (Opba10, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SN, 8) +Oper (Opba18, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SN, 8) +Oper (Opba20, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SN, 12) +Oper (Opba28, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SN, 12) +Oper (Opba30, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SN, 16) +Oper (Opba38, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opba40, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SN, 4) +Oper (Opba48, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 5, GRW, SN, 4) +Oper (Opba50, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SN, 8) +Oper (Opba58, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SN, 8) +Oper (Opba60, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SN, 12) +Oper (Opba68, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SN, 12) +Oper (Opba70, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SN, 16) +Oper (Opba78, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opba80, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SN, 8) +Oper (Opba88, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 5, GRL, SN, 8) +Oper (Opba90, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SN, 16) +Oper (Opba98, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SN, 16) +Oper (Opbaa0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SN, 16) +Oper (Opbaa8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SN, 20) +Oper (Opbab0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SN, 20) +Oper (Opbab8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opbac0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 5, GRL, SN, 8) +Oper (Opbac8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 5, GRL, SN, 8) +Oper (Opbad0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 5, GRL, SN, 12) +Oper (Opbad8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 5, GRL, SN, 12) +Oper (Opbae0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 5, GRL, SN, 12) +Oper (Opbae8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 5, GRL, SN, 16) +Oper (Opbaf0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 5, GRL, SN, 16) +Oper (Opbaf8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 5, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opbb08, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 5, GMB, SN, 12) +Oper (Opbb48, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 5, GMW, SN, 12) +Oper (Opbb88, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 5, GML, SN, 20) +Oper (Opbbc0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 5, GRL, SN, 8) +Oper (Opbbc8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 5, GRL, SN, 8) +Oper (Opbbd0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 5, GRL, SN, 16) +Oper (Opbbd8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 5, GRL, SN, 16) +Oper (Opbbe0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 5, GRL, SN, 16) +Oper (Opbbe8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 5, GRL, SN, 20) +Oper (Opbbf0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 5, GRL, SN, 20) +Oper (Opbbf8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 5, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Opbc00, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SN, 4) +Oper (Opbc10, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SN, 8) +Oper (Opbc18, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SN, 8) +Oper (Opbc20, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SN, 12) +Oper (Opbc28, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SN, 12) +Oper (Opbc30, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SN, 16) +Oper (Opbc38, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opbc40, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SN, 4) +Oper (Opbc48, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 6, GRW, SN, 4) +Oper (Opbc50, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SN, 8) +Oper (Opbc58, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SN, 8) +Oper (Opbc60, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SN, 12) +Oper (Opbc68, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SN, 12) +Oper (Opbc70, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SN, 16) +Oper (Opbc78, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opbc80, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SN, 8) +Oper (Opbc88, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 6, GRL, SN, 8) +Oper (Opbc90, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SN, 16) +Oper (Opbc98, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SN, 16) +Oper (Opbca0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SN, 16) +Oper (Opbca8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SN, 20) +Oper (Opbcb0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SN, 20) +Oper (Opbcb8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opbcc0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 6, GRL, SN, 8) +Oper (Opbcc8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 6, GRL, SN, 8) +Oper (Opbcd0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 6, GRL, SN, 12) +Oper (Opbcd8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 6, GRL, SN, 12) +Oper (Opbce0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 6, GRL, SN, 12) +Oper (Opbce8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 6, GRL, SN, 16) +Oper (Opbcf0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 6, GRL, SN, 16) +Oper (Opbcf8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 6, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opbd08, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 6, GMB, SN, 12) +Oper (Opbd48, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 6, GMW, SN, 12) +Oper (Opbd88, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 6, GML, SN, 20) +Oper (Opbdc0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 6, GRL, SN, 8) +Oper (Opbdc8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 6, GRL, SN, 8) +Oper (Opbdd0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 6, GRL, SN, 16) +Oper (Opbdd8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 6, GRL, SN, 16) +Oper (Opbde0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 6, GRL, SN, 16) +Oper (Opbde8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 6, GRL, SN, 20) +Oper (Opbdf0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 6, GRL, SN, 20) +Oper (Opbdf8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 6, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Opbe00, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SN, 4) +Oper (Opbe10, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SN, 8) +Oper (Opbe18, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SN, 8) +Oper (Opbe20, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SN, 12) +Oper (Opbe28, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SN, 12) +Oper (Opbe30, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SN, 16) +Oper (Opbe38, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opbe40, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SN, 4) +Oper (Opbe48, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 7, GRW, SN, 4) +Oper (Opbe50, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SN, 8) +Oper (Opbe58, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SN, 8) +Oper (Opbe60, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SN, 12) +Oper (Opbe68, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SN, 12) +Oper (Opbe70, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SN, 16) +Oper (Opbe78, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opbe80, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SN, 8) +Oper (Opbe88, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 7, GRL, SN, 8) +Oper (Opbe90, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SN, 16) +Oper (Opbe98, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SN, 16) +Oper (Opbea0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SN, 16) +Oper (Opbea8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SN, 20) +Oper (Opbeb0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SN, 20) +Oper (Opbeb8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opbec0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 7, GRL, SN, 8) +Oper (Opbec8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 7, GRL, SN, 8) +Oper (Opbed0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 7, GRL, SN, 12) +Oper (Opbed8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 7, GRL, SN, 12) +Oper (Opbee0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 7, GRL, SN, 12) +Oper (Opbee8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 7, GRL, SN, 16) +Oper (Opbef0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 7, GRL, SN, 16) +Oper (Opbef8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 7, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opbf08, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB15, 7, GMB, SN, 12) +Oper (Opbf48, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 7, GMW, SN, 12) +Oper (Opbf88, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 7, GML, SN, 20) +Oper (Opbfc0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 7, GRL, SN, 8) +Oper (Opbfc8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 7, GRL, SN, 8) +Oper (Opbfd0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 7, GRL, SN, 16) +Oper (Opbfd8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 7, GRL, SN, 16) +Oper (Opbfe0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 7, GRL, SN, 16) +Oper (Opbfe8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 7, GRL, SN, 20) +Oper (Opbff0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 7, GRL, SN, 20) +Oper (Opbff8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 7, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Op80c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 0, GRL, SRL, 140) +Oper (Op80d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 0, GRL, SRL, 144) +Oper (Op80d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 0, GRL, SRL, 144) +Oper (Op80e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 148) +Oper (Op80e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 148) +Oper (Op80f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 0, GRL, SRL, 152) +Oper (Op80f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op81c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 0, GRL, SRL, 160) +Oper (Op81d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 0, GRL, SRL, 164) +Oper (Op81d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 0, GRL, SRL, 164) +Oper (Op81e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 164) +Oper (Op81e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 168) +Oper (Op81f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 0, GRL, SRL, 168) +Oper (Op81f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op82c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 1, GRL, SRL, 140) +Oper (Op82d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 1, GRL, SRL, 144) +Oper (Op82d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 1, GRL, SRL, 144) +Oper (Op82e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 148) +Oper (Op82e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 148) +Oper (Op82f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 1, GRL, SRL, 152) +Oper (Op82f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op83c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 1, GRL, SRL, 160) +Oper (Op83d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 1, GRL, SRL, 164) +Oper (Op83d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 1, GRL, SRL, 164) +Oper (Op83e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 164) +Oper (Op83e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 168) +Oper (Op83f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 1, GRL, SRL, 168) +Oper (Op83f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op84c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 2, GRL, SRL, 140) +Oper (Op84d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 2, GRL, SRL, 144) +Oper (Op84d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 2, GRL, SRL, 144) +Oper (Op84e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 148) +Oper (Op84e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 148) +Oper (Op84f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 2, GRL, SRL, 152) +Oper (Op84f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op85c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 2, GRL, SRL, 160) +Oper (Op85d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 2, GRL, SRL, 164) +Oper (Op85d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 2, GRL, SRL, 164) +Oper (Op85e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 164) +Oper (Op85e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 168) +Oper (Op85f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 2, GRL, SRL, 168) +Oper (Op85f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op86c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 3, GRL, SRL, 140) +Oper (Op86d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 3, GRL, SRL, 144) +Oper (Op86d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 3, GRL, SRL, 144) +Oper (Op86e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 148) +Oper (Op86e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 148) +Oper (Op86f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 3, GRL, SRL, 152) +Oper (Op86f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op87c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 3, GRL, SRL, 160) +Oper (Op87d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 3, GRL, SRL, 164) +Oper (Op87d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 3, GRL, SRL, 164) +Oper (Op87e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 164) +Oper (Op87e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 168) +Oper (Op87f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 3, GRL, SRL, 168) +Oper (Op87f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op88c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 4, GRL, SRL, 140) +Oper (Op88d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 4, GRL, SRL, 144) +Oper (Op88d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 4, GRL, SRL, 144) +Oper (Op88e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 148) +Oper (Op88e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 148) +Oper (Op88f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 4, GRL, SRL, 152) +Oper (Op88f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op89c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 4, GRL, SRL, 160) +Oper (Op89d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 4, GRL, SRL, 164) +Oper (Op89d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 4, GRL, SRL, 164) +Oper (Op89e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 164) +Oper (Op89e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 168) +Oper (Op89f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 4, GRL, SRL, 168) +Oper (Op89f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op8ac0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 5, GRL, SRL, 140) +Oper (Op8ad0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 5, GRL, SRL, 144) +Oper (Op8ad8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 5, GRL, SRL, 144) +Oper (Op8ae0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 148) +Oper (Op8ae8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 148) +Oper (Op8af0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 5, GRL, SRL, 152) +Oper (Op8af8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op8bc0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 5, GRL, SRL, 160) +Oper (Op8bd0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 5, GRL, SRL, 164) +Oper (Op8bd8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 5, GRL, SRL, 164) +Oper (Op8be0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 164) +Oper (Op8be8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 168) +Oper (Op8bf0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 5, GRL, SRL, 168) +Oper (Op8bf8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op8cc0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 6, GRL, SRL, 140) +Oper (Op8cd0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 6, GRL, SRL, 144) +Oper (Op8cd8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 6, GRL, SRL, 144) +Oper (Op8ce0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 148) +Oper (Op8ce8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 148) +Oper (Op8cf0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 6, GRL, SRL, 152) +Oper (Op8cf8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op8dc0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 6, GRL, SRL, 160) +Oper (Op8dd0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 6, GRL, SRL, 164) +Oper (Op8dd8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 6, GRL, SRL, 164) +Oper (Op8de0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 164) +Oper (Op8de8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 168) +Oper (Op8df0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 6, GRL, SRL, 168) +Oper (Op8df8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op8ec0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 7, GRL, SRL, 140) +Oper (Op8ed0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 7, GRL, SRL, 144) +Oper (Op8ed8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 7, GRL, SRL, 144) +Oper (Op8ee0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 148) +Oper (Op8ee8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 148) +Oper (Op8ef0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 7, GRL, SRL, 152) +Oper (Op8ef8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op8fc0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 7, GRL, SRL, 160) +Oper (Op8fd0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 7, GRL, SRL, 164) +Oper (Op8fd8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 7, GRL, SRL, 164) +Oper (Op8fe0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 164) +Oper (Op8fe8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 168) +Oper (Op8ff0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 7, GRL, SRL, 168) +Oper (Op8ff8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op0c00, DoCmpB, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SN, 8) +Oper (Op0c10, DoCmpB, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SN, 12) +Oper (Op0c18, DoCmpB, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SN, 12) +Oper (Op0c20, DoCmpB, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SN, 16) +Oper (Op0c28, DoCmpB, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SN, 16) +Oper (Op0c30, DoCmpB, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SN, 20) +Oper (Op0c38, DoCmpB, DB, SimmB, 0, DB, DA, Ceaw, ins7, GMB, SN, (cycles+19)&0xfffffffc) +Oper (Op0c40, DoCmpW, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SN, 8) +Oper (Op0c50, DoCmpW, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SN, 12) +Oper (Op0c58, DoCmpW, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SN, 12) +Oper (Op0c60, DoCmpW, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SN, 16) +Oper (Op0c68, DoCmpW, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SN, 16) +Oper (Op0c70, DoCmpW, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SN, 20) +Oper (Op0c78, DoCmpW, DW, SimmW, 0, DW, DA, Ceaw, ins7, GMW, SN, (cycles+19)&0xfffffffc) +Oper (Op0c80, DoCmpL, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SN, 16) +Oper (Op0c90, DoCmpL, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SN, 20) +Oper (Op0c98, DoCmpL, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SN, 20) +Oper (Op0ca0, DoCmpL, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SN, 24) +Oper (Op0ca8, DoCmpL, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SN, 24) +Oper (Op0cb0, DoCmpL, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SN, 28) +Oper (Op0cb8, DoCmpL, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SN, (cycles+27)&0xfffffffc) + +Oper (Opc100, DoABCD, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Opc108, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 0, GMB, SMB, 20) +Oper (Opc300, DoABCD, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Opc308, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 1, GMB, SMB, 20) +Oper (Opc500, DoABCD, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Opc508, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 2, GMB, SMB, 20) +Oper (Opc700, DoABCD, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Opc708, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 3, GMB, SMB, 20) +Oper (Opc900, DoABCD, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Opc908, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 4, GMB, SMB, 20) +Oper (Opcb00, DoABCD, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Opcb08, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 5, GMB, SMB, 20) +Oper (Opcd00, DoABCD, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Opcd08, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 6, GMB, SMB, 20) +Oper (Opcf00, DoABCD, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Opcf08, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 7, GMB, SMB, 20) + +Oper (Op8100, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Op8108, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 0, GMB, SMB, 20) +Oper (Op8300, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Op8308, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 1, GMB, SMB, 20) +Oper (Op8500, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Op8508, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 2, GMB, SMB, 20) +Oper (Op8700, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Op8708, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 3, GMB, SMB, 20) +Oper (Op8900, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Op8908, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 4, GMB, SMB, 20) +Oper (Op8b00, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Op8b08, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 5, GMB, SMB, 20) +Oper (Op8d00, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Op8d08, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 6, GMB, SMB, 20) +Oper (Op8f00, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Op8f08, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 7, GMB, SMB, 20) + +Oper (Op4800, DoNBCD, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SRB, 8) +Oper (Op4810, DoNBCD, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op4818, DoNBCD, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op4820, DoNBCD, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op4828, DoNBCD, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op4830, DoNBCD, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op4838, DoNBCD, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) diff --git a/MCUME_esp32/espcastaway/main/68korig/op68klogop.cpp b/MCUME_esp32/espcastaway/main/68korig/op68klogop.cpp new file mode 100755 index 0000000..2f1e62f --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/op68klogop.cpp @@ -0,0 +1,974 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - 68k logical instructions +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 10.07.2002 JH Minor clarification when CCR/SR is target (without effect) +* 27.08.2002 JH ... with effect! Fixed bug. Restructured & clarified. +*/ +#ifndef PROTOH +static char sccsid[] = "$Id: op68klogop.c,v 1.3 2002/08/27 01:21:11 jhoenig Exp $"; +#include "68000.h" +#include "op68k.h" +#include "operin.h" + +/* +* Opfuncs. +*/ +#define OlogSR(Code, Op, OpSR, Priv, DeclS, Get1, DeclT, Get2, Set2, GetSR, SetSR, retval)\ + unsigned long Code(operin)\ +{\ + register unsigned long cycles=0;\ + DeclS(source)\ + DeclT(target)\ + long address;\ + switch ins7 {\ + case 0x0:\ + Get1(source, 0)\ + address = GetMPCW();\ + pc += 2;\ + Get2(address, target)\ + Op(target, source)\ + Set2(address, target)\ + break;\ + case 0x1:\ + Get1(source, 0)\ + address = GetMPCL();\ + pc += 4;\ + Get2(address, target)\ + Op(target, source)\ + Set2(address, target)\ + break;\ + case 0x4:\ + if (Priv && !GetS()) { ExceptionGroup1(PRIV); };\ + Get1(source, 0)\ + GetSR(address2, target)\ + OpSR(target, source)\ + SetSR(address2, target)\ + break;\ + default:\ + ExceptionGroup1(ILLINSTR);\ + break;\ +}\ + return retval;\ +} + +#define DoAnd(target,source) target &= source; ClrCVSetNZ(target); +#define DoAndSR(target,source) target &= source; + +#define DoEor(target,source) target ^= source; ClrCVSetNZ(target); +#define DoEorSR(target,source) target ^= source; + +#define DoOr(target,source) target |= source; ClrCVSetNZ(target); +#define DoOrSR(target,source) target |= source; + +#else + +#define OlogSR(a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12) \ +extern unsigned long a1(operin); + +#endif + +Oper (Opc000, DoAnd, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4) +Oper (Opc010, DoAnd, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Opc018, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Opc020, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Opc028, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Opc030, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SRB, 16) +Oper (Opc038, DoAnd, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opc040, DoAnd, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Opc050, DoAnd, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Opc058, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Opc060, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Opc068, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Opc070, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SRW, 16) +Oper (Opc078, DoAnd, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opc080, DoAnd, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Opc090, DoAnd, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Opc098, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Opc0a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Opc0a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Opc0b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Opc0b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opc110, DoAnd, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opc118, DoAnd, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opc120, DoAnd, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opc128, DoAnd, DB, SdB, 0, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opc130, DoAnd, DB, SdB, 0, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opc138, DoAnd, DB, SdB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opc150, DoAnd, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opc158, DoAnd, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opc160, DoAnd, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opc168, DoAnd, DW, SdW, 0, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opc170, DoAnd, DW, SdW, 0, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opc178, DoAnd, DW, SdW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opc190, DoAnd, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opc198, DoAnd, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opc1a0, DoAnd, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opc1a8, DoAnd, DL, SdL, 0, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opc1b0, DoAnd, DL, SdL, 0, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opc1b8, DoAnd, DL, SdL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opc200, DoAnd, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4) +Oper (Opc210, DoAnd, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Opc218, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Opc220, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Opc228, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Opc230, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SRB, 16) +Oper (Opc238, DoAnd, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opc240, DoAnd, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Opc250, DoAnd, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Opc258, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Opc260, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Opc268, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Opc270, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SRW, 16) +Oper (Opc278, DoAnd, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opc280, DoAnd, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Opc290, DoAnd, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Opc298, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Opc2a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Opc2a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Opc2b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Opc2b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opc310, DoAnd, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opc318, DoAnd, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opc320, DoAnd, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opc328, DoAnd, DB, SdB, 1, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opc330, DoAnd, DB, SdB, 1, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opc338, DoAnd, DB, SdB, 1, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opc350, DoAnd, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opc358, DoAnd, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opc360, DoAnd, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opc368, DoAnd, DW, SdW, 1, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opc370, DoAnd, DW, SdW, 1, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opc378, DoAnd, DW, SdW, 1, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opc390, DoAnd, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opc398, DoAnd, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opc3a0, DoAnd, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opc3a8, DoAnd, DL, SdL, 1, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opc3b0, DoAnd, DL, SdL, 1, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opc3b8, DoAnd, DL, SdL, 1, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opc400, DoAnd, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4) +Oper (Opc410, DoAnd, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Opc418, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Opc420, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Opc428, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Opc430, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SRB, 16) +Oper (Opc438, DoAnd, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opc440, DoAnd, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Opc450, DoAnd, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Opc458, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Opc460, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Opc468, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Opc470, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SRW, 16) +Oper (Opc478, DoAnd, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opc480, DoAnd, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Opc490, DoAnd, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Opc498, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Opc4a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Opc4a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Opc4b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Opc4b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opc510, DoAnd, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opc518, DoAnd, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opc520, DoAnd, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opc528, DoAnd, DB, SdB, 2, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opc530, DoAnd, DB, SdB, 2, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opc538, DoAnd, DB, SdB, 2, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opc550, DoAnd, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opc558, DoAnd, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opc560, DoAnd, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opc568, DoAnd, DW, SdW, 2, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opc570, DoAnd, DW, SdW, 2, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opc578, DoAnd, DW, SdW, 2, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opc590, DoAnd, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opc598, DoAnd, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opc5a0, DoAnd, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opc5a8, DoAnd, DL, SdL, 2, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opc5b0, DoAnd, DL, SdL, 2, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opc5b8, DoAnd, DL, SdL, 2, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opc600, DoAnd, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4) +Oper (Opc610, DoAnd, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Opc618, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Opc620, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Opc628, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Opc630, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SRB, 16) +Oper (Opc638, DoAnd, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opc640, DoAnd, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Opc650, DoAnd, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Opc658, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Opc660, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Opc668, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Opc670, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SRW, 16) +Oper (Opc678, DoAnd, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opc680, DoAnd, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Opc690, DoAnd, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Opc698, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Opc6a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Opc6a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Opc6b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Opc6b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opc710, DoAnd, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opc718, DoAnd, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opc720, DoAnd, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opc728, DoAnd, DB, SdB, 3, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opc730, DoAnd, DB, SdB, 3, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opc738, DoAnd, DB, SdB, 3, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opc750, DoAnd, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opc758, DoAnd, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opc760, DoAnd, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opc768, DoAnd, DW, SdW, 3, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opc770, DoAnd, DW, SdW, 3, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opc778, DoAnd, DW, SdW, 3, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opc790, DoAnd, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opc798, DoAnd, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opc7a0, DoAnd, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opc7a8, DoAnd, DL, SdL, 3, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opc7b0, DoAnd, DL, SdL, 3, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opc7b8, DoAnd, DL, SdL, 3, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opc800, DoAnd, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4) +Oper (Opc810, DoAnd, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Opc818, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Opc820, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Opc828, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Opc830, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SRB, 16) +Oper (Opc838, DoAnd, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opc840, DoAnd, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Opc850, DoAnd, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Opc858, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Opc860, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Opc868, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Opc870, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SRW, 16) +Oper (Opc878, DoAnd, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opc880, DoAnd, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Opc890, DoAnd, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Opc898, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Opc8a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Opc8a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Opc8b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Opc8b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opc910, DoAnd, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opc918, DoAnd, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opc920, DoAnd, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opc928, DoAnd, DB, SdB, 4, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opc930, DoAnd, DB, SdB, 4, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opc938, DoAnd, DB, SdB, 4, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opc950, DoAnd, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opc958, DoAnd, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opc960, DoAnd, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opc968, DoAnd, DW, SdW, 4, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opc970, DoAnd, DW, SdW, 4, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opc978, DoAnd, DW, SdW, 4, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opc990, DoAnd, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opc998, DoAnd, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opc9a0, DoAnd, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opc9a8, DoAnd, DL, SdL, 4, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opc9b0, DoAnd, DL, SdL, 4, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opc9b8, DoAnd, DL, SdL, 4, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opca00, DoAnd, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4) +Oper (Opca10, DoAnd, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Opca18, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Opca20, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Opca28, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Opca30, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SRB, 16) +Oper (Opca38, DoAnd, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opca40, DoAnd, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Opca50, DoAnd, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Opca58, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Opca60, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Opca68, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Opca70, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SRW, 16) +Oper (Opca78, DoAnd, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opca80, DoAnd, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Opca90, DoAnd, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Opca98, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Opcaa0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Opcaa8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Opcab0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Opcab8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opcb10, DoAnd, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opcb18, DoAnd, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opcb20, DoAnd, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opcb28, DoAnd, DB, SdB, 5, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opcb30, DoAnd, DB, SdB, 5, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opcb38, DoAnd, DB, SdB, 5, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opcb50, DoAnd, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opcb58, DoAnd, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opcb60, DoAnd, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opcb68, DoAnd, DW, SdW, 5, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opcb70, DoAnd, DW, SdW, 5, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opcb78, DoAnd, DW, SdW, 5, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opcb90, DoAnd, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opcb98, DoAnd, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opcba0, DoAnd, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opcba8, DoAnd, DL, SdL, 5, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opcbb0, DoAnd, DL, SdL, 5, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opcbb8, DoAnd, DL, SdL, 5, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opcc00, DoAnd, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4) +Oper (Opcc10, DoAnd, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Opcc18, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Opcc20, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Opcc28, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Opcc30, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SRB, 16) +Oper (Opcc38, DoAnd, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opcc40, DoAnd, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Opcc50, DoAnd, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Opcc58, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Opcc60, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Opcc68, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Opcc70, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SRW, 16) +Oper (Opcc78, DoAnd, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opcc80, DoAnd, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Opcc90, DoAnd, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Opcc98, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Opcca0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Opcca8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Opccb0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Opccb8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opcd10, DoAnd, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opcd18, DoAnd, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opcd20, DoAnd, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opcd28, DoAnd, DB, SdB, 6, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opcd30, DoAnd, DB, SdB, 6, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opcd38, DoAnd, DB, SdB, 6, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opcd50, DoAnd, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opcd58, DoAnd, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opcd60, DoAnd, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opcd68, DoAnd, DW, SdW, 6, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opcd70, DoAnd, DW, SdW, 6, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opcd78, DoAnd, DW, SdW, 6, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opcd90, DoAnd, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opcd98, DoAnd, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opcda0, DoAnd, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opcda8, DoAnd, DL, SdL, 6, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opcdb0, DoAnd, DL, SdL, 6, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opcdb8, DoAnd, DL, SdL, 6, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opce00, DoAnd, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4) +Oper (Opce10, DoAnd, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Opce18, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Opce20, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Opce28, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Opce30, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SRB, 16) +Oper (Opce38, DoAnd, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opce40, DoAnd, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Opce50, DoAnd, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Opce58, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Opce60, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Opce68, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Opce70, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SRW, 16) +Oper (Opce78, DoAnd, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opce80, DoAnd, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Opce90, DoAnd, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Opce98, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Opcea0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Opcea8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Opceb0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Opceb8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opcf10, DoAnd, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opcf18, DoAnd, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opcf20, DoAnd, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opcf28, DoAnd, DB, SdB, 7, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opcf30, DoAnd, DB, SdB, 7, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opcf38, DoAnd, DB, SdB, 7, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opcf50, DoAnd, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opcf58, DoAnd, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opcf60, DoAnd, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opcf68, DoAnd, DW, SdW, 7, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opcf70, DoAnd, DW, SdW, 7, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opcf78, DoAnd, DW, SdW, 7, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opcf90, DoAnd, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opcf98, DoAnd, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opcfa0, DoAnd, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opcfa8, DoAnd, DL, SdL, 7, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opcfb0, DoAnd, DL, SdL, 7, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opcfb8, DoAnd, DL, SdL, 7, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8000, DoOr, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4) +Oper (Op8010, DoOr, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Op8018, DoOr, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Op8020, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Op8028, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Op8030, DoOr, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SRB, 16) +Oper (Op8038, DoOr, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8040, DoOr, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Op8050, DoOr, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Op8058, DoOr, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Op8060, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Op8068, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Op8070, DoOr, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SRW, 16) +Oper (Op8078, DoOr, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8080, DoOr, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Op8090, DoOr, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Op8098, DoOr, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Op80a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Op80a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Op80b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Op80b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8110, DoOr, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8118, DoOr, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8120, DoOr, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8128, DoOr, DB, SdB, 0, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8130, DoOr, DB, SdB, 0, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8138, DoOr, DB, SdB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8150, DoOr, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8158, DoOr, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8160, DoOr, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8168, DoOr, DW, SdW, 0, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8170, DoOr, DW, SdW, 0, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8178, DoOr, DW, SdW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8190, DoOr, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8198, DoOr, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op81a0, DoOr, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op81a8, DoOr, DL, SdL, 0, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op81b0, DoOr, DL, SdL, 0, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op81b8, DoOr, DL, SdL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8200, DoOr, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4) +Oper (Op8210, DoOr, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Op8218, DoOr, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Op8220, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Op8228, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Op8230, DoOr, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SRB, 16) +Oper (Op8238, DoOr, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8240, DoOr, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Op8250, DoOr, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Op8258, DoOr, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Op8260, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Op8268, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Op8270, DoOr, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SRW, 16) +Oper (Op8278, DoOr, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8280, DoOr, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Op8290, DoOr, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Op8298, DoOr, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Op82a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Op82a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Op82b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Op82b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8310, DoOr, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8318, DoOr, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8320, DoOr, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8328, DoOr, DB, SdB, 1, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8330, DoOr, DB, SdB, 1, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8338, DoOr, DB, SdB, 1, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8350, DoOr, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8358, DoOr, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8360, DoOr, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8368, DoOr, DW, SdW, 1, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8370, DoOr, DW, SdW, 1, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8378, DoOr, DW, SdW, 1, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8390, DoOr, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8398, DoOr, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op83a0, DoOr, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op83a8, DoOr, DL, SdL, 1, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op83b0, DoOr, DL, SdL, 1, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op83b8, DoOr, DL, SdL, 1, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8400, DoOr, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4) +Oper (Op8410, DoOr, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Op8418, DoOr, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Op8420, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Op8428, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Op8430, DoOr, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SRB, 16) +Oper (Op8438, DoOr, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8440, DoOr, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Op8450, DoOr, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Op8458, DoOr, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Op8460, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Op8468, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Op8470, DoOr, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SRW, 16) +Oper (Op8478, DoOr, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8480, DoOr, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Op8490, DoOr, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Op8498, DoOr, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Op84a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Op84a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Op84b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Op84b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8510, DoOr, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8518, DoOr, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8520, DoOr, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8528, DoOr, DB, SdB, 2, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8530, DoOr, DB, SdB, 2, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8538, DoOr, DB, SdB, 2, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8550, DoOr, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8558, DoOr, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8560, DoOr, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8568, DoOr, DW, SdW, 2, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8570, DoOr, DW, SdW, 2, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8578, DoOr, DW, SdW, 2, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8590, DoOr, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8598, DoOr, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op85a0, DoOr, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op85a8, DoOr, DL, SdL, 2, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op85b0, DoOr, DL, SdL, 2, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op85b8, DoOr, DL, SdL, 2, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8600, DoOr, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4) +Oper (Op8610, DoOr, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Op8618, DoOr, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Op8620, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Op8628, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Op8630, DoOr, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SRB, 16) +Oper (Op8638, DoOr, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8640, DoOr, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Op8650, DoOr, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Op8658, DoOr, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Op8660, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Op8668, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Op8670, DoOr, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SRW, 16) +Oper (Op8678, DoOr, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8680, DoOr, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Op8690, DoOr, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Op8698, DoOr, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Op86a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Op86a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Op86b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Op86b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8710, DoOr, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8718, DoOr, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8720, DoOr, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8728, DoOr, DB, SdB, 3, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8730, DoOr, DB, SdB, 3, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8738, DoOr, DB, SdB, 3, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8750, DoOr, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8758, DoOr, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8760, DoOr, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8768, DoOr, DW, SdW, 3, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8770, DoOr, DW, SdW, 3, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8778, DoOr, DW, SdW, 3, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8790, DoOr, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8798, DoOr, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op87a0, DoOr, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op87a8, DoOr, DL, SdL, 3, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op87b0, DoOr, DL, SdL, 3, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op87b8, DoOr, DL, SdL, 3, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8800, DoOr, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4) +Oper (Op8810, DoOr, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Op8818, DoOr, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Op8820, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Op8828, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Op8830, DoOr, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SRB, 16) +Oper (Op8838, DoOr, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8840, DoOr, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Op8850, DoOr, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Op8858, DoOr, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Op8860, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Op8868, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Op8870, DoOr, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SRW, 16) +Oper (Op8878, DoOr, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8880, DoOr, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Op8890, DoOr, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Op8898, DoOr, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Op88a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Op88a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Op88b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Op88b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8910, DoOr, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8918, DoOr, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8920, DoOr, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8928, DoOr, DB, SdB, 4, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8930, DoOr, DB, SdB, 4, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8938, DoOr, DB, SdB, 4, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8950, DoOr, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8958, DoOr, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8960, DoOr, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8968, DoOr, DW, SdW, 4, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8970, DoOr, DW, SdW, 4, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8978, DoOr, DW, SdW, 4, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8990, DoOr, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8998, DoOr, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op89a0, DoOr, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op89a8, DoOr, DL, SdL, 4, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op89b0, DoOr, DL, SdL, 4, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op89b8, DoOr, DL, SdL, 4, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8a00, DoOr, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4) +Oper (Op8a10, DoOr, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Op8a18, DoOr, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Op8a20, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Op8a28, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Op8a30, DoOr, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SRB, 16) +Oper (Op8a38, DoOr, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8a40, DoOr, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Op8a50, DoOr, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Op8a58, DoOr, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Op8a60, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Op8a68, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Op8a70, DoOr, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SRW, 16) +Oper (Op8a78, DoOr, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8a80, DoOr, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Op8a90, DoOr, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Op8a98, DoOr, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Op8aa0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Op8aa8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Op8ab0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Op8ab8, DoOr, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8b10, DoOr, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8b18, DoOr, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8b20, DoOr, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8b28, DoOr, DB, SdB, 5, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8b30, DoOr, DB, SdB, 5, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8b38, DoOr, DB, SdB, 5, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8b50, DoOr, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8b58, DoOr, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8b60, DoOr, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8b68, DoOr, DW, SdW, 5, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8b70, DoOr, DW, SdW, 5, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8b78, DoOr, DW, SdW, 5, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8b90, DoOr, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8b98, DoOr, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op8ba0, DoOr, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op8ba8, DoOr, DL, SdL, 5, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op8bb0, DoOr, DL, SdL, 5, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op8bb8, DoOr, DL, SdL, 5, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8c00, DoOr, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4) +Oper (Op8c10, DoOr, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Op8c18, DoOr, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Op8c20, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Op8c28, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Op8c30, DoOr, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SRB, 16) +Oper (Op8c38, DoOr, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8c40, DoOr, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Op8c50, DoOr, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Op8c58, DoOr, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Op8c60, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Op8c68, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Op8c70, DoOr, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SRW, 16) +Oper (Op8c78, DoOr, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8c80, DoOr, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Op8c90, DoOr, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Op8c98, DoOr, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Op8ca0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Op8ca8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Op8cb0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Op8cb8, DoOr, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8d10, DoOr, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8d18, DoOr, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8d20, DoOr, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8d28, DoOr, DB, SdB, 6, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8d30, DoOr, DB, SdB, 6, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8d38, DoOr, DB, SdB, 6, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8d50, DoOr, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8d58, DoOr, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8d60, DoOr, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8d68, DoOr, DW, SdW, 6, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8d70, DoOr, DW, SdW, 6, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8d78, DoOr, DW, SdW, 6, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8d90, DoOr, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8d98, DoOr, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op8da0, DoOr, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op8da8, DoOr, DL, SdL, 6, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op8db0, DoOr, DL, SdL, 6, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op8db8, DoOr, DL, SdL, 6, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8e00, DoOr, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4) +Oper (Op8e10, DoOr, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Op8e18, DoOr, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Op8e20, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Op8e28, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Op8e30, DoOr, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SRB, 16) +Oper (Op8e38, DoOr, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8e40, DoOr, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Op8e50, DoOr, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Op8e58, DoOr, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Op8e60, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Op8e68, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Op8e70, DoOr, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SRW, 16) +Oper (Op8e78, DoOr, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8e80, DoOr, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Op8e90, DoOr, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Op8e98, DoOr, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Op8ea0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Op8ea8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Op8eb0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Op8eb8, DoOr, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8f10, DoOr, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8f18, DoOr, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8f20, DoOr, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8f28, DoOr, DB, SdB, 7, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8f30, DoOr, DB, SdB, 7, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8f38, DoOr, DB, SdB, 7, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8f50, DoOr, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8f58, DoOr, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8f60, DoOr, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8f68, DoOr, DW, SdW, 7, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8f70, DoOr, DW, SdW, 7, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8f78, DoOr, DW, SdW, 7, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8f90, DoOr, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8f98, DoOr, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op8fa0, DoOr, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op8fa8, DoOr, DL, SdL, 7, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op8fb0, DoOr, DL, SdL, 7, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op8fb8, DoOr, DL, SdL, 7, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opb100, DoEor, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opb110, DoEor, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opb118, DoEor, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opb120, DoEor, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opb128, DoEor, DB, SdB, 0, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opb130, DoEor, DB, SdB, 0, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opb138, DoEor, DB, SdB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opb140, DoEor, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opb150, DoEor, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opb158, DoEor, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opb160, DoEor, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opb168, DoEor, DW, SdW, 0, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opb170, DoEor, DW, SdW, 0, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opb178, DoEor, DW, SdW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opb180, DoEor, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opb190, DoEor, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opb198, DoEor, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opb1a0, DoEor, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opb1a8, DoEor, DL, SdL, 0, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opb1b0, DoEor, DL, SdL, 0, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opb1b8, DoEor, DL, SdL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opb300, DoEor, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opb310, DoEor, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opb318, DoEor, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opb320, DoEor, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opb328, DoEor, DB, SdB, 1, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opb330, DoEor, DB, SdB, 1, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opb338, DoEor, DB, SdB, 1, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opb340, DoEor, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opb350, DoEor, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opb358, DoEor, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opb360, DoEor, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opb368, DoEor, DW, SdW, 1, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opb370, DoEor, DW, SdW, 1, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opb378, DoEor, DW, SdW, 1, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opb380, DoEor, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opb390, DoEor, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opb398, DoEor, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opb3a0, DoEor, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opb3a8, DoEor, DL, SdL, 1, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opb3b0, DoEor, DL, SdL, 1, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opb3b8, DoEor, DL, SdL, 1, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opb500, DoEor, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opb510, DoEor, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opb518, DoEor, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opb520, DoEor, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opb528, DoEor, DB, SdB, 2, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opb530, DoEor, DB, SdB, 2, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opb538, DoEor, DB, SdB, 2, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opb540, DoEor, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opb550, DoEor, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opb558, DoEor, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opb560, DoEor, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opb568, DoEor, DW, SdW, 2, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opb570, DoEor, DW, SdW, 2, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opb578, DoEor, DW, SdW, 2, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opb580, DoEor, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opb590, DoEor, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opb598, DoEor, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opb5a0, DoEor, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opb5a8, DoEor, DL, SdL, 2, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opb5b0, DoEor, DL, SdL, 2, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opb5b8, DoEor, DL, SdL, 2, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opb700, DoEor, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opb710, DoEor, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opb718, DoEor, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opb720, DoEor, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opb728, DoEor, DB, SdB, 3, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opb730, DoEor, DB, SdB, 3, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opb738, DoEor, DB, SdB, 3, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opb740, DoEor, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opb750, DoEor, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opb758, DoEor, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opb760, DoEor, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opb768, DoEor, DW, SdW, 3, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opb770, DoEor, DW, SdW, 3, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opb778, DoEor, DW, SdW, 3, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opb780, DoEor, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opb790, DoEor, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opb798, DoEor, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opb7a0, DoEor, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opb7a8, DoEor, DL, SdL, 3, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opb7b0, DoEor, DL, SdL, 3, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opb7b8, DoEor, DL, SdL, 3, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opb900, DoEor, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opb910, DoEor, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opb918, DoEor, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opb920, DoEor, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opb928, DoEor, DB, SdB, 4, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opb930, DoEor, DB, SdB, 4, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opb938, DoEor, DB, SdB, 4, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opb940, DoEor, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opb950, DoEor, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opb958, DoEor, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opb960, DoEor, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opb968, DoEor, DW, SdW, 4, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opb970, DoEor, DW, SdW, 4, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opb978, DoEor, DW, SdW, 4, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opb980, DoEor, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opb990, DoEor, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opb998, DoEor, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opb9a0, DoEor, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opb9a8, DoEor, DL, SdL, 4, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opb9b0, DoEor, DL, SdL, 4, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opb9b8, DoEor, DL, SdL, 4, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opbb00, DoEor, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opbb10, DoEor, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opbb18, DoEor, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opbb20, DoEor, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opbb28, DoEor, DB, SdB, 5, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opbb30, DoEor, DB, SdB, 5, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opbb38, DoEor, DB, SdB, 5, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opbb40, DoEor, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opbb50, DoEor, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opbb58, DoEor, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opbb60, DoEor, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opbb68, DoEor, DW, SdW, 5, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opbb70, DoEor, DW, SdW, 5, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opbb78, DoEor, DW, SdW, 5, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opbb80, DoEor, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opbb90, DoEor, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opbb98, DoEor, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opbba0, DoEor, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opbba8, DoEor, DL, SdL, 5, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opbbb0, DoEor, DL, SdL, 5, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opbbb8, DoEor, DL, SdL, 5, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opbd00, DoEor, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opbd10, DoEor, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opbd18, DoEor, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opbd20, DoEor, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opbd28, DoEor, DB, SdB, 6, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opbd30, DoEor, DB, SdB, 6, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opbd38, DoEor, DB, SdB, 6, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opbd40, DoEor, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opbd50, DoEor, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opbd58, DoEor, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opbd60, DoEor, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opbd68, DoEor, DW, SdW, 6, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opbd70, DoEor, DW, SdW, 6, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opbd78, DoEor, DW, SdW, 6, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opbd80, DoEor, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opbd90, DoEor, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opbd98, DoEor, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opbda0, DoEor, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opbda8, DoEor, DL, SdL, 6, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opbdb0, DoEor, DL, SdL, 6, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opbdb8, DoEor, DL, SdL, 6, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opbf00, DoEor, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opbf10, DoEor, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opbf18, DoEor, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opbf20, DoEor, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opbf28, DoEor, DB, SdB, 7, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opbf30, DoEor, DB, SdB, 7, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opbf38, DoEor, DB, SdB, 7, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opbf40, DoEor, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opbf50, DoEor, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opbf58, DoEor, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opbf60, DoEor, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opbf68, DoEor, DW, SdW, 7, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opbf70, DoEor, DW, SdW, 7, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opbf78, DoEor, DW, SdW, 7, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opbf80, DoEor, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opbf90, DoEor, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opbf98, DoEor, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opbfa0, DoEor, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opbfa8, DoEor, DL, SdL, 7, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opbfb0, DoEor, DL, SdL, 7, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opbfb8, DoEor, DL, SdL, 7, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op0000, DoOr, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8) +Oper (Op0010, DoOr, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op0018, DoOr, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op0020, DoOr, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op0028, DoOr, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op0030, DoOr, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +OlogSR (Op0038, DoOr, DoOrSR, 0, DB, SimmB, DB, GMB, SMB, GCB, SCB, 20) +Oper (Op0040, DoOr, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8) +Oper (Op0050, DoOr, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16) +Oper (Op0058, DoOr, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16) +Oper (Op0060, DoOr, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20) +Oper (Op0068, DoOr, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20) +Oper (Op0070, DoOr, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24) +OlogSR (Op0078, DoOr, DoOrSR, 1, DW, SimmW, DW, GMW, SMW, GCW, SCW, 20) +Oper (Op0080, DoOr, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16) +Oper (Op0090, DoOr, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28) +Oper (Op0098, DoOr, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28) +Oper (Op00a0, DoOr, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32) +Oper (Op00a8, DoOr, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32) +Oper (Op00b0, DoOr, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36) +Oper (Op00b8, DoOr, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc) + +Oper (Op0200, DoAnd, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8) +Oper (Op0210, DoAnd, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op0218, DoAnd, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op0220, DoAnd, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op0228, DoAnd, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op0230, DoAnd, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +OlogSR (Op0238, DoAnd, DoAndSR, 0, DB, SimmB, DB, GMB, SMB, GCB, SCB, 20) +Oper (Op0240, DoAnd, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8) +Oper (Op0250, DoAnd, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16) +Oper (Op0258, DoAnd, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16) +Oper (Op0260, DoAnd, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20) +Oper (Op0268, DoAnd, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20) +Oper (Op0270, DoAnd, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24) +OlogSR (Op0278, DoAnd, DoAndSR, 1, DW, SimmW, DW, GMW, SMW, GCW, SCW, 20) +Oper (Op0280, DoAnd, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16) +Oper (Op0290, DoAnd, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28) +Oper (Op0298, DoAnd, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28) +Oper (Op02a0, DoAnd, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32) +Oper (Op02a8, DoAnd, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32) +Oper (Op02b0, DoAnd, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36) +Oper (Op02b8, DoAnd, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc) + +Oper (Op0a00, DoEor, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8) +Oper (Op0a10, DoEor, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op0a18, DoEor, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op0a20, DoEor, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op0a28, DoEor, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op0a30, DoEor, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +OlogSR (Op0a38, DoEor, DoEorSR, 0, DB, SimmB, DB, GMB, SMB, GCB, SCB, 20) +Oper (Op0a40, DoEor, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8) +Oper (Op0a50, DoEor, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16) +Oper (Op0a58, DoEor, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16) +Oper (Op0a60, DoEor, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20) +Oper (Op0a68, DoEor, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20) +Oper (Op0a70, DoEor, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24) +OlogSR (Op0a78, DoEor, DoEorSR, 1, DW, SimmW, DW, GMW, SMW, GCW, SCW, 20) +Oper (Op0a80, DoEor, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16) +Oper (Op0a90, DoEor, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28) +Oper (Op0a98, DoEor, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28) +Oper (Op0aa0, DoEor, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32) +Oper (Op0aa8, DoEor, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32) +Oper (Op0ab0, DoEor, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36) +Oper (Op0ab8, DoEor, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc) diff --git a/MCUME_esp32/espcastaway/main/68korig/op68kmisc.cpp b/MCUME_esp32/espcastaway/main/68korig/op68kmisc.cpp new file mode 100755 index 0000000..f0f10cf --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/op68kmisc.cpp @@ -0,0 +1,1896 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - 68k miscellaneous instructions +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 12.06.2002 JH Correct bus error/address error exception stack frame +* 14.06.2002 JH Implemented STOP, shutdown CPU after multiple bus errors. +* Removed inst parameter from CPU opcode functions. +* 09.07.2002 JH STOP should work now as expected. +* 10.07.2002 JH Fixed X, C and Z-Flag for NEGX, X and C for NEG. +* 27.08.2002 JH Some clarifications in op68k.h +* Implemented additional 68010 registers and instructions. +* 31.08.2002 JH Implemented M68010 exception stack frames. +* 10.09.2002 JH Fixed MOVE to/from CCR: word size +* 15.09.2002 JH Minor SR/Bcc/Scc optimization. +* 25.10.2002 JH CHKTRACE no longer optional, improved implementation. +* PC correct now if MOVE to SR raises privilege violation. +*/ +#ifndef PROTOH +static char sccsid[] = "$Id: op68kmisc.c,v 1.11 2002/10/25 21:56:27 jhoenig Exp $"; +#include "68000.h" +#include "op68k.h" +#include "operin.h" + + +/* +* Opfuncs. +*/ +#define OMoves(Code, Decl, CalcEA, GetReg, SetReg, GetMem, SetMem, retval) \ + unsigned long Code(operin)\ +{\ + register unsigned long cycles=0;\ + Decl(source)\ + unsigned long address;\ + unsigned short ext = GetMPCW();\ + unsigned short index = ext >> 12;\ + if (!GetS()) { ExceptionGroup1(PRIV); };\ + pc += 2;\ + CalcEA(address, ins7)\ + if (ext & 0x800) { \ + GetReg(index, source)\ + SetMem(address, source)\ + } else {\ + GetMem(address, source)\ + SetReg(index, source)\ +}\ + return retval;\ +} + +#define OMoveToSR(Code, Get1, retval)\ + unsigned long Code(operin)\ +{\ + register unsigned long cycles=0;\ + DW(source)\ + if (!GetS()) ExceptionGroup1(PRIV);\ + Get1(source, ins7)\ + SetSRW(source);\ + return retval;\ +} + +#define DoBtst8(target,source) SetZI ((target>>(source & 7))&1); +#define DoBtst32(target,source) SetZI ((target>>(source & 31))&1); +#define DoBchg8(target,source) {uint32 mask=(1 << (source & 7)); SetZI(target&mask); target^=mask;} +#define DoBchg32(target,source) {uint32 mask=(1 << (source & 31)); SetZI(target&mask); target^=mask;} +#define DoBclr8(target,source) {uint32 mask=(1 << (source & 7)); SetZI(target&mask); target&=~mask;} +#define DoBclr32(target,source) {uint32 mask=(1 << (source & 31)); SetZI(target&mask); target&=~mask;} +#define DoBset8(target,source) {uint32 mask=(1 << (source & 7)); SetZI(target&mask); target|=mask;} +#define DoBset32(target,source) {uint32 mask=(1 << (source & 31)); SetZI(target&mask); target|=mask;} +#define DoBra(target,source) if (!source) source = FastMPCW (); pc += source; +#define DoBras(target,source) pc += source; +#define DoBsr(target,source) reg[15] -= 4; if (!source) { source = FastMPCW (); SetMemL (reg[15], GetPC() + 2);} else {SetMemL (reg[15], GetPC());} pc += source; +#define DoBsrs(target,source) reg[15] -= 4; SetMemL (reg[15], GetPC()); pc += source; +#define DoBhi(target,source) if (!source) {source = FastMPCW (); if (CChi) {pc += source;} else { pc += 2;}} else {if (CChi) pc += source;}; +#define DoBhis(target,source) if (CChi) pc += source; +#define DoBls(target,source) if (!source) {source = FastMPCW (); if (CCls) {pc += source;} else { pc += 2;}} else {if (CCls) pc += source;}; +#define DoBlss(target,source) if (CCls) pc += source; +#define DoBcc(target,source) if (!source) {source = FastMPCW (); if (CCcc) {pc += source;} else { pc += 2;}} else {if (CCcc) pc += source;}; +#define DoBccs(target,source) if (CCcc) pc += source; +#define DoBcs(target,source) if (!source) {source = FastMPCW (); if (CCcs) {pc += source;} else { pc += 2;}} else {if (CCcs) pc += source;}; +#define DoBcss(target,source) if (CCcs) pc += source; +#define DoBne(target,source) if (!source) {source = FastMPCW (); if (CCne) {pc += source;} else { pc += 2;}} else {if (CCne) pc += source;}; +#define DoBnes(target,source) if (CCne) pc += source; +#define DoBeq(target,source) if (!source) {source = FastMPCW (); if (CCeq) {pc += source;} else { pc += 2;}} else {if (CCeq) pc += source;}; +#define DoBeqs(target,source) if (CCeq) pc += source; +#define DoBvc(target,source) if (!source) {source = FastMPCW (); if (CCvc) {pc += source;} else { pc += 2;}} else {if (CCvc) pc += source;}; +#define DoBvcs(target,source) if (CCvc) pc += source; +#define DoBvs(target,source) if (!source) {source = FastMPCW (); if (CCvs) {pc += source;} else { pc += 2;}} else {if (CCvs) pc += source;}; +#define DoBvss(target,source) if (CCvs) pc += source; +#define DoBpl(target,source) if (!source) {source = FastMPCW (); if (CCpl) {pc += source;} else { pc += 2;}} else {if (CCpl) pc += source;}; +#define DoBpls(target,source) if (CCpl) pc += source; +#define DoBmi(target,source) if (!source) {source = FastMPCW (); if (CCmi) {pc += source;} else { pc += 2;}} else {if (CCmi) pc += source;}; +#define DoBmis(target,source) if (CCmi) pc += source; +#define DoBge(target,source) if (!source) {source = FastMPCW (); if (CCge) {pc += source;} else { pc += 2;}} else {if (CCge) pc += source;}; +#define DoBges(target,source) if (CCge) pc += source; +#define DoBlt(target,source) if (!source) {source = FastMPCW (); if (CClt) {pc += source;} else { pc += 2;}} else {if (CClt) pc += source;}; +#define DoBlts(target,source) if (CClt) pc += source; +#define DoBgt(target,source) if (!source) {source = FastMPCW (); if (CCgt) {pc += source;} else { pc += 2;}} else {if (CCgt) pc += source;}; +#define DoBgts(target,source) if (CCgt) pc += source; +#define DoBle(target,source) if (!source) {source = FastMPCW (); if (CCle) {pc += source;} else { pc += 2;}} else {if (CCle) pc += source;}; +#define DoBles(target,source) if (CCle) pc += source; + +#define DoChk(target,source) \ +SetN (source < 0); if (source < 0 || source > target) ExceptionGroup2(TRAPCHK); + +#define DoClr(target,source) target = 0; ClrCVSetNZ(target); + +#define DoDbt(target,source) if (!CCt) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbf(target,source) if (!CCf) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbhi(target,source) if (!CChi) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbls(target,source) if (!CCls) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbcc(target,source) if (!CCcc) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbcs(target,source) if (!CCcs) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbne(target,source) if (!CCne) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbeq(target,source) if (!CCeq) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbvc(target,source) if (!CCvc) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbvs(target,source) if (!CCvs) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbpl(target,source) if (!CCpl) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbmi(target,source) if (!CCmi) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbge(target,source) if (!CCge) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDblt(target,source) if (!CClt) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbgt(target,source) if (!CCgt) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDble(target,source) if (!CCle) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; + +#define DoJmp(target,source) SetPC (source); + +#define DoJsr(target,source) reg[15] -= 4; SetMemL (reg[15], GetPC()); SetPC(source); + +#define DoLea(target,source) target = source; + +#define DoMovecc(target,source) target = source; + +#define DoMovep(target,source) target = source; + +#define DoMoveFromSR(target,source) \ + if (!GetS()) ExceptionGroup1(PRIV); \ +target = source; + +#define DoNeg(target,source) \ + SetV (target < 0 && -target < 0);\ + target = -target;\ + SetXC (target != 0);\ +SetNZ(target); + +/* simplified DoSubx */ +#define DoNegx(target,source) \ + SetV (target < 0);\ + if (GetX()) {\ + SetXC(1);\ + target = -target;\ + target -= 1;\ + } else {\ + SetXC (target != 0);\ + target = -target;\ + }\ + SetV (GetV() && (target < 0));\ + ZeroZ(target!=0);\ +SetN(target < 0); + +#define DoNot(target,source) target = ~target; ClrCVSetNZ(target); + +#define DoPea(target,source) reg[15] -= 4; SetMemL (reg[15],source); + +#define DoSt(target,source) target = CCt ? 0xff : 0x00; +#define DoSf(target,source) target = CCf ? 0xff : 0x00; +#define DoShi(target,source) target = CChi ? 0xff : 0x00; +#define DoSls(target,source) target = CCls ? 0xff : 0x00; +#define DoScc(target,source) target = CCcc ? 0xff : 0x00; +#define DoScs(target,source) target = CCcs ? 0xff : 0x00; +#define DoSne(target,source) target = CCne ? 0xff : 0x00; +#define DoSeq(target,source) target = CCeq ? 0xff : 0x00; +#define DoSvc(target,source) target = CCvc ? 0xff : 0x00; +#define DoSvs(target,source) target = CCvs ? 0xff : 0x00; +#define DoSpl(target,source) target = CCpl ? 0xff : 0x00; +#define DoSmi(target,source) target = CCmi ? 0xff : 0x00; +#define DoSge(target,source) target = CCge ? 0xff : 0x00; +#define DoSlt(target,source) target = CClt ? 0xff : 0x00; +#define DoSgt(target,source) target = CCgt ? 0xff : 0x00; +#define DoSle(target,source) target = CCle ? 0xff : 0x00; + +#define DoTst(target,source) ClrCVSetNZ(target); + +#define DoTas(target,source) ClrCVSetNZ(target); target |= 0x80; + +unsigned long Opc140(operin) /* EXG */ +{ + register long var; + var = reg[0]; + reg[0] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc148(operin) /* EXG */ +{ + register long var; + var = reg[8]; + reg[8] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc188(operin) /* EXG */ +{ + register long var; + var = reg[0]; + reg[0] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc340(operin) /* EXG */ +{ + register long var; + var = reg[1]; + reg[1] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc348(operin) /* EXG */ +{ + register long var; + var = reg[9]; + reg[9] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc388(operin) /* EXG */ +{ + register long var; + var = reg[1]; + reg[1] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc540(operin) /* EXG */ +{ + register long var; + var = reg[2]; + reg[2] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc548(operin) /* EXG */ +{ + register long var; + var = reg[10]; + reg[10] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc588 (operin) /* EXG */ +{ + register long var; + var = reg[2]; + reg[2] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc740(operin) /* EXG */ +{ + register long var; + var = reg[3]; + reg[3] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc748(operin) /* EXG */ +{ + register long var; + var = reg[11]; + reg[11] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc788(operin) /* EXG */ +{ + register long var; + var = reg[3]; + reg[3] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc940(operin) /* EXG */ +{ + register long var; + var = reg[4]; + reg[4] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc948(operin) /* EXG */ +{ + register long var; + var = reg[12]; + reg[12] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc988(operin) /* EXG */ +{ + register long var; + var = reg[4]; + reg[4] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcb40(operin) /* EXG */ +{ + register long var; + var = reg[5]; + reg[5] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcb48(operin) /* EXG */ +{ + register long var; + var = reg[13]; + reg[13] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcb88(operin) /* EXG */ +{ + register long var; + var = reg[5]; + reg[5] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcd40(operin) /* EXG */ +{ + register long var; + var = reg[6]; + reg[6] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcd48(operin) /* EXG */ +{ + register long var; + var = reg[14]; + reg[14] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcd88(operin) /* EXG */ +{ + register long var; + var = reg[6]; + reg[6] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcf40(operin) /* EXG */ +{ + register long var; + var = reg[7]; + reg[7] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcf48(operin) /* EXG */ +{ + register long var; + var = reg[15]; + reg[15] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcf88(operin) /* EXG */ +{ + register long var; + var = reg[7]; + reg[7] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Op4840(operin) /* SWAP */ +{ + long source, target; + source = GetRegL (ins7); + target = ((unsigned) source) >> 16; + source <<= 16; + target |= source; + SetRegL (ins7, target); + ClrCVSetNZ (target); + return 4; +} + +unsigned long Op4848(operin) /* BKPT */ +{ + ExceptionGroup1(ILLINSTR); + return 4; +} + +unsigned long Op4880(operin) /* EXT.W */ +{ + char source; + short target; + source = GetRegB (ins7); + target = source; + SetRegW (ins7, target); + ClrCVSetNZ (target); + return 4; +} + +unsigned long Op4890(operin) /* MOVEM.W to (ax) */ +{ + register unsigned long cycles=8+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW(); + pc += 2; + Cain (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemW (address, GetRegW (index)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +/* TODO: if ax is written, use initial ax content (68000, 68010) +* if ax is written, use final ax content (other CPUs) */ +unsigned long Op48a0(operin) /* MOVEM.W to -(ax) */ +{ + register unsigned long cycles=8+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW(); + pc += 2; + address = reg[8 + ins7]; + index = 15; + while (source) { + if (source & 0x1) { + address -= 2; + SetMemW (address, GetRegW (index)); + cycles+=4; + } + index--; + source = ((unsigned short) source) >> 1; + } + SetRegL (8 + ins7, address); + return cycles&0xfffffffc; +} + +unsigned long Op48a8(operin) /* MOVEM.W to d(ax) */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cdai (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemW (address, GetRegW (index)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op48b0(operin) /* MOVEM.W to d(ax,rx) */ +{ + register unsigned long cycles=14+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Caix (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemW (address, GetRegW (index)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op48b8(operin) /* MOVEM.W to w l */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Ceaw (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemW (address, GetRegW (index)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op48c0(operin) /* EXT.L */ +{ + short source; + long target; + source = GetRegW (ins7); + target = source; + SetRegL (ins7, target); + ClrCVSetNZ (target); + return 4; +} + +unsigned long Op48d0(operin) /* MOVEM.L to (ax) */ +{ + register unsigned long cycles=8+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW(); + pc += 2; + Cain (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemL (address, GetRegL (index)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +/* TODO: if ax is written, use initial ax content (68000, 68010) +* if ax is written, use final ax content (other CPUs) */ +unsigned long Op48e0(operin) /* MOVEM.L to -(ax) */ +{ + register unsigned long cycles=8+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + address = reg[8 + ins7]; + index = 15; + while (source) { + if (source & 0x1) { + address -= 4; + SetMemL (address, GetRegL (index)); + cycles+=8; + } + index--; + source = ((unsigned short) source) >> 1; + } + SetRegL (8 + ins7, address); + return cycles&0xfffffffc; +} + +unsigned long Op48e8(operin) /* MOVEM.L to d(ax) */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cdai (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemL (address, GetRegL (index)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op48f0(operin) /* MOVEM.L to d(ax,rx) */ +{ + register unsigned long cycles=14+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Caix (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemL (address, GetRegL (index)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op48f8(operin) /* MOVEM.L to w l */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Ceaw (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemL (address, GetRegL (index)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4c90(operin) /* MOVEM.W from (ax) */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cain (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemW (address)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4c98(operin) /* MOVEM.W from (ax)+ */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cain (address, ins7); /* no increment here! */ + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemW (address)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + SetRegL (8 + ins7, address); + return cycles&0xfffffffc; +} + +unsigned long Op4ca8(operin) /* MOVEM.W from d(ax) */ +{ + register unsigned long cycles=16+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cdai (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemW (address)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4cb0(operin) /* MOVEM.W from d(ax,rx) */ +{ + register unsigned long cycles=18+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Caix (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemW (address)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4cb8(operin) /* MOVEM.W from ea */ +{ + register unsigned long cycles=16+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cear (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemW (address)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4cd0(operin) /* MOVEM.L from (ax) */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cain (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemL (address)); + address += 4; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4cd8(operin) /* MOVEM.L from (ax)+ */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cain (address, ins7); /* no increment here! */ + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemL (address)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + SetRegL (8 + ins7, address); + return cycles&0xfffffffc; +} + +unsigned long Op4ce8(operin) /* MOVEM.L from d(ax) */ +{ + register unsigned long cycles=16+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cdai (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemL (address)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4cf0(operin) /* MOVEM.L from d(ax,rx) */ +{ + register unsigned long cycles=18+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Caix (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemL (address)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4cf8(operin) /* MOVEM.L from ea */ +{ + register unsigned long cycles=16+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cear (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemL (address)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4e40(operin) /* TRAP */ +{ + ExceptionGroup2(TRAP0 + (ins15)); + return 0; +} + +unsigned long Op4e50(operin) /* LINK */ +{ + long source; + source = GetRegL (8 + ins7); + reg[15] -= 4; + SetMemL (reg[15], source); + source = GetRegL (15); + SetRegL (8 + ins7, source); + source += GetMPCW (); + pc += 2; + SetRegL (15, source); + return 0; +} + +unsigned long Op4e58(operin) /* UNLK */ +{ + long source; + source = GetRegL (8 + ins7); + SetRegL (15, source); + source = GetMemL (reg[15]); + reg[15] += 4; + SetRegL (8 + ins7, source); + return 0; +} + +unsigned long Op4e60(operin) /* MOVE ax,usp */ +{ + if (!GetS ()) + ExceptionGroup1(PRIV); + usp = reg[8 + (ins7)]; + return 0; +} + +unsigned long Op4e68(operin) /* MOVE usp,ax */ +{ + if (!GetS ()) + ExceptionGroup1(PRIV); + reg[8 + (ins7)] = usp; + return 0; +} + +unsigned long Op4e70(operin) /* RESET, NOP, STOP, RTE, RTD, RTS, +* TRAPV, RTR */ +{ + switch (ins7) { + case 0: /* RESET */ + if (!GetS ()) + ExceptionGroup1(PRIV); + break; + case 1: /* NOP */ + break; + case 2: /* STOP */ + Stop(); + break; + case 3: /* RTE */ + if (!GetS ()) + ExceptionGroup1(PRIV); + { + unsigned short sr; +#if CPU_TYPE == 68000 + sr = GetMemW (reg[15]); reg[15] += 2; + SetPC (GetMemL (reg[15])); reg[15] += 4; + SetSRW(sr); +#else + switch (GetMemW(reg[15] + 6) >> 12) { + case 0x0: + break; + case 0x8: + /* FIXME: this shouldn't be a format error */ +#ifdef DEBUG + DBG_STOP(); +#endif + default: + ExceptionGroup1(FORMATERR); + break; + } + sr = GetMemW (reg[15]); reg[15] += 2; + SetPC (GetMemL (reg[15])); reg[15] += 4; + SetSRW(sr); + reg[15] += 2; +#endif + } + break; + case 4: /* RTD */ +#if CPU_TYPE == 68000 + ExceptionGroup1(ILLINSTR); +#else + { + short displacement = GetMPCW(); + SetPC(GetMemL(reg[15])); + reg[15] = reg[15] + 4 + displacement; + } +#endif + break; + case 5: /* RTS */ + SetPC (GetMemL (reg[15])); + reg[15] += 4; + break; + case 6: /* TRAPV */ + if (GetV ()) + ExceptionGroup1(TRAPV); + break; + case 7: /* RTR */ + SetSRB ( GetMemW (reg[15])); + reg[15] += 2; + SetPC (GetMemL (reg[15])); + reg[15] += 4; + break; + } + return 0; +} + +unsigned long Op4e78(operin) /* MOVEC */ +{ + switch (ins7) { + case 2: + if (!GetS ()) { + ExceptionGroup1(PRIV); + } else { + short source; + int index; + source = GetMPCW (); + pc += 2; + index = source >> 12; + switch (source & 0xfff) { + case 0x000: + reg[index] = sfc & 7; + break; + case 0x001: + reg[index] = dfc & 7; + break; + case 0x800: + reg[index] = usp; + break; + case 0x801: + reg[index] = vbr; + break; +#if CPU_TYPE == 68020 + case 0x002: + reg[index] = cacr & 0x3; + break; + case 0x802: + reg[index] = caar & 0xfc; + break; + case 0x803: + reg[index] = msp; + break; + case 0x804: + reg[index] = isp; + break; +#endif + default: + /* as specified by Motorola */ + ExceptionGroup1(ILLINSTR); + break; + } + } + break; + case 3: + if (!GetS ()) { + ExceptionGroup1(PRIV); + } else { + short source; + int index; + source = GetMPCW (); + pc += 2; + index = source >> 12; + switch (source & 0xfff) { + case 0x000: + sfc = reg[index] & 7; + break; + case 0x001: + dfc = reg[index] & 7; + break; + case 0x800: + usp = reg[index]; + break; + case 0x801: + vbr = reg[index]; + break; +#if CPU_TYPE == 68020 + case 0x002: + cacr = reg[index] & 0x3; + break; + case 0x802: + caar = reg[index] & 0xfc; + break; + case 0x803: + msp = reg[index]; + break; + case 0x804: + isp = reg[index]; + break; +#endif + default: + /* as specified by Motorola */ + ExceptionGroup1(ILLINSTR); + break; + } + } + break; + default: + ExceptionGroup1(ILLINSTR); + break; + } + return 0; +} +#else + +#define OMoves(a1,a2,a3,a4,a5,a6,a7,a8) \ +extern unsigned long a1(operin); +#define OMoveToSR(a1, a2, a3)\ +extern unsigned long a1(operin); +#endif + +Oper (Op4000, DoNegx, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op4010, DoNegx, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op4018, DoNegx, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op4020, DoNegx, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op4028, DoNegx, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op4030, DoNegx, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op4038, DoNegx, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op4040, DoNegx, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op4050, DoNegx, DN, SNN, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op4058, DoNegx, DN, SNN, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op4060, DoNegx, DN, SNN, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op4068, DoNegx, DN, SNN, 0, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op4070, DoNegx, DN, SNN, 0, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op4078, DoNegx, DN, SNN, 0, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op4080, DoNegx, DN, SNN, 0, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op4090, DoNegx, DN, SNN, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op4098, DoNegx, DN, SNN, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op40a0, DoNegx, DN, SNN, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op40a8, DoNegx, DN, SNN, 0, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op40b0, DoNegx, DN, SNN, 0, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op40b8, DoNegx, DN, SNN, 0, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +#if CPU_TYPE == 68000 // 68000: MOVE from SR not privileged +Oper (Op40c0, DoMovecc, DW, ScW, 0, DW, DR, Cd, ins7, GN, SRW, 8) +Oper (Op40d0, DoMovecc, DW, ScW, 0, DW, DA, Cain, ins7, GN, SMW, 12) +Oper (Op40d8, DoMovecc, DW, ScW, 0, DW, DA, CaipW, ins7, GN, SMW, 12) +Oper (Op40e0, DoMovecc, DW, ScW, 0, DW, DA, CmaiW, ins7, GN, SMW, 16) +Oper (Op40e8, DoMovecc, DW, ScW, 0, DW, DA, Fdai, ins7, GN, SMW, 16) +Oper (Op40f0, DoMovecc, DW, ScW, 0, DW, DA, Faix, ins7, GN, SMW, 20) +Oper (Op40f8, DoMovecc, DW, ScW, 0, DW, DA, Feaw, ins7, GN, SMW, (cycles+19)&0xfffffffc) +#else +Oper (Op40c0, DoMoveFromSR, DW, ScW, 0, DW, DR, Cd, ins7, GN, SRW, 8) +Oper (Op40d0, DoMoveFromSR, DW, ScW, 0, DW, DA, Cain, ins7, GN, SMW, 12) +Oper (Op40d8, DoMoveFromSR, DW, ScW, 0, DW, DA, CaipW, ins7, GN, SMW, 12) +Oper (Op40e0, DoMoveFromSR, DW, ScW, 0, DW, DA, CmaiW, ins7, GN, SMW, 16) +Oper (Op40e8, DoMoveFromSR, DW, ScW, 0, DW, DA, Fdai, ins7, GN, SMW, 16) +Oper (Op40f0, DoMoveFromSR, DW, ScW, 0, DW, DA, Faix, ins7, GN, SMW, 20) +Oper (Op40f8, DoMoveFromSR, DW, ScW, 0, DW, DA, Feaw, ins7, GN, SMW, (cycles+19)&0xfffffffc) +#endif + +Oper (Op4200, DoClr, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op4210, DoClr, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op4218, DoClr, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op4220, DoClr, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op4228, DoClr, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op4230, DoClr, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op4238, DoClr, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op4240, DoClr, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op4250, DoClr, DN, SNN, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op4258, DoClr, DN, SNN, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op4260, DoClr, DN, SNN, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op4268, DoClr, DN, SNN, 0, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op4270, DoClr, DN, SNN, 0, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op4278, DoClr, DN, SNN, 0, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op4280, DoClr, DN, SNN, 0, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op4290, DoClr, DN, SNN, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op4298, DoClr, DN, SNN, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op42a0, DoClr, DN, SNN, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op42a8, DoClr, DN, SNN, 0, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op42b0, DoClr, DN, SNN, 0, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op42b8, DoClr, DN, SNN, 0, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op42c0, DoMovecc, DW, ScB, 0, DW, DR, Cd, ins7, GN, SRW, 8) +Oper (Op42d0, DoMovecc, DW, ScB, 0, DW, DA, Cain, ins7, GN, SMW, 12) +Oper (Op42d8, DoMovecc, DW, ScB, 0, DW, DA, CaipW, ins7, GN, SMW, 12) +Oper (Op42e0, DoMovecc, DW, ScB, 0, DW, DA, CmaiW, ins7, GN, SMW, 16) +Oper (Op42e8, DoMovecc, DW, ScB, 0, DW, DA, Fdai, ins7, GN, SMW, 16) +Oper (Op42f0, DoMovecc, DW, ScB, 0, DW, DA, Faix, ins7, GN, SMW, 20) +Oper (Op42f8, DoMovecc, DW, ScB, 0, DW, DA, Feaw, ins7, GN, SMW, (cycles+19)&0xfffffffc) + +Oper (Op4400, DoNeg, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op4410, DoNeg, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op4418, DoNeg, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op4420, DoNeg, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op4428, DoNeg, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op4430, DoNeg, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op4438, DoNeg, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op4440, DoNeg, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op4450, DoNeg, DN, SNN, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op4458, DoNeg, DN, SNN, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op4460, DoNeg, DN, SNN, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op4468, DoNeg, DN, SNN, 0, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op4470, DoNeg, DN, SNN, 0, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op4478, DoNeg, DN, SNN, 0, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op4480, DoNeg, DN, SNN, 0, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op4490, DoNeg, DN, SNN, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op4498, DoNeg, DN, SNN, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op44a0, DoNeg, DN, SNN, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op44a8, DoNeg, DN, SNN, 0, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op44b0, DoNeg, DN, SNN, 0, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op44b8, DoNeg, DN, SNN, 0, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op44c0, DoMovecc, DW, SdW, ins7, DB, DN, CN, 0, GN, SCB, 12) +Oper (Op44d0, DoMovecc, DW, SainW, ins7, DB, DN, CN, 0, GN, SCB, 16) +Oper (Op44d8, DoMovecc, DW, SaipW, ins7, DB, DN, CN, 0, GN, SCB, 16) +Oper (Op44e0, DoMovecc, DW, SmaiW, ins7, DB, DN, CN, 0, GN, SCB, 20) +Oper (Op44e8, DoMovecc, DW, SdaiW, ins7, DB, DN, CN, 0, GN, SCB, 20) +Oper (Op44f0, DoMovecc, DW, SaixW, ins7, DB, DN, CN, 0, GN, SCB, 24) +Oper (Op44f8, DoMovecc, DW, SearW, ins7, DB, DN, CN, 0, GN, SCB, (cycles+19)&0xfffffffc) + +Oper (Op4600, DoNot, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op4610, DoNot, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op4618, DoNot, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op4620, DoNot, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op4628, DoNot, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op4630, DoNot, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op4638, DoNot, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op4640, DoNot, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op4650, DoNot, DN, SNN, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op4658, DoNot, DN, SNN, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op4660, DoNot, DN, SNN, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op4668, DoNot, DN, SNN, 0, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op4670, DoNot, DN, SNN, 0, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op4678, DoNot, DN, SNN, 0, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op4680, DoNot, DN, SNN, 0, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op4690, DoNot, DN, SNN, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op4698, DoNot, DN, SNN, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op46a0, DoNot, DN, SNN, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op46a8, DoNot, DN, SNN, 0, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op46b0, DoNot, DN, SNN, 0, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op46b8, DoNot, DN, SNN, 0, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +OMoveToSR (Op46c0, SdW, 12) +OMoveToSR (Op46d0, SainW, 16) +OMoveToSR (Op46d8, SaipW, 16) +OMoveToSR (Op46e0, SmaiW, 18) +OMoveToSR (Op46e8, SdaiW, 20) +OMoveToSR (Op46f0, SaixW, 22) +OMoveToSR (Op46f8, SearW, (cycles)+19&0xfffffffc) + +Oper (Op4850, DoPea, DL, SainA, ins7, DN, DN, CN, 0, GN, SN, 12) +Oper (Op4868, DoPea, DL, SdaiA, ins7, DN, DN, CN, 0, GN, SN, 16) +Oper (Op4870, DoPea, DL, SaixA, ins7, DN, DN, CN, 0, GN, SN, 20) +Oper (Op4878, DoPea, DL, SearA, ins7, DN, DN, CN, 0, GN, SN, (cycles+19)&0xfffffffc) + +Oper (Op4a00, DoTst, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SN, 4) +Oper (Op4a10, DoTst, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op4a18, DoTst, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op4a20, DoTst, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op4a28, DoTst, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op4a30, DoTst, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op4a38, DoTst, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op4a40, DoTst, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SN, 4) +Oper (Op4a50, DoTst, DN, SNN, 0, DW, DA, Cain, ins7, GMW, SN, 8) +Oper (Op4a58, DoTst, DN, SNN, 0, DW, DA, CaipW, ins7, GMW, SN, 8) +Oper (Op4a60, DoTst, DN, SNN, 0, DW, DA, CmaiW, ins7, GMW, SN, 12) +Oper (Op4a68, DoTst, DN, SNN, 0, DW, DA, Fdai, ins7, GMW, SN, 12) +Oper (Op4a70, DoTst, DN, SNN, 0, DW, DA, Faix, ins7, GMW, SN, 16) +Oper (Op4a78, DoTst, DN, SNN, 0, DW, DA, Feaw, ins7, GMW, SN, (cycles+11)&0xfffffffc) +Oper (Op4a80, DoTst, DN, SNN, 0, DL, DR, Cd, ins7, GRL, SN, 4) +Oper (Op4a90, DoTst, DN, SNN, 0, DL, DA, Cain, ins7, GML, SN, 12) +Oper (Op4a98, DoTst, DN, SNN, 0, DL, DA, CaipL, ins7, GML, SN, 12) +Oper (Op4aa0, DoTst, DN, SNN, 0, DL, DA, CmaiL, ins7, GML, SN, 16) +Oper (Op4aa8, DoTst, DN, SNN, 0, DL, DA, Fdai, ins7, GML, SN, 16) +Oper (Op4ab0, DoTst, DN, SNN, 0, DL, DA, Faix, ins7, GML, SN, 20) +Oper (Op4ab8, DoTst, DN, SNN, 0, DL, DA, Feaw, ins7, GML, SN, (cycles+15)&0xfffffffc) +Oper (Op4ac0, DoTas, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op4ad0, DoTas, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op4ad8, DoTas, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op4ae0, DoTas, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op4ae8, DoTas, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SMB, 20) +Oper (Op4af0, DoTas, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op4af8, DoTas, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+21)&0xfffffffc) + +Oper (Op4e90, DoJsr, DL, SainA, ins7, DN, DN, CN, 0, GN, SN, 16) +Oper (Op4ea8, DoJsr, DL, SdaiA, ins7, DN, DN, CN, 0, GN, SN, 20) +Oper (Op4eb0, DoJsr, DL, SaixA, ins7, DN, DN, CN, 0, GN, SN, 24) +Oper (Op4eb8, DoJsr, DL, SearA, ins7, DN, DN, CN, 0, GN, SN, (cycles+21)&0xfffffffc) + +Oper (Op4ed0, DoJmp, DL, SainA, ins7, DN, DN, CN, 0, GN, SN, 8) +Oper (Op4ee8, DoJmp, DL, SdaiA, ins7, DN, DN, CN, 0, GN, SN, 12) +Oper (Op4ef0, DoJmp, DL, SaixA, ins7, DN, DN, CN, 0, GN, SN, 16) +Oper (Op4ef8, DoJmp, DL, SearA, ins7, DN, DN, CN, 0, GN, SN, (cycles+13)&0xfffffffc) + +Oper (Op4180, DoChk, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4190, DoChk, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4198, DoChk, DW, SdW, 0, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op41a0, DoChk, DW, SdW, 0, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op41a8, DoChk, DW, SdW, 0, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op41b0, DoChk, DW, SdW, 0, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op41b8, DoChk, DW, SdW, 0, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op4380, DoChk, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4390, DoChk, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4398, DoChk, DW, SdW, 1, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op43a0, DoChk, DW, SdW, 1, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op43a8, DoChk, DW, SdW, 1, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op43b0, DoChk, DW, SdW, 1, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op43b8, DoChk, DW, SdW, 1, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op4580, DoChk, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4590, DoChk, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4598, DoChk, DW, SdW, 2, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op45a0, DoChk, DW, SdW, 2, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op45a8, DoChk, DW, SdW, 2, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op45b0, DoChk, DW, SdW, 2, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op45b8, DoChk, DW, SdW, 2, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op4780, DoChk, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4790, DoChk, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4798, DoChk, DW, SdW, 3, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op47a0, DoChk, DW, SdW, 3, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op47a8, DoChk, DW, SdW, 3, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op47b0, DoChk, DW, SdW, 3, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op47b8, DoChk, DW, SdW, 3, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op4980, DoChk, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4990, DoChk, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4998, DoChk, DW, SdW, 4, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op49a0, DoChk, DW, SdW, 4, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op49a8, DoChk, DW, SdW, 4, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op49b0, DoChk, DW, SdW, 4, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op49b8, DoChk, DW, SdW, 4, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op4b80, DoChk, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4b90, DoChk, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4b98, DoChk, DW, SdW, 5, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op4ba0, DoChk, DW, SdW, 5, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op4ba8, DoChk, DW, SdW, 5, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op4bb0, DoChk, DW, SdW, 5, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op4bb8, DoChk, DW, SdW, 5, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op4d80, DoChk, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4d90, DoChk, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4d98, DoChk, DW, SdW, 6, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op4da0, DoChk, DW, SdW, 6, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op4da8, DoChk, DW, SdW, 6, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op4db0, DoChk, DW, SdW, 6, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op4db8, DoChk, DW, SdW, 6, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op4f80, DoChk, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4f90, DoChk, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4f98, DoChk, DW, SdW, 7, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op4fa0, DoChk, DW, SdW, 7, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op4fa8, DoChk, DW, SdW, 7, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op4fb0, DoChk, DW, SdW, 7, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op4fb8, DoChk, DW, SdW, 7, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op41d0, DoLea, DL, SainA, ins7, DL, DR, Ca, 0, GN, SRL, 4) +Oper (Op41e8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 0, GN, SRL, 8) +Oper (Op41f0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 0, GN, SRL, 12) +Oper (Op41f8, DoLea, DL, SearA, ins7, DL, DR, Ca, 0, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op43d0, DoLea, DL, SainA, ins7, DL, DR, Ca, 1, GN, SRL, 4) +Oper (Op43e8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 1, GN, SRL, 8) +Oper (Op43f0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 1, GN, SRL, 12) +Oper (Op43f8, DoLea, DL, SearA, ins7, DL, DR, Ca, 1, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op45d0, DoLea, DL, SainA, ins7, DL, DR, Ca, 2, GN, SRL, 4) +Oper (Op45e8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 2, GN, SRL, 8) +Oper (Op45f0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 2, GN, SRL, 12) +Oper (Op45f8, DoLea, DL, SearA, ins7, DL, DR, Ca, 2, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op47d0, DoLea, DL, SainA, ins7, DL, DR, Ca, 3, GN, SRL, 4) +Oper (Op47e8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 3, GN, SRL, 8) +Oper (Op47f0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 3, GN, SRL, 12) +Oper (Op47f8, DoLea, DL, SearA, ins7, DL, DR, Ca, 3, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op49d0, DoLea, DL, SainA, ins7, DL, DR, Ca, 4, GN, SRL, 4) +Oper (Op49e8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 4, GN, SRL, 8) +Oper (Op49f0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 4, GN, SRL, 12) +Oper (Op49f8, DoLea, DL, SearA, ins7, DL, DR, Ca, 4, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op4bd0, DoLea, DL, SainA, ins7, DL, DR, Ca, 5, GN, SRL, 4) +Oper (Op4be8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 5, GN, SRL, 8) +Oper (Op4bf0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 5, GN, SRL, 12) +Oper (Op4bf8, DoLea, DL, SearA, ins7, DL, DR, Ca, 5, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op4dd0, DoLea, DL, SainA, ins7, DL, DR, Ca, 6, GN, SRL, 4) +Oper (Op4de8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 6, GN, SRL, 8) +Oper (Op4df0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 6, GN, SRL, 12) +Oper (Op4df8, DoLea, DL, SearA, ins7, DL, DR, Ca, 6, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op4fd0, DoLea, DL, SainA, ins7, DL, DR, Ca, 7, GN, SRL, 4) +Oper (Op4fe8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 7, GN, SRL, 8) +Oper (Op4ff0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 7, GN, SRL, 12) +Oper (Op4ff8, DoLea, DL, SearA, ins7, DL, DR, Ca, 7, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op50c0, DoSt, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op50c8, DoDbt, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op50d0, DoSt, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op50d8, DoSt, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op50e0, DoSt, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op50e8, DoSt, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op50f0, DoSt, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op50f8, DoSt, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op51c0, DoSf, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op51c8, DoDbf, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op51d0, DoSf, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op51d8, DoSf, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op51e0, DoSf, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op51e8, DoSf, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op51f0, DoSf, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op51f8, DoSf, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op52c0, DoShi, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op52c8, DoDbhi, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op52d0, DoShi, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op52d8, DoShi, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op52e0, DoShi, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op52e8, DoShi, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op52f0, DoShi, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op52f8, DoShi, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op53c0, DoSls, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op53c8, DoDbls, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op53d0, DoSls, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op53d8, DoSls, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op53e0, DoSls, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op53e8, DoSls, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op53f0, DoSls, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op53f8, DoSls, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op54c0, DoScc, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op54c8, DoDbcc, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op54d0, DoScc, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op54d8, DoScc, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op54e0, DoScc, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op54e8, DoScc, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op54f0, DoScc, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op54f8, DoScc, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op55c0, DoScs, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op55c8, DoDbcs, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op55d0, DoScs, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op55d8, DoScs, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op55e0, DoScs, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op55e8, DoScs, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op55f0, DoScs, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op55f8, DoScs, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op56c0, DoSne, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op56c8, DoDbne, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op56d0, DoSne, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op56d8, DoSne, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op56e0, DoSne, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op56e8, DoSne, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op56f0, DoSne, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op56f8, DoSne, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op57c0, DoSeq, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op57c8, DoDbeq, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op57d0, DoSeq, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op57d8, DoSeq, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op57e0, DoSeq, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op57e8, DoSeq, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op57f0, DoSeq, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op57f8, DoSeq, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op58c0, DoSvc, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op58c8, DoDbvc, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op58d0, DoSvc, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op58d8, DoSvc, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op58e0, DoSvc, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op58e8, DoSvc, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op58f0, DoSvc, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op58f8, DoSvc, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op59c0, DoSvs, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op59c8, DoDbvs, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op59d0, DoSvs, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op59d8, DoSvs, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op59e0, DoSvs, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op59e8, DoSvs, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op59f0, DoSvs, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op59f8, DoSvs, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op5ac0, DoSpl, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op5ac8, DoDbpl, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op5ad0, DoSpl, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op5ad8, DoSpl, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op5ae0, DoSpl, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op5ae8, DoSpl, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op5af0, DoSpl, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op5af8, DoSpl, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op5bc0, DoSmi, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op5bc8, DoDbmi, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op5bd0, DoSmi, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op5bd8, DoSmi, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op5be0, DoSmi, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op5be8, DoSmi, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op5bf0, DoSmi, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op5bf8, DoSmi, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op5cc0, DoSge, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op5cc8, DoDbge, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op5cd0, DoSge, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op5cd8, DoSge, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op5ce0, DoSge, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op5ce8, DoSge, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op5cf0, DoSge, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op5cf8, DoSge, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op5dc0, DoSlt, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op5dc8, DoDblt, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op5dd0, DoSlt, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op5dd8, DoSlt, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op5de0, DoSlt, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op5de8, DoSlt, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op5df0, DoSlt, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op5df8, DoSlt, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op5ec0, DoSgt, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op5ec8, DoDbgt, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op5ed0, DoSgt, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op5ed8, DoSgt, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op5ee0, DoSgt, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op5ee8, DoSgt, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op5ef0, DoSgt, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op5ef8, DoSgt, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op5fc0, DoSle, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op5fc8, DoDble, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op5fd0, DoSle, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op5fd8, DoSle, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op5fe0, DoSle, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op5fe8, DoSle, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op5ff0, DoSle, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op5ff8, DoSle, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op6000, DoBra, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6008, DoBras, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6100, DoBsr, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 20) +Oper (Op6108, DoBsrs, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6200, DoBhi, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6208, DoBhis, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6300, DoBls, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6308, DoBlss, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6400, DoBcc, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6408, DoBccs, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6500, DoBcs, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6508, DoBcss, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6600, DoBne, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6608, DoBnes, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6700, DoBeq, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6708, DoBeqs, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6800, DoBvc, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6808, DoBvcs, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6900, DoBvs, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6908, DoBvss, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6a00, DoBpl, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6a08, DoBpls, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6b00, DoBmi, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6b08, DoBmis, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6c00, DoBge, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6c08, DoBges, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6d00, DoBlt, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6d08, DoBlts, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6e00, DoBgt, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6e08, DoBgts, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6f00, DoBle, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6f08, DoBles, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) + +Oper (Op0100, DoBtst32, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0108, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 0, GN, SRW, 16) +Oper (Op0110, DoBtst8, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0118, DoBtst8, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0120, DoBtst8, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0128, DoBtst8, DB, SdB, 0, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0130, DoBtst8, DB, SdB, 0, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0138, DoBtst8, DB, SdB, 0, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0140, DoBchg32, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0148, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 0, GN, SRL, 24) +Oper (Op0150, DoBchg8, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0158, DoBchg8, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0160, DoBchg8, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0168, DoBchg8, DB, SdB, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0170, DoBchg8, DB, SdB, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0178, DoBchg8, DB, SdB, 0, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0180, DoBclr32, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0188, DoMovep, DW, SdW, 0, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0190, DoBclr8, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0198, DoBclr8, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op01a0, DoBclr8, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op01a8, DoBclr8, DB, SdB, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op01b0, DoBclr8, DB, SdB, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op01b8, DoBclr8, DB, SdB, 0, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op01c0, DoBset32, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op01c8, DoMovep, DL, SdL, 0, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op01d0, DoBset8, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op01d8, DoBset8, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op01e0, DoBset8, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op01e8, DoBset8, DB, SdB, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op01f0, DoBset8, DB, SdB, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op01f8, DoBset8, DB, SdB, 0, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +Oper (Op0300, DoBtst32, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0308, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 1, GN, SRW, 16) +Oper (Op0310, DoBtst8, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0318, DoBtst8, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0320, DoBtst8, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0328, DoBtst8, DB, SdB, 1, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0330, DoBtst8, DB, SdB, 1, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0338, DoBtst8, DB, SdB, 1, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0340, DoBchg32, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0348, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 1, GN, SRL, 24) +Oper (Op0350, DoBchg8, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0358, DoBchg8, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0360, DoBchg8, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0368, DoBchg8, DB, SdB, 1, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0370, DoBchg8, DB, SdB, 1, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0378, DoBchg8, DB, SdB, 1, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0380, DoBclr32, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0388, DoMovep, DW, SdW, 1, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0390, DoBclr8, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0398, DoBclr8, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op03a0, DoBclr8, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op03a8, DoBclr8, DB, SdB, 1, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op03b0, DoBclr8, DB, SdB, 1, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op03b8, DoBclr8, DB, SdB, 1, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op03c0, DoBset32, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op03c8, DoMovep, DL, SdL, 1, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op03d0, DoBset8, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op03d8, DoBset8, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op03e0, DoBset8, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op03e8, DoBset8, DB, SdB, 1, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op03f0, DoBset8, DB, SdB, 1, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op03f8, DoBset8, DB, SdB, 1, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +Oper (Op0500, DoBtst32, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0508, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 2, GN, SRW, 16) +Oper (Op0510, DoBtst8, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0518, DoBtst8, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0520, DoBtst8, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0528, DoBtst8, DB, SdB, 2, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0530, DoBtst8, DB, SdB, 2, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0538, DoBtst8, DB, SdB, 2, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0540, DoBchg32, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0548, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 2, GN, SRL, 24) +Oper (Op0550, DoBchg8, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0558, DoBchg8, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0560, DoBchg8, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0568, DoBchg8, DB, SdB, 2, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0570, DoBchg8, DB, SdB, 2, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0578, DoBchg8, DB, SdB, 2, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0580, DoBclr32, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0588, DoMovep, DW, SdW, 2, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0590, DoBclr8, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0598, DoBclr8, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op05a0, DoBclr8, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op05a8, DoBclr8, DB, SdB, 2, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op05b0, DoBclr8, DB, SdB, 2, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op05b8, DoBclr8, DB, SdB, 2, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op05c0, DoBset32, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op05c8, DoMovep, DL, SdL, 2, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op05d0, DoBset8, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op05d8, DoBset8, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op05e0, DoBset8, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op05e8, DoBset8, DB, SdB, 2, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op05f0, DoBset8, DB, SdB, 2, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op05f8, DoBset8, DB, SdB, 2, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +Oper (Op0700, DoBtst32, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0708, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 3, GN, SRW, 16) +Oper (Op0710, DoBtst8, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0718, DoBtst8, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0720, DoBtst8, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0728, DoBtst8, DB, SdB, 3, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0730, DoBtst8, DB, SdB, 3, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0738, DoBtst8, DB, SdB, 3, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0740, DoBchg32, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0748, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 3, GN, SRL, 24) +Oper (Op0750, DoBchg8, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0758, DoBchg8, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0760, DoBchg8, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0768, DoBchg8, DB, SdB, 3, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0770, DoBchg8, DB, SdB, 3, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0778, DoBchg8, DB, SdB, 3, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0780, DoBclr32, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0788, DoMovep, DW, SdW, 3, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0790, DoBclr8, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0798, DoBclr8, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op07a0, DoBclr8, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op07a8, DoBclr8, DB, SdB, 3, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op07b0, DoBclr8, DB, SdB, 3, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op07b8, DoBclr8, DB, SdB, 3, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op07c0, DoBset32, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op07c8, DoMovep, DL, SdL, 3, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op07d0, DoBset8, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op07d8, DoBset8, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op07e0, DoBset8, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op07e8, DoBset8, DB, SdB, 3, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op07f0, DoBset8, DB, SdB, 3, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op07f8, DoBset8, DB, SdB, 3, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +Oper (Op0900, DoBtst32, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0908, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 4, GN, SRW, 16) +Oper (Op0910, DoBtst8, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0918, DoBtst8, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0920, DoBtst8, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0928, DoBtst8, DB, SdB, 4, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0930, DoBtst8, DB, SdB, 4, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0938, DoBtst8, DB, SdB, 4, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0940, DoBchg32, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0948, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 4, GN, SRL, 24) +Oper (Op0950, DoBchg8, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0958, DoBchg8, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0960, DoBchg8, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0968, DoBchg8, DB, SdB, 4, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0970, DoBchg8, DB, SdB, 4, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0978, DoBchg8, DB, SdB, 4, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0980, DoBclr32, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0988, DoMovep, DW, SdW, 4, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0990, DoBclr8, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0998, DoBclr8, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op09a0, DoBclr8, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op09a8, DoBclr8, DB, SdB, 4, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op09b0, DoBclr8, DB, SdB, 4, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op09b8, DoBclr8, DB, SdB, 4, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op09c0, DoBset32, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op09c8, DoMovep, DL, SdL, 4, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op09d0, DoBset8, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op09d8, DoBset8, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op09e0, DoBset8, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op09e8, DoBset8, DB, SdB, 4, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op09f0, DoBset8, DB, SdB, 4, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op09f8, DoBset8, DB, SdB, 4, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +Oper (Op0b00, DoBtst32, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0b08, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 5, GN, SRW, 16) +Oper (Op0b10, DoBtst8, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0b18, DoBtst8, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0b20, DoBtst8, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0b28, DoBtst8, DB, SdB, 5, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0b30, DoBtst8, DB, SdB, 5, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0b38, DoBtst8, DB, SdB, 5, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0b40, DoBchg32, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0b48, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 5, GN, SRL, 24) +Oper (Op0b50, DoBchg8, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0b58, DoBchg8, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0b60, DoBchg8, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0b68, DoBchg8, DB, SdB, 5, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0b70, DoBchg8, DB, SdB, 5, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0b78, DoBchg8, DB, SdB, 5, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0b80, DoBclr32, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0b88, DoMovep, DW, SdW, 5, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0b90, DoBclr8, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0b98, DoBclr8, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0ba0, DoBclr8, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0ba8, DoBclr8, DB, SdB, 5, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0bb0, DoBclr8, DB, SdB, 5, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0bb8, DoBclr8, DB, SdB, 5, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0bc0, DoBset32, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0bc8, DoMovep, DL, SdL, 5, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op0bd0, DoBset8, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0bd8, DoBset8, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0be0, DoBset8, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0be8, DoBset8, DB, SdB, 5, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0bf0, DoBset8, DB, SdB, 5, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0bf8, DoBset8, DB, SdB, 5, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +Oper (Op0d00, DoBtst32, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0d08, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 6, GN, SRW, 16) +Oper (Op0d10, DoBtst8, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0d18, DoBtst8, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0d20, DoBtst8, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0d28, DoBtst8, DB, SdB, 6, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0d30, DoBtst8, DB, SdB, 6, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0d38, DoBtst8, DB, SdB, 6, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0d40, DoBchg32, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0d48, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 6, GN, SRL, 24) +Oper (Op0d50, DoBchg8, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0d58, DoBchg8, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0d60, DoBchg8, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0d68, DoBchg8, DB, SdB, 6, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0d70, DoBchg8, DB, SdB, 6, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0d78, DoBchg8, DB, SdB, 6, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0d80, DoBclr32, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0d88, DoMovep, DW, SdW, 6, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0d90, DoBclr8, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0d98, DoBclr8, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0da0, DoBclr8, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0da8, DoBclr8, DB, SdB, 6, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0db0, DoBclr8, DB, SdB, 6, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0db8, DoBclr8, DB, SdB, 6, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0dc0, DoBset32, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0dc8, DoMovep, DL, SdL, 6, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op0dd0, DoBset8, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0dd8, DoBset8, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0de0, DoBset8, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0de8, DoBset8, DB, SdB, 6, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0df0, DoBset8, DB, SdB, 6, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0df8, DoBset8, DB, SdB, 6, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +OMoves (Op0e10, DB, Cain, GRB, SRB, GMB, SMB, 12) +OMoves (Op0e18, DB, CaipB, GRB, SRB, GMB, SMB, 12) +OMoves (Op0e20, DB, CmaiB, GRB, SRB, GMB, SMB, 16) +OMoves (Op0e28, DB, Cdai, GRB, SRB, GMB, SMB, 16) +OMoves (Op0e30, DB, Caix, GRB, SRB, GMB, SMB, 20) +OMoves (Op0e38, DB, Ceaw, GRB, SRB, GMB, SMB, (cycles+19)&0xfffffffc) +OMoves (Op0e50, DW, Cain, GRW, SRW, GMW, SMW, 12) +OMoves (Op0e58, DW, CaipB, GRW, SRW, GMW, SMW, 12) +OMoves (Op0e60, DW, CmaiB, GRW, SRW, GMW, SMW, 16) +OMoves (Op0e68, DW, Cdai, GRW, SRW, GMW, SMW, 16) +OMoves (Op0e70, DW, Caix, GRW, SRW, GMW, SMW, 20) +OMoves (Op0e78, DW, Ceaw, GRW, SRW, GMW, SMW, (cycles+19)&0xfffffffc) +OMoves (Op0e90, DL, Cain, GRL, SRL, GML, SML, 20) +OMoves (Op0e98, DL, CaipB, GRL, SRL, GML, SML, 20) +OMoves (Op0ea0, DL, CmaiB, GRL, SRL, GML, SML, 24) +OMoves (Op0ea8, DL, Cdai, GRL, SRL, GML, SML, 24) +OMoves (Op0eb0, DL, Caix, GRL, SRL, GML, SML, 28) +OMoves (Op0eb8, DL, Ceaw, GRL, SRL, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op0f00, DoBtst32, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0f08, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 7, GN, SRW, 16) +Oper (Op0f10, DoBtst8, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0f18, DoBtst8, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0f20, DoBtst8, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0f28, DoBtst8, DB, SdB, 7, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0f30, DoBtst8, DB, SdB, 7, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0f38, DoBtst8, DB, SdB, 7, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0f40, DoBchg32, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0f48, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 7, GN, SRL, 24) +Oper (Op0f50, DoBchg8, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0f58, DoBchg8, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0f60, DoBchg8, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0f68, DoBchg8, DB, SdB, 7, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0f70, DoBchg8, DB, SdB, 7, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0f78, DoBchg8, DB, SdB, 7, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0f80, DoBclr32, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0f88, DoMovep, DW, SdW, 7, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0f90, DoBclr8, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0f98, DoBclr8, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0fa0, DoBclr8, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0fa8, DoBclr8, DB, SdB, 7, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0fb0, DoBclr8, DB, SdB, 7, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0fb8, DoBclr8, DB, SdB, 7, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0fc0, DoBset32, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0fc8, DoMovep, DL, SdL, 7, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op0fd0, DoBset8, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0fd8, DoBset8, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0fe0, DoBset8, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0fe8, DoBset8, DB, SdB, 7, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0ff0, DoBset8, DB, SdB, 7, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0ff8, DoBset8, DB, SdB, 7, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +Oper (Op0800, DoBtst32, DB, SimmB, 0, DL, DR, Cd, ins7, GRL, SN, 12) +Oper (Op0810, DoBtst8, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SN, 12) +Oper (Op0818, DoBtst8, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SN, 12) +Oper (Op0820, DoBtst8, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SN, 16) +Oper (Op0828, DoBtst8, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SN, 16) +Oper (Op0830, DoBtst8, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SN, 20) +Oper (Op0838, DoBtst8, DB, SimmB, 0, DB, DA, Cear, ins7, GMB, SN, (cycles+15)&0xfffffffc) +Oper (Op0840, DoBchg32, DL, SimmB, 0, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0850, DoBchg8, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op0858, DoBchg8, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op0860, DoBchg8, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op0868, DoBchg8, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op0870, DoBchg8, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +Oper (Op0878, DoBchg8, DB, SimmB, 0, DB, DA, Cear, ins7, GMB, SMB, (cycles+23)&0xfffffffc) +Oper (Op0880, DoBclr32, DL, SimmB, 0, DL, DR, Cd, ins7, GRL, SRL, 16) +Oper (Op0890, DoBclr8, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op0898, DoBclr8, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op08a0, DoBclr8, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op08a8, DoBclr8, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op08b0, DoBclr8, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +Oper (Op08b8, DoBclr8, DB, SimmB, 0, DB, DA, Cear, ins7, GMB, SMB, (cycles+23)&0xfffffffc) +Oper (Op08c0, DoBset32, DL, SimmB, 0, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op08d0, DoBset8, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op08d8, DoBset8, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op08e0, DoBset8, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op08e8, DoBset8, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op08f0, DoBset8, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +Oper (Op08f8, DoBset8, DB, SimmB, 0, DB, DA, Cear, ins7, GMB, SMB, (cycles+23)&0xfffffffc) diff --git a/MCUME_esp32/espcastaway/main/68korig/op68kmove.cpp b/MCUME_esp32/espcastaway/main/68korig/op68kmove.cpp new file mode 100755 index 0000000..c215a63 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/op68kmove.cpp @@ -0,0 +1,1335 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - 68k move instructions +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 0.02.00 JH FAST1.0.1 code import: KR -> ANSI, restructuring +*/ +#ifndef PROTOH +static char sccsid[] = "$Id: op68kmove.c,v 1.1.1.1 2002/05/25 23:04:30 jhoenig Exp $"; +#include "68000.h" +#include "op68k.h" + +#define DoMoveB(target,source) target = source; ClrCVSetNZ(target); +#define DoMoveW(target,source) target = source; ClrCVSetNZ(target); +#define DoMoveL(target,source) target = source; ClrCVSetNZ(target); + +#define DoMovea(target,source) target = source; + +#endif + +Oper (Op1000, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 0, GN, SRB, 4) +Oper (Op1010, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 0, GN, SRB, 8) +Oper (Op1018, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 0, GN, SRB, 8) +Oper (Op1020, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 0, GN, SRB, 12) +Oper (Op1028, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 0, GN, SRB, 12) +Oper (Op1030, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 0, GN, SRB, 16) +Oper (Op1038, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 0, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1080, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 0, GN, SMB, 8) +Oper (Op1090, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 0, GN, SMB, 12) +Oper (Op1098, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 0, GN, SMB, 12) +Oper (Op10a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 0, GN, SMB, 16) +Oper (Op10a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 0, GN, SMB, 16) +Oper (Op10b0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 0, GN, SMB, 20) +Oper (Op10b8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 0, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op10c0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB, 0, GN, SMB, 8) +Oper (Op10d0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB, 0, GN, SMB, 12) +Oper (Op10d8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB, 0, GN, SMB, 12) +Oper (Op10e0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB, 0, GN, SMB, 16) +Oper (Op10e8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB, 0, GN, SMB, 16) +Oper (Op10f0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB, 0, GN, SMB, 20) +Oper (Op10f8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB, 0, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1100, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB, 0, GN, SMB, 12) +Oper (Op1110, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB, 0, GN, SMB, 16) +Oper (Op1118, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB, 0, GN, SMB, 16) +Oper (Op1120, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB, 0, GN, SMB, 16) +Oper (Op1128, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB, 0, GN, SMB, 20) +Oper (Op1130, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB, 0, GN, SMB, 20) +Oper (Op1138, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB, 0, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1140, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 0, GN, SMB, 12) +Oper (Op1150, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 0, GN, SMB, 16) +Oper (Op1158, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 0, GN, SMB, 16) +Oper (Op1160, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 0, GN, SMB, 20) +Oper (Op1168, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 0, GN, SMB, 20) +Oper (Op1170, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 0, GN, SMB, 24) +Oper (Op1178, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 0, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1180, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 0, GN, SMB, 16) +Oper (Op1190, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 0, GN, SMB, 20) +Oper (Op1198, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 0, GN, SMB, 20) +Oper (Op11a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 0, GN, SMB, 20) +Oper (Op11a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 0, GN, SMB, 24) +Oper (Op11b0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 0, GN, SMB, 24) +Oper (Op11b8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 0, GN, SMB, (cycles+21)&0xfffffffc) +Oper (Op11c0, DoMoveB, DB, SdB, ins7, DB, DA, Feaw, 0, GN, SMB, 12) +Oper (Op11d0, DoMoveB, DB, SainB, ins7, DB, DA, Feaw, 0, GN, SMB, 16) +Oper (Op11d8, DoMoveB, DB, SaipB, ins7, DB, DA, Feaw, 0, GN, SMB, 16) +Oper (Op11e0, DoMoveB, DB, SmaiB, ins7, DB, DA, Feaw, 0, GN, SMB, 20) +Oper (Op11e8, DoMoveB, DB, SdaiB, ins7, DB, DA, Ceaw, 0, GN, SMB, 20) +Oper (Op11f0, DoMoveB, DB, SaixB, ins7, DB, DA, Ceaw, 0, GN, SMB, 24) +Oper (Op11f8, DoMoveB, DB, SearB, ins7, DB, DA, Ceaw, 0, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op1200, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 1, GN, SRB, 4) +Oper (Op1210, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 1, GN, SRB, 8) +Oper (Op1218, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 1, GN, SRB, 8) +Oper (Op1220, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 1, GN, SRB, 12) +Oper (Op1228, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 1, GN, SRB, 12) +Oper (Op1230, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 1, GN, SRB, 16) +Oper (Op1238, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 1, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1280, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 1, GN, SMB, 8) +Oper (Op1290, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 1, GN, SMB, 12) +Oper (Op1298, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 1, GN, SMB, 12) +Oper (Op12a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 1, GN, SMB, 16) +Oper (Op12a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 1, GN, SMB, 16) +Oper (Op12b0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 1, GN, SMB, 20) +Oper (Op12b8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 1, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op12c0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB, 1, GN, SMB, 8) +Oper (Op12d0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB, 1, GN, SMB, 12) +Oper (Op12d8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB, 1, GN, SMB, 12) +Oper (Op12e0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB, 1, GN, SMB, 16) +Oper (Op12e8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB, 1, GN, SMB, 16) +Oper (Op12f0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB, 1, GN, SMB, 20) +Oper (Op12f8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB, 1, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1300, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB, 1, GN, SMB, 12) +Oper (Op1310, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB, 1, GN, SMB, 16) +Oper (Op1318, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB, 1, GN, SMB, 16) +Oper (Op1320, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB, 1, GN, SMB, 16) +Oper (Op1328, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB, 1, GN, SMB, 20) +Oper (Op1330, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB, 1, GN, SMB, 20) +Oper (Op1338, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB, 1, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1340, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 1, GN, SMB, 12) +Oper (Op1350, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 1, GN, SMB, 16) +Oper (Op1358, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 1, GN, SMB, 16) +Oper (Op1360, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 1, GN, SMB, 20) +Oper (Op1368, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 1, GN, SMB, 20) +Oper (Op1370, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 1, GN, SMB, 24) +Oper (Op1378, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 1, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1380, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 1, GN, SMB, 16) +Oper (Op1390, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 1, GN, SMB, 20) +Oper (Op1398, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 1, GN, SMB, 20) +Oper (Op13a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 1, GN, SMB, 20) +Oper (Op13a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 1, GN, SMB, 24) +Oper (Op13b0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 1, GN, SMB, 24) +Oper (Op13b8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 1, GN, SMB, (cycles+21)&0xfffffffc) +Oper (Op13c0, DoMoveB, DB, SdB, ins7, DB, DA, Feaw, 1, GN, SMB, 16) +Oper (Op13d0, DoMoveB, DB, SainB, ins7, DB, DA, Feaw, 1, GN, SMB, 20) +Oper (Op13d8, DoMoveB, DB, SaipB, ins7, DB, DA, Feaw, 1, GN, SMB, 20) +Oper (Op13e0, DoMoveB, DB, SmaiB, ins7, DB, DA, Feaw, 1, GN, SMB, 24) +Oper (Op13e8, DoMoveB, DB, SdaiB, ins7, DB, DA, Ceaw, 1, GN, SMB, 24) +Oper (Op13f0, DoMoveB, DB, SaixB, ins7, DB, DA, Ceaw, 1, GN, SMB, 28) +Oper (Op13f8, DoMoveB, DB, SearB, ins7, DB, DA, Ceaw, 1, GN, SMB, (cycles+23)&0xfffffffc) + +Oper (Op1400, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 2, GN, SRB, 4) +Oper (Op1410, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 2, GN, SRB, 8) +Oper (Op1418, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 2, GN, SRB, 8) +Oper (Op1420, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 2, GN, SRB, 12) +Oper (Op1428, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 2, GN, SRB, 12) +Oper (Op1430, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 2, GN, SRB, 16) +Oper (Op1438, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 2, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1480, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 2, GN, SMB, 8) +Oper (Op1490, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 2, GN, SMB, 12) +Oper (Op1498, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 2, GN, SMB, 12) +Oper (Op14a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 2, GN, SMB, 16) +Oper (Op14a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 2, GN, SMB, 16) +Oper (Op14b0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 2, GN, SMB, 20) +Oper (Op14b8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 2, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op14c0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB, 2, GN, SMB, 8) +Oper (Op14d0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB, 2, GN, SMB, 12) +Oper (Op14d8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB, 2, GN, SMB, 12) +Oper (Op14e0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB, 2, GN, SMB, 16) +Oper (Op14e8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB, 2, GN, SMB, 16) +Oper (Op14f0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB, 2, GN, SMB, 20) +Oper (Op14f8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB, 2, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1500, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB, 2, GN, SMB, 12) +Oper (Op1510, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB, 2, GN, SMB, 16) +Oper (Op1518, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB, 2, GN, SMB, 16) +Oper (Op1520, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB, 2, GN, SMB, 16) +Oper (Op1528, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB, 2, GN, SMB, 20) +Oper (Op1530, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB, 2, GN, SMB, 20) +Oper (Op1538, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB, 2, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1540, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 2, GN, SMB, 12) +Oper (Op1550, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 2, GN, SMB, 16) +Oper (Op1558, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 2, GN, SMB, 16) +Oper (Op1560, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 2, GN, SMB, 20) +Oper (Op1568, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 2, GN, SMB, 20) +Oper (Op1570, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 2, GN, SMB, 24) +Oper (Op1578, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 2, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1580, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 2, GN, SMB, 16) +Oper (Op1590, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 2, GN, SMB, 20) +Oper (Op1598, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 2, GN, SMB, 20) +Oper (Op15a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 2, GN, SMB, 20) +Oper (Op15a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 2, GN, SMB, 24) +Oper (Op15b0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 2, GN, SMB, 24) +Oper (Op15b8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 2, GN, SMB, (cycles+21)&0xfffffffc) + +Oper (Op1600, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 3, GN, SRB, 4) +Oper (Op1610, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 3, GN, SRB, 8) +Oper (Op1618, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 3, GN, SRB, 8) +Oper (Op1620, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 3, GN, SRB, 12) +Oper (Op1628, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 3, GN, SRB, 12) +Oper (Op1630, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 3, GN, SRB, 16) +Oper (Op1638, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 3, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1680, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 3, GN, SMB, 8) +Oper (Op1690, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 3, GN, SMB, 12) +Oper (Op1698, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 3, GN, SMB, 12) +Oper (Op16a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 3, GN, SMB, 16) +Oper (Op16a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 3, GN, SMB, 16) +Oper (Op16b0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 3, GN, SMB, 20) +Oper (Op16b8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 3, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op16c0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB, 3, GN, SMB, 8) +Oper (Op16d0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB, 3, GN, SMB, 12) +Oper (Op16d8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB, 3, GN, SMB, 12) +Oper (Op16e0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB, 3, GN, SMB, 16) +Oper (Op16e8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB, 3, GN, SMB, 16) +Oper (Op16f0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB, 3, GN, SMB, 20) +Oper (Op16f8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB, 3, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1700, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB, 3, GN, SMB, 12) +Oper (Op1710, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB, 3, GN, SMB, 16) +Oper (Op1718, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB, 3, GN, SMB, 16) +Oper (Op1720, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB, 3, GN, SMB, 16) +Oper (Op1728, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB, 3, GN, SMB, 20) +Oper (Op1730, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB, 3, GN, SMB, 20) +Oper (Op1738, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB, 3, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1740, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 3, GN, SMB, 12) +Oper (Op1750, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 3, GN, SMB, 16) +Oper (Op1758, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 3, GN, SMB, 16) +Oper (Op1760, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 3, GN, SMB, 20) +Oper (Op1768, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 3, GN, SMB, 20) +Oper (Op1770, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 3, GN, SMB, 24) +Oper (Op1778, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 3, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1780, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 3, GN, SMB, 16) +Oper (Op1790, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 3, GN, SMB, 20) +Oper (Op1798, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 3, GN, SMB, 20) +Oper (Op17a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 3, GN, SMB, 20) +Oper (Op17a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 3, GN, SMB, 24) +Oper (Op17b0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 3, GN, SMB, 24) +Oper (Op17b8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 3, GN, SMB, (cycles+21)&0xfffffffc) + +Oper (Op1800, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 4, GN, SRB, 4) +Oper (Op1810, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 4, GN, SRB, 8) +Oper (Op1818, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 4, GN, SRB, 8) +Oper (Op1820, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 4, GN, SRB, 12) +Oper (Op1828, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 4, GN, SRB, 12) +Oper (Op1830, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 4, GN, SRB, 16) +Oper (Op1838, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 4, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1880, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 4, GN, SMB, 8) +Oper (Op1890, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 4, GN, SMB, 12) +Oper (Op1898, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 4, GN, SMB, 12) +Oper (Op18a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 4, GN, SMB, 16) +Oper (Op18a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 4, GN, SMB, 16) +Oper (Op18b0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 4, GN, SMB, 20) +Oper (Op18b8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 4, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op18c0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB, 4, GN, SMB, 8) +Oper (Op18d0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB, 4, GN, SMB, 12) +Oper (Op18d8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB, 4, GN, SMB, 12) +Oper (Op18e0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB, 4, GN, SMB, 16) +Oper (Op18e8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB, 4, GN, SMB, 16) +Oper (Op18f0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB, 4, GN, SMB, 20) +Oper (Op18f8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB, 4, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1900, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB, 4, GN, SMB, 12) +Oper (Op1910, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB, 4, GN, SMB, 16) +Oper (Op1918, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB, 4, GN, SMB, 16) +Oper (Op1920, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB, 4, GN, SMB, 16) +Oper (Op1928, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB, 4, GN, SMB, 20) +Oper (Op1930, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB, 4, GN, SMB, 20) +Oper (Op1938, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB, 4, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1940, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 4, GN, SMB, 12) +Oper (Op1950, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 4, GN, SMB, 16) +Oper (Op1958, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 4, GN, SMB, 16) +Oper (Op1960, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 4, GN, SMB, 20) +Oper (Op1968, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 4, GN, SMB, 20) +Oper (Op1970, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 4, GN, SMB, 24) +Oper (Op1978, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 4, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1980, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 4, GN, SMB, 16) +Oper (Op1990, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 4, GN, SMB, 20) +Oper (Op1998, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 4, GN, SMB, 20) +Oper (Op19a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 4, GN, SMB, 20) +Oper (Op19a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 4, GN, SMB, 24) +Oper (Op19b0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 4, GN, SMB, 24) +Oper (Op19b8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 4, GN, SMB, (cycles+21)&0xfffffffc) + +Oper (Op1a00, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 5, GN, SRB, 4) +Oper (Op1a10, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 5, GN, SRB, 8) +Oper (Op1a18, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 5, GN, SRB, 8) +Oper (Op1a20, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 5, GN, SRB, 12) +Oper (Op1a28, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 5, GN, SRB, 12) +Oper (Op1a30, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 5, GN, SRB, 16) +Oper (Op1a38, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 5, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1a80, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 5, GN, SMB, 8) +Oper (Op1a90, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 5, GN, SMB, 12) +Oper (Op1a98, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 5, GN, SMB, 12) +Oper (Op1aa0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 5, GN, SMB, 16) +Oper (Op1aa8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 5, GN, SMB, 16) +Oper (Op1ab0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 5, GN, SMB, 20) +Oper (Op1ab8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 5, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1ac0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB, 5, GN, SMB, 8) +Oper (Op1ad0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB, 5, GN, SMB, 12) +Oper (Op1ad8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB, 5, GN, SMB, 12) +Oper (Op1ae0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB, 5, GN, SMB, 16) +Oper (Op1ae8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB, 5, GN, SMB, 16) +Oper (Op1af0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB, 5, GN, SMB, 20) +Oper (Op1af8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB, 5, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1b00, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB, 5, GN, SMB, 12) +Oper (Op1b10, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB, 5, GN, SMB, 16) +Oper (Op1b18, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB, 5, GN, SMB, 16) +Oper (Op1b20, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB, 5, GN, SMB, 16) +Oper (Op1b28, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB, 5, GN, SMB, 20) +Oper (Op1b30, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB, 5, GN, SMB, 20) +Oper (Op1b38, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB, 5, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1b40, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 5, GN, SMB, 12) +Oper (Op1b50, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 5, GN, SMB, 16) +Oper (Op1b58, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 5, GN, SMB, 16) +Oper (Op1b60, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 5, GN, SMB, 20) +Oper (Op1b68, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 5, GN, SMB, 20) +Oper (Op1b70, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 5, GN, SMB, 24) +Oper (Op1b78, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 5, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1b80, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 5, GN, SMB, 16) +Oper (Op1b90, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 5, GN, SMB, 20) +Oper (Op1b98, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 5, GN, SMB, 20) +Oper (Op1ba0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 5, GN, SMB, 20) +Oper (Op1ba8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 5, GN, SMB, 24) +Oper (Op1bb0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 5, GN, SMB, 24) +Oper (Op1bb8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 5, GN, SMB, (cycles+21)&0xfffffffc) + +Oper (Op1c00, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 6, GN, SRB, 4) +Oper (Op1c10, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 6, GN, SRB, 8) +Oper (Op1c18, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 6, GN, SRB, 8) +Oper (Op1c20, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 6, GN, SRB, 12) +Oper (Op1c28, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 6, GN, SRB, 12) +Oper (Op1c30, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 6, GN, SRB, 16) +Oper (Op1c38, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 6, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1c80, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 6, GN, SMB, 8) +Oper (Op1c90, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 6, GN, SMB, 12) +Oper (Op1c98, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 6, GN, SMB, 12) +Oper (Op1ca0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 6, GN, SMB, 16) +Oper (Op1ca8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 6, GN, SMB, 16) +Oper (Op1cb0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 6, GN, SMB, 20) +Oper (Op1cb8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 6, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1cc0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB, 6, GN, SMB, 8) +Oper (Op1cd0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB, 6, GN, SMB, 12) +Oper (Op1cd8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB, 6, GN, SMB, 12) +Oper (Op1ce0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB, 6, GN, SMB, 16) +Oper (Op1ce8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB, 6, GN, SMB, 16) +Oper (Op1cf0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB, 6, GN, SMB, 20) +Oper (Op1cf8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB, 6, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1d00, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB, 6, GN, SMB, 12) +Oper (Op1d10, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB, 6, GN, SMB, 16) +Oper (Op1d18, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB, 6, GN, SMB, 16) +Oper (Op1d20, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB, 6, GN, SMB, 16) +Oper (Op1d28, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB, 6, GN, SMB, 20) +Oper (Op1d30, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB, 6, GN, SMB, 20) +Oper (Op1d38, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB, 6, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1d40, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 6, GN, SMB, 12) +Oper (Op1d50, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 6, GN, SMB, 16) +Oper (Op1d58, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 6, GN, SMB, 16) +Oper (Op1d60, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 6, GN, SMB, 20) +Oper (Op1d68, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 6, GN, SMB, 20) +Oper (Op1d70, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 6, GN, SMB, 24) +Oper (Op1d78, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 6, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1d80, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 6, GN, SMB, 16) +Oper (Op1d90, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 6, GN, SMB, 20) +Oper (Op1d98, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 6, GN, SMB, 20) +Oper (Op1da0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 6, GN, SMB, 20) +Oper (Op1da8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 6, GN, SMB, 24) +Oper (Op1db0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 6, GN, SMB, 24) +Oper (Op1db8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 6, GN, SMB, (cycles+21)&0xfffffffc) + +Oper (Op1e00, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 7, GN, SRB, 4) +Oper (Op1e10, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 7, GN, SRB, 8) +Oper (Op1e18, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 7, GN, SRB, 8) +Oper (Op1e20, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 7, GN, SRB, 12) +Oper (Op1e28, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 7, GN, SRB, 12) +Oper (Op1e30, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 7, GN, SRB, 16) +Oper (Op1e38, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 7, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1e80, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 7, GN, SMB, 8) +Oper (Op1e90, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 7, GN, SMB, 12) +Oper (Op1e98, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 7, GN, SMB, 12) +Oper (Op1ea0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 7, GN, SMB, 16) +Oper (Op1ea8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 7, GN, SMB, 16) +Oper (Op1eb0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 7, GN, SMB, 20) +Oper (Op1eb8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 7, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1ec0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB15, 7, GN, SMB, 8) +Oper (Op1ed0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB15, 7, GN, SMB, 12) +Oper (Op1ed8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB15, 7, GN, SMB, 12) +Oper (Op1ee0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB15, 7, GN, SMB, 16) +Oper (Op1ee8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB15, 7, GN, SMB, 16) +Oper (Op1ef0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB15, 7, GN, SMB, 20) +Oper (Op1ef8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB15, 7, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1f00, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB15, 7, GN, SMB, 12) +Oper (Op1f10, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB15, 7, GN, SMB, 16) +Oper (Op1f18, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB15, 7, GN, SMB, 16) +Oper (Op1f20, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB15, 7, GN, SMB, 16) +Oper (Op1f28, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB15, 7, GN, SMB, 20) +Oper (Op1f30, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB15, 7, GN, SMB, 20) +Oper (Op1f38, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB15, 7, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1f40, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 7, GN, SMB, 12) +Oper (Op1f50, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 7, GN, SMB, 16) +Oper (Op1f58, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 7, GN, SMB, 16) +Oper (Op1f60, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 7, GN, SMB, 20) +Oper (Op1f68, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 7, GN, SMB, 20) +Oper (Op1f70, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 7, GN, SMB, 24) +Oper (Op1f78, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 7, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1f80, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 7, GN, SMB, 16) +Oper (Op1f90, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 7, GN, SMB, 20) +Oper (Op1f98, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 7, GN, SMB, 20) +Oper (Op1fa0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 7, GN, SMB, 20) +Oper (Op1fa8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 7, GN, SMB, 24) +Oper (Op1fb0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 7, GN, SMB, 24) +Oper (Op1fb8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 7, GN, SMB, (cycles+21)&0xfffffffc) + +Oper (Op2000, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 0, GN, SRL, 4) +Oper (Op2008, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 0, GN, SRL, 4) +Oper (Op2010, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 0, GN, SRL, 12) +Oper (Op2018, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 0, GN, SRL, 12) +Oper (Op2020, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 0, GN, SRL, 16) +Oper (Op2028, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 0, GN, SRL, 16) +Oper (Op2030, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 0, GN, SRL, 20) +Oper (Op2038, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 0, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2040, DoMovea, DL, SdL, ins7, DL, DR, Ca, 0, GN, SRL, 4) +Oper (Op2048, DoMovea, DL, SaL, ins7, DL, DR, Ca, 0, GN, SRL, 4) +Oper (Op2050, DoMovea, DL, SainL, ins7, DL, DR, Ca, 0, GN, SRL, 12) +Oper (Op2058, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 0, GN, SRL, 12) +Oper (Op2060, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 0, GN, SRL, 16) +Oper (Op2068, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 0, GN, SRL, 16) +Oper (Op2070, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 0, GN, SRL, 20) +Oper (Op2078, DoMovea, DL, SearL, ins7, DL, DR, Ca, 0, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2080, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 0, GN, SML, 12) +Oper (Op2088, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 0, GN, SML, 12) +Oper (Op2090, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 0, GN, SML, 20) +Oper (Op2098, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 0, GN, SML, 20) +Oper (Op20a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 0, GN, SML, 24) +Oper (Op20a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 0, GN, SML, 24) +Oper (Op20b0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 0, GN, SML, 28) +Oper (Op20b8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 0, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op20c0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 0, GN, SML, 12) +Oper (Op20c8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 0, GN, SML, 12) +Oper (Op20d0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 0, GN, SML, 20) +Oper (Op20d8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 0, GN, SML, 20) +Oper (Op20e0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 0, GN, SML, 24) +Oper (Op20e8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 0, GN, SML, 24) +Oper (Op20f0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 0, GN, SML, 28) +Oper (Op20f8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 0, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2100, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 0, GN, SML, 16) +Oper (Op2108, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 0, GN, SML, 16) +Oper (Op2110, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 0, GN, SML, 24) +Oper (Op2118, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 0, GN, SML, 24) +Oper (Op2120, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 0, GN, SML, 24) +Oper (Op2128, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 0, GN, SML, 28) +Oper (Op2130, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 0, GN, SML, 28) +Oper (Op2138, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 0, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2140, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 0, GN, SML, 16) +Oper (Op2148, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 0, GN, SML, 16) +Oper (Op2150, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 0, GN, SML, 24) +Oper (Op2158, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 0, GN, SML, 24) +Oper (Op2160, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 0, GN, SML, 28) +Oper (Op2168, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 0, GN, SML, 28) +Oper (Op2170, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 0, GN, SML, 32) +Oper (Op2178, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 0, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2180, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 0, GN, SML, 20) +Oper (Op2188, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 0, GN, SML, 20) +Oper (Op2190, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 0, GN, SML, 28) +Oper (Op2198, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 0, GN, SML, 28) +Oper (Op21a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 0, GN, SML, 28) +Oper (Op21a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 0, GN, SML, 32) +Oper (Op21b0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 0, GN, SML, 32) +Oper (Op21b8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 0, GN, SML, (cycles+29)&0xfffffffc) +Oper (Op21c0, DoMoveL, DL, SdL, ins7, DL, DA, Feaw, 0, GN, SML, 16) +Oper (Op21c8, DoMoveL, DL, SaL, ins7, DL, DA, Feaw, 0, GN, SML, 16) +Oper (Op21d0, DoMoveL, DL, SainL, ins7, DL, DA, Feaw, 0, GN, SML, 24) +Oper (Op21d8, DoMoveL, DL, SaipL, ins7, DL, DA, Feaw, 0, GN, SML, 24) +Oper (Op21e0, DoMoveL, DL, SmaiL, ins7, DL, DA, Feaw, 0, GN, SML, 28) +Oper (Op21e8, DoMoveL, DL, SdaiL, ins7, DL, DA, Ceaw, 0, GN, SML, 28) +Oper (Op21f0, DoMoveL, DL, SaixL, ins7, DL, DA, Ceaw, 0, GN, SML, 32) +Oper (Op21f8, DoMoveL, DL, SearL, ins7, DL, DA, Ceaw, 0, GN, SML, (cycles+27)&0xfffffffc) + +Oper (Op2200, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 1, GN, SRL, 4) +Oper (Op2208, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 1, GN, SRL, 4) +Oper (Op2210, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 1, GN, SRL, 12) +Oper (Op2218, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 1, GN, SRL, 12) +Oper (Op2220, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 1, GN, SRL, 16) +Oper (Op2228, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 1, GN, SRL, 16) +Oper (Op2230, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 1, GN, SRL, 20) +Oper (Op2238, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 1, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2240, DoMovea, DL, SdL, ins7, DL, DR, Ca, 1, GN, SRL, 4) +Oper (Op2248, DoMovea, DL, SaL, ins7, DL, DR, Ca, 1, GN, SRL, 4) +Oper (Op2250, DoMovea, DL, SainL, ins7, DL, DR, Ca, 1, GN, SRL, 12) +Oper (Op2258, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 1, GN, SRL, 12) +Oper (Op2260, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 1, GN, SRL, 16) +Oper (Op2268, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 1, GN, SRL, 16) +Oper (Op2270, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 1, GN, SRL, 20) +Oper (Op2278, DoMovea, DL, SearL, ins7, DL, DR, Ca, 1, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2280, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 1, GN, SML, 12) +Oper (Op2288, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 1, GN, SML, 12) +Oper (Op2290, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 1, GN, SML, 20) +Oper (Op2298, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 1, GN, SML, 20) +Oper (Op22a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 1, GN, SML, 24) +Oper (Op22a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 1, GN, SML, 24) +Oper (Op22b0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 1, GN, SML, 28) +Oper (Op22b8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 1, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op22c0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 1, GN, SML, 12) +Oper (Op22c8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 1, GN, SML, 12) +Oper (Op22d0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 1, GN, SML, 20) +Oper (Op22d8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 1, GN, SML, 20) +Oper (Op22e0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 1, GN, SML, 24) +Oper (Op22e8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 1, GN, SML, 24) +Oper (Op22f0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 1, GN, SML, 28) +Oper (Op22f8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 1, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2300, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 1, GN, SML, 16) +Oper (Op2308, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 1, GN, SML, 16) +Oper (Op2310, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 1, GN, SML, 24) +Oper (Op2318, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 1, GN, SML, 24) +Oper (Op2320, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 1, GN, SML, 24) +Oper (Op2328, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 1, GN, SML, 28) +Oper (Op2330, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 1, GN, SML, 28) +Oper (Op2338, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 1, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2340, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 1, GN, SML, 16) +Oper (Op2348, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 1, GN, SML, 16) +Oper (Op2350, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 1, GN, SML, 24) +Oper (Op2358, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 1, GN, SML, 24) +Oper (Op2360, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 1, GN, SML, 28) +Oper (Op2368, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 1, GN, SML, 28) +Oper (Op2370, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 1, GN, SML, 32) +Oper (Op2378, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 1, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2380, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 1, GN, SML, 20) +Oper (Op2388, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 1, GN, SML, 20) +Oper (Op2390, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 1, GN, SML, 28) +Oper (Op2398, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 1, GN, SML, 28) +Oper (Op23a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 1, GN, SML, 28) +Oper (Op23a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 1, GN, SML, 32) +Oper (Op23b0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 1, GN, SML, 32) +Oper (Op23b8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 1, GN, SML, (cycles+29)&0xfffffffc) +Oper (Op23c0, DoMoveL, DL, SdL, ins7, DL, DA, Feaw, 1, GN, SML, 20) +Oper (Op23c8, DoMoveL, DL, SaL, ins7, DL, DA, Feaw, 1, GN, SML, 20) +Oper (Op23d0, DoMoveL, DL, SainL, ins7, DL, DA, Feaw, 1, GN, SML, 28) +Oper (Op23d8, DoMoveL, DL, SaipL, ins7, DL, DA, Feaw, 1, GN, SML, 28) +Oper (Op23e0, DoMoveL, DL, SmaiL, ins7, DL, DA, Feaw, 1, GN, SML, 32) +Oper (Op23e8, DoMoveL, DL, SdaiL, ins7, DL, DA, Ceaw, 1, GN, SML, 32) +Oper (Op23f0, DoMoveL, DL, SaixL, ins7, DL, DA, Ceaw, 1, GN, SML, 36) +Oper (Op23f8, DoMoveL, DL, SearL, ins7, DL, DA, Ceaw, 1, GN, SML, (cycles+31)&0xfffffffc) + +Oper (Op2400, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 2, GN, SRL, 4) +Oper (Op2408, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 2, GN, SRL, 4) +Oper (Op2410, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 2, GN, SRL, 12) +Oper (Op2418, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 2, GN, SRL, 12) +Oper (Op2420, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 2, GN, SRL, 16) +Oper (Op2428, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 2, GN, SRL, 16) +Oper (Op2430, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 2, GN, SRL, 20) +Oper (Op2438, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 2, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2440, DoMovea, DL, SdL, ins7, DL, DR, Ca, 2, GN, SRL, 4) +Oper (Op2448, DoMovea, DL, SaL, ins7, DL, DR, Ca, 2, GN, SRL, 4) +Oper (Op2450, DoMovea, DL, SainL, ins7, DL, DR, Ca, 2, GN, SRL, 12) +Oper (Op2458, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 2, GN, SRL, 12) +Oper (Op2460, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 2, GN, SRL, 16) +Oper (Op2468, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 2, GN, SRL, 16) +Oper (Op2470, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 2, GN, SRL, 20) +Oper (Op2478, DoMovea, DL, SearL, ins7, DL, DR, Ca, 2, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2480, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 2, GN, SML, 12) +Oper (Op2488, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 2, GN, SML, 12) +Oper (Op2490, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 2, GN, SML, 20) +Oper (Op2498, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 2, GN, SML, 20) +Oper (Op24a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 2, GN, SML, 24) +Oper (Op24a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 2, GN, SML, 24) +Oper (Op24b0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 2, GN, SML, 28) +Oper (Op24b8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 2, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op24c0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 2, GN, SML, 12) +Oper (Op24c8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 2, GN, SML, 12) +Oper (Op24d0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 2, GN, SML, 20) +Oper (Op24d8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 2, GN, SML, 20) +Oper (Op24e0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 2, GN, SML, 24) +Oper (Op24e8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 2, GN, SML, 24) +Oper (Op24f0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 2, GN, SML, 28) +Oper (Op24f8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 2, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2500, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 2, GN, SML, 16) +Oper (Op2508, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 2, GN, SML, 16) +Oper (Op2510, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 2, GN, SML, 24) +Oper (Op2518, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 2, GN, SML, 24) +Oper (Op2520, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 2, GN, SML, 24) +Oper (Op2528, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 2, GN, SML, 28) +Oper (Op2530, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 2, GN, SML, 28) +Oper (Op2538, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 2, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2540, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 2, GN, SML, 16) +Oper (Op2548, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 2, GN, SML, 16) +Oper (Op2550, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 2, GN, SML, 24) +Oper (Op2558, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 2, GN, SML, 24) +Oper (Op2560, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 2, GN, SML, 28) +Oper (Op2568, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 2, GN, SML, 28) +Oper (Op2570, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 2, GN, SML, 32) +Oper (Op2578, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 2, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2580, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 2, GN, SML, 20) +Oper (Op2588, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 2, GN, SML, 20) +Oper (Op2590, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 2, GN, SML, 28) +Oper (Op2598, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 2, GN, SML, 28) +Oper (Op25a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 2, GN, SML, 28) +Oper (Op25a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 2, GN, SML, 32) +Oper (Op25b0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 2, GN, SML, 32) +Oper (Op25b8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 2, GN, SML, (cycles+29)&0xfffffffc) + +Oper (Op2600, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 3, GN, SRL, 4) +Oper (Op2608, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 3, GN, SRL, 4) +Oper (Op2610, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 3, GN, SRL, 12) +Oper (Op2618, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 3, GN, SRL, 12) +Oper (Op2620, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 3, GN, SRL, 16) +Oper (Op2628, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 3, GN, SRL, 16) +Oper (Op2630, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 3, GN, SRL, 20) +Oper (Op2638, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 3, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2640, DoMovea, DL, SdL, ins7, DL, DR, Ca, 3, GN, SRL, 4) +Oper (Op2648, DoMovea, DL, SaL, ins7, DL, DR, Ca, 3, GN, SRL, 4) +Oper (Op2650, DoMovea, DL, SainL, ins7, DL, DR, Ca, 3, GN, SRL, 12) +Oper (Op2658, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 3, GN, SRL, 12) +Oper (Op2660, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 3, GN, SRL, 16) +Oper (Op2668, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 3, GN, SRL, 16) +Oper (Op2670, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 3, GN, SRL, 20) +Oper (Op2678, DoMovea, DL, SearL, ins7, DL, DR, Ca, 3, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2680, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 3, GN, SML, 12) +Oper (Op2688, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 3, GN, SML, 12) +Oper (Op2690, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 3, GN, SML, 20) +Oper (Op2698, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 3, GN, SML, 20) +Oper (Op26a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 3, GN, SML, 24) +Oper (Op26a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 3, GN, SML, 24) +Oper (Op26b0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 3, GN, SML, 28) +Oper (Op26b8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 3, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op26c0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 3, GN, SML, 12) +Oper (Op26c8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 3, GN, SML, 12) +Oper (Op26d0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 3, GN, SML, 20) +Oper (Op26d8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 3, GN, SML, 20) +Oper (Op26e0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 3, GN, SML, 24) +Oper (Op26e8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 3, GN, SML, 24) +Oper (Op26f0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 3, GN, SML, 28) +Oper (Op26f8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 3, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2700, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 3, GN, SML, 16) +Oper (Op2708, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 3, GN, SML, 16) +Oper (Op2710, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 3, GN, SML, 24) +Oper (Op2718, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 3, GN, SML, 24) +Oper (Op2720, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 3, GN, SML, 24) +Oper (Op2728, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 3, GN, SML, 28) +Oper (Op2730, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 3, GN, SML, 28) +Oper (Op2738, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 3, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2740, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 3, GN, SML, 16) +Oper (Op2748, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 3, GN, SML, 16) +Oper (Op2750, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 3, GN, SML, 24) +Oper (Op2758, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 3, GN, SML, 24) +Oper (Op2760, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 3, GN, SML, 28) +Oper (Op2768, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 3, GN, SML, 28) +Oper (Op2770, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 3, GN, SML, 32) +Oper (Op2778, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 3, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2780, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 3, GN, SML, 20) +Oper (Op2788, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 3, GN, SML, 20) +Oper (Op2790, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 3, GN, SML, 28) +Oper (Op2798, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 3, GN, SML, 28) +Oper (Op27a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 3, GN, SML, 28) +Oper (Op27a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 3, GN, SML, 32) +Oper (Op27b0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 3, GN, SML, 32) +Oper (Op27b8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 3, GN, SML, (cycles+29)&0xfffffffc) + +Oper (Op2800, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 4, GN, SRL, 4) +Oper (Op2808, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 4, GN, SRL, 4) +Oper (Op2810, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 4, GN, SRL, 12) +Oper (Op2818, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 4, GN, SRL, 12) +Oper (Op2820, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 4, GN, SRL, 16) +Oper (Op2828, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 4, GN, SRL, 16) +Oper (Op2830, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 4, GN, SRL, 20) +Oper (Op2838, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 4, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2840, DoMovea, DL, SdL, ins7, DL, DR, Ca, 4, GN, SRL, 4) +Oper (Op2848, DoMovea, DL, SaL, ins7, DL, DR, Ca, 4, GN, SRL, 4) +Oper (Op2850, DoMovea, DL, SainL, ins7, DL, DR, Ca, 4, GN, SRL, 12) +Oper (Op2858, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 4, GN, SRL, 12) +Oper (Op2860, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 4, GN, SRL, 16) +Oper (Op2868, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 4, GN, SRL, 16) +Oper (Op2870, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 4, GN, SRL, 20) +Oper (Op2878, DoMovea, DL, SearL, ins7, DL, DR, Ca, 4, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2880, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 4, GN, SML, 12) +Oper (Op2888, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 4, GN, SML, 12) +Oper (Op2890, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 4, GN, SML, 20) +Oper (Op2898, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 4, GN, SML, 20) +Oper (Op28a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 4, GN, SML, 24) +Oper (Op28a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 4, GN, SML, 24) +Oper (Op28b0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 4, GN, SML, 28) +Oper (Op28b8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 4, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op28c0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 4, GN, SML, 12) +Oper (Op28c8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 4, GN, SML, 12) +Oper (Op28d0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 4, GN, SML, 20) +Oper (Op28d8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 4, GN, SML, 20) +Oper (Op28e0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 4, GN, SML, 24) +Oper (Op28e8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 4, GN, SML, 24) +Oper (Op28f0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 4, GN, SML, 28) +Oper (Op28f8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 4, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2900, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 4, GN, SML, 16) +Oper (Op2908, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 4, GN, SML, 16) +Oper (Op2910, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 4, GN, SML, 24) +Oper (Op2918, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 4, GN, SML, 24) +Oper (Op2920, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 4, GN, SML, 24) +Oper (Op2928, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 4, GN, SML, 28) +Oper (Op2930, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 4, GN, SML, 28) +Oper (Op2938, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 4, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2940, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 4, GN, SML, 16) +Oper (Op2948, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 4, GN, SML, 16) +Oper (Op2950, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 4, GN, SML, 24) +Oper (Op2958, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 4, GN, SML, 24) +Oper (Op2960, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 4, GN, SML, 28) +Oper (Op2968, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 4, GN, SML, 28) +Oper (Op2970, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 4, GN, SML, 32) +Oper (Op2978, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 4, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2980, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 4, GN, SML, 20) +Oper (Op2988, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 4, GN, SML, 20) +Oper (Op2990, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 4, GN, SML, 28) +Oper (Op2998, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 4, GN, SML, 28) +Oper (Op29a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 4, GN, SML, 28) +Oper (Op29a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 4, GN, SML, 32) +Oper (Op29b0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 4, GN, SML, 32) +Oper (Op29b8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 4, GN, SML, (cycles+29)&0xfffffffc) + +Oper (Op2a00, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 5, GN, SRL, 4) +Oper (Op2a08, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 5, GN, SRL, 4) +Oper (Op2a10, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 5, GN, SRL, 12) +Oper (Op2a18, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 5, GN, SRL, 12) +Oper (Op2a20, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 5, GN, SRL, 16) +Oper (Op2a28, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 5, GN, SRL, 16) +Oper (Op2a30, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 5, GN, SRL, 20) +Oper (Op2a38, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 5, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2a40, DoMovea, DL, SdL, ins7, DL, DR, Ca, 5, GN, SRL, 4) +Oper (Op2a48, DoMovea, DL, SaL, ins7, DL, DR, Ca, 5, GN, SRL, 4) +Oper (Op2a50, DoMovea, DL, SainL, ins7, DL, DR, Ca, 5, GN, SRL, 12) +Oper (Op2a58, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 5, GN, SRL, 12) +Oper (Op2a60, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 5, GN, SRL, 16) +Oper (Op2a68, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 5, GN, SRL, 16) +Oper (Op2a70, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 5, GN, SRL, 20) +Oper (Op2a78, DoMovea, DL, SearL, ins7, DL, DR, Ca, 5, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2a80, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 5, GN, SML, 12) +Oper (Op2a88, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 5, GN, SML, 12) +Oper (Op2a90, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 5, GN, SML, 20) +Oper (Op2a98, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 5, GN, SML, 20) +Oper (Op2aa0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 5, GN, SML, 24) +Oper (Op2aa8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 5, GN, SML, 24) +Oper (Op2ab0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 5, GN, SML, 28) +Oper (Op2ab8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 5, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2ac0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 5, GN, SML, 12) +Oper (Op2ac8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 5, GN, SML, 12) +Oper (Op2ad0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 5, GN, SML, 20) +Oper (Op2ad8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 5, GN, SML, 20) +Oper (Op2ae0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 5, GN, SML, 24) +Oper (Op2ae8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 5, GN, SML, 24) +Oper (Op2af0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 5, GN, SML, 28) +Oper (Op2af8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 5, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2b00, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 5, GN, SML, 16) +Oper (Op2b08, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 5, GN, SML, 16) +Oper (Op2b10, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 5, GN, SML, 24) +Oper (Op2b18, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 5, GN, SML, 24) +Oper (Op2b20, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 5, GN, SML, 24) +Oper (Op2b28, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 5, GN, SML, 28) +Oper (Op2b30, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 5, GN, SML, 28) +Oper (Op2b38, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 5, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2b40, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 5, GN, SML, 16) +Oper (Op2b48, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 5, GN, SML, 16) +Oper (Op2b50, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 5, GN, SML, 24) +Oper (Op2b58, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 5, GN, SML, 24) +Oper (Op2b60, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 5, GN, SML, 28) +Oper (Op2b68, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 5, GN, SML, 28) +Oper (Op2b70, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 5, GN, SML, 32) +Oper (Op2b78, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 5, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2b80, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 5, GN, SML, 20) +Oper (Op2b88, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 5, GN, SML, 20) +Oper (Op2b90, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 5, GN, SML, 28) +Oper (Op2b98, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 5, GN, SML, 28) +Oper (Op2ba0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 5, GN, SML, 28) +Oper (Op2ba8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 5, GN, SML, 32) +Oper (Op2bb0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 5, GN, SML, 32) +Oper (Op2bb8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 5, GN, SML, (cycles+29)&0xfffffffc) + +Oper (Op2c00, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 6, GN, SRL, 4) +Oper (Op2c08, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 6, GN, SRL, 4) +Oper (Op2c10, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 6, GN, SRL, 12) +Oper (Op2c18, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 6, GN, SRL, 12) +Oper (Op2c20, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 6, GN, SRL, 16) +Oper (Op2c28, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 6, GN, SRL, 16) +Oper (Op2c30, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 6, GN, SRL, 20) +Oper (Op2c38, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 6, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2c40, DoMovea, DL, SdL, ins7, DL, DR, Ca, 6, GN, SRL, 4) +Oper (Op2c48, DoMovea, DL, SaL, ins7, DL, DR, Ca, 6, GN, SRL, 4) +Oper (Op2c50, DoMovea, DL, SainL, ins7, DL, DR, Ca, 6, GN, SRL, 12) +Oper (Op2c58, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 6, GN, SRL, 12) +Oper (Op2c60, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 6, GN, SRL, 16) +Oper (Op2c68, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 6, GN, SRL, 16) +Oper (Op2c70, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 6, GN, SRL, 20) +Oper (Op2c78, DoMovea, DL, SearL, ins7, DL, DR, Ca, 6, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2c80, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 6, GN, SML, 12) +Oper (Op2c88, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 6, GN, SML, 12) +Oper (Op2c90, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 6, GN, SML, 20) +Oper (Op2c98, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 6, GN, SML, 20) +Oper (Op2ca0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 6, GN, SML, 24) +Oper (Op2ca8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 6, GN, SML, 24) +Oper (Op2cb0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 6, GN, SML, 28) +Oper (Op2cb8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 6, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2cc0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 6, GN, SML, 12) +Oper (Op2cc8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 6, GN, SML, 12) +Oper (Op2cd0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 6, GN, SML, 20) +Oper (Op2cd8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 6, GN, SML, 20) +Oper (Op2ce0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 6, GN, SML, 24) +Oper (Op2ce8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 6, GN, SML, 24) +Oper (Op2cf0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 6, GN, SML, 28) +Oper (Op2cf8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 6, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2d00, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 6, GN, SML, 16) +Oper (Op2d08, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 6, GN, SML, 16) +Oper (Op2d10, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 6, GN, SML, 24) +Oper (Op2d18, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 6, GN, SML, 24) +Oper (Op2d20, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 6, GN, SML, 24) +Oper (Op2d28, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 6, GN, SML, 28) +Oper (Op2d30, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 6, GN, SML, 28) +Oper (Op2d38, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 6, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2d40, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 6, GN, SML, 16) +Oper (Op2d48, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 6, GN, SML, 16) +Oper (Op2d50, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 6, GN, SML, 24) +Oper (Op2d58, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 6, GN, SML, 24) +Oper (Op2d60, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 6, GN, SML, 28) +Oper (Op2d68, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 6, GN, SML, 28) +Oper (Op2d70, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 6, GN, SML, 32) +Oper (Op2d78, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 6, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2d80, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 6, GN, SML, 20) +Oper (Op2d88, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 6, GN, SML, 20) +Oper (Op2d90, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 6, GN, SML, 28) +Oper (Op2d98, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 6, GN, SML, 28) +Oper (Op2da0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 6, GN, SML, 28) +Oper (Op2da8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 6, GN, SML, 32) +Oper (Op2db0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 6, GN, SML, 32) +Oper (Op2db8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 6, GN, SML, (cycles+29)&0xfffffffc) + +Oper (Op2e00, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 7, GN, SRL, 4) +Oper (Op2e08, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 7, GN, SRL, 4) +Oper (Op2e10, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 7, GN, SRL, 12) +Oper (Op2e18, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 7, GN, SRL, 12) +Oper (Op2e20, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 7, GN, SRL, 16) +Oper (Op2e28, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 7, GN, SRL, 16) +Oper (Op2e30, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 7, GN, SRL, 20) +Oper (Op2e38, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 7, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2e40, DoMovea, DL, SdL, ins7, DL, DR, Ca, 7, GN, SRL, 4) +Oper (Op2e48, DoMovea, DL, SaL, ins7, DL, DR, Ca, 7, GN, SRL, 4) +Oper (Op2e50, DoMovea, DL, SainL, ins7, DL, DR, Ca, 7, GN, SRL, 12) +Oper (Op2e58, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 7, GN, SRL, 12) +Oper (Op2e60, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 7, GN, SRL, 16) +Oper (Op2e68, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 7, GN, SRL, 16) +Oper (Op2e70, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 7, GN, SRL, 20) +Oper (Op2e78, DoMovea, DL, SearL, ins7, DL, DR, Ca, 7, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2e80, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 7, GN, SML, 12) +Oper (Op2e88, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 7, GN, SML, 12) +Oper (Op2e90, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 7, GN, SML, 20) +Oper (Op2e98, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 7, GN, SML, 20) +Oper (Op2ea0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 7, GN, SML, 24) +Oper (Op2ea8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 7, GN, SML, 24) +Oper (Op2eb0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 7, GN, SML, 28) +Oper (Op2eb8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 7, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2ec0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 7, GN, SML, 12) +Oper (Op2ec8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 7, GN, SML, 12) +Oper (Op2ed0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 7, GN, SML, 20) +Oper (Op2ed8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 7, GN, SML, 20) +Oper (Op2ee0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 7, GN, SML, 24) +Oper (Op2ee8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 7, GN, SML, 24) +Oper (Op2ef0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 7, GN, SML, 28) +Oper (Op2ef8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 7, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2f00, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 7, GN, SML, 16) +Oper (Op2f08, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 7, GN, SML, 16) +Oper (Op2f10, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 7, GN, SML, 24) +Oper (Op2f18, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 7, GN, SML, 24) +Oper (Op2f20, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 7, GN, SML, 24) +Oper (Op2f28, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 7, GN, SML, 28) +Oper (Op2f30, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 7, GN, SML, 28) +Oper (Op2f38, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 7, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2f40, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 7, GN, SML, 16) +Oper (Op2f48, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 7, GN, SML, 16) +Oper (Op2f50, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 7, GN, SML, 24) +Oper (Op2f58, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 7, GN, SML, 24) +Oper (Op2f60, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 7, GN, SML, 28) +Oper (Op2f68, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 7, GN, SML, 28) +Oper (Op2f70, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 7, GN, SML, 32) +Oper (Op2f78, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 7, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2f80, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 7, GN, SML, 20) +Oper (Op2f88, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 7, GN, SML, 20) +Oper (Op2f90, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 7, GN, SML, 28) +Oper (Op2f98, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 7, GN, SML, 28) +Oper (Op2fa0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 7, GN, SML, 28) +Oper (Op2fa8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 7, GN, SML, 32) +Oper (Op2fb0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 7, GN, SML, 32) +Oper (Op2fb8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 7, GN, SML, (cycles+29)&0xfffffffc) + +Oper (Op3000, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 0, GN, SRW, 4) +Oper (Op3008, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 0, GN, SRW, 4) +Oper (Op3010, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 0, GN, SRW, 8) +Oper (Op3018, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 0, GN, SRW, 8) +Oper (Op3020, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 0, GN, SRW, 12) +Oper (Op3028, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 0, GN, SRW, 12) +Oper (Op3030, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 0, GN, SRW, 16) +Oper (Op3038, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 0, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3040, DoMovea, DW, SdW, ins7, DL, DR, Ca, 0, GN, SRL, 4) +Oper (Op3048, DoMovea, DW, SaW, ins7, DL, DR, Ca, 0, GN, SRL, 4) +Oper (Op3050, DoMovea, DW, SainW, ins7, DL, DR, Ca, 0, GN, SRL, 8) +Oper (Op3058, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 0, GN, SRL, 8) +Oper (Op3060, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 0, GN, SRL, 12) +Oper (Op3068, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 0, GN, SRL, 12) +Oper (Op3070, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 0, GN, SRL, 16) +Oper (Op3078, DoMovea, DW, SearW, ins7, DL, DR, Ca, 0, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3080, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 0, GN, SMW, 8) +Oper (Op3088, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 0, GN, SMW, 8) +Oper (Op3090, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 0, GN, SMW, 12) +Oper (Op3098, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 0, GN, SMW, 12) +Oper (Op30a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 0, GN, SMW, 16) +Oper (Op30a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 0, GN, SMW, 16) +Oper (Op30b0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 0, GN, SMW, 20) +Oper (Op30b8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 0, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op30c0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 0, GN, SMW, 8) +Oper (Op30c8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 0, GN, SMW, 8) +Oper (Op30d0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 0, GN, SMW, 12) +Oper (Op30d8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 0, GN, SMW, 12) +Oper (Op30e0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 0, GN, SMW, 16) +Oper (Op30e8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 0, GN, SMW, 16) +Oper (Op30f0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 0, GN, SMW, 20) +Oper (Op30f8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 0, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3100, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 0, GN, SMW, 12) +Oper (Op3108, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 0, GN, SMW, 12) +Oper (Op3110, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 0, GN, SMW, 16) +Oper (Op3118, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 0, GN, SMW, 16) +Oper (Op3120, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 0, GN, SMW, 16) +Oper (Op3128, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 0, GN, SMW, 20) +Oper (Op3130, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 0, GN, SMW, 20) +Oper (Op3138, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 0, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3140, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 0, GN, SMW, 12) +Oper (Op3148, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 0, GN, SMW, 12) +Oper (Op3150, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 0, GN, SMW, 16) +Oper (Op3158, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 0, GN, SMW, 16) +Oper (Op3160, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 0, GN, SMW, 20) +Oper (Op3168, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 0, GN, SMW, 20) +Oper (Op3170, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 0, GN, SMW, 24) +Oper (Op3178, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 0, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3180, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 0, GN, SMW, 16) +Oper (Op3188, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 0, GN, SMW, 16) +Oper (Op3190, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 0, GN, SMW, 20) +Oper (Op3198, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 0, GN, SMW, 20) +Oper (Op31a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 0, GN, SMW, 20) +Oper (Op31a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 0, GN, SMW, 24) +Oper (Op31b0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 0, GN, SMW, 24) +Oper (Op31b8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 0, GN, SMW, (cycles+21)&0xfffffffc) +Oper (Op31c0, DoMoveW, DW, SdW, ins7, DW, DA, Feaw, 0, GN, SMW, 12) +Oper (Op31c8, DoMoveW, DW, SaW, ins7, DW, DA, Feaw, 0, GN, SMW, 12) +Oper (Op31d0, DoMoveW, DW, SainW, ins7, DW, DA, Feaw, 0, GN, SMW, 16) +Oper (Op31d8, DoMoveW, DW, SaipW, ins7, DW, DA, Feaw, 0, GN, SMW, 16) +Oper (Op31e0, DoMoveW, DW, SmaiW, ins7, DW, DA, Feaw, 0, GN, SMW, 20) +Oper (Op31e8, DoMoveW, DW, SdaiW, ins7, DW, DA, Ceaw, 0, GN, SMW, 20) +Oper (Op31f0, DoMoveW, DW, SaixW, ins7, DW, DA, Ceaw, 0, GN, SMW, 24) +Oper (Op31f8, DoMoveW, DW, SearW, ins7, DW, DA, Ceaw, 0, GN, SMW, (cycles+19)&0xfffffffc) + +Oper (Op3200, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 1, GN, SRW, 4) +Oper (Op3208, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 1, GN, SRW, 4) +Oper (Op3210, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 1, GN, SRW, 8) +Oper (Op3218, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 1, GN, SRW, 8) +Oper (Op3220, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 1, GN, SRW, 12) +Oper (Op3228, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 1, GN, SRW, 12) +Oper (Op3230, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 1, GN, SRW, 16) +Oper (Op3238, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 1, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3240, DoMovea, DW, SdW, ins7, DL, DR, Ca, 1, GN, SRL, 4) +Oper (Op3248, DoMovea, DW, SaW, ins7, DL, DR, Ca, 1, GN, SRL, 4) +Oper (Op3250, DoMovea, DW, SainW, ins7, DL, DR, Ca, 1, GN, SRL, 8) +Oper (Op3258, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 1, GN, SRL, 8) +Oper (Op3260, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 1, GN, SRL, 12) +Oper (Op3268, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 1, GN, SRL, 12) +Oper (Op3270, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 1, GN, SRL, 16) +Oper (Op3278, DoMovea, DW, SearW, ins7, DL, DR, Ca, 1, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3280, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 1, GN, SMW, 8) +Oper (Op3288, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 1, GN, SMW, 8) +Oper (Op3290, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 1, GN, SMW, 12) +Oper (Op3298, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 1, GN, SMW, 12) +Oper (Op32a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 1, GN, SMW, 16) +Oper (Op32a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 1, GN, SMW, 16) +Oper (Op32b0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 1, GN, SMW, 20) +Oper (Op32b8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 1, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op32c0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 1, GN, SMW, 8) +Oper (Op32c8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 1, GN, SMW, 8) +Oper (Op32d0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 1, GN, SMW, 12) +Oper (Op32d8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 1, GN, SMW, 12) +Oper (Op32e0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 1, GN, SMW, 16) +Oper (Op32e8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 1, GN, SMW, 16) +Oper (Op32f0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 1, GN, SMW, 20) +Oper (Op32f8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 1, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3300, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 1, GN, SMW, 12) +Oper (Op3308, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 1, GN, SMW, 12) +Oper (Op3310, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 1, GN, SMW, 16) +Oper (Op3318, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 1, GN, SMW, 16) +Oper (Op3320, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 1, GN, SMW, 16) +Oper (Op3328, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 1, GN, SMW, 20) +Oper (Op3330, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 1, GN, SMW, 20) +Oper (Op3338, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 1, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3340, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 1, GN, SMW, 12) +Oper (Op3348, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 1, GN, SMW, 12) +Oper (Op3350, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 1, GN, SMW, 16) +Oper (Op3358, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 1, GN, SMW, 16) +Oper (Op3360, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 1, GN, SMW, 20) +Oper (Op3368, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 1, GN, SMW, 20) +Oper (Op3370, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 1, GN, SMW, 24) +Oper (Op3378, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 1, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3380, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 1, GN, SMW, 16) +Oper (Op3388, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 1, GN, SMW, 16) +Oper (Op3390, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 1, GN, SMW, 20) +Oper (Op3398, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 1, GN, SMW, 20) +Oper (Op33a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 1, GN, SMW, 20) +Oper (Op33a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 1, GN, SMW, 24) +Oper (Op33b0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 1, GN, SMW, 24) +Oper (Op33b8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 1, GN, SMW, (cycles+21)&0xfffffffc) +Oper (Op33c0, DoMoveW, DW, SdW, ins7, DW, DA, Feaw, 1, GN, SMW, 16) +Oper (Op33c8, DoMoveW, DW, SaW, ins7, DW, DA, Feaw, 1, GN, SMW, 16) +Oper (Op33d0, DoMoveW, DW, SainW, ins7, DW, DA, Feaw, 1, GN, SMW, 20) +Oper (Op33d8, DoMoveW, DW, SaipW, ins7, DW, DA, Feaw, 1, GN, SMW, 20) +Oper (Op33e0, DoMoveW, DW, SmaiW, ins7, DW, DA, Feaw, 1, GN, SMW, 24) +Oper (Op33e8, DoMoveW, DW, SdaiW, ins7, DW, DA, Ceaw, 1, GN, SMW, 24) +Oper (Op33f0, DoMoveW, DW, SaixW, ins7, DW, DA, Ceaw, 1, GN, SMW, 28) +Oper (Op33f8, DoMoveW, DW, SearW, ins7, DW, DA, Ceaw, 1, GN, SMW, (cycles+23)&0xfffffffc) + +Oper (Op3400, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 2, GN, SRW, 4) +Oper (Op3408, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 2, GN, SRW, 4) +Oper (Op3410, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 2, GN, SRW, 8) +Oper (Op3418, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 2, GN, SRW, 8) +Oper (Op3420, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 2, GN, SRW, 12) +Oper (Op3428, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 2, GN, SRW, 12) +Oper (Op3430, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 2, GN, SRW, 16) +Oper (Op3438, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 2, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3440, DoMovea, DW, SdW, ins7, DL, DR, Ca, 2, GN, SRL, 4) +Oper (Op3448, DoMovea, DW, SaW, ins7, DL, DR, Ca, 2, GN, SRL, 4) +Oper (Op3450, DoMovea, DW, SainW, ins7, DL, DR, Ca, 2, GN, SRL, 8) +Oper (Op3458, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 2, GN, SRL, 8) +Oper (Op3460, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 2, GN, SRL, 12) +Oper (Op3468, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 2, GN, SRL, 12) +Oper (Op3470, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 2, GN, SRL, 16) +Oper (Op3478, DoMovea, DW, SearW, ins7, DL, DR, Ca, 2, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3480, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 2, GN, SMW, 8) +Oper (Op3488, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 2, GN, SMW, 8) +Oper (Op3490, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 2, GN, SMW, 12) +Oper (Op3498, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 2, GN, SMW, 12) +Oper (Op34a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 2, GN, SMW, 16) +Oper (Op34a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 2, GN, SMW, 16) +Oper (Op34b0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 2, GN, SMW, 20) +Oper (Op34b8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 2, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op34c0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 2, GN, SMW, 8) +Oper (Op34c8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 2, GN, SMW, 8) +Oper (Op34d0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 2, GN, SMW, 12) +Oper (Op34d8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 2, GN, SMW, 12) +Oper (Op34e0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 2, GN, SMW, 16) +Oper (Op34e8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 2, GN, SMW, 16) +Oper (Op34f0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 2, GN, SMW, 20) +Oper (Op34f8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 2, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3500, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 2, GN, SMW, 12) +Oper (Op3508, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 2, GN, SMW, 12) +Oper (Op3510, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 2, GN, SMW, 16) +Oper (Op3518, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 2, GN, SMW, 16) +Oper (Op3520, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 2, GN, SMW, 16) +Oper (Op3528, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 2, GN, SMW, 20) +Oper (Op3530, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 2, GN, SMW, 20) +Oper (Op3538, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 2, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3540, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 2, GN, SMW, 12) +Oper (Op3548, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 2, GN, SMW, 12) +Oper (Op3550, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 2, GN, SMW, 16) +Oper (Op3558, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 2, GN, SMW, 16) +Oper (Op3560, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 2, GN, SMW, 20) +Oper (Op3568, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 2, GN, SMW, 20) +Oper (Op3570, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 2, GN, SMW, 24) +Oper (Op3578, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 2, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3580, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 2, GN, SMW, 16) +Oper (Op3588, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 2, GN, SMW, 16) +Oper (Op3590, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 2, GN, SMW, 20) +Oper (Op3598, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 2, GN, SMW, 20) +Oper (Op35a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 2, GN, SMW, 20) +Oper (Op35a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 2, GN, SMW, 24) +Oper (Op35b0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 2, GN, SMW, 24) +Oper (Op35b8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 2, GN, SMW, (cycles+21)&0xfffffffc) + +Oper (Op3600, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 3, GN, SRW, 4) +Oper (Op3608, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 3, GN, SRW, 4) +Oper (Op3610, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 3, GN, SRW, 8) +Oper (Op3618, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 3, GN, SRW, 8) +Oper (Op3620, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 3, GN, SRW, 12) +Oper (Op3628, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 3, GN, SRW, 12) +Oper (Op3630, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 3, GN, SRW, 16) +Oper (Op3638, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 3, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3640, DoMovea, DW, SdW, ins7, DL, DR, Ca, 3, GN, SRL, 4) +Oper (Op3648, DoMovea, DW, SaW, ins7, DL, DR, Ca, 3, GN, SRL, 4) +Oper (Op3650, DoMovea, DW, SainW, ins7, DL, DR, Ca, 3, GN, SRL, 8) +Oper (Op3658, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 3, GN, SRL, 8) +Oper (Op3660, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 3, GN, SRL, 12) +Oper (Op3668, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 3, GN, SRL, 12) +Oper (Op3670, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 3, GN, SRL, 16) +Oper (Op3678, DoMovea, DW, SearW, ins7, DL, DR, Ca, 3, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3680, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 3, GN, SMW, 8) +Oper (Op3688, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 3, GN, SMW, 8) +Oper (Op3690, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 3, GN, SMW, 12) +Oper (Op3698, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 3, GN, SMW, 12) +Oper (Op36a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 3, GN, SMW, 16) +Oper (Op36a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 3, GN, SMW, 16) +Oper (Op36b0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 3, GN, SMW, 20) +Oper (Op36b8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 3, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op36c0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 3, GN, SMW, 8) +Oper (Op36c8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 3, GN, SMW, 8) +Oper (Op36d0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 3, GN, SMW, 12) +Oper (Op36d8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 3, GN, SMW, 12) +Oper (Op36e0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 3, GN, SMW, 16) +Oper (Op36e8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 3, GN, SMW, 16) +Oper (Op36f0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 3, GN, SMW, 20) +Oper (Op36f8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 3, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3700, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 3, GN, SMW, 12) +Oper (Op3708, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 3, GN, SMW, 12) +Oper (Op3710, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 3, GN, SMW, 16) +Oper (Op3718, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 3, GN, SMW, 16) +Oper (Op3720, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 3, GN, SMW, 16) +Oper (Op3728, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 3, GN, SMW, 20) +Oper (Op3730, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 3, GN, SMW, 20) +Oper (Op3738, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 3, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3740, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 3, GN, SMW, 12) +Oper (Op3748, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 3, GN, SMW, 12) +Oper (Op3750, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 3, GN, SMW, 16) +Oper (Op3758, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 3, GN, SMW, 16) +Oper (Op3760, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 3, GN, SMW, 20) +Oper (Op3768, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 3, GN, SMW, 20) +Oper (Op3770, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 3, GN, SMW, 24) +Oper (Op3778, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 3, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3780, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 3, GN, SMW, 16) +Oper (Op3788, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 3, GN, SMW, 16) +Oper (Op3790, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 3, GN, SMW, 20) +Oper (Op3798, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 3, GN, SMW, 20) +Oper (Op37a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 3, GN, SMW, 20) +Oper (Op37a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 3, GN, SMW, 24) +Oper (Op37b0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 3, GN, SMW, 24) +Oper (Op37b8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 3, GN, SMW, (cycles+21)&0xfffffffc) + +Oper (Op3800, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 4, GN, SRW, 4) +Oper (Op3808, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 4, GN, SRW, 4) +Oper (Op3810, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 4, GN, SRW, 8) +Oper (Op3818, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 4, GN, SRW, 8) +Oper (Op3820, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 4, GN, SRW, 12) +Oper (Op3828, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 4, GN, SRW, 12) +Oper (Op3830, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 4, GN, SRW, 16) +Oper (Op3838, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 4, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3840, DoMovea, DW, SdW, ins7, DL, DR, Ca, 4, GN, SRL, 4) +Oper (Op3848, DoMovea, DW, SaW, ins7, DL, DR, Ca, 4, GN, SRL, 4) +Oper (Op3850, DoMovea, DW, SainW, ins7, DL, DR, Ca, 4, GN, SRL, 8) +Oper (Op3858, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 4, GN, SRL, 8) +Oper (Op3860, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 4, GN, SRL, 12) +Oper (Op3868, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 4, GN, SRL, 12) +Oper (Op3870, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 4, GN, SRL, 16) +Oper (Op3878, DoMovea, DW, SearW, ins7, DL, DR, Ca, 4, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3880, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 4, GN, SMW, 8) +Oper (Op3888, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 4, GN, SMW, 8) +Oper (Op3890, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 4, GN, SMW, 12) +Oper (Op3898, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 4, GN, SMW, 12) +Oper (Op38a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 4, GN, SMW, 16) +Oper (Op38a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 4, GN, SMW, 16) +Oper (Op38b0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 4, GN, SMW, 20) +Oper (Op38b8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 4, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op38c0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 4, GN, SMW, 8) +Oper (Op38c8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 4, GN, SMW, 8) +Oper (Op38d0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 4, GN, SMW, 12) +Oper (Op38d8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 4, GN, SMW, 12) +Oper (Op38e0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 4, GN, SMW, 16) +Oper (Op38e8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 4, GN, SMW, 16) +Oper (Op38f0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 4, GN, SMW, 20) +Oper (Op38f8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 4, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3900, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 4, GN, SMW, 12) +Oper (Op3908, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 4, GN, SMW, 12) +Oper (Op3910, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 4, GN, SMW, 16) +Oper (Op3918, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 4, GN, SMW, 16) +Oper (Op3920, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 4, GN, SMW, 16) +Oper (Op3928, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 4, GN, SMW, 20) +Oper (Op3930, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 4, GN, SMW, 20) +Oper (Op3938, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 4, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3940, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 4, GN, SMW, 12) +Oper (Op3948, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 4, GN, SMW, 12) +Oper (Op3950, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 4, GN, SMW, 16) +Oper (Op3958, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 4, GN, SMW, 16) +Oper (Op3960, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 4, GN, SMW, 20) +Oper (Op3968, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 4, GN, SMW, 20) +Oper (Op3970, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 4, GN, SMW, 24) +Oper (Op3978, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 4, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3980, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 4, GN, SMW, 16) +Oper (Op3988, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 4, GN, SMW, 16) +Oper (Op3990, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 4, GN, SMW, 20) +Oper (Op3998, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 4, GN, SMW, 20) +Oper (Op39a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 4, GN, SMW, 20) +Oper (Op39a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 4, GN, SMW, 24) +Oper (Op39b0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 4, GN, SMW, 24) +Oper (Op39b8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 4, GN, SMW, (cycles+21)&0xfffffffc) + +Oper (Op3a00, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 5, GN, SRW, 4) +Oper (Op3a08, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 5, GN, SRW, 4) +Oper (Op3a10, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 5, GN, SRW, 8) +Oper (Op3a18, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 5, GN, SRW, 8) +Oper (Op3a20, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 5, GN, SRW, 12) +Oper (Op3a28, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 5, GN, SRW, 12) +Oper (Op3a30, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 5, GN, SRW, 16) +Oper (Op3a38, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 5, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3a40, DoMovea, DW, SdW, ins7, DL, DR, Ca, 5, GN, SRL, 4) +Oper (Op3a48, DoMovea, DW, SaW, ins7, DL, DR, Ca, 5, GN, SRL, 4) +Oper (Op3a50, DoMovea, DW, SainW, ins7, DL, DR, Ca, 5, GN, SRL, 8) +Oper (Op3a58, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 5, GN, SRL, 8) +Oper (Op3a60, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 5, GN, SRL, 12) +Oper (Op3a68, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 5, GN, SRL, 12) +Oper (Op3a70, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 5, GN, SRL, 16) +Oper (Op3a78, DoMovea, DW, SearW, ins7, DL, DR, Ca, 5, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3a80, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 5, GN, SMW, 8) +Oper (Op3a88, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 5, GN, SMW, 8) +Oper (Op3a90, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 5, GN, SMW, 12) +Oper (Op3a98, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 5, GN, SMW, 12) +Oper (Op3aa0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 5, GN, SMW, 16) +Oper (Op3aa8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 5, GN, SMW, 16) +Oper (Op3ab0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 5, GN, SMW, 20) +Oper (Op3ab8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 5, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3ac0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 5, GN, SMW, 8) +Oper (Op3ac8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 5, GN, SMW, 8) +Oper (Op3ad0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 5, GN, SMW, 12) +Oper (Op3ad8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 5, GN, SMW, 12) +Oper (Op3ae0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 5, GN, SMW, 16) +Oper (Op3ae8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 5, GN, SMW, 16) +Oper (Op3af0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 5, GN, SMW, 20) +Oper (Op3af8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 5, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3b00, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 5, GN, SMW, 12) +Oper (Op3b08, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 5, GN, SMW, 12) +Oper (Op3b10, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 5, GN, SMW, 16) +Oper (Op3b18, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 5, GN, SMW, 16) +Oper (Op3b20, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 5, GN, SMW, 16) +Oper (Op3b28, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 5, GN, SMW, 20) +Oper (Op3b30, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 5, GN, SMW, 20) +Oper (Op3b38, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 5, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3b40, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 5, GN, SMW, 12) +Oper (Op3b48, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 5, GN, SMW, 12) +Oper (Op3b50, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 5, GN, SMW, 16) +Oper (Op3b58, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 5, GN, SMW, 16) +Oper (Op3b60, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 5, GN, SMW, 20) +Oper (Op3b68, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 5, GN, SMW, 20) +Oper (Op3b70, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 5, GN, SMW, 24) +Oper (Op3b78, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 5, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3b80, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 5, GN, SMW, 16) +Oper (Op3b88, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 5, GN, SMW, 16) +Oper (Op3b90, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 5, GN, SMW, 20) +Oper (Op3b98, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 5, GN, SMW, 20) +Oper (Op3ba0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 5, GN, SMW, 20) +Oper (Op3ba8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 5, GN, SMW, 24) +Oper (Op3bb0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 5, GN, SMW, 24) +Oper (Op3bb8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 5, GN, SMW, (cycles+21)&0xfffffffc) + +Oper (Op3c00, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 6, GN, SRW, 4) +Oper (Op3c08, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 6, GN, SRW, 4) +Oper (Op3c10, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 6, GN, SRW, 8) +Oper (Op3c18, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 6, GN, SRW, 8) +Oper (Op3c20, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 6, GN, SRW, 12) +Oper (Op3c28, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 6, GN, SRW, 12) +Oper (Op3c30, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 6, GN, SRW, 16) +Oper (Op3c38, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 6, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3c40, DoMovea, DW, SdW, ins7, DL, DR, Ca, 6, GN, SRL, 4) +Oper (Op3c48, DoMovea, DW, SaW, ins7, DL, DR, Ca, 6, GN, SRL, 4) +Oper (Op3c50, DoMovea, DW, SainW, ins7, DL, DR, Ca, 6, GN, SRL, 8) +Oper (Op3c58, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 6, GN, SRL, 8) +Oper (Op3c60, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 6, GN, SRL, 12) +Oper (Op3c68, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 6, GN, SRL, 12) +Oper (Op3c70, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 6, GN, SRL, 16) +Oper (Op3c78, DoMovea, DW, SearW, ins7, DL, DR, Ca, 6, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3c80, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 6, GN, SMW, 8) +Oper (Op3c88, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 6, GN, SMW, 8) +Oper (Op3c90, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 6, GN, SMW, 12) +Oper (Op3c98, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 6, GN, SMW, 12) +Oper (Op3ca0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 6, GN, SMW, 16) +Oper (Op3ca8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 6, GN, SMW, 16) +Oper (Op3cb0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 6, GN, SMW, 20) +Oper (Op3cb8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 6, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3cc0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 6, GN, SMW, 8) +Oper (Op3cc8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 6, GN, SMW, 8) +Oper (Op3cd0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 6, GN, SMW, 12) +Oper (Op3cd8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 6, GN, SMW, 12) +Oper (Op3ce0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 6, GN, SMW, 16) +Oper (Op3ce8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 6, GN, SMW, 16) +Oper (Op3cf0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 6, GN, SMW, 20) +Oper (Op3cf8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 6, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3d00, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 6, GN, SMW, 12) +Oper (Op3d08, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 6, GN, SMW, 12) +Oper (Op3d10, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 6, GN, SMW, 16) +Oper (Op3d18, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 6, GN, SMW, 16) +Oper (Op3d20, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 6, GN, SMW, 16) +Oper (Op3d28, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 6, GN, SMW, 20) +Oper (Op3d30, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 6, GN, SMW, 20) +Oper (Op3d38, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 6, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3d40, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 6, GN, SMW, 12) +Oper (Op3d48, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 6, GN, SMW, 12) +Oper (Op3d50, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 6, GN, SMW, 16) +Oper (Op3d58, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 6, GN, SMW, 16) +Oper (Op3d60, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 6, GN, SMW, 20) +Oper (Op3d68, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 6, GN, SMW, 20) +Oper (Op3d70, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 6, GN, SMW, 24) +Oper (Op3d78, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 6, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3d80, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 6, GN, SMW, 16) +Oper (Op3d88, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 6, GN, SMW, 16) +Oper (Op3d90, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 6, GN, SMW, 20) +Oper (Op3d98, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 6, GN, SMW, 20) +Oper (Op3da0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 6, GN, SMW, 20) +Oper (Op3da8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 6, GN, SMW, 24) +Oper (Op3db0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 6, GN, SMW, 24) +Oper (Op3db8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 6, GN, SMW, (cycles+21)&0xfffffffc) + +Oper (Op3e00, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 7, GN, SRW, 4) +Oper (Op3e08, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 7, GN, SRW, 4) +Oper (Op3e10, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 7, GN, SRW, 8) +Oper (Op3e18, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 7, GN, SRW, 8) +Oper (Op3e20, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 7, GN, SRW, 12) +Oper (Op3e28, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 7, GN, SRW, 12) +Oper (Op3e30, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 7, GN, SRW, 16) +Oper (Op3e38, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 7, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3e40, DoMovea, DW, SdW, ins7, DL, DR, Ca, 7, GN, SRL, 4) +Oper (Op3e48, DoMovea, DW, SaW, ins7, DL, DR, Ca, 7, GN, SRL, 4) +Oper (Op3e50, DoMovea, DW, SainW, ins7, DL, DR, Ca, 7, GN, SRL, 8) +Oper (Op3e58, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 7, GN, SRL, 8) +Oper (Op3e60, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 7, GN, SRL, 12) +Oper (Op3e68, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 7, GN, SRL, 12) +Oper (Op3e70, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 7, GN, SRL, 16) +Oper (Op3e78, DoMovea, DW, SearW, ins7, DL, DR, Ca, 7, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3e80, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 7, GN, SMW, 8) +Oper (Op3e88, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 7, GN, SMW, 8) +Oper (Op3e90, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 7, GN, SMW, 12) +Oper (Op3e98, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 7, GN, SMW, 12) +Oper (Op3ea0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 7, GN, SMW, 16) +Oper (Op3ea8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 7, GN, SMW, 16) +Oper (Op3eb0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 7, GN, SMW, 20) +Oper (Op3eb8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 7, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3ec0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 7, GN, SMW, 8) +Oper (Op3ec8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 7, GN, SMW, 8) +Oper (Op3ed0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 7, GN, SMW, 12) +Oper (Op3ed8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 7, GN, SMW, 12) +Oper (Op3ee0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 7, GN, SMW, 16) +Oper (Op3ee8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 7, GN, SMW, 16) +Oper (Op3ef0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 7, GN, SMW, 20) +Oper (Op3ef8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 7, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3f00, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 7, GN, SMW, 12) +Oper (Op3f08, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 7, GN, SMW, 12) +Oper (Op3f10, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 7, GN, SMW, 16) +Oper (Op3f18, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 7, GN, SMW, 16) +Oper (Op3f20, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 7, GN, SMW, 16) +Oper (Op3f28, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 7, GN, SMW, 20) +Oper (Op3f30, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 7, GN, SMW, 20) +Oper (Op3f38, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 7, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3f40, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 7, GN, SMW, 12) +Oper (Op3f48, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 7, GN, SMW, 12) +Oper (Op3f50, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 7, GN, SMW, 16) +Oper (Op3f58, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 7, GN, SMW, 16) +Oper (Op3f60, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 7, GN, SMW, 20) +Oper (Op3f68, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 7, GN, SMW, 20) +Oper (Op3f70, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 7, GN, SMW, 24) +Oper (Op3f78, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 7, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3f80, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 7, GN, SMW, 16) +Oper (Op3f88, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 7, GN, SMW, 16) +Oper (Op3f90, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 7, GN, SMW, 20) +Oper (Op3f98, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 7, GN, SMW, 20) +Oper (Op3fa0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 7, GN, SMW, 20) +Oper (Op3fa8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 7, GN, SMW, 24) +Oper (Op3fb0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 7, GN, SMW, 24) +Oper (Op3fb8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 7, GN, SMW, (cycles+21)&0xfffffffc) + +Oper (Op7000, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 0, GN, SRL, 4) +Oper (Op7200, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 1, GN, SRL, 4) +Oper (Op7400, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 2, GN, SRL, 4) +Oper (Op7600, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 3, GN, SRL, 4) +Oper (Op7800, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 4, GN, SRL, 4) +Oper (Op7a00, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 5, GN, SRL, 4) +Oper (Op7c00, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 6, GN, SRL, 4) +Oper (Op7e00, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 7, GN, SRL, 4) diff --git a/MCUME_esp32/espcastaway/main/68korig/op68kshift.cpp b/MCUME_esp32/espcastaway/main/68korig/op68kshift.cpp new file mode 100755 index 0000000..1b03f12 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/op68kshift.cpp @@ -0,0 +1,864 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - 68k shift instructions +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 22.06.2002 JH V-flag after ASL was broken in some special cases. +* 09.07.2002 JH ROXL/ROXR: X-flag not modified when shift count is 0. +* 10.07.2002 JH other shift ops: X-flag not modified when shift count is 0. +* 10.09.2002 JH Bugfix: ROXL.L +* 15.09.2002 JH Minor SR/Bcc/Scc optimization. Fixed V-Flag for ASL.L. +* Wrapped 68k operand types in typedefs. +* 01.10.2002 JH Bugfix: -(Ax) and (Ax)+ addressing modes were swapped. +* *** Many thx to olivencia@wanado.fr for finding this!! *** +* 02.10.2002 JH SetV simplified for ASL. +*/ +#ifndef PROTOH +static char sccsid[] = "$Id: op68kshift.c,v 1.10 2002/10/05 08:25:08 jhoenig Exp $"; +#include "68000.h" +#include "op68k.h" + +#define addcycles cycles+=source<<1; + +#define DoAslB(target,source) \ + source&=0x3f; \ + addcycles \ + if (source> 0) {\ + register uint32 cvnz=0;\ + register uint32 tgt=target< 0) {\ + register uint32 cvnz=0;\ + register uint32 tgt=target<0) {\ + register uint32 cvnz=0;\ + register uint32 tgt=target<<(source-1);\ + if (tgt&0x80000000) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\ + tgt<<=1;\ + if ((((uint32)target)>>31)!=(tgt>>31)) cvnz+=Vflag;\ + target=tgt;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ + } else {\ + ClrCVSetNZ(target);\ +} + +#define DoAsr(target,source) \ + source&=0x3f; \ + addcycles \ + if (source>0) {\ + register uint32 cvnz=0;\ + target >>= source - 1;\ + if (target & 0x1) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\ + target >>= 1;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ + } else {\ + ClrCVSetNZ(target);\ +} + +#define DoAsrB(target,source) DoAsr(target,source) +#define DoAsrW(target,source) DoAsr(target,source) +#define DoAsrL(target,source) DoAsr(target,source) + +#define DoLslB(target,source) \ + source&=0x3f; \ + addcycles \ + if (source>0) {\ + register uint32 cvnz=0;\ + register uint32 tgt=target<0) {\ + register uint32 cvnz=0;\ + register uint32 tgt=target< 0) {\ + register uint32 cvnz=0;\ + target <<= source - 1;\ + if (target & 0x80000000) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\ + target <<= 1;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ + } else {\ + ClrCVSetNZ(target);\ + } + +#define DoLsr(target,source,type) \ + source&=0x3f; \ + addcycles \ + if (source> 0) {\ + register uint32 cvnz=0;\ + if (target&(1<<(source-1))) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\ + target=((type)target)>>source;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ + } else {\ + ClrCVSetNZ(target);\ + } + +#define DoLsrB(target,source) DoLsr(target,source,uint8) +#define DoLsrW(target,source) DoLsr(target,source,uint16) +#define DoLsrL(target,source) DoLsr(target,source,uint32) + + +#define DoRoxlB(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + SetC(GetX());\ + } else {\ + register uint16 tgt1, tgt2;\ + source %= 9;\ + tgt1 = (uint8) target;\ + tgt1 |= (uint16) (GetX()) << 8;\ + tgt2 = tgt1;\ + tgt2 >>= (9 - source);\ + tgt1 <<= source;\ + tgt1 |= tgt2;\ + SetXC ((tgt1 >> 8) & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRoxlW(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + SetC(GetX());\ + } else {\ + register uint32 tgt1, tgt2;\ + source %= 17;\ + tgt1 = (uint16) target;\ + tgt1 |= (uint32) (GetX()) << 16;\ + tgt2 = tgt1;\ + tgt2 >>= (17 - source);\ + tgt1 <<= source;\ + tgt1 |= tgt2;\ + SetXC ((tgt1 >> 16) & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRoxlL(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + SetC(GetX());\ + } else {\ + register uint32 tgt1, tgt2;\ + source %= 33;\ + tgt2 = tgt1 = (uint32) target;\ + if (source != 0) {\ + tgt1 <<= 1;\ + tgt1 |= (uint32) (GetX());\ + tgt1 <<= (source - 1);\ + tgt2 >>= (32 - source);\ + SetXC (tgt2 & 0x1);\ + tgt2 >>= 1;\ + tgt1 |= tgt2;\ + target = tgt1;\ + }\ + }\ + SetNZ (target);\ +} + +#define DoRoxrB(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + SetC(GetX());\ + } else {\ + register uint16 tgt1, tgt2;\ + source %= 9;\ + tgt1 = (uint8) target;\ + tgt1 |= (uint16) (GetX()) << 8;\ + tgt2 = tgt1;\ + tgt2 <<= (9 - source);\ + tgt1 >>= source;\ + tgt1 |= tgt2;\ + SetXC ((tgt1 >> 8) & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRoxrW(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + SetC(GetX());\ + } else {\ + register uint32 tgt1, tgt2;\ + source %= 17;\ + tgt1 = (uint16) target;\ + tgt1 |= (uint32) (GetX()) << 16;\ + tgt2 = tgt1;\ + tgt2 <<= (17 - source);\ + tgt1 >>= source;\ + tgt1 |= tgt2;\ + SetXC ((tgt1 >> 16) & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRoxrL(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + SetC(GetX());\ + } else {\ + register uint32 tgt1, tgt2;\ + source %= 33;\ + tgt2 = tgt1 = (uint32) target;\ + if (source != 0) {\ + tgt2 <<= 1;\ + tgt2 |= (uint32) (GetX());\ + tgt2 <<= (32 - source);\ + tgt1 >>= (source - 1);\ + SetXC (tgt1 & 0x1);\ + tgt1 >>= 1;\ + tgt1 |= tgt2;\ + target = tgt1;\ + }\ + }\ + SetNZ (target);\ +} + +#define DoRolB(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + ForceC (0);\ + } else {\ + register uint8 tgt1, tgt2;\ + source &= 0x7;\ + tgt2 = tgt1 = target;\ + tgt2 >>= (8 - source);\ + tgt1 <<= source;\ + tgt1 |= tgt2;\ + SetC (tgt1 & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRolW(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + ForceC (0);\ + } else {\ + register uint16 tgt1, tgt2;\ + source &= 0xf;\ + tgt2 = tgt1 = target;\ + tgt2 >>= (16 - source);\ + tgt1 <<= source;\ + tgt1 |= tgt2;\ + SetC (tgt1 & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRolL(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + ForceC (0);\ + } else {\ + register uint32 tgt1, tgt2;\ + source &= 0x1f;\ + tgt2 = tgt1 = (uint32) target;\ + tgt2 >>= (32 - source);\ + tgt1 <<= source;\ + tgt1 |= tgt2;\ + SetC (tgt1 & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRorB(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + ForceC (0);\ + } else {\ + register uint8 tgt1, tgt2;\ + source &= 0x7;\ + tgt2 = tgt1 = target;\ + tgt2 <<= (8 - source);\ + tgt1 >>= source;\ + tgt1 |= tgt2;\ + SetC ((tgt1 >> 7) & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRorW(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + ForceC (0);\ + } else {\ + register uint16 tgt1, tgt2;\ + source &= 0xf;\ + tgt2 = tgt1 = target;\ + tgt2 <<= (16 - source);\ + tgt1 >>= source;\ + tgt1 |= tgt2;\ + SetC ((tgt1 >> 15) & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRorL(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + ForceC (0);\ + } else {\ + register uint32 tgt1, tgt2;\ + source &= 0x1f;\ + tgt2 = tgt1 = target;\ + tgt2 <<= (32 - source);\ + tgt1 >>= source;\ + tgt1 |= tgt2;\ + SetC ((tgt1 >> 31) & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#endif + +Oper (Ope000, DoAsrB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope008, DoLsrB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope010, DoRoxrB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope018, DoRorB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope020, DoAsrB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope028, DoLsrB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope030, DoRoxrB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope038, DoRorB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope040, DoAsrW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope048, DoLsrW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope050, DoRoxrW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope058, DoRorW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope060, DoAsrW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope068, DoLsrW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope070, DoRoxrW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope078, DoRorW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope080, DoAsrL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope088, DoLsrL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope090, DoRoxrL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope098, DoRorL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope0a0, DoAsrL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope0a8, DoLsrL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope0b0, DoRoxrL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope0b8, DoRorL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope100, DoAslB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope108, DoLslB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope110, DoRoxlB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope118, DoRolB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope120, DoAslB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope128, DoLslB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope130, DoRoxlB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope138, DoRolB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope140, DoAslW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope148, DoLslW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope150, DoRoxlW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope158, DoRolW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope160, DoAslW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope168, DoLslW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope170, DoRoxlW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope178, DoRolW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope180, DoAslL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope188, DoLslL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope190, DoRoxlL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope198, DoRolL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope1a0, DoAslL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope1a8, DoLslL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope1b0, DoRoxlL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope1b8, DoRolL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope200, DoAsrB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope208, DoLsrB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope210, DoRoxrB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope218, DoRorB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope220, DoAsrB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope228, DoLsrB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope230, DoRoxrB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope238, DoRorB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope240, DoAsrW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope248, DoLsrW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope250, DoRoxrW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope258, DoRorW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope260, DoAsrW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope268, DoLsrW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope270, DoRoxrW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope278, DoRorW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope280, DoAsrL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope288, DoLsrL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope290, DoRoxrL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope298, DoRorL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope2a0, DoAsrL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope2a8, DoLsrL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope2b0, DoRoxrL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope2b8, DoRorL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope300, DoAslB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope308, DoLslB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope310, DoRoxlB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope318, DoRolB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope320, DoAslB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope328, DoLslB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope330, DoRoxlB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope338, DoRolB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope340, DoAslW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope348, DoLslW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope350, DoRoxlW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope358, DoRolW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope360, DoAslW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope368, DoLslW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope370, DoRoxlW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope378, DoRolW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope380, DoAslL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope388, DoLslL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope390, DoRoxlL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope398, DoRolL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope3a0, DoAslL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope3a8, DoLslL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope3b0, DoRoxlL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope3b8, DoRolL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope400, DoAsrB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope408, DoLsrB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope410, DoRoxrB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope418, DoRorB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope420, DoAsrB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope428, DoLsrB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope430, DoRoxrB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope438, DoRorB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope440, DoAsrW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope448, DoLsrW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope450, DoRoxrW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope458, DoRorW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope460, DoAsrW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope468, DoLsrW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope470, DoRoxrW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope478, DoRorW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope480, DoAsrL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope488, DoLsrL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope490, DoRoxrL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope498, DoRorL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope4a0, DoAsrL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope4a8, DoLsrL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope4b0, DoRoxrL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope4b8, DoRorL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope500, DoAslB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope508, DoLslB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope510, DoRoxlB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope518, DoRolB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope520, DoAslB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope528, DoLslB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope530, DoRoxlB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope538, DoRolB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope540, DoAslW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope548, DoLslW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope550, DoRoxlW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope558, DoRolW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope560, DoAslW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope568, DoLslW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope570, DoRoxlW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope578, DoRolW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope580, DoAslL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope588, DoLslL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope590, DoRoxlL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope598, DoRolL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope5a0, DoAslL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope5a8, DoLslL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope5b0, DoRoxlL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope5b8, DoRolL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope600, DoAsrB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope608, DoLsrB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope610, DoRoxrB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope618, DoRorB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope620, DoAsrB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope628, DoLsrB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope630, DoRoxrB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope638, DoRorB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope640, DoAsrW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope648, DoLsrW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope650, DoRoxrW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope658, DoRorW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope660, DoAsrW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope668, DoLsrW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope670, DoRoxrW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope678, DoRorW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope680, DoAsrL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope688, DoLsrL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope690, DoRoxrL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope698, DoRorL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope6a0, DoAsrL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope6a8, DoLsrL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope6b0, DoRoxrL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope6b8, DoRorL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope700, DoAslB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope708, DoLslB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope710, DoRoxlB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope718, DoRolB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope720, DoAslB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope728, DoLslB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope730, DoRoxlB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope738, DoRolB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope740, DoAslW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope748, DoLslW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope750, DoRoxlW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope758, DoRolW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope760, DoAslW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope768, DoLslW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope770, DoRoxlW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope778, DoRolW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope780, DoAslL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope788, DoLslL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope790, DoRoxlL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope798, DoRolL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope7a0, DoAslL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope7a8, DoLslL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope7b0, DoRoxlL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope7b8, DoRolL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope800, DoAsrB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope808, DoLsrB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope810, DoRoxrB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope818, DoRorB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope820, DoAsrB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope828, DoLsrB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope830, DoRoxrB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope838, DoRorB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope840, DoAsrW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope848, DoLsrW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope850, DoRoxrW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope858, DoRorW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope860, DoAsrW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope868, DoLsrW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope870, DoRoxrW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope878, DoRorW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope880, DoAsrL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope888, DoLsrL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope890, DoRoxrL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope898, DoRorL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope8a0, DoAsrL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope8a8, DoLsrL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope8b0, DoRoxrL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope8b8, DoRorL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope900, DoAslB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope908, DoLslB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope910, DoRoxlB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope918, DoRolB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope920, DoAslB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope928, DoLslB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope930, DoRoxlB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope938, DoRolB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope940, DoAslW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope948, DoLslW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope950, DoRoxlW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope958, DoRolW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope960, DoAslW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope968, DoLslW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope970, DoRoxlW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope978, DoRolW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope980, DoAslL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope988, DoLslL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope990, DoRoxlL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope998, DoRolL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope9a0, DoAslL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope9a8, DoLslL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope9b0, DoRoxlL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope9b8, DoRolL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Opea00, DoAsrB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea08, DoLsrB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea10, DoRoxrB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea18, DoRorB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea20, DoAsrB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea28, DoLsrB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea30, DoRoxrB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea38, DoRorB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea40, DoAsrW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea48, DoLsrW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea50, DoRoxrW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea58, DoRorW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea60, DoAsrW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea68, DoLsrW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea70, DoRoxrW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea78, DoRorW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea80, DoAsrL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opea88, DoLsrL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opea90, DoRoxrL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opea98, DoRorL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeaa0, DoAsrL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeaa8, DoLsrL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeab0, DoRoxrL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeab8, DoRorL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Opeb00, DoAslB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb08, DoLslB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb10, DoRoxlB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb18, DoRolB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb20, DoAslB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb28, DoLslB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb30, DoRoxlB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb38, DoRolB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb40, DoAslW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb48, DoLslW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb50, DoRoxlW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb58, DoRolW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb60, DoAslW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb68, DoLslW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb70, DoRoxlW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb78, DoRolW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb80, DoAslL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeb88, DoLslL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeb90, DoRoxlL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeb98, DoRolL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeba0, DoAslL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeba8, DoLslL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opebb0, DoRoxlL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opebb8, DoRolL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Opec00, DoAsrB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec08, DoLsrB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec10, DoRoxrB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec18, DoRorB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec20, DoAsrB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec28, DoLsrB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec30, DoRoxrB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec38, DoRorB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec40, DoAsrW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec48, DoLsrW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec50, DoRoxrW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec58, DoRorW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec60, DoAsrW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec68, DoLsrW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec70, DoRoxrW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec78, DoRorW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec80, DoAsrL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opec88, DoLsrL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opec90, DoRoxrL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opec98, DoRorL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeca0, DoAsrL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeca8, DoLsrL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opecb0, DoRoxrL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opecb8, DoRorL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Oped00, DoAslB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped08, DoLslB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped10, DoRoxlB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped18, DoRolB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped20, DoAslB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped28, DoLslB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped30, DoRoxlB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped38, DoRolB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped40, DoAslW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped48, DoLslW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped50, DoRoxlW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped58, DoRolW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped60, DoAslW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped68, DoLslW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped70, DoRoxlW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped78, DoRolW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped80, DoAslL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Oped88, DoLslL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Oped90, DoRoxlL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Oped98, DoRolL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeda0, DoAslL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeda8, DoLslL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opedb0, DoRoxlL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opedb8, DoRolL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Opee00, DoAsrB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee08, DoLsrB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee10, DoRoxrB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee18, DoRorB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee20, DoAsrB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee28, DoLsrB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee30, DoRoxrB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee38, DoRorB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee40, DoAsrW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee48, DoLsrW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee50, DoRoxrW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee58, DoRorW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee60, DoAsrW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee68, DoLsrW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee70, DoRoxrW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee78, DoRorW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee80, DoAsrL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opee88, DoLsrL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opee90, DoRoxrL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opee98, DoRorL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeea0, DoAsrL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeea8, DoLsrL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeeb0, DoRoxrL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeeb8, DoRorL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Opef00, DoAslB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef08, DoLslB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef10, DoRoxlB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef18, DoRolB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef20, DoAslB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef28, DoLslB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef30, DoRoxlB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef38, DoRolB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef40, DoAslW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef48, DoLslW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef50, DoRoxlW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef58, DoRolW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef60, DoAslW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef68, DoLslW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef70, DoRoxlW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef78, DoRolW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef80, DoAslL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opef88, DoLslL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opef90, DoRoxlL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opef98, DoRolL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opefa0, DoAslL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opefa8, DoLslL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opefb0, DoRoxlL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opefb8, DoRolL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope0d0, DoAsrW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope0d8, DoAsrW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope0e0, DoAsrW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope0e8, DoAsrW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope0f0, DoAsrW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope0f8, DoAsrW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + +Oper (Ope1d0, DoAslW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope1d8, DoAslW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope1e0, DoAslW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope1e8, DoAslW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope1f0, DoAslW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope1f8, DoAslW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + +Oper (Ope2d0, DoLsrW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope2d8, DoLsrW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope2e0, DoLsrW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope2e8, DoLsrW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope2f0, DoLsrW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope2f8, DoLsrW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + +Oper (Ope3d0, DoLslW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope3d8, DoLslW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope3e0, DoLslW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope3e8, DoLslW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope3f0, DoLslW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope3f8, DoLslW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + +Oper (Ope4d0, DoRoxrW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope4d8, DoRoxrW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope4e0, DoRoxrW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope4e8, DoRoxrW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope4f0, DoRoxrW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope4f8, DoRoxrW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + +Oper (Ope5d0, DoRoxlW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope5d8, DoRoxlW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope5e0, DoRoxlW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope5e8, DoRoxlW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope5f0, DoRoxlW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope5f8, DoRoxlW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + +Oper (Ope6d0, DoRorW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope6d8, DoRorW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope6e0, DoRorW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope6e8, DoRorW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope6f0, DoRorW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope6f8, DoRorW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + +Oper (Ope7d0, DoRolW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope7d8, DoRolW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope7e0, DoRolW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope7e8, DoRolW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope7f0, DoRolW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope7f8, DoRolW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + diff --git a/MCUME_esp32/espcastaway/main/68korig/op68ksub.cpp b/MCUME_esp32/espcastaway/main/68korig/op68ksub.cpp new file mode 100755 index 0000000..0154772 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/op68ksub.cpp @@ -0,0 +1,810 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - 68k subtract instructions +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 10.07.2002 JH Fixed Z-Flag for SUBX +* 08.10.2002 JH Fixed Z-Flag for ADD.B 0x80+0x80 and Add.W 0x8000+0x8000. +*/ +#ifndef PROTOH +static char sccsid[] = "$Id: op68ksub.c,v 1.3 2002/10/08 00:18:02 jhoenig Exp $"; +#include "68000.h" +#include "op68k.h" + +/* +* Opfuncs. +*/ + +#define DoSubB(target,source) \ +{register int32 tgt, cvnz=0;\ + tgt = target - source;\ + if ((uint32) source > (uint32) target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\ + target = tgt;\ + if (tgt!=target) cvnz+=Vflag;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoSubW(target,source) \ +{register int32 tgt, cvnz=0;\ + tgt = target - source;\ + if ((uint32) source > (uint32) target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\ + target = tgt;\ + if (tgt!=target) cvnz+=Vflag;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoSubL(target,source) \ + /* Overflow precondition: source has different sign */\ +{register int32 precon=(target>>31)-(source>>31), cvnz=0;\ + if ((uint32) source > (uint32) target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\ + target -= source;\ + /* target and source now have same sign: overflow! */\ + if (precon && (target>>31)==(source>>31)) cvnz+=Vflag;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoSuba(target,source) target -= source; + +#define DoSubx(target,source) \ + /* Overflow precondition: source has different sign */\ +{register int32 precon=(target>>31)-(source>>31);\ + if (GetX ()) {\ + SetXC ((uint32) source >= (uint32) target);\ + target -= source;\ + target -= 1;\ + } else {\ + SetXC ((uint32) source > (uint32) target);\ + target -= source;\ +}\ + /* target and source now have same sign: overflow! */\ + SetV(precon && (target>>31)==(source>>31));\ + ZeroZ(target!=0);\ +SetN(target < 0);}; +#endif + + +Oper (Op9000, DoSubB, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4) +Oper (Op9010, DoSubB, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Op9018, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Op9020, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Op9028, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Op9030, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SRB, 16) +Oper (Op9038, DoSubB, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9040, DoSubW, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Op9048, DoSubW, DW, SaW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Op9050, DoSubW, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Op9058, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Op9060, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Op9068, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Op9070, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SRW, 16) +Oper (Op9078, DoSubW, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9080, DoSubL, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Op9088, DoSubL, DL, SaL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Op9090, DoSubL, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Op9098, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Op90a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Op90a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Op90b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Op90b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op90c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Op90c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Op90d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 0, GRL, SRL, 12) +Oper (Op90d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 0, GRL, SRL, 12) +Oper (Op90e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Op90e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Op90f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 0, GRL, SRL, 20) +Oper (Op90f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 0, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9100, DoSubx, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4) +Oper (Op9108, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 0, GMB, SMB, 20) +Oper (Op9110, DoSubB, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9118, DoSubB, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9120, DoSubB, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9128, DoSubB, DB, SdB, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9130, DoSubB, DB, SdB, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9138, DoSubB, DB, SdB, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9140, DoSubx, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Op9148, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 0, GMW, SMW, 20) +Oper (Op9150, DoSubW, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9158, DoSubW, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9160, DoSubW, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9168, DoSubW, DW, SdW, 0, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9170, DoSubW, DW, SdW, 0, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9178, DoSubW, DW, SdW, 0, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9180, DoSubx, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Op9188, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 0, GML, SML, 32) +Oper (Op9190, DoSubL, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9198, DoSubL, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op91a0, DoSubL, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op91a8, DoSubL, DL, SdL, 0, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op91b0, DoSubL, DL, SdL, 0, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op91b8, DoSubL, DL, SdL, 0, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op91c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Op91c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Op91d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Op91d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Op91e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Op91e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 0, GRL, SRL, 20) +Oper (Op91f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 0, GRL, SRL, 20) +Oper (Op91f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 0, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op9200, DoSubB, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4) +Oper (Op9210, DoSubB, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Op9218, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Op9220, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Op9228, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Op9230, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SRB, 16) +Oper (Op9238, DoSubB, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9240, DoSubW, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Op9248, DoSubW, DW, SaW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Op9250, DoSubW, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Op9258, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Op9260, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Op9268, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Op9270, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SRW, 16) +Oper (Op9278, DoSubW, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9280, DoSubL, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Op9288, DoSubL, DL, SaL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Op9290, DoSubL, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Op9298, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Op92a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Op92a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Op92b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Op92b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op92c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Op92c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Op92d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 1, GRL, SRL, 12) +Oper (Op92d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 1, GRL, SRL, 12) +Oper (Op92e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Op92e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Op92f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 1, GRL, SRL, 20) +Oper (Op92f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 1, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9300, DoSubx, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4) +Oper (Op9308, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 1, GMB, SMB, 20) +Oper (Op9310, DoSubB, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9318, DoSubB, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9320, DoSubB, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9328, DoSubB, DB, SdB, 1, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9330, DoSubB, DB, SdB, 1, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9338, DoSubB, DB, SdB, 1, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9340, DoSubx, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Op9348, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 1, GMW, SMW, 20) +Oper (Op9350, DoSubW, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9358, DoSubW, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9360, DoSubW, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9368, DoSubW, DW, SdW, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9370, DoSubW, DW, SdW, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9378, DoSubW, DW, SdW, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9380, DoSubx, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Op9388, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 1, GML, SML, 32) +Oper (Op9390, DoSubL, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9398, DoSubL, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op93a0, DoSubL, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op93a8, DoSubL, DL, SdL, 1, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op93b0, DoSubL, DL, SdL, 1, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op93b8, DoSubL, DL, SdL, 1, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op93c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Op93c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Op93d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Op93d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Op93e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Op93e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 1, GRL, SRL, 20) +Oper (Op93f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 1, GRL, SRL, 20) +Oper (Op93f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 1, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op9400, DoSubB, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4) +Oper (Op9410, DoSubB, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Op9418, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Op9420, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Op9428, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Op9430, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SRB, 16) +Oper (Op9438, DoSubB, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9440, DoSubW, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Op9448, DoSubW, DW, SaW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Op9450, DoSubW, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Op9458, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Op9460, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Op9468, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Op9470, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SRW, 16) +Oper (Op9478, DoSubW, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9480, DoSubL, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Op9488, DoSubL, DL, SaL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Op9490, DoSubL, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Op9498, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Op94a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Op94a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Op94b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Op94b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op94c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Op94c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Op94d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 2, GRL, SRL, 12) +Oper (Op94d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 2, GRL, SRL, 12) +Oper (Op94e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Op94e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Op94f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 2, GRL, SRL, 20) +Oper (Op94f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 2, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9500, DoSubx, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4) +Oper (Op9508, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 2, GMB, SMB, 20) +Oper (Op9510, DoSubB, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9518, DoSubB, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9520, DoSubB, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9528, DoSubB, DB, SdB, 2, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9530, DoSubB, DB, SdB, 2, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9538, DoSubB, DB, SdB, 2, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9540, DoSubx, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Op9548, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 2, GMW, SMW, 20) +Oper (Op9550, DoSubW, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9558, DoSubW, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9560, DoSubW, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9568, DoSubW, DW, SdW, 2, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9570, DoSubW, DW, SdW, 2, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9578, DoSubW, DW, SdW, 2, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9580, DoSubx, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Op9588, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 2, GML, SML, 32) +Oper (Op9590, DoSubL, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9598, DoSubL, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op95a0, DoSubL, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op95a8, DoSubL, DL, SdL, 2, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op95b0, DoSubL, DL, SdL, 2, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op95b8, DoSubL, DL, SdL, 2, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op95c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Op95c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Op95d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Op95d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Op95e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Op95e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 2, GRL, SRL, 20) +Oper (Op95f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 2, GRL, SRL, 20) +Oper (Op95f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 2, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op9600, DoSubB, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4) +Oper (Op9610, DoSubB, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Op9618, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Op9620, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Op9628, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Op9630, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SRB, 16) +Oper (Op9638, DoSubB, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9640, DoSubW, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Op9648, DoSubW, DW, SaW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Op9650, DoSubW, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Op9658, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Op9660, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Op9668, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Op9670, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SRW, 16) +Oper (Op9678, DoSubW, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9680, DoSubL, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Op9688, DoSubL, DL, SaL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Op9690, DoSubL, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Op9698, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Op96a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Op96a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Op96b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Op96b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op96c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Op96c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Op96d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 3, GRL, SRL, 12) +Oper (Op96d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 3, GRL, SRL, 12) +Oper (Op96e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Op96e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Op96f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 3, GRL, SRL, 20) +Oper (Op96f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 3, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9700, DoSubx, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4) +Oper (Op9708, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 3, GMB, SMB, 20) +Oper (Op9710, DoSubB, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9718, DoSubB, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9720, DoSubB, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9728, DoSubB, DB, SdB, 3, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9730, DoSubB, DB, SdB, 3, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9738, DoSubB, DB, SdB, 3, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9740, DoSubx, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Op9748, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 3, GMW, SMW, 20) +Oper (Op9750, DoSubW, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9758, DoSubW, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9760, DoSubW, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9768, DoSubW, DW, SdW, 3, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9770, DoSubW, DW, SdW, 3, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9778, DoSubW, DW, SdW, 3, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9780, DoSubx, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Op9788, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 3, GML, SML, 32) +Oper (Op9790, DoSubL, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9798, DoSubL, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op97a0, DoSubL, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op97a8, DoSubL, DL, SdL, 3, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op97b0, DoSubL, DL, SdL, 3, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op97b8, DoSubL, DL, SdL, 3, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op97c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Op97c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Op97d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Op97d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Op97e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Op97e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 3, GRL, SRL, 20) +Oper (Op97f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 3, GRL, SRL, 20) +Oper (Op97f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 3, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op9800, DoSubB, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4) +Oper (Op9810, DoSubB, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Op9818, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Op9820, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Op9828, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Op9830, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SRB, 16) +Oper (Op9838, DoSubB, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9840, DoSubW, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Op9848, DoSubW, DW, SaW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Op9850, DoSubW, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Op9858, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Op9860, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Op9868, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Op9870, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SRW, 16) +Oper (Op9878, DoSubW, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9880, DoSubL, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Op9888, DoSubL, DL, SaL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Op9890, DoSubL, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Op9898, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Op98a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Op98a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Op98b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Op98b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op98c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Op98c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Op98d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 4, GRL, SRL, 12) +Oper (Op98d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 4, GRL, SRL, 12) +Oper (Op98e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Op98e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Op98f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 4, GRL, SRL, 20) +Oper (Op98f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 4, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9900, DoSubx, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4) +Oper (Op9908, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 4, GMB, SMB, 20) +Oper (Op9910, DoSubB, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9918, DoSubB, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9920, DoSubB, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9928, DoSubB, DB, SdB, 4, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9930, DoSubB, DB, SdB, 4, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9938, DoSubB, DB, SdB, 4, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9940, DoSubx, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Op9948, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 4, GMW, SMW, 20) +Oper (Op9950, DoSubW, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9958, DoSubW, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9960, DoSubW, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9968, DoSubW, DW, SdW, 4, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9970, DoSubW, DW, SdW, 4, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9978, DoSubW, DW, SdW, 4, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9980, DoSubx, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Op9988, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 4, GML, SML, 32) +Oper (Op9990, DoSubL, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9998, DoSubL, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op99a0, DoSubL, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op99a8, DoSubL, DL, SdL, 4, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op99b0, DoSubL, DL, SdL, 4, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op99b8, DoSubL, DL, SdL, 4, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op99c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Op99c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Op99d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Op99d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Op99e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Op99e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 4, GRL, SRL, 20) +Oper (Op99f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 4, GRL, SRL, 20) +Oper (Op99f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 4, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op9a00, DoSubB, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4) +Oper (Op9a10, DoSubB, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Op9a18, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Op9a20, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Op9a28, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Op9a30, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SRB, 16) +Oper (Op9a38, DoSubB, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9a40, DoSubW, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Op9a48, DoSubW, DW, SaW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Op9a50, DoSubW, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Op9a58, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Op9a60, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Op9a68, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Op9a70, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SRW, 16) +Oper (Op9a78, DoSubW, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9a80, DoSubL, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Op9a88, DoSubL, DL, SaL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Op9a90, DoSubL, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Op9a98, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Op9aa0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Op9aa8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Op9ab0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Op9ab8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op9ac0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Op9ac8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Op9ad0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 5, GRL, SRL, 12) +Oper (Op9ad8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 5, GRL, SRL, 12) +Oper (Op9ae0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Op9ae8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Op9af0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 5, GRL, SRL, 20) +Oper (Op9af8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 5, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9b00, DoSubx, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4) +Oper (Op9b08, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 5, GMB, SMB, 20) +Oper (Op9b10, DoSubB, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9b18, DoSubB, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9b20, DoSubB, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9b28, DoSubB, DB, SdB, 5, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9b30, DoSubB, DB, SdB, 5, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9b38, DoSubB, DB, SdB, 5, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9b40, DoSubx, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Op9b48, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 5, GMW, SMW, 20) +Oper (Op9b50, DoSubW, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9b58, DoSubW, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9b60, DoSubW, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9b68, DoSubW, DW, SdW, 5, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9b70, DoSubW, DW, SdW, 5, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9b78, DoSubW, DW, SdW, 5, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9b80, DoSubx, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Op9b88, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 5, GML, SML, 32) +Oper (Op9b90, DoSubL, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9b98, DoSubL, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op9ba0, DoSubL, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op9ba8, DoSubL, DL, SdL, 5, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op9bb0, DoSubL, DL, SdL, 5, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op9bb8, DoSubL, DL, SdL, 5, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op9bc0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Op9bc8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Op9bd0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Op9bd8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Op9be0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Op9be8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 5, GRL, SRL, 20) +Oper (Op9bf0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 5, GRL, SRL, 20) +Oper (Op9bf8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 5, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op9c00, DoSubB, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4) +Oper (Op9c10, DoSubB, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Op9c18, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Op9c20, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Op9c28, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Op9c30, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SRB, 16) +Oper (Op9c38, DoSubB, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9c40, DoSubW, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Op9c48, DoSubW, DW, SaW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Op9c50, DoSubW, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Op9c58, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Op9c60, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Op9c68, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Op9c70, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SRW, 16) +Oper (Op9c78, DoSubW, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9c80, DoSubL, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Op9c88, DoSubL, DL, SaL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Op9c90, DoSubL, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Op9c98, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Op9ca0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Op9ca8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Op9cb0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Op9cb8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op9cc0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Op9cc8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Op9cd0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 6, GRL, SRL, 12) +Oper (Op9cd8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 6, GRL, SRL, 12) +Oper (Op9ce0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Op9ce8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Op9cf0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 6, GRL, SRL, 20) +Oper (Op9cf8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 6, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9d00, DoSubx, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4) +Oper (Op9d08, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 6, GMB, SMB, 20) +Oper (Op9d10, DoSubB, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9d18, DoSubB, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9d20, DoSubB, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9d28, DoSubB, DB, SdB, 6, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9d30, DoSubB, DB, SdB, 6, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9d38, DoSubB, DB, SdB, 6, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9d40, DoSubx, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Op9d48, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 6, GMW, SMW, 20) +Oper (Op9d50, DoSubW, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9d58, DoSubW, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9d60, DoSubW, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9d68, DoSubW, DW, SdW, 6, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9d70, DoSubW, DW, SdW, 6, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9d78, DoSubW, DW, SdW, 6, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9d80, DoSubx, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Op9d88, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 6, GML, SML, 32) +Oper (Op9d90, DoSubL, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9d98, DoSubL, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op9da0, DoSubL, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op9da8, DoSubL, DL, SdL, 6, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op9db0, DoSubL, DL, SdL, 6, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op9db8, DoSubL, DL, SdL, 6, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op9dc0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Op9dc8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Op9dd0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Op9dd8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Op9de0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Op9de8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 6, GRL, SRL, 20) +Oper (Op9df0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 6, GRL, SRL, 20) +Oper (Op9df8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 6, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op9e00, DoSubB, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4) +Oper (Op9e10, DoSubB, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Op9e18, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Op9e20, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Op9e28, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Op9e30, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SRB, 16) +Oper (Op9e38, DoSubB, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9e40, DoSubW, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Op9e48, DoSubW, DW, SaW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Op9e50, DoSubW, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Op9e58, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Op9e60, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Op9e68, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Op9e70, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SRW, 16) +Oper (Op9e78, DoSubW, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9e80, DoSubL, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Op9e88, DoSubL, DL, SaL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Op9e90, DoSubL, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Op9e98, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Op9ea0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Op9ea8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Op9eb0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Op9eb8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op9ec0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Op9ec8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Op9ed0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 7, GRL, SRL, 12) +Oper (Op9ed8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 7, GRL, SRL, 12) +Oper (Op9ee0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Op9ee8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Op9ef0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 7, GRL, SRL, 20) +Oper (Op9ef8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 7, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9f00, DoSubx, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4) +Oper (Op9f08, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB15, 7, GMB, SMB, 20) +Oper (Op9f10, DoSubB, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9f18, DoSubB, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9f20, DoSubB, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9f28, DoSubB, DB, SdB, 7, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9f30, DoSubB, DB, SdB, 7, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9f38, DoSubB, DB, SdB, 7, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9f40, DoSubx, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Op9f48, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 7, GMW, SMW, 20) +Oper (Op9f50, DoSubW, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9f58, DoSubW, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9f60, DoSubW, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9f68, DoSubW, DW, SdW, 7, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9f70, DoSubW, DW, SdW, 7, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9f78, DoSubW, DW, SdW, 7, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9f80, DoSubx, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Op9f88, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 7, GML, SML, 32) +Oper (Op9f90, DoSubL, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9f98, DoSubL, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op9fa0, DoSubL, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op9fa8, DoSubL, DL, SdL, 7, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op9fb0, DoSubL, DL, SdL, 7, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op9fb8, DoSubL, DL, SdL, 7, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op9fc0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Op9fc8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Op9fd0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Op9fd8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Op9fe0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Op9fe8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 7, GRL, SRL, 20) +Oper (Op9ff0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 7, GRL, SRL, 20) +Oper (Op9ff8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 7, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op0400, DoSubB, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8) +Oper (Op0410, DoSubB, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op0418, DoSubB, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op0420, DoSubB, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op0428, DoSubB, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op0430, DoSubB, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +Oper (Op0438, DoSubB, DB, SimmB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+23)&0xfffffffc) +Oper (Op0440, DoSubW, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8) +Oper (Op0450, DoSubW, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16) +Oper (Op0458, DoSubW, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16) +Oper (Op0460, DoSubW, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20) +Oper (Op0468, DoSubW, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20) +Oper (Op0470, DoSubW, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24) +Oper (Op0478, DoSubW, DW, SimmW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+23)&0xfffffffc) +Oper (Op0480, DoSubL, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16) +Oper (Op0490, DoSubL, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28) +Oper (Op0498, DoSubL, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28) +Oper (Op04a0, DoSubL, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32) +Oper (Op04a8, DoSubL, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32) +Oper (Op04b0, DoSubL, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36) +Oper (Op04b8, DoSubL, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc) + +Oper (Op5100, DoSubB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5110, DoSubB, DB, Ss, 8, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5118, DoSubB, DB, Ss, 8, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5120, DoSubB, DB, Ss, 8, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5128, DoSubB, DB, Ss, 8, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5130, DoSubB, DB, Ss, 8, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5138, DoSubB, DB, Ss, 8, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5140, DoSubW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5148, DoSuba, DL, Ss, 8, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5150, DoSubW, DW, Ss, 8, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5158, DoSubW, DW, Ss, 8, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5160, DoSubW, DW, Ss, 8, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5168, DoSubW, DW, Ss, 8, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5170, DoSubW, DW, Ss, 8, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5178, DoSubW, DW, Ss, 8, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5180, DoSubL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5188, DoSuba, DL, Ss, 8, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5190, DoSubL, DL, Ss, 8, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5198, DoSubL, DL, Ss, 8, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op51a0, DoSubL, DL, Ss, 8, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op51a8, DoSubL, DL, Ss, 8, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op51b0, DoSubL, DL, Ss, 8, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op51b8, DoSubL, DL, Ss, 8, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5300, DoSubB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5310, DoSubB, DB, Ss, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5318, DoSubB, DB, Ss, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5320, DoSubB, DB, Ss, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5328, DoSubB, DB, Ss, 1, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5330, DoSubB, DB, Ss, 1, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5338, DoSubB, DB, Ss, 1, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5340, DoSubW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5348, DoSuba, DL, Ss, 1, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5350, DoSubW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5358, DoSubW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5360, DoSubW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5368, DoSubW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5370, DoSubW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5378, DoSubW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5380, DoSubL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5388, DoSuba, DL, Ss, 1, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5390, DoSubL, DL, Ss, 1, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5398, DoSubL, DL, Ss, 1, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op53a0, DoSubL, DL, Ss, 1, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op53a8, DoSubL, DL, Ss, 1, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op53b0, DoSubL, DL, Ss, 1, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op53b8, DoSubL, DL, Ss, 1, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5500, DoSubB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5510, DoSubB, DB, Ss, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5518, DoSubB, DB, Ss, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5520, DoSubB, DB, Ss, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5528, DoSubB, DB, Ss, 2, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5530, DoSubB, DB, Ss, 2, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5538, DoSubB, DB, Ss, 2, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5540, DoSubW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5548, DoSuba, DL, Ss, 2, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5550, DoSubW, DW, Ss, 2, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5558, DoSubW, DW, Ss, 2, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5560, DoSubW, DW, Ss, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5568, DoSubW, DW, Ss, 2, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5570, DoSubW, DW, Ss, 2, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5578, DoSubW, DW, Ss, 2, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5580, DoSubL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5588, DoSuba, DL, Ss, 2, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5590, DoSubL, DL, Ss, 2, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5598, DoSubL, DL, Ss, 2, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op55a0, DoSubL, DL, Ss, 2, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op55a8, DoSubL, DL, Ss, 2, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op55b0, DoSubL, DL, Ss, 2, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op55b8, DoSubL, DL, Ss, 2, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5700, DoSubB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5710, DoSubB, DB, Ss, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5718, DoSubB, DB, Ss, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5720, DoSubB, DB, Ss, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5728, DoSubB, DB, Ss, 3, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5730, DoSubB, DB, Ss, 3, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5738, DoSubB, DB, Ss, 3, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5740, DoSubW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5748, DoSuba, DL, Ss, 3, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5750, DoSubW, DW, Ss, 3, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5758, DoSubW, DW, Ss, 3, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5760, DoSubW, DW, Ss, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5768, DoSubW, DW, Ss, 3, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5770, DoSubW, DW, Ss, 3, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5778, DoSubW, DW, Ss, 3, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5780, DoSubL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5788, DoSuba, DL, Ss, 3, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5790, DoSubL, DL, Ss, 3, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5798, DoSubL, DL, Ss, 3, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op57a0, DoSubL, DL, Ss, 3, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op57a8, DoSubL, DL, Ss, 3, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op57b0, DoSubL, DL, Ss, 3, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op57b8, DoSubL, DL, Ss, 3, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5900, DoSubB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5910, DoSubB, DB, Ss, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5918, DoSubB, DB, Ss, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5920, DoSubB, DB, Ss, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5928, DoSubB, DB, Ss, 4, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5930, DoSubB, DB, Ss, 4, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5938, DoSubB, DB, Ss, 4, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5940, DoSubW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5948, DoSuba, DL, Ss, 4, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5950, DoSubW, DW, Ss, 4, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5958, DoSubW, DW, Ss, 4, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5960, DoSubW, DW, Ss, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5968, DoSubW, DW, Ss, 4, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5970, DoSubW, DW, Ss, 4, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5978, DoSubW, DW, Ss, 4, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5980, DoSubL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5988, DoSuba, DL, Ss, 4, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5990, DoSubL, DL, Ss, 4, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5998, DoSubL, DL, Ss, 4, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op59a0, DoSubL, DL, Ss, 4, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op59a8, DoSubL, DL, Ss, 4, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op59b0, DoSubL, DL, Ss, 4, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op59b8, DoSubL, DL, Ss, 4, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5b00, DoSubB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5b10, DoSubB, DB, Ss, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5b18, DoSubB, DB, Ss, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5b20, DoSubB, DB, Ss, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5b28, DoSubB, DB, Ss, 5, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5b30, DoSubB, DB, Ss, 5, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5b38, DoSubB, DB, Ss, 5, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5b40, DoSubW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5b48, DoSuba, DL, Ss, 5, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5b50, DoSubW, DW, Ss, 5, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5b58, DoSubW, DW, Ss, 5, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5b60, DoSubW, DW, Ss, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5b68, DoSubW, DW, Ss, 5, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5b70, DoSubW, DW, Ss, 5, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5b78, DoSubW, DW, Ss, 5, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5b80, DoSubL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5b88, DoSuba, DL, Ss, 5, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5b90, DoSubL, DL, Ss, 5, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5b98, DoSubL, DL, Ss, 5, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op5ba0, DoSubL, DL, Ss, 5, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op5ba8, DoSubL, DL, Ss, 5, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op5bb0, DoSubL, DL, Ss, 5, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op5bb8, DoSubL, DL, Ss, 5, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5d00, DoSubB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5d10, DoSubB, DB, Ss, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5d18, DoSubB, DB, Ss, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5d20, DoSubB, DB, Ss, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5d28, DoSubB, DB, Ss, 6, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5d30, DoSubB, DB, Ss, 6, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5d38, DoSubB, DB, Ss, 6, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5d40, DoSubW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5d48, DoSuba, DL, Ss, 6, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5d50, DoSubW, DW, Ss, 6, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5d58, DoSubW, DW, Ss, 6, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5d60, DoSubW, DW, Ss, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5d68, DoSubW, DW, Ss, 6, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5d70, DoSubW, DW, Ss, 6, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5d78, DoSubW, DW, Ss, 6, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5d80, DoSubL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5d88, DoSuba, DL, Ss, 6, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5d90, DoSubL, DL, Ss, 6, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5d98, DoSubL, DL, Ss, 6, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op5da0, DoSubL, DL, Ss, 6, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op5da8, DoSubL, DL, Ss, 6, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op5db0, DoSubL, DL, Ss, 6, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op5db8, DoSubL, DL, Ss, 6, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5f00, DoSubB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5f10, DoSubB, DB, Ss, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5f18, DoSubB, DB, Ss, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5f20, DoSubB, DB, Ss, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5f28, DoSubB, DB, Ss, 7, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5f30, DoSubB, DB, Ss, 7, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5f38, DoSubB, DB, Ss, 7, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5f40, DoSubW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5f48, DoSuba, DL, Ss, 7, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5f50, DoSubW, DW, Ss, 7, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5f58, DoSubW, DW, Ss, 7, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5f60, DoSubW, DW, Ss, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5f68, DoSubW, DW, Ss, 7, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5f70, DoSubW, DW, Ss, 7, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5f78, DoSubW, DW, Ss, 7, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5f80, DoSubL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5f88, DoSuba, DL, Ss, 7, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5f90, DoSubL, DL, Ss, 7, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5f98, DoSubL, DL, Ss, 7, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op5fa0, DoSubL, DL, Ss, 7, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op5fa8, DoSubL, DL, Ss, 7, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op5fb0, DoSubL, DL, Ss, 7, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op5fb8, DoSubL, DL, Ss, 7, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) diff --git a/MCUME_esp32/espcastaway/main/68korig/operin.h b/MCUME_esp32/espcastaway/main/68korig/operin.h new file mode 100755 index 0000000..8fe87c2 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/operin.h @@ -0,0 +1 @@ +#define operin unsigned long *reg diff --git a/MCUME_esp32/espcastaway/main/68korig/proto.h b/MCUME_esp32/espcastaway/main/68korig/proto.h new file mode 100755 index 0000000..afc3d3d --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korig/proto.h @@ -0,0 +1,99 @@ +/* + * proto.h - FAST 68000 emulator instruction prototypes + * Version 1.0 + * Copyright (C) 1994, 1995 Joachim Hönig + * (hoenig@informatik.uni-erlangen.de) + * + * This file is part of FAST, the Fine Atari ST Emulator. + * + * FAST is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * FAST is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with FAST; see the file COPYING. If not, write to + * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Prototypes of all 68000 opcodes defined in op68k*.c + */ + +#include "operin.h" + +#undef Oper +#define Oper(a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12) \ + extern unsigned long a1(operin); + +#define PROTOH + +#include "op68kadd.cpp" +#include "op68karith.cpp" +#include "op68ksub.cpp" +#include "op68klogop.cpp" +#include "op68kmisc.cpp" +#include "op68kmove.cpp" +#include "op68kshift.cpp" + +extern unsigned long Op4840(operin); /* SWAP */ +extern unsigned long Op4848(operin); /* BKPT */ +extern unsigned long Op4880(operin); /* EXT.W */ +extern unsigned long Op4890(operin); /* MOVEM.W to (ax) */ +extern unsigned long Op48a0(operin); /* MOVEM.W to -(ax) */ +extern unsigned long Op48a8(operin); /* MOVEM.W to d(ax) */ +extern unsigned long Op48b0(operin); /* MOVEM.W to d(ax,rx) */ +extern unsigned long Op48b8(operin); /* MOVEM.W to w l */ +extern unsigned long Op48c0(operin); /* EXT.L */ +extern unsigned long Op48d0(operin); /* MOVEM.L to (ax) */ +extern unsigned long Op48e0(operin); /* MOVEM.L to -(ax) */ +extern unsigned long Op48e8(operin); /* MOVEM.L to d(ax) */ +extern unsigned long Op48f0(operin); /* MOVEM.L to d(ax,rx) */ +extern unsigned long Op48f8(operin); /* MOVEM.L to w l */ +extern unsigned long Op4c90(operin); /* MOVEM.W from (ax) */ +extern unsigned long Op4c98(operin); /* MOVEM.W from (ax)+ */ +extern unsigned long Op4ca8(operin); /* MOVEM.W from d(ax) */ +extern unsigned long Op4cb0(operin); /* MOVEM.W from d(ax,rx) */ +extern unsigned long Op4cb8(operin); /* MOVEM.W from ea */ +extern unsigned long Op4cd0(operin); /* MOVEM.L from (ax) */ +extern unsigned long Op4cd8(operin); /* MOVEM.L from (ax)+ */ +extern unsigned long Op4ce8(operin); /* MOVEM.L from d(ax) */ +extern unsigned long Op4cf0(operin); /* MOVEM.L from d(ax,rx) */ +extern unsigned long Op4cf8(operin); /* MOVEM.L from ea */ +extern unsigned long Op4e40(operin); /* TRAP */ +extern unsigned long Op4e50(operin); /* LINK */ +extern unsigned long Op4e58(operin); /* UNLK */ +extern unsigned long Op4e60(operin); /* MOVE ax,usp */ +extern unsigned long Op4e68(operin); /* MOVE usp,ax */ +extern unsigned long Op4e70(operin); /* RESET, NOP, STOP, RTE, + * RTD, RTS, TRAPV, RTR */ +extern unsigned long Op4e78(operin); /* MOVEC */ + +extern unsigned long Opc140(operin); /* EXG */ +extern unsigned long Opc148(operin); /* EXG */ +extern unsigned long Opc188(operin); /* EXG */ +extern unsigned long Opc340(operin); /* EXG */ +extern unsigned long Opc348(operin); /* EXG */ +extern unsigned long Opc388(operin); /* EXG */ +extern unsigned long Opc540(operin); /* EXG */ +extern unsigned long Opc548(operin); /* EXG */ +extern unsigned long Opc588(operin); /* EXG */ +extern unsigned long Opc740(operin); /* EXG */ +extern unsigned long Opc748(operin); /* EXG */ +extern unsigned long Opc788(operin); /* EXG */ +extern unsigned long Opc940(operin); /* EXG */ +extern unsigned long Opc948(operin); /* EXG */ +extern unsigned long Opc988(operin); /* EXG */ +extern unsigned long Opcb40(operin); /* EXG */ +extern unsigned long Opcb48(operin); /* EXG */ +extern unsigned long Opcb88(operin); /* EXG */ +extern unsigned long Opcd40(operin); /* EXG */ +extern unsigned long Opcd48(operin); /* EXG */ +extern unsigned long Opcd88(operin); /* EXG */ +extern unsigned long Opcf40(operin); /* EXG */ +extern unsigned long Opcf48(operin); /* EXG */ +extern unsigned long Opcf88(operin); /* EXG */ diff --git a/MCUME_esp32/espcastaway/main/68korigbad/.DS_Store b/MCUME_esp32/espcastaway/main/68korigbad/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..5008ddfcf53c02e82d7eee2e57c38e5672ef89f6 GIT binary patch literal 6148 zcmeH~Jr2S!425mzP>H1@V-^m;4Wg<&0T*E43hX&L&p$$qDprKhvt+--jT7}7np#A3 zem<@ulZcFPQ@L2!n>{z**++&mCkOWA81W14cNZlEfg7;MkzE(HCqgga^y>{tEnwC%0;vJ&^%eQ zLs35+`xjp>T0 ANSI, restructuring +* 09.06.2002 JH Use of mmap for memory access discontinued +* 12.06.2002 JH Correct bus error/address error exception stack frame +* 13.06.2002 JH Merged in Martin's BCD implementation (untested), +* completed jump table. STOP is now the only +* unimplemented instruction. +* 14.06.2002 JH Implemented STOP, shutdown CPU after multiple bus errors. +* Removed inst parameter from CPU opcode functions. +* 19.06.2002 JH CPURun() returns # of executed instructions. +* 20.06.2002 JH added yet another SR implementation variant. +* 02.07.2002 JH Support different CPU types. Removed MOVE CCR, from +* 68000 jump table. +* 20.08.2002 JH Fixed CPU shutdown. +* 27.08.2002 JH Bugfix: S and T flag incorrectly reported for group 0 exceptions +* Implemented additional 68010 registers and instructions. +* 31.08.2002 JH Implemented M68010 exception stack frames. +* 08.10.2002 JH Implemented Trace exception +*/ +static char sccsid[] = "$Id: 68000.c,v 1.18 2002/10/10 19:52:11 jhoenig Exp $"; +#include "config.h" + +#include +#include +#include +#include "68000.h" +#include "mem.h" +#include "st.h" +#include "op68k.h" +#include "proto.h" +#include "operin.h" + + +#if (CPU_TYPE == 68000 || CPU_TYPE == 68008) +#include "op68000.h" +#elif (CPU_TYPE == 68010) // broken +#include "op68010.h" +#endif +extern int disass; +unsigned long reg[23]; +unsigned long dfc, sfc, vbr; +#define biginst reg[18] +#define pc reg[19] +#define usp reg[20] +#define ssp reg[21] +#define recalc_int reg[22] + + +extern void StartDisass(); +unsigned short SaveWordTrc; +unsigned char GetTrc; +unsigned short int0=0; +unsigned long exaddress=0x12345678; +int intmask, intpri; +char cpu_state; +unsigned cpu_type; +volatile unsigned cpu_count; + +jmp_buf trap_buf; + + +unsigned short GetSRB(void) +{ + uint32 cvnz=reg[16]; //-------c-------v-------n-------z + uint32 stx=reg[17]; //---------------s-------t-------x + uint32 sr=(cvnz>>24)+(cvnz>>15)+(cvnz<<2)+(cvnz>>5)+(stx<<4); + return sr&(unsigned short)0xff; +} + +unsigned short GetSRW(void) +{ + uint32 cvnz=reg[16]; //-------c-------v-------n-------z + uint32 stx=reg[17]; //---------------s-------t-------x + uint32 sr=(cvnz>>24)+(cvnz>>15)+(cvnz<<2)+(cvnz>>5)+(stx<<4); + uint32 sr2=(stx<<7)+(stx>>3)+(intmask<<8); + return (sr&(unsigned short)0xff)+(sr2&(unsigned short)0xff00); +} + + +void SetSRB(unsigned long sr) +{ + uint32 cvnz=((sr&1)<<24)+((sr&2)<<15)+((sr&4)>>2)+((sr&8)<<5); + reg[16]=cvnz; + SetX(sr&0x10); +} + +void SetSRW(unsigned long sr) +{ + uint32 cvnz=((sr&1)<<24)+((sr&2)<<15)+((sr&4)>>2)+((sr&8)<<5); + reg[16]=cvnz; + SetX (sr&0x10); + SetI ((sr&0x700)>>8); + SetS (sr&0x2000); + SetT (sr&0x8000); +} + +void ExceptionGroup0( + int number, + unsigned long address, + int ReadWrite) +{ + short sr = GetSRW(), context = 0; +#ifdef DEBUG + ON_TRAP(number); + assert(cpu_state != -3); +#endif + if ((exaddress+1!=address)&&(exaddress+2!=address)&&(exaddress+3!=address)){ + if (cpu_state == 0) { + cpu_state = -3; + longjmp(trap_buf, 1); + } +#if CPU_TYPE == 68000 + else if (cpu_state > 0) { + context |= 0x8; + } + if (ReadWrite) context |= 0x10; +#else + if (ReadWrite) context |= 0x100; +#endif + if (GetS()) context |= 0x4; + if (ReadWrite && address == pc) context |= 0x2; + else context |= 0x1; + cpu_state = 0; /* begin group 0 exception processing */ + SetS (1); + SetT (0); +#if CPU_TYPE == 68010 + reg[15] -= 44; /* Rerun info */ + reg[15] -= 4; SetMemL(reg[15], address); /* fault address */ + reg[15] -= 2; SetMemW(reg[15], context); + reg[15] -= 2; SetMemW(reg[15], 0x8000 | (number * 4)); + reg[15] -= 4; SetMemL(reg[15], GetPC()); + reg[15] -= 2; SetMemW(reg[15], sr); +#else + reg[15] = reg[15] - 14; + SetMemW(reg[15], context); + SetMemL(reg[15] + 2, address); + SetMemW(reg[15] + 6, (uint16)biginst); + SetMemW(reg[15] + 8, sr); + SetMemL(reg[15] + 10, GetPC()); +#endif + + SetPC (GetMemL ((long) number * 4) + vbr); + /* end exception processing */ + cpu_state = -1; + exaddress=address; + + } + int0=1; +} + +void ExceptionGroup1(int number) +{ + + uint32 sp, newpc=pc; + short sr = GetSRW(); + + if (number!=TRAPV) newpc-=2; + SetS(1); + SetT(0); + sp=reg[15]; + sp-=4; SetMemL(sp, newpc); + sp-=2; SetMemW(sp, sr); + reg[15]=sp; + SetPC (GetMemL(number*4+vbr)); + int0=1; +} + +void Interrupt(int number, int level) +{ + uint32 sp; + short sr = GetSRW(); + SetI(level); SetS(1); SetT(0); + sp=reg[15]; + sp-=4; SetMemL(sp, GetPC()); + sp-=2; SetMemW(sp, sr); + reg[15]=sp; + SetPC (GetMemL(number*4+vbr)); +} + +void ExceptionGroup2(int number) +{ + uint32 sp; + short sr = GetSRW(); + SetS(1); SetT(0); + sp=reg[15]; + sp-=4; SetMemL(sp, GetPC()); + sp-=2; SetMemW(sp, sr); + reg[15]=sp; + SetPC (GetMemL(number*4+vbr)); +} + +unsigned long Trace() +{ + uint32 sp; + short sr; + register unsigned long cycleco=0; + register unsigned long address,timeinst; + register int8 *mymembase=membase; + register int8 *myrombase=rombase; + register uint32 myinst; + address = pc&MEMADDRMASK; + // disass=1; + int0=0; + if (address=ROMBASE) myinst=biginst=ReadSL(myrombase+address); + else { ExceptionGroup1(ADDRESSERR); return cycleco; } +#ifdef DISASS + if (disass==1) StoreTrace(); +#endif + pc+=2; + cycleco+=(*jmp_table[(myinst<<16)>>19])(reg); + + if (!int0){ + sr = GetSRW(); + SetS(1); SetT(0); + sp=reg[15]; + sp-=4; SetMemL(sp, GetPC()); + sp-=2; SetMemW(sp, sr); + reg[15]=sp; + SetPC (GetMemL(TRACE*4+vbr)); + return cycleco; + } + return 0; + +} + + +unsigned long IllIns(operin) +{ + ExceptionGroup1(ILLINSTR); + return 0; +} + +unsigned long Line_A(operin) +{ + ExceptionGroup1(LINE_A); + return 0; +} + +unsigned long Line_F(operin) +{ + ExceptionGroup1(LINE_F); + return 0; +} + +unsigned long Stop(void) +{ + if (!GetS()) + ExceptionGroup1(PRIV); + SetSRW(GetMPCW()); + pc += 2; + cpu_state = -2; /* stopped */ + //longjmp(trap_buf, 1); + return 0; +} + +void HWReset(void) +{ + reg[15] = GetMemL (0l); + SetPC(GetMemL (4l)); + SetI(7); + SetT(0); + SetS(1); + cpu_state = -1; /* running */ + cpu_type = CPU_TYPE; +} diff --git a/MCUME_esp32/espcastaway/main/68korigbad/68000.h b/MCUME_esp32/espcastaway/main/68korigbad/68000.h new file mode 100755 index 0000000..730b83e --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/68000.h @@ -0,0 +1,187 @@ +/* + * Castaway + * (C) 1994 - 2002 Martin Doering, Joachim Hoenig + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ +#ifndef _68000H +#define _68000H + +#include "config.h" // wg. define +#include "operin.h" + +/* + * Supported CPU types + * CPU CPU_TYPE + * MC68000 68000 + * MC68008 68000 + * MC68EC000 not supported (yet) + * MC68010 68010 + * MC68020 68020 + * MC68EC020 not supported (yet) + * MC68030 not supported (yet) + * MC68EC030 not supported (yet) + * MC68040 not supported (yet) + * MC68EC040 not supported (yet) + * CPU32 not supported (yet) + */ +#define CPU_TYPE 68000 + +/* + * Exception vector numbers (trap numbers). + */ +#define RESET 0 +#define BUSERR 2 +#define ADDRESSERR 3 +#define ILLINSTR 4 +#define DIVZ 5 +#define TRAPCHK 6 +#define TRAPV 7 +#define PRIV 8 +#define TRACE 9 +#define LINE_A 10 +#define LINE_F 11 +#if CPU_TYPE != 68000 +#define FORMATERR 14 +#endif +#define AUTOINT1 25 +#define AUTOINT2 26 +#define AUTOINT3 27 +#define AUTOINT4 28 +#define AUTOINT5 29 +#define AUTOINT6 30 +#define AUTOINT7 31 +#define TRAP0 32 + 0 +#define TRAP1 32 + 1 +#define TRAP2 32 + 2 +#define TRAP3 32 + 3 +#define TRAP4 32 + 4 +#define TRAP5 32 + 5 +#define TRAP6 32 + 6 +#define TRAP7 32 + 7 +#define TRAP8 32 + 8 +#define TRAP9 32 + 9 +#define TRAP10 32 + 10 +#define TRAP11 32 + 11 +#define TRAP12 32 + 12 +#define TRAP13 32 + 13 +#define TRAP14 32 + 14 +#define TRAP15 32 + 15 + +/* Group 0 exceptions (address error / bus error) */ +extern void ExceptionGroup0( + int number, /* trap number */ + unsigned long address, /* fault address */ + int ReadWrite); /* read = true, write = false */ +/* Group 1 exceptions: illegal instruction, privilege violation, interrupts */ +extern void ExceptionGroup1(int number); +extern void Interrupt(int number, int level); +/* Group 2 exceptions: traps, divide by zero */ +extern void ExceptionGroup2(int number); + +extern void HWReset(void); /* Reset */ +extern unsigned long IllIns(operin); /* Illegal instruction */ +extern unsigned long Line_A(operin); /* Axxx instruction opcode */ +extern unsigned long Line_F(operin); /* Fxxx instruction opcode */ +extern unsigned long Stop(void); /* Stop instruction */ + +extern unsigned char tracemode; //For Trace Switching +extern unsigned short SaveWordTrc; +extern unsigned char GetTrc; + +/* + * CPU Registers + * + * WARNING: + * Never access registers directly from outside the emulator. + * The internal representation of registers may change. + */ +/* Data and address registers are stored in native byte order. + * register numbering: 0=d0, 1=d1, ..., 8=a0, 9=a1, ... 15=a7 */ +extern unsigned long reg[23]; +#define biginst reg[18] +#define pc reg[19] +#define usp reg[20] +#define ssp reg[21] +#define recalc_int reg[22] + + +#define ins7 (biginst & 7) +#define ins15 (biginst & 15) + +/* 68010 registers */ +extern unsigned long dfc, sfc, vbr; +/* 68020 registers */ +extern unsigned long caar, cacr, isp, msp; + +extern int intmask; +extern char cpu_state; /* 0, 1, 2 while processing exceptions, + * -1 executing, -2 stopped, -3 shutdown */ +extern unsigned cpu_type; /* 68000, 68010 */ + +/* + * Interrupts + * + * The state of interrupt lines IPL0-IPL2 is stored in the variable + * intpri. The emulator acknowledges interrupts by calling QueryIRQ(). + * It expects the interrupt vector number to be returned. + * WARNING: + * Never update intpri asynchronously. Use the CPUEvent() function + * to force CPURun() to return before updating intpri. + */ +extern int intpri; +extern int QueryIRQ(int level); /* get interrupt vector number */ + +#define GetS() *(((int8*)reg)+70) +#define GetFC2() GetS() +#define GetFC1() address == pc +#define GetFC0() address != pc +#define GetFC() (((GetFC2() << 1) | GetFC1()) << 1) | GetFC0() + +/* + * memory access jump tables + */ +#define MEMADDRMASK 0x00ffffffl +#define MEMADDRMASKS 0x00fffffel +#define MEMIDXSHIFT 11 +#define MEMADDRSIZE (MEMADDRMASK + 1) +#define MEMTABLESIZE (MEMADDRSIZE >> MEMIDXSHIFT) +#define MEMBANKSIZE (MEMADDRSIZE / MEMTABLESIZE) +#define MEMBANKMASK (MEMBANKSIZE - 1) + +/* Fetch byte from address */ +char GetMemB(unsigned long address); +short GetMemW(unsigned long address); +long GetMemL(unsigned long address); +void SetMemB (unsigned long address, unsigned char value); +void SetMemW(unsigned long address, unsigned short value); +void SetMemL(unsigned long address, unsigned long value); +#ifdef DEBUG +extern int stop_on; +extern int verb_on; +/* go to sleep (gives debugger a chance to attach) */ +void DebugStop(void); +#ifdef TRACEBACK +/* + * execution trace + */ +struct state { + uint32 reg[16]; + uint32 stack[8]; + uint32 pc, usp, ssp; + uint16 inst[5]; + uint16 sr; + +}; +extern int hide_supervisor; +extern unsigned long instcnt; +extern int tbi; +extern struct state traceback[TRACEBACK]; +extern int trace_on; +/* print execution trace of last TRACEBACK instructions and sleep */ +void TraceStop(void); +#endif +#endif +#endif + diff --git a/MCUME_esp32/espcastaway/main/68korigbad/component.mk b/MCUME_esp32/espcastaway/main/68korigbad/component.mk new file mode 100755 index 0000000..5eb32c5 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/component.mk @@ -0,0 +1,19 @@ +# +# Component Makefile +# +# This Makefile can be left empty. By default, it will take the sources in the +# src/ directory, compile them and link them into lib(subdirectory_name).a +# in the build directory. This behaviour is entirely configurable, +# please read the ESP-IDF documents if you need to do this. +# + +COMPONENT_ADD_INCLUDEDIRS := . ../.. +COMPONENT_SRCDIRS := . + +CPPFLAGS += -fpermissive #-O3 -ffast-math +CPPFLAGS += -DNO_SOUND #-DEMULATED_JOYSTICK -DUSE_SHORT_SLICE -DUSE_DOUBLE_BUFFER +CPPFLAGS += -Wno-error=sequence-point -Wno-error=parentheses -Wno-error=maybe-uninitialized -Wno-unused-variable -fno-common -fno-builtin -fno-exceptions -fstrict-aliasing -Wno-narrowing + +#CPPFLAGS += -Wno-error=parentheses -Wno-error=maybe-uninitialized -Wno-error=char-subscripts -Wno-error=attributes +#CPPFLAGS += -fno-common -fno-builtin -fno-exceptions -fstrict-aliasing -Wno-narrowing -Wno-error=maybe-uninitialized -Wno-error=sequence-point -Wno-error=implicit-int -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=implicit-function-declaration -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-error=char-subscripts -Wno-error=attributes + diff --git a/MCUME_esp32/espcastaway/main/68korigbad/debug.cpp b/MCUME_esp32/espcastaway/main/68korigbad/debug.cpp new file mode 100755 index 0000000..5d20270 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/debug.cpp @@ -0,0 +1,1210 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - debugging fns - CAUTION: this file is a mess! +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 09.07.2002 JH Added a disassembler. Traced instructions now +* disassembled. +* 22.08.2002 JH Bugfix: Shift instructions now disassembled correctly +* 29.08.2002 JH Bugfix: MOVEC disassembled correctly. +* 30.08.2002 JH MOVEM register list now disassembled. +*/ +static char sccsid[] = "$Id: debug.c,v 1.9 2002/08/30 22:27:03 jhoenig Exp $"; +#include +#include +#include +#include "config.h" +#include "68000.h" +#include "st.h" +#include "op68k.h" + +#ifdef DISASS +char Msg[400]; +FILE* logfile; +/* +* 680x0 Disassembler functions (experimental) +*/ +int totnbinst=0; +int traceindex=0; + + +char *disass_cc(unsigned char cc) +{ + switch(cc) { + case 0: + return "T "; + case 1: + return "F "; + case 2: + return "HI"; + case 3: + return "LS"; + case 4: + return "CC"; + case 5: + return "CS"; + case 6: + return "NE"; + case 7: + return "EQ"; + case 8: + return "VC"; + case 9: + return "VS"; + case 0xa: + return "PL"; + case 0xb: + return "MI"; + case 0xc: + return "GE"; + case 0xd: + return "LT"; + case 0xe: + return "GT"; + case 0xf: + return "LE"; + default: + return "??"; + } +} + +char *disass_areg(unsigned char spec) +{ + switch (spec) { + case 0: return "A0"; + case 1: return "A1"; + case 2: return "A2"; + case 3: return "A3"; + case 4: return "A4"; + case 5: return "A5"; + case 6: return "A6"; + case 7: return "A7"; + default: return "??"; + } +} + +char *disass_dreg(unsigned char spec) +{ + switch (spec) { + case 0: return "D0"; + case 1: return "D1"; + case 2: return "D2"; + case 3: return "D3"; + case 4: return "D4"; + case 5: return "D5"; + case 6: return "D6"; + case 7: return "D7"; + default: return "??"; + } +} + +char *disass_reg(unsigned char spec) +{ + if (spec >= 8) return disass_areg(spec & 0x7); + else return disass_dreg(spec); +} + +void disass_reglist(char *buf, unsigned short reglist, int predecrement) +{ + int index = 0, len; + *buf = 0; + if (!predecrement) { + while (reglist) { + if (reglist & 0x1) { + strcat(buf, disass_reg(index)); + strcat(buf, "/"); + } + index++; + reglist = reglist >> 1; + } + } else { + while (reglist) { + if (reglist & 0x8000) { + strcat(buf, disass_reg(index)); + strcat(buf, "/"); + } + index++; + reglist = reglist << 1; + } + } + /* remove trailing / */ + len = strlen(buf); + if (len > 0) *(buf + len - 1) = 0; +} + +int disass_count(unsigned char spec) +{ + if (spec == 0) return 8; + else return spec; +} + +/* +* return # of extension words used for addressing +*/ +int disass_displacement(char *buf, unsigned short *inst_stream, char displacement) +{ + if (displacement == 0) { + sprintf(buf, "%04x", inst_stream[1]); + return 1; + } else if (displacement == -1) { + sprintf(buf, "%04x%04x", inst_stream[1], inst_stream[2]); + return 2; + } else { + sprintf(buf, "%02x", displacement); + return 0; + } +} + +/* +* return # of extension words used for addressing +*/ +int disass_ea(char *buf, unsigned short *inst_stream, unsigned char mode, unsigned char spec, unsigned char size) +{ + switch(mode) { + case 0: + strcpy(buf, disass_dreg(spec)); + return 0; + case 1: + strcpy(buf, disass_areg(spec)); + return 0; + case 2: + sprintf(buf, "(%s)", disass_areg(spec)); + return 0; + case 3: + sprintf(buf, "(%s)+", disass_areg(spec)); + return 0; + case 4: + sprintf(buf, "-(%s)", disass_areg(spec)); + return 0; + case 5: + sprintf(buf, "%04x(%s)", inst_stream[1], disass_areg(spec)); + return 1; + case 6: // TODO: 680x0 full extension format + sprintf(buf, "(%02x(%s,%s.%c*%x)", + (char) inst_stream[1], disass_areg(spec), + disass_reg(inst_stream[1] >> 12), + (inst_stream[1] & 0x0800)?'L':'W', + 1 << ((inst_stream[1] & 0x0600) >> 9)); + return 1; + case 7: + switch(spec) { + case 0: + sprintf(buf, "%04x", inst_stream[1]); + return 1; + case 1: + sprintf(buf, "%04x%04x", inst_stream[1], inst_stream[2]); + return 2; + case 2: + sprintf(buf, "%04x(PC)", inst_stream[1]); + return 1; + case 3: // TODO: 680x0 full extension format + sprintf(buf, "(%02x(PC,%s.%c*%x)", + (char) inst_stream[1], + disass_reg(inst_stream[1] >> 12), + (inst_stream[1] & 0x0800)?'L':'W', + 1 << ((inst_stream[1] & 0x0600) >> 9)); + return 1; + case 4: + switch(size) { + case 0: + case 1: + sprintf(buf, "#%04x", inst_stream[1]); + return 1; + case 2: + sprintf(buf, "#%04x%04x", inst_stream[1], inst_stream[2]); + return 2; + case 3: + sprintf(buf, "???"); + return 0; + } + } + } + sprintf (buf, "???"); + return 0; +} + +void disassemble(char *buf, unsigned short *inst_stream) +{ + char src_ea_buf[80]; + char tgt_ea_buf[80]; + unsigned char src_mode = (inst_stream[0] & 0x0038) >> 3; + unsigned char src_spec = (inst_stream[0] & 0x0007); + unsigned char src_size = (inst_stream[0] & 0x00c0) >> 6; + unsigned char tgt_mode = (inst_stream[0] & 0x01c0) >> 6; + unsigned char tgt_spec = (inst_stream[0] & 0x0e00) >> 9; + unsigned char condition = (inst_stream[0] & 0x0f00) >> 8; + int wc; + switch (inst_stream[0] & 0xf000) { + case 0x0000: + // TODO: CAS2, CAS + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0]) { + case 0x003c: + sprintf(buf, "ORI.B #%02x,CCR", (char) inst_stream[1]); + return; + case 0x007c: + sprintf(buf, "ORI.W #%04x,SR", inst_stream[1]); + return; + case 0x013c: + sprintf(buf, "ANDI.B #%02x,CCR", (char) inst_stream[1]); + return; + case 0x017c: + sprintf(buf, "ANDI.W #%04x,SR", inst_stream[1]); + return; + case 0x0a3c: + sprintf(buf, "EORI.B #%02x,CCR", (char) inst_stream[1]); + return; + case 0x0a7c: + sprintf(buf, "EORI.W #%04x,SR", inst_stream[1]); + return; + } + switch (inst_stream[0] & 0x0fc0) { + case 0x0000: + sprintf(buf, "ORI.B #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0040: + sprintf(buf, "ORI.W #%04x,%s", inst_stream[1], src_ea_buf); + return; + case 0x0080: + sprintf(buf, "ORI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf); + return; + case 0x0200: + sprintf(buf, "ANDI.B #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0240: + sprintf(buf, "ANDI.W #%04x,%s", inst_stream[1], src_ea_buf); + return; + case 0x0280: + sprintf(buf, "ANDI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf); + return; + case 0x0400: + sprintf(buf, "SUBI.B #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0440: + sprintf(buf, "SUBI.W #%04x,%s", inst_stream[1], src_ea_buf); + return; + case 0x0480: + sprintf(buf, "SUBI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf); + return; + case 0x0600: + sprintf(buf, "ADDI.B #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0640: + sprintf(buf, "ADDI.W #%04x,%s", inst_stream[1], src_ea_buf); + return; + case 0x0680: + sprintf(buf, "ADDI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf); + return; + case 0x0800: + sprintf(buf, "BTST #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0840: + sprintf(buf, "BCHG #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0880: + sprintf(buf, "BCLR #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x08c0: + sprintf(buf, "BSET #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0a00: + sprintf(buf, "EORI.B #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0a40: + sprintf(buf, "EORI.W #%04x,%s", inst_stream[1], src_ea_buf); + return; + case 0x0a80: + sprintf(buf, "EORI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf); + return; + case 0x0c00: + sprintf(buf, "CMPI.B #%02x,%s", (char) inst_stream[1], src_ea_buf); + return; + case 0x0c40: + sprintf(buf, "CMPI.W #%04x,%s", inst_stream[1], src_ea_buf); + return; + case 0x0c80: + sprintf(buf, "CMPI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf); + return; + case 0x0e00: + switch (inst_stream[1] & 0x0800) { + case 0x0000: sprintf(buf, "MOVES.B %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + case 0x0800: sprintf(buf, "MOVES.B %s,%s", disass_reg((inst_stream[1] >> 12) & 0xf), src_ea_buf); + return; + } + case 0x0e40: + switch (inst_stream[1] & 0x0800) { + case 0x0000: sprintf(buf, "MOVES.W %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + case 0x0800: sprintf(buf, "MOVES.W %s,%s", disass_reg((inst_stream[1] >> 12) & 0xf), src_ea_buf); + return; + } + case 0x0e80: + switch (inst_stream[1] & 0x0800) { + case 0x0000: sprintf(buf, "MOVES.L %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + case 0x0800: sprintf(buf, "MOVES.L %s,%s", disass_reg((inst_stream[1] >> 12) & 0xf), src_ea_buf); + return; + } + case 0x06c0: + switch (inst_stream[0] & 0x0030) { + case 0x0000: sprintf(buf, "RTM %s", disass_reg(inst_stream[0] & 0xf)); + return; + case 0x0030: sprintf(buf, "CALLM %s", src_ea_buf); + return; + } + case 0x00c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 0); + switch (inst_stream[1] & 0x0800) { + case 0x0000: sprintf(buf, "CMP2.B %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + case 0x0800: sprintf(buf, "CHK2.B %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + } + case 0x02c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + switch (inst_stream[1] & 0x0800) { + case 0x0000: sprintf(buf, "CMP2.W %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + case 0x0800: sprintf(buf, "CHK2.W %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + } + case 0x04c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2); + switch (inst_stream[1] & 0x0800) { + case 0x0000: sprintf(buf, "CMP2.L %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + case 0x0800: sprintf(buf, "CHK2.L %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf)); + return; + } + } + if (inst_stream[0] & 0x0100) { + if (src_mode == 1) { + switch (tgt_mode) { + case 0x0100: sprintf(buf, "MOVEP.W #%04x(%s),%s", inst_stream[1], disass_areg(src_spec), disass_dreg(tgt_spec)); + return; + case 0x0140: sprintf(buf, "MOVEP.L #%04x(%s),%s", inst_stream[1], disass_areg(src_spec), disass_dreg(tgt_spec)); + return; + case 0x0180: sprintf(buf, "MOVEP.W %s,#%04x(%s)", disass_dreg(tgt_spec), inst_stream[1], disass_areg(src_spec)); + return; + case 0x01c0: sprintf(buf, "MOVEP.L %s,#%04x(%s)", disass_dreg(tgt_spec), inst_stream[1], disass_areg(src_spec)); + return; + } + } + switch (inst_stream[0] & 0x0030) { + case 0x0000: sprintf(buf, "BTST %s,%s", disass_dreg(tgt_spec), src_ea_buf); + return; + case 0x0010: sprintf(buf, "BCHG %s,%s", disass_dreg(tgt_spec), src_ea_buf); + return; + case 0x0020: sprintf(buf, "BCLR %s,%s", disass_dreg(tgt_spec), src_ea_buf); + return; + case 0x0030: sprintf(buf, "BSET %s,%s", disass_dreg(tgt_spec), src_ea_buf); + return; + } + } + case 0x1000: /* Move Byte */ + wc = disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 0); + disass_ea(tgt_ea_buf, inst_stream + wc, tgt_mode, tgt_spec, 0); + sprintf(buf, "MOVE.B %s,%s", src_ea_buf, tgt_ea_buf); + return; + case 0x2000: /* Move Long */ + wc = disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2); + disass_ea(tgt_ea_buf, inst_stream + wc, tgt_mode, tgt_spec, 2); + sprintf(buf, "MOVE.L %s,%s", src_ea_buf, tgt_ea_buf); + return; + case 0x3000: /* Move Word */ + wc = disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + disass_ea(tgt_ea_buf, inst_stream + wc, tgt_mode, tgt_spec, 1); + sprintf(buf, "MOVE.W %s,%s", src_ea_buf, tgt_ea_buf); + return; + case 0x4000: /* Miscellaneous */ + // TODO: MULU.L, MULS.L, DIVU.L, DIVS.L, EXTB.L + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0xffc0) { + case 0x4000: + sprintf(buf, "NEGX.B %s", src_ea_buf); + return; + case 0x4040: + sprintf(buf, "NEGX.W %s", src_ea_buf); + return; + case 0x4080: + sprintf(buf, "NEGX.L %s", src_ea_buf); + return; + case 0x40c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "MOVE.W SR,%s", src_ea_buf); + return; + case 0x4200: + sprintf(buf, "CLR.B %s", src_ea_buf); + return; + case 0x4240: + sprintf(buf, "CLR.W %s", src_ea_buf); + return; + case 0x4280: + sprintf(buf, "CLR.L %s", src_ea_buf); + return; + case 0x42c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "MOVE.W CCR,%s", src_ea_buf); + return; + case 0x4400: + sprintf(buf, "NEG.B %s", src_ea_buf); + return; + case 0x4440: + sprintf(buf, "NEG.W %s", src_ea_buf); + return; + case 0x4480: + sprintf(buf, "NEG.L %s", src_ea_buf); + return; + case 0x44c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "MOVE.W %s,CCR", src_ea_buf); + return; + case 0x4600: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "NOT.B %s", src_ea_buf); + return; + case 0x4640: + sprintf(buf, "NOT.W %s", src_ea_buf); + return; + case 0x4680: + sprintf(buf, "NOT.L %s", src_ea_buf); + return; + case 0x46c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "MOVE.W %s,SR", src_ea_buf); + return; + case 0x4800: + if (src_mode == 1) { + sprintf(buf, "LINK.L #%04x%04x,%s", + inst_stream[1], inst_stream[2], disass_areg(src_spec)); + } else { + sprintf(buf, "NBCD %s", src_ea_buf); + } + return; + case 0x4840: + if (src_mode == 0) { + sprintf(buf, "SWAP.W %s", disass_dreg(src_spec)); + } else if (src_mode == 1) { + sprintf(buf, "BKPT #%x", src_spec); + } else { + sprintf(buf, "PEA %s", src_ea_buf); + } + return; + case 0x4880: + if (src_mode == 0) { + sprintf(buf, "EXT.W %s", disass_dreg(src_spec)); + } else { + disass_reglist(tgt_ea_buf, inst_stream[1], src_mode == 6); + disass_ea(src_ea_buf, inst_stream + 1, src_mode, src_spec, src_size); + sprintf(buf, "MOVEM.W %s,%s", tgt_ea_buf, src_ea_buf); + } + return; + case 0x48c0: + if (src_mode == 0) { + sprintf(buf, "EXT.L %s", disass_dreg(src_spec)); + } else { + disass_reglist(tgt_ea_buf, inst_stream[1], src_mode == 6); + disass_ea(src_ea_buf, inst_stream + 1, src_mode, src_spec, src_size); + sprintf(buf, "MOVEM.L %s,%s", tgt_ea_buf, src_ea_buf); + } + return; + case 0x4a00: + sprintf(buf, "TST.B %s", src_ea_buf); + return; + case 0x4a40: + sprintf(buf, "TST.W %s", src_ea_buf); + return; + case 0x4a80: + sprintf(buf, "TST.L %s", src_ea_buf); + return; + case 0x4ac0: + switch (inst_stream[0] & 0x003f) { + case 0x003a: + sprintf(buf, "BGND "); + return; + case 0x003c: + sprintf(buf, "ILLEGAL"); + return; + default: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 0); + sprintf(buf, "TAS %s", src_ea_buf); + return; + } + case 0x4c80: + if (src_mode == 0) { + } else { + disass_reglist(tgt_ea_buf, inst_stream[1], src_mode == 6); + disass_ea(src_ea_buf, inst_stream + 1, src_mode, src_spec, src_size); + sprintf(buf, "MOVEM.W %s,%s", src_ea_buf, tgt_ea_buf); + } + return; + case 0x4cc0: + if (src_mode == 0) { + } else { + disass_reglist(tgt_ea_buf, inst_stream[1], src_mode == 6); + disass_ea(src_ea_buf, inst_stream + 1, src_mode, src_spec, 2); + sprintf(buf, "MOVEM.L %s,%s", src_ea_buf, tgt_ea_buf); + } + return; + case 0x4e40: + switch(src_mode) { + case 0: + case 1: + sprintf(buf, "TRAP #%x", inst_stream[0] & 0xf); + return; + case 2: + sprintf(buf, "LINK #%4x,%s", inst_stream[1], disass_areg(src_spec)); + return; + case 3: + sprintf(buf, "UNLK %s", disass_areg(src_spec)); + return; + case 4: + sprintf(buf, "MOVE.L %s,USP", disass_areg(src_spec)); + return; + case 5: + sprintf(buf, "MOVE.L USP,%s", disass_areg(src_spec)); + return; + case 6: + switch(inst_stream[0]) { + case 0x4e70: + sprintf(buf, "RESET "); + return; + case 0x4e71: + sprintf(buf, "NOP "); + return; + case 0x4e72: + sprintf(buf, "STOP "); + return; + case 0x4e73: + sprintf(buf, "RTE "); + return; + case 0x4e74: + sprintf(buf, "RTD "); + return; + case 0x4e75: + sprintf(buf, "RTS "); + return; + case 0x4e76: + sprintf(buf, "TRAPV "); + return; + case 0x4e77: + sprintf(buf, "RTR "); + return; + } + case 7: + switch(inst_stream[0]) { + case 0x4e7a: + sprintf(buf, "MOVEC #%04x,%s", inst_stream[1] & 0xfff, disass_reg(inst_stream[1] >> 12)); + return; + case 0x4e7b: + sprintf(buf, "MOVEC #%s,%04x", disass_reg(inst_stream[1] >> 12), inst_stream[1] & 0xfff); + return; + } + } + sprintf(buf, "??? "); + return; + case 0x4e80: + sprintf(buf, "JSR %s", src_ea_buf); + return; + case 0x4ec0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2); + sprintf(buf, "JMP %s", src_ea_buf); + return; + } + switch (tgt_mode) { + case 4: + sprintf(buf, "CHK.L %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 6: + sprintf(buf, "CHK.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 7: + sprintf(buf, "LEA %s,%s", src_ea_buf, disass_areg(tgt_spec)); + return; + } + case 0x5000: /* ADDQ/SUBQ/Scc/DBcc/TRAPcc */ + // TODO: TRAPcc + wc = disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0x00c0) { + case 0x0000: + if (inst_stream[0] & 0x0100) { + sprintf(buf, "SUBQ.B #%x,%s", disass_count(tgt_spec), src_ea_buf); + } else { + sprintf(buf, "ADDQ.B #%x,%s", disass_count(tgt_spec), src_ea_buf); + } + return; + case 0x0040: + if (inst_stream[0] & 0x0100) { + sprintf(buf, "SUBQ.W #%x,%s", disass_count(tgt_spec), src_ea_buf); + } else { + sprintf(buf, "ADDQ.W #%x,%s", disass_count(tgt_spec), src_ea_buf); + } + return; + case 0x0080: + if (inst_stream[0] & 0x0100) { + sprintf(buf, "SUBQ.L #%x,%s", disass_count(tgt_spec), src_ea_buf); + } else { + sprintf(buf, "ADDQ.L #%x,%s", disass_count(tgt_spec), src_ea_buf); + } + return; + case 0x00c0: + if (src_mode == 1) { + disass_displacement(tgt_ea_buf, inst_stream + wc, 0); + sprintf(buf, "DB%s %s,%s", disass_cc(condition), tgt_ea_buf, disass_dreg(src_spec)); + } else { + sprintf(buf, "S%s %s", disass_cc(condition), src_ea_buf); + } + return; + } + case 0x6000: /* Bcc/BSR/BRA */ + disass_displacement(tgt_ea_buf, inst_stream, inst_stream[0]); + if ((inst_stream[0] & 0xff00) == 0x6000) { + sprintf(buf, "BRA %s", tgt_ea_buf); + } else if ((inst_stream[0] & 0xff00) == 0x6100) { + sprintf(buf, "BSR %s", tgt_ea_buf); + } else { + sprintf(buf, "B%s %s",disass_cc(condition), tgt_ea_buf); + } + return; + case 0x7000: /* MOVEQ */ + sprintf(buf, "MOVEQ.L #%02x,%s", (char) inst_stream[0], disass_dreg(tgt_spec)); + return; + case 0x8000: /* OR/DIV/SBCD */ + // TODO: PACK, UNPK + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0x01c0) { + case 0x0000: + sprintf(buf, "OR.B %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0040: + sprintf(buf, "OR.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0080: + sprintf(buf, "OR.L %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x00c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "DIVU.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0100: + if (src_mode == 0) { + sprintf(buf, "SBCD %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "SBCD -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "OR.B %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0140: + sprintf(buf, "OR.W %s,%s", disass_reg(tgt_spec), src_ea_buf); + return; + case 0x0180: + sprintf(buf, "OR.L %s,%s", disass_reg(tgt_spec), src_ea_buf); + return; + case 0x01c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "DIVS.W %s,%s", src_ea_buf, disass_reg(tgt_spec)); + return; + } + case 0x9000: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0x01c0) { + case 0x0000: + sprintf(buf, "SUB.B %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0040: + sprintf(buf, "SUB.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0080: + sprintf(buf, "SUB.L %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x00c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "SUBA.W %s,%s", src_ea_buf, disass_areg(tgt_spec)); + return; + case 0x0100: + if (src_mode == 0) { + sprintf(buf, "SUBX.B %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "SUBX.B -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "SUB.B %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0140: + if (src_mode == 0) { + sprintf(buf, "SUBX.W %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "SUBX.W -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "SUB.W %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0180: + if (src_mode == 0) { + sprintf(buf, "SUBX.L %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "SUBX.L -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "SUB.L %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x01c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2); + sprintf(buf, "SUBA.L %s,%s", src_ea_buf, disass_areg(tgt_spec)); + return; + } + case 0xb000: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0x01c0) { + case 0x0000: + sprintf(buf, "CMP.B %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0040: + sprintf(buf, "CMP.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0080: + sprintf(buf, "CMP.L %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x00c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "CMPA.W %s,%s", src_ea_buf, disass_areg(tgt_spec)); + return; + case 0x0100: + if (src_mode == 1) { + sprintf(buf, "CMPM.B (%s)+,(%s)+", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "EOR.B %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0140: + if (src_mode == 1) { + sprintf(buf, "CMPM.W (%s)+,(%s)+", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "EOR.W %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0180: + if (src_mode == 1) { + sprintf(buf, "CMPM.L (%s)+,(%s)+", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "EOR.L %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x01c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2); + sprintf(buf, "CMPA.L %s,%s", src_ea_buf, disass_areg(tgt_spec)); + return; + } + case 0xc000: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0x01c0) { + case 0x0000: + sprintf(buf, "AND.B %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0040: + sprintf(buf, "AND.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0080: + sprintf(buf, "AND.L %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x00c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "MULU.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0100: + if (src_mode == 0) { + sprintf(buf, "ABCD %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "ABCD -(%s),-(%s)", disass_areg(src_spec), disass_reg(tgt_spec)); + } else { + sprintf(buf, "AND.B %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0140: + if (src_mode == 0) { + sprintf(buf, "EXG %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "EXG %s,%s", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "AND.W %s,%s", disass_reg(tgt_spec), src_ea_buf); + } + return; + case 0x0180: + if (src_mode == 1) { + sprintf(buf, "EXG %s,%s", disass_dreg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "AND.L %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x01c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "MULS.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + } + case 0xd000: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0x01c0) { + case 0x0000: + sprintf(buf, "ADD.B %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0040: + sprintf(buf, "ADD.W %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x0080: + sprintf(buf, "ADD.L %s,%s", src_ea_buf, disass_dreg(tgt_spec)); + return; + case 0x00c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1); + sprintf(buf, "ADDA.W %s,%s", src_ea_buf, disass_areg(tgt_spec)); + return; + case 0x0100: + if (src_mode == 0) { + sprintf(buf, "ADDX.B %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 0x0008) { + sprintf(buf, "ADDX.B -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "ADD.B %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0140: + if (src_mode == 0) { + sprintf(buf, "ADDX.W %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "ADDX.W -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "ADD.W %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x0180: + if (src_mode == 0) { + sprintf(buf, "ADDX.L %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec)); + } else if (src_mode == 1) { + sprintf(buf, "ADDX.L -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec)); + } else { + sprintf(buf, "ADD.L %s,%s", disass_dreg(tgt_spec), src_ea_buf); + } + return; + case 0x01c0: + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2); + sprintf(buf, "ADDA.L %s,%s", src_ea_buf, disass_areg(tgt_spec)); + return; + } + case 0xe000: + // TODO: BFTST, BFEXTU, BFCHG, BFEXTS, BFCLR, BFFFO, BFSET, BFINS + disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size); + switch (inst_stream[0] & 0x07c0) { + case 0x00c0: + sprintf(buf, "ASR.B #1,%s", src_ea_buf); + return; + case 0x01c0: + sprintf(buf, "ASL.B #1,%s", src_ea_buf); + return; + case 0x02c0: + sprintf(buf, "LSR.B #1,%s", src_ea_buf); + return; + case 0x03c0: + sprintf(buf, "LSL.B #1,%s", src_ea_buf); + return; + case 0x04c0: + sprintf(buf, "ROXR.B #1,%s", src_ea_buf); + return; + case 0x05c0: + sprintf(buf, "ROXL.B #1,%s", src_ea_buf); + return; + case 0x06c0: + sprintf(buf, "ROR.B #1,%s", src_ea_buf); + return; + case 0x07c0: + sprintf(buf, "ROL.B #1,%s", src_ea_buf); + return; + } + switch (inst_stream[0] & 0x01f8) { + case 0x0000: + sprintf(buf, "ASR.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0008: + sprintf(buf, "LSR.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0010: + sprintf(buf, "ROXR.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0018: + sprintf(buf, "ROR.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0020: + sprintf(buf, "ASR.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0028: + sprintf(buf, "LSR.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0030: + sprintf(buf, "ROXR.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0038: + sprintf(buf, "ROR.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0040: + sprintf(buf, "ASR.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0048: + sprintf(buf, "LSR.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0050: + sprintf(buf, "ROXR.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0058: + sprintf(buf, "ROR.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0060: + sprintf(buf, "ASR.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0068: + sprintf(buf, "LSR.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0070: + sprintf(buf, "ROXR.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0078: + sprintf(buf, "ROR.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0080: + sprintf(buf, "ASR.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0088: + sprintf(buf, "LSR.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0090: + sprintf(buf, "ROXR.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0098: + sprintf(buf, "ROR.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x00a0: + sprintf(buf, "ASR.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x00a8: + sprintf(buf, "LSR.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x00b0: + sprintf(buf, "ROXR.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x00b8: + sprintf(buf, "ROR.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0100: + sprintf(buf, "ASL.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0108: + sprintf(buf, "LSL.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0110: + sprintf(buf, "ROXL.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0118: + sprintf(buf, "ROL.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0120: + sprintf(buf, "ASL.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0128: + sprintf(buf, "LSL.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0130: + sprintf(buf, "ROXL.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0138: + sprintf(buf, "ROL.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0140: + sprintf(buf, "ASL.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0148: + sprintf(buf, "LSL.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0150: + sprintf(buf, "ROXL.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0158: + sprintf(buf, "ROL.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0160: + sprintf(buf, "ASL.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0168: + sprintf(buf, "LSL.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0170: + sprintf(buf, "ROXL.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0178: + sprintf(buf, "ROL.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0180: + sprintf(buf, "ASL.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0188: + sprintf(buf, "LSL.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0190: + sprintf(buf, "ROXL.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x0198: + sprintf(buf, "ROL.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec)); + return; + case 0x01a0: + sprintf(buf, "ASL.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x01a8: + sprintf(buf, "LSL.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x01b0: + sprintf(buf, "ROXL.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + case 0x01b8: + sprintf(buf, "ROL.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec)); + return; + } + } +} + + +struct state { + uint32 reg[16]; + uint32 stack[8]; + uint32 spc, susp, sssp; + uint16 inst[5]; + uint16 sr; + +}; +struct state traceback[10000]; +void PrintTrace (int index) +{ + + int before; + char disass_buf[80]; + before = (index + (10000 - 1)) % 10000; + disassemble(disass_buf, traceback[before].inst); + sprintf (Msg,"%s\n", disass_buf); + fwrite(Msg,strlen(Msg),1,logfile); + sprintf (Msg,"D0-D7=%08lx, %08lx, %08lx, %08lx, %08lx, %08lx, %08lx, %08lx\n", + traceback[before].reg[0], traceback[before].reg[1], + traceback[before].reg[2], traceback[before].reg[3], + traceback[before].reg[4], traceback[before].reg[5], + traceback[before].reg[6], traceback[before].reg[7]); + fwrite(Msg,strlen(Msg),1,logfile); + if (index != traceindex){ sprintf (Msg,"D0-D7=%08lx, %08lx, %08lx, %08lx, %08lx, %08lx, %08lx, %08lx\n", + traceback[index].reg[0], traceback[index].reg[1], + traceback[index].reg[2], traceback[index].reg[3], + traceback[index].reg[4], traceback[index].reg[5], + traceback[index].reg[6], traceback[index].reg[7]); + fwrite(Msg,strlen(Msg),1,logfile); + } + sprintf (Msg,"A0-A7=%08lx, %08lx, %08lx, %08lx, %08lx, %08lx, %08lx, %08lx\n", + traceback[before].reg[8], traceback[before].reg[9], + traceback[before].reg[10], traceback[before].reg[11], + traceback[before].reg[12], traceback[before].reg[13], + traceback[before].reg[14], traceback[before].reg[15]); + fwrite(Msg,strlen(Msg),1,logfile); + if (index != traceindex){ sprintf (Msg,"A0-A7=%08lx, %08lx, %08lx, %08lx, %08lx, %08lx, %08lx, %08lx\n", + traceback[index].reg[8], traceback[index].reg[9], + traceback[index].reg[10], traceback[index].reg[11], + traceback[index].reg[12], traceback[index].reg[13], + traceback[index].reg[14], traceback[index].reg[15]); + fwrite(Msg,strlen(Msg),1,logfile); + } + sprintf (Msg,"Stack=%08lx, %08lx, %08lx, %08lx, %08lx, %08lx, %08lx, %08lx\n", + traceback[before].stack[0], traceback[before].stack[1], + traceback[before].stack[2], traceback[before].stack[3], + traceback[before].stack[4], traceback[before].stack[5], + traceback[before].stack[6], traceback[before].stack[7]); + fwrite(Msg,strlen(Msg),1,logfile); + if (index != traceindex){ sprintf (Msg,"Stack=%08lx, %08lx, %08lx, %08lx, %08lx, %08lx, %08lx, %08lx\n", + traceback[index].stack[0], traceback[index].stack[1], + traceback[index].stack[2], traceback[index].stack[3], + traceback[index].stack[4], traceback[index].stack[5], + traceback[index].stack[6], traceback[index].stack[7]); + fwrite(Msg,strlen(Msg),1,logfile); + } + sprintf (Msg,"*** PC=%08lx(%04x %04x %04x %04x %04x), SR=%04x, SSP=%08lx, USP=%08lx\n", + traceback[before].spc, traceback[before].inst[0], + traceback[before].inst[1], traceback[before].inst[2], + traceback[before].inst[3], traceback[before].inst[4], + traceback[before].sr, traceback[before].ssp, traceback[before].usp); + fwrite(Msg,strlen(Msg),1,logfile); + if (index != traceindex){ sprintf (Msg,"*** PC=%08lx(%04x %04x %04x %04x %04x), SR=%04x, SSP=%08lx, USP=%08lx\n", + traceback[index].spc, traceback[index].inst[0], + traceback[index].inst[1], traceback[index].inst[2], + traceback[index].inst[3], traceback[index].inst[4], + traceback[index].sr, traceback[index].sssp, traceback[index].susp); + fwrite(Msg,strlen(Msg),1,logfile); + } +} + +void StartDisass() +{ + int i; + + logfile = fopen("\\disass.txt","at"); + sprintf (Msg,"NB INSTRUCTION:%d\n", totnbinst); + fwrite(Msg,strlen(Msg),1,logfile); + if (totnbinst>9999){ + for (i=traceindex;i<10000;i++) PrintTrace (i); + } + for (i=0;i=0x400&®[0x13]<0x580){ + outs=1; + }else outs=0; + if (outs==1){ + totnbinst++; + if ((reg[15] & 0xffffff) < MEMSIZE) { + unsigned long stackaddress = reg[15]; + traceback[traceindex].stack[0] = GetMemL(stackaddress); + traceback[traceindex].stack[1] = GetMemL(stackaddress + 4); + traceback[traceindex].stack[2] = GetMemL(stackaddress + 8); + traceback[traceindex].stack[3] = GetMemL(stackaddress + 12); + traceback[traceindex].stack[4] = GetMemL(stackaddress + 16); + traceback[traceindex].stack[5] = GetMemL(stackaddress + 20); + traceback[traceindex].stack[6] = GetMemL(stackaddress + 24); + traceback[traceindex].stack[7] = GetMemL(stackaddress + 28); + } + memcpy (traceback[traceindex].reg, reg, sizeof (unsigned long) * 16); + traceback[traceindex].spc = GetPC (); + traceback[traceindex].susp = usp; + traceback[traceindex].sssp = ssp; + traceback[traceindex].inst[0] = GetMemW(pc); + traceback[traceindex].inst[1] = GetMemW(pc+2); + traceback[traceindex].inst[2] = GetMemW(pc+4); + traceback[traceindex].inst[3] = GetMemW(pc+6); + traceback[traceindex].inst[4] = GetMemW(pc+8); + traceback[traceindex].sr = GetSRW (); + traceindex = (traceindex + 1) % 10000; + + } + + // if (reg[0x13]==0x10f76){ + // StartDisass(); + // exit(1); + // } +} + + + +#endif diff --git a/MCUME_esp32/espcastaway/main/68korigbad/m68k_intrf.h b/MCUME_esp32/espcastaway/main/68korigbad/m68k_intrf.h new file mode 100755 index 0000000..677969e --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/m68k_intrf.h @@ -0,0 +1,231 @@ +#include +#include +#include "config.h" +#include "dcastaway.h" + +extern int waitstate; + +#ifndef USE_FAME_CORE + +#include "68000.h" +#include "op68k.h" + +extern unsigned IO_CYCLE; + +static __inline__ unsigned long cpu_loop(unsigned slice) { + +extern const unsigned long (*jmp_table[8192])(operin); + +#define initialize_memmap() + +#define cpuinst \ + address = pc&MEMADDRMASK; \ + if (address=ROMBASE2) myinst=biginst=ReadSL(myrombase+address); \ + else { HWReset(); return slice-IO_CYCLE; } \ + pc+=2; \ + IO_CYCLE-=(*jmp_table[(myinst<<16)>>19])(reg); + + register unsigned long *p_reg=(unsigned long *)®[0]; + register unsigned long address; + register int8 *mymembase=membase; + register int8 *myrombase=rombase; + register uint32 myinst; + IO_CYCLE=slice; + //Execute 10 instructions + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + cpuinst + return slice-IO_CYCLE; +#undef cpuinst +} + + +#else + +#include "fame.h" + + +#if defined(DREAMCAST) || defined(USE_FAME_CORE_C) +#define M68KCONTEXT m68kcontext +#define IO_CYCLE io_cycle_counter +#else +#define M68KCONTEXT _m68kcontext +#define IO_CYCLE __io_cycle_counter +#endif + +extern unsigned IO_CYCLE; + +//extern struct M68K_CONTEXT M68KCONTEXT; +extern M68K_CONTEXT M68KCONTEXT; +extern int recalc_int; +extern void SetMemW(unsigned long address, unsigned short value); +extern void HWReset(void); + +#define GetS() ((M68KCONTEXT.sr >> 13) & 1) +#define GetFC2() GetS() +#define GetI() ((M68KCONTEXT.sr >> 8) & 7) +#ifdef DEBUG_FAME +#define Interrupt(NUM,LEV) \ +{ \ + extern int fame_debug_output; \ + extern FILE *fame_debug_file; \ + if (fame_debug_output) \ + { fprintf(fame_debug_file,"Interrupt(%i,%i)\n",(NUM),(LEV)); DEBUG_FAME_FFLUSH; } \ + m68k_lower_irq((LEV)); \ + m68k_raise_irq((LEV),(NUM)); \ +} +#else +#define Interrupt(NUM,LEV) \ +{ \ + M68KCONTEXT.interrupts[0] |= (1 << (LEV)); \ + M68KCONTEXT.interrupts[(LEV)]=(NUM); \ + M68KCONTEXT.execinfo &= 0x7F; \ +} +#endif + +#define ClearInterrupt(LEV) M68KCONTEXT.interrupts[0] &= ~(1 << (LEV)) + + +#define MEMADDRMASK 0x00ffffffl +#define MEMADDRMASKS 0x00fffffel +#define MEMIDXSHIFT 11 +#define MEMADDRSIZE (MEMADDRMASK + 1) +#define AUTOINT2 26 +#define AUTOINT4 28 +#define BUSERR 2 +#define ADDRESSERR 3 + +char GetMemB(unsigned long address); +short GetMemW(unsigned long address); +void initialize_memmap(void); +void ExceptionGroup0( int, unsigned long, int); +void ExceptionGroup0_execute(void); + + +#ifdef DEBUG_FAME +static char dis_msg[96]; +static unsigned short dis_buf[10]; +void disassemble68k(char *buf, unsigned short *inst_stream); +static __inline__ unsigned long cpu_loop(unsigned slice) +{ + unsigned i; + extern int number_exg0_fame; + extern int in_fame_core; + extern unsigned fame_debug_count; + extern int fame_debug_output; + extern FILE *fame_debug_file; + +#ifdef DEBUG_FAME_START + if (fame_debug_count>=((unsigned)(DEBUG_FAME_START))) + fame_debug_output=1; + else { + unsigned long cycles_actual=M68KCONTEXT.cycles_counter; + short lastint=M68KCONTEXT.sr&0x700; + + in_fame_core=1; + m68k_emulate(slice); + in_fame_core=0; + + fprintf(fame_debug_file,"SLICE(%u) %u (%u) ret=%u (%x %x)\n",slice,fame_debug_count,slice,M68KCONTEXT.cycles_counter-cycles_actual,M68KCONTEXT.execinfo&0x80,M68KCONTEXT.interrupts[0]); + fame_debug_count++; + + if (number_exg0_fame) + ExceptionGroup0_execute(); + + if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700))) + M68KCONTEXT.execinfo&=0x7f; + + return (M68KCONTEXT.cycles_counter-cycles_actual); + } + + if (fame_debug_output) + fprintf(fame_debug_file,"SLICE(%u) %u (%u)\n",slice,fame_debug_count,slice); +#endif + + in_fame_core=1; + unsigned long cycles_actual=M68KCONTEXT.cycles_counter; + short lastint=M68KCONTEXT.sr&0x700; + while(M68KCONTEXT.cycles_counter-cycles_actual((unsigned)(DEBUG_FAME_STOP))) + { +#ifdef DEBUG_FAME_FILE + extern FILE *fame_debug_file; + if (fame_debug_file) + fclose(fame_debug_file); + fame_debug_file=NULL; +#endif + free(malloc(24*1024*1024)); exit(0); } +#endif + if (number_exg0_fame) + { + ExceptionGroup0_execute(); + number_exg0_fame=0; + } + if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700))) + M68KCONTEXT.execinfo&=0x7f; + return (M68KCONTEXT.cycles_counter-cycles_actual); +} + +#else +static __inline__ unsigned long cpu_loop(unsigned slice) +{ + extern int in_fame_core; + extern int number_exg0_fame; + + unsigned long cycles_actual=M68KCONTEXT.cycles_counter; + short lastint=M68KCONTEXT.sr&0x700; + + in_fame_core=1; + m68k_emulate(slice); + in_fame_core=0; + + if (number_exg0_fame) + ExceptionGroup0_execute(); + + if ((M68KCONTEXT.execinfo&0x80)&&(lastint!=(M68KCONTEXT.sr&0x700))) + M68KCONTEXT.execinfo&=0x7f; + + return (M68KCONTEXT.cycles_counter-cycles_actual); +} +#endif + + +#endif diff --git a/MCUME_esp32/espcastaway/main/68korigbad/op68000.h b/MCUME_esp32/espcastaway/main/68korigbad/op68000.h new file mode 100755 index 0000000..098fd46 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/op68000.h @@ -0,0 +1,1066 @@ +#include "operin.h" + +/* + * Castaway + * (C) 1994 - 2002 Martin Doering, Joachim Hoenig + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ +const unsigned long (*jmp_table[8192])(operin) = { + /* 0000 */ + Op0000, IllIns, Op0010, Op0018, Op0020, Op0028, Op0030, Op0038, + Op0040, IllIns, Op0050, Op0058, Op0060, Op0068, Op0070, Op0078, + Op0080, IllIns, Op0090, Op0098, Op00a0, Op00a8, Op00b0, Op00b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0100, Op0108, Op0110, Op0118, Op0120, Op0128, Op0130, Op0138, + Op0140, Op0148, Op0150, Op0158, Op0160, Op0168, Op0170, Op0178, + Op0180, Op0188, Op0190, Op0198, Op01a0, Op01a8, Op01b0, Op01b8, + Op01c0, Op01c8, Op01d0, Op01d8, Op01e0, Op01e8, Op01f0, Op01f8, + Op0200, IllIns, Op0210, Op0218, Op0220, Op0228, Op0230, Op0238, + Op0240, IllIns, Op0250, Op0258, Op0260, Op0268, Op0270, Op0278, + Op0280, IllIns, Op0290, Op0298, Op02a0, Op02a8, Op02b0, Op02b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0300, Op0308, Op0310, Op0318, Op0320, Op0328, Op0330, Op0338, + Op0340, Op0348, Op0350, Op0358, Op0360, Op0368, Op0370, Op0378, + Op0380, Op0388, Op0390, Op0398, Op03a0, Op03a8, Op03b0, Op03b8, + Op03c0, Op03c8, Op03d0, Op03d8, Op03e0, Op03e8, Op03f0, Op03f8, + Op0400, IllIns, Op0410, Op0418, Op0420, Op0428, Op0430, Op0438, + Op0440, IllIns, Op0450, Op0458, Op0460, Op0468, Op0470, Op0478, + Op0480, IllIns, Op0490, Op0498, Op04a0, Op04a8, Op04b0, Op04b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0500, Op0508, Op0510, Op0518, Op0520, Op0528, Op0530, Op0538, + Op0540, Op0548, Op0550, Op0558, Op0560, Op0568, Op0570, Op0578, + Op0580, Op0588, Op0590, Op0598, Op05a0, Op05a8, Op05b0, Op05b8, + Op05c0, Op05c8, Op05d0, Op05d8, Op05e0, Op05e8, Op05f0, Op05f8, + Op0600, IllIns, Op0610, Op0618, Op0620, Op0628, Op0630, Op0638, + Op0640, IllIns, Op0650, Op0658, Op0660, Op0668, Op0670, Op0678, + Op0680, IllIns, Op0690, Op0698, Op06a0, Op06a8, Op06b0, Op06b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0700, Op0708, Op0710, Op0718, Op0720, Op0728, Op0730, Op0738, + Op0740, Op0748, Op0750, Op0758, Op0760, Op0768, Op0770, Op0778, + Op0780, Op0788, Op0790, Op0798, Op07a0, Op07a8, Op07b0, Op07b8, + Op07c0, Op07c8, Op07d0, Op07d8, Op07e0, Op07e8, Op07f0, Op07f8, + Op0800, IllIns, Op0810, Op0818, Op0820, Op0828, Op0830, Op0838, + Op0840, IllIns, Op0850, Op0858, Op0860, Op0868, Op0870, Op0878, + Op0880, IllIns, Op0890, Op0898, Op08a0, Op08a8, Op08b0, Op08b8, + Op08c0, IllIns, Op08d0, Op08d8, Op08e0, Op08e8, Op08f0, Op08f8, + Op0900, Op0908, Op0910, Op0918, Op0920, Op0928, Op0930, Op0938, + Op0940, Op0948, Op0950, Op0958, Op0960, Op0968, Op0970, Op0978, + Op0980, Op0988, Op0990, Op0998, Op09a0, Op09a8, Op09b0, Op09b8, + Op09c0, Op09c8, Op09d0, Op09d8, Op09e0, Op09e8, Op09f0, Op09f8, + Op0a00, IllIns, Op0a10, Op0a18, Op0a20, Op0a28, Op0a30, Op0a38, + Op0a40, IllIns, Op0a50, Op0a58, Op0a60, Op0a68, Op0a70, Op0a78, + Op0a80, IllIns, Op0a90, Op0a98, Op0aa0, Op0aa8, Op0ab0, Op0ab8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0b00, Op0b08, Op0b10, Op0b18, Op0b20, Op0b28, Op0b30, Op0b38, + Op0b40, Op0b48, Op0b50, Op0b58, Op0b60, Op0b68, Op0b70, Op0b78, + Op0b80, Op0b88, Op0b90, Op0b98, Op0ba0, Op0ba8, Op0bb0, Op0bb8, + Op0bc0, Op0bc8, Op0bd0, Op0bd8, Op0be0, Op0be8, Op0bf0, Op0bf8, + Op0c00, IllIns, Op0c10, Op0c18, Op0c20, Op0c28, Op0c30, Op0c38, + Op0c40, IllIns, Op0c50, Op0c58, Op0c60, Op0c68, Op0c70, Op0c78, + Op0c80, IllIns, Op0c90, Op0c98, Op0ca0, Op0ca8, Op0cb0, Op0cb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0d00, Op0d08, Op0d10, Op0d18, Op0d20, Op0d28, Op0d30, Op0d38, + Op0d40, Op0d48, Op0d50, Op0d58, Op0d60, Op0d68, Op0d70, Op0d78, + Op0d80, Op0d88, Op0d90, Op0d98, Op0da0, Op0da8, Op0db0, Op0db8, + Op0dc0, Op0dc8, Op0dd0, Op0dd8, Op0de0, Op0de8, Op0df0, Op0df8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0f00, Op0f08, Op0f10, Op0f18, Op0f20, Op0f28, Op0f30, Op0f38, + Op0f40, Op0f48, Op0f50, Op0f58, Op0f60, Op0f68, Op0f70, Op0f78, + Op0f80, Op0f88, Op0f90, Op0f98, Op0fa0, Op0fa8, Op0fb0, Op0fb8, + Op0fc0, Op0fc8, Op0fd0, Op0fd8, Op0fe0, Op0fe8, Op0ff0, Op0ff8, + + /* 1000 */ + Op1000, IllIns, Op1010, Op1018, Op1020, Op1028, Op1030, Op1038, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1080, IllIns, Op1090, Op1098, Op10a0, Op10a8, Op10b0, Op10b8, + Op10c0, IllIns, Op10d0, Op10d8, Op10e0, Op10e8, Op10f0, Op10f8, + Op1100, IllIns, Op1110, Op1118, Op1120, Op1128, Op1130, Op1138, + Op1140, IllIns, Op1150, Op1158, Op1160, Op1168, Op1170, Op1178, + Op1180, IllIns, Op1190, Op1198, Op11a0, Op11a8, Op11b0, Op11b8, + Op11c0, IllIns, Op11d0, Op11d8, Op11e0, Op11e8, Op11f0, Op11f8, + Op1200, IllIns, Op1210, Op1218, Op1220, Op1228, Op1230, Op1238, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1280, IllIns, Op1290, Op1298, Op12a0, Op12a8, Op12b0, Op12b8, + Op12c0, IllIns, Op12d0, Op12d8, Op12e0, Op12e8, Op12f0, Op12f8, + Op1300, IllIns, Op1310, Op1318, Op1320, Op1328, Op1330, Op1338, + Op1340, IllIns, Op1350, Op1358, Op1360, Op1368, Op1370, Op1378, + Op1380, IllIns, Op1390, Op1398, Op13a0, Op13a8, Op13b0, Op13b8, + Op13c0, IllIns, Op13d0, Op13d8, Op13e0, Op13e8, Op13f0, Op13f8, + Op1400, IllIns, Op1410, Op1418, Op1420, Op1428, Op1430, Op1438, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1480, IllIns, Op1490, Op1498, Op14a0, Op14a8, Op14b0, Op14b8, + Op14c0, IllIns, Op14d0, Op14d8, Op14e0, Op14e8, Op14f0, Op14f8, + Op1500, IllIns, Op1510, Op1518, Op1520, Op1528, Op1530, Op1538, + Op1540, IllIns, Op1550, Op1558, Op1560, Op1568, Op1570, Op1578, + Op1580, IllIns, Op1590, Op1598, Op15a0, Op15a8, Op15b0, Op15b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1600, IllIns, Op1610, Op1618, Op1620, Op1628, Op1630, Op1638, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1680, IllIns, Op1690, Op1698, Op16a0, Op16a8, Op16b0, Op16b8, + Op16c0, IllIns, Op16d0, Op16d8, Op16e0, Op16e8, Op16f0, Op16f8, + Op1700, IllIns, Op1710, Op1718, Op1720, Op1728, Op1730, Op1738, + Op1740, IllIns, Op1750, Op1758, Op1760, Op1768, Op1770, Op1778, + Op1780, IllIns, Op1790, Op1798, Op17a0, Op17a8, Op17b0, Op17b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1800, IllIns, Op1810, Op1818, Op1820, Op1828, Op1830, Op1838, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1880, IllIns, Op1890, Op1898, Op18a0, Op18a8, Op18b0, Op18b8, + Op18c0, IllIns, Op18d0, Op18d8, Op18e0, Op18e8, Op18f0, Op18f8, + Op1900, IllIns, Op1910, Op1918, Op1920, Op1928, Op1930, Op1938, + Op1940, IllIns, Op1950, Op1958, Op1960, Op1968, Op1970, Op1978, + Op1980, IllIns, Op1990, Op1998, Op19a0, Op19a8, Op19b0, Op19b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1a00, IllIns, Op1a10, Op1a18, Op1a20, Op1a28, Op1a30, Op1a38, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1a80, IllIns, Op1a90, Op1a98, Op1aa0, Op1aa8, Op1ab0, Op1ab8, + Op1ac0, IllIns, Op1ad0, Op1ad8, Op1ae0, Op1ae8, Op1af0, Op1af8, + Op1b00, IllIns, Op1b10, Op1b18, Op1b20, Op1b28, Op1b30, Op1b38, + Op1b40, IllIns, Op1b50, Op1b58, Op1b60, Op1b68, Op1b70, Op1b78, + Op1b80, IllIns, Op1b90, Op1b98, Op1ba0, Op1ba8, Op1bb0, Op1bb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1c00, IllIns, Op1c10, Op1c18, Op1c20, Op1c28, Op1c30, Op1c38, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1c80, IllIns, Op1c90, Op1c98, Op1ca0, Op1ca8, Op1cb0, Op1cb8, + Op1cc0, IllIns, Op1cd0, Op1cd8, Op1ce0, Op1ce8, Op1cf0, Op1cf8, + Op1d00, IllIns, Op1d10, Op1d18, Op1d20, Op1d28, Op1d30, Op1d38, + Op1d40, IllIns, Op1d50, Op1d58, Op1d60, Op1d68, Op1d70, Op1d78, + Op1d80, IllIns, Op1d90, Op1d98, Op1da0, Op1da8, Op1db0, Op1db8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1e00, IllIns, Op1e10, Op1e18, Op1e20, Op1e28, Op1e30, Op1e38, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1e80, IllIns, Op1e90, Op1e98, Op1ea0, Op1ea8, Op1eb0, Op1eb8, + Op1ec0, IllIns, Op1ed0, Op1ed8, Op1ee0, Op1ee8, Op1ef0, Op1ef8, + Op1f00, IllIns, Op1f10, Op1f18, Op1f20, Op1f28, Op1f30, Op1f38, + Op1f40, IllIns, Op1f50, Op1f58, Op1f60, Op1f68, Op1f70, Op1f78, + Op1f80, IllIns, Op1f90, Op1f98, Op1fa0, Op1fa8, Op1fb0, Op1fb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 2000 */ + Op2000, Op2008, Op2010, Op2018, Op2020, Op2028, Op2030, Op2038, + Op2040, Op2048, Op2050, Op2058, Op2060, Op2068, Op2070, Op2078, + Op2080, Op2088, Op2090, Op2098, Op20a0, Op20a8, Op20b0, Op20b8, + Op20c0, Op20c8, Op20d0, Op20d8, Op20e0, Op20e8, Op20f0, Op20f8, + Op2100, Op2108, Op2110, Op2118, Op2120, Op2128, Op2130, Op2138, + Op2140, Op2148, Op2150, Op2158, Op2160, Op2168, Op2170, Op2178, + Op2180, Op2188, Op2190, Op2198, Op21a0, Op21a8, Op21b0, Op21b8, + Op21c0, Op21c8, Op21d0, Op21d8, Op21e0, Op21e8, Op21f0, Op21f8, + Op2200, Op2208, Op2210, Op2218, Op2220, Op2228, Op2230, Op2238, + Op2240, Op2248, Op2250, Op2258, Op2260, Op2268, Op2270, Op2278, + Op2280, Op2288, Op2290, Op2298, Op22a0, Op22a8, Op22b0, Op22b8, + Op22c0, Op22c8, Op22d0, Op22d8, Op22e0, Op22e8, Op22f0, Op22f8, + Op2300, Op2308, Op2310, Op2318, Op2320, Op2328, Op2330, Op2338, + Op2340, Op2348, Op2350, Op2358, Op2360, Op2368, Op2370, Op2378, + Op2380, Op2388, Op2390, Op2398, Op23a0, Op23a8, Op23b0, Op23b8, + Op23c0, Op23c8, Op23d0, Op23d8, Op23e0, Op23e8, Op23f0, Op23f8, + Op2400, Op2408, Op2410, Op2418, Op2420, Op2428, Op2430, Op2438, + Op2440, Op2448, Op2450, Op2458, Op2460, Op2468, Op2470, Op2478, + Op2480, Op2488, Op2490, Op2498, Op24a0, Op24a8, Op24b0, Op24b8, + Op24c0, Op24c8, Op24d0, Op24d8, Op24e0, Op24e8, Op24f0, Op24f8, + Op2500, Op2508, Op2510, Op2518, Op2520, Op2528, Op2530, Op2538, + Op2540, Op2548, Op2550, Op2558, Op2560, Op2568, Op2570, Op2578, + Op2580, Op2588, Op2590, Op2598, Op25a0, Op25a8, Op25b0, Op25b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2600, Op2608, Op2610, Op2618, Op2620, Op2628, Op2630, Op2638, + Op2640, Op2648, Op2650, Op2658, Op2660, Op2668, Op2670, Op2678, + Op2680, Op2688, Op2690, Op2698, Op26a0, Op26a8, Op26b0, Op26b8, + Op26c0, Op26c8, Op26d0, Op26d8, Op26e0, Op26e8, Op26f0, Op26f8, + Op2700, Op2708, Op2710, Op2718, Op2720, Op2728, Op2730, Op2738, + Op2740, Op2748, Op2750, Op2758, Op2760, Op2768, Op2770, Op2778, + Op2780, Op2788, Op2790, Op2798, Op27a0, Op27a8, Op27b0, Op27b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2800, Op2808, Op2810, Op2818, Op2820, Op2828, Op2830, Op2838, + Op2840, Op2848, Op2850, Op2858, Op2860, Op2868, Op2870, Op2878, + Op2880, Op2888, Op2890, Op2898, Op28a0, Op28a8, Op28b0, Op28b8, + Op28c0, Op28c8, Op28d0, Op28d8, Op28e0, Op28e8, Op28f0, Op28f8, + Op2900, Op2908, Op2910, Op2918, Op2920, Op2928, Op2930, Op2938, + Op2940, Op2948, Op2950, Op2958, Op2960, Op2968, Op2970, Op2978, + Op2980, Op2988, Op2990, Op2998, Op29a0, Op29a8, Op29b0, Op29b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2a00, Op2a08, Op2a10, Op2a18, Op2a20, Op2a28, Op2a30, Op2a38, + Op2a40, Op2a48, Op2a50, Op2a58, Op2a60, Op2a68, Op2a70, Op2a78, + Op2a80, Op2a88, Op2a90, Op2a98, Op2aa0, Op2aa8, Op2ab0, Op2ab8, + Op2ac0, Op2ac8, Op2ad0, Op2ad8, Op2ae0, Op2ae8, Op2af0, Op2af8, + Op2b00, Op2b08, Op2b10, Op2b18, Op2b20, Op2b28, Op2b30, Op2b38, + Op2b40, Op2b48, Op2b50, Op2b58, Op2b60, Op2b68, Op2b70, Op2b78, + Op2b80, Op2b88, Op2b90, Op2b98, Op2ba0, Op2ba8, Op2bb0, Op2bb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2c00, Op2c08, Op2c10, Op2c18, Op2c20, Op2c28, Op2c30, Op2c38, + Op2c40, Op2c48, Op2c50, Op2c58, Op2c60, Op2c68, Op2c70, Op2c78, + Op2c80, Op2c88, Op2c90, Op2c98, Op2ca0, Op2ca8, Op2cb0, Op2cb8, + Op2cc0, Op2cc8, Op2cd0, Op2cd8, Op2ce0, Op2ce8, Op2cf0, Op2cf8, + Op2d00, Op2d08, Op2d10, Op2d18, Op2d20, Op2d28, Op2d30, Op2d38, + Op2d40, Op2d48, Op2d50, Op2d58, Op2d60, Op2d68, Op2d70, Op2d78, + Op2d80, Op2d88, Op2d90, Op2d98, Op2da0, Op2da8, Op2db0, Op2db8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2e00, Op2e08, Op2e10, Op2e18, Op2e20, Op2e28, Op2e30, Op2e38, + Op2e40, Op2e48, Op2e50, Op2e58, Op2e60, Op2e68, Op2e70, Op2e78, + Op2e80, Op2e88, Op2e90, Op2e98, Op2ea0, Op2ea8, Op2eb0, Op2eb8, + Op2ec0, Op2ec8, Op2ed0, Op2ed8, Op2ee0, Op2ee8, Op2ef0, Op2ef8, + Op2f00, Op2f08, Op2f10, Op2f18, Op2f20, Op2f28, Op2f30, Op2f38, + Op2f40, Op2f48, Op2f50, Op2f58, Op2f60, Op2f68, Op2f70, Op2f78, + Op2f80, Op2f88, Op2f90, Op2f98, Op2fa0, Op2fa8, Op2fb0, Op2fb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 3000 */ + Op3000, Op3008, Op3010, Op3018, Op3020, Op3028, Op3030, Op3038, + Op3040, Op3048, Op3050, Op3058, Op3060, Op3068, Op3070, Op3078, + Op3080, Op3088, Op3090, Op3098, Op30a0, Op30a8, Op30b0, Op30b8, + Op30c0, Op30c8, Op30d0, Op30d8, Op30e0, Op30e8, Op30f0, Op30f8, + Op3100, Op3108, Op3110, Op3118, Op3120, Op3128, Op3130, Op3138, + Op3140, Op3148, Op3150, Op3158, Op3160, Op3168, Op3170, Op3178, + Op3180, Op3188, Op3190, Op3198, Op31a0, Op31a8, Op31b0, Op31b8, + Op31c0, Op31c8, Op31d0, Op31d8, Op31e0, Op31e8, Op31f0, Op31f8, + Op3200, Op3208, Op3210, Op3218, Op3220, Op3228, Op3230, Op3238, + Op3240, Op3248, Op3250, Op3258, Op3260, Op3268, Op3270, Op3278, + Op3280, Op3288, Op3290, Op3298, Op32a0, Op32a8, Op32b0, Op32b8, + Op32c0, Op32c8, Op32d0, Op32d8, Op32e0, Op32e8, Op32f0, Op32f8, + Op3300, Op3308, Op3310, Op3318, Op3320, Op3328, Op3330, Op3338, + Op3340, Op3348, Op3350, Op3358, Op3360, Op3368, Op3370, Op3378, + Op3380, Op3388, Op3390, Op3398, Op33a0, Op33a8, Op33b0, Op33b8, + Op33c0, Op33c8, Op33d0, Op33d8, Op33e0, Op33e8, Op33f0, Op33f8, + Op3400, Op3408, Op3410, Op3418, Op3420, Op3428, Op3430, Op3438, + Op3440, Op3448, Op3450, Op3458, Op3460, Op3468, Op3470, Op3478, + Op3480, Op3488, Op3490, Op3498, Op34a0, Op34a8, Op34b0, Op34b8, + Op34c0, Op34c8, Op34d0, Op34d8, Op34e0, Op34e8, Op34f0, Op34f8, + Op3500, Op3508, Op3510, Op3518, Op3520, Op3528, Op3530, Op3538, + Op3540, Op3548, Op3550, Op3558, Op3560, Op3568, Op3570, Op3578, + Op3580, Op3588, Op3590, Op3598, Op35a0, Op35a8, Op35b0, Op35b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3600, Op3608, Op3610, Op3618, Op3620, Op3628, Op3630, Op3638, + Op3640, Op3648, Op3650, Op3658, Op3660, Op3668, Op3670, Op3678, + Op3680, Op3688, Op3690, Op3698, Op36a0, Op36a8, Op36b0, Op36b8, + Op36c0, Op36c8, Op36d0, Op36d8, Op36e0, Op36e8, Op36f0, Op36f8, + Op3700, Op3708, Op3710, Op3718, Op3720, Op3728, Op3730, Op3738, + Op3740, Op3748, Op3750, Op3758, Op3760, Op3768, Op3770, Op3778, + Op3780, Op3788, Op3790, Op3798, Op37a0, Op37a8, Op37b0, Op37b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3800, Op3808, Op3810, Op3818, Op3820, Op3828, Op3830, Op3838, + Op3840, Op3848, Op3850, Op3858, Op3860, Op3868, Op3870, Op3878, + Op3880, Op3888, Op3890, Op3898, Op38a0, Op38a8, Op38b0, Op38b8, + Op38c0, Op38c8, Op38d0, Op38d8, Op38e0, Op38e8, Op38f0, Op38f8, + Op3900, Op3908, Op3910, Op3918, Op3920, Op3928, Op3930, Op3938, + Op3940, Op3948, Op3950, Op3958, Op3960, Op3968, Op3970, Op3978, + Op3980, Op3988, Op3990, Op3998, Op39a0, Op39a8, Op39b0, Op39b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3a00, Op3a08, Op3a10, Op3a18, Op3a20, Op3a28, Op3a30, Op3a38, + Op3a40, Op3a48, Op3a50, Op3a58, Op3a60, Op3a68, Op3a70, Op3a78, + Op3a80, Op3a88, Op3a90, Op3a98, Op3aa0, Op3aa8, Op3ab0, Op3ab8, + Op3ac0, Op3ac8, Op3ad0, Op3ad8, Op3ae0, Op3ae8, Op3af0, Op3af8, + Op3b00, Op3b08, Op3b10, Op3b18, Op3b20, Op3b28, Op3b30, Op3b38, + Op3b40, Op3b48, Op3b50, Op3b58, Op3b60, Op3b68, Op3b70, Op3b78, + Op3b80, Op3b88, Op3b90, Op3b98, Op3ba0, Op3ba8, Op3bb0, Op3bb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3c00, Op3c08, Op3c10, Op3c18, Op3c20, Op3c28, Op3c30, Op3c38, + Op3c40, Op3c48, Op3c50, Op3c58, Op3c60, Op3c68, Op3c70, Op3c78, + Op3c80, Op3c88, Op3c90, Op3c98, Op3ca0, Op3ca8, Op3cb0, Op3cb8, + Op3cc0, Op3cc8, Op3cd0, Op3cd8, Op3ce0, Op3ce8, Op3cf0, Op3cf8, + Op3d00, Op3d08, Op3d10, Op3d18, Op3d20, Op3d28, Op3d30, Op3d38, + Op3d40, Op3d48, Op3d50, Op3d58, Op3d60, Op3d68, Op3d70, Op3d78, + Op3d80, Op3d88, Op3d90, Op3d98, Op3da0, Op3da8, Op3db0, Op3db8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3e00, Op3e08, Op3e10, Op3e18, Op3e20, Op3e28, Op3e30, Op3e38, + Op3e40, Op3e48, Op3e50, Op3e58, Op3e60, Op3e68, Op3e70, Op3e78, + Op3e80, Op3e88, Op3e90, Op3e98, Op3ea0, Op3ea8, Op3eb0, Op3eb8, + Op3ec0, Op3ec8, Op3ed0, Op3ed8, Op3ee0, Op3ee8, Op3ef0, Op3ef8, + Op3f00, Op3f08, Op3f10, Op3f18, Op3f20, Op3f28, Op3f30, Op3f38, + Op3f40, Op3f48, Op3f50, Op3f58, Op3f60, Op3f68, Op3f70, Op3f78, + Op3f80, Op3f88, Op3f90, Op3f98, Op3fa0, Op3fa8, Op3fb0, Op3fb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 4000 */ + Op4000, IllIns, Op4010, Op4018, Op4020, Op4028, Op4030, Op4038, + Op4040, IllIns, Op4050, Op4058, Op4060, Op4068, Op4070, Op4078, + Op4080, IllIns, Op4090, Op4098, Op40a0, Op40a8, Op40b0, Op40b8, + Op40c0, IllIns, Op40d0, Op40d8, Op40e0, Op40e8, Op40f0, Op40f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4180, IllIns, Op4190, Op4198, Op41a0, Op41a8, Op41b0, Op41b8, + IllIns, IllIns, Op41d0, IllIns, IllIns, Op41e8, Op41f0, Op41f8, + Op4200, IllIns, Op4210, Op4218, Op4220, Op4228, Op4230, Op4238, + Op4240, IllIns, Op4250, Op4258, Op4260, Op4268, Op4270, Op4278, + Op4280, IllIns, Op4290, Op4298, Op42a0, Op42a8, Op42b0, Op42b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4380, IllIns, Op4390, Op4398, Op43a0, Op43a8, Op43b0, Op43b8, + IllIns, IllIns, Op43d0, IllIns, IllIns, Op43e8, Op43f0, Op43f8, + Op4400, IllIns, Op4410, Op4418, Op4420, Op4428, Op4430, Op4438, + Op4440, IllIns, Op4450, Op4458, Op4460, Op4468, Op4470, Op4478, + Op4480, IllIns, Op4490, Op4498, Op44a0, Op44a8, Op44b0, Op44b8, + Op44c0, IllIns, Op44d0, Op44d8, Op44e0, Op44e8, Op44f0, Op44f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4580, IllIns, Op4590, Op4598, Op45a0, Op45a8, Op45b0, Op45b8, + IllIns, IllIns, Op45d0, IllIns, IllIns, Op45e8, Op45f0, Op45f8, + Op4600, IllIns, Op4610, Op4618, Op4620, Op4628, Op4630, Op4638, + Op4640, IllIns, Op4650, Op4658, Op4660, Op4668, Op4670, Op4678, + Op4680, IllIns, Op4690, Op4698, Op46a0, Op46a8, Op46b0, Op46b8, + Op46c0, IllIns, Op46d0, Op46d8, Op46e0, Op46e8, Op46f0, Op46f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4780, IllIns, Op4790, Op4798, Op47a0, Op47a8, Op47b0, Op47b8, + IllIns, IllIns, Op47d0, IllIns, IllIns, Op47e8, Op47f0, Op47f8, + Op4800, IllIns, Op4810, Op4818, Op4820, Op4828, Op4830, Op4838, + Op4840, IllIns, Op4850, IllIns, IllIns, Op4868, Op4870, Op4878, + Op4880, IllIns, Op4890, IllIns, Op48a0, Op48a8, Op48b0, Op48b8, + Op48c0, IllIns, Op48d0, IllIns, Op48e0, Op48e8, Op48f0, Op48f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4980, IllIns, Op4990, Op4998, Op49a0, Op49a8, Op49b0, Op49b8, + IllIns, IllIns, Op49d0, IllIns, IllIns, Op49e8, Op49f0, Op49f8, + Op4a00, IllIns, Op4a10, Op4a18, Op4a20, Op4a28, Op4a30, Op4a38, + Op4a40, IllIns, Op4a50, Op4a58, Op4a60, Op4a68, Op4a70, Op4a78, + Op4a80, IllIns, Op4a90, Op4a98, Op4aa0, Op4aa8, Op4ab0, Op4ab8, + Op4ac0, IllIns, Op4ad0, Op4ad8, Op4ae0, Op4ae8, Op4af0, Op4af8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4b80, IllIns, Op4b90, Op4b98, Op4ba0, Op4ba8, Op4bb0, Op4bb8, + IllIns, IllIns, Op4bd0, IllIns, IllIns, Op4be8, Op4bf0, Op4bf8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, Op4c90, Op4c98, IllIns, Op4ca8, Op4cb0, Op4cb8, + IllIns, IllIns, Op4cd0, Op4cd8, IllIns, Op4ce8, Op4cf0, Op4cf8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4d80, IllIns, Op4d90, Op4d98, Op4da0, Op4da8, Op4db0, Op4db8, + IllIns, IllIns, Op4dd0, IllIns, IllIns, Op4de8, Op4df0, Op4df8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, // Special Instruction to Switch Trace mode + Op4e40, Op4e40, Op4e50, Op4e58, Op4e60, Op4e68, Op4e70, IllIns, + IllIns, IllIns, Op4e90, IllIns, IllIns, Op4ea8, Op4eb0, Op4eb8, + IllIns, IllIns, Op4ed0, IllIns, IllIns, Op4ee8, Op4ef0, Op4ef8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4f80, IllIns, Op4f90, Op4f98, Op4fa0, Op4fa8, Op4fb0, Op4fb8, + IllIns, IllIns, Op4fd0, IllIns, IllIns, Op4fe8, Op4ff0, Op4ff8, + + /* 5000 */ + Op5000, IllIns, Op5010, Op5018, Op5020, Op5028, Op5030, Op5038, + Op5040, Op5048, Op5050, Op5058, Op5060, Op5068, Op5070, Op5078, + Op5080, Op5088, Op5090, Op5098, Op50a0, Op50a8, Op50b0, Op50b8, + Op50c0, Op50c8, Op50d0, Op50d8, Op50e0, Op50e8, Op50f0, Op50f8, + Op5100, IllIns, Op5110, Op5118, Op5120, Op5128, Op5130, Op5138, + Op5140, Op5148, Op5150, Op5158, Op5160, Op5168, Op5170, Op5178, + Op5180, Op5188, Op5190, Op5198, Op51a0, Op51a8, Op51b0, Op51b8, + Op51c0, Op51c8, Op51d0, Op51d8, Op51e0, Op51e8, Op51f0, Op51f8, + Op5200, IllIns, Op5210, Op5218, Op5220, Op5228, Op5230, Op5238, + Op5240, Op5248, Op5250, Op5258, Op5260, Op5268, Op5270, Op5278, + Op5280, Op5288, Op5290, Op5298, Op52a0, Op52a8, Op52b0, Op52b8, + Op52c0, Op52c8, Op52d0, Op52d8, Op52e0, Op52e8, Op52f0, Op52f8, + Op5300, IllIns, Op5310, Op5318, Op5320, Op5328, Op5330, Op5338, + Op5340, Op5348, Op5350, Op5358, Op5360, Op5368, Op5370, Op5378, + Op5380, Op5388, Op5390, Op5398, Op53a0, Op53a8, Op53b0, Op53b8, + Op53c0, Op53c8, Op53d0, Op53d8, Op53e0, Op53e8, Op53f0, Op53f8, + Op5400, IllIns, Op5410, Op5418, Op5420, Op5428, Op5430, Op5438, + Op5440, Op5448, Op5450, Op5458, Op5460, Op5468, Op5470, Op5478, + Op5480, Op5488, Op5490, Op5498, Op54a0, Op54a8, Op54b0, Op54b8, + Op54c0, Op54c8, Op54d0, Op54d8, Op54e0, Op54e8, Op54f0, Op54f8, + Op5500, IllIns, Op5510, Op5518, Op5520, Op5528, Op5530, Op5538, + Op5540, Op5548, Op5550, Op5558, Op5560, Op5568, Op5570, Op5578, + Op5580, Op5588, Op5590, Op5598, Op55a0, Op55a8, Op55b0, Op55b8, + Op55c0, Op55c8, Op55d0, Op55d8, Op55e0, Op55e8, Op55f0, Op55f8, + Op5600, IllIns, Op5610, Op5618, Op5620, Op5628, Op5630, Op5638, + Op5640, Op5648, Op5650, Op5658, Op5660, Op5668, Op5670, Op5678, + Op5680, Op5688, Op5690, Op5698, Op56a0, Op56a8, Op56b0, Op56b8, + Op56c0, Op56c8, Op56d0, Op56d8, Op56e0, Op56e8, Op56f0, Op56f8, + Op5700, IllIns, Op5710, Op5718, Op5720, Op5728, Op5730, Op5738, + Op5740, Op5748, Op5750, Op5758, Op5760, Op5768, Op5770, Op5778, + Op5780, Op5788, Op5790, Op5798, Op57a0, Op57a8, Op57b0, Op57b8, + Op57c0, Op57c8, Op57d0, Op57d8, Op57e0, Op57e8, Op57f0, Op57f8, + Op5800, IllIns, Op5810, Op5818, Op5820, Op5828, Op5830, Op5838, + Op5840, Op5848, Op5850, Op5858, Op5860, Op5868, Op5870, Op5878, + Op5880, Op5888, Op5890, Op5898, Op58a0, Op58a8, Op58b0, Op58b8, + Op58c0, Op58c8, Op58d0, Op58d8, Op58e0, Op58e8, Op58f0, Op58f8, + Op5900, IllIns, Op5910, Op5918, Op5920, Op5928, Op5930, Op5938, + Op5940, Op5948, Op5950, Op5958, Op5960, Op5968, Op5970, Op5978, + Op5980, Op5988, Op5990, Op5998, Op59a0, Op59a8, Op59b0, Op59b8, + Op59c0, Op59c8, Op59d0, Op59d8, Op59e0, Op59e8, Op59f0, Op59f8, + Op5a00, IllIns, Op5a10, Op5a18, Op5a20, Op5a28, Op5a30, Op5a38, + Op5a40, Op5a48, Op5a50, Op5a58, Op5a60, Op5a68, Op5a70, Op5a78, + Op5a80, Op5a88, Op5a90, Op5a98, Op5aa0, Op5aa8, Op5ab0, Op5ab8, + Op5ac0, Op5ac8, Op5ad0, Op5ad8, Op5ae0, Op5ae8, Op5af0, Op5af8, + Op5b00, IllIns, Op5b10, Op5b18, Op5b20, Op5b28, Op5b30, Op5b38, + Op5b40, Op5b48, Op5b50, Op5b58, Op5b60, Op5b68, Op5b70, Op5b78, + Op5b80, Op5b88, Op5b90, Op5b98, Op5ba0, Op5ba8, Op5bb0, Op5bb8, + Op5bc0, Op5bc8, Op5bd0, Op5bd8, Op5be0, Op5be8, Op5bf0, Op5bf8, + Op5c00, IllIns, Op5c10, Op5c18, Op5c20, Op5c28, Op5c30, Op5c38, + Op5c40, Op5c48, Op5c50, Op5c58, Op5c60, Op5c68, Op5c70, Op5c78, + Op5c80, Op5c88, Op5c90, Op5c98, Op5ca0, Op5ca8, Op5cb0, Op5cb8, + Op5cc0, Op5cc8, Op5cd0, Op5cd8, Op5ce0, Op5ce8, Op5cf0, Op5cf8, + Op5d00, IllIns, Op5d10, Op5d18, Op5d20, Op5d28, Op5d30, Op5d38, + Op5d40, Op5d48, Op5d50, Op5d58, Op5d60, Op5d68, Op5d70, Op5d78, + Op5d80, Op5d88, Op5d90, Op5d98, Op5da0, Op5da8, Op5db0, Op5db8, + Op5dc0, Op5dc8, Op5dd0, Op5dd8, Op5de0, Op5de8, Op5df0, Op5df8, + Op5e00, IllIns, Op5e10, Op5e18, Op5e20, Op5e28, Op5e30, Op5e38, + Op5e40, Op5e48, Op5e50, Op5e58, Op5e60, Op5e68, Op5e70, Op5e78, + Op5e80, Op5e88, Op5e90, Op5e98, Op5ea0, Op5ea8, Op5eb0, Op5eb8, + Op5ec0, Op5ec8, Op5ed0, Op5ed8, Op5ee0, Op5ee8, Op5ef0, Op5ef8, + Op5f00, IllIns, Op5f10, Op5f18, Op5f20, Op5f28, Op5f30, Op5f38, + Op5f40, Op5f48, Op5f50, Op5f58, Op5f60, Op5f68, Op5f70, Op5f78, + Op5f80, Op5f88, Op5f90, Op5f98, Op5fa0, Op5fa8, Op5fb0, Op5fb8, + Op5fc0, Op5fc8, Op5fd0, Op5fd8, Op5fe0, Op5fe8, Op5ff0, Op5ff8, + + /* 6000 */ + Op6000, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6100, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6200, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6300, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6400, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6500, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6600, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6700, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6800, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6900, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6a00, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6b00, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6c00, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6d00, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6e00, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6f00, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + + /* 7000 */ + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 8000 */ + Op8000, IllIns, Op8010, Op8018, Op8020, Op8028, Op8030, Op8038, + Op8040, IllIns, Op8050, Op8058, Op8060, Op8068, Op8070, Op8078, + Op8080, IllIns, Op8090, Op8098, Op80a0, Op80a8, Op80b0, Op80b8, + Op80c0, IllIns, Op80d0, Op80d8, Op80e0, Op80e8, Op80f0, Op80f8, + Op8100, Op8108, Op8110, Op8118, Op8120, Op8128, Op8130, Op8138, + IllIns, IllIns, Op8150, Op8158, Op8160, Op8168, Op8170, Op8178, + IllIns, IllIns, Op8190, Op8198, Op81a0, Op81a8, Op81b0, Op81b8, + Op81c0, IllIns, Op81d0, Op81d8, Op81e0, Op81e8, Op81f0, Op81f8, + Op8200, IllIns, Op8210, Op8218, Op8220, Op8228, Op8230, Op8238, + Op8240, IllIns, Op8250, Op8258, Op8260, Op8268, Op8270, Op8278, + Op8280, IllIns, Op8290, Op8298, Op82a0, Op82a8, Op82b0, Op82b8, + Op82c0, IllIns, Op82d0, Op82d8, Op82e0, Op82e8, Op82f0, Op82f8, + Op8300, Op8308, Op8310, Op8318, Op8320, Op8328, Op8330, Op8338, + IllIns, IllIns, Op8350, Op8358, Op8360, Op8368, Op8370, Op8378, + IllIns, IllIns, Op8390, Op8398, Op83a0, Op83a8, Op83b0, Op83b8, + Op83c0, IllIns, Op83d0, Op83d8, Op83e0, Op83e8, Op83f0, Op83f8, + Op8400, IllIns, Op8410, Op8418, Op8420, Op8428, Op8430, Op8438, + Op8440, IllIns, Op8450, Op8458, Op8460, Op8468, Op8470, Op8478, + Op8480, IllIns, Op8490, Op8498, Op84a0, Op84a8, Op84b0, Op84b8, + Op84c0, IllIns, Op84d0, Op84d8, Op84e0, Op84e8, Op84f0, Op84f8, + Op8500, Op8508, Op8510, Op8518, Op8520, Op8528, Op8530, Op8538, + IllIns, IllIns, Op8550, Op8558, Op8560, Op8568, Op8570, Op8578, + IllIns, IllIns, Op8590, Op8598, Op85a0, Op85a8, Op85b0, Op85b8, + Op85c0, IllIns, Op85d0, Op85d8, Op85e0, Op85e8, Op85f0, Op85f8, + Op8600, IllIns, Op8610, Op8618, Op8620, Op8628, Op8630, Op8638, + Op8640, IllIns, Op8650, Op8658, Op8660, Op8668, Op8670, Op8678, + Op8680, IllIns, Op8690, Op8698, Op86a0, Op86a8, Op86b0, Op86b8, + Op86c0, IllIns, Op86d0, Op86d8, Op86e0, Op86e8, Op86f0, Op86f8, + Op8700, Op8708, Op8710, Op8718, Op8720, Op8728, Op8730, Op8738, + IllIns, IllIns, Op8750, Op8758, Op8760, Op8768, Op8770, Op8778, + IllIns, IllIns, Op8790, Op8798, Op87a0, Op87a8, Op87b0, Op87b8, + Op87c0, IllIns, Op87d0, Op87d8, Op87e0, Op87e8, Op87f0, Op87f8, + Op8800, IllIns, Op8810, Op8818, Op8820, Op8828, Op8830, Op8838, + Op8840, IllIns, Op8850, Op8858, Op8860, Op8868, Op8870, Op8878, + Op8880, IllIns, Op8890, Op8898, Op88a0, Op88a8, Op88b0, Op88b8, + Op88c0, IllIns, Op88d0, Op88d8, Op88e0, Op88e8, Op88f0, Op88f8, + Op8900, Op8908, Op8910, Op8918, Op8920, Op8928, Op8930, Op8938, + IllIns, IllIns, Op8950, Op8958, Op8960, Op8968, Op8970, Op8978, + IllIns, IllIns, Op8990, Op8998, Op89a0, Op89a8, Op89b0, Op89b8, + Op89c0, IllIns, Op89d0, Op89d8, Op89e0, Op89e8, Op89f0, Op89f8, + Op8a00, IllIns, Op8a10, Op8a18, Op8a20, Op8a28, Op8a30, Op8a38, + Op8a40, IllIns, Op8a50, Op8a58, Op8a60, Op8a68, Op8a70, Op8a78, + Op8a80, IllIns, Op8a90, Op8a98, Op8aa0, Op8aa8, Op8ab0, Op8ab8, + Op8ac0, IllIns, Op8ad0, Op8ad8, Op8ae0, Op8ae8, Op8af0, Op8af8, + Op8b00, Op8b08, Op8b10, Op8b18, Op8b20, Op8b28, Op8b30, Op8b38, + IllIns, IllIns, Op8b50, Op8b58, Op8b60, Op8b68, Op8b70, Op8b78, + IllIns, IllIns, Op8b90, Op8b98, Op8ba0, Op8ba8, Op8bb0, Op8bb8, + Op8bc0, IllIns, Op8bd0, Op8bd8, Op8be0, Op8be8, Op8bf0, Op8bf8, + Op8c00, IllIns, Op8c10, Op8c18, Op8c20, Op8c28, Op8c30, Op8c38, + Op8c40, IllIns, Op8c50, Op8c58, Op8c60, Op8c68, Op8c70, Op8c78, + Op8c80, IllIns, Op8c90, Op8c98, Op8ca0, Op8ca8, Op8cb0, Op8cb8, + Op8cc0, IllIns, Op8cd0, Op8cd8, Op8ce0, Op8ce8, Op8cf0, Op8cf8, + Op8d00, Op8d08, Op8d10, Op8d18, Op8d20, Op8d28, Op8d30, Op8d38, + IllIns, IllIns, Op8d50, Op8d58, Op8d60, Op8d68, Op8d70, Op8d78, + IllIns, IllIns, Op8d90, Op8d98, Op8da0, Op8da8, Op8db0, Op8db8, + Op8dc0, IllIns, Op8dd0, Op8dd8, Op8de0, Op8de8, Op8df0, Op8df8, + Op8e00, IllIns, Op8e10, Op8e18, Op8e20, Op8e28, Op8e30, Op8e38, + Op8e40, IllIns, Op8e50, Op8e58, Op8e60, Op8e68, Op8e70, Op8e78, + Op8e80, IllIns, Op8e90, Op8e98, Op8ea0, Op8ea8, Op8eb0, Op8eb8, + Op8ec0, IllIns, Op8ed0, Op8ed8, Op8ee0, Op8ee8, Op8ef0, Op8ef8, + Op8f00, Op8f08, Op8f10, Op8f18, Op8f20, Op8f28, Op8f30, Op8f38, + IllIns, IllIns, Op8f50, Op8f58, Op8f60, Op8f68, Op8f70, Op8f78, + IllIns, IllIns, Op8f90, Op8f98, Op8fa0, Op8fa8, Op8fb0, Op8fb8, + Op8fc0, IllIns, Op8fd0, Op8fd8, Op8fe0, Op8fe8, Op8ff0, Op8ff8, + + /* 9000 */ + Op9000, IllIns, Op9010, Op9018, Op9020, Op9028, Op9030, Op9038, + Op9040, Op9048, Op9050, Op9058, Op9060, Op9068, Op9070, Op9078, + Op9080, Op9088, Op9090, Op9098, Op90a0, Op90a8, Op90b0, Op90b8, + Op90c0, Op90c8, Op90d0, Op90d8, Op90e0, Op90e8, Op90f0, Op90f8, + Op9100, Op9108, Op9110, Op9118, Op9120, Op9128, Op9130, Op9138, + Op9140, Op9148, Op9150, Op9158, Op9160, Op9168, Op9170, Op9178, + Op9180, Op9188, Op9190, Op9198, Op91a0, Op91a8, Op91b0, Op91b8, + Op91c0, Op91c8, Op91d0, Op91d8, Op91e0, Op91e8, Op91f0, Op91f8, + Op9200, IllIns, Op9210, Op9218, Op9220, Op9228, Op9230, Op9238, + Op9240, Op9248, Op9250, Op9258, Op9260, Op9268, Op9270, Op9278, + Op9280, Op9288, Op9290, Op9298, Op92a0, Op92a8, Op92b0, Op92b8, + Op92c0, Op92c8, Op92d0, Op92d8, Op92e0, Op92e8, Op92f0, Op92f8, + Op9300, Op9308, Op9310, Op9318, Op9320, Op9328, Op9330, Op9338, + Op9340, Op9348, Op9350, Op9358, Op9360, Op9368, Op9370, Op9378, + Op9380, Op9388, Op9390, Op9398, Op93a0, Op93a8, Op93b0, Op93b8, + Op93c0, Op93c8, Op93d0, Op93d8, Op93e0, Op93e8, Op93f0, Op93f8, + Op9400, IllIns, Op9410, Op9418, Op9420, Op9428, Op9430, Op9438, + Op9440, Op9448, Op9450, Op9458, Op9460, Op9468, Op9470, Op9478, + Op9480, Op9488, Op9490, Op9498, Op94a0, Op94a8, Op94b0, Op94b8, + Op94c0, Op94c8, Op94d0, Op94d8, Op94e0, Op94e8, Op94f0, Op94f8, + Op9500, Op9508, Op9510, Op9518, Op9520, Op9528, Op9530, Op9538, + Op9540, Op9548, Op9550, Op9558, Op9560, Op9568, Op9570, Op9578, + Op9580, Op9588, Op9590, Op9598, Op95a0, Op95a8, Op95b0, Op95b8, + Op95c0, Op95c8, Op95d0, Op95d8, Op95e0, Op95e8, Op95f0, Op95f8, + Op9600, IllIns, Op9610, Op9618, Op9620, Op9628, Op9630, Op9638, + Op9640, Op9648, Op9650, Op9658, Op9660, Op9668, Op9670, Op9678, + Op9680, Op9688, Op9690, Op9698, Op96a0, Op96a8, Op96b0, Op96b8, + Op96c0, Op96c8, Op96d0, Op96d8, Op96e0, Op96e8, Op96f0, Op96f8, + Op9700, Op9708, Op9710, Op9718, Op9720, Op9728, Op9730, Op9738, + Op9740, Op9748, Op9750, Op9758, Op9760, Op9768, Op9770, Op9778, + Op9780, Op9788, Op9790, Op9798, Op97a0, Op97a8, Op97b0, Op97b8, + Op97c0, Op97c8, Op97d0, Op97d8, Op97e0, Op97e8, Op97f0, Op97f8, + Op9800, IllIns, Op9810, Op9818, Op9820, Op9828, Op9830, Op9838, + Op9840, Op9848, Op9850, Op9858, Op9860, Op9868, Op9870, Op9878, + Op9880, Op9888, Op9890, Op9898, Op98a0, Op98a8, Op98b0, Op98b8, + Op98c0, Op98c8, Op98d0, Op98d8, Op98e0, Op98e8, Op98f0, Op98f8, + Op9900, Op9908, Op9910, Op9918, Op9920, Op9928, Op9930, Op9938, + Op9940, Op9948, Op9950, Op9958, Op9960, Op9968, Op9970, Op9978, + Op9980, Op9988, Op9990, Op9998, Op99a0, Op99a8, Op99b0, Op99b8, + Op99c0, Op99c8, Op99d0, Op99d8, Op99e0, Op99e8, Op99f0, Op99f8, + Op9a00, IllIns, Op9a10, Op9a18, Op9a20, Op9a28, Op9a30, Op9a38, + Op9a40, Op9a48, Op9a50, Op9a58, Op9a60, Op9a68, Op9a70, Op9a78, + Op9a80, Op9a88, Op9a90, Op9a98, Op9aa0, Op9aa8, Op9ab0, Op9ab8, + Op9ac0, Op9ac8, Op9ad0, Op9ad8, Op9ae0, Op9ae8, Op9af0, Op9af8, + Op9b00, Op9b08, Op9b10, Op9b18, Op9b20, Op9b28, Op9b30, Op9b38, + Op9b40, Op9b48, Op9b50, Op9b58, Op9b60, Op9b68, Op9b70, Op9b78, + Op9b80, Op9b88, Op9b90, Op9b98, Op9ba0, Op9ba8, Op9bb0, Op9bb8, + Op9bc0, Op9bc8, Op9bd0, Op9bd8, Op9be0, Op9be8, Op9bf0, Op9bf8, + Op9c00, IllIns, Op9c10, Op9c18, Op9c20, Op9c28, Op9c30, Op9c38, + Op9c40, Op9c48, Op9c50, Op9c58, Op9c60, Op9c68, Op9c70, Op9c78, + Op9c80, Op9c88, Op9c90, Op9c98, Op9ca0, Op9ca8, Op9cb0, Op9cb8, + Op9cc0, Op9cc8, Op9cd0, Op9cd8, Op9ce0, Op9ce8, Op9cf0, Op9cf8, + Op9d00, Op9d08, Op9d10, Op9d18, Op9d20, Op9d28, Op9d30, Op9d38, + Op9d40, Op9d48, Op9d50, Op9d58, Op9d60, Op9d68, Op9d70, Op9d78, + Op9d80, Op9d88, Op9d90, Op9d98, Op9da0, Op9da8, Op9db0, Op9db8, + Op9dc0, Op9dc8, Op9dd0, Op9dd8, Op9de0, Op9de8, Op9df0, Op9df8, + Op9e00, IllIns, Op9e10, Op9e18, Op9e20, Op9e28, Op9e30, Op9e38, + Op9e40, Op9e48, Op9e50, Op9e58, Op9e60, Op9e68, Op9e70, Op9e78, + Op9e80, Op9e88, Op9e90, Op9e98, Op9ea0, Op9ea8, Op9eb0, Op9eb8, + Op9ec0, Op9ec8, Op9ed0, Op9ed8, Op9ee0, Op9ee8, Op9ef0, Op9ef8, + Op9f00, Op9f08, Op9f10, Op9f18, Op9f20, Op9f28, Op9f30, Op9f38, + Op9f40, Op9f48, Op9f50, Op9f58, Op9f60, Op9f68, Op9f70, Op9f78, + Op9f80, Op9f88, Op9f90, Op9f98, Op9fa0, Op9fa8, Op9fb0, Op9fb8, + Op9fc0, Op9fc8, Op9fd0, Op9fd8, Op9fe0, Op9fe8, Op9ff0, Op9ff8, + + /* A000 */ + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + + /* B000 */ + Opb000, IllIns, Opb010, Opb018, Opb020, Opb028, Opb030, Opb038, + Opb040, Opb048, Opb050, Opb058, Opb060, Opb068, Opb070, Opb078, + Opb080, Opb088, Opb090, Opb098, Opb0a0, Opb0a8, Opb0b0, Opb0b8, + Opb0c0, Opb0c8, Opb0d0, Opb0d8, Opb0e0, Opb0e8, Opb0f0, Opb0f8, + Opb100, Opb108, Opb110, Opb118, Opb120, Opb128, Opb130, Opb138, + Opb140, Opb148, Opb150, Opb158, Opb160, Opb168, Opb170, Opb178, + Opb180, Opb188, Opb190, Opb198, Opb1a0, Opb1a8, Opb1b0, Opb1b8, + Opb1c0, Opb1c8, Opb1d0, Opb1d8, Opb1e0, Opb1e8, Opb1f0, Opb1f8, + Opb200, IllIns, Opb210, Opb218, Opb220, Opb228, Opb230, Opb238, + Opb240, Opb248, Opb250, Opb258, Opb260, Opb268, Opb270, Opb278, + Opb280, Opb288, Opb290, Opb298, Opb2a0, Opb2a8, Opb2b0, Opb2b8, + Opb2c0, Opb2c8, Opb2d0, Opb2d8, Opb2e0, Opb2e8, Opb2f0, Opb2f8, + Opb300, Opb308, Opb310, Opb318, Opb320, Opb328, Opb330, Opb338, + Opb340, Opb348, Opb350, Opb358, Opb360, Opb368, Opb370, Opb378, + Opb380, Opb388, Opb390, Opb398, Opb3a0, Opb3a8, Opb3b0, Opb3b8, + Opb3c0, Opb3c8, Opb3d0, Opb3d8, Opb3e0, Opb3e8, Opb3f0, Opb3f8, + Opb400, IllIns, Opb410, Opb418, Opb420, Opb428, Opb430, Opb438, + Opb440, Opb448, Opb450, Opb458, Opb460, Opb468, Opb470, Opb478, + Opb480, Opb488, Opb490, Opb498, Opb4a0, Opb4a8, Opb4b0, Opb4b8, + Opb4c0, Opb4c8, Opb4d0, Opb4d8, Opb4e0, Opb4e8, Opb4f0, Opb4f8, + Opb500, Opb508, Opb510, Opb518, Opb520, Opb528, Opb530, Opb538, + Opb540, Opb548, Opb550, Opb558, Opb560, Opb568, Opb570, Opb578, + Opb580, Opb588, Opb590, Opb598, Opb5a0, Opb5a8, Opb5b0, Opb5b8, + Opb5c0, Opb5c8, Opb5d0, Opb5d8, Opb5e0, Opb5e8, Opb5f0, Opb5f8, + Opb600, IllIns, Opb610, Opb618, Opb620, Opb628, Opb630, Opb638, + Opb640, Opb648, Opb650, Opb658, Opb660, Opb668, Opb670, Opb678, + Opb680, Opb688, Opb690, Opb698, Opb6a0, Opb6a8, Opb6b0, Opb6b8, + Opb6c0, Opb6c8, Opb6d0, Opb6d8, Opb6e0, Opb6e8, Opb6f0, Opb6f8, + Opb700, Opb708, Opb710, Opb718, Opb720, Opb728, Opb730, Opb738, + Opb740, Opb748, Opb750, Opb758, Opb760, Opb768, Opb770, Opb778, + Opb780, Opb788, Opb790, Opb798, Opb7a0, Opb7a8, Opb7b0, Opb7b8, + Opb7c0, Opb7c8, Opb7d0, Opb7d8, Opb7e0, Opb7e8, Opb7f0, Opb7f8, + Opb800, IllIns, Opb810, Opb818, Opb820, Opb828, Opb830, Opb838, + Opb840, Opb848, Opb850, Opb858, Opb860, Opb868, Opb870, Opb878, + Opb880, Opb888, Opb890, Opb898, Opb8a0, Opb8a8, Opb8b0, Opb8b8, + Opb8c0, Opb8c8, Opb8d0, Opb8d8, Opb8e0, Opb8e8, Opb8f0, Opb8f8, + Opb900, Opb908, Opb910, Opb918, Opb920, Opb928, Opb930, Opb938, + Opb940, Opb948, Opb950, Opb958, Opb960, Opb968, Opb970, Opb978, + Opb980, Opb988, Opb990, Opb998, Opb9a0, Opb9a8, Opb9b0, Opb9b8, + Opb9c0, Opb9c8, Opb9d0, Opb9d8, Opb9e0, Opb9e8, Opb9f0, Opb9f8, + Opba00, IllIns, Opba10, Opba18, Opba20, Opba28, Opba30, Opba38, + Opba40, Opba48, Opba50, Opba58, Opba60, Opba68, Opba70, Opba78, + Opba80, Opba88, Opba90, Opba98, Opbaa0, Opbaa8, Opbab0, Opbab8, + Opbac0, Opbac8, Opbad0, Opbad8, Opbae0, Opbae8, Opbaf0, Opbaf8, + Opbb00, Opbb08, Opbb10, Opbb18, Opbb20, Opbb28, Opbb30, Opbb38, + Opbb40, Opbb48, Opbb50, Opbb58, Opbb60, Opbb68, Opbb70, Opbb78, + Opbb80, Opbb88, Opbb90, Opbb98, Opbba0, Opbba8, Opbbb0, Opbbb8, + Opbbc0, Opbbc8, Opbbd0, Opbbd8, Opbbe0, Opbbe8, Opbbf0, Opbbf8, + Opbc00, IllIns, Opbc10, Opbc18, Opbc20, Opbc28, Opbc30, Opbc38, + Opbc40, Opbc48, Opbc50, Opbc58, Opbc60, Opbc68, Opbc70, Opbc78, + Opbc80, Opbc88, Opbc90, Opbc98, Opbca0, Opbca8, Opbcb0, Opbcb8, + Opbcc0, Opbcc8, Opbcd0, Opbcd8, Opbce0, Opbce8, Opbcf0, Opbcf8, + Opbd00, Opbd08, Opbd10, Opbd18, Opbd20, Opbd28, Opbd30, Opbd38, + Opbd40, Opbd48, Opbd50, Opbd58, Opbd60, Opbd68, Opbd70, Opbd78, + Opbd80, Opbd88, Opbd90, Opbd98, Opbda0, Opbda8, Opbdb0, Opbdb8, + Opbdc0, Opbdc8, Opbdd0, Opbdd8, Opbde0, Opbde8, Opbdf0, Opbdf8, + Opbe00, IllIns, Opbe10, Opbe18, Opbe20, Opbe28, Opbe30, Opbe38, + Opbe40, Opbe48, Opbe50, Opbe58, Opbe60, Opbe68, Opbe70, Opbe78, + Opbe80, Opbe88, Opbe90, Opbe98, Opbea0, Opbea8, Opbeb0, Opbeb8, + Opbec0, Opbec8, Opbed0, Opbed8, Opbee0, Opbee8, Opbef0, Opbef8, + Opbf00, Opbf08, Opbf10, Opbf18, Opbf20, Opbf28, Opbf30, Opbf38, + Opbf40, Opbf48, Opbf50, Opbf58, Opbf60, Opbf68, Opbf70, Opbf78, + Opbf80, Opbf88, Opbf90, Opbf98, Opbfa0, Opbfa8, Opbfb0, Opbfb8, + Opbfc0, Opbfc8, Opbfd0, Opbfd8, Opbfe0, Opbfe8, Opbff0, Opbff8, + + /* C000 */ + Opc000, IllIns, Opc010, Opc018, Opc020, Opc028, Opc030, Opc038, + Opc040, IllIns, Opc050, Opc058, Opc060, Opc068, Opc070, Opc078, + Opc080, IllIns, Opc090, Opc098, Opc0a0, Opc0a8, Opc0b0, Opc0b8, + Opc0c0, IllIns, Opc0d0, Opc0d8, Opc0e0, Opc0e8, Opc0f0, Opc0f8, + Opc100, Opc108, Opc110, Opc118, Opc120, Opc128, Opc130, Opc138, + Opc140, Opc148, Opc150, Opc158, Opc160, Opc168, Opc170, Opc178, + IllIns, Opc188, Opc190, Opc198, Opc1a0, Opc1a8, Opc1b0, Opc1b8, + Opc1c0, IllIns, Opc1d0, Opc1d8, Opc1e0, Opc1e8, Opc1f0, Opc1f8, + Opc200, IllIns, Opc210, Opc218, Opc220, Opc228, Opc230, Opc238, + Opc240, IllIns, Opc250, Opc258, Opc260, Opc268, Opc270, Opc278, + Opc280, IllIns, Opc290, Opc298, Opc2a0, Opc2a8, Opc2b0, Opc2b8, + Opc2c0, IllIns, Opc2d0, Opc2d8, Opc2e0, Opc2e8, Opc2f0, Opc2f8, + Opc300, Opc308, Opc310, Opc318, Opc320, Opc328, Opc330, Opc338, + Opc340, Opc348, Opc350, Opc358, Opc360, Opc368, Opc370, Opc378, + IllIns, Opc388, Opc390, Opc398, Opc3a0, Opc3a8, Opc3b0, Opc3b8, + Opc3c0, IllIns, Opc3d0, Opc3d8, Opc3e0, Opc3e8, Opc3f0, Opc3f8, + Opc400, IllIns, Opc410, Opc418, Opc420, Opc428, Opc430, Opc438, + Opc440, IllIns, Opc450, Opc458, Opc460, Opc468, Opc470, Opc478, + Opc480, IllIns, Opc490, Opc498, Opc4a0, Opc4a8, Opc4b0, Opc4b8, + Opc4c0, IllIns, Opc4d0, Opc4d8, Opc4e0, Opc4e8, Opc4f0, Opc4f8, + Opc500, Opc508, Opc510, Opc518, Opc520, Opc528, Opc530, Opc538, + Opc540, Opc548, Opc550, Opc558, Opc560, Opc568, Opc570, Opc578, + IllIns, Opc588, Opc590, Opc598, Opc5a0, Opc5a8, Opc5b0, Opc5b8, + Opc5c0, IllIns, Opc5d0, Opc5d8, Opc5e0, Opc5e8, Opc5f0, Opc5f8, + Opc600, IllIns, Opc610, Opc618, Opc620, Opc628, Opc630, Opc638, + Opc640, IllIns, Opc650, Opc658, Opc660, Opc668, Opc670, Opc678, + Opc680, IllIns, Opc690, Opc698, Opc6a0, Opc6a8, Opc6b0, Opc6b8, + Opc6c0, IllIns, Opc6d0, Opc6d8, Opc6e0, Opc6e8, Opc6f0, Opc6f8, + Opc700, Opc708, Opc710, Opc718, Opc720, Opc728, Opc730, Opc738, + Opc740, Opc748, Opc750, Opc758, Opc760, Opc768, Opc770, Opc778, + IllIns, Opc788, Opc790, Opc798, Opc7a0, Opc7a8, Opc7b0, Opc7b8, + Opc7c0, IllIns, Opc7d0, Opc7d8, Opc7e0, Opc7e8, Opc7f0, Opc7f8, + Opc800, IllIns, Opc810, Opc818, Opc820, Opc828, Opc830, Opc838, + Opc840, IllIns, Opc850, Opc858, Opc860, Opc868, Opc870, Opc878, + Opc880, IllIns, Opc890, Opc898, Opc8a0, Opc8a8, Opc8b0, Opc8b8, + Opc8c0, IllIns, Opc8d0, Opc8d8, Opc8e0, Opc8e8, Opc8f0, Opc8f8, + Opc900, Opc908, Opc910, Opc918, Opc920, Opc928, Opc930, Opc938, + Opc940, Opc948, Opc950, Opc958, Opc960, Opc968, Opc970, Opc978, + IllIns, Opc988, Opc990, Opc998, Opc9a0, Opc9a8, Opc9b0, Opc9b8, + Opc9c0, IllIns, Opc9d0, Opc9d8, Opc9e0, Opc9e8, Opc9f0, Opc9f8, + Opca00, IllIns, Opca10, Opca18, Opca20, Opca28, Opca30, Opca38, + Opca40, IllIns, Opca50, Opca58, Opca60, Opca68, Opca70, Opca78, + Opca80, IllIns, Opca90, Opca98, Opcaa0, Opcaa8, Opcab0, Opcab8, + Opcac0, IllIns, Opcad0, Opcad8, Opcae0, Opcae8, Opcaf0, Opcaf8, + Opcb00, Opcb08, Opcb10, Opcb18, Opcb20, Opcb28, Opcb30, Opcb38, + Opcb40, Opcb48, Opcb50, Opcb58, Opcb60, Opcb68, Opcb70, Opcb78, + IllIns, Opcb88, Opcb90, Opcb98, Opcba0, Opcba8, Opcbb0, Opcbb8, + Opcbc0, IllIns, Opcbd0, Opcbd8, Opcbe0, Opcbe8, Opcbf0, Opcbf8, + Opcc00, IllIns, Opcc10, Opcc18, Opcc20, Opcc28, Opcc30, Opcc38, + Opcc40, IllIns, Opcc50, Opcc58, Opcc60, Opcc68, Opcc70, Opcc78, + Opcc80, IllIns, Opcc90, Opcc98, Opcca0, Opcca8, Opccb0, Opccb8, + Opccc0, IllIns, Opccd0, Opccd8, Opcce0, Opcce8, Opccf0, Opccf8, + Opcd00, Opcd08, Opcd10, Opcd18, Opcd20, Opcd28, Opcd30, Opcd38, + Opcd40, Opcd48, Opcd50, Opcd58, Opcd60, Opcd68, Opcd70, Opcd78, + IllIns, Opcd88, Opcd90, Opcd98, Opcda0, Opcda8, Opcdb0, Opcdb8, + Opcdc0, IllIns, Opcdd0, Opcdd8, Opcde0, Opcde8, Opcdf0, Opcdf8, + Opce00, IllIns, Opce10, Opce18, Opce20, Opce28, Opce30, Opce38, + Opce40, IllIns, Opce50, Opce58, Opce60, Opce68, Opce70, Opce78, + Opce80, IllIns, Opce90, Opce98, Opcea0, Opcea8, Opceb0, Opceb8, + Opcec0, IllIns, Opced0, Opced8, Opcee0, Opcee8, Opcef0, Opcef8, + Opcf00, Opcf08, Opcf10, Opcf18, Opcf20, Opcf28, Opcf30, Opcf38, + Opcf40, Opcf48, Opcf50, Opcf58, Opcf60, Opcf68, Opcf70, Opcf78, + IllIns, Opcf88, Opcf90, Opcf98, Opcfa0, Opcfa8, Opcfb0, Opcfb8, + Opcfc0, IllIns, Opcfd0, Opcfd8, Opcfe0, Opcfe8, Opcff0, Opcff8, + + /* D000 */ + Opd000, IllIns, Opd010, Opd018, Opd020, Opd028, Opd030, Opd038, + Opd040, Opd048, Opd050, Opd058, Opd060, Opd068, Opd070, Opd078, + Opd080, Opd088, Opd090, Opd098, Opd0a0, Opd0a8, Opd0b0, Opd0b8, + Opd0c0, Opd0c8, Opd0d0, Opd0d8, Opd0e0, Opd0e8, Opd0f0, Opd0f8, + Opd100, Opd108, Opd110, Opd118, Opd120, Opd128, Opd130, Opd138, + Opd140, Opd148, Opd150, Opd158, Opd160, Opd168, Opd170, Opd178, + Opd180, Opd188, Opd190, Opd198, Opd1a0, Opd1a8, Opd1b0, Opd1b8, + Opd1c0, Opd1c8, Opd1d0, Opd1d8, Opd1e0, Opd1e8, Opd1f0, Opd1f8, + Opd200, IllIns, Opd210, Opd218, Opd220, Opd228, Opd230, Opd238, + Opd240, Opd248, Opd250, Opd258, Opd260, Opd268, Opd270, Opd278, + Opd280, Opd288, Opd290, Opd298, Opd2a0, Opd2a8, Opd2b0, Opd2b8, + Opd2c0, Opd2c8, Opd2d0, Opd2d8, Opd2e0, Opd2e8, Opd2f0, Opd2f8, + Opd300, Opd308, Opd310, Opd318, Opd320, Opd328, Opd330, Opd338, + Opd340, Opd348, Opd350, Opd358, Opd360, Opd368, Opd370, Opd378, + Opd380, Opd388, Opd390, Opd398, Opd3a0, Opd3a8, Opd3b0, Opd3b8, + Opd3c0, Opd3c8, Opd3d0, Opd3d8, Opd3e0, Opd3e8, Opd3f0, Opd3f8, + Opd400, IllIns, Opd410, Opd418, Opd420, Opd428, Opd430, Opd438, + Opd440, Opd448, Opd450, Opd458, Opd460, Opd468, Opd470, Opd478, + Opd480, Opd488, Opd490, Opd498, Opd4a0, Opd4a8, Opd4b0, Opd4b8, + Opd4c0, Opd4c8, Opd4d0, Opd4d8, Opd4e0, Opd4e8, Opd4f0, Opd4f8, + Opd500, Opd508, Opd510, Opd518, Opd520, Opd528, Opd530, Opd538, + Opd540, Opd548, Opd550, Opd558, Opd560, Opd568, Opd570, Opd578, + Opd580, Opd588, Opd590, Opd598, Opd5a0, Opd5a8, Opd5b0, Opd5b8, + Opd5c0, Opd5c8, Opd5d0, Opd5d8, Opd5e0, Opd5e8, Opd5f0, Opd5f8, + Opd600, IllIns, Opd610, Opd618, Opd620, Opd628, Opd630, Opd638, + Opd640, Opd648, Opd650, Opd658, Opd660, Opd668, Opd670, Opd678, + Opd680, Opd688, Opd690, Opd698, Opd6a0, Opd6a8, Opd6b0, Opd6b8, + Opd6c0, Opd6c8, Opd6d0, Opd6d8, Opd6e0, Opd6e8, Opd6f0, Opd6f8, + Opd700, Opd708, Opd710, Opd718, Opd720, Opd728, Opd730, Opd738, + Opd740, Opd748, Opd750, Opd758, Opd760, Opd768, Opd770, Opd778, + Opd780, Opd788, Opd790, Opd798, Opd7a0, Opd7a8, Opd7b0, Opd7b8, + Opd7c0, Opd7c8, Opd7d0, Opd7d8, Opd7e0, Opd7e8, Opd7f0, Opd7f8, + Opd800, IllIns, Opd810, Opd818, Opd820, Opd828, Opd830, Opd838, + Opd840, Opd848, Opd850, Opd858, Opd860, Opd868, Opd870, Opd878, + Opd880, Opd888, Opd890, Opd898, Opd8a0, Opd8a8, Opd8b0, Opd8b8, + Opd8c0, Opd8c8, Opd8d0, Opd8d8, Opd8e0, Opd8e8, Opd8f0, Opd8f8, + Opd900, Opd908, Opd910, Opd918, Opd920, Opd928, Opd930, Opd938, + Opd940, Opd948, Opd950, Opd958, Opd960, Opd968, Opd970, Opd978, + Opd980, Opd988, Opd990, Opd998, Opd9a0, Opd9a8, Opd9b0, Opd9b8, + Opd9c0, Opd9c8, Opd9d0, Opd9d8, Opd9e0, Opd9e8, Opd9f0, Opd9f8, + Opda00, IllIns, Opda10, Opda18, Opda20, Opda28, Opda30, Opda38, + Opda40, Opda48, Opda50, Opda58, Opda60, Opda68, Opda70, Opda78, + Opda80, Opda88, Opda90, Opda98, Opdaa0, Opdaa8, Opdab0, Opdab8, + Opdac0, Opdac8, Opdad0, Opdad8, Opdae0, Opdae8, Opdaf0, Opdaf8, + Opdb00, Opdb08, Opdb10, Opdb18, Opdb20, Opdb28, Opdb30, Opdb38, + Opdb40, Opdb48, Opdb50, Opdb58, Opdb60, Opdb68, Opdb70, Opdb78, + Opdb80, Opdb88, Opdb90, Opdb98, Opdba0, Opdba8, Opdbb0, Opdbb8, + Opdbc0, Opdbc8, Opdbd0, Opdbd8, Opdbe0, Opdbe8, Opdbf0, Opdbf8, + Opdc00, IllIns, Opdc10, Opdc18, Opdc20, Opdc28, Opdc30, Opdc38, + Opdc40, Opdc48, Opdc50, Opdc58, Opdc60, Opdc68, Opdc70, Opdc78, + Opdc80, Opdc88, Opdc90, Opdc98, Opdca0, Opdca8, Opdcb0, Opdcb8, + Opdcc0, Opdcc8, Opdcd0, Opdcd8, Opdce0, Opdce8, Opdcf0, Opdcf8, + Opdd00, Opdd08, Opdd10, Opdd18, Opdd20, Opdd28, Opdd30, Opdd38, + Opdd40, Opdd48, Opdd50, Opdd58, Opdd60, Opdd68, Opdd70, Opdd78, + Opdd80, Opdd88, Opdd90, Opdd98, Opdda0, Opdda8, Opddb0, Opddb8, + Opddc0, Opddc8, Opddd0, Opddd8, Opdde0, Opdde8, Opddf0, Opddf8, + Opde00, IllIns, Opde10, Opde18, Opde20, Opde28, Opde30, Opde38, + Opde40, Opde48, Opde50, Opde58, Opde60, Opde68, Opde70, Opde78, + Opde80, Opde88, Opde90, Opde98, Opdea0, Opdea8, Opdeb0, Opdeb8, + Opdec0, Opdec8, Opded0, Opded8, Opdee0, Opdee8, Opdef0, Opdef8, + Opdf00, Opdf08, Opdf10, Opdf18, Opdf20, Opdf28, Opdf30, Opdf38, + Opdf40, Opdf48, Opdf50, Opdf58, Opdf60, Opdf68, Opdf70, Opdf78, + Opdf80, Opdf88, Opdf90, Opdf98, Opdfa0, Opdfa8, Opdfb0, Opdfb8, + Opdfc0, Opdfc8, Opdfd0, Opdfd8, Opdfe0, Opdfe8, Opdff0, Opdff8, + + /* E000 */ + Ope000, Ope008, Ope010, Ope018, Ope020, Ope028, Ope030, Ope038, + Ope040, Ope048, Ope050, Ope058, Ope060, Ope068, Ope070, Ope078, + Ope080, Ope088, Ope090, Ope098, Ope0a0, Ope0a8, Ope0b0, Ope0b8, + IllIns, IllIns, Ope0d0, Ope0d8, Ope0e0, Ope0e8, Ope0f0, Ope0f8, + Ope100, Ope108, Ope110, Ope118, Ope120, Ope128, Ope130, Ope138, + Ope140, Ope148, Ope150, Ope158, Ope160, Ope168, Ope170, Ope178, + Ope180, Ope188, Ope190, Ope198, Ope1a0, Ope1a8, Ope1b0, Ope1b8, + IllIns, IllIns, Ope1d0, Ope1d8, Ope1e0, Ope1e8, Ope1f0, Ope1f8, + Ope200, Ope208, Ope210, Ope218, Ope220, Ope228, Ope230, Ope238, + Ope240, Ope248, Ope250, Ope258, Ope260, Ope268, Ope270, Ope278, + Ope280, Ope288, Ope290, Ope298, Ope2a0, Ope2a8, Ope2b0, Ope2b8, + IllIns, IllIns, Ope2d0, Ope2d8, Ope2e0, Ope2e8, Ope2f0, Ope2f8, + Ope300, Ope308, Ope310, Ope318, Ope320, Ope328, Ope330, Ope338, + Ope340, Ope348, Ope350, Ope358, Ope360, Ope368, Ope370, Ope378, + Ope380, Ope388, Ope390, Ope398, Ope3a0, Ope3a8, Ope3b0, Ope3b8, + IllIns, IllIns, Ope3d0, Ope3d8, Ope3e0, Ope3e8, Ope3f0, Ope3f8, + Ope400, Ope408, Ope410, Ope418, Ope420, Ope428, Ope430, Ope438, + Ope440, Ope448, Ope450, Ope458, Ope460, Ope468, Ope470, Ope478, + Ope480, Ope488, Ope490, Ope498, Ope4a0, Ope4a8, Ope4b0, Ope4b8, + IllIns, IllIns, Ope4d0, Ope4d8, Ope4e0, Ope4e8, Ope4f0, Ope4f8, + Ope500, Ope508, Ope510, Ope518, Ope520, Ope528, Ope530, Ope538, + Ope540, Ope548, Ope550, Ope558, Ope560, Ope568, Ope570, Ope578, + Ope580, Ope588, Ope590, Ope598, Ope5a0, Ope5a8, Ope5b0, Ope5b8, + IllIns, IllIns, Ope5d0, Ope5d8, Ope5e0, Ope5e8, Ope5f0, Ope5f8, + Ope600, Ope608, Ope610, Ope618, Ope620, Ope628, Ope630, Ope638, + Ope640, Ope648, Ope650, Ope658, Ope660, Ope668, Ope670, Ope678, + Ope680, Ope688, Ope690, Ope698, Ope6a0, Ope6a8, Ope6b0, Ope6b8, + IllIns, IllIns, Ope6d0, Ope6d8, Ope6e0, Ope6e8, Ope6f0, Ope6f8, + Ope700, Ope708, Ope710, Ope718, Ope720, Ope728, Ope730, Ope738, + Ope740, Ope748, Ope750, Ope758, Ope760, Ope768, Ope770, Ope778, + Ope780, Ope788, Ope790, Ope798, Ope7a0, Ope7a8, Ope7b0, Ope7b8, + IllIns, IllIns, Ope7d0, Ope7d8, Ope7e0, Ope7e8, Ope7f0, Ope7f8, + Ope800, Ope808, Ope810, Ope818, Ope820, Ope828, Ope830, Ope838, + Ope840, Ope848, Ope850, Ope858, Ope860, Ope868, Ope870, Ope878, + Ope880, Ope888, Ope890, Ope898, Ope8a0, Ope8a8, Ope8b0, Ope8b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Ope900, Ope908, Ope910, Ope918, Ope920, Ope928, Ope930, Ope938, + Ope940, Ope948, Ope950, Ope958, Ope960, Ope968, Ope970, Ope978, + Ope980, Ope988, Ope990, Ope998, Ope9a0, Ope9a8, Ope9b0, Ope9b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opea00, Opea08, Opea10, Opea18, Opea20, Opea28, Opea30, Opea38, + Opea40, Opea48, Opea50, Opea58, Opea60, Opea68, Opea70, Opea78, + Opea80, Opea88, Opea90, Opea98, Opeaa0, Opeaa8, Opeab0, Opeab8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opeb00, Opeb08, Opeb10, Opeb18, Opeb20, Opeb28, Opeb30, Opeb38, + Opeb40, Opeb48, Opeb50, Opeb58, Opeb60, Opeb68, Opeb70, Opeb78, + Opeb80, Opeb88, Opeb90, Opeb98, Opeba0, Opeba8, Opebb0, Opebb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opec00, Opec08, Opec10, Opec18, Opec20, Opec28, Opec30, Opec38, + Opec40, Opec48, Opec50, Opec58, Opec60, Opec68, Opec70, Opec78, + Opec80, Opec88, Opec90, Opec98, Opeca0, Opeca8, Opecb0, Opecb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Oped00, Oped08, Oped10, Oped18, Oped20, Oped28, Oped30, Oped38, + Oped40, Oped48, Oped50, Oped58, Oped60, Oped68, Oped70, Oped78, + Oped80, Oped88, Oped90, Oped98, Opeda0, Opeda8, Opedb0, Opedb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opee00, Opee08, Opee10, Opee18, Opee20, Opee28, Opee30, Opee38, + Opee40, Opee48, Opee50, Opee58, Opee60, Opee68, Opee70, Opee78, + Opee80, Opee88, Opee90, Opee98, Opeea0, Opeea8, Opeeb0, Opeeb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opef00, Opef08, Opef10, Opef18, Opef20, Opef28, Opef30, Opef38, + Opef40, Opef48, Opef50, Opef58, Opef60, Opef68, Opef70, Opef78, + Opef80, Opef88, Opef90, Opef98, Opefa0, Opefa8, Opefb0, Opefb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* F000 */ + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F +}; diff --git a/MCUME_esp32/espcastaway/main/68korigbad/op68010.h b/MCUME_esp32/espcastaway/main/68korigbad/op68010.h new file mode 100755 index 0000000..abdb521 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/op68010.h @@ -0,0 +1,1066 @@ +#include "operin.h" + +/* + * Castaway + * (C) 1994 - 2002 Martin Doering, Joachim Hoenig + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ +const unsigned long (*jmp_table[8192])(operin) = { + /* 0000 */ + Op0000, IllIns, Op0010, Op0018, Op0020, Op0028, Op0030, Op0038, + Op0040, IllIns, Op0050, Op0058, Op0060, Op0068, Op0070, Op0078, + Op0080, IllIns, Op0090, Op0098, Op00a0, Op00a8, Op00b0, Op00b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0100, Op0108, Op0110, Op0118, Op0120, Op0128, Op0130, Op0138, + Op0140, Op0148, Op0150, Op0158, Op0160, Op0168, Op0170, Op0178, + Op0180, Op0188, Op0190, Op0198, Op01a0, Op01a8, Op01b0, Op01b8, + Op01c0, Op01c8, Op01d0, Op01d8, Op01e0, Op01e8, Op01f0, Op01f8, + Op0200, IllIns, Op0210, Op0218, Op0220, Op0228, Op0230, Op0238, + Op0240, IllIns, Op0250, Op0258, Op0260, Op0268, Op0270, Op0278, + Op0280, IllIns, Op0290, Op0298, Op02a0, Op02a8, Op02b0, Op02b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0300, Op0308, Op0310, Op0318, Op0320, Op0328, Op0330, Op0338, + Op0340, Op0348, Op0350, Op0358, Op0360, Op0368, Op0370, Op0378, + Op0380, Op0388, Op0390, Op0398, Op03a0, Op03a8, Op03b0, Op03b8, + Op03c0, Op03c8, Op03d0, Op03d8, Op03e0, Op03e8, Op03f0, Op03f8, + Op0400, IllIns, Op0410, Op0418, Op0420, Op0428, Op0430, Op0438, + Op0440, IllIns, Op0450, Op0458, Op0460, Op0468, Op0470, Op0478, + Op0480, IllIns, Op0490, Op0498, Op04a0, Op04a8, Op04b0, Op04b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0500, Op0508, Op0510, Op0518, Op0520, Op0528, Op0530, Op0538, + Op0540, Op0548, Op0550, Op0558, Op0560, Op0568, Op0570, Op0578, + Op0580, Op0588, Op0590, Op0598, Op05a0, Op05a8, Op05b0, Op05b8, + Op05c0, Op05c8, Op05d0, Op05d8, Op05e0, Op05e8, Op05f0, Op05f8, + Op0600, IllIns, Op0610, Op0618, Op0620, Op0628, Op0630, Op0638, + Op0640, IllIns, Op0650, Op0658, Op0660, Op0668, Op0670, Op0678, + Op0680, IllIns, Op0690, Op0698, Op06a0, Op06a8, Op06b0, Op06b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0700, Op0708, Op0710, Op0718, Op0720, Op0728, Op0730, Op0738, + Op0740, Op0748, Op0750, Op0758, Op0760, Op0768, Op0770, Op0778, + Op0780, Op0788, Op0790, Op0798, Op07a0, Op07a8, Op07b0, Op07b8, + Op07c0, Op07c8, Op07d0, Op07d8, Op07e0, Op07e8, Op07f0, Op07f8, + Op0800, IllIns, Op0810, Op0818, Op0820, Op0828, Op0830, Op0838, + Op0840, IllIns, Op0850, Op0858, Op0860, Op0868, Op0870, Op0878, + Op0880, IllIns, Op0890, Op0898, Op08a0, Op08a8, Op08b0, Op08b8, + Op08c0, IllIns, Op08d0, Op08d8, Op08e0, Op08e8, Op08f0, Op08f8, + Op0900, Op0908, Op0910, Op0918, Op0920, Op0928, Op0930, Op0938, + Op0940, Op0948, Op0950, Op0958, Op0960, Op0968, Op0970, Op0978, + Op0980, Op0988, Op0990, Op0998, Op09a0, Op09a8, Op09b0, Op09b8, + Op09c0, Op09c8, Op09d0, Op09d8, Op09e0, Op09e8, Op09f0, Op09f8, + Op0a00, IllIns, Op0a10, Op0a18, Op0a20, Op0a28, Op0a30, Op0a38, + Op0a40, IllIns, Op0a50, Op0a58, Op0a60, Op0a68, Op0a70, Op0a78, + Op0a80, IllIns, Op0a90, Op0a98, Op0aa0, Op0aa8, Op0ab0, Op0ab8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0b00, Op0b08, Op0b10, Op0b18, Op0b20, Op0b28, Op0b30, Op0b38, + Op0b40, Op0b48, Op0b50, Op0b58, Op0b60, Op0b68, Op0b70, Op0b78, + Op0b80, Op0b88, Op0b90, Op0b98, Op0ba0, Op0ba8, Op0bb0, Op0bb8, + Op0bc0, Op0bc8, Op0bd0, Op0bd8, Op0be0, Op0be8, Op0bf0, Op0bf8, + Op0c00, IllIns, Op0c10, Op0c18, Op0c20, Op0c28, Op0c30, Op0c38, + Op0c40, IllIns, Op0c50, Op0c58, Op0c60, Op0c68, Op0c70, Op0c78, + Op0c80, IllIns, Op0c90, Op0c98, Op0ca0, Op0ca8, Op0cb0, Op0cb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0d00, Op0d08, Op0d10, Op0d18, Op0d20, Op0d28, Op0d30, Op0d38, + Op0d40, Op0d48, Op0d50, Op0d58, Op0d60, Op0d68, Op0d70, Op0d78, + Op0d80, Op0d88, Op0d90, Op0d98, Op0da0, Op0da8, Op0db0, Op0db8, + Op0dc0, Op0dc8, Op0dd0, Op0dd8, Op0de0, Op0de8, Op0df0, Op0df8, + IllIns, IllIns, Op0e10, Op0e18, Op0e20, Op0e28, Op0e30, Op0e38, + IllIns, IllIns, Op0e50, Op0e58, Op0e60, Op0e68, Op0e70, Op0e78, + IllIns, IllIns, Op0e90, Op0e98, Op0ea0, Op0ea8, Op0eb0, Op0eb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op0f00, Op0f08, Op0f10, Op0f18, Op0f20, Op0f28, Op0f30, Op0f38, + Op0f40, Op0f48, Op0f50, Op0f58, Op0f60, Op0f68, Op0f70, Op0f78, + Op0f80, Op0f88, Op0f90, Op0f98, Op0fa0, Op0fa8, Op0fb0, Op0fb8, + Op0fc0, Op0fc8, Op0fd0, Op0fd8, Op0fe0, Op0fe8, Op0ff0, Op0ff8, + + /* 1000 */ + Op1000, IllIns, Op1010, Op1018, Op1020, Op1028, Op1030, Op1038, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1080, IllIns, Op1090, Op1098, Op10a0, Op10a8, Op10b0, Op10b8, + Op10c0, IllIns, Op10d0, Op10d8, Op10e0, Op10e8, Op10f0, Op10f8, + Op1100, IllIns, Op1110, Op1118, Op1120, Op1128, Op1130, Op1138, + Op1140, IllIns, Op1150, Op1158, Op1160, Op1168, Op1170, Op1178, + Op1180, IllIns, Op1190, Op1198, Op11a0, Op11a8, Op11b0, Op11b8, + Op11c0, IllIns, Op11d0, Op11d8, Op11e0, Op11e8, Op11f0, Op11f8, + Op1200, IllIns, Op1210, Op1218, Op1220, Op1228, Op1230, Op1238, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1280, IllIns, Op1290, Op1298, Op12a0, Op12a8, Op12b0, Op12b8, + Op12c0, IllIns, Op12d0, Op12d8, Op12e0, Op12e8, Op12f0, Op12f8, + Op1300, IllIns, Op1310, Op1318, Op1320, Op1328, Op1330, Op1338, + Op1340, IllIns, Op1350, Op1358, Op1360, Op1368, Op1370, Op1378, + Op1380, IllIns, Op1390, Op1398, Op13a0, Op13a8, Op13b0, Op13b8, + Op13c0, IllIns, Op13d0, Op13d8, Op13e0, Op13e8, Op13f0, Op13f8, + Op1400, IllIns, Op1410, Op1418, Op1420, Op1428, Op1430, Op1438, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1480, IllIns, Op1490, Op1498, Op14a0, Op14a8, Op14b0, Op14b8, + Op14c0, IllIns, Op14d0, Op14d8, Op14e0, Op14e8, Op14f0, Op14f8, + Op1500, IllIns, Op1510, Op1518, Op1520, Op1528, Op1530, Op1538, + Op1540, IllIns, Op1550, Op1558, Op1560, Op1568, Op1570, Op1578, + Op1580, IllIns, Op1590, Op1598, Op15a0, Op15a8, Op15b0, Op15b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1600, IllIns, Op1610, Op1618, Op1620, Op1628, Op1630, Op1638, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1680, IllIns, Op1690, Op1698, Op16a0, Op16a8, Op16b0, Op16b8, + Op16c0, IllIns, Op16d0, Op16d8, Op16e0, Op16e8, Op16f0, Op16f8, + Op1700, IllIns, Op1710, Op1718, Op1720, Op1728, Op1730, Op1738, + Op1740, IllIns, Op1750, Op1758, Op1760, Op1768, Op1770, Op1778, + Op1780, IllIns, Op1790, Op1798, Op17a0, Op17a8, Op17b0, Op17b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1800, IllIns, Op1810, Op1818, Op1820, Op1828, Op1830, Op1838, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1880, IllIns, Op1890, Op1898, Op18a0, Op18a8, Op18b0, Op18b8, + Op18c0, IllIns, Op18d0, Op18d8, Op18e0, Op18e8, Op18f0, Op18f8, + Op1900, IllIns, Op1910, Op1918, Op1920, Op1928, Op1930, Op1938, + Op1940, IllIns, Op1950, Op1958, Op1960, Op1968, Op1970, Op1978, + Op1980, IllIns, Op1990, Op1998, Op19a0, Op19a8, Op19b0, Op19b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1a00, IllIns, Op1a10, Op1a18, Op1a20, Op1a28, Op1a30, Op1a38, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1a80, IllIns, Op1a90, Op1a98, Op1aa0, Op1aa8, Op1ab0, Op1ab8, + Op1ac0, IllIns, Op1ad0, Op1ad8, Op1ae0, Op1ae8, Op1af0, Op1af8, + Op1b00, IllIns, Op1b10, Op1b18, Op1b20, Op1b28, Op1b30, Op1b38, + Op1b40, IllIns, Op1b50, Op1b58, Op1b60, Op1b68, Op1b70, Op1b78, + Op1b80, IllIns, Op1b90, Op1b98, Op1ba0, Op1ba8, Op1bb0, Op1bb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1c00, IllIns, Op1c10, Op1c18, Op1c20, Op1c28, Op1c30, Op1c38, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1c80, IllIns, Op1c90, Op1c98, Op1ca0, Op1ca8, Op1cb0, Op1cb8, + Op1cc0, IllIns, Op1cd0, Op1cd8, Op1ce0, Op1ce8, Op1cf0, Op1cf8, + Op1d00, IllIns, Op1d10, Op1d18, Op1d20, Op1d28, Op1d30, Op1d38, + Op1d40, IllIns, Op1d50, Op1d58, Op1d60, Op1d68, Op1d70, Op1d78, + Op1d80, IllIns, Op1d90, Op1d98, Op1da0, Op1da8, Op1db0, Op1db8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1e00, IllIns, Op1e10, Op1e18, Op1e20, Op1e28, Op1e30, Op1e38, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op1e80, IllIns, Op1e90, Op1e98, Op1ea0, Op1ea8, Op1eb0, Op1eb8, + Op1ec0, IllIns, Op1ed0, Op1ed8, Op1ee0, Op1ee8, Op1ef0, Op1ef8, + Op1f00, IllIns, Op1f10, Op1f18, Op1f20, Op1f28, Op1f30, Op1f38, + Op1f40, IllIns, Op1f50, Op1f58, Op1f60, Op1f68, Op1f70, Op1f78, + Op1f80, IllIns, Op1f90, Op1f98, Op1fa0, Op1fa8, Op1fb0, Op1fb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 2000 */ + Op2000, Op2008, Op2010, Op2018, Op2020, Op2028, Op2030, Op2038, + Op2040, Op2048, Op2050, Op2058, Op2060, Op2068, Op2070, Op2078, + Op2080, Op2088, Op2090, Op2098, Op20a0, Op20a8, Op20b0, Op20b8, + Op20c0, Op20c8, Op20d0, Op20d8, Op20e0, Op20e8, Op20f0, Op20f8, + Op2100, Op2108, Op2110, Op2118, Op2120, Op2128, Op2130, Op2138, + Op2140, Op2148, Op2150, Op2158, Op2160, Op2168, Op2170, Op2178, + Op2180, Op2188, Op2190, Op2198, Op21a0, Op21a8, Op21b0, Op21b8, + Op21c0, Op21c8, Op21d0, Op21d8, Op21e0, Op21e8, Op21f0, Op21f8, + Op2200, Op2208, Op2210, Op2218, Op2220, Op2228, Op2230, Op2238, + Op2240, Op2248, Op2250, Op2258, Op2260, Op2268, Op2270, Op2278, + Op2280, Op2288, Op2290, Op2298, Op22a0, Op22a8, Op22b0, Op22b8, + Op22c0, Op22c8, Op22d0, Op22d8, Op22e0, Op22e8, Op22f0, Op22f8, + Op2300, Op2308, Op2310, Op2318, Op2320, Op2328, Op2330, Op2338, + Op2340, Op2348, Op2350, Op2358, Op2360, Op2368, Op2370, Op2378, + Op2380, Op2388, Op2390, Op2398, Op23a0, Op23a8, Op23b0, Op23b8, + Op23c0, Op23c8, Op23d0, Op23d8, Op23e0, Op23e8, Op23f0, Op23f8, + Op2400, Op2408, Op2410, Op2418, Op2420, Op2428, Op2430, Op2438, + Op2440, Op2448, Op2450, Op2458, Op2460, Op2468, Op2470, Op2478, + Op2480, Op2488, Op2490, Op2498, Op24a0, Op24a8, Op24b0, Op24b8, + Op24c0, Op24c8, Op24d0, Op24d8, Op24e0, Op24e8, Op24f0, Op24f8, + Op2500, Op2508, Op2510, Op2518, Op2520, Op2528, Op2530, Op2538, + Op2540, Op2548, Op2550, Op2558, Op2560, Op2568, Op2570, Op2578, + Op2580, Op2588, Op2590, Op2598, Op25a0, Op25a8, Op25b0, Op25b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2600, Op2608, Op2610, Op2618, Op2620, Op2628, Op2630, Op2638, + Op2640, Op2648, Op2650, Op2658, Op2660, Op2668, Op2670, Op2678, + Op2680, Op2688, Op2690, Op2698, Op26a0, Op26a8, Op26b0, Op26b8, + Op26c0, Op26c8, Op26d0, Op26d8, Op26e0, Op26e8, Op26f0, Op26f8, + Op2700, Op2708, Op2710, Op2718, Op2720, Op2728, Op2730, Op2738, + Op2740, Op2748, Op2750, Op2758, Op2760, Op2768, Op2770, Op2778, + Op2780, Op2788, Op2790, Op2798, Op27a0, Op27a8, Op27b0, Op27b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2800, Op2808, Op2810, Op2818, Op2820, Op2828, Op2830, Op2838, + Op2840, Op2848, Op2850, Op2858, Op2860, Op2868, Op2870, Op2878, + Op2880, Op2888, Op2890, Op2898, Op28a0, Op28a8, Op28b0, Op28b8, + Op28c0, Op28c8, Op28d0, Op28d8, Op28e0, Op28e8, Op28f0, Op28f8, + Op2900, Op2908, Op2910, Op2918, Op2920, Op2928, Op2930, Op2938, + Op2940, Op2948, Op2950, Op2958, Op2960, Op2968, Op2970, Op2978, + Op2980, Op2988, Op2990, Op2998, Op29a0, Op29a8, Op29b0, Op29b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2a00, Op2a08, Op2a10, Op2a18, Op2a20, Op2a28, Op2a30, Op2a38, + Op2a40, Op2a48, Op2a50, Op2a58, Op2a60, Op2a68, Op2a70, Op2a78, + Op2a80, Op2a88, Op2a90, Op2a98, Op2aa0, Op2aa8, Op2ab0, Op2ab8, + Op2ac0, Op2ac8, Op2ad0, Op2ad8, Op2ae0, Op2ae8, Op2af0, Op2af8, + Op2b00, Op2b08, Op2b10, Op2b18, Op2b20, Op2b28, Op2b30, Op2b38, + Op2b40, Op2b48, Op2b50, Op2b58, Op2b60, Op2b68, Op2b70, Op2b78, + Op2b80, Op2b88, Op2b90, Op2b98, Op2ba0, Op2ba8, Op2bb0, Op2bb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2c00, Op2c08, Op2c10, Op2c18, Op2c20, Op2c28, Op2c30, Op2c38, + Op2c40, Op2c48, Op2c50, Op2c58, Op2c60, Op2c68, Op2c70, Op2c78, + Op2c80, Op2c88, Op2c90, Op2c98, Op2ca0, Op2ca8, Op2cb0, Op2cb8, + Op2cc0, Op2cc8, Op2cd0, Op2cd8, Op2ce0, Op2ce8, Op2cf0, Op2cf8, + Op2d00, Op2d08, Op2d10, Op2d18, Op2d20, Op2d28, Op2d30, Op2d38, + Op2d40, Op2d48, Op2d50, Op2d58, Op2d60, Op2d68, Op2d70, Op2d78, + Op2d80, Op2d88, Op2d90, Op2d98, Op2da0, Op2da8, Op2db0, Op2db8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op2e00, Op2e08, Op2e10, Op2e18, Op2e20, Op2e28, Op2e30, Op2e38, + Op2e40, Op2e48, Op2e50, Op2e58, Op2e60, Op2e68, Op2e70, Op2e78, + Op2e80, Op2e88, Op2e90, Op2e98, Op2ea0, Op2ea8, Op2eb0, Op2eb8, + Op2ec0, Op2ec8, Op2ed0, Op2ed8, Op2ee0, Op2ee8, Op2ef0, Op2ef8, + Op2f00, Op2f08, Op2f10, Op2f18, Op2f20, Op2f28, Op2f30, Op2f38, + Op2f40, Op2f48, Op2f50, Op2f58, Op2f60, Op2f68, Op2f70, Op2f78, + Op2f80, Op2f88, Op2f90, Op2f98, Op2fa0, Op2fa8, Op2fb0, Op2fb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 3000 */ + Op3000, Op3008, Op3010, Op3018, Op3020, Op3028, Op3030, Op3038, + Op3040, Op3048, Op3050, Op3058, Op3060, Op3068, Op3070, Op3078, + Op3080, Op3088, Op3090, Op3098, Op30a0, Op30a8, Op30b0, Op30b8, + Op30c0, Op30c8, Op30d0, Op30d8, Op30e0, Op30e8, Op30f0, Op30f8, + Op3100, Op3108, Op3110, Op3118, Op3120, Op3128, Op3130, Op3138, + Op3140, Op3148, Op3150, Op3158, Op3160, Op3168, Op3170, Op3178, + Op3180, Op3188, Op3190, Op3198, Op31a0, Op31a8, Op31b0, Op31b8, + Op31c0, Op31c8, Op31d0, Op31d8, Op31e0, Op31e8, Op31f0, Op31f8, + Op3200, Op3208, Op3210, Op3218, Op3220, Op3228, Op3230, Op3238, + Op3240, Op3248, Op3250, Op3258, Op3260, Op3268, Op3270, Op3278, + Op3280, Op3288, Op3290, Op3298, Op32a0, Op32a8, Op32b0, Op32b8, + Op32c0, Op32c8, Op32d0, Op32d8, Op32e0, Op32e8, Op32f0, Op32f8, + Op3300, Op3308, Op3310, Op3318, Op3320, Op3328, Op3330, Op3338, + Op3340, Op3348, Op3350, Op3358, Op3360, Op3368, Op3370, Op3378, + Op3380, Op3388, Op3390, Op3398, Op33a0, Op33a8, Op33b0, Op33b8, + Op33c0, Op33c8, Op33d0, Op33d8, Op33e0, Op33e8, Op33f0, Op33f8, + Op3400, Op3408, Op3410, Op3418, Op3420, Op3428, Op3430, Op3438, + Op3440, Op3448, Op3450, Op3458, Op3460, Op3468, Op3470, Op3478, + Op3480, Op3488, Op3490, Op3498, Op34a0, Op34a8, Op34b0, Op34b8, + Op34c0, Op34c8, Op34d0, Op34d8, Op34e0, Op34e8, Op34f0, Op34f8, + Op3500, Op3508, Op3510, Op3518, Op3520, Op3528, Op3530, Op3538, + Op3540, Op3548, Op3550, Op3558, Op3560, Op3568, Op3570, Op3578, + Op3580, Op3588, Op3590, Op3598, Op35a0, Op35a8, Op35b0, Op35b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3600, Op3608, Op3610, Op3618, Op3620, Op3628, Op3630, Op3638, + Op3640, Op3648, Op3650, Op3658, Op3660, Op3668, Op3670, Op3678, + Op3680, Op3688, Op3690, Op3698, Op36a0, Op36a8, Op36b0, Op36b8, + Op36c0, Op36c8, Op36d0, Op36d8, Op36e0, Op36e8, Op36f0, Op36f8, + Op3700, Op3708, Op3710, Op3718, Op3720, Op3728, Op3730, Op3738, + Op3740, Op3748, Op3750, Op3758, Op3760, Op3768, Op3770, Op3778, + Op3780, Op3788, Op3790, Op3798, Op37a0, Op37a8, Op37b0, Op37b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3800, Op3808, Op3810, Op3818, Op3820, Op3828, Op3830, Op3838, + Op3840, Op3848, Op3850, Op3858, Op3860, Op3868, Op3870, Op3878, + Op3880, Op3888, Op3890, Op3898, Op38a0, Op38a8, Op38b0, Op38b8, + Op38c0, Op38c8, Op38d0, Op38d8, Op38e0, Op38e8, Op38f0, Op38f8, + Op3900, Op3908, Op3910, Op3918, Op3920, Op3928, Op3930, Op3938, + Op3940, Op3948, Op3950, Op3958, Op3960, Op3968, Op3970, Op3978, + Op3980, Op3988, Op3990, Op3998, Op39a0, Op39a8, Op39b0, Op39b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3a00, Op3a08, Op3a10, Op3a18, Op3a20, Op3a28, Op3a30, Op3a38, + Op3a40, Op3a48, Op3a50, Op3a58, Op3a60, Op3a68, Op3a70, Op3a78, + Op3a80, Op3a88, Op3a90, Op3a98, Op3aa0, Op3aa8, Op3ab0, Op3ab8, + Op3ac0, Op3ac8, Op3ad0, Op3ad8, Op3ae0, Op3ae8, Op3af0, Op3af8, + Op3b00, Op3b08, Op3b10, Op3b18, Op3b20, Op3b28, Op3b30, Op3b38, + Op3b40, Op3b48, Op3b50, Op3b58, Op3b60, Op3b68, Op3b70, Op3b78, + Op3b80, Op3b88, Op3b90, Op3b98, Op3ba0, Op3ba8, Op3bb0, Op3bb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3c00, Op3c08, Op3c10, Op3c18, Op3c20, Op3c28, Op3c30, Op3c38, + Op3c40, Op3c48, Op3c50, Op3c58, Op3c60, Op3c68, Op3c70, Op3c78, + Op3c80, Op3c88, Op3c90, Op3c98, Op3ca0, Op3ca8, Op3cb0, Op3cb8, + Op3cc0, Op3cc8, Op3cd0, Op3cd8, Op3ce0, Op3ce8, Op3cf0, Op3cf8, + Op3d00, Op3d08, Op3d10, Op3d18, Op3d20, Op3d28, Op3d30, Op3d38, + Op3d40, Op3d48, Op3d50, Op3d58, Op3d60, Op3d68, Op3d70, Op3d78, + Op3d80, Op3d88, Op3d90, Op3d98, Op3da0, Op3da8, Op3db0, Op3db8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op3e00, Op3e08, Op3e10, Op3e18, Op3e20, Op3e28, Op3e30, Op3e38, + Op3e40, Op3e48, Op3e50, Op3e58, Op3e60, Op3e68, Op3e70, Op3e78, + Op3e80, Op3e88, Op3e90, Op3e98, Op3ea0, Op3ea8, Op3eb0, Op3eb8, + Op3ec0, Op3ec8, Op3ed0, Op3ed8, Op3ee0, Op3ee8, Op3ef0, Op3ef8, + Op3f00, Op3f08, Op3f10, Op3f18, Op3f20, Op3f28, Op3f30, Op3f38, + Op3f40, Op3f48, Op3f50, Op3f58, Op3f60, Op3f68, Op3f70, Op3f78, + Op3f80, Op3f88, Op3f90, Op3f98, Op3fa0, Op3fa8, Op3fb0, Op3fb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 4000 */ + Op4000, IllIns, Op4010, Op4018, Op4020, Op4028, Op4030, Op4038, + Op4040, IllIns, Op4050, Op4058, Op4060, Op4068, Op4070, Op4078, + Op4080, IllIns, Op4090, Op4098, Op40a0, Op40a8, Op40b0, Op40b8, + Op40c0, IllIns, Op40d0, Op40d8, Op40e0, Op40e8, Op40f0, Op40f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4180, IllIns, Op4190, Op4198, Op41a0, Op41a8, Op41b0, Op41b8, + IllIns, IllIns, Op41d0, IllIns, IllIns, Op41e8, Op41f0, Op41f8, + Op4200, IllIns, Op4210, Op4218, Op4220, Op4228, Op4230, Op4238, + Op4240, IllIns, Op4250, Op4258, Op4260, Op4268, Op4270, Op4278, + Op4280, IllIns, Op4290, Op4298, Op42a0, Op42a8, Op42b0, Op42b8, + Op42c0, IllIns, Op42d0, Op42d8, Op42e0, Op42e8, Op42f0, Op42f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4380, IllIns, Op4390, Op4398, Op43a0, Op43a8, Op43b0, Op43b8, + IllIns, IllIns, Op43d0, IllIns, IllIns, Op43e8, Op43f0, Op43f8, + Op4400, IllIns, Op4410, Op4418, Op4420, Op4428, Op4430, Op4438, + Op4440, IllIns, Op4450, Op4458, Op4460, Op4468, Op4470, Op4478, + Op4480, IllIns, Op4490, Op4498, Op44a0, Op44a8, Op44b0, Op44b8, + Op44c0, IllIns, Op44d0, Op44d8, Op44e0, Op44e8, Op44f0, Op44f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4580, IllIns, Op4590, Op4598, Op45a0, Op45a8, Op45b0, Op45b8, + IllIns, IllIns, Op45d0, IllIns, IllIns, Op45e8, Op45f0, Op45f8, + Op4600, IllIns, Op4610, Op4618, Op4620, Op4628, Op4630, Op4638, + Op4640, IllIns, Op4650, Op4658, Op4660, Op4668, Op4670, Op4678, + Op4680, IllIns, Op4690, Op4698, Op46a0, Op46a8, Op46b0, Op46b8, + Op46c0, IllIns, Op46d0, Op46d8, Op46e0, Op46e8, Op46f0, Op46f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4780, IllIns, Op4790, Op4798, Op47a0, Op47a8, Op47b0, Op47b8, + IllIns, IllIns, Op47d0, IllIns, IllIns, Op47e8, Op47f0, Op47f8, + Op4800, IllIns, Op4810, Op4818, Op4820, Op4828, Op4830, Op4838, + Op4840, Op4848, Op4850, IllIns, IllIns, Op4868, Op4870, Op4878, + Op4880, IllIns, Op4890, IllIns, Op48a0, Op48a8, Op48b0, Op48b8, + Op48c0, IllIns, Op48d0, IllIns, Op48e0, Op48e8, Op48f0, Op48f8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4980, IllIns, Op4990, Op4998, Op49a0, Op49a8, Op49b0, Op49b8, + IllIns, IllIns, Op49d0, IllIns, IllIns, Op49e8, Op49f0, Op49f8, + Op4a00, IllIns, Op4a10, Op4a18, Op4a20, Op4a28, Op4a30, Op4a38, + Op4a40, IllIns, Op4a50, Op4a58, Op4a60, Op4a68, Op4a70, Op4a78, + Op4a80, IllIns, Op4a90, Op4a98, Op4aa0, Op4aa8, Op4ab0, Op4ab8, + Op4ac0, IllIns, Op4ad0, Op4ad8, Op4ae0, Op4ae8, Op4af0, Op4af8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4b80, IllIns, Op4b90, Op4b98, Op4ba0, Op4ba8, Op4bb0, Op4bb8, + IllIns, IllIns, Op4bd0, IllIns, IllIns, Op4be8, Op4bf0, Op4bf8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, Op4c90, Op4c98, IllIns, Op4ca8, Op4cb8, Op4cb8, + IllIns, IllIns, Op4cd0, Op4cd8, IllIns, Op4ce8, Op4cf0, Op4cf8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4d80, IllIns, Op4d90, Op4d98, Op4da0, Op4da8, Op4db0, Op4db8, + IllIns, IllIns, Op4dd0, IllIns, IllIns, Op4de8, Op4df0, Op4df8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4e40, Op4e40, Op4e50, Op4e58, Op4e60, Op4e68, Op4e70, Op4e78, + IllIns, IllIns, Op4e90, IllIns, IllIns, Op4ea8, Op4eb0, Op4eb8, + IllIns, IllIns, Op4ed0, IllIns, IllIns, Op4ee8, Op4ef0, Op4ef8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op4f80, IllIns, Op4f90, Op4f98, Op4fa0, Op4fa8, Op4fb0, Op4fb8, + IllIns, IllIns, Op4fd0, IllIns, IllIns, Op4fe8, Op4ff0, Op4ff8, + + /* 5000 */ + Op5000, IllIns, Op5010, Op5018, Op5020, Op5028, Op5030, Op5038, + Op5040, Op5048, Op5050, Op5058, Op5060, Op5068, Op5070, Op5078, + Op5080, Op5088, Op5090, Op5098, Op50a0, Op50a8, Op50b0, Op50b8, + Op50c0, Op50c8, Op50d0, Op50d8, Op50e0, Op50e8, Op50f0, Op50f8, + Op5100, IllIns, Op5110, Op5118, Op5120, Op5128, Op5130, Op5138, + Op5140, Op5148, Op5150, Op5158, Op5160, Op5168, Op5170, Op5178, + Op5180, Op5188, Op5190, Op5198, Op51a0, Op51a8, Op51b0, Op51b8, + Op51c0, Op51c8, Op51d0, Op51d8, Op51e0, Op51e8, Op51f0, Op51f8, + Op5200, IllIns, Op5210, Op5218, Op5220, Op5228, Op5230, Op5238, + Op5240, Op5248, Op5250, Op5258, Op5260, Op5268, Op5270, Op5278, + Op5280, Op5288, Op5290, Op5298, Op52a0, Op52a8, Op52b0, Op52b8, + Op52c0, Op52c8, Op52d0, Op52d8, Op52e0, Op52e8, Op52f0, Op52f8, + Op5300, IllIns, Op5310, Op5318, Op5320, Op5328, Op5330, Op5338, + Op5340, Op5348, Op5350, Op5358, Op5360, Op5368, Op5370, Op5378, + Op5380, Op5388, Op5390, Op5398, Op53a0, Op53a8, Op53b0, Op53b8, + Op53c0, Op53c8, Op53d0, Op53d8, Op53e0, Op53e8, Op53f0, Op53f8, + Op5400, IllIns, Op5410, Op5418, Op5420, Op5428, Op5430, Op5438, + Op5440, Op5448, Op5450, Op5458, Op5460, Op5468, Op5470, Op5478, + Op5480, Op5488, Op5490, Op5498, Op54a0, Op54a8, Op54b0, Op54b8, + Op54c0, Op54c8, Op54d0, Op54d8, Op54e0, Op54e8, Op54f0, Op54f8, + Op5500, IllIns, Op5510, Op5518, Op5520, Op5528, Op5530, Op5538, + Op5540, Op5548, Op5550, Op5558, Op5560, Op5568, Op5570, Op5578, + Op5580, Op5588, Op5590, Op5598, Op55a0, Op55a8, Op55b0, Op55b8, + Op55c0, Op55c8, Op55d0, Op55d8, Op55e0, Op55e8, Op55f0, Op55f8, + Op5600, IllIns, Op5610, Op5618, Op5620, Op5628, Op5630, Op5638, + Op5640, Op5648, Op5650, Op5658, Op5660, Op5668, Op5670, Op5678, + Op5680, Op5688, Op5690, Op5698, Op56a0, Op56a8, Op56b0, Op56b8, + Op56c0, Op56c8, Op56d0, Op56d8, Op56e0, Op56e8, Op56f0, Op56f8, + Op5700, IllIns, Op5710, Op5718, Op5720, Op5728, Op5730, Op5738, + Op5740, Op5748, Op5750, Op5758, Op5760, Op5768, Op5770, Op5778, + Op5780, Op5788, Op5790, Op5798, Op57a0, Op57a8, Op57b0, Op57b8, + Op57c0, Op57c8, Op57d0, Op57d8, Op57e0, Op57e8, Op57f0, Op57f8, + Op5800, IllIns, Op5810, Op5818, Op5820, Op5828, Op5830, Op5838, + Op5840, Op5848, Op5850, Op5858, Op5860, Op5868, Op5870, Op5878, + Op5880, Op5888, Op5890, Op5898, Op58a0, Op58a8, Op58b0, Op58b8, + Op58c0, Op58c8, Op58d0, Op58d8, Op58e0, Op58e8, Op58f0, Op58f8, + Op5900, IllIns, Op5910, Op5918, Op5920, Op5928, Op5930, Op5938, + Op5940, Op5948, Op5950, Op5958, Op5960, Op5968, Op5970, Op5978, + Op5980, Op5988, Op5990, Op5998, Op59a0, Op59a8, Op59b0, Op59b8, + Op59c0, Op59c8, Op59d0, Op59d8, Op59e0, Op59e8, Op59f0, Op59f8, + Op5a00, IllIns, Op5a10, Op5a18, Op5a20, Op5a28, Op5a30, Op5a38, + Op5a40, Op5a48, Op5a50, Op5a58, Op5a60, Op5a68, Op5a70, Op5a78, + Op5a80, Op5a88, Op5a90, Op5a98, Op5aa0, Op5aa8, Op5ab0, Op5ab8, + Op5ac0, Op5ac8, Op5ad0, Op5ad8, Op5ae0, Op5ae8, Op5af0, Op5af8, + Op5b00, IllIns, Op5b10, Op5b18, Op5b20, Op5b28, Op5b30, Op5b38, + Op5b40, Op5b48, Op5b50, Op5b58, Op5b60, Op5b68, Op5b70, Op5b78, + Op5b80, Op5b88, Op5b90, Op5b98, Op5ba0, Op5ba8, Op5bb0, Op5bb8, + Op5bc0, Op5bc8, Op5bd0, Op5bd8, Op5be0, Op5be8, Op5bf0, Op5bf8, + Op5c00, IllIns, Op5c10, Op5c18, Op5c20, Op5c28, Op5c30, Op5c38, + Op5c40, Op5c48, Op5c50, Op5c58, Op5c60, Op5c68, Op5c70, Op5c78, + Op5c80, Op5c88, Op5c90, Op5c98, Op5ca0, Op5ca8, Op5cb0, Op5cb8, + Op5cc0, Op5cc8, Op5cd0, Op5cd8, Op5ce0, Op5ce8, Op5cf0, Op5cf8, + Op5d00, IllIns, Op5d10, Op5d18, Op5d20, Op5d28, Op5d30, Op5d38, + Op5d40, Op5d48, Op5d50, Op5d58, Op5d60, Op5d68, Op5d70, Op5d78, + Op5d80, Op5d88, Op5d90, Op5d98, Op5da0, Op5da8, Op5db0, Op5db8, + Op5dc0, Op5dc8, Op5dd0, Op5dd8, Op5de0, Op5de8, Op5df0, Op5df8, + Op5e00, IllIns, Op5e10, Op5e18, Op5e20, Op5e28, Op5e30, Op5e38, + Op5e40, Op5e48, Op5e50, Op5e58, Op5e60, Op5e68, Op5e70, Op5e78, + Op5e80, Op5e88, Op5e90, Op5e98, Op5ea0, Op5ea8, Op5eb0, Op5eb8, + Op5ec0, Op5ec8, Op5ed0, Op5ed8, Op5ee0, Op5ee8, Op5ef0, Op5ef8, + Op5f00, IllIns, Op5f10, Op5f18, Op5f20, Op5f28, Op5f30, Op5f38, + Op5f40, Op5f48, Op5f50, Op5f58, Op5f60, Op5f68, Op5f70, Op5f78, + Op5f80, Op5f88, Op5f90, Op5f98, Op5fa0, Op5fa8, Op5fb0, Op5fb8, + Op5fc0, Op5fc8, Op5fd0, Op5fd8, Op5fe0, Op5fe8, Op5ff0, Op5ff8, + + /* 6000 */ + Op6000, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, Op6008, + Op6100, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, Op6108, + Op6200, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, Op6208, + Op6300, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, Op6308, + Op6400, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, Op6408, + Op6500, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, Op6508, + Op6600, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, Op6608, + Op6700, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, Op6708, + Op6800, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, Op6808, + Op6900, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, Op6908, + Op6a00, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, Op6a08, + Op6b00, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, Op6b08, + Op6c00, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, Op6c08, + Op6d00, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, Op6d08, + Op6e00, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, Op6e08, + Op6f00, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, Op6f08, + + /* 7000 */ + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, Op7000, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, Op7200, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, Op7400, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, Op7600, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, Op7800, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, Op7a00, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, Op7c00, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, Op7e00, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* 8000 */ + Op8000, IllIns, Op8010, Op8018, Op8020, Op8028, Op8030, Op8038, + Op8040, IllIns, Op8050, Op8058, Op8060, Op8068, Op8070, Op8078, + Op8080, IllIns, Op8090, Op8098, Op80a0, Op80a8, Op80b0, Op80b8, + Op80c0, IllIns, Op80d0, Op80d8, Op80e0, Op80e8, Op80f0, Op80f8, + Op8100, Op8108, Op8110, Op8118, Op8120, Op8128, Op8130, Op8138, + IllIns, IllIns, Op8150, Op8158, Op8160, Op8168, Op8170, Op8178, + IllIns, IllIns, Op8190, Op8198, Op81a0, Op81a8, Op81b0, Op81b8, + Op81c0, IllIns, Op81d0, Op81d8, Op81e0, Op81e8, Op81f0, Op81f8, + Op8200, IllIns, Op8210, Op8218, Op8220, Op8228, Op8230, Op8238, + Op8240, IllIns, Op8250, Op8258, Op8260, Op8268, Op8270, Op8278, + Op8280, IllIns, Op8290, Op8298, Op82a0, Op82a8, Op82b0, Op82b8, + Op82c0, IllIns, Op82d0, Op82d8, Op82e0, Op82e8, Op82f0, Op82f8, + Op8300, Op8308, Op8310, Op8318, Op8320, Op8328, Op8330, Op8338, + IllIns, IllIns, Op8350, Op8358, Op8360, Op8368, Op8370, Op8378, + IllIns, IllIns, Op8390, Op8398, Op83a0, Op83a8, Op83b0, Op83b8, + Op83c0, IllIns, Op83d0, Op83d8, Op83e0, Op83e8, Op83f0, Op83f8, + Op8400, IllIns, Op8410, Op8418, Op8420, Op8428, Op8430, Op8438, + Op8440, IllIns, Op8450, Op8458, Op8460, Op8468, Op8470, Op8478, + Op8480, IllIns, Op8490, Op8498, Op84a0, Op84a8, Op84b0, Op84b8, + Op84c0, IllIns, Op84d0, Op84d8, Op84e0, Op84e8, Op84f0, Op84f8, + Op8500, Op8508, Op8510, Op8518, Op8520, Op8528, Op8530, Op8538, + IllIns, IllIns, Op8550, Op8558, Op8560, Op8568, Op8570, Op8578, + IllIns, IllIns, Op8590, Op8598, Op85a0, Op85a8, Op85b0, Op85b8, + Op85c0, IllIns, Op85d0, Op85d8, Op85e0, Op85e8, Op85f0, Op85f8, + Op8600, IllIns, Op8610, Op8618, Op8620, Op8628, Op8630, Op8638, + Op8640, IllIns, Op8650, Op8658, Op8660, Op8668, Op8670, Op8678, + Op8680, IllIns, Op8690, Op8698, Op86a0, Op86a8, Op86b0, Op86b8, + Op86c0, IllIns, Op86d0, Op86d8, Op86e0, Op86e8, Op86f0, Op86f8, + Op8700, Op8708, Op8710, Op8718, Op8720, Op8728, Op8730, Op8738, + IllIns, IllIns, Op8750, Op8758, Op8760, Op8768, Op8770, Op8778, + IllIns, IllIns, Op8790, Op8798, Op87a0, Op87a8, Op87b0, Op87b8, + Op87c0, IllIns, Op87d0, Op87d8, Op87e0, Op87e8, Op87f0, Op87f8, + Op8800, IllIns, Op8810, Op8818, Op8820, Op8828, Op8830, Op8838, + Op8840, IllIns, Op8850, Op8858, Op8860, Op8868, Op8870, Op8878, + Op8880, IllIns, Op8890, Op8898, Op88a0, Op88a8, Op88b0, Op88b8, + Op88c0, IllIns, Op88d0, Op88d8, Op88e0, Op88e8, Op88f0, Op88f8, + Op8900, Op8908, Op8910, Op8918, Op8920, Op8928, Op8930, Op8938, + IllIns, IllIns, Op8950, Op8958, Op8960, Op8968, Op8970, Op8978, + IllIns, IllIns, Op8990, Op8998, Op89a0, Op89a8, Op89b0, Op89b8, + Op89c0, IllIns, Op89d0, Op89d8, Op89e0, Op89e8, Op89f0, Op89f8, + Op8a00, IllIns, Op8a10, Op8a18, Op8a20, Op8a28, Op8a30, Op8a38, + Op8a40, IllIns, Op8a50, Op8a58, Op8a60, Op8a68, Op8a70, Op8a78, + Op8a80, IllIns, Op8a90, Op8a98, Op8aa0, Op8aa8, Op8ab0, Op8ab8, + Op8ac0, IllIns, Op8ad0, Op8ad8, Op8ae0, Op8ae8, Op8af0, Op8af8, + Op8b00, Op8b08, Op8b10, Op8b18, Op8b20, Op8b28, Op8b30, Op8b38, + IllIns, IllIns, Op8b50, Op8b58, Op8b60, Op8b68, Op8b70, Op8b78, + IllIns, IllIns, Op8b90, Op8b98, Op8ba0, Op8ba8, Op8bb0, Op8bb8, + Op8bc0, IllIns, Op8bd0, Op8bd8, Op8be0, Op8be8, Op8bf0, Op8bf8, + Op8c00, IllIns, Op8c10, Op8c18, Op8c20, Op8c28, Op8c30, Op8c38, + Op8c40, IllIns, Op8c50, Op8c58, Op8c60, Op8c68, Op8c70, Op8c78, + Op8c80, IllIns, Op8c90, Op8c98, Op8ca0, Op8ca8, Op8cb0, Op8cb8, + Op8cc0, IllIns, Op8cd0, Op8cd8, Op8ce0, Op8ce8, Op8cf0, Op8cf8, + Op8d00, Op8d08, Op8d10, Op8d18, Op8d20, Op8d28, Op8d30, Op8d38, + IllIns, IllIns, Op8d50, Op8d58, Op8d60, Op8d68, Op8d70, Op8d78, + IllIns, IllIns, Op8d90, Op8d98, Op8da0, Op8da8, Op8db0, Op8db8, + Op8dc0, IllIns, Op8dd0, Op8dd8, Op8de0, Op8de8, Op8df0, Op8df8, + Op8e00, IllIns, Op8e10, Op8e18, Op8e20, Op8e28, Op8e30, Op8e38, + Op8e40, IllIns, Op8e50, Op8e58, Op8e60, Op8e68, Op8e70, Op8e78, + Op8e80, IllIns, Op8e90, Op8e98, Op8ea0, Op8ea8, Op8eb0, Op8eb8, + Op8ec0, IllIns, Op8ed0, Op8ed8, Op8ee0, Op8ee8, Op8ef0, Op8ef8, + Op8f00, Op8f08, Op8f10, Op8f18, Op8f20, Op8f28, Op8f30, Op8f38, + IllIns, IllIns, Op8f50, Op8f58, Op8f60, Op8f68, Op8f70, Op8f78, + IllIns, IllIns, Op8f90, Op8f98, Op8fa0, Op8fa8, Op8fb0, Op8fb8, + Op8fc0, IllIns, Op8fd0, Op8fd8, Op8fe0, Op8fe8, Op8ff0, Op8ff8, + + /* 9000 */ + Op9000, IllIns, Op9010, Op9018, Op9020, Op9028, Op9030, Op9038, + Op9040, Op9048, Op9050, Op9058, Op9060, Op9068, Op9070, Op9078, + Op9080, Op9088, Op9090, Op9098, Op90a0, Op90a8, Op90b0, Op90b8, + Op90c0, Op90c8, Op90d0, Op90d8, Op90e0, Op90e8, Op90f0, Op90f8, + Op9100, Op9108, Op9110, Op9118, Op9120, Op9128, Op9130, Op9138, + Op9140, Op9148, Op9150, Op9158, Op9160, Op9168, Op9170, Op9178, + Op9180, Op9188, Op9190, Op9198, Op91a0, Op91a8, Op91b0, Op91b8, + Op91c0, Op91c8, Op91d0, Op91d8, Op91e0, Op91e8, Op91f0, Op91f8, + Op9200, IllIns, Op9210, Op9218, Op9220, Op9228, Op9230, Op9238, + Op9240, Op9248, Op9250, Op9258, Op9260, Op9268, Op9270, Op9278, + Op9280, Op9288, Op9290, Op9298, Op92a0, Op92a8, Op92b0, Op92b8, + Op92c0, Op92c8, Op92d0, Op92d8, Op92e0, Op92e8, Op92f0, Op92f8, + Op9300, Op9308, Op9310, Op9318, Op9320, Op9328, Op9330, Op9338, + Op9340, Op9348, Op9350, Op9358, Op9360, Op9368, Op9370, Op9378, + Op9380, Op9388, Op9390, Op9398, Op93a0, Op93a8, Op93b0, Op93b8, + Op93c0, Op93c8, Op93d0, Op93d8, Op93e0, Op93e8, Op93f0, Op93f8, + Op9400, IllIns, Op9410, Op9418, Op9420, Op9428, Op9430, Op9438, + Op9440, Op9448, Op9450, Op9458, Op9460, Op9468, Op9470, Op9478, + Op9480, Op9488, Op9490, Op9498, Op94a0, Op94a8, Op94b0, Op94b8, + Op94c0, Op94c8, Op94d0, Op94d8, Op94e0, Op94e8, Op94f0, Op94f8, + Op9500, Op9508, Op9510, Op9518, Op9520, Op9528, Op9530, Op9538, + Op9540, Op9548, Op9550, Op9558, Op9560, Op9568, Op9570, Op9578, + Op9580, Op9588, Op9590, Op9598, Op95a0, Op95a8, Op95b0, Op95b8, + Op95c0, Op95c8, Op95d0, Op95d8, Op95e0, Op95e8, Op95f0, Op95f8, + Op9600, IllIns, Op9610, Op9618, Op9620, Op9628, Op9630, Op9638, + Op9640, Op9648, Op9650, Op9658, Op9660, Op9668, Op9670, Op9678, + Op9680, Op9688, Op9690, Op9698, Op96a0, Op96a8, Op96b0, Op96b8, + Op96c0, Op96c8, Op96d0, Op96d8, Op96e0, Op96e8, Op96f0, Op96f8, + Op9700, Op9708, Op9710, Op9718, Op9720, Op9728, Op9730, Op9738, + Op9740, Op9748, Op9750, Op9758, Op9760, Op9768, Op9770, Op9778, + Op9780, Op9788, Op9790, Op9798, Op97a0, Op97a8, Op97b0, Op97b8, + Op97c0, Op97c8, Op97d0, Op97d8, Op97e0, Op97e8, Op97f0, Op97f8, + Op9800, IllIns, Op9810, Op9818, Op9820, Op9828, Op9830, Op9838, + Op9840, Op9848, Op9850, Op9858, Op9860, Op9868, Op9870, Op9878, + Op9880, Op9888, Op9890, Op9898, Op98a0, Op98a8, Op98b0, Op98b8, + Op98c0, Op98c8, Op98d0, Op98d8, Op98e0, Op98e8, Op98f0, Op98f8, + Op9900, Op9908, Op9910, Op9918, Op9920, Op9928, Op9930, Op9938, + Op9940, Op9948, Op9950, Op9958, Op9960, Op9968, Op9970, Op9978, + Op9980, Op9988, Op9990, Op9998, Op99a0, Op99a8, Op99b0, Op99b8, + Op99c0, Op99c8, Op99d0, Op99d8, Op99e0, Op99e8, Op99f0, Op99f8, + Op9a00, IllIns, Op9a10, Op9a18, Op9a20, Op9a28, Op9a30, Op9a38, + Op9a40, Op9a48, Op9a50, Op9a58, Op9a60, Op9a68, Op9a70, Op9a78, + Op9a80, Op9a88, Op9a90, Op9a98, Op9aa0, Op9aa8, Op9ab0, Op9ab8, + Op9ac0, Op9ac8, Op9ad0, Op9ad8, Op9ae0, Op9ae8, Op9af0, Op9af8, + Op9b00, Op9b08, Op9b10, Op9b18, Op9b20, Op9b28, Op9b30, Op9b38, + Op9b40, Op9b48, Op9b50, Op9b58, Op9b60, Op9b68, Op9b70, Op9b78, + Op9b80, Op9b88, Op9b90, Op9b98, Op9ba0, Op9ba8, Op9bb0, Op9bb8, + Op9bc0, Op9bc8, Op9bd0, Op9bd8, Op9be0, Op9be8, Op9bf0, Op9bf8, + Op9c00, IllIns, Op9c10, Op9c18, Op9c20, Op9c28, Op9c30, Op9c38, + Op9c40, Op9c48, Op9c50, Op9c58, Op9c60, Op9c68, Op9c70, Op9c78, + Op9c80, Op9c88, Op9c90, Op9c98, Op9ca0, Op9ca8, Op9cb0, Op9cb8, + Op9cc0, Op9cc8, Op9cd0, Op9cd8, Op9ce0, Op9ce8, Op9cf0, Op9cf8, + Op9d00, Op9d08, Op9d10, Op9d18, Op9d20, Op9d28, Op9d30, Op9d38, + Op9d40, Op9d48, Op9d50, Op9d58, Op9d60, Op9d68, Op9d70, Op9d78, + Op9d80, Op9d88, Op9d90, Op9d98, Op9da0, Op9da8, Op9db0, Op9db8, + Op9dc0, Op9dc8, Op9dd0, Op9dd8, Op9de0, Op9de8, Op9df0, Op9df8, + Op9e00, IllIns, Op9e10, Op9e18, Op9e20, Op9e28, Op9e30, Op9e38, + Op9e40, Op9e48, Op9e50, Op9e58, Op9e60, Op9e68, Op9e70, Op9e78, + Op9e80, Op9e88, Op9e90, Op9e98, Op9ea0, Op9ea8, Op9eb0, Op9eb8, + Op9ec0, Op9ec8, Op9ed0, Op9ed8, Op9ee0, Op9ee8, Op9ef0, Op9ef8, + Op9f00, Op9f08, Op9f10, Op9f18, Op9f20, Op9f28, Op9f30, Op9f38, + Op9f40, Op9f48, Op9f50, Op9f58, Op9f60, Op9f68, Op9f70, Op9f78, + Op9f80, Op9f88, Op9f90, Op9f98, Op9fa0, Op9fa8, Op9fb0, Op9fb8, + Op9fc0, Op9fc8, Op9fd0, Op9fd8, Op9fe0, Op9fe8, Op9ff0, Op9ff8, + + /* A000 */ + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, Line_A, + + /* B000 */ + Opb000, IllIns, Opb010, Opb018, Opb020, Opb028, Opb030, Opb038, + Opb040, Opb048, Opb050, Opb058, Opb060, Opb068, Opb070, Opb078, + Opb080, Opb088, Opb090, Opb098, Opb0a0, Opb0a8, Opb0b0, Opb0b8, + Opb0c0, Opb0c8, Opb0d0, Opb0d8, Opb0e0, Opb0e8, Opb0f0, Opb0f8, + Opb100, Opb108, Opb110, Opb118, Opb120, Opb128, Opb130, Opb138, + Opb140, Opb148, Opb150, Opb158, Opb160, Opb168, Opb170, Opb178, + Opb180, Opb188, Opb190, Opb198, Opb1a0, Opb1a8, Opb1b0, Opb1b8, + Opb1c0, Opb1c8, Opb1d0, Opb1d8, Opb1e0, Opb1e8, Opb1f0, Opb1f8, + Opb200, IllIns, Opb210, Opb218, Opb220, Opb228, Opb230, Opb238, + Opb240, Opb248, Opb250, Opb258, Opb260, Opb268, Opb270, Opb278, + Opb280, Opb288, Opb290, Opb298, Opb2a0, Opb2a8, Opb2b0, Opb2b8, + Opb2c0, Opb2c8, Opb2d0, Opb2d8, Opb2e0, Opb2e8, Opb2f0, Opb2f8, + Opb300, Opb308, Opb310, Opb318, Opb320, Opb328, Opb330, Opb338, + Opb340, Opb348, Opb350, Opb358, Opb360, Opb368, Opb370, Opb378, + Opb380, Opb388, Opb390, Opb398, Opb3a0, Opb3a8, Opb3b0, Opb3b8, + Opb3c0, Opb3c8, Opb3d0, Opb3d8, Opb3e0, Opb3e8, Opb3f0, Opb3f8, + Opb400, IllIns, Opb410, Opb418, Opb420, Opb428, Opb430, Opb438, + Opb440, Opb448, Opb450, Opb458, Opb460, Opb468, Opb470, Opb478, + Opb480, Opb488, Opb490, Opb498, Opb4a0, Opb4a8, Opb4b0, Opb4b8, + Opb4c0, Opb4c8, Opb4d0, Opb4d8, Opb4e0, Opb4e8, Opb4f0, Opb4f8, + Opb500, Opb508, Opb510, Opb518, Opb520, Opb528, Opb530, Opb538, + Opb540, Opb548, Opb550, Opb558, Opb560, Opb568, Opb570, Opb578, + Opb580, Opb588, Opb590, Opb598, Opb5a0, Opb5a8, Opb5b0, Opb5b8, + Opb5c0, Opb5c8, Opb5d0, Opb5d8, Opb5e0, Opb5e8, Opb5f0, Opb5f8, + Opb600, IllIns, Opb610, Opb618, Opb620, Opb628, Opb630, Opb638, + Opb640, Opb648, Opb650, Opb658, Opb660, Opb668, Opb670, Opb678, + Opb680, Opb688, Opb690, Opb698, Opb6a0, Opb6a8, Opb6b0, Opb6b8, + Opb6c0, Opb6c8, Opb6d0, Opb6d8, Opb6e0, Opb6e8, Opb6f0, Opb6f8, + Opb700, Opb708, Opb710, Opb718, Opb720, Opb728, Opb730, Opb738, + Opb740, Opb748, Opb750, Opb758, Opb760, Opb768, Opb770, Opb778, + Opb780, Opb788, Opb790, Opb798, Opb7a0, Opb7a8, Opb7b0, Opb7b8, + Opb7c0, Opb7c8, Opb7d0, Opb7d8, Opb7e0, Opb7e8, Opb7f0, Opb7f8, + Opb800, IllIns, Opb810, Opb818, Opb820, Opb828, Opb830, Opb838, + Opb840, Opb848, Opb850, Opb858, Opb860, Opb868, Opb870, Opb878, + Opb880, Opb888, Opb890, Opb898, Opb8a0, Opb8a8, Opb8b0, Opb8b8, + Opb8c0, Opb8c8, Opb8d0, Opb8d8, Opb8e0, Opb8e8, Opb8f0, Opb8f8, + Opb900, Opb908, Opb910, Opb918, Opb920, Opb928, Opb930, Opb938, + Opb940, Opb948, Opb950, Opb958, Opb960, Opb968, Opb970, Opb978, + Opb980, Opb988, Opb990, Opb998, Opb9a0, Opb9a8, Opb9b0, Opb9b8, + Opb9c0, Opb9c8, Opb9d0, Opb9d8, Opb9e0, Opb9e8, Opb9f0, Opb9f8, + Opba00, IllIns, Opba10, Opba18, Opba20, Opba28, Opba30, Opba38, + Opba40, Opba48, Opba50, Opba58, Opba60, Opba68, Opba70, Opba78, + Opba80, Opba88, Opba90, Opba98, Opbaa0, Opbaa8, Opbab0, Opbab8, + Opbac0, Opbac8, Opbad0, Opbad8, Opbae0, Opbae8, Opbaf0, Opbaf8, + Opbb00, Opbb08, Opbb10, Opbb18, Opbb20, Opbb28, Opbb30, Opbb38, + Opbb40, Opbb48, Opbb50, Opbb58, Opbb60, Opbb68, Opbb70, Opbb78, + Opbb80, Opbb88, Opbb90, Opbb98, Opbba0, Opbba8, Opbbb0, Opbbb8, + Opbbc0, Opbbc8, Opbbd0, Opbbd8, Opbbe0, Opbbe8, Opbbf0, Opbbf8, + Opbc00, IllIns, Opbc10, Opbc18, Opbc20, Opbc28, Opbc30, Opbc38, + Opbc40, Opbc48, Opbc50, Opbc58, Opbc60, Opbc68, Opbc70, Opbc78, + Opbc80, Opbc88, Opbc90, Opbc98, Opbca0, Opbca8, Opbcb0, Opbcb8, + Opbcc0, Opbcc8, Opbcd0, Opbcd8, Opbce0, Opbce8, Opbcf0, Opbcf8, + Opbd00, Opbd08, Opbd10, Opbd18, Opbd20, Opbd28, Opbd30, Opbd38, + Opbd40, Opbd48, Opbd50, Opbd58, Opbd60, Opbd68, Opbd70, Opbd78, + Opbd80, Opbd88, Opbd90, Opbd98, Opbda0, Opbda8, Opbdb0, Opbdb8, + Opbdc0, Opbdc8, Opbdd0, Opbdd8, Opbde0, Opbde8, Opbdf0, Opbdf8, + Opbe00, IllIns, Opbe10, Opbe18, Opbe20, Opbe28, Opbe30, Opbe38, + Opbe40, Opbe48, Opbe50, Opbe58, Opbe60, Opbe68, Opbe70, Opbe78, + Opbe80, Opbe88, Opbe90, Opbe98, Opbea0, Opbea8, Opbeb0, Opbeb8, + Opbec0, Opbec8, Opbed0, Opbed8, Opbee0, Opbee8, Opbef0, Opbef8, + Opbf00, Opbf08, Opbf10, Opbf18, Opbf20, Opbf28, Opbf30, Opbf38, + Opbf40, Opbf48, Opbf50, Opbf58, Opbf60, Opbf68, Opbf70, Opbf78, + Opbf80, Opbf88, Opbf90, Opbf98, Opbfa0, Opbfa8, Opbfb0, Opbfb8, + Opbfc0, Opbfc8, Opbfd0, Opbfd8, Opbfe0, Opbfe8, Opbff0, Opbff8, + + /* C000 */ + Opc000, IllIns, Opc010, Opc018, Opc020, Opc028, Opc030, Opc038, + Opc040, IllIns, Opc050, Opc058, Opc060, Opc068, Opc070, Opc078, + Opc080, IllIns, Opc090, Opc098, Opc0a0, Opc0a8, Opc0b0, Opc0b8, + Opc0c0, IllIns, Opc0d0, Opc0d8, Opc0e0, Opc0e8, Opc0f0, Opc0f8, + Opc100, Opc108, Opc110, Opc118, Opc120, Opc128, Opc130, Opc138, + Opc140, Opc148, Opc150, Opc158, Opc160, Opc168, Opc170, Opc178, + IllIns, Opc188, Opc190, Opc198, Opc1a0, Opc1a8, Opc1b0, Opc1b8, + Opc1c0, IllIns, Opc1d0, Opc1d8, Opc1e0, Opc1e8, Opc1f0, Opc1f8, + Opc200, IllIns, Opc210, Opc218, Opc220, Opc228, Opc230, Opc238, + Opc240, IllIns, Opc250, Opc258, Opc260, Opc268, Opc270, Opc278, + Opc280, IllIns, Opc290, Opc298, Opc2a0, Opc2a8, Opc2b0, Opc2b8, + Opc2c0, IllIns, Opc2d0, Opc2d8, Opc2e0, Opc2e8, Opc2f0, Opc2f8, + Opc300, Opc308, Opc310, Opc318, Opc320, Opc328, Opc330, Opc338, + Opc340, Opc348, Opc350, Opc358, Opc360, Opc368, Opc370, Opc378, + IllIns, Opc388, Opc390, Opc398, Opc3a0, Opc3a8, Opc3b0, Opc3b8, + Opc3c0, IllIns, Opc3d0, Opc3d8, Opc3e0, Opc3e8, Opc3f0, Opc3f8, + Opc400, IllIns, Opc410, Opc418, Opc420, Opc428, Opc430, Opc438, + Opc440, IllIns, Opc450, Opc458, Opc460, Opc468, Opc470, Opc478, + Opc480, IllIns, Opc490, Opc498, Opc4a0, Opc4a8, Opc4b0, Opc4b8, + Opc4c0, IllIns, Opc4d0, Opc4d8, Opc4e0, Opc4e8, Opc4f0, Opc4f8, + Opc500, Opc508, Opc510, Opc518, Opc520, Opc528, Opc530, Opc538, + Opc540, Opc548, Opc550, Opc558, Opc560, Opc568, Opc570, Opc578, + IllIns, Opc588, Opc590, Opc598, Opc5a0, Opc5a8, Opc5b0, Opc5b8, + Opc5c0, IllIns, Opc5d0, Opc5d8, Opc5e0, Opc5e8, Opc5f0, Opc5f8, + Opc600, IllIns, Opc610, Opc618, Opc620, Opc628, Opc630, Opc638, + Opc640, IllIns, Opc650, Opc658, Opc660, Opc668, Opc670, Opc678, + Opc680, IllIns, Opc690, Opc698, Opc6a0, Opc6a8, Opc6b0, Opc6b8, + Opc6c0, IllIns, Opc6d0, Opc6d8, Opc6e0, Opc6e8, Opc6f0, Opc6f8, + Opc700, Opc708, Opc710, Opc718, Opc720, Opc728, Opc730, Opc738, + Opc740, Opc748, Opc750, Opc758, Opc760, Opc768, Opc770, Opc778, + IllIns, Opc788, Opc790, Opc798, Opc7a0, Opc7a8, Opc7b0, Opc7b8, + Opc7c0, IllIns, Opc7d0, Opc7d8, Opc7e0, Opc7e8, Opc7f0, Opc7f8, + Opc800, IllIns, Opc810, Opc818, Opc820, Opc828, Opc830, Opc838, + Opc840, IllIns, Opc850, Opc858, Opc860, Opc868, Opc870, Opc878, + Opc880, IllIns, Opc890, Opc898, Opc8a0, Opc8a8, Opc8b0, Opc8b8, + Opc8c0, IllIns, Opc8d0, Opc8d8, Opc8e0, Opc8e8, Opc8f0, Opc8f8, + Opc900, Opc908, Opc910, Opc918, Opc920, Opc928, Opc930, Opc938, + Opc940, Opc948, Opc950, Opc958, Opc960, Opc968, Opc970, Opc978, + IllIns, Opc988, Opc990, Opc998, Opc9a0, Opc9a8, Opc9b0, Opc9b8, + Opc9c0, IllIns, Opc9d0, Opc9d8, Opc9e0, Opc9e8, Opc9f0, Opc9f8, + Opca00, IllIns, Opca10, Opca18, Opca20, Opca28, Opca30, Opca38, + Opca40, IllIns, Opca50, Opca58, Opca60, Opca68, Opca70, Opca78, + Opca80, IllIns, Opca90, Opca98, Opcaa0, Opcaa8, Opcab0, Opcab8, + Opcac0, IllIns, Opcad0, Opcad8, Opcae0, Opcae8, Opcaf0, Opcaf8, + Opcb00, Opcb08, Opcb10, Opcb18, Opcb20, Opcb28, Opcb30, Opcb38, + Opcb40, Opcb48, Opcb50, Opcb58, Opcb60, Opcb68, Opcb70, Opcb78, + IllIns, Opcb88, Opcb90, Opcb98, Opcba0, Opcba8, Opcbb0, Opcbb8, + Opcbc0, IllIns, Opcbd0, Opcbd8, Opcbe0, Opcbe8, Opcbf0, Opcbf8, + Opcc00, IllIns, Opcc10, Opcc18, Opcc20, Opcc28, Opcc30, Opcc38, + Opcc40, IllIns, Opcc50, Opcc58, Opcc60, Opcc68, Opcc70, Opcc78, + Opcc80, IllIns, Opcc90, Opcc98, Opcca0, Opcca8, Opccb0, Opccb8, + Opccc0, IllIns, Opccd0, Opccd8, Opcce0, Opcce8, Opccf0, Opccf8, + Opcd00, Opcd08, Opcd10, Opcd18, Opcd20, Opcd28, Opcd30, Opcd38, + Opcd40, Opcd48, Opcd50, Opcd58, Opcd60, Opcd68, Opcd70, Opcd78, + IllIns, Opcd88, Opcd90, Opcd98, Opcda0, Opcda8, Opcdb0, Opcdb8, + Opcdc0, IllIns, Opcdd0, Opcdd8, Opcde0, Opcde8, Opcdf0, Opcdf8, + Opce00, IllIns, Opce10, Opce18, Opce20, Opce28, Opce30, Opce38, + Opce40, IllIns, Opce50, Opce58, Opce60, Opce68, Opce70, Opce78, + Opce80, IllIns, Opce90, Opce98, Opcea0, Opcea8, Opceb0, Opceb8, + Opcec0, IllIns, Opced0, Opced8, Opcee0, Opcee8, Opcef0, Opcef8, + Opcf00, Opcf08, Opcf10, Opcf18, Opcf20, Opcf28, Opcf30, Opcf38, + Opcf40, Opcf48, Opcf50, Opcf58, Opcf60, Opcf68, Opcf70, Opcf78, + IllIns, Opcf88, Opcf90, Opcf98, Opcfa0, Opcfa8, Opcfb0, Opcfb8, + Opcfc0, IllIns, Opcfd0, Opcfd8, Opcfe0, Opcfe8, Opcff0, Opcff8, + + /* D000 */ + Opd000, IllIns, Opd010, Opd018, Opd020, Opd028, Opd030, Opd038, + Opd040, Opd048, Opd050, Opd058, Opd060, Opd068, Opd070, Opd078, + Opd080, Opd088, Opd090, Opd098, Opd0a0, Opd0a8, Opd0b0, Opd0b8, + Opd0c0, Opd0c8, Opd0d0, Opd0d8, Opd0e0, Opd0e8, Opd0f0, Opd0f8, + Opd100, Opd108, Opd110, Opd118, Opd120, Opd128, Opd130, Opd138, + Opd140, Opd148, Opd150, Opd158, Opd160, Opd168, Opd170, Opd178, + Opd180, Opd188, Opd190, Opd198, Opd1a0, Opd1a8, Opd1b0, Opd1b8, + Opd1c0, Opd1c8, Opd1d0, Opd1d8, Opd1e0, Opd1e8, Opd1f0, Opd1f8, + Opd200, IllIns, Opd210, Opd218, Opd220, Opd228, Opd230, Opd238, + Opd240, Opd248, Opd250, Opd258, Opd260, Opd268, Opd270, Opd278, + Opd280, Opd288, Opd290, Opd298, Opd2a0, Opd2a8, Opd2b0, Opd2b8, + Opd2c0, Opd2c8, Opd2d0, Opd2d8, Opd2e0, Opd2e8, Opd2f0, Opd2f8, + Opd300, Opd308, Opd310, Opd318, Opd320, Opd328, Opd330, Opd338, + Opd340, Opd348, Opd350, Opd358, Opd360, Opd368, Opd370, Opd378, + Opd380, Opd388, Opd390, Opd398, Opd3a0, Opd3a8, Opd3b0, Opd3b8, + Opd3c0, Opd3c8, Opd3d0, Opd3d8, Opd3e0, Opd3e8, Opd3f0, Opd3f8, + Opd400, IllIns, Opd410, Opd418, Opd420, Opd428, Opd430, Opd438, + Opd440, Opd448, Opd450, Opd458, Opd460, Opd468, Opd470, Opd478, + Opd480, Opd488, Opd490, Opd498, Opd4a0, Opd4a8, Opd4b0, Opd4b8, + Opd4c0, Opd4c8, Opd4d0, Opd4d8, Opd4e0, Opd4e8, Opd4f0, Opd4f8, + Opd500, Opd508, Opd510, Opd518, Opd520, Opd528, Opd530, Opd538, + Opd540, Opd548, Opd550, Opd558, Opd560, Opd568, Opd570, Opd578, + Opd580, Opd588, Opd590, Opd598, Opd5a0, Opd5a8, Opd5b0, Opd5b8, + Opd5c0, Opd5c8, Opd5d0, Opd5d8, Opd5e0, Opd5e8, Opd5f0, Opd5f8, + Opd600, IllIns, Opd610, Opd618, Opd620, Opd628, Opd630, Opd638, + Opd640, Opd648, Opd650, Opd658, Opd660, Opd668, Opd670, Opd678, + Opd680, Opd688, Opd690, Opd698, Opd6a0, Opd6a8, Opd6b0, Opd6b8, + Opd6c0, Opd6c8, Opd6d0, Opd6d8, Opd6e0, Opd6e8, Opd6f0, Opd6f8, + Opd700, Opd708, Opd710, Opd718, Opd720, Opd728, Opd730, Opd738, + Opd740, Opd748, Opd750, Opd758, Opd760, Opd768, Opd770, Opd778, + Opd780, Opd788, Opd790, Opd798, Opd7a0, Opd7a8, Opd7b0, Opd7b8, + Opd7c0, Opd7c8, Opd7d0, Opd7d8, Opd7e0, Opd7e8, Opd7f0, Opd7f8, + Opd800, IllIns, Opd810, Opd818, Opd820, Opd828, Opd830, Opd838, + Opd840, Opd848, Opd850, Opd858, Opd860, Opd868, Opd870, Opd878, + Opd880, Opd888, Opd890, Opd898, Opd8a0, Opd8a8, Opd8b0, Opd8b8, + Opd8c0, Opd8c8, Opd8d0, Opd8d8, Opd8e0, Opd8e8, Opd8f0, Opd8f8, + Opd900, Opd908, Opd910, Opd918, Opd920, Opd928, Opd930, Opd938, + Opd940, Opd948, Opd950, Opd958, Opd960, Opd968, Opd970, Opd978, + Opd980, Opd988, Opd990, Opd998, Opd9a0, Opd9a8, Opd9b0, Opd9b8, + Opd9c0, Opd9c8, Opd9d0, Opd9d8, Opd9e0, Opd9e8, Opd9f0, Opd9f8, + Opda00, IllIns, Opda10, Opda18, Opda20, Opda28, Opda30, Opda38, + Opda40, Opda48, Opda50, Opda58, Opda60, Opda68, Opda70, Opda78, + Opda80, Opda88, Opda90, Opda98, Opdaa0, Opdaa8, Opdab0, Opdab8, + Opdac0, Opdac8, Opdad0, Opdad8, Opdae0, Opdae8, Opdaf0, Opdaf8, + Opdb00, Opdb08, Opdb10, Opdb18, Opdb20, Opdb28, Opdb30, Opdb38, + Opdb40, Opdb48, Opdb50, Opdb58, Opdb60, Opdb68, Opdb70, Opdb78, + Opdb80, Opdb88, Opdb90, Opdb98, Opdba0, Opdba8, Opdbb0, Opdbb8, + Opdbc0, Opdbc8, Opdbd0, Opdbd8, Opdbe0, Opdbe8, Opdbf0, Opdbf8, + Opdc00, IllIns, Opdc10, Opdc18, Opdc20, Opdc28, Opdc30, Opdc38, + Opdc40, Opdc48, Opdc50, Opdc58, Opdc60, Opdc68, Opdc70, Opdc78, + Opdc80, Opdc88, Opdc90, Opdc98, Opdca0, Opdca8, Opdcb0, Opdcb8, + Opdcc0, Opdcc8, Opdcd0, Opdcd8, Opdce0, Opdce8, Opdcf0, Opdcf8, + Opdd00, Opdd08, Opdd10, Opdd18, Opdd20, Opdd28, Opdd30, Opdd38, + Opdd40, Opdd48, Opdd50, Opdd58, Opdd60, Opdd68, Opdd70, Opdd78, + Opdd80, Opdd88, Opdd90, Opdd98, Opdda0, Opdda8, Opddb0, Opddb8, + Opddc0, Opddc8, Opddd0, Opddd8, Opdde0, Opdde8, Opddf0, Opddf8, + Opde00, IllIns, Opde10, Opde18, Opde20, Opde28, Opde30, Opde38, + Opde40, Opde48, Opde50, Opde58, Opde60, Opde68, Opde70, Opde78, + Opde80, Opde88, Opde90, Opde98, Opdea0, Opdea8, Opdeb0, Opdeb8, + Opdec0, Opdec8, Opded0, Opded8, Opdee0, Opdee8, Opdef0, Opdef8, + Opdf00, Opdf08, Opdf10, Opdf18, Opdf20, Opdf28, Opdf30, Opdf38, + Opdf40, Opdf48, Opdf50, Opdf58, Opdf60, Opdf68, Opdf70, Opdf78, + Opdf80, Opdf88, Opdf90, Opdf98, Opdfa0, Opdfa8, Opdfb0, Opdfb8, + Opdfc0, Opdfc8, Opdfd0, Opdfd8, Opdfe0, Opdfe8, Opdff0, Opdff8, + + /* E000 */ + Ope000, Ope008, Ope010, Ope018, Ope020, Ope028, Ope030, Ope038, + Ope040, Ope048, Ope050, Ope058, Ope060, Ope068, Ope070, Ope078, + Ope080, Ope088, Ope090, Ope098, Ope0a0, Ope0a8, Ope0b0, Ope0b8, + IllIns, IllIns, Ope0d0, Ope0d8, Ope0e0, Ope0e8, Ope0f0, Ope0f8, + Ope100, Ope108, Ope110, Ope118, Ope120, Ope128, Ope130, Ope138, + Ope140, Ope148, Ope150, Ope158, Ope160, Ope168, Ope170, Ope178, + Ope180, Ope188, Ope190, Ope198, Ope1a0, Ope1a8, Ope1b0, Ope1b8, + IllIns, IllIns, Ope1d0, Ope1d8, Ope1e0, Ope1e8, Ope1f0, Ope1f8, + Ope200, Ope208, Ope210, Ope218, Ope220, Ope228, Ope230, Ope238, + Ope240, Ope248, Ope250, Ope258, Ope260, Ope268, Ope270, Ope278, + Ope280, Ope288, Ope290, Ope298, Ope2a0, Ope2a8, Ope2b0, Ope2b8, + IllIns, IllIns, Ope2d0, Ope2d8, Ope2e0, Ope2e8, Ope2f0, Ope2f8, + Ope300, Ope308, Ope310, Ope318, Ope320, Ope328, Ope330, Ope338, + Ope340, Ope348, Ope350, Ope358, Ope360, Ope368, Ope370, Ope378, + Ope380, Ope388, Ope390, Ope398, Ope3a0, Ope3a8, Ope3b0, Ope3b8, + IllIns, IllIns, Ope3d0, Ope3d8, Ope3e0, Ope3e8, Ope3f0, Ope3f8, + Ope400, Ope408, Ope410, Ope418, Ope420, Ope428, Ope430, Ope438, + Ope440, Ope448, Ope450, Ope458, Ope460, Ope468, Ope470, Ope478, + Ope480, Ope488, Ope490, Ope498, Ope4a0, Ope4a8, Ope4b0, Ope4b8, + IllIns, IllIns, Ope4d0, Ope4d8, Ope4e0, Ope4e8, Ope4f0, Ope4f8, + Ope500, Ope508, Ope510, Ope518, Ope520, Ope528, Ope530, Ope538, + Ope540, Ope548, Ope550, Ope558, Ope560, Ope568, Ope570, Ope578, + Ope580, Ope588, Ope590, Ope598, Ope5a0, Ope5a8, Ope5b0, Ope5b8, + IllIns, IllIns, Ope5d0, Ope5d8, Ope5e0, Ope5e8, Ope5f0, Ope5f8, + Ope600, Ope608, Ope610, Ope618, Ope620, Ope628, Ope630, Ope638, + Ope640, Ope648, Ope650, Ope658, Ope660, Ope668, Ope670, Ope678, + Ope680, Ope688, Ope690, Ope698, Ope6a0, Ope6a8, Ope6b0, Ope6b8, + IllIns, IllIns, Ope6d0, Ope6d8, Ope6e0, Ope6e8, Ope6f0, Ope6f8, + Ope700, Ope708, Ope710, Ope718, Ope720, Ope728, Ope730, Ope738, + Ope740, Ope748, Ope750, Ope758, Ope760, Ope768, Ope770, Ope778, + Ope780, Ope788, Ope790, Ope798, Ope7a0, Ope7a8, Ope7b0, Ope7b8, + IllIns, IllIns, Ope7d0, Ope7d8, Ope7e0, Ope7e8, Ope7f0, Ope7f8, + Ope800, Ope808, Ope810, Ope818, Ope820, Ope828, Ope830, Ope838, + Ope840, Ope848, Ope850, Ope858, Ope860, Ope868, Ope870, Ope878, + Ope880, Ope888, Ope890, Ope898, Ope8a0, Ope8a8, Ope8b0, Ope8b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Ope900, Ope908, Ope910, Ope918, Ope920, Ope928, Ope930, Ope938, + Ope940, Ope948, Ope950, Ope958, Ope960, Ope968, Ope970, Ope978, + Ope980, Ope988, Ope990, Ope998, Ope9a0, Ope9a8, Ope9b0, Ope9b8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opea00, Opea08, Opea10, Opea18, Opea20, Opea28, Opea30, Opea38, + Opea40, Opea48, Opea50, Opea58, Opea60, Opea68, Opea70, Opea78, + Opea80, Opea88, Opea90, Opea98, Opeaa0, Opeaa8, Opeab0, Opeab8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opeb00, Opeb08, Opeb10, Opeb18, Opeb20, Opeb28, Opeb30, Opeb38, + Opeb40, Opeb48, Opeb50, Opeb58, Opeb60, Opeb68, Opeb70, Opeb78, + Opeb80, Opeb88, Opeb90, Opeb98, Opeba0, Opeba8, Opebb0, Opebb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opec00, Opec08, Opec10, Opec18, Opec20, Opec28, Opec30, Opec38, + Opec40, Opec48, Opec50, Opec58, Opec60, Opec68, Opec70, Opec78, + Opec80, Opec88, Opec90, Opec98, Opeca0, Opeca8, Opecb0, Opecb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Oped00, Oped08, Oped10, Oped18, Oped20, Oped28, Oped30, Oped38, + Oped40, Oped48, Oped50, Oped58, Oped60, Oped68, Oped70, Oped78, + Oped80, Oped88, Oped90, Oped98, Opeda0, Opeda8, Opedb0, Opedb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opee00, Opee08, Opee10, Opee18, Opee20, Opee28, Opee30, Opee38, + Opee40, Opee48, Opee50, Opee58, Opee60, Opee68, Opee70, Opee78, + Opee80, Opee88, Opee90, Opee98, Opeea0, Opeea8, Opeeb0, Opeeb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + Opef00, Opef08, Opef10, Opef18, Opef20, Opef28, Opef30, Opef38, + Opef40, Opef48, Opef50, Opef58, Opef60, Opef68, Opef70, Opef78, + Opef80, Opef88, Opef90, Opef98, Opefa0, Opefa8, Opefb0, Opefb8, + IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, IllIns, + + /* F000 */ + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, + Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F, Line_F +}; diff --git a/MCUME_esp32/espcastaway/main/68korigbad/op68k.h b/MCUME_esp32/espcastaway/main/68korigbad/op68k.h new file mode 100755 index 0000000..436f6af --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/op68k.h @@ -0,0 +1,577 @@ +/* + * Castaway + * (C) 1994 - 2002 Martin Doering, Joachim Hoenig + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ +#ifndef OP68KH +#define OP68KH + +#include "config.h" +#include "operin.h" + +extern short GetMemWpc(unsigned long address); +extern long GetMemLpc(unsigned long address); +extern void SetMemPL(unsigned long address, unsigned long value); +extern void SetMemPW(unsigned long address, unsigned long value); + + +/* + * Status Register Access + */ +//AG: Changed to yet another SR implementation which is faster +//Note this code is little endian dependant and will need changing for big endian machines + +//reg[16]=ZNVC +//reg[17]=XTS- +//reg[18]=inst + +#define Zflag 0x1 +#define Nflag 0x100 +#define Vflag 0x10000 +#define Cflag 0x1000000 + +#define SetC(flag) if (flag) *(((int8*)reg)+67)=1; else *(((int8*)reg)+67)=0; +#define SetV(flag) if (flag) *(((int8*)reg)+66)=1; else *(((int8*)reg)+66)=0; +#define SetX(flag) if (flag) *(((int8*)reg)+68)=1; else *(((int8*)reg)+68)=0; +#define SetT(flag) if (flag) *(((int8*)reg)+69)=1; else *(((int8*)reg)+69)=0; +#define SetZ(flag) if (flag) *(((int8*)reg)+64)=1; else *(((int8*)reg)+64)=0; +#define SetZI(flag) if (flag) *(((int8*)reg)+64)=0; else *(((int8*)reg)+64)=1; +#define SetN(flag) if (flag) *(((int8*)reg)+65)=1; else *(((int8*)reg)+65)=0; +#define SetXC(flag) if (flag) *(((int8*)reg)+68)=*(((int8*)reg)+67)=1; else *(((int8*)reg)+68)=*(((int8*)reg)+67)=0; + +#define ForceX(flag) *(((int8*)reg)+68)=flag; +#define ForceC(flag) *(((int8*)reg)+67)=flag; +#define ForceV(flag) *(((int8*)reg)+66)=flag; +#define ForceZ(flag) *(((int8*)reg)+64)=flag; +#define ForceCVNZ(operand) reg[16]=operand; + +#define ZeroZ(flag) if (flag) *(((int8*)reg)+64)=0; + +#define SetNZ(operand) \ + if (operand==0) *(((int16*)reg)+32)=0x1; \ + else if (operand<0) *(((int16*)reg)+32)=0x100; \ + else *(((int16*)reg)+32)=0; + +#define SetI(imask) intmask=(imask); recalc_int=1; + +#define SetS(flag) \ + if (*(((int8*)reg)+70)) ssp=reg[15]; else usp=reg[15]; \ + if (flag) {*(((int8*)reg)+70)=1; reg[15]=ssp;} else {*(((int8*)reg)+70)=0; reg[15]=usp;} + +#define ClrCVSetNZ(operand) \ + if (operand==0) reg[16]=0x1; \ + else if (operand<0) reg[16]=0x100; \ + else reg[16]=0; + +#define GetC() *(((int8*)reg)+67) +#define GetV() *(((int8*)reg)+66) +#define GetZ() *(((int8*)reg)+64) +#define GetN() *(((int8*)reg)+65) +#define GetX() *(((int8*)reg)+68) +#define GetI() intmask +#define GetS() *(((int8*)reg)+70) +#define GetT() *(((int8*)reg)+69) + +//------------------------------- + +extern uint16 GetSRB(void); +extern uint16 GetSRW(void); +extern void SetSRB(unsigned long); +extern void SetSRW(unsigned long); + + +/* + * Other Register Access + */ +#define GetPC() pc +#define SetPC(addr) pc = addr + +#define FastMPCB() (char)(biginst>>16) +#define FastMPCW() (((int32)biginst)>>16) +#define FastMPCW32() (biginst>>16) + +#define GetMPCB() GetMemBpc (pc + 1) +#define GetMPCW() GetMemWpc (pc) +#define GetMPCL() GetMemLpc (pc) + +#define IncMPCB(var) {register uint32 regpc=pc; pc=regpc+2; var=GetMemBpc (regpc+1);} +#define IncMPCW(var) {register uint32 regpc=pc; pc=regpc+2; var=GetMemWpc (regpc);} +#define IncMPCL(var) {register uint32 regpc=pc; pc=regpc+4; var=GetMemLpc (regpc);} + +#define GetRegB(regno) (int8) reg[regno] +#define GetRegW(regno) (int16) reg[regno] +#define GetRegL(regno) (int32) reg[regno] + +#define GetARegW(regno) (int16) reg[regno+8] +#define GetARegL(regno) (int32) reg[regno+8] + +#ifndef USE_LITTLE_ENDIAN /* USE_BIG_ENDIAN */ +#define SetRegB(regno, value) *(((int8 *) ®[regno]) + 3) = value +#define SetRegW(regno, value) *(((int16 *) ®[regno]) + 1) = value +#define SetARegW(regno, value) *(((int16 *) ®[regno+8]) + 1) = value +#else /* USE_LITTLE_ENDIAN */ +#define SetRegB(regno, value) *((int8 *) ®[regno]) = value +#define SetRegW(regno, value) *((int16 *) ®[regno]) = value +#define SetARegW(regno, value) *((int16 *) ®[regno+8]) = value +#endif +#define SetRegL(regno, value) reg[regno] = value +#define SetARegL(regno, value) reg[regno+8] = value + + + +/* + * Addressing modes (target) + */ +/* d, a, ain, aip, mai, dai, aix, imm, (eaw,ear,eac) */ +#define CN(address,spec) +#define Cs(address,spec) address=spec; +#define Cd(address,spec) address=spec; +#define Ca(address,spec) address=8+spec; +#define Cain(address,spec) address=reg[spec+8]; +#define CaipW(address,spec) address=reg[spec+8]; reg[spec+8]=address+2; +#define CaipL(address,spec) address=reg[spec+8]; reg[spec+8]=address+4; +#define CmaiW(address,spec) address=reg[spec+8]; address-=2; reg[spec+8]=address; +#define CmaiL(address,spec) address=reg[spec+8]; address-=4; reg[spec+8]=address; +#define Cdai(address,spec) IncMPCW(address); address+=reg[spec+8]; +#define Caix(address,spec) { register uint16 mod = GetMPCW(); pc += 2; address = reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)); } +#define CaipB(address,spec) address=reg[spec+8]; if (spec==7) reg[spec+8]=address+2; else reg[spec+8]=address+1; +#define CaipB15(address,spec) address=reg[spec+8]; reg[spec+8]=address+2; + +#define CmaiB(address,spec) address=reg[spec+8]; if (spec==7) address-=2; else address--; reg[spec+8]=address; +#define CmaiB15(address,spec) address=reg[spec+8]; address-=2; reg[spec+8]=address; + +#define Ceaw(address, spec) \ +switch (spec) {\ +case 0x0:\ + IncMPCW(address);\ + break;\ +case 0x1:\ + IncMPCL(address);\ + cycles += 4;\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + address = 0;\ + break;\ +} +#define Cear(address,spec) \ +{ register uint16 mod;\ + register uint32 regpc=pc;\ +switch (spec) {\ +case 0x0:\ + pc=regpc+2;\ + address = GetMemWpc(regpc);\ + break;\ +case 0x1:\ + pc=regpc+4;\ + address = GetMemLpc(regpc);\ + cycles += 4;\ + break;\ +case 0x2:\ + pc=regpc+2;\ + address = regpc + GetMemWpc(regpc);\ + break;\ +case 0x3:\ + pc=regpc+2;\ + mod = GetMemWpc(regpc);\ + address = regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12));\ + cycles += 2;\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + address = 0;\ + break;\ +}} + +//Faster version of effective address macros +//Only use these when the pc hasn't been advanced by an earlier macro +#define Fdai(address,spec) address=FastMPCW()+reg[spec+8]; pc+=2; +#define Faix(address,spec) {register uint32 mod=FastMPCW32(); pc += 2; address = reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)); } +#define Feaw(address, spec) \ +switch (spec) {\ +case 0x0:\ + address=FastMPCW(); pc+=2;\ + break;\ +case 0x1:\ + IncMPCL(address);\ + cycles += 4;\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + address = 0;\ + break;\ +} +#define Fear(address,spec) \ +{ register uint32 mod;\ + register uint32 regpc=pc;\ +switch (spec) {\ +case 0x0:\ + pc=regpc+2;\ + address = FastMPCW();\ + break;\ +case 0x1:\ + pc=regpc+4;\ + address = GetMemLpc(regpc);\ + cycles += 4;\ + break;\ +case 0x2:\ + pc=regpc+2;\ + address = regpc + FastMPCW();\ + break;\ +case 0x3:\ + pc=regpc+2;\ + mod = FastMPCW32();\ + address = regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12));\ + cycles += 2;\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + address = 0;\ + break;\ +}} + + + +/* + * Operand types: B byte, W word, L long, R regno, A address + */ +#define DN(name) +#define DB(name) register int8 name; +#define DW(name) register int16 name; +#define DL(name) register int32 name; +#define DR(name) register uint16 name; +#define DA(name) register int32 name; + + +/* + * target macros + */ +#define GRB(regno, name) name = GetRegB (regno); +#define GRW(regno, name) name = GetRegW (regno); +#define GRL(regno, name) name = GetRegL (regno); +#define SRB(regno, name) SetRegB (regno, name); +#define SRW(regno, name) SetRegW (regno, name); +#define SRL(regno, name) SetRegL (regno, name); +#define GMB(address, name) name = GetMemB (address); +#define GMW(address, name) name = GetMemW (address); +#define GML(address, name) name = GetMemL (address); +#define GN(address, name) +#define SMB(address, name) SetMemB (address, name); +#define SMW(address, name) SetMemW (address, name); +#define SML(address, name) SetMemL (address, name); +#define SN(address, name) +#define GCB(dummy, name) name = GetSRB (); +#define GCW(dummy, name) name = GetSRW (); +#define SCB(dummy, name) SetSRB (name); +#define SCW(dummy, name) SetSRW (name); +#define GPW(address, name) \ + name = GetMemB(address);\ + name <<= 8;\ + name |= (uint8) GetMemB(address + 2); +#define GPL(address, name) \ + name = GetMemB(address);\ + name <<= 8;\ + name |= (uint8) GetMemB(address + 2);\ + name <<= 8;\ + name |= (uint8) GetMemB(address + 4);\ + name <<= 8;\ + name |= (uint8) GetMemB(address + 6); +#define SPW(address, name) \ + SetMemPW(address, name); +#define SPL(address, name) \ + SetMemPL(address, name); + + +/* + * source macros + */ +#define SdaiPW(var,spec) {uint32 a; Cdai(a,spec); var = GPW(a,var);} +#define SdaiPL(var,spec) {uint32 a; Cdai(a,spec); var = GPL(a,var);} +#define SNN(var,spec) +#define SNQ(var, dummy) var = (int8) biginst; +#define ScB(var,spec) var = GetSRB(); +#define ScW(var,spec) var = GetSRW(); +#define Ss(var,spec) var = spec; +#define SimmB(var,spec) var=FastMPCB(); pc+=2; +#define SimmW(var,spec) var=FastMPCW(); pc+=2; +#define SimmL(var,spec) IncMPCL(var); +#define SdB(var,spec) var = GetRegB (spec); +#define SdW(var,spec) var = GetRegW (spec); +#define SdL(var,spec) var = GetRegL (spec); +#define SaW(var,spec) var = GetARegW (spec); +#define SaL(var,spec) var = GetARegL (spec); +#define SainB(var,spec) var = GetMemB (reg[spec+8]); +#define SainW(var,spec) var = GetMemW (reg[spec+8]); +#define SainL(var,spec) var = GetMemL (reg[spec+8]); +#define SainA(var,spec) var = (reg[spec+8]); +#define SaipW(var,spec) {register uint32 myadr=reg[spec+8]; reg[spec+8]=myadr+2; var=GetMemW(myadr);} +#define SaipL(var,spec) {register uint32 myadr=reg[spec+8]; reg[spec+8]=myadr+4; var=GetMemL(myadr);} +#define SmaiW(var,spec) {register uint32 myadr=reg[spec+8]; myadr-=2; reg[spec+8]=myadr; var=GetMemW(myadr);} +#define SmaiL(var,spec) {register uint32 myadr=reg[spec+8]; myadr-=4; reg[spec+8]=myadr; var=GetMemL(myadr);} +#define SdaiB(var,spec) var = GetMemB(reg[spec+8]+FastMPCW()); pc+=2; +#define SdaiW(var,spec) var = GetMemW(reg[spec+8]+FastMPCW()); pc+=2; +#define SdaiL(var,spec) var = GetMemL(reg[spec+8]+FastMPCW()); pc+=2; +#define SdaiA(var,spec) var = reg[spec+8]+FastMPCW(); pc+=2; +#define SaixB(var,spec) {register uint32 mod=FastMPCW32(); pc+=2; var = GetMemB(reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));}; +#define SaixW(var,spec) {register uint32 mod=FastMPCW32(); pc+=2; var = GetMemW(reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));}; +#define SaixL(var,spec) {register uint32 mod=FastMPCW32(); pc+=2; var = GetMemL(reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));}; +#define SaixA(var,spec) {register uint32 mod=FastMPCW32(); pc+=2; var = (reg[spec+8] + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));}; +#define SaipB(var,spec) {register uint32 myadr=reg[spec+8]; if (spec==7) reg[spec+8]=myadr+2; else reg[spec+8]=myadr+1; var=GetMemB(myadr);} +#define SmaiB(var,spec) {register uint32 myadr=reg[spec+8]; if (spec==7) myadr-=2; else myadr--; reg[spec+8]=myadr; var=GetMemB(myadr);} + +#define SearB(var,spec) \ +{ register uint32 mod;\ + register uint32 regpc=pc;\ +switch (spec) {\ +case 0x0:\ + pc=regpc+2;\ + var = GetMemB (FastMPCW());\ + cycles += 4;\ + break;\ +case 0x1:\ + pc=regpc+4;\ + var = GetMemB (GetMemLpc(regpc));\ + cycles += 8;\ + break;\ +case 0x2:\ + pc=regpc+2;\ + var = GetMemB (regpc+FastMPCW());\ + cycles += 4;\ + break;\ +case 0x3:\ + pc=regpc+2;\ + mod = FastMPCW32();\ + var = GetMemB (regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));\ + cycles += 6;\ + break;\ +case 0x4:\ + pc=regpc+2;\ + var = FastMPCB();\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + var = 0;\ + break;\ +}} +#define SearW(var,spec) \ +{ register uint32 mod;\ + register uint32 regpc=pc;\ +switch (spec) {\ +case 0x0:\ + pc=regpc+2;\ + var = GetMemW (FastMPCW());\ + cycles += 4;\ + break;\ +case 0x1:\ + pc=regpc+4;\ + var = GetMemW (GetMemLpc(regpc));\ + cycles += 8;\ + break;\ +case 0x2:\ + pc=regpc+2;\ + var = GetMemW (regpc+FastMPCW());\ + cycles += 4;\ + break;\ +case 0x3:\ + pc=regpc+2;\ + mod = FastMPCW32();\ + var = GetMemW (regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));\ + cycles += 6;\ + break;\ +case 0x4:\ + pc=regpc+2;\ + var = FastMPCW();\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + var = 0;\ + break;\ +}} +#define SearL(var,spec) \ +{ register uint32 mod;\ + register uint32 regpc=pc;\ +switch (spec) {\ +case 0x0:\ + pc=regpc+2;\ + var = GetMemL (FastMPCW());\ + cycles += 4;\ + break;\ +case 0x1:\ + pc=regpc+4;\ + var = GetMemL (GetMemLpc(regpc));\ + cycles += 8;\ + break;\ +case 0x2:\ + pc=regpc+2;\ + var = GetMemL (regpc+FastMPCW());\ + cycles += 4;\ + break;\ +case 0x3:\ + pc=regpc+2;\ + mod = FastMPCW32();\ + var = GetMemL (regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12)));\ + cycles += 6;\ + break;\ +case 0x4:\ + pc=regpc+4;\ + var = GetMemLpc(regpc);\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + var = 0;\ + break;\ +}} +#define SearA(var,spec) \ +{ register uint32 mod;\ + register uint32 regpc=pc;\ +switch (spec) {\ +case 0x0:\ + pc=regpc+2;\ + var = FastMPCW();\ + break;\ +case 0x1:\ + pc=regpc+4;\ + var = GetMemLpc(regpc);\ + cycles += 4;\ + break;\ +case 0x2:\ + pc=regpc+2;\ + var = regpc+FastMPCW();\ + break;\ +case 0x3:\ + pc=regpc+2;\ + mod = FastMPCW32();\ + var = regpc + (int8) mod + ((mod & 0x800) ? GetRegL(mod >> 12) : GetRegW(mod >> 12));\ + cycles += 2;\ + break;\ +default:\ + ExceptionGroup1(ILLINSTR);\ + var = 0;\ + break;\ +}} + +/* + * Condition-Code queries + */ +#define CCt 0xff +#define CCf 0x00 +#define CChi (!GetC() && !GetZ()) +#define CCls (GetC() || GetZ()) +#define CCcc !GetC() +#define CCcs GetC() +#define CCne !GetZ() +#define CCeq GetZ() +#define CCvc !GetV() +#define CCvs GetV() +#define CCpl !GetN() +#define CCmi GetN() +#define CCge !(GetN() ^ GetV()) +#define CClt (GetN() ^ GetV()) +#define CCgt (!(GetN() ^ GetV()) && !GetZ()) +#define CCle ((GetN() ^ GetV()) || GetZ()) + +/* + * Oper arguments: + * Code Opcode + * Op(target,source) Macro used to execute operation + * DeclS(name) Macro to declare source (such as DB, DW or DL, or + DN=no source, DA=address, DR=register number) + * GetS(var,spec) Macro to fetch source, with addressing mode evaluation. + SNN = no fetch + SNQ = used in MOVEQ + ScB = condition code register + ScW = status register word (s-flag not checked) + Ss = source equals source specifier (spec1) + SaW, SaL = get # data register value + SdB, SdW, SdL = get data register value + SainB, SainW, SainL = (A) + SainA = (LEA only) + SaixB, SaixW, SaixL = (d8,A,X<>) + SaixA = (LEA only) + SdaiB, SdaiW, SdaiL = d16(A) + SdaiA = (LEA only) + SaipB, SaipW, SaipL = (A)+ + SmaiB, SmaiW, SmaiL = -(A) + SimmB, SimmW, SimmL = immediate + SdaiPW, SdaiPL = used in MOVEP + SearB, SearW, SearL = other addressing modes + SearA = (LEA only) + * spec1 source specifier, usually the data or address register number. + * DeclT(name) Macro to declare target (such as DB, DW or DL, or + DN=no target, DA=address, DR=register number) + * DeclEA2(name) Macro to declare target address (typically DA, DR, or DN) + * CalcEA2(address,spec) Macro to calculate address, with addressing mode evaluation. + CN = no address + Cs = equals target specifier (spec2) + Cd = equals target specifier (spec2) (data register number) + Ca = equals target specifier (spec2) + 8 (address register number) + Cain = (A) + Caix = (d8,A,X<>) + Cdai = d16(A) + CaipB, CaipW, CaipL = (A)+, + CaipB15 = stack pointer only + CmaiB, CmaiW, CmaiL = -(A) + CmaiB15 = stack pointer only + Ceaw = other addressing modes (if target is modified) + Cear = other addressing modes (if target is not modified) + * spec2 target specifier, usually the data or address register number. + * GetEA2(address,name) Macro to get target value + GCB = get condition code + GCW = get status (s-flag not checked) + GN = no read + GMB, GMW, GML = read from memory + GPW, GPL = (MOVEP) + GRB, GRW, GRL = read from register + * SetEA2(address,name) Macro to set target value + SCB = set condition code + SCW = set status (s-flag not checked) + SN = no write + SMB, SMW, SML = write to memory + SPW, SPL = (MOVEP) + SRB, SRW, SRL = write to register + */ + +#if (!defined(DEBUG) || !defined(INTERNALTRACE)) +#define Oper(Code, Op, DeclS, GetS, spec1, DeclT, DeclEA2, CalcEA2, spec2, GetEA2, SetEA2, rval)\ +unsigned long Code(operin)\ +{\ + register unsigned long cycles=0;\ + DeclS (source)\ + DeclT (target)\ + DeclEA2 (address2)\ + GetS (source, spec1)\ + CalcEA2 (address2, spec2)\ + GetEA2 (address2, target)\ + Op (target, source)\ + SetEA2 (address2, target)\ + return rval; \ +} +#else +/* quick'n dirty debug hack */ +#undef DN +#define DN(name) int name; +#define Oper(Code, Op, DeclS, GetS, spec1, DeclT, DeclEA2, CalcEA2, spec2, GetEA2, SetEA2, rval)\ +unsigned long Code(operin)\ +{\ + register unsigned long cycles=0;\ + DeclS (source)\ + DeclT (target)\ + DeclEA2 (address2)\ + source = 0; \ + target = 0; \ + address2 = 0; \ + GetS (source, spec1)\ + CalcEA2 (address2, spec2)\ + GetEA2 (address2, target)\ + traceback[tbi].address = address2; \ + traceback[tbi].source = source; \ + traceback[tbi].target = target; \ + Op (target, source)\ + traceback[tbi].result = target; \ + SetEA2 (address2, target)\ + return rval; \ +} +#endif +#endif diff --git a/MCUME_esp32/espcastaway/main/68korigbad/op68kadd.cpp b/MCUME_esp32/espcastaway/main/68korigbad/op68kadd.cpp new file mode 100755 index 0000000..a000189 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/op68kadd.cpp @@ -0,0 +1,809 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - 68k add instructions +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 10.07.2002 JH Fixed Z-Flag for ADDX +* 08.10.2002 JH Fixed Z-Flag for ADD.B 0x80+0x80 and Add.W 0x8000+0x8000. +*/ +#ifndef PROTOH +static char sccsid[] = "$Id: op68kadd.c,v 1.3 2002/10/08 00:18:02 jhoenig Exp $"; +#include "68000.h" +#include "op68k.h" + +/* +* Opfuncs. +*/ + +#define DoAddB(target,source) \ +{register int32 tgt,cvnz=0;\ + tgt = target + source;\ + if ((uint32) source > (uint32) ~target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\ + target = tgt;\ + if (tgt!=target) cvnz+=Vflag;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoAddW(target,source) \ +{register int32 tgt,cvnz=0;\ + tgt = target + source;\ + if ((uint32) source > (uint32) ~target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\ + target = tgt;\ + if (tgt!=target) cvnz+=Vflag;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoAddL(target,source) \ + /* Overflow precondition: source has same sign */\ +{register int32 precon=(target>>31)-(source>>31),cvnz=0;\ + if ((uint32) source > (uint32) ~target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\ + target += source;\ + /* target and source now have different sign: overflow! */\ + if (precon==0 && (target>>31)!=(source>>31)) cvnz+=Vflag;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoAdda(target,source) target += source; + +#define DoAddx(target,source) \ + /* Overflow precondition: source has same sign */\ +{register int32 precon=(target>>31)-(source>>31);\ + if (GetX ()) {\ + SetXC ((uint32) source >= (uint32) ~target);\ + target += source + 1;\ + } else {\ + SetXC ((uint32) source > (uint32) ~target);\ + target += source;\ +}\ + /* target and source now have different sign: overflow! */\ + SetV(precon==0 && (target>>31)!=(source>>31));\ + ZeroZ(target!=0);\ +SetN(target < 0);}; + +#endif + +Oper (Opd000, DoAddB, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4) +Oper (Opd010, DoAddB, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Opd018, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Opd020, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Opd028, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Opd030, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SRB, 16) +Oper (Opd038, DoAddB, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opd040, DoAddW, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Opd048, DoAddW, DW, SaW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Opd050, DoAddW, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Opd058, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Opd060, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Opd068, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Opd070, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SRW, 16) +Oper (Opd078, DoAddW, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opd080, DoAddL, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Opd088, DoAddL, DL, SaL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Opd090, DoAddL, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Opd098, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Opd0a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Opd0a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Opd0b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Opd0b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opd0c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Opd0c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Opd0d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 0, GRL, SRL, 12) +Oper (Opd0d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 0, GRL, SRL, 12) +Oper (Opd0e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Opd0e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Opd0f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 0, GRL, SRL, 20) +Oper (Opd0f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 0, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opd100, DoAddx, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4) +Oper (Opd108, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 0, GMB, SMB, 20) +Oper (Opd110, DoAddB, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opd118, DoAddB, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opd120, DoAddB, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opd128, DoAddB, DB, SdB, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opd130, DoAddB, DB, SdB, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opd138, DoAddB, DB, SdB, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opd140, DoAddx, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Opd148, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 0, GMW, SMW, 20) +Oper (Opd150, DoAddW, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opd158, DoAddW, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opd160, DoAddW, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opd168, DoAddW, DW, SdW, 0, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opd170, DoAddW, DW, SdW, 0, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opd178, DoAddW, DW, SdW, 0, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opd180, DoAddx, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Opd188, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 0, GML, SML, 32) +Oper (Opd190, DoAddL, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opd198, DoAddL, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opd1a0, DoAddL, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opd1a8, DoAddL, DL, SdL, 0, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opd1b0, DoAddL, DL, SdL, 0, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opd1b8, DoAddL, DL, SdL, 0, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opd1c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Opd1c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Opd1d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Opd1d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Opd1e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Opd1e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 0, GRL, SRL, 20) +Oper (Opd1f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 0, GRL, SRL, 20) +Oper (Opd1f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 0, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opd200, DoAddB, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4) +Oper (Opd210, DoAddB, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Opd218, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Opd220, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Opd228, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Opd230, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SRB, 16) +Oper (Opd238, DoAddB, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opd240, DoAddW, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Opd248, DoAddW, DW, SaW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Opd250, DoAddW, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Opd258, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Opd260, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Opd268, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Opd270, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SRW, 16) +Oper (Opd278, DoAddW, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opd280, DoAddL, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Opd288, DoAddL, DL, SaL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Opd290, DoAddL, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Opd298, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Opd2a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Opd2a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Opd2b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Opd2b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opd2c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Opd2c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Opd2d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 1, GRL, SRL, 12) +Oper (Opd2d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 1, GRL, SRL, 12) +Oper (Opd2e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Opd2e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Opd2f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 1, GRL, SRL, 20) +Oper (Opd2f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 1, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opd300, DoAddx, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4) +Oper (Opd308, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 1, GMB, SMB, 20) +Oper (Opd310, DoAddB, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opd318, DoAddB, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opd320, DoAddB, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opd328, DoAddB, DB, SdB, 1, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opd330, DoAddB, DB, SdB, 1, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opd338, DoAddB, DB, SdB, 1, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opd340, DoAddx, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Opd348, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 1, GMW, SMW, 20) +Oper (Opd350, DoAddW, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opd358, DoAddW, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opd360, DoAddW, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opd368, DoAddW, DW, SdW, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opd370, DoAddW, DW, SdW, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opd378, DoAddW, DW, SdW, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opd380, DoAddx, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Opd388, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 1, GML, SML, 32) +Oper (Opd390, DoAddL, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opd398, DoAddL, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opd3a0, DoAddL, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opd3a8, DoAddL, DL, SdL, 1, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opd3b0, DoAddL, DL, SdL, 1, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opd3b8, DoAddL, DL, SdL, 1, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opd3c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Opd3c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Opd3d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Opd3d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Opd3e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Opd3e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 1, GRL, SRL, 20) +Oper (Opd3f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 1, GRL, SRL, 20) +Oper (Opd3f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 1, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opd400, DoAddB, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4) +Oper (Opd410, DoAddB, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Opd418, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Opd420, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Opd428, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Opd430, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SRB, 16) +Oper (Opd438, DoAddB, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opd440, DoAddW, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Opd448, DoAddW, DW, SaW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Opd450, DoAddW, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Opd458, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Opd460, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Opd468, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Opd470, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SRW, 16) +Oper (Opd478, DoAddW, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opd480, DoAddL, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Opd488, DoAddL, DL, SaL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Opd490, DoAddL, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Opd498, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Opd4a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Opd4a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Opd4b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Opd4b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opd4c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Opd4c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Opd4d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 2, GRL, SRL, 12) +Oper (Opd4d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 2, GRL, SRL, 12) +Oper (Opd4e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Opd4e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Opd4f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 2, GRL, SRL, 20) +Oper (Opd4f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 2, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opd500, DoAddx, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4) +Oper (Opd508, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 2, GMB, SMB, 20) +Oper (Opd510, DoAddB, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opd518, DoAddB, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opd520, DoAddB, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opd528, DoAddB, DB, SdB, 2, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opd530, DoAddB, DB, SdB, 2, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opd538, DoAddB, DB, SdB, 2, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opd540, DoAddx, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Opd548, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 2, GMW, SMW, 20) +Oper (Opd550, DoAddW, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opd558, DoAddW, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opd560, DoAddW, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opd568, DoAddW, DW, SdW, 2, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opd570, DoAddW, DW, SdW, 2, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opd578, DoAddW, DW, SdW, 2, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opd580, DoAddx, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Opd588, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 2, GML, SML, 32) +Oper (Opd590, DoAddL, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opd598, DoAddL, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opd5a0, DoAddL, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opd5a8, DoAddL, DL, SdL, 2, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opd5b0, DoAddL, DL, SdL, 2, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opd5b8, DoAddL, DL, SdL, 2, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opd5c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Opd5c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Opd5d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Opd5d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Opd5e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Opd5e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 2, GRL, SRL, 20) +Oper (Opd5f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 2, GRL, SRL, 20) +Oper (Opd5f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 2, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opd600, DoAddB, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4) +Oper (Opd610, DoAddB, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Opd618, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Opd620, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Opd628, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Opd630, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SRB, 16) +Oper (Opd638, DoAddB, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opd640, DoAddW, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Opd648, DoAddW, DW, SaW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Opd650, DoAddW, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Opd658, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Opd660, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Opd668, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Opd670, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SRW, 16) +Oper (Opd678, DoAddW, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opd680, DoAddL, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Opd688, DoAddL, DL, SaL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Opd690, DoAddL, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Opd698, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Opd6a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Opd6a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Opd6b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Opd6b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opd6c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Opd6c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Opd6d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 3, GRL, SRL, 12) +Oper (Opd6d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 3, GRL, SRL, 12) +Oper (Opd6e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Opd6e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Opd6f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 3, GRL, SRL, 20) +Oper (Opd6f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 3, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opd700, DoAddx, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4) +Oper (Opd708, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 3, GMB, SMB, 20) +Oper (Opd710, DoAddB, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opd718, DoAddB, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opd720, DoAddB, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opd728, DoAddB, DB, SdB, 3, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opd730, DoAddB, DB, SdB, 3, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opd738, DoAddB, DB, SdB, 3, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opd740, DoAddx, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Opd748, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 3, GMW, SMW, 20) +Oper (Opd750, DoAddW, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opd758, DoAddW, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opd760, DoAddW, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opd768, DoAddW, DW, SdW, 3, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opd770, DoAddW, DW, SdW, 3, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opd778, DoAddW, DW, SdW, 3, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opd780, DoAddx, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Opd788, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 3, GML, SML, 32) +Oper (Opd790, DoAddL, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opd798, DoAddL, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opd7a0, DoAddL, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opd7a8, DoAddL, DL, SdL, 3, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opd7b0, DoAddL, DL, SdL, 3, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opd7b8, DoAddL, DL, SdL, 3, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opd7c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Opd7c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Opd7d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Opd7d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Opd7e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Opd7e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 3, GRL, SRL, 20) +Oper (Opd7f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 3, GRL, SRL, 20) +Oper (Opd7f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 3, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opd800, DoAddB, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4) +Oper (Opd810, DoAddB, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Opd818, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Opd820, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Opd828, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Opd830, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SRB, 16) +Oper (Opd838, DoAddB, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opd840, DoAddW, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Opd848, DoAddW, DW, SaW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Opd850, DoAddW, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Opd858, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Opd860, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Opd868, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Opd870, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SRW, 16) +Oper (Opd878, DoAddW, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opd880, DoAddL, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Opd888, DoAddL, DL, SaL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Opd890, DoAddL, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Opd898, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Opd8a0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Opd8a8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Opd8b0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Opd8b8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opd8c0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Opd8c8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Opd8d0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 4, GRL, SRL, 12) +Oper (Opd8d8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 4, GRL, SRL, 12) +Oper (Opd8e0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Opd8e8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Opd8f0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 4, GRL, SRL, 20) +Oper (Opd8f8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 4, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opd900, DoAddx, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4) +Oper (Opd908, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 4, GMB, SMB, 20) +Oper (Opd910, DoAddB, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opd918, DoAddB, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opd920, DoAddB, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opd928, DoAddB, DB, SdB, 4, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opd930, DoAddB, DB, SdB, 4, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opd938, DoAddB, DB, SdB, 4, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opd940, DoAddx, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Opd948, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 4, GMW, SMW, 20) +Oper (Opd950, DoAddW, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opd958, DoAddW, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opd960, DoAddW, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opd968, DoAddW, DW, SdW, 4, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opd970, DoAddW, DW, SdW, 4, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opd978, DoAddW, DW, SdW, 4, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opd980, DoAddx, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Opd988, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 4, GML, SML, 32) +Oper (Opd990, DoAddL, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opd998, DoAddL, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opd9a0, DoAddL, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opd9a8, DoAddL, DL, SdL, 4, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opd9b0, DoAddL, DL, SdL, 4, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opd9b8, DoAddL, DL, SdL, 4, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opd9c0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Opd9c8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Opd9d0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Opd9d8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Opd9e0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Opd9e8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 4, GRL, SRL, 20) +Oper (Opd9f0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 4, GRL, SRL, 20) +Oper (Opd9f8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 4, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opda00, DoAddB, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4) +Oper (Opda10, DoAddB, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Opda18, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Opda20, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Opda28, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Opda30, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SRB, 16) +Oper (Opda38, DoAddB, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opda40, DoAddW, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Opda48, DoAddW, DW, SaW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Opda50, DoAddW, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Opda58, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Opda60, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Opda68, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Opda70, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SRW, 16) +Oper (Opda78, DoAddW, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opda80, DoAddL, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Opda88, DoAddL, DL, SaL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Opda90, DoAddL, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Opda98, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Opdaa0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Opdaa8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Opdab0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Opdab8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opdac0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Opdac8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Opdad0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 5, GRL, SRL, 12) +Oper (Opdad8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 5, GRL, SRL, 12) +Oper (Opdae0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Opdae8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Opdaf0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 5, GRL, SRL, 20) +Oper (Opdaf8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 5, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opdb00, DoAddx, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4) +Oper (Opdb08, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 5, GMB, SMB, 20) +Oper (Opdb10, DoAddB, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opdb18, DoAddB, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opdb20, DoAddB, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opdb28, DoAddB, DB, SdB, 5, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opdb30, DoAddB, DB, SdB, 5, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opdb38, DoAddB, DB, SdB, 5, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opdb40, DoAddx, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Opdb48, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 5, GMW, SMW, 20) +Oper (Opdb50, DoAddW, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opdb58, DoAddW, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opdb60, DoAddW, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opdb68, DoAddW, DW, SdW, 5, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opdb70, DoAddW, DW, SdW, 5, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opdb78, DoAddW, DW, SdW, 5, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opdb80, DoAddx, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Opdb88, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 5, GML, SML, 32) +Oper (Opdb90, DoAddL, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opdb98, DoAddL, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opdba0, DoAddL, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opdba8, DoAddL, DL, SdL, 5, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opdbb0, DoAddL, DL, SdL, 5, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opdbb8, DoAddL, DL, SdL, 5, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opdbc0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Opdbc8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Opdbd0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Opdbd8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Opdbe0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Opdbe8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 5, GRL, SRL, 20) +Oper (Opdbf0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 5, GRL, SRL, 20) +Oper (Opdbf8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 5, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opdc00, DoAddB, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4) +Oper (Opdc10, DoAddB, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Opdc18, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Opdc20, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Opdc28, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Opdc30, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SRB, 16) +Oper (Opdc38, DoAddB, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opdc40, DoAddW, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Opdc48, DoAddW, DW, SaW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Opdc50, DoAddW, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Opdc58, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Opdc60, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Opdc68, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Opdc70, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SRW, 16) +Oper (Opdc78, DoAddW, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opdc80, DoAddL, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Opdc88, DoAddL, DL, SaL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Opdc90, DoAddL, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Opdc98, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Opdca0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Opdca8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Opdcb0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Opdcb8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opdcc0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Opdcc8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Opdcd0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 6, GRL, SRL, 12) +Oper (Opdcd8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 6, GRL, SRL, 12) +Oper (Opdce0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Opdce8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Opdcf0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 6, GRL, SRL, 20) +Oper (Opdcf8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 6, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opdd00, DoAddx, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4) +Oper (Opdd08, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB, 6, GMB, SMB, 20) +Oper (Opdd10, DoAddB, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opdd18, DoAddB, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opdd20, DoAddB, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opdd28, DoAddB, DB, SdB, 6, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opdd30, DoAddB, DB, SdB, 6, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opdd38, DoAddB, DB, SdB, 6, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opdd40, DoAddx, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Opdd48, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 6, GMW, SMW, 20) +Oper (Opdd50, DoAddW, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opdd58, DoAddW, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opdd60, DoAddW, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opdd68, DoAddW, DW, SdW, 6, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opdd70, DoAddW, DW, SdW, 6, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opdd78, DoAddW, DW, SdW, 6, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opdd80, DoAddx, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Opdd88, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 6, GML, SML, 32) +Oper (Opdd90, DoAddL, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opdd98, DoAddL, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opdda0, DoAddL, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opdda8, DoAddL, DL, SdL, 6, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opddb0, DoAddL, DL, SdL, 6, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opddb8, DoAddL, DL, SdL, 6, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opddc0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Opddc8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Opddd0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Opddd8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Opdde0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Opdde8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 6, GRL, SRL, 20) +Oper (Opddf0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 6, GRL, SRL, 20) +Oper (Opddf8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 6, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opde00, DoAddB, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4) +Oper (Opde10, DoAddB, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Opde18, DoAddB, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Opde20, DoAddB, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Opde28, DoAddB, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Opde30, DoAddB, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SRB, 16) +Oper (Opde38, DoAddB, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opde40, DoAddW, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Opde48, DoAddW, DW, SaW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Opde50, DoAddW, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Opde58, DoAddW, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Opde60, DoAddW, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Opde68, DoAddW, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Opde70, DoAddW, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SRW, 16) +Oper (Opde78, DoAddW, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opde80, DoAddL, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Opde88, DoAddL, DL, SaL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Opde90, DoAddL, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Opde98, DoAddL, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Opdea0, DoAddL, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Opdea8, DoAddL, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Opdeb0, DoAddL, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Opdeb8, DoAddL, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Opdec0, DoAdda, DL, SdW, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Opdec8, DoAdda, DL, SaW, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Opded0, DoAdda, DL, SainW, ins7, DL, DR, Ca, 7, GRL, SRL, 12) +Oper (Opded8, DoAdda, DL, SaipW, ins7, DL, DR, Ca, 7, GRL, SRL, 12) +Oper (Opdee0, DoAdda, DL, SmaiW, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Opdee8, DoAdda, DL, SdaiW, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Opdef0, DoAdda, DL, SaixW, ins7, DL, DR, Ca, 7, GRL, SRL, 20) +Oper (Opdef8, DoAdda, DL, SearW, ins7, DL, DR, Ca, 7, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Opdf00, DoAddx, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4) +Oper (Opdf08, DoAddx, DB, SmaiB, ins7, DB, DA, CmaiB15, 7, GMB, SMB, 20) +Oper (Opdf10, DoAddB, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opdf18, DoAddB, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opdf20, DoAddB, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opdf28, DoAddB, DB, SdB, 7, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Opdf30, DoAddB, DB, SdB, 7, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Opdf38, DoAddB, DB, SdB, 7, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opdf40, DoAddx, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Opdf48, DoAddx, DW, SmaiW, ins7, DW, DA, CmaiW, 7, GMW, SMW, 20) +Oper (Opdf50, DoAddW, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opdf58, DoAddW, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opdf60, DoAddW, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opdf68, DoAddW, DW, SdW, 7, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Opdf70, DoAddW, DW, SdW, 7, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Opdf78, DoAddW, DW, SdW, 7, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opdf80, DoAddx, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Opdf88, DoAddx, DL, SmaiL, ins7, DL, DA, CmaiL, 7, GML, SML, 32) +Oper (Opdf90, DoAddL, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opdf98, DoAddL, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opdfa0, DoAddL, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opdfa8, DoAddL, DL, SdL, 7, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Opdfb0, DoAddL, DL, SdL, 7, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Opdfb8, DoAddL, DL, SdL, 7, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Opdfc0, DoAdda, DL, SdL, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Opdfc8, DoAdda, DL, SaL, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Opdfd0, DoAdda, DL, SainL, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Opdfd8, DoAdda, DL, SaipL, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Opdfe0, DoAdda, DL, SmaiL, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Opdfe8, DoAdda, DL, SdaiL, ins7, DL, DR, Ca, 7, GRL, SRL, 20) +Oper (Opdff0, DoAdda, DL, SaixL, ins7, DL, DR, Ca, 7, GRL, SRL, 20) +Oper (Opdff8, DoAdda, DL, SearL, ins7, DL, DR, Ca, 7, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op0600, DoAddB, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8) +Oper (Op0610, DoAddB, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op0618, DoAddB, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op0620, DoAddB, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op0628, DoAddB, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op0630, DoAddB, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +Oper (Op0638, DoAddB, DB, SimmB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+23)&0xfffffffc) +Oper (Op0640, DoAddW, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8) +Oper (Op0650, DoAddW, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16) +Oper (Op0658, DoAddW, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16) +Oper (Op0660, DoAddW, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20) +Oper (Op0668, DoAddW, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20) +Oper (Op0670, DoAddW, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24) +Oper (Op0678, DoAddW, DW, SimmW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+23)&0xfffffffc) +Oper (Op0680, DoAddL, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16) +Oper (Op0690, DoAddL, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28) +Oper (Op0698, DoAddL, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28) +Oper (Op06a0, DoAddL, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32) +Oper (Op06a8, DoAddL, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32) +Oper (Op06b0, DoAddL, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36) +Oper (Op06b8, DoAddL, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc) + +Oper (Op5000, DoAddB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5010, DoAddB, DB, Ss, 8, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5018, DoAddB, DB, Ss, 8, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5020, DoAddB, DB, Ss, 8, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5028, DoAddB, DB, Ss, 8, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5030, DoAddB, DB, Ss, 8, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5038, DoAddB, DB, Ss, 8, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5040, DoAddW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5048, DoAdda, DL, Ss, 8, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5050, DoAddW, DW, Ss, 8, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5058, DoAddW, DW, Ss, 8, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5060, DoAddW, DW, Ss, 8, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5068, DoAddW, DW, Ss, 8, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5070, DoAddW, DW, Ss, 8, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5078, DoAddW, DW, Ss, 8, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5080, DoAddL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5088, DoAdda, DL, Ss, 8, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5090, DoAddL, DL, Ss, 8, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5098, DoAddL, DL, Ss, 8, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op50a0, DoAddL, DL, Ss, 8, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op50a8, DoAddL, DL, Ss, 8, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op50b0, DoAddL, DL, Ss, 8, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op50b8, DoAddL, DL, Ss, 8, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5200, DoAddB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5210, DoAddB, DB, Ss, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5218, DoAddB, DB, Ss, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5220, DoAddB, DB, Ss, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5228, DoAddB, DB, Ss, 1, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5230, DoAddB, DB, Ss, 1, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5238, DoAddB, DB, Ss, 1, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5240, DoAddW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5248, DoAdda, DL, Ss, 1, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5250, DoAddW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5258, DoAddW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5260, DoAddW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5268, DoAddW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5270, DoAddW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5278, DoAddW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5280, DoAddL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5288, DoAdda, DL, Ss, 1, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5290, DoAddL, DL, Ss, 1, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5298, DoAddL, DL, Ss, 1, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op52a0, DoAddL, DL, Ss, 1, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op52a8, DoAddL, DL, Ss, 1, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op52b0, DoAddL, DL, Ss, 1, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op52b8, DoAddL, DL, Ss, 1, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5400, DoAddB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5410, DoAddB, DB, Ss, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5418, DoAddB, DB, Ss, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5420, DoAddB, DB, Ss, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5428, DoAddB, DB, Ss, 2, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5430, DoAddB, DB, Ss, 2, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5438, DoAddB, DB, Ss, 2, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5440, DoAddW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5448, DoAdda, DL, Ss, 2, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5450, DoAddW, DW, Ss, 2, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5458, DoAddW, DW, Ss, 2, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5460, DoAddW, DW, Ss, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5468, DoAddW, DW, Ss, 2, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5470, DoAddW, DW, Ss, 2, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5478, DoAddW, DW, Ss, 2, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5480, DoAddL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5488, DoAdda, DL, Ss, 2, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5490, DoAddL, DL, Ss, 2, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5498, DoAddL, DL, Ss, 2, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op54a0, DoAddL, DL, Ss, 2, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op54a8, DoAddL, DL, Ss, 2, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op54b0, DoAddL, DL, Ss, 2, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op54b8, DoAddL, DL, Ss, 2, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5600, DoAddB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5610, DoAddB, DB, Ss, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5618, DoAddB, DB, Ss, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5620, DoAddB, DB, Ss, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5628, DoAddB, DB, Ss, 3, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5630, DoAddB, DB, Ss, 3, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5638, DoAddB, DB, Ss, 3, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5640, DoAddW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5648, DoAdda, DL, Ss, 3, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5650, DoAddW, DW, Ss, 3, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5658, DoAddW, DW, Ss, 3, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5660, DoAddW, DW, Ss, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5668, DoAddW, DW, Ss, 3, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5670, DoAddW, DW, Ss, 3, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5678, DoAddW, DW, Ss, 3, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5680, DoAddL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5688, DoAdda, DL, Ss, 3, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5690, DoAddL, DL, Ss, 3, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5698, DoAddL, DL, Ss, 3, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op56a0, DoAddL, DL, Ss, 3, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op56a8, DoAddL, DL, Ss, 3, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op56b0, DoAddL, DL, Ss, 3, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op56b8, DoAddL, DL, Ss, 3, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5800, DoAddB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5810, DoAddB, DB, Ss, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5818, DoAddB, DB, Ss, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5820, DoAddB, DB, Ss, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5828, DoAddB, DB, Ss, 4, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5830, DoAddB, DB, Ss, 4, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5838, DoAddB, DB, Ss, 4, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5840, DoAddW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5848, DoAdda, DL, Ss, 4, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5850, DoAddW, DW, Ss, 4, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5858, DoAddW, DW, Ss, 4, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5860, DoAddW, DW, Ss, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5868, DoAddW, DW, Ss, 4, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5870, DoAddW, DW, Ss, 4, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5878, DoAddW, DW, Ss, 4, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5880, DoAddL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5888, DoAdda, DL, Ss, 4, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5890, DoAddL, DL, Ss, 4, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5898, DoAddL, DL, Ss, 4, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op58a0, DoAddL, DL, Ss, 4, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op58a8, DoAddL, DL, Ss, 4, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op58b0, DoAddL, DL, Ss, 4, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op58b8, DoAddL, DL, Ss, 4, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5a00, DoAddB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5a10, DoAddB, DB, Ss, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5a18, DoAddB, DB, Ss, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5a20, DoAddB, DB, Ss, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5a28, DoAddB, DB, Ss, 5, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5a30, DoAddB, DB, Ss, 5, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5a38, DoAddB, DB, Ss, 5, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5a40, DoAddW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5a48, DoAdda, DL, Ss, 5, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5a50, DoAddW, DW, Ss, 5, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5a58, DoAddW, DW, Ss, 5, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5a60, DoAddW, DW, Ss, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5a68, DoAddW, DW, Ss, 5, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5a70, DoAddW, DW, Ss, 5, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5a78, DoAddW, DW, Ss, 5, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5a80, DoAddL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5a88, DoAdda, DL, Ss, 5, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5a90, DoAddL, DL, Ss, 5, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5a98, DoAddL, DL, Ss, 5, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op5aa0, DoAddL, DL, Ss, 5, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op5aa8, DoAddL, DL, Ss, 5, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op5ab0, DoAddL, DL, Ss, 5, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op5ab8, DoAddL, DL, Ss, 5, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5c00, DoAddB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5c10, DoAddB, DB, Ss, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5c18, DoAddB, DB, Ss, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5c20, DoAddB, DB, Ss, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5c28, DoAddB, DB, Ss, 6, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5c30, DoAddB, DB, Ss, 6, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5c38, DoAddB, DB, Ss, 6, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5c40, DoAddW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5c48, DoAdda, DL, Ss, 6, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5c50, DoAddW, DW, Ss, 6, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5c58, DoAddW, DW, Ss, 6, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5c60, DoAddW, DW, Ss, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5c68, DoAddW, DW, Ss, 6, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5c70, DoAddW, DW, Ss, 6, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5c78, DoAddW, DW, Ss, 6, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5c80, DoAddL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5c88, DoAdda, DL, Ss, 6, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5c90, DoAddL, DL, Ss, 6, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5c98, DoAddL, DL, Ss, 6, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op5ca0, DoAddL, DL, Ss, 6, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op5ca8, DoAddL, DL, Ss, 6, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op5cb0, DoAddL, DL, Ss, 6, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op5cb8, DoAddL, DL, Ss, 6, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5e00, DoAddB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5e10, DoAddB, DB, Ss, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5e18, DoAddB, DB, Ss, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5e20, DoAddB, DB, Ss, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5e28, DoAddB, DB, Ss, 7, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5e30, DoAddB, DB, Ss, 7, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5e38, DoAddB, DB, Ss, 7, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5e40, DoAddW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5e48, DoAdda, DL, Ss, 7, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5e50, DoAddW, DW, Ss, 7, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5e58, DoAddW, DW, Ss, 7, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5e60, DoAddW, DW, Ss, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5e68, DoAddW, DW, Ss, 7, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5e70, DoAddW, DW, Ss, 7, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5e78, DoAddW, DW, Ss, 7, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5e80, DoAddL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5e88, DoAdda, DL, Ss, 7, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5e90, DoAddL, DL, Ss, 7, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5e98, DoAddL, DL, Ss, 7, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op5ea0, DoAddL, DL, Ss, 7, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op5ea8, DoAddL, DL, Ss, 7, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op5eb0, DoAddL, DL, Ss, 7, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op5eb8, DoAddL, DL, Ss, 7, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) diff --git a/MCUME_esp32/espcastaway/main/68korigbad/op68karith.cpp b/MCUME_esp32/espcastaway/main/68korigbad/op68karith.cpp new file mode 100755 index 0000000..0b86d91 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/op68karith.cpp @@ -0,0 +1,844 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - 68k arithmetic instructions +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 12.06.2002 JH Correct bus error/address error exception stack frame +* 13.06.2002 JH Merged in Martin's BCD implementation (untested), +* completed jump table. STOP is now the only +* unimplemented instruction. +* 08.10.2002 JH Fixed Z-Flag for ADD.B 0x80+0x80 and Add.W 0x8000+0x8000. +*/ +#ifndef PROTOH +static char sccsid[] = "$Id: op68karith.c,v 1.5 2002/10/08 00:18:02 jhoenig Exp $"; +#include "68000.h" +#include "op68k.h" + +#include + +/* +* Opfuncs. +*/ + +#define DoCmpB(target,source) \ +{register int32 tgt,cvnz=0; register int8 tgt8;\ + tgt = target - source;\ + if ((uint32) source > (uint32) target) cvnz+=Cflag;\ + tgt8=tgt;\ + if (tgt!=tgt8) cvnz+=Vflag;\ + if (tgt8==0) cvnz+=Zflag;\ + else if (tgt8<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoCmpW(target,source) \ +{register int32 tgt,cvnz=0; register int16 tgt16;\ + tgt = target - source;\ + if ((uint32) source > (uint32) target) cvnz+=Cflag;\ + tgt16=tgt;\ + if (tgt!=tgt16) cvnz+=Vflag;\ + if (tgt16==0) cvnz+=Zflag;\ + else if (tgt16<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoCmpL(target,source) \ + /* Overflow precondition: source has different sign */\ +{register int32 precon=(target>>31)-(source>>31),cvnz=0;\ + if ((uint32) source > (uint32) target) cvnz+=Cflag;\ + target -= source;\ + /* target and source now have same sign: overflow! */\ + if (precon && (target>>31)==(source>>31)) cvnz+=Vflag;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoCmpa(target,source) DoCmpL(target,source) +#define DoCmpm(target,source) DoCmpL(target,source) + + +#define DoDivs(target,source) \ + if (source == 0) {\ + ExceptionGroup2(DIVZ);\ + } else {\ + int16 quot, rest;\ + if ((target / source) > 32767 || (target / source) < -32768) {\ + ForceV (1);\ + ForceC (0);\ + } else {\ + rest = target % source;\ + quot = target / source;\ + target = (rest << 16) | (uint16) quot;\ + ClrCVSetNZ ((int16) target);\ +}\ +} + +#define DoDivu(target,source) \ + if (source == 0) {\ + ExceptionGroup2(DIVZ);\ + } else {\ + uint16 quot, rest;\ + if (((uint32) target / (uint16) source) & 0xffff0000) {\ + ForceV (1);\ + ForceC (0);\ + } else {\ + rest = (uint32) target % (uint16) source;\ + quot = (uint32) target / (uint16) source;\ + target = (rest << 16) | quot;\ + ClrCVSetNZ ((int16) target);\ +}\ +} + +#define DoMuls(target,source) \ + target = ((int16) target * source);\ +ClrCVSetNZ (target); + +#define DoMulu(target,source) \ + target = ((uint16) target * (uint16) source);\ +ClrCVSetNZ (target); + +//#define DoSuba(target,source) target -= source; + +/* +#define DoSubx(target,source) \ +// Overflow precondition: source has different sign \ +SetV ((target < 0) != (source < 0));\ +if (GetX ()) {\ +SetXC ((uint32) source >= (uint32) target);\ +target -= source;\ +target -= 1;\ +} else {\ +SetXC ((uint32) source > (uint32) target);\ +target -= source;\ +}\ +//target and source now have same sign: overflow! +SetV (GetV() && (target<0) == (source<0));\ +SetNZ (target); +*/ + +/* BCD all totally untested (MAD) */ + +#define DoNBCD(target, source) \ +{ register uint32 lo = (target & 0xF) + GetX();\ + register uint32 hi = (target & 0xF0);\ + if (lo>10) {lo=20-lo; hi+=0x20;}\ + else if (lo>0) {lo=10-lo; hi+=0x10;}\ + if (hi>0xa0) {hi=0x140-hi; ForceX(1); ForceC(1);}\ + else if (hi>0) {hi=0xa0-hi; ForceX(1); ForceC(1);}\ + else {ForceC(0); ForceX(0);}\ + target=hi+lo;\ + if (target!=0) ForceZ(0);\ +}; + +#define DoABCD(target, source) \ + { register int32 tgt; \ + tgt = (source & 0xF) + (target & 0xF) + GetX(); \ + if(tgt >= 0xA) \ + tgt += 0x6; \ + tgt += (source & 0xF0) + (target & 0xF0); \ + if(tgt >= 0xA0) \ + tgt += 0x60; \ + SetXC (tgt & 0xFF00); \ + tgt &= 0xFF; \ + SetZ(tgt == 0); \ + target = tgt; \ + }; + +#define DoSBCD(target, source) \ + { register int32 tgt, hi; \ + tgt = (target & 0xF) - (source & 0xF) - GetX(); \ + hi = (target & 0xF0) - (source & 0xF0); \ + if(tgt < 0) { \ + tgt += 10; \ + hi -= 0x10; \ + } \ + if(hi < 0) { \ + hi -= 0x60; \ + } \ + tgt += hi; \ + SetXC (tgt & 0xFF00); \ + tgt &= 0xFF; \ + SetZ(tgt == 0); \ + target = tgt; \ + }; + +#endif + +Oper (Opc0c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 0, GRL, SRL, 72) +Oper (Opc0d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 0, GRL, SRL, 76) +Oper (Opc0d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 0, GRL, SRL, 76) +Oper (Opc0e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 76) +Oper (Opc0e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 80) +Oper (Opc0f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 0, GRL, SRL, 80) +Oper (Opc0f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc1c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 0, GRL, SRL, 72) +Oper (Opc1d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 0, GRL, SRL, 76) +Oper (Opc1d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 0, GRL, SRL, 76) +Oper (Opc1e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 76) +Oper (Opc1e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 80) +Oper (Opc1f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 0, GRL, SRL, 80) +Oper (Opc1f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc2c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 1, GRL, SRL, 72) +Oper (Opc2d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 1, GRL, SRL, 76) +Oper (Opc2d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 1, GRL, SRL, 76) +Oper (Opc2e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 76) +Oper (Opc2e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 80) +Oper (Opc2f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 1, GRL, SRL, 80) +Oper (Opc2f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc3c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 1, GRL, SRL, 72) +Oper (Opc3d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 1, GRL, SRL, 76) +Oper (Opc3d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 1, GRL, SRL, 76) +Oper (Opc3e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 76) +Oper (Opc3e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 80) +Oper (Opc3f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 1, GRL, SRL, 80) +Oper (Opc3f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc4c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 2, GRL, SRL, 72) +Oper (Opc4d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 2, GRL, SRL, 76) +Oper (Opc4d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 2, GRL, SRL, 76) +Oper (Opc4e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 76) +Oper (Opc4e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 80) +Oper (Opc4f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 2, GRL, SRL, 80) +Oper (Opc4f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc5c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 2, GRL, SRL, 72) +Oper (Opc5d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 2, GRL, SRL, 76) +Oper (Opc5d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 2, GRL, SRL, 76) +Oper (Opc5e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 76) +Oper (Opc5e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 80) +Oper (Opc5f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 2, GRL, SRL, 80) +Oper (Opc5f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc6c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 3, GRL, SRL, 72) +Oper (Opc6d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 3, GRL, SRL, 76) +Oper (Opc6d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 3, GRL, SRL, 76) +Oper (Opc6e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 76) +Oper (Opc6e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 80) +Oper (Opc6f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 3, GRL, SRL, 80) +Oper (Opc6f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc7c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 3, GRL, SRL, 72) +Oper (Opc7d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 3, GRL, SRL, 76) +Oper (Opc7d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 3, GRL, SRL, 76) +Oper (Opc7e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 76) +Oper (Opc7e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 80) +Oper (Opc7f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 3, GRL, SRL, 80) +Oper (Opc7f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc8c0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 4, GRL, SRL, 72) +Oper (Opc8d0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 4, GRL, SRL, 76) +Oper (Opc8d8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 4, GRL, SRL, 76) +Oper (Opc8e0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 76) +Oper (Opc8e8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 80) +Oper (Opc8f0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 4, GRL, SRL, 80) +Oper (Opc8f8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opc9c0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 4, GRL, SRL, 72) +Oper (Opc9d0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 4, GRL, SRL, 76) +Oper (Opc9d8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 4, GRL, SRL, 76) +Oper (Opc9e0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 76) +Oper (Opc9e8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 80) +Oper (Opc9f0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 4, GRL, SRL, 80) +Oper (Opc9f8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opcac0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 5, GRL, SRL, 72) +Oper (Opcad0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 5, GRL, SRL, 76) +Oper (Opcad8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 5, GRL, SRL, 76) +Oper (Opcae0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 76) +Oper (Opcae8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 80) +Oper (Opcaf0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 5, GRL, SRL, 80) +Oper (Opcaf8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opcbc0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 5, GRL, SRL, 72) +Oper (Opcbd0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 5, GRL, SRL, 76) +Oper (Opcbd8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 5, GRL, SRL, 76) +Oper (Opcbe0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 76) +Oper (Opcbe8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 80) +Oper (Opcbf0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 5, GRL, SRL, 80) +Oper (Opcbf8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opccc0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 6, GRL, SRL, 72) +Oper (Opccd0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 6, GRL, SRL, 76) +Oper (Opccd8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 6, GRL, SRL, 76) +Oper (Opcce0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 76) +Oper (Opcce8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 80) +Oper (Opccf0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 6, GRL, SRL, 80) +Oper (Opccf8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opcdc0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 6, GRL, SRL, 72) +Oper (Opcdd0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 6, GRL, SRL, 76) +Oper (Opcdd8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 6, GRL, SRL, 76) +Oper (Opcde0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 76) +Oper (Opcde8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 80) +Oper (Opcdf0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 6, GRL, SRL, 80) +Oper (Opcdf8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opcec0, DoMulu, DW, SdW, ins7, DL, DR, Cd, 7, GRL, SRL, 72) +Oper (Opced0, DoMulu, DW, SainW, ins7, DL, DR, Cd, 7, GRL, SRL, 76) +Oper (Opced8, DoMulu, DW, SaipW, ins7, DL, DR, Cd, 7, GRL, SRL, 76) +Oper (Opcee0, DoMulu, DW, SmaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 76) +Oper (Opcee8, DoMulu, DW, SdaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 80) +Oper (Opcef0, DoMulu, DW, SaixW, ins7, DL, DR, Cd, 7, GRL, SRL, 80) +Oper (Opcef8, DoMulu, DW, SearW, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opcfc0, DoMuls, DW, SdW, ins7, DL, DR, Cd, 7, GRL, SRL, 72) +Oper (Opcfd0, DoMuls, DW, SainW, ins7, DL, DR, Cd, 7, GRL, SRL, 76) +Oper (Opcfd8, DoMuls, DW, SaipW, ins7, DL, DR, Cd, 7, GRL, SRL, 76) +Oper (Opcfe0, DoMuls, DW, SmaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 76) +Oper (Opcfe8, DoMuls, DW, SdaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 80) +Oper (Opcff0, DoMuls, DW, SaixW, ins7, DL, DR, Cd, 7, GRL, SRL, 80) +Oper (Opcff8, DoMuls, DW, SearW, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+77)&0xfffffffc) + +Oper (Opb000, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SN, 4) +Oper (Opb010, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SN, 8) +Oper (Opb018, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SN, 8) +Oper (Opb020, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SN, 12) +Oper (Opb028, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SN, 12) +Oper (Opb030, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SN, 16) +Oper (Opb038, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opb040, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SN, 4) +Oper (Opb048, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 0, GRW, SN, 4) +Oper (Opb050, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SN, 8) +Oper (Opb058, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SN, 8) +Oper (Opb060, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SN, 12) +Oper (Opb068, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SN, 12) +Oper (Opb070, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SN, 16) +Oper (Opb078, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opb080, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SN, 8) +Oper (Opb088, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 0, GRL, SN, 8) +Oper (Opb090, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SN, 16) +Oper (Opb098, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SN, 16) +Oper (Opb0a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SN, 16) +Oper (Opb0a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SN, 20) +Oper (Opb0b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SN, 20) +Oper (Opb0b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opb0c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 0, GRL, SN, 8) +Oper (Opb0c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 0, GRL, SN, 8) +Oper (Opb0d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 0, GRL, SN, 12) +Oper (Opb0d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 0, GRL, SN, 12) +Oper (Opb0e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 0, GRL, SN, 12) +Oper (Opb0e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 0, GRL, SN, 16) +Oper (Opb0f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 0, GRL, SN, 16) +Oper (Opb0f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 0, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opb108, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 0, GMB, SN, 12) +Oper (Opb148, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 0, GMW, SN, 12) +Oper (Opb188, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 0, GML, SN, 20) +Oper (Opb1c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 0, GRL, SN, 8) +Oper (Opb1c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 0, GRL, SN, 8) +Oper (Opb1d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 0, GRL, SN, 16) +Oper (Opb1d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 0, GRL, SN, 16) +Oper (Opb1e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 0, GRL, SN, 16) +Oper (Opb1e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 0, GRL, SN, 20) +Oper (Opb1f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 0, GRL, SN, 20) +Oper (Opb1f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 0, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Opb200, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SN, 4) +Oper (Opb210, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SN, 8) +Oper (Opb218, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SN, 8) +Oper (Opb220, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SN, 12) +Oper (Opb228, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SN, 12) +Oper (Opb230, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SN, 16) +Oper (Opb238, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opb240, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SN, 4) +Oper (Opb248, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 1, GRW, SN, 4) +Oper (Opb250, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SN, 8) +Oper (Opb258, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SN, 8) +Oper (Opb260, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SN, 12) +Oper (Opb268, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SN, 12) +Oper (Opb270, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SN, 16) +Oper (Opb278, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opb280, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SN, 8) +Oper (Opb288, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 1, GRL, SN, 8) +Oper (Opb290, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SN, 16) +Oper (Opb298, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SN, 16) +Oper (Opb2a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SN, 16) +Oper (Opb2a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SN, 20) +Oper (Opb2b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SN, 20) +Oper (Opb2b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opb2c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 1, GRL, SN, 8) +Oper (Opb2c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 1, GRL, SN, 8) +Oper (Opb2d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 1, GRL, SN, 12) +Oper (Opb2d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 1, GRL, SN, 12) +Oper (Opb2e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 1, GRL, SN, 12) +Oper (Opb2e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 1, GRL, SN, 16) +Oper (Opb2f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 1, GRL, SN, 16) +Oper (Opb2f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 1, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opb308, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 1, GMB, SN, 12) +Oper (Opb348, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 1, GMW, SN, 12) +Oper (Opb388, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 1, GML, SN, 20) +Oper (Opb3c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 1, GRL, SN, 8) +Oper (Opb3c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 1, GRL, SN, 8) +Oper (Opb3d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 1, GRL, SN, 16) +Oper (Opb3d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 1, GRL, SN, 16) +Oper (Opb3e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 1, GRL, SN, 16) +Oper (Opb3e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 1, GRL, SN, 20) +Oper (Opb3f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 1, GRL, SN, 20) +Oper (Opb3f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 1, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Opb400, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SN, 4) +Oper (Opb410, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SN, 8) +Oper (Opb418, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SN, 8) +Oper (Opb420, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SN, 12) +Oper (Opb428, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SN, 12) +Oper (Opb430, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SN, 16) +Oper (Opb438, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opb440, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SN, 4) +Oper (Opb448, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 2, GRW, SN, 4) +Oper (Opb450, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SN, 8) +Oper (Opb458, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SN, 8) +Oper (Opb460, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SN, 12) +Oper (Opb468, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SN, 12) +Oper (Opb470, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SN, 16) +Oper (Opb478, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opb480, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SN, 8) +Oper (Opb488, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 2, GRL, SN, 8) +Oper (Opb490, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SN, 16) +Oper (Opb498, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SN, 16) +Oper (Opb4a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SN, 16) +Oper (Opb4a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SN, 20) +Oper (Opb4b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SN, 20) +Oper (Opb4b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opb4c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 2, GRL, SN, 8) +Oper (Opb4c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 2, GRL, SN, 8) +Oper (Opb4d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 2, GRL, SN, 12) +Oper (Opb4d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 2, GRL, SN, 12) +Oper (Opb4e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 2, GRL, SN, 12) +Oper (Opb4e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 2, GRL, SN, 16) +Oper (Opb4f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 2, GRL, SN, 16) +Oper (Opb4f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 2, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opb508, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 2, GMB, SN, 12) +Oper (Opb548, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 2, GMW, SN, 12) +Oper (Opb588, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 2, GML, SN, 20) +Oper (Opb5c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 2, GRL, SN, 8) +Oper (Opb5c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 2, GRL, SN, 8) +Oper (Opb5d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 2, GRL, SN, 16) +Oper (Opb5d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 2, GRL, SN, 16) +Oper (Opb5e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 2, GRL, SN, 16) +Oper (Opb5e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 2, GRL, SN, 20) +Oper (Opb5f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 2, GRL, SN, 20) +Oper (Opb5f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 2, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Opb600, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SN, 4) +Oper (Opb610, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SN, 8) +Oper (Opb618, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SN, 8) +Oper (Opb620, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SN, 12) +Oper (Opb628, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SN, 12) +Oper (Opb630, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SN, 16) +Oper (Opb638, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opb640, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SN, 4) +Oper (Opb648, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 3, GRW, SN, 4) +Oper (Opb650, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SN, 8) +Oper (Opb658, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SN, 8) +Oper (Opb660, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SN, 12) +Oper (Opb668, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SN, 12) +Oper (Opb670, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SN, 16) +Oper (Opb678, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opb680, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SN, 8) +Oper (Opb688, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 3, GRL, SN, 8) +Oper (Opb690, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SN, 16) +Oper (Opb698, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SN, 16) +Oper (Opb6a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SN, 16) +Oper (Opb6a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SN, 20) +Oper (Opb6b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SN, 20) +Oper (Opb6b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opb6c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 3, GRL, SN, 8) +Oper (Opb6c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 3, GRL, SN, 8) +Oper (Opb6d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 3, GRL, SN, 12) +Oper (Opb6d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 3, GRL, SN, 12) +Oper (Opb6e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 3, GRL, SN, 12) +Oper (Opb6e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 3, GRL, SN, 16) +Oper (Opb6f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 3, GRL, SN, 16) +Oper (Opb6f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 3, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opb708, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 3, GMB, SN, 12) +Oper (Opb748, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 3, GMW, SN, 12) +Oper (Opb788, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 3, GML, SN, 20) +Oper (Opb7c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 3, GRL, SN, 8) +Oper (Opb7c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 3, GRL, SN, 8) +Oper (Opb7d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 3, GRL, SN, 16) +Oper (Opb7d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 3, GRL, SN, 16) +Oper (Opb7e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 3, GRL, SN, 16) +Oper (Opb7e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 3, GRL, SN, 20) +Oper (Opb7f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 3, GRL, SN, 20) +Oper (Opb7f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 3, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Opb800, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SN, 4) +Oper (Opb810, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SN, 8) +Oper (Opb818, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SN, 8) +Oper (Opb820, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SN, 12) +Oper (Opb828, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SN, 12) +Oper (Opb830, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SN, 16) +Oper (Opb838, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opb840, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SN, 4) +Oper (Opb848, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 4, GRW, SN, 4) +Oper (Opb850, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SN, 8) +Oper (Opb858, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SN, 8) +Oper (Opb860, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SN, 12) +Oper (Opb868, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SN, 12) +Oper (Opb870, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SN, 16) +Oper (Opb878, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opb880, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SN, 8) +Oper (Opb888, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 4, GRL, SN, 8) +Oper (Opb890, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SN, 16) +Oper (Opb898, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SN, 16) +Oper (Opb8a0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SN, 16) +Oper (Opb8a8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SN, 20) +Oper (Opb8b0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SN, 20) +Oper (Opb8b8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opb8c0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 4, GRL, SN, 8) +Oper (Opb8c8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 4, GRL, SN, 8) +Oper (Opb8d0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 4, GRL, SN, 12) +Oper (Opb8d8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 4, GRL, SN, 12) +Oper (Opb8e0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 4, GRL, SN, 12) +Oper (Opb8e8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 4, GRL, SN, 16) +Oper (Opb8f0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 4, GRL, SN, 16) +Oper (Opb8f8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 4, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opb908, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 4, GMB, SN, 12) +Oper (Opb948, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 4, GMW, SN, 12) +Oper (Opb988, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 4, GML, SN, 20) +Oper (Opb9c0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 4, GRL, SN, 8) +Oper (Opb9c8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 4, GRL, SN, 8) +Oper (Opb9d0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 4, GRL, SN, 16) +Oper (Opb9d8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 4, GRL, SN, 16) +Oper (Opb9e0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 4, GRL, SN, 16) +Oper (Opb9e8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 4, GRL, SN, 20) +Oper (Opb9f0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 4, GRL, SN, 20) +Oper (Opb9f8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 4, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Opba00, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SN, 4) +Oper (Opba10, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SN, 8) +Oper (Opba18, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SN, 8) +Oper (Opba20, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SN, 12) +Oper (Opba28, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SN, 12) +Oper (Opba30, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SN, 16) +Oper (Opba38, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opba40, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SN, 4) +Oper (Opba48, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 5, GRW, SN, 4) +Oper (Opba50, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SN, 8) +Oper (Opba58, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SN, 8) +Oper (Opba60, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SN, 12) +Oper (Opba68, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SN, 12) +Oper (Opba70, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SN, 16) +Oper (Opba78, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opba80, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SN, 8) +Oper (Opba88, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 5, GRL, SN, 8) +Oper (Opba90, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SN, 16) +Oper (Opba98, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SN, 16) +Oper (Opbaa0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SN, 16) +Oper (Opbaa8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SN, 20) +Oper (Opbab0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SN, 20) +Oper (Opbab8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opbac0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 5, GRL, SN, 8) +Oper (Opbac8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 5, GRL, SN, 8) +Oper (Opbad0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 5, GRL, SN, 12) +Oper (Opbad8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 5, GRL, SN, 12) +Oper (Opbae0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 5, GRL, SN, 12) +Oper (Opbae8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 5, GRL, SN, 16) +Oper (Opbaf0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 5, GRL, SN, 16) +Oper (Opbaf8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 5, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opbb08, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 5, GMB, SN, 12) +Oper (Opbb48, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 5, GMW, SN, 12) +Oper (Opbb88, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 5, GML, SN, 20) +Oper (Opbbc0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 5, GRL, SN, 8) +Oper (Opbbc8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 5, GRL, SN, 8) +Oper (Opbbd0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 5, GRL, SN, 16) +Oper (Opbbd8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 5, GRL, SN, 16) +Oper (Opbbe0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 5, GRL, SN, 16) +Oper (Opbbe8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 5, GRL, SN, 20) +Oper (Opbbf0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 5, GRL, SN, 20) +Oper (Opbbf8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 5, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Opbc00, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SN, 4) +Oper (Opbc10, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SN, 8) +Oper (Opbc18, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SN, 8) +Oper (Opbc20, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SN, 12) +Oper (Opbc28, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SN, 12) +Oper (Opbc30, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SN, 16) +Oper (Opbc38, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opbc40, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SN, 4) +Oper (Opbc48, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 6, GRW, SN, 4) +Oper (Opbc50, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SN, 8) +Oper (Opbc58, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SN, 8) +Oper (Opbc60, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SN, 12) +Oper (Opbc68, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SN, 12) +Oper (Opbc70, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SN, 16) +Oper (Opbc78, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opbc80, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SN, 8) +Oper (Opbc88, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 6, GRL, SN, 8) +Oper (Opbc90, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SN, 16) +Oper (Opbc98, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SN, 16) +Oper (Opbca0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SN, 16) +Oper (Opbca8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SN, 20) +Oper (Opbcb0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SN, 20) +Oper (Opbcb8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opbcc0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 6, GRL, SN, 8) +Oper (Opbcc8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 6, GRL, SN, 8) +Oper (Opbcd0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 6, GRL, SN, 12) +Oper (Opbcd8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 6, GRL, SN, 12) +Oper (Opbce0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 6, GRL, SN, 12) +Oper (Opbce8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 6, GRL, SN, 16) +Oper (Opbcf0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 6, GRL, SN, 16) +Oper (Opbcf8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 6, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opbd08, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB, 6, GMB, SN, 12) +Oper (Opbd48, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 6, GMW, SN, 12) +Oper (Opbd88, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 6, GML, SN, 20) +Oper (Opbdc0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 6, GRL, SN, 8) +Oper (Opbdc8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 6, GRL, SN, 8) +Oper (Opbdd0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 6, GRL, SN, 16) +Oper (Opbdd8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 6, GRL, SN, 16) +Oper (Opbde0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 6, GRL, SN, 16) +Oper (Opbde8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 6, GRL, SN, 20) +Oper (Opbdf0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 6, GRL, SN, 20) +Oper (Opbdf8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 6, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Opbe00, DoCmpB, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SN, 4) +Oper (Opbe10, DoCmpB, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SN, 8) +Oper (Opbe18, DoCmpB, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SN, 8) +Oper (Opbe20, DoCmpB, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SN, 12) +Oper (Opbe28, DoCmpB, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SN, 12) +Oper (Opbe30, DoCmpB, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SN, 16) +Oper (Opbe38, DoCmpB, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SN, (cycles+11)&0xfffffffc) +Oper (Opbe40, DoCmpW, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SN, 4) +Oper (Opbe48, DoCmpW, DW, SaW, ins7, DW, DR, Cd, 7, GRW, SN, 4) +Oper (Opbe50, DoCmpW, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SN, 8) +Oper (Opbe58, DoCmpW, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SN, 8) +Oper (Opbe60, DoCmpW, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SN, 12) +Oper (Opbe68, DoCmpW, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SN, 12) +Oper (Opbe70, DoCmpW, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SN, 16) +Oper (Opbe78, DoCmpW, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SN, (cycles+11)&0xfffffffc) +Oper (Opbe80, DoCmpL, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SN, 8) +Oper (Opbe88, DoCmpL, DL, SaL, ins7, DL, DR, Cd, 7, GRL, SN, 8) +Oper (Opbe90, DoCmpL, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SN, 16) +Oper (Opbe98, DoCmpL, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SN, 16) +Oper (Opbea0, DoCmpL, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SN, 16) +Oper (Opbea8, DoCmpL, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SN, 20) +Oper (Opbeb0, DoCmpL, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SN, 20) +Oper (Opbeb8, DoCmpL, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SN, (cycles+17)&0xfffffffc) +Oper (Opbec0, DoCmpa, DL, SdW, ins7, DL, DR, Ca, 7, GRL, SN, 8) +Oper (Opbec8, DoCmpa, DL, SaW, ins7, DL, DR, Ca, 7, GRL, SN, 8) +Oper (Opbed0, DoCmpa, DL, SainW, ins7, DL, DR, Ca, 7, GRL, SN, 12) +Oper (Opbed8, DoCmpa, DL, SaipW, ins7, DL, DR, Ca, 7, GRL, SN, 12) +Oper (Opbee0, DoCmpa, DL, SmaiW, ins7, DL, DR, Ca, 7, GRL, SN, 12) +Oper (Opbee8, DoCmpa, DL, SdaiW, ins7, DL, DR, Ca, 7, GRL, SN, 16) +Oper (Opbef0, DoCmpa, DL, SaixW, ins7, DL, DR, Ca, 7, GRL, SN, 16) +Oper (Opbef8, DoCmpa, DL, SearW, ins7, DL, DR, Ca, 7, GRL, SN, (cycles+13)&0xfffffffc) + +Oper (Opbf08, DoCmpm, DB, SaipB, ins7, DB, DA, CaipB15, 7, GMB, SN, 12) +Oper (Opbf48, DoCmpm, DW, SaipW, ins7, DW, DA, CaipW, 7, GMW, SN, 12) +Oper (Opbf88, DoCmpm, DL, SaipL, ins7, DL, DA, CaipL, 7, GML, SN, 20) +Oper (Opbfc0, DoCmpa, DL, SdL, ins7, DL, DR, Ca, 7, GRL, SN, 8) +Oper (Opbfc8, DoCmpa, DL, SaL, ins7, DL, DR, Ca, 7, GRL, SN, 8) +Oper (Opbfd0, DoCmpa, DL, SainL, ins7, DL, DR, Ca, 7, GRL, SN, 16) +Oper (Opbfd8, DoCmpa, DL, SaipL, ins7, DL, DR, Ca, 7, GRL, SN, 16) +Oper (Opbfe0, DoCmpa, DL, SmaiL, ins7, DL, DR, Ca, 7, GRL, SN, 16) +Oper (Opbfe8, DoCmpa, DL, SdaiL, ins7, DL, DR, Ca, 7, GRL, SN, 20) +Oper (Opbff0, DoCmpa, DL, SaixL, ins7, DL, DR, Ca, 7, GRL, SN, 20) +Oper (Opbff8, DoCmpa, DL, SearL, ins7, DL, DR, Ca, 7, GRL, SN, (cycles+17)&0xfffffffc) + +Oper (Op80c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 0, GRL, SRL, 140) +Oper (Op80d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 0, GRL, SRL, 144) +Oper (Op80d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 0, GRL, SRL, 144) +Oper (Op80e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 148) +Oper (Op80e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 148) +Oper (Op80f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 0, GRL, SRL, 152) +Oper (Op80f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op81c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 0, GRL, SRL, 160) +Oper (Op81d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 0, GRL, SRL, 164) +Oper (Op81d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 0, GRL, SRL, 164) +Oper (Op81e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 164) +Oper (Op81e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 0, GRL, SRL, 168) +Oper (Op81f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 0, GRL, SRL, 168) +Oper (Op81f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op82c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 1, GRL, SRL, 140) +Oper (Op82d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 1, GRL, SRL, 144) +Oper (Op82d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 1, GRL, SRL, 144) +Oper (Op82e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 148) +Oper (Op82e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 148) +Oper (Op82f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 1, GRL, SRL, 152) +Oper (Op82f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op83c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 1, GRL, SRL, 160) +Oper (Op83d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 1, GRL, SRL, 164) +Oper (Op83d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 1, GRL, SRL, 164) +Oper (Op83e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 164) +Oper (Op83e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 1, GRL, SRL, 168) +Oper (Op83f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 1, GRL, SRL, 168) +Oper (Op83f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op84c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 2, GRL, SRL, 140) +Oper (Op84d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 2, GRL, SRL, 144) +Oper (Op84d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 2, GRL, SRL, 144) +Oper (Op84e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 148) +Oper (Op84e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 148) +Oper (Op84f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 2, GRL, SRL, 152) +Oper (Op84f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op85c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 2, GRL, SRL, 160) +Oper (Op85d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 2, GRL, SRL, 164) +Oper (Op85d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 2, GRL, SRL, 164) +Oper (Op85e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 164) +Oper (Op85e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 2, GRL, SRL, 168) +Oper (Op85f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 2, GRL, SRL, 168) +Oper (Op85f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op86c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 3, GRL, SRL, 140) +Oper (Op86d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 3, GRL, SRL, 144) +Oper (Op86d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 3, GRL, SRL, 144) +Oper (Op86e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 148) +Oper (Op86e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 148) +Oper (Op86f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 3, GRL, SRL, 152) +Oper (Op86f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op87c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 3, GRL, SRL, 160) +Oper (Op87d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 3, GRL, SRL, 164) +Oper (Op87d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 3, GRL, SRL, 164) +Oper (Op87e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 164) +Oper (Op87e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 3, GRL, SRL, 168) +Oper (Op87f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 3, GRL, SRL, 168) +Oper (Op87f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op88c0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 4, GRL, SRL, 140) +Oper (Op88d0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 4, GRL, SRL, 144) +Oper (Op88d8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 4, GRL, SRL, 144) +Oper (Op88e0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 148) +Oper (Op88e8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 148) +Oper (Op88f0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 4, GRL, SRL, 152) +Oper (Op88f8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op89c0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 4, GRL, SRL, 160) +Oper (Op89d0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 4, GRL, SRL, 164) +Oper (Op89d8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 4, GRL, SRL, 164) +Oper (Op89e0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 164) +Oper (Op89e8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 4, GRL, SRL, 168) +Oper (Op89f0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 4, GRL, SRL, 168) +Oper (Op89f8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op8ac0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 5, GRL, SRL, 140) +Oper (Op8ad0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 5, GRL, SRL, 144) +Oper (Op8ad8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 5, GRL, SRL, 144) +Oper (Op8ae0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 148) +Oper (Op8ae8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 148) +Oper (Op8af0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 5, GRL, SRL, 152) +Oper (Op8af8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op8bc0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 5, GRL, SRL, 160) +Oper (Op8bd0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 5, GRL, SRL, 164) +Oper (Op8bd8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 5, GRL, SRL, 164) +Oper (Op8be0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 164) +Oper (Op8be8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 5, GRL, SRL, 168) +Oper (Op8bf0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 5, GRL, SRL, 168) +Oper (Op8bf8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op8cc0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 6, GRL, SRL, 140) +Oper (Op8cd0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 6, GRL, SRL, 144) +Oper (Op8cd8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 6, GRL, SRL, 144) +Oper (Op8ce0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 148) +Oper (Op8ce8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 148) +Oper (Op8cf0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 6, GRL, SRL, 152) +Oper (Op8cf8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op8dc0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 6, GRL, SRL, 160) +Oper (Op8dd0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 6, GRL, SRL, 164) +Oper (Op8dd8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 6, GRL, SRL, 164) +Oper (Op8de0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 164) +Oper (Op8de8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 6, GRL, SRL, 168) +Oper (Op8df0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 6, GRL, SRL, 168) +Oper (Op8df8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op8ec0, DoDivu, DW, SdW, ins7, DL, DR, Cd, 7, GRL, SRL, 140) +Oper (Op8ed0, DoDivu, DW, SainW, ins7, DL, DR, Cd, 7, GRL, SRL, 144) +Oper (Op8ed8, DoDivu, DW, SaipW, ins7, DL, DR, Cd, 7, GRL, SRL, 144) +Oper (Op8ee0, DoDivu, DW, SmaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 148) +Oper (Op8ee8, DoDivu, DW, SdaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 148) +Oper (Op8ef0, DoDivu, DW, SaixW, ins7, DL, DR, Cd, 7, GRL, SRL, 152) +Oper (Op8ef8, DoDivu, DW, SearW, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+147)&0xfffffffc) + +Oper (Op8fc0, DoDivs, DW, SdW, ins7, DL, DR, Cd, 7, GRL, SRL, 160) +Oper (Op8fd0, DoDivs, DW, SainW, ins7, DL, DR, Cd, 7, GRL, SRL, 164) +Oper (Op8fd8, DoDivs, DW, SaipW, ins7, DL, DR, Cd, 7, GRL, SRL, 164) +Oper (Op8fe0, DoDivs, DW, SmaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 164) +Oper (Op8fe8, DoDivs, DW, SdaiW, ins7, DL, DR, Cd, 7, GRL, SRL, 168) +Oper (Op8ff0, DoDivs, DW, SaixW, ins7, DL, DR, Cd, 7, GRL, SRL, 168) +Oper (Op8ff8, DoDivs, DW, SearW, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+165)&0xfffffffc) + +Oper (Op0c00, DoCmpB, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SN, 8) +Oper (Op0c10, DoCmpB, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SN, 12) +Oper (Op0c18, DoCmpB, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SN, 12) +Oper (Op0c20, DoCmpB, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SN, 16) +Oper (Op0c28, DoCmpB, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SN, 16) +Oper (Op0c30, DoCmpB, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SN, 20) +Oper (Op0c38, DoCmpB, DB, SimmB, 0, DB, DA, Ceaw, ins7, GMB, SN, (cycles+19)&0xfffffffc) +Oper (Op0c40, DoCmpW, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SN, 8) +Oper (Op0c50, DoCmpW, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SN, 12) +Oper (Op0c58, DoCmpW, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SN, 12) +Oper (Op0c60, DoCmpW, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SN, 16) +Oper (Op0c68, DoCmpW, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SN, 16) +Oper (Op0c70, DoCmpW, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SN, 20) +Oper (Op0c78, DoCmpW, DW, SimmW, 0, DW, DA, Ceaw, ins7, GMW, SN, (cycles+19)&0xfffffffc) +Oper (Op0c80, DoCmpL, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SN, 16) +Oper (Op0c90, DoCmpL, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SN, 20) +Oper (Op0c98, DoCmpL, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SN, 20) +Oper (Op0ca0, DoCmpL, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SN, 24) +Oper (Op0ca8, DoCmpL, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SN, 24) +Oper (Op0cb0, DoCmpL, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SN, 28) +Oper (Op0cb8, DoCmpL, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SN, (cycles+27)&0xfffffffc) + +Oper (Opc100, DoABCD, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Opc108, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 0, GMB, SMB, 20) +Oper (Opc300, DoABCD, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Opc308, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 1, GMB, SMB, 20) +Oper (Opc500, DoABCD, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Opc508, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 2, GMB, SMB, 20) +Oper (Opc700, DoABCD, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Opc708, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 3, GMB, SMB, 20) +Oper (Opc900, DoABCD, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Opc908, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 4, GMB, SMB, 20) +Oper (Opcb00, DoABCD, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Opcb08, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 5, GMB, SMB, 20) +Oper (Opcd00, DoABCD, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Opcd08, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 6, GMB, SMB, 20) +Oper (Opcf00, DoABCD, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Opcf08, DoABCD, DB, SmaiB, ins7, DB, DA, CmaiB, 7, GMB, SMB, 20) + +Oper (Op8100, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Op8108, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 0, GMB, SMB, 20) +Oper (Op8300, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Op8308, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 1, GMB, SMB, 20) +Oper (Op8500, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Op8508, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 2, GMB, SMB, 20) +Oper (Op8700, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Op8708, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 3, GMB, SMB, 20) +Oper (Op8900, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Op8908, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 4, GMB, SMB, 20) +Oper (Op8b00, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Op8b08, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 5, GMB, SMB, 20) +Oper (Op8d00, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Op8d08, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 6, GMB, SMB, 20) +Oper (Op8f00, DoSBCD, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Op8f08, DoSBCD, DB, SmaiB, ins7, DB, DA, CmaiB, 7, GMB, SMB, 20) + +Oper (Op4800, DoNBCD, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SRB, 8) +Oper (Op4810, DoNBCD, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op4818, DoNBCD, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op4820, DoNBCD, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op4828, DoNBCD, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op4830, DoNBCD, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op4838, DoNBCD, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) diff --git a/MCUME_esp32/espcastaway/main/68korigbad/op68klogop.cpp b/MCUME_esp32/espcastaway/main/68korigbad/op68klogop.cpp new file mode 100755 index 0000000..2f1e62f --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/op68klogop.cpp @@ -0,0 +1,974 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - 68k logical instructions +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 10.07.2002 JH Minor clarification when CCR/SR is target (without effect) +* 27.08.2002 JH ... with effect! Fixed bug. Restructured & clarified. +*/ +#ifndef PROTOH +static char sccsid[] = "$Id: op68klogop.c,v 1.3 2002/08/27 01:21:11 jhoenig Exp $"; +#include "68000.h" +#include "op68k.h" +#include "operin.h" + +/* +* Opfuncs. +*/ +#define OlogSR(Code, Op, OpSR, Priv, DeclS, Get1, DeclT, Get2, Set2, GetSR, SetSR, retval)\ + unsigned long Code(operin)\ +{\ + register unsigned long cycles=0;\ + DeclS(source)\ + DeclT(target)\ + long address;\ + switch ins7 {\ + case 0x0:\ + Get1(source, 0)\ + address = GetMPCW();\ + pc += 2;\ + Get2(address, target)\ + Op(target, source)\ + Set2(address, target)\ + break;\ + case 0x1:\ + Get1(source, 0)\ + address = GetMPCL();\ + pc += 4;\ + Get2(address, target)\ + Op(target, source)\ + Set2(address, target)\ + break;\ + case 0x4:\ + if (Priv && !GetS()) { ExceptionGroup1(PRIV); };\ + Get1(source, 0)\ + GetSR(address2, target)\ + OpSR(target, source)\ + SetSR(address2, target)\ + break;\ + default:\ + ExceptionGroup1(ILLINSTR);\ + break;\ +}\ + return retval;\ +} + +#define DoAnd(target,source) target &= source; ClrCVSetNZ(target); +#define DoAndSR(target,source) target &= source; + +#define DoEor(target,source) target ^= source; ClrCVSetNZ(target); +#define DoEorSR(target,source) target ^= source; + +#define DoOr(target,source) target |= source; ClrCVSetNZ(target); +#define DoOrSR(target,source) target |= source; + +#else + +#define OlogSR(a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12) \ +extern unsigned long a1(operin); + +#endif + +Oper (Opc000, DoAnd, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4) +Oper (Opc010, DoAnd, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Opc018, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Opc020, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Opc028, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Opc030, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SRB, 16) +Oper (Opc038, DoAnd, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opc040, DoAnd, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Opc050, DoAnd, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Opc058, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Opc060, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Opc068, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Opc070, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SRW, 16) +Oper (Opc078, DoAnd, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opc080, DoAnd, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Opc090, DoAnd, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Opc098, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Opc0a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Opc0a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Opc0b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Opc0b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opc110, DoAnd, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opc118, DoAnd, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opc120, DoAnd, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opc128, DoAnd, DB, SdB, 0, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opc130, DoAnd, DB, SdB, 0, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opc138, DoAnd, DB, SdB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opc150, DoAnd, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opc158, DoAnd, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opc160, DoAnd, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opc168, DoAnd, DW, SdW, 0, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opc170, DoAnd, DW, SdW, 0, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opc178, DoAnd, DW, SdW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opc190, DoAnd, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opc198, DoAnd, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opc1a0, DoAnd, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opc1a8, DoAnd, DL, SdL, 0, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opc1b0, DoAnd, DL, SdL, 0, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opc1b8, DoAnd, DL, SdL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opc200, DoAnd, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4) +Oper (Opc210, DoAnd, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Opc218, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Opc220, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Opc228, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Opc230, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SRB, 16) +Oper (Opc238, DoAnd, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opc240, DoAnd, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Opc250, DoAnd, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Opc258, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Opc260, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Opc268, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Opc270, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SRW, 16) +Oper (Opc278, DoAnd, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opc280, DoAnd, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Opc290, DoAnd, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Opc298, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Opc2a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Opc2a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Opc2b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Opc2b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opc310, DoAnd, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opc318, DoAnd, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opc320, DoAnd, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opc328, DoAnd, DB, SdB, 1, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opc330, DoAnd, DB, SdB, 1, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opc338, DoAnd, DB, SdB, 1, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opc350, DoAnd, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opc358, DoAnd, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opc360, DoAnd, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opc368, DoAnd, DW, SdW, 1, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opc370, DoAnd, DW, SdW, 1, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opc378, DoAnd, DW, SdW, 1, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opc390, DoAnd, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opc398, DoAnd, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opc3a0, DoAnd, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opc3a8, DoAnd, DL, SdL, 1, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opc3b0, DoAnd, DL, SdL, 1, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opc3b8, DoAnd, DL, SdL, 1, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opc400, DoAnd, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4) +Oper (Opc410, DoAnd, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Opc418, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Opc420, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Opc428, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Opc430, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SRB, 16) +Oper (Opc438, DoAnd, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opc440, DoAnd, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Opc450, DoAnd, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Opc458, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Opc460, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Opc468, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Opc470, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SRW, 16) +Oper (Opc478, DoAnd, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opc480, DoAnd, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Opc490, DoAnd, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Opc498, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Opc4a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Opc4a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Opc4b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Opc4b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opc510, DoAnd, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opc518, DoAnd, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opc520, DoAnd, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opc528, DoAnd, DB, SdB, 2, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opc530, DoAnd, DB, SdB, 2, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opc538, DoAnd, DB, SdB, 2, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opc550, DoAnd, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opc558, DoAnd, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opc560, DoAnd, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opc568, DoAnd, DW, SdW, 2, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opc570, DoAnd, DW, SdW, 2, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opc578, DoAnd, DW, SdW, 2, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opc590, DoAnd, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opc598, DoAnd, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opc5a0, DoAnd, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opc5a8, DoAnd, DL, SdL, 2, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opc5b0, DoAnd, DL, SdL, 2, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opc5b8, DoAnd, DL, SdL, 2, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opc600, DoAnd, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4) +Oper (Opc610, DoAnd, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Opc618, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Opc620, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Opc628, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Opc630, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SRB, 16) +Oper (Opc638, DoAnd, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opc640, DoAnd, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Opc650, DoAnd, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Opc658, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Opc660, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Opc668, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Opc670, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SRW, 16) +Oper (Opc678, DoAnd, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opc680, DoAnd, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Opc690, DoAnd, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Opc698, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Opc6a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Opc6a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Opc6b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Opc6b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opc710, DoAnd, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opc718, DoAnd, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opc720, DoAnd, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opc728, DoAnd, DB, SdB, 3, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opc730, DoAnd, DB, SdB, 3, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opc738, DoAnd, DB, SdB, 3, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opc750, DoAnd, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opc758, DoAnd, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opc760, DoAnd, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opc768, DoAnd, DW, SdW, 3, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opc770, DoAnd, DW, SdW, 3, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opc778, DoAnd, DW, SdW, 3, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opc790, DoAnd, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opc798, DoAnd, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opc7a0, DoAnd, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opc7a8, DoAnd, DL, SdL, 3, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opc7b0, DoAnd, DL, SdL, 3, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opc7b8, DoAnd, DL, SdL, 3, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opc800, DoAnd, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4) +Oper (Opc810, DoAnd, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Opc818, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Opc820, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Opc828, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Opc830, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SRB, 16) +Oper (Opc838, DoAnd, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opc840, DoAnd, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Opc850, DoAnd, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Opc858, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Opc860, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Opc868, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Opc870, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SRW, 16) +Oper (Opc878, DoAnd, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opc880, DoAnd, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Opc890, DoAnd, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Opc898, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Opc8a0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Opc8a8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Opc8b0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Opc8b8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opc910, DoAnd, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opc918, DoAnd, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opc920, DoAnd, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opc928, DoAnd, DB, SdB, 4, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opc930, DoAnd, DB, SdB, 4, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opc938, DoAnd, DB, SdB, 4, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opc950, DoAnd, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opc958, DoAnd, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opc960, DoAnd, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opc968, DoAnd, DW, SdW, 4, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opc970, DoAnd, DW, SdW, 4, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opc978, DoAnd, DW, SdW, 4, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opc990, DoAnd, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opc998, DoAnd, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opc9a0, DoAnd, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opc9a8, DoAnd, DL, SdL, 4, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opc9b0, DoAnd, DL, SdL, 4, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opc9b8, DoAnd, DL, SdL, 4, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opca00, DoAnd, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4) +Oper (Opca10, DoAnd, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Opca18, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Opca20, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Opca28, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Opca30, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SRB, 16) +Oper (Opca38, DoAnd, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opca40, DoAnd, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Opca50, DoAnd, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Opca58, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Opca60, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Opca68, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Opca70, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SRW, 16) +Oper (Opca78, DoAnd, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opca80, DoAnd, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Opca90, DoAnd, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Opca98, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Opcaa0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Opcaa8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Opcab0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Opcab8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opcb10, DoAnd, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opcb18, DoAnd, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opcb20, DoAnd, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opcb28, DoAnd, DB, SdB, 5, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opcb30, DoAnd, DB, SdB, 5, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opcb38, DoAnd, DB, SdB, 5, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opcb50, DoAnd, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opcb58, DoAnd, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opcb60, DoAnd, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opcb68, DoAnd, DW, SdW, 5, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opcb70, DoAnd, DW, SdW, 5, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opcb78, DoAnd, DW, SdW, 5, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opcb90, DoAnd, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opcb98, DoAnd, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opcba0, DoAnd, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opcba8, DoAnd, DL, SdL, 5, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opcbb0, DoAnd, DL, SdL, 5, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opcbb8, DoAnd, DL, SdL, 5, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opcc00, DoAnd, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4) +Oper (Opcc10, DoAnd, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Opcc18, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Opcc20, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Opcc28, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Opcc30, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SRB, 16) +Oper (Opcc38, DoAnd, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opcc40, DoAnd, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Opcc50, DoAnd, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Opcc58, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Opcc60, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Opcc68, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Opcc70, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SRW, 16) +Oper (Opcc78, DoAnd, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opcc80, DoAnd, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Opcc90, DoAnd, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Opcc98, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Opcca0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Opcca8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Opccb0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Opccb8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opcd10, DoAnd, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opcd18, DoAnd, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opcd20, DoAnd, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opcd28, DoAnd, DB, SdB, 6, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opcd30, DoAnd, DB, SdB, 6, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opcd38, DoAnd, DB, SdB, 6, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opcd50, DoAnd, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opcd58, DoAnd, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opcd60, DoAnd, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opcd68, DoAnd, DW, SdW, 6, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opcd70, DoAnd, DW, SdW, 6, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opcd78, DoAnd, DW, SdW, 6, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opcd90, DoAnd, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opcd98, DoAnd, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opcda0, DoAnd, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opcda8, DoAnd, DL, SdL, 6, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opcdb0, DoAnd, DL, SdL, 6, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opcdb8, DoAnd, DL, SdL, 6, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opce00, DoAnd, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4) +Oper (Opce10, DoAnd, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Opce18, DoAnd, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Opce20, DoAnd, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Opce28, DoAnd, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Opce30, DoAnd, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SRB, 16) +Oper (Opce38, DoAnd, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Opce40, DoAnd, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Opce50, DoAnd, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Opce58, DoAnd, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Opce60, DoAnd, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Opce68, DoAnd, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Opce70, DoAnd, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SRW, 16) +Oper (Opce78, DoAnd, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Opce80, DoAnd, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Opce90, DoAnd, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Opce98, DoAnd, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Opcea0, DoAnd, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Opcea8, DoAnd, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Opceb0, DoAnd, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Opceb8, DoAnd, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Opcf10, DoAnd, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opcf18, DoAnd, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opcf20, DoAnd, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opcf28, DoAnd, DB, SdB, 7, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opcf30, DoAnd, DB, SdB, 7, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opcf38, DoAnd, DB, SdB, 7, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opcf50, DoAnd, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opcf58, DoAnd, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opcf60, DoAnd, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opcf68, DoAnd, DW, SdW, 7, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opcf70, DoAnd, DW, SdW, 7, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opcf78, DoAnd, DW, SdW, 7, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opcf90, DoAnd, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opcf98, DoAnd, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opcfa0, DoAnd, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opcfa8, DoAnd, DL, SdL, 7, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opcfb0, DoAnd, DL, SdL, 7, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opcfb8, DoAnd, DL, SdL, 7, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8000, DoOr, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4) +Oper (Op8010, DoOr, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Op8018, DoOr, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Op8020, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Op8028, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Op8030, DoOr, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SRB, 16) +Oper (Op8038, DoOr, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8040, DoOr, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Op8050, DoOr, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Op8058, DoOr, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Op8060, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Op8068, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Op8070, DoOr, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SRW, 16) +Oper (Op8078, DoOr, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8080, DoOr, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Op8090, DoOr, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Op8098, DoOr, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Op80a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Op80a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Op80b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Op80b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8110, DoOr, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8118, DoOr, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8120, DoOr, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8128, DoOr, DB, SdB, 0, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8130, DoOr, DB, SdB, 0, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8138, DoOr, DB, SdB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8150, DoOr, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8158, DoOr, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8160, DoOr, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8168, DoOr, DW, SdW, 0, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8170, DoOr, DW, SdW, 0, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8178, DoOr, DW, SdW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8190, DoOr, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8198, DoOr, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op81a0, DoOr, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op81a8, DoOr, DL, SdL, 0, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op81b0, DoOr, DL, SdL, 0, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op81b8, DoOr, DL, SdL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8200, DoOr, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4) +Oper (Op8210, DoOr, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Op8218, DoOr, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Op8220, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Op8228, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Op8230, DoOr, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SRB, 16) +Oper (Op8238, DoOr, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8240, DoOr, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Op8250, DoOr, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Op8258, DoOr, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Op8260, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Op8268, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Op8270, DoOr, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SRW, 16) +Oper (Op8278, DoOr, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8280, DoOr, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Op8290, DoOr, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Op8298, DoOr, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Op82a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Op82a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Op82b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Op82b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8310, DoOr, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8318, DoOr, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8320, DoOr, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8328, DoOr, DB, SdB, 1, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8330, DoOr, DB, SdB, 1, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8338, DoOr, DB, SdB, 1, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8350, DoOr, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8358, DoOr, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8360, DoOr, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8368, DoOr, DW, SdW, 1, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8370, DoOr, DW, SdW, 1, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8378, DoOr, DW, SdW, 1, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8390, DoOr, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8398, DoOr, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op83a0, DoOr, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op83a8, DoOr, DL, SdL, 1, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op83b0, DoOr, DL, SdL, 1, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op83b8, DoOr, DL, SdL, 1, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8400, DoOr, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4) +Oper (Op8410, DoOr, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Op8418, DoOr, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Op8420, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Op8428, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Op8430, DoOr, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SRB, 16) +Oper (Op8438, DoOr, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8440, DoOr, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Op8450, DoOr, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Op8458, DoOr, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Op8460, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Op8468, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Op8470, DoOr, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SRW, 16) +Oper (Op8478, DoOr, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8480, DoOr, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Op8490, DoOr, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Op8498, DoOr, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Op84a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Op84a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Op84b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Op84b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8510, DoOr, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8518, DoOr, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8520, DoOr, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8528, DoOr, DB, SdB, 2, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8530, DoOr, DB, SdB, 2, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8538, DoOr, DB, SdB, 2, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8550, DoOr, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8558, DoOr, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8560, DoOr, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8568, DoOr, DW, SdW, 2, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8570, DoOr, DW, SdW, 2, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8578, DoOr, DW, SdW, 2, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8590, DoOr, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8598, DoOr, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op85a0, DoOr, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op85a8, DoOr, DL, SdL, 2, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op85b0, DoOr, DL, SdL, 2, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op85b8, DoOr, DL, SdL, 2, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8600, DoOr, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4) +Oper (Op8610, DoOr, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Op8618, DoOr, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Op8620, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Op8628, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Op8630, DoOr, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SRB, 16) +Oper (Op8638, DoOr, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8640, DoOr, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Op8650, DoOr, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Op8658, DoOr, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Op8660, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Op8668, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Op8670, DoOr, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SRW, 16) +Oper (Op8678, DoOr, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8680, DoOr, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Op8690, DoOr, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Op8698, DoOr, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Op86a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Op86a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Op86b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Op86b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8710, DoOr, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8718, DoOr, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8720, DoOr, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8728, DoOr, DB, SdB, 3, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8730, DoOr, DB, SdB, 3, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8738, DoOr, DB, SdB, 3, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8750, DoOr, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8758, DoOr, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8760, DoOr, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8768, DoOr, DW, SdW, 3, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8770, DoOr, DW, SdW, 3, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8778, DoOr, DW, SdW, 3, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8790, DoOr, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8798, DoOr, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op87a0, DoOr, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op87a8, DoOr, DL, SdL, 3, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op87b0, DoOr, DL, SdL, 3, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op87b8, DoOr, DL, SdL, 3, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8800, DoOr, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4) +Oper (Op8810, DoOr, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Op8818, DoOr, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Op8820, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Op8828, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Op8830, DoOr, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SRB, 16) +Oper (Op8838, DoOr, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8840, DoOr, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Op8850, DoOr, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Op8858, DoOr, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Op8860, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Op8868, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Op8870, DoOr, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SRW, 16) +Oper (Op8878, DoOr, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8880, DoOr, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Op8890, DoOr, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Op8898, DoOr, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Op88a0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Op88a8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Op88b0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Op88b8, DoOr, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8910, DoOr, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8918, DoOr, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8920, DoOr, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8928, DoOr, DB, SdB, 4, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8930, DoOr, DB, SdB, 4, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8938, DoOr, DB, SdB, 4, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8950, DoOr, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8958, DoOr, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8960, DoOr, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8968, DoOr, DW, SdW, 4, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8970, DoOr, DW, SdW, 4, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8978, DoOr, DW, SdW, 4, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8990, DoOr, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8998, DoOr, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op89a0, DoOr, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op89a8, DoOr, DL, SdL, 4, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op89b0, DoOr, DL, SdL, 4, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op89b8, DoOr, DL, SdL, 4, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8a00, DoOr, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4) +Oper (Op8a10, DoOr, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Op8a18, DoOr, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Op8a20, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Op8a28, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Op8a30, DoOr, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SRB, 16) +Oper (Op8a38, DoOr, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8a40, DoOr, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Op8a50, DoOr, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Op8a58, DoOr, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Op8a60, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Op8a68, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Op8a70, DoOr, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SRW, 16) +Oper (Op8a78, DoOr, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8a80, DoOr, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Op8a90, DoOr, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Op8a98, DoOr, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Op8aa0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Op8aa8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Op8ab0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Op8ab8, DoOr, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8b10, DoOr, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8b18, DoOr, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8b20, DoOr, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8b28, DoOr, DB, SdB, 5, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8b30, DoOr, DB, SdB, 5, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8b38, DoOr, DB, SdB, 5, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8b50, DoOr, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8b58, DoOr, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8b60, DoOr, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8b68, DoOr, DW, SdW, 5, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8b70, DoOr, DW, SdW, 5, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8b78, DoOr, DW, SdW, 5, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8b90, DoOr, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8b98, DoOr, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op8ba0, DoOr, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op8ba8, DoOr, DL, SdL, 5, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op8bb0, DoOr, DL, SdL, 5, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op8bb8, DoOr, DL, SdL, 5, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8c00, DoOr, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4) +Oper (Op8c10, DoOr, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Op8c18, DoOr, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Op8c20, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Op8c28, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Op8c30, DoOr, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SRB, 16) +Oper (Op8c38, DoOr, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8c40, DoOr, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Op8c50, DoOr, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Op8c58, DoOr, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Op8c60, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Op8c68, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Op8c70, DoOr, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SRW, 16) +Oper (Op8c78, DoOr, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8c80, DoOr, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Op8c90, DoOr, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Op8c98, DoOr, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Op8ca0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Op8ca8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Op8cb0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Op8cb8, DoOr, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8d10, DoOr, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8d18, DoOr, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8d20, DoOr, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8d28, DoOr, DB, SdB, 6, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8d30, DoOr, DB, SdB, 6, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8d38, DoOr, DB, SdB, 6, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8d50, DoOr, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8d58, DoOr, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8d60, DoOr, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8d68, DoOr, DW, SdW, 6, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8d70, DoOr, DW, SdW, 6, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8d78, DoOr, DW, SdW, 6, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8d90, DoOr, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8d98, DoOr, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op8da0, DoOr, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op8da8, DoOr, DL, SdL, 6, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op8db0, DoOr, DL, SdL, 6, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op8db8, DoOr, DL, SdL, 6, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op8e00, DoOr, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4) +Oper (Op8e10, DoOr, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Op8e18, DoOr, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Op8e20, DoOr, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Op8e28, DoOr, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Op8e30, DoOr, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SRB, 16) +Oper (Op8e38, DoOr, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op8e40, DoOr, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Op8e50, DoOr, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Op8e58, DoOr, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Op8e60, DoOr, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Op8e68, DoOr, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Op8e70, DoOr, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SRW, 16) +Oper (Op8e78, DoOr, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op8e80, DoOr, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Op8e90, DoOr, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Op8e98, DoOr, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Op8ea0, DoOr, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Op8ea8, DoOr, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Op8eb0, DoOr, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Op8eb8, DoOr, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op8f10, DoOr, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op8f18, DoOr, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op8f20, DoOr, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op8f28, DoOr, DB, SdB, 7, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Op8f30, DoOr, DB, SdB, 7, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Op8f38, DoOr, DB, SdB, 7, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op8f50, DoOr, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op8f58, DoOr, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op8f60, DoOr, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op8f68, DoOr, DW, SdW, 7, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Op8f70, DoOr, DW, SdW, 7, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Op8f78, DoOr, DW, SdW, 7, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op8f90, DoOr, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op8f98, DoOr, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op8fa0, DoOr, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op8fa8, DoOr, DL, SdL, 7, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Op8fb0, DoOr, DL, SdL, 7, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Op8fb8, DoOr, DL, SdL, 7, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opb100, DoEor, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opb110, DoEor, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opb118, DoEor, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opb120, DoEor, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opb128, DoEor, DB, SdB, 0, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opb130, DoEor, DB, SdB, 0, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opb138, DoEor, DB, SdB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opb140, DoEor, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opb150, DoEor, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opb158, DoEor, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opb160, DoEor, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opb168, DoEor, DW, SdW, 0, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opb170, DoEor, DW, SdW, 0, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opb178, DoEor, DW, SdW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opb180, DoEor, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opb190, DoEor, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opb198, DoEor, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opb1a0, DoEor, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opb1a8, DoEor, DL, SdL, 0, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opb1b0, DoEor, DL, SdL, 0, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opb1b8, DoEor, DL, SdL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opb300, DoEor, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opb310, DoEor, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opb318, DoEor, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opb320, DoEor, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opb328, DoEor, DB, SdB, 1, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opb330, DoEor, DB, SdB, 1, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opb338, DoEor, DB, SdB, 1, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opb340, DoEor, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opb350, DoEor, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opb358, DoEor, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opb360, DoEor, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opb368, DoEor, DW, SdW, 1, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opb370, DoEor, DW, SdW, 1, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opb378, DoEor, DW, SdW, 1, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opb380, DoEor, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opb390, DoEor, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opb398, DoEor, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opb3a0, DoEor, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opb3a8, DoEor, DL, SdL, 1, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opb3b0, DoEor, DL, SdL, 1, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opb3b8, DoEor, DL, SdL, 1, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opb500, DoEor, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opb510, DoEor, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opb518, DoEor, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opb520, DoEor, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opb528, DoEor, DB, SdB, 2, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opb530, DoEor, DB, SdB, 2, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opb538, DoEor, DB, SdB, 2, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opb540, DoEor, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opb550, DoEor, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opb558, DoEor, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opb560, DoEor, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opb568, DoEor, DW, SdW, 2, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opb570, DoEor, DW, SdW, 2, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opb578, DoEor, DW, SdW, 2, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opb580, DoEor, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opb590, DoEor, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opb598, DoEor, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opb5a0, DoEor, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opb5a8, DoEor, DL, SdL, 2, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opb5b0, DoEor, DL, SdL, 2, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opb5b8, DoEor, DL, SdL, 2, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opb700, DoEor, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opb710, DoEor, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opb718, DoEor, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opb720, DoEor, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opb728, DoEor, DB, SdB, 3, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opb730, DoEor, DB, SdB, 3, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opb738, DoEor, DB, SdB, 3, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opb740, DoEor, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opb750, DoEor, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opb758, DoEor, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opb760, DoEor, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opb768, DoEor, DW, SdW, 3, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opb770, DoEor, DW, SdW, 3, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opb778, DoEor, DW, SdW, 3, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opb780, DoEor, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opb790, DoEor, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opb798, DoEor, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opb7a0, DoEor, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opb7a8, DoEor, DL, SdL, 3, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opb7b0, DoEor, DL, SdL, 3, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opb7b8, DoEor, DL, SdL, 3, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opb900, DoEor, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opb910, DoEor, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opb918, DoEor, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opb920, DoEor, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opb928, DoEor, DB, SdB, 4, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opb930, DoEor, DB, SdB, 4, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opb938, DoEor, DB, SdB, 4, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opb940, DoEor, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opb950, DoEor, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opb958, DoEor, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opb960, DoEor, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opb968, DoEor, DW, SdW, 4, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opb970, DoEor, DW, SdW, 4, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opb978, DoEor, DW, SdW, 4, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opb980, DoEor, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opb990, DoEor, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opb998, DoEor, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opb9a0, DoEor, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opb9a8, DoEor, DL, SdL, 4, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opb9b0, DoEor, DL, SdL, 4, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opb9b8, DoEor, DL, SdL, 4, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opbb00, DoEor, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opbb10, DoEor, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opbb18, DoEor, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opbb20, DoEor, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opbb28, DoEor, DB, SdB, 5, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opbb30, DoEor, DB, SdB, 5, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opbb38, DoEor, DB, SdB, 5, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opbb40, DoEor, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opbb50, DoEor, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opbb58, DoEor, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opbb60, DoEor, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opbb68, DoEor, DW, SdW, 5, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opbb70, DoEor, DW, SdW, 5, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opbb78, DoEor, DW, SdW, 5, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opbb80, DoEor, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opbb90, DoEor, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opbb98, DoEor, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opbba0, DoEor, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opbba8, DoEor, DL, SdL, 5, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opbbb0, DoEor, DL, SdL, 5, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opbbb8, DoEor, DL, SdL, 5, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opbd00, DoEor, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opbd10, DoEor, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opbd18, DoEor, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opbd20, DoEor, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opbd28, DoEor, DB, SdB, 6, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opbd30, DoEor, DB, SdB, 6, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opbd38, DoEor, DB, SdB, 6, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opbd40, DoEor, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opbd50, DoEor, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opbd58, DoEor, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opbd60, DoEor, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opbd68, DoEor, DW, SdW, 6, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opbd70, DoEor, DW, SdW, 6, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opbd78, DoEor, DW, SdW, 6, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opbd80, DoEor, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opbd90, DoEor, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opbd98, DoEor, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opbda0, DoEor, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opbda8, DoEor, DL, SdL, 6, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opbdb0, DoEor, DL, SdL, 6, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opbdb8, DoEor, DL, SdL, 6, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Opbf00, DoEor, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Opbf10, DoEor, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Opbf18, DoEor, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Opbf20, DoEor, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Opbf28, DoEor, DB, SdB, 7, DB, DA, Cdai, ins7, GMB, SMB, 16) +Oper (Opbf30, DoEor, DB, SdB, 7, DB, DA, Caix, ins7, GMB, SMB, 20) +Oper (Opbf38, DoEor, DB, SdB, 7, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Opbf40, DoEor, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Opbf50, DoEor, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Opbf58, DoEor, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Opbf60, DoEor, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Opbf68, DoEor, DW, SdW, 7, DW, DA, Cdai, ins7, GMW, SMW, 16) +Oper (Opbf70, DoEor, DW, SdW, 7, DW, DA, Caix, ins7, GMW, SMW, 20) +Oper (Opbf78, DoEor, DW, SdW, 7, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Opbf80, DoEor, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Opbf90, DoEor, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Opbf98, DoEor, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Opbfa0, DoEor, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Opbfa8, DoEor, DL, SdL, 7, DL, DA, Cdai, ins7, GML, SML, 24) +Oper (Opbfb0, DoEor, DL, SdL, 7, DL, DA, Caix, ins7, GML, SML, 28) +Oper (Opbfb8, DoEor, DL, SdL, 7, DL, DA, Ceaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op0000, DoOr, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8) +Oper (Op0010, DoOr, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op0018, DoOr, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op0020, DoOr, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op0028, DoOr, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op0030, DoOr, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +OlogSR (Op0038, DoOr, DoOrSR, 0, DB, SimmB, DB, GMB, SMB, GCB, SCB, 20) +Oper (Op0040, DoOr, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8) +Oper (Op0050, DoOr, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16) +Oper (Op0058, DoOr, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16) +Oper (Op0060, DoOr, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20) +Oper (Op0068, DoOr, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20) +Oper (Op0070, DoOr, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24) +OlogSR (Op0078, DoOr, DoOrSR, 1, DW, SimmW, DW, GMW, SMW, GCW, SCW, 20) +Oper (Op0080, DoOr, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16) +Oper (Op0090, DoOr, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28) +Oper (Op0098, DoOr, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28) +Oper (Op00a0, DoOr, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32) +Oper (Op00a8, DoOr, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32) +Oper (Op00b0, DoOr, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36) +Oper (Op00b8, DoOr, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc) + +Oper (Op0200, DoAnd, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8) +Oper (Op0210, DoAnd, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op0218, DoAnd, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op0220, DoAnd, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op0228, DoAnd, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op0230, DoAnd, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +OlogSR (Op0238, DoAnd, DoAndSR, 0, DB, SimmB, DB, GMB, SMB, GCB, SCB, 20) +Oper (Op0240, DoAnd, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8) +Oper (Op0250, DoAnd, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16) +Oper (Op0258, DoAnd, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16) +Oper (Op0260, DoAnd, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20) +Oper (Op0268, DoAnd, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20) +Oper (Op0270, DoAnd, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24) +OlogSR (Op0278, DoAnd, DoAndSR, 1, DW, SimmW, DW, GMW, SMW, GCW, SCW, 20) +Oper (Op0280, DoAnd, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16) +Oper (Op0290, DoAnd, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28) +Oper (Op0298, DoAnd, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28) +Oper (Op02a0, DoAnd, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32) +Oper (Op02a8, DoAnd, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32) +Oper (Op02b0, DoAnd, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36) +Oper (Op02b8, DoAnd, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc) + +Oper (Op0a00, DoEor, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8) +Oper (Op0a10, DoEor, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op0a18, DoEor, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op0a20, DoEor, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op0a28, DoEor, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op0a30, DoEor, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +OlogSR (Op0a38, DoEor, DoEorSR, 0, DB, SimmB, DB, GMB, SMB, GCB, SCB, 20) +Oper (Op0a40, DoEor, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8) +Oper (Op0a50, DoEor, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16) +Oper (Op0a58, DoEor, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16) +Oper (Op0a60, DoEor, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20) +Oper (Op0a68, DoEor, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20) +Oper (Op0a70, DoEor, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24) +OlogSR (Op0a78, DoEor, DoEorSR, 1, DW, SimmW, DW, GMW, SMW, GCW, SCW, 20) +Oper (Op0a80, DoEor, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16) +Oper (Op0a90, DoEor, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28) +Oper (Op0a98, DoEor, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28) +Oper (Op0aa0, DoEor, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32) +Oper (Op0aa8, DoEor, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32) +Oper (Op0ab0, DoEor, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36) +Oper (Op0ab8, DoEor, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc) diff --git a/MCUME_esp32/espcastaway/main/68korigbad/op68kmisc.cpp b/MCUME_esp32/espcastaway/main/68korigbad/op68kmisc.cpp new file mode 100755 index 0000000..f0f10cf --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/op68kmisc.cpp @@ -0,0 +1,1896 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - 68k miscellaneous instructions +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 12.06.2002 JH Correct bus error/address error exception stack frame +* 14.06.2002 JH Implemented STOP, shutdown CPU after multiple bus errors. +* Removed inst parameter from CPU opcode functions. +* 09.07.2002 JH STOP should work now as expected. +* 10.07.2002 JH Fixed X, C and Z-Flag for NEGX, X and C for NEG. +* 27.08.2002 JH Some clarifications in op68k.h +* Implemented additional 68010 registers and instructions. +* 31.08.2002 JH Implemented M68010 exception stack frames. +* 10.09.2002 JH Fixed MOVE to/from CCR: word size +* 15.09.2002 JH Minor SR/Bcc/Scc optimization. +* 25.10.2002 JH CHKTRACE no longer optional, improved implementation. +* PC correct now if MOVE to SR raises privilege violation. +*/ +#ifndef PROTOH +static char sccsid[] = "$Id: op68kmisc.c,v 1.11 2002/10/25 21:56:27 jhoenig Exp $"; +#include "68000.h" +#include "op68k.h" +#include "operin.h" + + +/* +* Opfuncs. +*/ +#define OMoves(Code, Decl, CalcEA, GetReg, SetReg, GetMem, SetMem, retval) \ + unsigned long Code(operin)\ +{\ + register unsigned long cycles=0;\ + Decl(source)\ + unsigned long address;\ + unsigned short ext = GetMPCW();\ + unsigned short index = ext >> 12;\ + if (!GetS()) { ExceptionGroup1(PRIV); };\ + pc += 2;\ + CalcEA(address, ins7)\ + if (ext & 0x800) { \ + GetReg(index, source)\ + SetMem(address, source)\ + } else {\ + GetMem(address, source)\ + SetReg(index, source)\ +}\ + return retval;\ +} + +#define OMoveToSR(Code, Get1, retval)\ + unsigned long Code(operin)\ +{\ + register unsigned long cycles=0;\ + DW(source)\ + if (!GetS()) ExceptionGroup1(PRIV);\ + Get1(source, ins7)\ + SetSRW(source);\ + return retval;\ +} + +#define DoBtst8(target,source) SetZI ((target>>(source & 7))&1); +#define DoBtst32(target,source) SetZI ((target>>(source & 31))&1); +#define DoBchg8(target,source) {uint32 mask=(1 << (source & 7)); SetZI(target&mask); target^=mask;} +#define DoBchg32(target,source) {uint32 mask=(1 << (source & 31)); SetZI(target&mask); target^=mask;} +#define DoBclr8(target,source) {uint32 mask=(1 << (source & 7)); SetZI(target&mask); target&=~mask;} +#define DoBclr32(target,source) {uint32 mask=(1 << (source & 31)); SetZI(target&mask); target&=~mask;} +#define DoBset8(target,source) {uint32 mask=(1 << (source & 7)); SetZI(target&mask); target|=mask;} +#define DoBset32(target,source) {uint32 mask=(1 << (source & 31)); SetZI(target&mask); target|=mask;} +#define DoBra(target,source) if (!source) source = FastMPCW (); pc += source; +#define DoBras(target,source) pc += source; +#define DoBsr(target,source) reg[15] -= 4; if (!source) { source = FastMPCW (); SetMemL (reg[15], GetPC() + 2);} else {SetMemL (reg[15], GetPC());} pc += source; +#define DoBsrs(target,source) reg[15] -= 4; SetMemL (reg[15], GetPC()); pc += source; +#define DoBhi(target,source) if (!source) {source = FastMPCW (); if (CChi) {pc += source;} else { pc += 2;}} else {if (CChi) pc += source;}; +#define DoBhis(target,source) if (CChi) pc += source; +#define DoBls(target,source) if (!source) {source = FastMPCW (); if (CCls) {pc += source;} else { pc += 2;}} else {if (CCls) pc += source;}; +#define DoBlss(target,source) if (CCls) pc += source; +#define DoBcc(target,source) if (!source) {source = FastMPCW (); if (CCcc) {pc += source;} else { pc += 2;}} else {if (CCcc) pc += source;}; +#define DoBccs(target,source) if (CCcc) pc += source; +#define DoBcs(target,source) if (!source) {source = FastMPCW (); if (CCcs) {pc += source;} else { pc += 2;}} else {if (CCcs) pc += source;}; +#define DoBcss(target,source) if (CCcs) pc += source; +#define DoBne(target,source) if (!source) {source = FastMPCW (); if (CCne) {pc += source;} else { pc += 2;}} else {if (CCne) pc += source;}; +#define DoBnes(target,source) if (CCne) pc += source; +#define DoBeq(target,source) if (!source) {source = FastMPCW (); if (CCeq) {pc += source;} else { pc += 2;}} else {if (CCeq) pc += source;}; +#define DoBeqs(target,source) if (CCeq) pc += source; +#define DoBvc(target,source) if (!source) {source = FastMPCW (); if (CCvc) {pc += source;} else { pc += 2;}} else {if (CCvc) pc += source;}; +#define DoBvcs(target,source) if (CCvc) pc += source; +#define DoBvs(target,source) if (!source) {source = FastMPCW (); if (CCvs) {pc += source;} else { pc += 2;}} else {if (CCvs) pc += source;}; +#define DoBvss(target,source) if (CCvs) pc += source; +#define DoBpl(target,source) if (!source) {source = FastMPCW (); if (CCpl) {pc += source;} else { pc += 2;}} else {if (CCpl) pc += source;}; +#define DoBpls(target,source) if (CCpl) pc += source; +#define DoBmi(target,source) if (!source) {source = FastMPCW (); if (CCmi) {pc += source;} else { pc += 2;}} else {if (CCmi) pc += source;}; +#define DoBmis(target,source) if (CCmi) pc += source; +#define DoBge(target,source) if (!source) {source = FastMPCW (); if (CCge) {pc += source;} else { pc += 2;}} else {if (CCge) pc += source;}; +#define DoBges(target,source) if (CCge) pc += source; +#define DoBlt(target,source) if (!source) {source = FastMPCW (); if (CClt) {pc += source;} else { pc += 2;}} else {if (CClt) pc += source;}; +#define DoBlts(target,source) if (CClt) pc += source; +#define DoBgt(target,source) if (!source) {source = FastMPCW (); if (CCgt) {pc += source;} else { pc += 2;}} else {if (CCgt) pc += source;}; +#define DoBgts(target,source) if (CCgt) pc += source; +#define DoBle(target,source) if (!source) {source = FastMPCW (); if (CCle) {pc += source;} else { pc += 2;}} else {if (CCle) pc += source;}; +#define DoBles(target,source) if (CCle) pc += source; + +#define DoChk(target,source) \ +SetN (source < 0); if (source < 0 || source > target) ExceptionGroup2(TRAPCHK); + +#define DoClr(target,source) target = 0; ClrCVSetNZ(target); + +#define DoDbt(target,source) if (!CCt) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbf(target,source) if (!CCf) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbhi(target,source) if (!CChi) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbls(target,source) if (!CCls) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbcc(target,source) if (!CCcc) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbcs(target,source) if (!CCcs) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbne(target,source) if (!CCne) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbeq(target,source) if (!CCeq) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbvc(target,source) if (!CCvc) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbvs(target,source) if (!CCvs) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbpl(target,source) if (!CCpl) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbmi(target,source) if (!CCmi) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbge(target,source) if (!CCge) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDblt(target,source) if (!CClt) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDbgt(target,source) if (!CCgt) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; +#define DoDble(target,source) if (!CCle) {if (--target != -1) pc += FastMPCW(); else pc += 2;} else pc += 2; + +#define DoJmp(target,source) SetPC (source); + +#define DoJsr(target,source) reg[15] -= 4; SetMemL (reg[15], GetPC()); SetPC(source); + +#define DoLea(target,source) target = source; + +#define DoMovecc(target,source) target = source; + +#define DoMovep(target,source) target = source; + +#define DoMoveFromSR(target,source) \ + if (!GetS()) ExceptionGroup1(PRIV); \ +target = source; + +#define DoNeg(target,source) \ + SetV (target < 0 && -target < 0);\ + target = -target;\ + SetXC (target != 0);\ +SetNZ(target); + +/* simplified DoSubx */ +#define DoNegx(target,source) \ + SetV (target < 0);\ + if (GetX()) {\ + SetXC(1);\ + target = -target;\ + target -= 1;\ + } else {\ + SetXC (target != 0);\ + target = -target;\ + }\ + SetV (GetV() && (target < 0));\ + ZeroZ(target!=0);\ +SetN(target < 0); + +#define DoNot(target,source) target = ~target; ClrCVSetNZ(target); + +#define DoPea(target,source) reg[15] -= 4; SetMemL (reg[15],source); + +#define DoSt(target,source) target = CCt ? 0xff : 0x00; +#define DoSf(target,source) target = CCf ? 0xff : 0x00; +#define DoShi(target,source) target = CChi ? 0xff : 0x00; +#define DoSls(target,source) target = CCls ? 0xff : 0x00; +#define DoScc(target,source) target = CCcc ? 0xff : 0x00; +#define DoScs(target,source) target = CCcs ? 0xff : 0x00; +#define DoSne(target,source) target = CCne ? 0xff : 0x00; +#define DoSeq(target,source) target = CCeq ? 0xff : 0x00; +#define DoSvc(target,source) target = CCvc ? 0xff : 0x00; +#define DoSvs(target,source) target = CCvs ? 0xff : 0x00; +#define DoSpl(target,source) target = CCpl ? 0xff : 0x00; +#define DoSmi(target,source) target = CCmi ? 0xff : 0x00; +#define DoSge(target,source) target = CCge ? 0xff : 0x00; +#define DoSlt(target,source) target = CClt ? 0xff : 0x00; +#define DoSgt(target,source) target = CCgt ? 0xff : 0x00; +#define DoSle(target,source) target = CCle ? 0xff : 0x00; + +#define DoTst(target,source) ClrCVSetNZ(target); + +#define DoTas(target,source) ClrCVSetNZ(target); target |= 0x80; + +unsigned long Opc140(operin) /* EXG */ +{ + register long var; + var = reg[0]; + reg[0] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc148(operin) /* EXG */ +{ + register long var; + var = reg[8]; + reg[8] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc188(operin) /* EXG */ +{ + register long var; + var = reg[0]; + reg[0] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc340(operin) /* EXG */ +{ + register long var; + var = reg[1]; + reg[1] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc348(operin) /* EXG */ +{ + register long var; + var = reg[9]; + reg[9] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc388(operin) /* EXG */ +{ + register long var; + var = reg[1]; + reg[1] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc540(operin) /* EXG */ +{ + register long var; + var = reg[2]; + reg[2] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc548(operin) /* EXG */ +{ + register long var; + var = reg[10]; + reg[10] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc588 (operin) /* EXG */ +{ + register long var; + var = reg[2]; + reg[2] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc740(operin) /* EXG */ +{ + register long var; + var = reg[3]; + reg[3] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc748(operin) /* EXG */ +{ + register long var; + var = reg[11]; + reg[11] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc788(operin) /* EXG */ +{ + register long var; + var = reg[3]; + reg[3] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc940(operin) /* EXG */ +{ + register long var; + var = reg[4]; + reg[4] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc948(operin) /* EXG */ +{ + register long var; + var = reg[12]; + reg[12] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opc988(operin) /* EXG */ +{ + register long var; + var = reg[4]; + reg[4] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcb40(operin) /* EXG */ +{ + register long var; + var = reg[5]; + reg[5] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcb48(operin) /* EXG */ +{ + register long var; + var = reg[13]; + reg[13] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcb88(operin) /* EXG */ +{ + register long var; + var = reg[5]; + reg[5] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcd40(operin) /* EXG */ +{ + register long var; + var = reg[6]; + reg[6] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcd48(operin) /* EXG */ +{ + register long var; + var = reg[14]; + reg[14] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcd88(operin) /* EXG */ +{ + register long var; + var = reg[6]; + reg[6] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcf40(operin) /* EXG */ +{ + register long var; + var = reg[7]; + reg[7] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcf48(operin) /* EXG */ +{ + register long var; + var = reg[15]; + reg[15] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Opcf88(operin) /* EXG */ +{ + register long var; + var = reg[7]; + reg[7] = reg[ins15]; + reg[ins15] = var; + return 6; +} + +unsigned long Op4840(operin) /* SWAP */ +{ + long source, target; + source = GetRegL (ins7); + target = ((unsigned) source) >> 16; + source <<= 16; + target |= source; + SetRegL (ins7, target); + ClrCVSetNZ (target); + return 4; +} + +unsigned long Op4848(operin) /* BKPT */ +{ + ExceptionGroup1(ILLINSTR); + return 4; +} + +unsigned long Op4880(operin) /* EXT.W */ +{ + char source; + short target; + source = GetRegB (ins7); + target = source; + SetRegW (ins7, target); + ClrCVSetNZ (target); + return 4; +} + +unsigned long Op4890(operin) /* MOVEM.W to (ax) */ +{ + register unsigned long cycles=8+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW(); + pc += 2; + Cain (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemW (address, GetRegW (index)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +/* TODO: if ax is written, use initial ax content (68000, 68010) +* if ax is written, use final ax content (other CPUs) */ +unsigned long Op48a0(operin) /* MOVEM.W to -(ax) */ +{ + register unsigned long cycles=8+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW(); + pc += 2; + address = reg[8 + ins7]; + index = 15; + while (source) { + if (source & 0x1) { + address -= 2; + SetMemW (address, GetRegW (index)); + cycles+=4; + } + index--; + source = ((unsigned short) source) >> 1; + } + SetRegL (8 + ins7, address); + return cycles&0xfffffffc; +} + +unsigned long Op48a8(operin) /* MOVEM.W to d(ax) */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cdai (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemW (address, GetRegW (index)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op48b0(operin) /* MOVEM.W to d(ax,rx) */ +{ + register unsigned long cycles=14+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Caix (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemW (address, GetRegW (index)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op48b8(operin) /* MOVEM.W to w l */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Ceaw (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemW (address, GetRegW (index)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op48c0(operin) /* EXT.L */ +{ + short source; + long target; + source = GetRegW (ins7); + target = source; + SetRegL (ins7, target); + ClrCVSetNZ (target); + return 4; +} + +unsigned long Op48d0(operin) /* MOVEM.L to (ax) */ +{ + register unsigned long cycles=8+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW(); + pc += 2; + Cain (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemL (address, GetRegL (index)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +/* TODO: if ax is written, use initial ax content (68000, 68010) +* if ax is written, use final ax content (other CPUs) */ +unsigned long Op48e0(operin) /* MOVEM.L to -(ax) */ +{ + register unsigned long cycles=8+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + address = reg[8 + ins7]; + index = 15; + while (source) { + if (source & 0x1) { + address -= 4; + SetMemL (address, GetRegL (index)); + cycles+=8; + } + index--; + source = ((unsigned short) source) >> 1; + } + SetRegL (8 + ins7, address); + return cycles&0xfffffffc; +} + +unsigned long Op48e8(operin) /* MOVEM.L to d(ax) */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cdai (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemL (address, GetRegL (index)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op48f0(operin) /* MOVEM.L to d(ax,rx) */ +{ + register unsigned long cycles=14+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Caix (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemL (address, GetRegL (index)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op48f8(operin) /* MOVEM.L to w l */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Ceaw (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetMemL (address, GetRegL (index)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4c90(operin) /* MOVEM.W from (ax) */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cain (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemW (address)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4c98(operin) /* MOVEM.W from (ax)+ */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cain (address, ins7); /* no increment here! */ + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemW (address)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + SetRegL (8 + ins7, address); + return cycles&0xfffffffc; +} + +unsigned long Op4ca8(operin) /* MOVEM.W from d(ax) */ +{ + register unsigned long cycles=16+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cdai (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemW (address)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4cb0(operin) /* MOVEM.W from d(ax,rx) */ +{ + register unsigned long cycles=18+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Caix (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemW (address)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4cb8(operin) /* MOVEM.W from ea */ +{ + register unsigned long cycles=16+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cear (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemW (address)); + address += 2; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4cd0(operin) /* MOVEM.L from (ax) */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cain (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemL (address)); + address += 4; + cycles+=4; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4cd8(operin) /* MOVEM.L from (ax)+ */ +{ + register unsigned long cycles=12+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cain (address, ins7); /* no increment here! */ + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemL (address)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + SetRegL (8 + ins7, address); + return cycles&0xfffffffc; +} + +unsigned long Op4ce8(operin) /* MOVEM.L from d(ax) */ +{ + register unsigned long cycles=16+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cdai (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemL (address)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4cf0(operin) /* MOVEM.L from d(ax,rx) */ +{ + register unsigned long cycles=18+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Caix (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemL (address)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4cf8(operin) /* MOVEM.L from ea */ +{ + register unsigned long cycles=16+3; + short source; + int index; + long address; + int movecount=0; + source = GetMPCW (); + pc += 2; + Cear (address, ins7); + index = 0; + while (source) { + if (source & 0x1) { + SetRegL (index, (long) GetMemL (address)); + address += 4; + cycles+=8; + } + index++; + source = ((unsigned short) source) >> 1; + } + return cycles&0xfffffffc; +} + +unsigned long Op4e40(operin) /* TRAP */ +{ + ExceptionGroup2(TRAP0 + (ins15)); + return 0; +} + +unsigned long Op4e50(operin) /* LINK */ +{ + long source; + source = GetRegL (8 + ins7); + reg[15] -= 4; + SetMemL (reg[15], source); + source = GetRegL (15); + SetRegL (8 + ins7, source); + source += GetMPCW (); + pc += 2; + SetRegL (15, source); + return 0; +} + +unsigned long Op4e58(operin) /* UNLK */ +{ + long source; + source = GetRegL (8 + ins7); + SetRegL (15, source); + source = GetMemL (reg[15]); + reg[15] += 4; + SetRegL (8 + ins7, source); + return 0; +} + +unsigned long Op4e60(operin) /* MOVE ax,usp */ +{ + if (!GetS ()) + ExceptionGroup1(PRIV); + usp = reg[8 + (ins7)]; + return 0; +} + +unsigned long Op4e68(operin) /* MOVE usp,ax */ +{ + if (!GetS ()) + ExceptionGroup1(PRIV); + reg[8 + (ins7)] = usp; + return 0; +} + +unsigned long Op4e70(operin) /* RESET, NOP, STOP, RTE, RTD, RTS, +* TRAPV, RTR */ +{ + switch (ins7) { + case 0: /* RESET */ + if (!GetS ()) + ExceptionGroup1(PRIV); + break; + case 1: /* NOP */ + break; + case 2: /* STOP */ + Stop(); + break; + case 3: /* RTE */ + if (!GetS ()) + ExceptionGroup1(PRIV); + { + unsigned short sr; +#if CPU_TYPE == 68000 + sr = GetMemW (reg[15]); reg[15] += 2; + SetPC (GetMemL (reg[15])); reg[15] += 4; + SetSRW(sr); +#else + switch (GetMemW(reg[15] + 6) >> 12) { + case 0x0: + break; + case 0x8: + /* FIXME: this shouldn't be a format error */ +#ifdef DEBUG + DBG_STOP(); +#endif + default: + ExceptionGroup1(FORMATERR); + break; + } + sr = GetMemW (reg[15]); reg[15] += 2; + SetPC (GetMemL (reg[15])); reg[15] += 4; + SetSRW(sr); + reg[15] += 2; +#endif + } + break; + case 4: /* RTD */ +#if CPU_TYPE == 68000 + ExceptionGroup1(ILLINSTR); +#else + { + short displacement = GetMPCW(); + SetPC(GetMemL(reg[15])); + reg[15] = reg[15] + 4 + displacement; + } +#endif + break; + case 5: /* RTS */ + SetPC (GetMemL (reg[15])); + reg[15] += 4; + break; + case 6: /* TRAPV */ + if (GetV ()) + ExceptionGroup1(TRAPV); + break; + case 7: /* RTR */ + SetSRB ( GetMemW (reg[15])); + reg[15] += 2; + SetPC (GetMemL (reg[15])); + reg[15] += 4; + break; + } + return 0; +} + +unsigned long Op4e78(operin) /* MOVEC */ +{ + switch (ins7) { + case 2: + if (!GetS ()) { + ExceptionGroup1(PRIV); + } else { + short source; + int index; + source = GetMPCW (); + pc += 2; + index = source >> 12; + switch (source & 0xfff) { + case 0x000: + reg[index] = sfc & 7; + break; + case 0x001: + reg[index] = dfc & 7; + break; + case 0x800: + reg[index] = usp; + break; + case 0x801: + reg[index] = vbr; + break; +#if CPU_TYPE == 68020 + case 0x002: + reg[index] = cacr & 0x3; + break; + case 0x802: + reg[index] = caar & 0xfc; + break; + case 0x803: + reg[index] = msp; + break; + case 0x804: + reg[index] = isp; + break; +#endif + default: + /* as specified by Motorola */ + ExceptionGroup1(ILLINSTR); + break; + } + } + break; + case 3: + if (!GetS ()) { + ExceptionGroup1(PRIV); + } else { + short source; + int index; + source = GetMPCW (); + pc += 2; + index = source >> 12; + switch (source & 0xfff) { + case 0x000: + sfc = reg[index] & 7; + break; + case 0x001: + dfc = reg[index] & 7; + break; + case 0x800: + usp = reg[index]; + break; + case 0x801: + vbr = reg[index]; + break; +#if CPU_TYPE == 68020 + case 0x002: + cacr = reg[index] & 0x3; + break; + case 0x802: + caar = reg[index] & 0xfc; + break; + case 0x803: + msp = reg[index]; + break; + case 0x804: + isp = reg[index]; + break; +#endif + default: + /* as specified by Motorola */ + ExceptionGroup1(ILLINSTR); + break; + } + } + break; + default: + ExceptionGroup1(ILLINSTR); + break; + } + return 0; +} +#else + +#define OMoves(a1,a2,a3,a4,a5,a6,a7,a8) \ +extern unsigned long a1(operin); +#define OMoveToSR(a1, a2, a3)\ +extern unsigned long a1(operin); +#endif + +Oper (Op4000, DoNegx, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op4010, DoNegx, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op4018, DoNegx, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op4020, DoNegx, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op4028, DoNegx, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op4030, DoNegx, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op4038, DoNegx, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op4040, DoNegx, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op4050, DoNegx, DN, SNN, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op4058, DoNegx, DN, SNN, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op4060, DoNegx, DN, SNN, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op4068, DoNegx, DN, SNN, 0, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op4070, DoNegx, DN, SNN, 0, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op4078, DoNegx, DN, SNN, 0, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op4080, DoNegx, DN, SNN, 0, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op4090, DoNegx, DN, SNN, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op4098, DoNegx, DN, SNN, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op40a0, DoNegx, DN, SNN, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op40a8, DoNegx, DN, SNN, 0, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op40b0, DoNegx, DN, SNN, 0, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op40b8, DoNegx, DN, SNN, 0, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +#if CPU_TYPE == 68000 // 68000: MOVE from SR not privileged +Oper (Op40c0, DoMovecc, DW, ScW, 0, DW, DR, Cd, ins7, GN, SRW, 8) +Oper (Op40d0, DoMovecc, DW, ScW, 0, DW, DA, Cain, ins7, GN, SMW, 12) +Oper (Op40d8, DoMovecc, DW, ScW, 0, DW, DA, CaipW, ins7, GN, SMW, 12) +Oper (Op40e0, DoMovecc, DW, ScW, 0, DW, DA, CmaiW, ins7, GN, SMW, 16) +Oper (Op40e8, DoMovecc, DW, ScW, 0, DW, DA, Fdai, ins7, GN, SMW, 16) +Oper (Op40f0, DoMovecc, DW, ScW, 0, DW, DA, Faix, ins7, GN, SMW, 20) +Oper (Op40f8, DoMovecc, DW, ScW, 0, DW, DA, Feaw, ins7, GN, SMW, (cycles+19)&0xfffffffc) +#else +Oper (Op40c0, DoMoveFromSR, DW, ScW, 0, DW, DR, Cd, ins7, GN, SRW, 8) +Oper (Op40d0, DoMoveFromSR, DW, ScW, 0, DW, DA, Cain, ins7, GN, SMW, 12) +Oper (Op40d8, DoMoveFromSR, DW, ScW, 0, DW, DA, CaipW, ins7, GN, SMW, 12) +Oper (Op40e0, DoMoveFromSR, DW, ScW, 0, DW, DA, CmaiW, ins7, GN, SMW, 16) +Oper (Op40e8, DoMoveFromSR, DW, ScW, 0, DW, DA, Fdai, ins7, GN, SMW, 16) +Oper (Op40f0, DoMoveFromSR, DW, ScW, 0, DW, DA, Faix, ins7, GN, SMW, 20) +Oper (Op40f8, DoMoveFromSR, DW, ScW, 0, DW, DA, Feaw, ins7, GN, SMW, (cycles+19)&0xfffffffc) +#endif + +Oper (Op4200, DoClr, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op4210, DoClr, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op4218, DoClr, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op4220, DoClr, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op4228, DoClr, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op4230, DoClr, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op4238, DoClr, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op4240, DoClr, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op4250, DoClr, DN, SNN, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op4258, DoClr, DN, SNN, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op4260, DoClr, DN, SNN, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op4268, DoClr, DN, SNN, 0, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op4270, DoClr, DN, SNN, 0, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op4278, DoClr, DN, SNN, 0, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op4280, DoClr, DN, SNN, 0, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op4290, DoClr, DN, SNN, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op4298, DoClr, DN, SNN, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op42a0, DoClr, DN, SNN, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op42a8, DoClr, DN, SNN, 0, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op42b0, DoClr, DN, SNN, 0, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op42b8, DoClr, DN, SNN, 0, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op42c0, DoMovecc, DW, ScB, 0, DW, DR, Cd, ins7, GN, SRW, 8) +Oper (Op42d0, DoMovecc, DW, ScB, 0, DW, DA, Cain, ins7, GN, SMW, 12) +Oper (Op42d8, DoMovecc, DW, ScB, 0, DW, DA, CaipW, ins7, GN, SMW, 12) +Oper (Op42e0, DoMovecc, DW, ScB, 0, DW, DA, CmaiW, ins7, GN, SMW, 16) +Oper (Op42e8, DoMovecc, DW, ScB, 0, DW, DA, Fdai, ins7, GN, SMW, 16) +Oper (Op42f0, DoMovecc, DW, ScB, 0, DW, DA, Faix, ins7, GN, SMW, 20) +Oper (Op42f8, DoMovecc, DW, ScB, 0, DW, DA, Feaw, ins7, GN, SMW, (cycles+19)&0xfffffffc) + +Oper (Op4400, DoNeg, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op4410, DoNeg, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op4418, DoNeg, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op4420, DoNeg, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op4428, DoNeg, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op4430, DoNeg, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op4438, DoNeg, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op4440, DoNeg, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op4450, DoNeg, DN, SNN, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op4458, DoNeg, DN, SNN, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op4460, DoNeg, DN, SNN, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op4468, DoNeg, DN, SNN, 0, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op4470, DoNeg, DN, SNN, 0, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op4478, DoNeg, DN, SNN, 0, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op4480, DoNeg, DN, SNN, 0, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op4490, DoNeg, DN, SNN, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op4498, DoNeg, DN, SNN, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op44a0, DoNeg, DN, SNN, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op44a8, DoNeg, DN, SNN, 0, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op44b0, DoNeg, DN, SNN, 0, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op44b8, DoNeg, DN, SNN, 0, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op44c0, DoMovecc, DW, SdW, ins7, DB, DN, CN, 0, GN, SCB, 12) +Oper (Op44d0, DoMovecc, DW, SainW, ins7, DB, DN, CN, 0, GN, SCB, 16) +Oper (Op44d8, DoMovecc, DW, SaipW, ins7, DB, DN, CN, 0, GN, SCB, 16) +Oper (Op44e0, DoMovecc, DW, SmaiW, ins7, DB, DN, CN, 0, GN, SCB, 20) +Oper (Op44e8, DoMovecc, DW, SdaiW, ins7, DB, DN, CN, 0, GN, SCB, 20) +Oper (Op44f0, DoMovecc, DW, SaixW, ins7, DB, DN, CN, 0, GN, SCB, 24) +Oper (Op44f8, DoMovecc, DW, SearW, ins7, DB, DN, CN, 0, GN, SCB, (cycles+19)&0xfffffffc) + +Oper (Op4600, DoNot, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op4610, DoNot, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op4618, DoNot, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op4620, DoNot, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op4628, DoNot, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op4630, DoNot, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op4638, DoNot, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op4640, DoNot, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op4650, DoNot, DN, SNN, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op4658, DoNot, DN, SNN, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op4660, DoNot, DN, SNN, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op4668, DoNot, DN, SNN, 0, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op4670, DoNot, DN, SNN, 0, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op4678, DoNot, DN, SNN, 0, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op4680, DoNot, DN, SNN, 0, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op4690, DoNot, DN, SNN, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op4698, DoNot, DN, SNN, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op46a0, DoNot, DN, SNN, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op46a8, DoNot, DN, SNN, 0, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op46b0, DoNot, DN, SNN, 0, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op46b8, DoNot, DN, SNN, 0, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +OMoveToSR (Op46c0, SdW, 12) +OMoveToSR (Op46d0, SainW, 16) +OMoveToSR (Op46d8, SaipW, 16) +OMoveToSR (Op46e0, SmaiW, 18) +OMoveToSR (Op46e8, SdaiW, 20) +OMoveToSR (Op46f0, SaixW, 22) +OMoveToSR (Op46f8, SearW, (cycles)+19&0xfffffffc) + +Oper (Op4850, DoPea, DL, SainA, ins7, DN, DN, CN, 0, GN, SN, 12) +Oper (Op4868, DoPea, DL, SdaiA, ins7, DN, DN, CN, 0, GN, SN, 16) +Oper (Op4870, DoPea, DL, SaixA, ins7, DN, DN, CN, 0, GN, SN, 20) +Oper (Op4878, DoPea, DL, SearA, ins7, DN, DN, CN, 0, GN, SN, (cycles+19)&0xfffffffc) + +Oper (Op4a00, DoTst, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SN, 4) +Oper (Op4a10, DoTst, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op4a18, DoTst, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op4a20, DoTst, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op4a28, DoTst, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op4a30, DoTst, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op4a38, DoTst, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op4a40, DoTst, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SN, 4) +Oper (Op4a50, DoTst, DN, SNN, 0, DW, DA, Cain, ins7, GMW, SN, 8) +Oper (Op4a58, DoTst, DN, SNN, 0, DW, DA, CaipW, ins7, GMW, SN, 8) +Oper (Op4a60, DoTst, DN, SNN, 0, DW, DA, CmaiW, ins7, GMW, SN, 12) +Oper (Op4a68, DoTst, DN, SNN, 0, DW, DA, Fdai, ins7, GMW, SN, 12) +Oper (Op4a70, DoTst, DN, SNN, 0, DW, DA, Faix, ins7, GMW, SN, 16) +Oper (Op4a78, DoTst, DN, SNN, 0, DW, DA, Feaw, ins7, GMW, SN, (cycles+11)&0xfffffffc) +Oper (Op4a80, DoTst, DN, SNN, 0, DL, DR, Cd, ins7, GRL, SN, 4) +Oper (Op4a90, DoTst, DN, SNN, 0, DL, DA, Cain, ins7, GML, SN, 12) +Oper (Op4a98, DoTst, DN, SNN, 0, DL, DA, CaipL, ins7, GML, SN, 12) +Oper (Op4aa0, DoTst, DN, SNN, 0, DL, DA, CmaiL, ins7, GML, SN, 16) +Oper (Op4aa8, DoTst, DN, SNN, 0, DL, DA, Fdai, ins7, GML, SN, 16) +Oper (Op4ab0, DoTst, DN, SNN, 0, DL, DA, Faix, ins7, GML, SN, 20) +Oper (Op4ab8, DoTst, DN, SNN, 0, DL, DA, Feaw, ins7, GML, SN, (cycles+15)&0xfffffffc) +Oper (Op4ac0, DoTas, DN, SNN, 0, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op4ad0, DoTas, DN, SNN, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op4ad8, DoTas, DN, SNN, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op4ae0, DoTas, DN, SNN, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op4ae8, DoTas, DN, SNN, 0, DB, DA, Fdai, ins7, GMB, SMB, 20) +Oper (Op4af0, DoTas, DN, SNN, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op4af8, DoTas, DN, SNN, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+21)&0xfffffffc) + +Oper (Op4e90, DoJsr, DL, SainA, ins7, DN, DN, CN, 0, GN, SN, 16) +Oper (Op4ea8, DoJsr, DL, SdaiA, ins7, DN, DN, CN, 0, GN, SN, 20) +Oper (Op4eb0, DoJsr, DL, SaixA, ins7, DN, DN, CN, 0, GN, SN, 24) +Oper (Op4eb8, DoJsr, DL, SearA, ins7, DN, DN, CN, 0, GN, SN, (cycles+21)&0xfffffffc) + +Oper (Op4ed0, DoJmp, DL, SainA, ins7, DN, DN, CN, 0, GN, SN, 8) +Oper (Op4ee8, DoJmp, DL, SdaiA, ins7, DN, DN, CN, 0, GN, SN, 12) +Oper (Op4ef0, DoJmp, DL, SaixA, ins7, DN, DN, CN, 0, GN, SN, 16) +Oper (Op4ef8, DoJmp, DL, SearA, ins7, DN, DN, CN, 0, GN, SN, (cycles+13)&0xfffffffc) + +Oper (Op4180, DoChk, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4190, DoChk, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4198, DoChk, DW, SdW, 0, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op41a0, DoChk, DW, SdW, 0, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op41a8, DoChk, DW, SdW, 0, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op41b0, DoChk, DW, SdW, 0, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op41b8, DoChk, DW, SdW, 0, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op4380, DoChk, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4390, DoChk, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4398, DoChk, DW, SdW, 1, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op43a0, DoChk, DW, SdW, 1, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op43a8, DoChk, DW, SdW, 1, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op43b0, DoChk, DW, SdW, 1, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op43b8, DoChk, DW, SdW, 1, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op4580, DoChk, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4590, DoChk, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4598, DoChk, DW, SdW, 2, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op45a0, DoChk, DW, SdW, 2, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op45a8, DoChk, DW, SdW, 2, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op45b0, DoChk, DW, SdW, 2, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op45b8, DoChk, DW, SdW, 2, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op4780, DoChk, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4790, DoChk, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4798, DoChk, DW, SdW, 3, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op47a0, DoChk, DW, SdW, 3, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op47a8, DoChk, DW, SdW, 3, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op47b0, DoChk, DW, SdW, 3, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op47b8, DoChk, DW, SdW, 3, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op4980, DoChk, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4990, DoChk, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4998, DoChk, DW, SdW, 4, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op49a0, DoChk, DW, SdW, 4, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op49a8, DoChk, DW, SdW, 4, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op49b0, DoChk, DW, SdW, 4, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op49b8, DoChk, DW, SdW, 4, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op4b80, DoChk, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4b90, DoChk, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4b98, DoChk, DW, SdW, 5, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op4ba0, DoChk, DW, SdW, 5, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op4ba8, DoChk, DW, SdW, 5, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op4bb0, DoChk, DW, SdW, 5, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op4bb8, DoChk, DW, SdW, 5, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op4d80, DoChk, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4d90, DoChk, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4d98, DoChk, DW, SdW, 6, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op4da0, DoChk, DW, SdW, 6, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op4da8, DoChk, DW, SdW, 6, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op4db0, DoChk, DW, SdW, 6, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op4db8, DoChk, DW, SdW, 6, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op4f80, DoChk, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SN, 12) +Oper (Op4f90, DoChk, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SN, 16) +Oper (Op4f98, DoChk, DW, SdW, 7, DW, DA, CaipB, ins7, GMW, SN, 16) +Oper (Op4fa0, DoChk, DW, SdW, 7, DW, DA, CmaiB, ins7, GMW, SN, 16) +Oper (Op4fa8, DoChk, DW, SdW, 7, DW, DA, Fdai, ins7, GMW, SN, 20) +Oper (Op4fb0, DoChk, DW, SdW, 7, DW, DA, Faix, ins7, GMW, SN, 20) +Oper (Op4fb8, DoChk, DW, SdW, 7, DW, DA, Fear, ins7, GMW, SN, (cycles+17)&0xfffffffc) + +Oper (Op41d0, DoLea, DL, SainA, ins7, DL, DR, Ca, 0, GN, SRL, 4) +Oper (Op41e8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 0, GN, SRL, 8) +Oper (Op41f0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 0, GN, SRL, 12) +Oper (Op41f8, DoLea, DL, SearA, ins7, DL, DR, Ca, 0, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op43d0, DoLea, DL, SainA, ins7, DL, DR, Ca, 1, GN, SRL, 4) +Oper (Op43e8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 1, GN, SRL, 8) +Oper (Op43f0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 1, GN, SRL, 12) +Oper (Op43f8, DoLea, DL, SearA, ins7, DL, DR, Ca, 1, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op45d0, DoLea, DL, SainA, ins7, DL, DR, Ca, 2, GN, SRL, 4) +Oper (Op45e8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 2, GN, SRL, 8) +Oper (Op45f0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 2, GN, SRL, 12) +Oper (Op45f8, DoLea, DL, SearA, ins7, DL, DR, Ca, 2, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op47d0, DoLea, DL, SainA, ins7, DL, DR, Ca, 3, GN, SRL, 4) +Oper (Op47e8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 3, GN, SRL, 8) +Oper (Op47f0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 3, GN, SRL, 12) +Oper (Op47f8, DoLea, DL, SearA, ins7, DL, DR, Ca, 3, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op49d0, DoLea, DL, SainA, ins7, DL, DR, Ca, 4, GN, SRL, 4) +Oper (Op49e8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 4, GN, SRL, 8) +Oper (Op49f0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 4, GN, SRL, 12) +Oper (Op49f8, DoLea, DL, SearA, ins7, DL, DR, Ca, 4, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op4bd0, DoLea, DL, SainA, ins7, DL, DR, Ca, 5, GN, SRL, 4) +Oper (Op4be8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 5, GN, SRL, 8) +Oper (Op4bf0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 5, GN, SRL, 12) +Oper (Op4bf8, DoLea, DL, SearA, ins7, DL, DR, Ca, 5, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op4dd0, DoLea, DL, SainA, ins7, DL, DR, Ca, 6, GN, SRL, 4) +Oper (Op4de8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 6, GN, SRL, 8) +Oper (Op4df0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 6, GN, SRL, 12) +Oper (Op4df8, DoLea, DL, SearA, ins7, DL, DR, Ca, 6, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op4fd0, DoLea, DL, SainA, ins7, DL, DR, Ca, 7, GN, SRL, 4) +Oper (Op4fe8, DoLea, DL, SdaiA, ins7, DL, DR, Ca, 7, GN, SRL, 8) +Oper (Op4ff0, DoLea, DL, SaixA, ins7, DL, DR, Ca, 7, GN, SRL, 12) +Oper (Op4ff8, DoLea, DL, SearA, ins7, DL, DR, Ca, 7, GN, SRL, (cycles+11)&0xfffffffc) + +Oper (Op50c0, DoSt, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op50c8, DoDbt, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op50d0, DoSt, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op50d8, DoSt, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op50e0, DoSt, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op50e8, DoSt, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op50f0, DoSt, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op50f8, DoSt, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op51c0, DoSf, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op51c8, DoDbf, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op51d0, DoSf, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op51d8, DoSf, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op51e0, DoSf, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op51e8, DoSf, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op51f0, DoSf, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op51f8, DoSf, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op52c0, DoShi, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op52c8, DoDbhi, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op52d0, DoShi, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op52d8, DoShi, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op52e0, DoShi, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op52e8, DoShi, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op52f0, DoShi, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op52f8, DoShi, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op53c0, DoSls, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op53c8, DoDbls, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op53d0, DoSls, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op53d8, DoSls, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op53e0, DoSls, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op53e8, DoSls, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op53f0, DoSls, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op53f8, DoSls, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op54c0, DoScc, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op54c8, DoDbcc, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op54d0, DoScc, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op54d8, DoScc, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op54e0, DoScc, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op54e8, DoScc, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op54f0, DoScc, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op54f8, DoScc, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op55c0, DoScs, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op55c8, DoDbcs, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op55d0, DoScs, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op55d8, DoScs, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op55e0, DoScs, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op55e8, DoScs, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op55f0, DoScs, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op55f8, DoScs, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op56c0, DoSne, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op56c8, DoDbne, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op56d0, DoSne, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op56d8, DoSne, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op56e0, DoSne, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op56e8, DoSne, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op56f0, DoSne, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op56f8, DoSne, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op57c0, DoSeq, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op57c8, DoDbeq, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op57d0, DoSeq, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op57d8, DoSeq, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op57e0, DoSeq, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op57e8, DoSeq, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op57f0, DoSeq, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op57f8, DoSeq, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op58c0, DoSvc, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op58c8, DoDbvc, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op58d0, DoSvc, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op58d8, DoSvc, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op58e0, DoSvc, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op58e8, DoSvc, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op58f0, DoSvc, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op58f8, DoSvc, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op59c0, DoSvs, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op59c8, DoDbvs, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op59d0, DoSvs, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op59d8, DoSvs, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op59e0, DoSvs, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op59e8, DoSvs, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op59f0, DoSvs, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op59f8, DoSvs, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op5ac0, DoSpl, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op5ac8, DoDbpl, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op5ad0, DoSpl, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op5ad8, DoSpl, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op5ae0, DoSpl, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op5ae8, DoSpl, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op5af0, DoSpl, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op5af8, DoSpl, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op5bc0, DoSmi, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op5bc8, DoDbmi, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op5bd0, DoSmi, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op5bd8, DoSmi, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op5be0, DoSmi, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op5be8, DoSmi, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op5bf0, DoSmi, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op5bf8, DoSmi, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op5cc0, DoSge, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op5cc8, DoDbge, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op5cd0, DoSge, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op5cd8, DoSge, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op5ce0, DoSge, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op5ce8, DoSge, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op5cf0, DoSge, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op5cf8, DoSge, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op5dc0, DoSlt, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op5dc8, DoDblt, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op5dd0, DoSlt, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op5dd8, DoSlt, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op5de0, DoSlt, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op5de8, DoSlt, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op5df0, DoSlt, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op5df8, DoSlt, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op5ec0, DoSgt, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op5ec8, DoDbgt, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op5ed0, DoSgt, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op5ed8, DoSgt, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op5ee0, DoSgt, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op5ee8, DoSgt, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op5ef0, DoSgt, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op5ef8, DoSgt, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op5fc0, DoSle, DN, SNN, 0, DB, DR, Cd, ins7, GN, SRB, 4) +Oper (Op5fc8, DoDble, DN, SNN, 0, DW, DR, Cd, ins7, GRW, SRW, 12) +Oper (Op5fd0, DoSle, DN, SNN, 0, DB, DA, Cain, ins7, GN, SMB, 12) +Oper (Op5fd8, DoSle, DN, SNN, 0, DB, DA, CaipB, ins7, GN, SMB, 12) +Oper (Op5fe0, DoSle, DN, SNN, 0, DB, DA, CmaiB, ins7, GN, SMB, 16) +Oper (Op5fe8, DoSle, DN, SNN, 0, DB, DA, Fdai, ins7, GN, SMB, 16) +Oper (Op5ff0, DoSle, DN, SNN, 0, DB, DA, Faix, ins7, GN, SMB, 20) +Oper (Op5ff8, DoSle, DN, SNN, 0, DB, DA, Feaw, ins7, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op6000, DoBra, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6008, DoBras, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6100, DoBsr, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 20) +Oper (Op6108, DoBsrs, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6200, DoBhi, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6208, DoBhis, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6300, DoBls, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6308, DoBlss, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6400, DoBcc, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6408, DoBccs, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6500, DoBcs, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6508, DoBcss, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6600, DoBne, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6608, DoBnes, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6700, DoBeq, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6708, DoBeqs, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6800, DoBvc, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6808, DoBvcs, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6900, DoBvs, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6908, DoBvss, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6a00, DoBpl, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6a08, DoBpls, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6b00, DoBmi, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6b08, DoBmis, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6c00, DoBge, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6c08, DoBges, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6d00, DoBlt, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6d08, DoBlts, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6e00, DoBgt, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6e08, DoBgts, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 4) +Oper (Op6f00, DoBle, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) +Oper (Op6f08, DoBles, DW, SNQ, 0, DN, DN, CN, 0, GN, SN, 12) + +Oper (Op0100, DoBtst32, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0108, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 0, GN, SRW, 16) +Oper (Op0110, DoBtst8, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0118, DoBtst8, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0120, DoBtst8, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0128, DoBtst8, DB, SdB, 0, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0130, DoBtst8, DB, SdB, 0, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0138, DoBtst8, DB, SdB, 0, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0140, DoBchg32, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0148, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 0, GN, SRL, 24) +Oper (Op0150, DoBchg8, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0158, DoBchg8, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0160, DoBchg8, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0168, DoBchg8, DB, SdB, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0170, DoBchg8, DB, SdB, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0178, DoBchg8, DB, SdB, 0, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0180, DoBclr32, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0188, DoMovep, DW, SdW, 0, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0190, DoBclr8, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0198, DoBclr8, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op01a0, DoBclr8, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op01a8, DoBclr8, DB, SdB, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op01b0, DoBclr8, DB, SdB, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op01b8, DoBclr8, DB, SdB, 0, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op01c0, DoBset32, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op01c8, DoMovep, DL, SdL, 0, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op01d0, DoBset8, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op01d8, DoBset8, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op01e0, DoBset8, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op01e8, DoBset8, DB, SdB, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op01f0, DoBset8, DB, SdB, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op01f8, DoBset8, DB, SdB, 0, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +Oper (Op0300, DoBtst32, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0308, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 1, GN, SRW, 16) +Oper (Op0310, DoBtst8, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0318, DoBtst8, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0320, DoBtst8, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0328, DoBtst8, DB, SdB, 1, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0330, DoBtst8, DB, SdB, 1, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0338, DoBtst8, DB, SdB, 1, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0340, DoBchg32, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0348, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 1, GN, SRL, 24) +Oper (Op0350, DoBchg8, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0358, DoBchg8, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0360, DoBchg8, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0368, DoBchg8, DB, SdB, 1, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0370, DoBchg8, DB, SdB, 1, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0378, DoBchg8, DB, SdB, 1, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0380, DoBclr32, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0388, DoMovep, DW, SdW, 1, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0390, DoBclr8, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0398, DoBclr8, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op03a0, DoBclr8, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op03a8, DoBclr8, DB, SdB, 1, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op03b0, DoBclr8, DB, SdB, 1, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op03b8, DoBclr8, DB, SdB, 1, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op03c0, DoBset32, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op03c8, DoMovep, DL, SdL, 1, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op03d0, DoBset8, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op03d8, DoBset8, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op03e0, DoBset8, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op03e8, DoBset8, DB, SdB, 1, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op03f0, DoBset8, DB, SdB, 1, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op03f8, DoBset8, DB, SdB, 1, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +Oper (Op0500, DoBtst32, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0508, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 2, GN, SRW, 16) +Oper (Op0510, DoBtst8, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0518, DoBtst8, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0520, DoBtst8, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0528, DoBtst8, DB, SdB, 2, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0530, DoBtst8, DB, SdB, 2, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0538, DoBtst8, DB, SdB, 2, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0540, DoBchg32, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0548, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 2, GN, SRL, 24) +Oper (Op0550, DoBchg8, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0558, DoBchg8, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0560, DoBchg8, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0568, DoBchg8, DB, SdB, 2, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0570, DoBchg8, DB, SdB, 2, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0578, DoBchg8, DB, SdB, 2, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0580, DoBclr32, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0588, DoMovep, DW, SdW, 2, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0590, DoBclr8, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0598, DoBclr8, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op05a0, DoBclr8, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op05a8, DoBclr8, DB, SdB, 2, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op05b0, DoBclr8, DB, SdB, 2, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op05b8, DoBclr8, DB, SdB, 2, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op05c0, DoBset32, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op05c8, DoMovep, DL, SdL, 2, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op05d0, DoBset8, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op05d8, DoBset8, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op05e0, DoBset8, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op05e8, DoBset8, DB, SdB, 2, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op05f0, DoBset8, DB, SdB, 2, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op05f8, DoBset8, DB, SdB, 2, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +Oper (Op0700, DoBtst32, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0708, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 3, GN, SRW, 16) +Oper (Op0710, DoBtst8, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0718, DoBtst8, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0720, DoBtst8, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0728, DoBtst8, DB, SdB, 3, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0730, DoBtst8, DB, SdB, 3, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0738, DoBtst8, DB, SdB, 3, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0740, DoBchg32, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0748, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 3, GN, SRL, 24) +Oper (Op0750, DoBchg8, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0758, DoBchg8, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0760, DoBchg8, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0768, DoBchg8, DB, SdB, 3, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0770, DoBchg8, DB, SdB, 3, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0778, DoBchg8, DB, SdB, 3, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0780, DoBclr32, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0788, DoMovep, DW, SdW, 3, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0790, DoBclr8, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0798, DoBclr8, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op07a0, DoBclr8, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op07a8, DoBclr8, DB, SdB, 3, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op07b0, DoBclr8, DB, SdB, 3, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op07b8, DoBclr8, DB, SdB, 3, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op07c0, DoBset32, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op07c8, DoMovep, DL, SdL, 3, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op07d0, DoBset8, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op07d8, DoBset8, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op07e0, DoBset8, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op07e8, DoBset8, DB, SdB, 3, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op07f0, DoBset8, DB, SdB, 3, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op07f8, DoBset8, DB, SdB, 3, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +Oper (Op0900, DoBtst32, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0908, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 4, GN, SRW, 16) +Oper (Op0910, DoBtst8, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0918, DoBtst8, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0920, DoBtst8, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0928, DoBtst8, DB, SdB, 4, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0930, DoBtst8, DB, SdB, 4, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0938, DoBtst8, DB, SdB, 4, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0940, DoBchg32, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0948, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 4, GN, SRL, 24) +Oper (Op0950, DoBchg8, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0958, DoBchg8, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0960, DoBchg8, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0968, DoBchg8, DB, SdB, 4, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0970, DoBchg8, DB, SdB, 4, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0978, DoBchg8, DB, SdB, 4, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0980, DoBclr32, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0988, DoMovep, DW, SdW, 4, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0990, DoBclr8, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0998, DoBclr8, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op09a0, DoBclr8, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op09a8, DoBclr8, DB, SdB, 4, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op09b0, DoBclr8, DB, SdB, 4, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op09b8, DoBclr8, DB, SdB, 4, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op09c0, DoBset32, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op09c8, DoMovep, DL, SdL, 4, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op09d0, DoBset8, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op09d8, DoBset8, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op09e0, DoBset8, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op09e8, DoBset8, DB, SdB, 4, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op09f0, DoBset8, DB, SdB, 4, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op09f8, DoBset8, DB, SdB, 4, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +Oper (Op0b00, DoBtst32, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0b08, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 5, GN, SRW, 16) +Oper (Op0b10, DoBtst8, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0b18, DoBtst8, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0b20, DoBtst8, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0b28, DoBtst8, DB, SdB, 5, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0b30, DoBtst8, DB, SdB, 5, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0b38, DoBtst8, DB, SdB, 5, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0b40, DoBchg32, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0b48, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 5, GN, SRL, 24) +Oper (Op0b50, DoBchg8, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0b58, DoBchg8, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0b60, DoBchg8, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0b68, DoBchg8, DB, SdB, 5, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0b70, DoBchg8, DB, SdB, 5, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0b78, DoBchg8, DB, SdB, 5, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0b80, DoBclr32, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0b88, DoMovep, DW, SdW, 5, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0b90, DoBclr8, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0b98, DoBclr8, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0ba0, DoBclr8, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0ba8, DoBclr8, DB, SdB, 5, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0bb0, DoBclr8, DB, SdB, 5, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0bb8, DoBclr8, DB, SdB, 5, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0bc0, DoBset32, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0bc8, DoMovep, DL, SdL, 5, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op0bd0, DoBset8, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0bd8, DoBset8, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0be0, DoBset8, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0be8, DoBset8, DB, SdB, 5, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0bf0, DoBset8, DB, SdB, 5, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0bf8, DoBset8, DB, SdB, 5, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +Oper (Op0d00, DoBtst32, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0d08, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 6, GN, SRW, 16) +Oper (Op0d10, DoBtst8, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0d18, DoBtst8, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0d20, DoBtst8, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0d28, DoBtst8, DB, SdB, 6, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0d30, DoBtst8, DB, SdB, 6, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0d38, DoBtst8, DB, SdB, 6, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0d40, DoBchg32, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0d48, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 6, GN, SRL, 24) +Oper (Op0d50, DoBchg8, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0d58, DoBchg8, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0d60, DoBchg8, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0d68, DoBchg8, DB, SdB, 6, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0d70, DoBchg8, DB, SdB, 6, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0d78, DoBchg8, DB, SdB, 6, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0d80, DoBclr32, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0d88, DoMovep, DW, SdW, 6, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0d90, DoBclr8, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0d98, DoBclr8, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0da0, DoBclr8, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0da8, DoBclr8, DB, SdB, 6, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0db0, DoBclr8, DB, SdB, 6, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0db8, DoBclr8, DB, SdB, 6, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0dc0, DoBset32, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0dc8, DoMovep, DL, SdL, 6, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op0dd0, DoBset8, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0dd8, DoBset8, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0de0, DoBset8, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0de8, DoBset8, DB, SdB, 6, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0df0, DoBset8, DB, SdB, 6, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0df8, DoBset8, DB, SdB, 6, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +OMoves (Op0e10, DB, Cain, GRB, SRB, GMB, SMB, 12) +OMoves (Op0e18, DB, CaipB, GRB, SRB, GMB, SMB, 12) +OMoves (Op0e20, DB, CmaiB, GRB, SRB, GMB, SMB, 16) +OMoves (Op0e28, DB, Cdai, GRB, SRB, GMB, SMB, 16) +OMoves (Op0e30, DB, Caix, GRB, SRB, GMB, SMB, 20) +OMoves (Op0e38, DB, Ceaw, GRB, SRB, GMB, SMB, (cycles+19)&0xfffffffc) +OMoves (Op0e50, DW, Cain, GRW, SRW, GMW, SMW, 12) +OMoves (Op0e58, DW, CaipB, GRW, SRW, GMW, SMW, 12) +OMoves (Op0e60, DW, CmaiB, GRW, SRW, GMW, SMW, 16) +OMoves (Op0e68, DW, Cdai, GRW, SRW, GMW, SMW, 16) +OMoves (Op0e70, DW, Caix, GRW, SRW, GMW, SMW, 20) +OMoves (Op0e78, DW, Ceaw, GRW, SRW, GMW, SMW, (cycles+19)&0xfffffffc) +OMoves (Op0e90, DL, Cain, GRL, SRL, GML, SML, 20) +OMoves (Op0e98, DL, CaipB, GRL, SRL, GML, SML, 20) +OMoves (Op0ea0, DL, CmaiB, GRL, SRL, GML, SML, 24) +OMoves (Op0ea8, DL, Cdai, GRL, SRL, GML, SML, 24) +OMoves (Op0eb0, DL, Caix, GRL, SRL, GML, SML, 28) +OMoves (Op0eb8, DL, Ceaw, GRL, SRL, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op0f00, DoBtst32, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SN, 8) +Oper (Op0f08, DoMovep, DW, SdaiPW, ins7, DW, DR, Cd, 7, GN, SRW, 16) +Oper (Op0f10, DoBtst8, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SN, 8) +Oper (Op0f18, DoBtst8, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SN, 8) +Oper (Op0f20, DoBtst8, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SN, 12) +Oper (Op0f28, DoBtst8, DB, SdB, 7, DB, DA, Fdai, ins7, GMB, SN, 12) +Oper (Op0f30, DoBtst8, DB, SdB, 7, DB, DA, Faix, ins7, GMB, SN, 16) +Oper (Op0f38, DoBtst8, DB, SdB, 7, DB, DA, Fear, ins7, GMB, SN, (cycles+11)&0xfffffffc) +Oper (Op0f40, DoBchg32, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0f48, DoMovep, DL, SdaiPL, ins7, DL, DR, Cd, 7, GN, SRL, 24) +Oper (Op0f50, DoBchg8, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0f58, DoBchg8, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0f60, DoBchg8, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0f68, DoBchg8, DB, SdB, 7, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0f70, DoBchg8, DB, SdB, 7, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0f78, DoBchg8, DB, SdB, 7, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0f80, DoBclr32, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0f88, DoMovep, DW, SdW, 7, DW, DA, Fdai, ins7, GN, SPW, 16) +Oper (Op0f90, DoBclr8, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0f98, DoBclr8, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0fa0, DoBclr8, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0fa8, DoBclr8, DB, SdB, 7, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0fb0, DoBclr8, DB, SdB, 7, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0fb8, DoBclr8, DB, SdB, 7, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op0fc0, DoBset32, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op0fc8, DoMovep, DL, SdL, 7, DL, DA, Fdai, ins7, GN, SPL, 24) +Oper (Op0fd0, DoBset8, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op0fd8, DoBset8, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op0fe0, DoBset8, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op0fe8, DoBset8, DB, SdB, 7, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op0ff0, DoBset8, DB, SdB, 7, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op0ff8, DoBset8, DB, SdB, 7, DB, DA, Fear, ins7, GMB, SMB, (cycles+19)&0xfffffffc) + +Oper (Op0800, DoBtst32, DB, SimmB, 0, DL, DR, Cd, ins7, GRL, SN, 12) +Oper (Op0810, DoBtst8, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SN, 12) +Oper (Op0818, DoBtst8, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SN, 12) +Oper (Op0820, DoBtst8, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SN, 16) +Oper (Op0828, DoBtst8, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SN, 16) +Oper (Op0830, DoBtst8, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SN, 20) +Oper (Op0838, DoBtst8, DB, SimmB, 0, DB, DA, Cear, ins7, GMB, SN, (cycles+15)&0xfffffffc) +Oper (Op0840, DoBchg32, DL, SimmB, 0, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op0850, DoBchg8, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op0858, DoBchg8, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op0860, DoBchg8, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op0868, DoBchg8, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op0870, DoBchg8, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +Oper (Op0878, DoBchg8, DB, SimmB, 0, DB, DA, Cear, ins7, GMB, SMB, (cycles+23)&0xfffffffc) +Oper (Op0880, DoBclr32, DL, SimmB, 0, DL, DR, Cd, ins7, GRL, SRL, 16) +Oper (Op0890, DoBclr8, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op0898, DoBclr8, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op08a0, DoBclr8, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op08a8, DoBclr8, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op08b0, DoBclr8, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +Oper (Op08b8, DoBclr8, DB, SimmB, 0, DB, DA, Cear, ins7, GMB, SMB, (cycles+23)&0xfffffffc) +Oper (Op08c0, DoBset32, DL, SimmB, 0, DL, DR, Cd, ins7, GRL, SRL, 12) +Oper (Op08d0, DoBset8, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op08d8, DoBset8, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op08e0, DoBset8, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op08e8, DoBset8, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op08f0, DoBset8, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +Oper (Op08f8, DoBset8, DB, SimmB, 0, DB, DA, Cear, ins7, GMB, SMB, (cycles+23)&0xfffffffc) diff --git a/MCUME_esp32/espcastaway/main/68korigbad/op68kmove.cpp b/MCUME_esp32/espcastaway/main/68korigbad/op68kmove.cpp new file mode 100755 index 0000000..c215a63 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/op68kmove.cpp @@ -0,0 +1,1335 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - 68k move instructions +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 0.02.00 JH FAST1.0.1 code import: KR -> ANSI, restructuring +*/ +#ifndef PROTOH +static char sccsid[] = "$Id: op68kmove.c,v 1.1.1.1 2002/05/25 23:04:30 jhoenig Exp $"; +#include "68000.h" +#include "op68k.h" + +#define DoMoveB(target,source) target = source; ClrCVSetNZ(target); +#define DoMoveW(target,source) target = source; ClrCVSetNZ(target); +#define DoMoveL(target,source) target = source; ClrCVSetNZ(target); + +#define DoMovea(target,source) target = source; + +#endif + +Oper (Op1000, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 0, GN, SRB, 4) +Oper (Op1010, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 0, GN, SRB, 8) +Oper (Op1018, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 0, GN, SRB, 8) +Oper (Op1020, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 0, GN, SRB, 12) +Oper (Op1028, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 0, GN, SRB, 12) +Oper (Op1030, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 0, GN, SRB, 16) +Oper (Op1038, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 0, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1080, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 0, GN, SMB, 8) +Oper (Op1090, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 0, GN, SMB, 12) +Oper (Op1098, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 0, GN, SMB, 12) +Oper (Op10a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 0, GN, SMB, 16) +Oper (Op10a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 0, GN, SMB, 16) +Oper (Op10b0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 0, GN, SMB, 20) +Oper (Op10b8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 0, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op10c0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB, 0, GN, SMB, 8) +Oper (Op10d0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB, 0, GN, SMB, 12) +Oper (Op10d8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB, 0, GN, SMB, 12) +Oper (Op10e0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB, 0, GN, SMB, 16) +Oper (Op10e8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB, 0, GN, SMB, 16) +Oper (Op10f0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB, 0, GN, SMB, 20) +Oper (Op10f8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB, 0, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1100, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB, 0, GN, SMB, 12) +Oper (Op1110, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB, 0, GN, SMB, 16) +Oper (Op1118, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB, 0, GN, SMB, 16) +Oper (Op1120, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB, 0, GN, SMB, 16) +Oper (Op1128, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB, 0, GN, SMB, 20) +Oper (Op1130, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB, 0, GN, SMB, 20) +Oper (Op1138, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB, 0, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1140, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 0, GN, SMB, 12) +Oper (Op1150, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 0, GN, SMB, 16) +Oper (Op1158, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 0, GN, SMB, 16) +Oper (Op1160, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 0, GN, SMB, 20) +Oper (Op1168, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 0, GN, SMB, 20) +Oper (Op1170, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 0, GN, SMB, 24) +Oper (Op1178, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 0, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1180, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 0, GN, SMB, 16) +Oper (Op1190, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 0, GN, SMB, 20) +Oper (Op1198, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 0, GN, SMB, 20) +Oper (Op11a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 0, GN, SMB, 20) +Oper (Op11a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 0, GN, SMB, 24) +Oper (Op11b0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 0, GN, SMB, 24) +Oper (Op11b8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 0, GN, SMB, (cycles+21)&0xfffffffc) +Oper (Op11c0, DoMoveB, DB, SdB, ins7, DB, DA, Feaw, 0, GN, SMB, 12) +Oper (Op11d0, DoMoveB, DB, SainB, ins7, DB, DA, Feaw, 0, GN, SMB, 16) +Oper (Op11d8, DoMoveB, DB, SaipB, ins7, DB, DA, Feaw, 0, GN, SMB, 16) +Oper (Op11e0, DoMoveB, DB, SmaiB, ins7, DB, DA, Feaw, 0, GN, SMB, 20) +Oper (Op11e8, DoMoveB, DB, SdaiB, ins7, DB, DA, Ceaw, 0, GN, SMB, 20) +Oper (Op11f0, DoMoveB, DB, SaixB, ins7, DB, DA, Ceaw, 0, GN, SMB, 24) +Oper (Op11f8, DoMoveB, DB, SearB, ins7, DB, DA, Ceaw, 0, GN, SMB, (cycles+19)&0xfffffffc) + +Oper (Op1200, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 1, GN, SRB, 4) +Oper (Op1210, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 1, GN, SRB, 8) +Oper (Op1218, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 1, GN, SRB, 8) +Oper (Op1220, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 1, GN, SRB, 12) +Oper (Op1228, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 1, GN, SRB, 12) +Oper (Op1230, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 1, GN, SRB, 16) +Oper (Op1238, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 1, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1280, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 1, GN, SMB, 8) +Oper (Op1290, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 1, GN, SMB, 12) +Oper (Op1298, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 1, GN, SMB, 12) +Oper (Op12a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 1, GN, SMB, 16) +Oper (Op12a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 1, GN, SMB, 16) +Oper (Op12b0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 1, GN, SMB, 20) +Oper (Op12b8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 1, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op12c0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB, 1, GN, SMB, 8) +Oper (Op12d0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB, 1, GN, SMB, 12) +Oper (Op12d8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB, 1, GN, SMB, 12) +Oper (Op12e0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB, 1, GN, SMB, 16) +Oper (Op12e8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB, 1, GN, SMB, 16) +Oper (Op12f0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB, 1, GN, SMB, 20) +Oper (Op12f8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB, 1, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1300, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB, 1, GN, SMB, 12) +Oper (Op1310, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB, 1, GN, SMB, 16) +Oper (Op1318, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB, 1, GN, SMB, 16) +Oper (Op1320, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB, 1, GN, SMB, 16) +Oper (Op1328, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB, 1, GN, SMB, 20) +Oper (Op1330, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB, 1, GN, SMB, 20) +Oper (Op1338, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB, 1, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1340, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 1, GN, SMB, 12) +Oper (Op1350, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 1, GN, SMB, 16) +Oper (Op1358, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 1, GN, SMB, 16) +Oper (Op1360, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 1, GN, SMB, 20) +Oper (Op1368, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 1, GN, SMB, 20) +Oper (Op1370, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 1, GN, SMB, 24) +Oper (Op1378, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 1, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1380, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 1, GN, SMB, 16) +Oper (Op1390, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 1, GN, SMB, 20) +Oper (Op1398, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 1, GN, SMB, 20) +Oper (Op13a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 1, GN, SMB, 20) +Oper (Op13a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 1, GN, SMB, 24) +Oper (Op13b0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 1, GN, SMB, 24) +Oper (Op13b8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 1, GN, SMB, (cycles+21)&0xfffffffc) +Oper (Op13c0, DoMoveB, DB, SdB, ins7, DB, DA, Feaw, 1, GN, SMB, 16) +Oper (Op13d0, DoMoveB, DB, SainB, ins7, DB, DA, Feaw, 1, GN, SMB, 20) +Oper (Op13d8, DoMoveB, DB, SaipB, ins7, DB, DA, Feaw, 1, GN, SMB, 20) +Oper (Op13e0, DoMoveB, DB, SmaiB, ins7, DB, DA, Feaw, 1, GN, SMB, 24) +Oper (Op13e8, DoMoveB, DB, SdaiB, ins7, DB, DA, Ceaw, 1, GN, SMB, 24) +Oper (Op13f0, DoMoveB, DB, SaixB, ins7, DB, DA, Ceaw, 1, GN, SMB, 28) +Oper (Op13f8, DoMoveB, DB, SearB, ins7, DB, DA, Ceaw, 1, GN, SMB, (cycles+23)&0xfffffffc) + +Oper (Op1400, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 2, GN, SRB, 4) +Oper (Op1410, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 2, GN, SRB, 8) +Oper (Op1418, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 2, GN, SRB, 8) +Oper (Op1420, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 2, GN, SRB, 12) +Oper (Op1428, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 2, GN, SRB, 12) +Oper (Op1430, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 2, GN, SRB, 16) +Oper (Op1438, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 2, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1480, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 2, GN, SMB, 8) +Oper (Op1490, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 2, GN, SMB, 12) +Oper (Op1498, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 2, GN, SMB, 12) +Oper (Op14a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 2, GN, SMB, 16) +Oper (Op14a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 2, GN, SMB, 16) +Oper (Op14b0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 2, GN, SMB, 20) +Oper (Op14b8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 2, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op14c0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB, 2, GN, SMB, 8) +Oper (Op14d0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB, 2, GN, SMB, 12) +Oper (Op14d8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB, 2, GN, SMB, 12) +Oper (Op14e0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB, 2, GN, SMB, 16) +Oper (Op14e8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB, 2, GN, SMB, 16) +Oper (Op14f0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB, 2, GN, SMB, 20) +Oper (Op14f8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB, 2, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1500, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB, 2, GN, SMB, 12) +Oper (Op1510, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB, 2, GN, SMB, 16) +Oper (Op1518, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB, 2, GN, SMB, 16) +Oper (Op1520, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB, 2, GN, SMB, 16) +Oper (Op1528, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB, 2, GN, SMB, 20) +Oper (Op1530, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB, 2, GN, SMB, 20) +Oper (Op1538, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB, 2, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1540, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 2, GN, SMB, 12) +Oper (Op1550, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 2, GN, SMB, 16) +Oper (Op1558, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 2, GN, SMB, 16) +Oper (Op1560, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 2, GN, SMB, 20) +Oper (Op1568, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 2, GN, SMB, 20) +Oper (Op1570, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 2, GN, SMB, 24) +Oper (Op1578, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 2, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1580, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 2, GN, SMB, 16) +Oper (Op1590, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 2, GN, SMB, 20) +Oper (Op1598, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 2, GN, SMB, 20) +Oper (Op15a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 2, GN, SMB, 20) +Oper (Op15a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 2, GN, SMB, 24) +Oper (Op15b0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 2, GN, SMB, 24) +Oper (Op15b8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 2, GN, SMB, (cycles+21)&0xfffffffc) + +Oper (Op1600, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 3, GN, SRB, 4) +Oper (Op1610, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 3, GN, SRB, 8) +Oper (Op1618, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 3, GN, SRB, 8) +Oper (Op1620, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 3, GN, SRB, 12) +Oper (Op1628, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 3, GN, SRB, 12) +Oper (Op1630, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 3, GN, SRB, 16) +Oper (Op1638, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 3, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1680, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 3, GN, SMB, 8) +Oper (Op1690, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 3, GN, SMB, 12) +Oper (Op1698, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 3, GN, SMB, 12) +Oper (Op16a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 3, GN, SMB, 16) +Oper (Op16a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 3, GN, SMB, 16) +Oper (Op16b0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 3, GN, SMB, 20) +Oper (Op16b8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 3, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op16c0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB, 3, GN, SMB, 8) +Oper (Op16d0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB, 3, GN, SMB, 12) +Oper (Op16d8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB, 3, GN, SMB, 12) +Oper (Op16e0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB, 3, GN, SMB, 16) +Oper (Op16e8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB, 3, GN, SMB, 16) +Oper (Op16f0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB, 3, GN, SMB, 20) +Oper (Op16f8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB, 3, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1700, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB, 3, GN, SMB, 12) +Oper (Op1710, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB, 3, GN, SMB, 16) +Oper (Op1718, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB, 3, GN, SMB, 16) +Oper (Op1720, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB, 3, GN, SMB, 16) +Oper (Op1728, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB, 3, GN, SMB, 20) +Oper (Op1730, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB, 3, GN, SMB, 20) +Oper (Op1738, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB, 3, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1740, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 3, GN, SMB, 12) +Oper (Op1750, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 3, GN, SMB, 16) +Oper (Op1758, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 3, GN, SMB, 16) +Oper (Op1760, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 3, GN, SMB, 20) +Oper (Op1768, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 3, GN, SMB, 20) +Oper (Op1770, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 3, GN, SMB, 24) +Oper (Op1778, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 3, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1780, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 3, GN, SMB, 16) +Oper (Op1790, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 3, GN, SMB, 20) +Oper (Op1798, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 3, GN, SMB, 20) +Oper (Op17a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 3, GN, SMB, 20) +Oper (Op17a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 3, GN, SMB, 24) +Oper (Op17b0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 3, GN, SMB, 24) +Oper (Op17b8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 3, GN, SMB, (cycles+21)&0xfffffffc) + +Oper (Op1800, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 4, GN, SRB, 4) +Oper (Op1810, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 4, GN, SRB, 8) +Oper (Op1818, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 4, GN, SRB, 8) +Oper (Op1820, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 4, GN, SRB, 12) +Oper (Op1828, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 4, GN, SRB, 12) +Oper (Op1830, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 4, GN, SRB, 16) +Oper (Op1838, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 4, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1880, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 4, GN, SMB, 8) +Oper (Op1890, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 4, GN, SMB, 12) +Oper (Op1898, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 4, GN, SMB, 12) +Oper (Op18a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 4, GN, SMB, 16) +Oper (Op18a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 4, GN, SMB, 16) +Oper (Op18b0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 4, GN, SMB, 20) +Oper (Op18b8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 4, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op18c0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB, 4, GN, SMB, 8) +Oper (Op18d0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB, 4, GN, SMB, 12) +Oper (Op18d8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB, 4, GN, SMB, 12) +Oper (Op18e0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB, 4, GN, SMB, 16) +Oper (Op18e8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB, 4, GN, SMB, 16) +Oper (Op18f0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB, 4, GN, SMB, 20) +Oper (Op18f8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB, 4, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1900, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB, 4, GN, SMB, 12) +Oper (Op1910, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB, 4, GN, SMB, 16) +Oper (Op1918, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB, 4, GN, SMB, 16) +Oper (Op1920, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB, 4, GN, SMB, 16) +Oper (Op1928, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB, 4, GN, SMB, 20) +Oper (Op1930, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB, 4, GN, SMB, 20) +Oper (Op1938, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB, 4, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1940, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 4, GN, SMB, 12) +Oper (Op1950, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 4, GN, SMB, 16) +Oper (Op1958, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 4, GN, SMB, 16) +Oper (Op1960, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 4, GN, SMB, 20) +Oper (Op1968, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 4, GN, SMB, 20) +Oper (Op1970, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 4, GN, SMB, 24) +Oper (Op1978, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 4, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1980, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 4, GN, SMB, 16) +Oper (Op1990, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 4, GN, SMB, 20) +Oper (Op1998, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 4, GN, SMB, 20) +Oper (Op19a0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 4, GN, SMB, 20) +Oper (Op19a8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 4, GN, SMB, 24) +Oper (Op19b0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 4, GN, SMB, 24) +Oper (Op19b8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 4, GN, SMB, (cycles+21)&0xfffffffc) + +Oper (Op1a00, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 5, GN, SRB, 4) +Oper (Op1a10, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 5, GN, SRB, 8) +Oper (Op1a18, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 5, GN, SRB, 8) +Oper (Op1a20, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 5, GN, SRB, 12) +Oper (Op1a28, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 5, GN, SRB, 12) +Oper (Op1a30, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 5, GN, SRB, 16) +Oper (Op1a38, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 5, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1a80, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 5, GN, SMB, 8) +Oper (Op1a90, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 5, GN, SMB, 12) +Oper (Op1a98, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 5, GN, SMB, 12) +Oper (Op1aa0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 5, GN, SMB, 16) +Oper (Op1aa8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 5, GN, SMB, 16) +Oper (Op1ab0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 5, GN, SMB, 20) +Oper (Op1ab8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 5, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1ac0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB, 5, GN, SMB, 8) +Oper (Op1ad0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB, 5, GN, SMB, 12) +Oper (Op1ad8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB, 5, GN, SMB, 12) +Oper (Op1ae0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB, 5, GN, SMB, 16) +Oper (Op1ae8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB, 5, GN, SMB, 16) +Oper (Op1af0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB, 5, GN, SMB, 20) +Oper (Op1af8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB, 5, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1b00, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB, 5, GN, SMB, 12) +Oper (Op1b10, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB, 5, GN, SMB, 16) +Oper (Op1b18, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB, 5, GN, SMB, 16) +Oper (Op1b20, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB, 5, GN, SMB, 16) +Oper (Op1b28, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB, 5, GN, SMB, 20) +Oper (Op1b30, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB, 5, GN, SMB, 20) +Oper (Op1b38, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB, 5, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1b40, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 5, GN, SMB, 12) +Oper (Op1b50, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 5, GN, SMB, 16) +Oper (Op1b58, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 5, GN, SMB, 16) +Oper (Op1b60, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 5, GN, SMB, 20) +Oper (Op1b68, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 5, GN, SMB, 20) +Oper (Op1b70, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 5, GN, SMB, 24) +Oper (Op1b78, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 5, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1b80, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 5, GN, SMB, 16) +Oper (Op1b90, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 5, GN, SMB, 20) +Oper (Op1b98, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 5, GN, SMB, 20) +Oper (Op1ba0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 5, GN, SMB, 20) +Oper (Op1ba8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 5, GN, SMB, 24) +Oper (Op1bb0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 5, GN, SMB, 24) +Oper (Op1bb8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 5, GN, SMB, (cycles+21)&0xfffffffc) + +Oper (Op1c00, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 6, GN, SRB, 4) +Oper (Op1c10, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 6, GN, SRB, 8) +Oper (Op1c18, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 6, GN, SRB, 8) +Oper (Op1c20, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 6, GN, SRB, 12) +Oper (Op1c28, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 6, GN, SRB, 12) +Oper (Op1c30, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 6, GN, SRB, 16) +Oper (Op1c38, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 6, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1c80, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 6, GN, SMB, 8) +Oper (Op1c90, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 6, GN, SMB, 12) +Oper (Op1c98, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 6, GN, SMB, 12) +Oper (Op1ca0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 6, GN, SMB, 16) +Oper (Op1ca8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 6, GN, SMB, 16) +Oper (Op1cb0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 6, GN, SMB, 20) +Oper (Op1cb8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 6, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1cc0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB, 6, GN, SMB, 8) +Oper (Op1cd0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB, 6, GN, SMB, 12) +Oper (Op1cd8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB, 6, GN, SMB, 12) +Oper (Op1ce0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB, 6, GN, SMB, 16) +Oper (Op1ce8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB, 6, GN, SMB, 16) +Oper (Op1cf0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB, 6, GN, SMB, 20) +Oper (Op1cf8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB, 6, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1d00, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB, 6, GN, SMB, 12) +Oper (Op1d10, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB, 6, GN, SMB, 16) +Oper (Op1d18, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB, 6, GN, SMB, 16) +Oper (Op1d20, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB, 6, GN, SMB, 16) +Oper (Op1d28, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB, 6, GN, SMB, 20) +Oper (Op1d30, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB, 6, GN, SMB, 20) +Oper (Op1d38, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB, 6, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1d40, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 6, GN, SMB, 12) +Oper (Op1d50, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 6, GN, SMB, 16) +Oper (Op1d58, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 6, GN, SMB, 16) +Oper (Op1d60, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 6, GN, SMB, 20) +Oper (Op1d68, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 6, GN, SMB, 20) +Oper (Op1d70, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 6, GN, SMB, 24) +Oper (Op1d78, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 6, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1d80, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 6, GN, SMB, 16) +Oper (Op1d90, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 6, GN, SMB, 20) +Oper (Op1d98, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 6, GN, SMB, 20) +Oper (Op1da0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 6, GN, SMB, 20) +Oper (Op1da8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 6, GN, SMB, 24) +Oper (Op1db0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 6, GN, SMB, 24) +Oper (Op1db8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 6, GN, SMB, (cycles+21)&0xfffffffc) + +Oper (Op1e00, DoMoveB, DB, SdB, ins7, DB, DR, Cd, 7, GN, SRB, 4) +Oper (Op1e10, DoMoveB, DB, SainB, ins7, DB, DR, Cd, 7, GN, SRB, 8) +Oper (Op1e18, DoMoveB, DB, SaipB, ins7, DB, DR, Cd, 7, GN, SRB, 8) +Oper (Op1e20, DoMoveB, DB, SmaiB, ins7, DB, DR, Cd, 7, GN, SRB, 12) +Oper (Op1e28, DoMoveB, DB, SdaiB, ins7, DB, DR, Cd, 7, GN, SRB, 12) +Oper (Op1e30, DoMoveB, DB, SaixB, ins7, DB, DR, Cd, 7, GN, SRB, 16) +Oper (Op1e38, DoMoveB, DB, SearB, ins7, DB, DR, Cd, 7, GN, SRB, (cycles+11)&0xfffffffc) +Oper (Op1e80, DoMoveB, DB, SdB, ins7, DB, DA, Cain, 7, GN, SMB, 8) +Oper (Op1e90, DoMoveB, DB, SainB, ins7, DB, DA, Cain, 7, GN, SMB, 12) +Oper (Op1e98, DoMoveB, DB, SaipB, ins7, DB, DA, Cain, 7, GN, SMB, 12) +Oper (Op1ea0, DoMoveB, DB, SmaiB, ins7, DB, DA, Cain, 7, GN, SMB, 16) +Oper (Op1ea8, DoMoveB, DB, SdaiB, ins7, DB, DA, Cain, 7, GN, SMB, 16) +Oper (Op1eb0, DoMoveB, DB, SaixB, ins7, DB, DA, Cain, 7, GN, SMB, 20) +Oper (Op1eb8, DoMoveB, DB, SearB, ins7, DB, DA, Cain, 7, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1ec0, DoMoveB, DB, SdB, ins7, DB, DA, CaipB15, 7, GN, SMB, 8) +Oper (Op1ed0, DoMoveB, DB, SainB, ins7, DB, DA, CaipB15, 7, GN, SMB, 12) +Oper (Op1ed8, DoMoveB, DB, SaipB, ins7, DB, DA, CaipB15, 7, GN, SMB, 12) +Oper (Op1ee0, DoMoveB, DB, SmaiB, ins7, DB, DA, CaipB15, 7, GN, SMB, 16) +Oper (Op1ee8, DoMoveB, DB, SdaiB, ins7, DB, DA, CaipB15, 7, GN, SMB, 16) +Oper (Op1ef0, DoMoveB, DB, SaixB, ins7, DB, DA, CaipB15, 7, GN, SMB, 20) +Oper (Op1ef8, DoMoveB, DB, SearB, ins7, DB, DA, CaipB15, 7, GN, SMB, (cycles+15)&0xfffffffc) +Oper (Op1f00, DoMoveB, DB, SdB, ins7, DB, DA, CmaiB15, 7, GN, SMB, 12) +Oper (Op1f10, DoMoveB, DB, SainB, ins7, DB, DA, CmaiB15, 7, GN, SMB, 16) +Oper (Op1f18, DoMoveB, DB, SaipB, ins7, DB, DA, CmaiB15, 7, GN, SMB, 16) +Oper (Op1f20, DoMoveB, DB, SmaiB, ins7, DB, DA, CmaiB15, 7, GN, SMB, 16) +Oper (Op1f28, DoMoveB, DB, SdaiB, ins7, DB, DA, CmaiB15, 7, GN, SMB, 20) +Oper (Op1f30, DoMoveB, DB, SaixB, ins7, DB, DA, CmaiB15, 7, GN, SMB, 20) +Oper (Op1f38, DoMoveB, DB, SearB, ins7, DB, DA, CmaiB15, 7, GN, SMB, (cycles+17)&0xfffffffc) +Oper (Op1f40, DoMoveB, DB, SdB, ins7, DB, DA, Fdai, 7, GN, SMB, 12) +Oper (Op1f50, DoMoveB, DB, SainB, ins7, DB, DA, Fdai, 7, GN, SMB, 16) +Oper (Op1f58, DoMoveB, DB, SaipB, ins7, DB, DA, Fdai, 7, GN, SMB, 16) +Oper (Op1f60, DoMoveB, DB, SmaiB, ins7, DB, DA, Fdai, 7, GN, SMB, 20) +Oper (Op1f68, DoMoveB, DB, SdaiB, ins7, DB, DA, Cdai, 7, GN, SMB, 20) +Oper (Op1f70, DoMoveB, DB, SaixB, ins7, DB, DA, Cdai, 7, GN, SMB, 24) +Oper (Op1f78, DoMoveB, DB, SearB, ins7, DB, DA, Cdai, 7, GN, SMB, (cycles+19)&0xfffffffc) +Oper (Op1f80, DoMoveB, DB, SdB, ins7, DB, DA, Faix, 7, GN, SMB, 16) +Oper (Op1f90, DoMoveB, DB, SainB, ins7, DB, DA, Faix, 7, GN, SMB, 20) +Oper (Op1f98, DoMoveB, DB, SaipB, ins7, DB, DA, Faix, 7, GN, SMB, 20) +Oper (Op1fa0, DoMoveB, DB, SmaiB, ins7, DB, DA, Faix, 7, GN, SMB, 20) +Oper (Op1fa8, DoMoveB, DB, SdaiB, ins7, DB, DA, Caix, 7, GN, SMB, 24) +Oper (Op1fb0, DoMoveB, DB, SaixB, ins7, DB, DA, Caix, 7, GN, SMB, 24) +Oper (Op1fb8, DoMoveB, DB, SearB, ins7, DB, DA, Caix, 7, GN, SMB, (cycles+21)&0xfffffffc) + +Oper (Op2000, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 0, GN, SRL, 4) +Oper (Op2008, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 0, GN, SRL, 4) +Oper (Op2010, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 0, GN, SRL, 12) +Oper (Op2018, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 0, GN, SRL, 12) +Oper (Op2020, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 0, GN, SRL, 16) +Oper (Op2028, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 0, GN, SRL, 16) +Oper (Op2030, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 0, GN, SRL, 20) +Oper (Op2038, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 0, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2040, DoMovea, DL, SdL, ins7, DL, DR, Ca, 0, GN, SRL, 4) +Oper (Op2048, DoMovea, DL, SaL, ins7, DL, DR, Ca, 0, GN, SRL, 4) +Oper (Op2050, DoMovea, DL, SainL, ins7, DL, DR, Ca, 0, GN, SRL, 12) +Oper (Op2058, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 0, GN, SRL, 12) +Oper (Op2060, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 0, GN, SRL, 16) +Oper (Op2068, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 0, GN, SRL, 16) +Oper (Op2070, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 0, GN, SRL, 20) +Oper (Op2078, DoMovea, DL, SearL, ins7, DL, DR, Ca, 0, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2080, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 0, GN, SML, 12) +Oper (Op2088, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 0, GN, SML, 12) +Oper (Op2090, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 0, GN, SML, 20) +Oper (Op2098, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 0, GN, SML, 20) +Oper (Op20a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 0, GN, SML, 24) +Oper (Op20a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 0, GN, SML, 24) +Oper (Op20b0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 0, GN, SML, 28) +Oper (Op20b8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 0, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op20c0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 0, GN, SML, 12) +Oper (Op20c8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 0, GN, SML, 12) +Oper (Op20d0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 0, GN, SML, 20) +Oper (Op20d8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 0, GN, SML, 20) +Oper (Op20e0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 0, GN, SML, 24) +Oper (Op20e8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 0, GN, SML, 24) +Oper (Op20f0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 0, GN, SML, 28) +Oper (Op20f8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 0, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2100, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 0, GN, SML, 16) +Oper (Op2108, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 0, GN, SML, 16) +Oper (Op2110, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 0, GN, SML, 24) +Oper (Op2118, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 0, GN, SML, 24) +Oper (Op2120, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 0, GN, SML, 24) +Oper (Op2128, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 0, GN, SML, 28) +Oper (Op2130, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 0, GN, SML, 28) +Oper (Op2138, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 0, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2140, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 0, GN, SML, 16) +Oper (Op2148, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 0, GN, SML, 16) +Oper (Op2150, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 0, GN, SML, 24) +Oper (Op2158, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 0, GN, SML, 24) +Oper (Op2160, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 0, GN, SML, 28) +Oper (Op2168, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 0, GN, SML, 28) +Oper (Op2170, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 0, GN, SML, 32) +Oper (Op2178, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 0, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2180, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 0, GN, SML, 20) +Oper (Op2188, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 0, GN, SML, 20) +Oper (Op2190, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 0, GN, SML, 28) +Oper (Op2198, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 0, GN, SML, 28) +Oper (Op21a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 0, GN, SML, 28) +Oper (Op21a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 0, GN, SML, 32) +Oper (Op21b0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 0, GN, SML, 32) +Oper (Op21b8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 0, GN, SML, (cycles+29)&0xfffffffc) +Oper (Op21c0, DoMoveL, DL, SdL, ins7, DL, DA, Feaw, 0, GN, SML, 16) +Oper (Op21c8, DoMoveL, DL, SaL, ins7, DL, DA, Feaw, 0, GN, SML, 16) +Oper (Op21d0, DoMoveL, DL, SainL, ins7, DL, DA, Feaw, 0, GN, SML, 24) +Oper (Op21d8, DoMoveL, DL, SaipL, ins7, DL, DA, Feaw, 0, GN, SML, 24) +Oper (Op21e0, DoMoveL, DL, SmaiL, ins7, DL, DA, Feaw, 0, GN, SML, 28) +Oper (Op21e8, DoMoveL, DL, SdaiL, ins7, DL, DA, Ceaw, 0, GN, SML, 28) +Oper (Op21f0, DoMoveL, DL, SaixL, ins7, DL, DA, Ceaw, 0, GN, SML, 32) +Oper (Op21f8, DoMoveL, DL, SearL, ins7, DL, DA, Ceaw, 0, GN, SML, (cycles+27)&0xfffffffc) + +Oper (Op2200, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 1, GN, SRL, 4) +Oper (Op2208, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 1, GN, SRL, 4) +Oper (Op2210, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 1, GN, SRL, 12) +Oper (Op2218, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 1, GN, SRL, 12) +Oper (Op2220, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 1, GN, SRL, 16) +Oper (Op2228, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 1, GN, SRL, 16) +Oper (Op2230, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 1, GN, SRL, 20) +Oper (Op2238, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 1, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2240, DoMovea, DL, SdL, ins7, DL, DR, Ca, 1, GN, SRL, 4) +Oper (Op2248, DoMovea, DL, SaL, ins7, DL, DR, Ca, 1, GN, SRL, 4) +Oper (Op2250, DoMovea, DL, SainL, ins7, DL, DR, Ca, 1, GN, SRL, 12) +Oper (Op2258, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 1, GN, SRL, 12) +Oper (Op2260, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 1, GN, SRL, 16) +Oper (Op2268, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 1, GN, SRL, 16) +Oper (Op2270, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 1, GN, SRL, 20) +Oper (Op2278, DoMovea, DL, SearL, ins7, DL, DR, Ca, 1, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2280, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 1, GN, SML, 12) +Oper (Op2288, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 1, GN, SML, 12) +Oper (Op2290, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 1, GN, SML, 20) +Oper (Op2298, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 1, GN, SML, 20) +Oper (Op22a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 1, GN, SML, 24) +Oper (Op22a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 1, GN, SML, 24) +Oper (Op22b0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 1, GN, SML, 28) +Oper (Op22b8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 1, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op22c0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 1, GN, SML, 12) +Oper (Op22c8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 1, GN, SML, 12) +Oper (Op22d0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 1, GN, SML, 20) +Oper (Op22d8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 1, GN, SML, 20) +Oper (Op22e0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 1, GN, SML, 24) +Oper (Op22e8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 1, GN, SML, 24) +Oper (Op22f0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 1, GN, SML, 28) +Oper (Op22f8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 1, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2300, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 1, GN, SML, 16) +Oper (Op2308, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 1, GN, SML, 16) +Oper (Op2310, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 1, GN, SML, 24) +Oper (Op2318, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 1, GN, SML, 24) +Oper (Op2320, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 1, GN, SML, 24) +Oper (Op2328, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 1, GN, SML, 28) +Oper (Op2330, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 1, GN, SML, 28) +Oper (Op2338, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 1, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2340, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 1, GN, SML, 16) +Oper (Op2348, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 1, GN, SML, 16) +Oper (Op2350, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 1, GN, SML, 24) +Oper (Op2358, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 1, GN, SML, 24) +Oper (Op2360, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 1, GN, SML, 28) +Oper (Op2368, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 1, GN, SML, 28) +Oper (Op2370, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 1, GN, SML, 32) +Oper (Op2378, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 1, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2380, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 1, GN, SML, 20) +Oper (Op2388, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 1, GN, SML, 20) +Oper (Op2390, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 1, GN, SML, 28) +Oper (Op2398, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 1, GN, SML, 28) +Oper (Op23a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 1, GN, SML, 28) +Oper (Op23a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 1, GN, SML, 32) +Oper (Op23b0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 1, GN, SML, 32) +Oper (Op23b8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 1, GN, SML, (cycles+29)&0xfffffffc) +Oper (Op23c0, DoMoveL, DL, SdL, ins7, DL, DA, Feaw, 1, GN, SML, 20) +Oper (Op23c8, DoMoveL, DL, SaL, ins7, DL, DA, Feaw, 1, GN, SML, 20) +Oper (Op23d0, DoMoveL, DL, SainL, ins7, DL, DA, Feaw, 1, GN, SML, 28) +Oper (Op23d8, DoMoveL, DL, SaipL, ins7, DL, DA, Feaw, 1, GN, SML, 28) +Oper (Op23e0, DoMoveL, DL, SmaiL, ins7, DL, DA, Feaw, 1, GN, SML, 32) +Oper (Op23e8, DoMoveL, DL, SdaiL, ins7, DL, DA, Ceaw, 1, GN, SML, 32) +Oper (Op23f0, DoMoveL, DL, SaixL, ins7, DL, DA, Ceaw, 1, GN, SML, 36) +Oper (Op23f8, DoMoveL, DL, SearL, ins7, DL, DA, Ceaw, 1, GN, SML, (cycles+31)&0xfffffffc) + +Oper (Op2400, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 2, GN, SRL, 4) +Oper (Op2408, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 2, GN, SRL, 4) +Oper (Op2410, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 2, GN, SRL, 12) +Oper (Op2418, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 2, GN, SRL, 12) +Oper (Op2420, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 2, GN, SRL, 16) +Oper (Op2428, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 2, GN, SRL, 16) +Oper (Op2430, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 2, GN, SRL, 20) +Oper (Op2438, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 2, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2440, DoMovea, DL, SdL, ins7, DL, DR, Ca, 2, GN, SRL, 4) +Oper (Op2448, DoMovea, DL, SaL, ins7, DL, DR, Ca, 2, GN, SRL, 4) +Oper (Op2450, DoMovea, DL, SainL, ins7, DL, DR, Ca, 2, GN, SRL, 12) +Oper (Op2458, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 2, GN, SRL, 12) +Oper (Op2460, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 2, GN, SRL, 16) +Oper (Op2468, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 2, GN, SRL, 16) +Oper (Op2470, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 2, GN, SRL, 20) +Oper (Op2478, DoMovea, DL, SearL, ins7, DL, DR, Ca, 2, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2480, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 2, GN, SML, 12) +Oper (Op2488, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 2, GN, SML, 12) +Oper (Op2490, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 2, GN, SML, 20) +Oper (Op2498, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 2, GN, SML, 20) +Oper (Op24a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 2, GN, SML, 24) +Oper (Op24a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 2, GN, SML, 24) +Oper (Op24b0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 2, GN, SML, 28) +Oper (Op24b8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 2, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op24c0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 2, GN, SML, 12) +Oper (Op24c8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 2, GN, SML, 12) +Oper (Op24d0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 2, GN, SML, 20) +Oper (Op24d8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 2, GN, SML, 20) +Oper (Op24e0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 2, GN, SML, 24) +Oper (Op24e8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 2, GN, SML, 24) +Oper (Op24f0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 2, GN, SML, 28) +Oper (Op24f8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 2, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2500, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 2, GN, SML, 16) +Oper (Op2508, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 2, GN, SML, 16) +Oper (Op2510, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 2, GN, SML, 24) +Oper (Op2518, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 2, GN, SML, 24) +Oper (Op2520, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 2, GN, SML, 24) +Oper (Op2528, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 2, GN, SML, 28) +Oper (Op2530, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 2, GN, SML, 28) +Oper (Op2538, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 2, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2540, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 2, GN, SML, 16) +Oper (Op2548, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 2, GN, SML, 16) +Oper (Op2550, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 2, GN, SML, 24) +Oper (Op2558, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 2, GN, SML, 24) +Oper (Op2560, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 2, GN, SML, 28) +Oper (Op2568, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 2, GN, SML, 28) +Oper (Op2570, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 2, GN, SML, 32) +Oper (Op2578, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 2, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2580, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 2, GN, SML, 20) +Oper (Op2588, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 2, GN, SML, 20) +Oper (Op2590, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 2, GN, SML, 28) +Oper (Op2598, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 2, GN, SML, 28) +Oper (Op25a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 2, GN, SML, 28) +Oper (Op25a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 2, GN, SML, 32) +Oper (Op25b0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 2, GN, SML, 32) +Oper (Op25b8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 2, GN, SML, (cycles+29)&0xfffffffc) + +Oper (Op2600, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 3, GN, SRL, 4) +Oper (Op2608, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 3, GN, SRL, 4) +Oper (Op2610, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 3, GN, SRL, 12) +Oper (Op2618, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 3, GN, SRL, 12) +Oper (Op2620, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 3, GN, SRL, 16) +Oper (Op2628, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 3, GN, SRL, 16) +Oper (Op2630, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 3, GN, SRL, 20) +Oper (Op2638, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 3, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2640, DoMovea, DL, SdL, ins7, DL, DR, Ca, 3, GN, SRL, 4) +Oper (Op2648, DoMovea, DL, SaL, ins7, DL, DR, Ca, 3, GN, SRL, 4) +Oper (Op2650, DoMovea, DL, SainL, ins7, DL, DR, Ca, 3, GN, SRL, 12) +Oper (Op2658, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 3, GN, SRL, 12) +Oper (Op2660, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 3, GN, SRL, 16) +Oper (Op2668, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 3, GN, SRL, 16) +Oper (Op2670, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 3, GN, SRL, 20) +Oper (Op2678, DoMovea, DL, SearL, ins7, DL, DR, Ca, 3, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2680, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 3, GN, SML, 12) +Oper (Op2688, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 3, GN, SML, 12) +Oper (Op2690, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 3, GN, SML, 20) +Oper (Op2698, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 3, GN, SML, 20) +Oper (Op26a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 3, GN, SML, 24) +Oper (Op26a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 3, GN, SML, 24) +Oper (Op26b0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 3, GN, SML, 28) +Oper (Op26b8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 3, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op26c0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 3, GN, SML, 12) +Oper (Op26c8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 3, GN, SML, 12) +Oper (Op26d0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 3, GN, SML, 20) +Oper (Op26d8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 3, GN, SML, 20) +Oper (Op26e0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 3, GN, SML, 24) +Oper (Op26e8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 3, GN, SML, 24) +Oper (Op26f0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 3, GN, SML, 28) +Oper (Op26f8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 3, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2700, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 3, GN, SML, 16) +Oper (Op2708, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 3, GN, SML, 16) +Oper (Op2710, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 3, GN, SML, 24) +Oper (Op2718, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 3, GN, SML, 24) +Oper (Op2720, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 3, GN, SML, 24) +Oper (Op2728, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 3, GN, SML, 28) +Oper (Op2730, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 3, GN, SML, 28) +Oper (Op2738, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 3, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2740, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 3, GN, SML, 16) +Oper (Op2748, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 3, GN, SML, 16) +Oper (Op2750, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 3, GN, SML, 24) +Oper (Op2758, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 3, GN, SML, 24) +Oper (Op2760, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 3, GN, SML, 28) +Oper (Op2768, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 3, GN, SML, 28) +Oper (Op2770, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 3, GN, SML, 32) +Oper (Op2778, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 3, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2780, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 3, GN, SML, 20) +Oper (Op2788, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 3, GN, SML, 20) +Oper (Op2790, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 3, GN, SML, 28) +Oper (Op2798, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 3, GN, SML, 28) +Oper (Op27a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 3, GN, SML, 28) +Oper (Op27a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 3, GN, SML, 32) +Oper (Op27b0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 3, GN, SML, 32) +Oper (Op27b8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 3, GN, SML, (cycles+29)&0xfffffffc) + +Oper (Op2800, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 4, GN, SRL, 4) +Oper (Op2808, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 4, GN, SRL, 4) +Oper (Op2810, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 4, GN, SRL, 12) +Oper (Op2818, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 4, GN, SRL, 12) +Oper (Op2820, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 4, GN, SRL, 16) +Oper (Op2828, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 4, GN, SRL, 16) +Oper (Op2830, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 4, GN, SRL, 20) +Oper (Op2838, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 4, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2840, DoMovea, DL, SdL, ins7, DL, DR, Ca, 4, GN, SRL, 4) +Oper (Op2848, DoMovea, DL, SaL, ins7, DL, DR, Ca, 4, GN, SRL, 4) +Oper (Op2850, DoMovea, DL, SainL, ins7, DL, DR, Ca, 4, GN, SRL, 12) +Oper (Op2858, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 4, GN, SRL, 12) +Oper (Op2860, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 4, GN, SRL, 16) +Oper (Op2868, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 4, GN, SRL, 16) +Oper (Op2870, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 4, GN, SRL, 20) +Oper (Op2878, DoMovea, DL, SearL, ins7, DL, DR, Ca, 4, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2880, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 4, GN, SML, 12) +Oper (Op2888, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 4, GN, SML, 12) +Oper (Op2890, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 4, GN, SML, 20) +Oper (Op2898, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 4, GN, SML, 20) +Oper (Op28a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 4, GN, SML, 24) +Oper (Op28a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 4, GN, SML, 24) +Oper (Op28b0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 4, GN, SML, 28) +Oper (Op28b8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 4, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op28c0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 4, GN, SML, 12) +Oper (Op28c8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 4, GN, SML, 12) +Oper (Op28d0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 4, GN, SML, 20) +Oper (Op28d8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 4, GN, SML, 20) +Oper (Op28e0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 4, GN, SML, 24) +Oper (Op28e8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 4, GN, SML, 24) +Oper (Op28f0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 4, GN, SML, 28) +Oper (Op28f8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 4, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2900, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 4, GN, SML, 16) +Oper (Op2908, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 4, GN, SML, 16) +Oper (Op2910, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 4, GN, SML, 24) +Oper (Op2918, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 4, GN, SML, 24) +Oper (Op2920, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 4, GN, SML, 24) +Oper (Op2928, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 4, GN, SML, 28) +Oper (Op2930, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 4, GN, SML, 28) +Oper (Op2938, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 4, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2940, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 4, GN, SML, 16) +Oper (Op2948, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 4, GN, SML, 16) +Oper (Op2950, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 4, GN, SML, 24) +Oper (Op2958, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 4, GN, SML, 24) +Oper (Op2960, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 4, GN, SML, 28) +Oper (Op2968, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 4, GN, SML, 28) +Oper (Op2970, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 4, GN, SML, 32) +Oper (Op2978, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 4, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2980, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 4, GN, SML, 20) +Oper (Op2988, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 4, GN, SML, 20) +Oper (Op2990, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 4, GN, SML, 28) +Oper (Op2998, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 4, GN, SML, 28) +Oper (Op29a0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 4, GN, SML, 28) +Oper (Op29a8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 4, GN, SML, 32) +Oper (Op29b0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 4, GN, SML, 32) +Oper (Op29b8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 4, GN, SML, (cycles+29)&0xfffffffc) + +Oper (Op2a00, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 5, GN, SRL, 4) +Oper (Op2a08, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 5, GN, SRL, 4) +Oper (Op2a10, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 5, GN, SRL, 12) +Oper (Op2a18, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 5, GN, SRL, 12) +Oper (Op2a20, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 5, GN, SRL, 16) +Oper (Op2a28, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 5, GN, SRL, 16) +Oper (Op2a30, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 5, GN, SRL, 20) +Oper (Op2a38, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 5, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2a40, DoMovea, DL, SdL, ins7, DL, DR, Ca, 5, GN, SRL, 4) +Oper (Op2a48, DoMovea, DL, SaL, ins7, DL, DR, Ca, 5, GN, SRL, 4) +Oper (Op2a50, DoMovea, DL, SainL, ins7, DL, DR, Ca, 5, GN, SRL, 12) +Oper (Op2a58, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 5, GN, SRL, 12) +Oper (Op2a60, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 5, GN, SRL, 16) +Oper (Op2a68, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 5, GN, SRL, 16) +Oper (Op2a70, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 5, GN, SRL, 20) +Oper (Op2a78, DoMovea, DL, SearL, ins7, DL, DR, Ca, 5, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2a80, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 5, GN, SML, 12) +Oper (Op2a88, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 5, GN, SML, 12) +Oper (Op2a90, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 5, GN, SML, 20) +Oper (Op2a98, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 5, GN, SML, 20) +Oper (Op2aa0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 5, GN, SML, 24) +Oper (Op2aa8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 5, GN, SML, 24) +Oper (Op2ab0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 5, GN, SML, 28) +Oper (Op2ab8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 5, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2ac0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 5, GN, SML, 12) +Oper (Op2ac8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 5, GN, SML, 12) +Oper (Op2ad0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 5, GN, SML, 20) +Oper (Op2ad8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 5, GN, SML, 20) +Oper (Op2ae0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 5, GN, SML, 24) +Oper (Op2ae8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 5, GN, SML, 24) +Oper (Op2af0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 5, GN, SML, 28) +Oper (Op2af8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 5, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2b00, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 5, GN, SML, 16) +Oper (Op2b08, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 5, GN, SML, 16) +Oper (Op2b10, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 5, GN, SML, 24) +Oper (Op2b18, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 5, GN, SML, 24) +Oper (Op2b20, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 5, GN, SML, 24) +Oper (Op2b28, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 5, GN, SML, 28) +Oper (Op2b30, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 5, GN, SML, 28) +Oper (Op2b38, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 5, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2b40, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 5, GN, SML, 16) +Oper (Op2b48, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 5, GN, SML, 16) +Oper (Op2b50, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 5, GN, SML, 24) +Oper (Op2b58, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 5, GN, SML, 24) +Oper (Op2b60, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 5, GN, SML, 28) +Oper (Op2b68, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 5, GN, SML, 28) +Oper (Op2b70, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 5, GN, SML, 32) +Oper (Op2b78, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 5, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2b80, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 5, GN, SML, 20) +Oper (Op2b88, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 5, GN, SML, 20) +Oper (Op2b90, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 5, GN, SML, 28) +Oper (Op2b98, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 5, GN, SML, 28) +Oper (Op2ba0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 5, GN, SML, 28) +Oper (Op2ba8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 5, GN, SML, 32) +Oper (Op2bb0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 5, GN, SML, 32) +Oper (Op2bb8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 5, GN, SML, (cycles+29)&0xfffffffc) + +Oper (Op2c00, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 6, GN, SRL, 4) +Oper (Op2c08, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 6, GN, SRL, 4) +Oper (Op2c10, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 6, GN, SRL, 12) +Oper (Op2c18, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 6, GN, SRL, 12) +Oper (Op2c20, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 6, GN, SRL, 16) +Oper (Op2c28, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 6, GN, SRL, 16) +Oper (Op2c30, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 6, GN, SRL, 20) +Oper (Op2c38, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 6, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2c40, DoMovea, DL, SdL, ins7, DL, DR, Ca, 6, GN, SRL, 4) +Oper (Op2c48, DoMovea, DL, SaL, ins7, DL, DR, Ca, 6, GN, SRL, 4) +Oper (Op2c50, DoMovea, DL, SainL, ins7, DL, DR, Ca, 6, GN, SRL, 12) +Oper (Op2c58, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 6, GN, SRL, 12) +Oper (Op2c60, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 6, GN, SRL, 16) +Oper (Op2c68, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 6, GN, SRL, 16) +Oper (Op2c70, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 6, GN, SRL, 20) +Oper (Op2c78, DoMovea, DL, SearL, ins7, DL, DR, Ca, 6, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2c80, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 6, GN, SML, 12) +Oper (Op2c88, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 6, GN, SML, 12) +Oper (Op2c90, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 6, GN, SML, 20) +Oper (Op2c98, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 6, GN, SML, 20) +Oper (Op2ca0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 6, GN, SML, 24) +Oper (Op2ca8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 6, GN, SML, 24) +Oper (Op2cb0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 6, GN, SML, 28) +Oper (Op2cb8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 6, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2cc0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 6, GN, SML, 12) +Oper (Op2cc8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 6, GN, SML, 12) +Oper (Op2cd0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 6, GN, SML, 20) +Oper (Op2cd8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 6, GN, SML, 20) +Oper (Op2ce0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 6, GN, SML, 24) +Oper (Op2ce8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 6, GN, SML, 24) +Oper (Op2cf0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 6, GN, SML, 28) +Oper (Op2cf8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 6, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2d00, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 6, GN, SML, 16) +Oper (Op2d08, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 6, GN, SML, 16) +Oper (Op2d10, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 6, GN, SML, 24) +Oper (Op2d18, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 6, GN, SML, 24) +Oper (Op2d20, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 6, GN, SML, 24) +Oper (Op2d28, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 6, GN, SML, 28) +Oper (Op2d30, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 6, GN, SML, 28) +Oper (Op2d38, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 6, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2d40, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 6, GN, SML, 16) +Oper (Op2d48, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 6, GN, SML, 16) +Oper (Op2d50, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 6, GN, SML, 24) +Oper (Op2d58, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 6, GN, SML, 24) +Oper (Op2d60, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 6, GN, SML, 28) +Oper (Op2d68, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 6, GN, SML, 28) +Oper (Op2d70, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 6, GN, SML, 32) +Oper (Op2d78, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 6, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2d80, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 6, GN, SML, 20) +Oper (Op2d88, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 6, GN, SML, 20) +Oper (Op2d90, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 6, GN, SML, 28) +Oper (Op2d98, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 6, GN, SML, 28) +Oper (Op2da0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 6, GN, SML, 28) +Oper (Op2da8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 6, GN, SML, 32) +Oper (Op2db0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 6, GN, SML, 32) +Oper (Op2db8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 6, GN, SML, (cycles+29)&0xfffffffc) + +Oper (Op2e00, DoMoveL, DL, SdL, ins7, DL, DR, Cd, 7, GN, SRL, 4) +Oper (Op2e08, DoMoveL, DL, SaL, ins7, DL, DR, Cd, 7, GN, SRL, 4) +Oper (Op2e10, DoMoveL, DL, SainL, ins7, DL, DR, Cd, 7, GN, SRL, 12) +Oper (Op2e18, DoMoveL, DL, SaipL, ins7, DL, DR, Cd, 7, GN, SRL, 12) +Oper (Op2e20, DoMoveL, DL, SmaiL, ins7, DL, DR, Cd, 7, GN, SRL, 16) +Oper (Op2e28, DoMoveL, DL, SdaiL, ins7, DL, DR, Cd, 7, GN, SRL, 16) +Oper (Op2e30, DoMoveL, DL, SaixL, ins7, DL, DR, Cd, 7, GN, SRL, 20) +Oper (Op2e38, DoMoveL, DL, SearL, ins7, DL, DR, Cd, 7, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2e40, DoMovea, DL, SdL, ins7, DL, DR, Ca, 7, GN, SRL, 4) +Oper (Op2e48, DoMovea, DL, SaL, ins7, DL, DR, Ca, 7, GN, SRL, 4) +Oper (Op2e50, DoMovea, DL, SainL, ins7, DL, DR, Ca, 7, GN, SRL, 12) +Oper (Op2e58, DoMovea, DL, SaipL, ins7, DL, DR, Ca, 7, GN, SRL, 12) +Oper (Op2e60, DoMovea, DL, SmaiL, ins7, DL, DR, Ca, 7, GN, SRL, 16) +Oper (Op2e68, DoMovea, DL, SdaiL, ins7, DL, DR, Ca, 7, GN, SRL, 16) +Oper (Op2e70, DoMovea, DL, SaixL, ins7, DL, DR, Ca, 7, GN, SRL, 20) +Oper (Op2e78, DoMovea, DL, SearL, ins7, DL, DR, Ca, 7, GN, SRL, (cycles+15)&0xfffffffc) +Oper (Op2e80, DoMoveL, DL, SdL, ins7, DL, DA, Cain, 7, GN, SML, 12) +Oper (Op2e88, DoMoveL, DL, SaL, ins7, DL, DA, Cain, 7, GN, SML, 12) +Oper (Op2e90, DoMoveL, DL, SainL, ins7, DL, DA, Cain, 7, GN, SML, 20) +Oper (Op2e98, DoMoveL, DL, SaipL, ins7, DL, DA, Cain, 7, GN, SML, 20) +Oper (Op2ea0, DoMoveL, DL, SmaiL, ins7, DL, DA, Cain, 7, GN, SML, 24) +Oper (Op2ea8, DoMoveL, DL, SdaiL, ins7, DL, DA, Cain, 7, GN, SML, 24) +Oper (Op2eb0, DoMoveL, DL, SaixL, ins7, DL, DA, Cain, 7, GN, SML, 28) +Oper (Op2eb8, DoMoveL, DL, SearL, ins7, DL, DA, Cain, 7, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2ec0, DoMoveL, DL, SdL, ins7, DL, DA, CaipL, 7, GN, SML, 12) +Oper (Op2ec8, DoMoveL, DL, SaL, ins7, DL, DA, CaipL, 7, GN, SML, 12) +Oper (Op2ed0, DoMoveL, DL, SainL, ins7, DL, DA, CaipL, 7, GN, SML, 20) +Oper (Op2ed8, DoMoveL, DL, SaipL, ins7, DL, DA, CaipL, 7, GN, SML, 20) +Oper (Op2ee0, DoMoveL, DL, SmaiL, ins7, DL, DA, CaipL, 7, GN, SML, 24) +Oper (Op2ee8, DoMoveL, DL, SdaiL, ins7, DL, DA, CaipL, 7, GN, SML, 24) +Oper (Op2ef0, DoMoveL, DL, SaixL, ins7, DL, DA, CaipL, 7, GN, SML, 28) +Oper (Op2ef8, DoMoveL, DL, SearL, ins7, DL, DA, CaipL, 7, GN, SML, (cycles+23)&0xfffffffc) +Oper (Op2f00, DoMoveL, DL, SdL, ins7, DL, DA, CmaiL, 7, GN, SML, 16) +Oper (Op2f08, DoMoveL, DL, SaL, ins7, DL, DA, CmaiL, 7, GN, SML, 16) +Oper (Op2f10, DoMoveL, DL, SainL, ins7, DL, DA, CmaiL, 7, GN, SML, 24) +Oper (Op2f18, DoMoveL, DL, SaipL, ins7, DL, DA, CmaiL, 7, GN, SML, 24) +Oper (Op2f20, DoMoveL, DL, SmaiL, ins7, DL, DA, CmaiL, 7, GN, SML, 24) +Oper (Op2f28, DoMoveL, DL, SdaiL, ins7, DL, DA, CmaiL, 7, GN, SML, 28) +Oper (Op2f30, DoMoveL, DL, SaixL, ins7, DL, DA, CmaiL, 7, GN, SML, 28) +Oper (Op2f38, DoMoveL, DL, SearL, ins7, DL, DA, CmaiL, 7, GN, SML, (cycles+25)&0xfffffffc) +Oper (Op2f40, DoMoveL, DL, SdL, ins7, DL, DA, Fdai, 7, GN, SML, 16) +Oper (Op2f48, DoMoveL, DL, SaL, ins7, DL, DA, Fdai, 7, GN, SML, 16) +Oper (Op2f50, DoMoveL, DL, SainL, ins7, DL, DA, Fdai, 7, GN, SML, 24) +Oper (Op2f58, DoMoveL, DL, SaipL, ins7, DL, DA, Fdai, 7, GN, SML, 24) +Oper (Op2f60, DoMoveL, DL, SmaiL, ins7, DL, DA, Fdai, 7, GN, SML, 28) +Oper (Op2f68, DoMoveL, DL, SdaiL, ins7, DL, DA, Cdai, 7, GN, SML, 28) +Oper (Op2f70, DoMoveL, DL, SaixL, ins7, DL, DA, Cdai, 7, GN, SML, 32) +Oper (Op2f78, DoMoveL, DL, SearL, ins7, DL, DA, Cdai, 7, GN, SML, (cycles+27)&0xfffffffc) +Oper (Op2f80, DoMoveL, DL, SdL, ins7, DL, DA, Faix, 7, GN, SML, 20) +Oper (Op2f88, DoMoveL, DL, SaL, ins7, DL, DA, Faix, 7, GN, SML, 20) +Oper (Op2f90, DoMoveL, DL, SainL, ins7, DL, DA, Faix, 7, GN, SML, 28) +Oper (Op2f98, DoMoveL, DL, SaipL, ins7, DL, DA, Faix, 7, GN, SML, 28) +Oper (Op2fa0, DoMoveL, DL, SmaiL, ins7, DL, DA, Faix, 7, GN, SML, 28) +Oper (Op2fa8, DoMoveL, DL, SdaiL, ins7, DL, DA, Caix, 7, GN, SML, 32) +Oper (Op2fb0, DoMoveL, DL, SaixL, ins7, DL, DA, Caix, 7, GN, SML, 32) +Oper (Op2fb8, DoMoveL, DL, SearL, ins7, DL, DA, Caix, 7, GN, SML, (cycles+29)&0xfffffffc) + +Oper (Op3000, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 0, GN, SRW, 4) +Oper (Op3008, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 0, GN, SRW, 4) +Oper (Op3010, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 0, GN, SRW, 8) +Oper (Op3018, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 0, GN, SRW, 8) +Oper (Op3020, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 0, GN, SRW, 12) +Oper (Op3028, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 0, GN, SRW, 12) +Oper (Op3030, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 0, GN, SRW, 16) +Oper (Op3038, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 0, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3040, DoMovea, DW, SdW, ins7, DL, DR, Ca, 0, GN, SRL, 4) +Oper (Op3048, DoMovea, DW, SaW, ins7, DL, DR, Ca, 0, GN, SRL, 4) +Oper (Op3050, DoMovea, DW, SainW, ins7, DL, DR, Ca, 0, GN, SRL, 8) +Oper (Op3058, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 0, GN, SRL, 8) +Oper (Op3060, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 0, GN, SRL, 12) +Oper (Op3068, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 0, GN, SRL, 12) +Oper (Op3070, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 0, GN, SRL, 16) +Oper (Op3078, DoMovea, DW, SearW, ins7, DL, DR, Ca, 0, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3080, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 0, GN, SMW, 8) +Oper (Op3088, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 0, GN, SMW, 8) +Oper (Op3090, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 0, GN, SMW, 12) +Oper (Op3098, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 0, GN, SMW, 12) +Oper (Op30a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 0, GN, SMW, 16) +Oper (Op30a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 0, GN, SMW, 16) +Oper (Op30b0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 0, GN, SMW, 20) +Oper (Op30b8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 0, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op30c0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 0, GN, SMW, 8) +Oper (Op30c8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 0, GN, SMW, 8) +Oper (Op30d0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 0, GN, SMW, 12) +Oper (Op30d8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 0, GN, SMW, 12) +Oper (Op30e0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 0, GN, SMW, 16) +Oper (Op30e8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 0, GN, SMW, 16) +Oper (Op30f0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 0, GN, SMW, 20) +Oper (Op30f8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 0, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3100, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 0, GN, SMW, 12) +Oper (Op3108, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 0, GN, SMW, 12) +Oper (Op3110, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 0, GN, SMW, 16) +Oper (Op3118, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 0, GN, SMW, 16) +Oper (Op3120, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 0, GN, SMW, 16) +Oper (Op3128, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 0, GN, SMW, 20) +Oper (Op3130, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 0, GN, SMW, 20) +Oper (Op3138, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 0, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3140, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 0, GN, SMW, 12) +Oper (Op3148, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 0, GN, SMW, 12) +Oper (Op3150, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 0, GN, SMW, 16) +Oper (Op3158, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 0, GN, SMW, 16) +Oper (Op3160, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 0, GN, SMW, 20) +Oper (Op3168, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 0, GN, SMW, 20) +Oper (Op3170, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 0, GN, SMW, 24) +Oper (Op3178, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 0, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3180, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 0, GN, SMW, 16) +Oper (Op3188, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 0, GN, SMW, 16) +Oper (Op3190, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 0, GN, SMW, 20) +Oper (Op3198, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 0, GN, SMW, 20) +Oper (Op31a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 0, GN, SMW, 20) +Oper (Op31a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 0, GN, SMW, 24) +Oper (Op31b0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 0, GN, SMW, 24) +Oper (Op31b8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 0, GN, SMW, (cycles+21)&0xfffffffc) +Oper (Op31c0, DoMoveW, DW, SdW, ins7, DW, DA, Feaw, 0, GN, SMW, 12) +Oper (Op31c8, DoMoveW, DW, SaW, ins7, DW, DA, Feaw, 0, GN, SMW, 12) +Oper (Op31d0, DoMoveW, DW, SainW, ins7, DW, DA, Feaw, 0, GN, SMW, 16) +Oper (Op31d8, DoMoveW, DW, SaipW, ins7, DW, DA, Feaw, 0, GN, SMW, 16) +Oper (Op31e0, DoMoveW, DW, SmaiW, ins7, DW, DA, Feaw, 0, GN, SMW, 20) +Oper (Op31e8, DoMoveW, DW, SdaiW, ins7, DW, DA, Ceaw, 0, GN, SMW, 20) +Oper (Op31f0, DoMoveW, DW, SaixW, ins7, DW, DA, Ceaw, 0, GN, SMW, 24) +Oper (Op31f8, DoMoveW, DW, SearW, ins7, DW, DA, Ceaw, 0, GN, SMW, (cycles+19)&0xfffffffc) + +Oper (Op3200, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 1, GN, SRW, 4) +Oper (Op3208, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 1, GN, SRW, 4) +Oper (Op3210, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 1, GN, SRW, 8) +Oper (Op3218, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 1, GN, SRW, 8) +Oper (Op3220, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 1, GN, SRW, 12) +Oper (Op3228, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 1, GN, SRW, 12) +Oper (Op3230, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 1, GN, SRW, 16) +Oper (Op3238, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 1, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3240, DoMovea, DW, SdW, ins7, DL, DR, Ca, 1, GN, SRL, 4) +Oper (Op3248, DoMovea, DW, SaW, ins7, DL, DR, Ca, 1, GN, SRL, 4) +Oper (Op3250, DoMovea, DW, SainW, ins7, DL, DR, Ca, 1, GN, SRL, 8) +Oper (Op3258, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 1, GN, SRL, 8) +Oper (Op3260, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 1, GN, SRL, 12) +Oper (Op3268, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 1, GN, SRL, 12) +Oper (Op3270, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 1, GN, SRL, 16) +Oper (Op3278, DoMovea, DW, SearW, ins7, DL, DR, Ca, 1, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3280, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 1, GN, SMW, 8) +Oper (Op3288, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 1, GN, SMW, 8) +Oper (Op3290, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 1, GN, SMW, 12) +Oper (Op3298, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 1, GN, SMW, 12) +Oper (Op32a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 1, GN, SMW, 16) +Oper (Op32a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 1, GN, SMW, 16) +Oper (Op32b0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 1, GN, SMW, 20) +Oper (Op32b8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 1, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op32c0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 1, GN, SMW, 8) +Oper (Op32c8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 1, GN, SMW, 8) +Oper (Op32d0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 1, GN, SMW, 12) +Oper (Op32d8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 1, GN, SMW, 12) +Oper (Op32e0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 1, GN, SMW, 16) +Oper (Op32e8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 1, GN, SMW, 16) +Oper (Op32f0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 1, GN, SMW, 20) +Oper (Op32f8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 1, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3300, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 1, GN, SMW, 12) +Oper (Op3308, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 1, GN, SMW, 12) +Oper (Op3310, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 1, GN, SMW, 16) +Oper (Op3318, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 1, GN, SMW, 16) +Oper (Op3320, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 1, GN, SMW, 16) +Oper (Op3328, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 1, GN, SMW, 20) +Oper (Op3330, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 1, GN, SMW, 20) +Oper (Op3338, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 1, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3340, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 1, GN, SMW, 12) +Oper (Op3348, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 1, GN, SMW, 12) +Oper (Op3350, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 1, GN, SMW, 16) +Oper (Op3358, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 1, GN, SMW, 16) +Oper (Op3360, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 1, GN, SMW, 20) +Oper (Op3368, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 1, GN, SMW, 20) +Oper (Op3370, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 1, GN, SMW, 24) +Oper (Op3378, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 1, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3380, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 1, GN, SMW, 16) +Oper (Op3388, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 1, GN, SMW, 16) +Oper (Op3390, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 1, GN, SMW, 20) +Oper (Op3398, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 1, GN, SMW, 20) +Oper (Op33a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 1, GN, SMW, 20) +Oper (Op33a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 1, GN, SMW, 24) +Oper (Op33b0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 1, GN, SMW, 24) +Oper (Op33b8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 1, GN, SMW, (cycles+21)&0xfffffffc) +Oper (Op33c0, DoMoveW, DW, SdW, ins7, DW, DA, Feaw, 1, GN, SMW, 16) +Oper (Op33c8, DoMoveW, DW, SaW, ins7, DW, DA, Feaw, 1, GN, SMW, 16) +Oper (Op33d0, DoMoveW, DW, SainW, ins7, DW, DA, Feaw, 1, GN, SMW, 20) +Oper (Op33d8, DoMoveW, DW, SaipW, ins7, DW, DA, Feaw, 1, GN, SMW, 20) +Oper (Op33e0, DoMoveW, DW, SmaiW, ins7, DW, DA, Feaw, 1, GN, SMW, 24) +Oper (Op33e8, DoMoveW, DW, SdaiW, ins7, DW, DA, Ceaw, 1, GN, SMW, 24) +Oper (Op33f0, DoMoveW, DW, SaixW, ins7, DW, DA, Ceaw, 1, GN, SMW, 28) +Oper (Op33f8, DoMoveW, DW, SearW, ins7, DW, DA, Ceaw, 1, GN, SMW, (cycles+23)&0xfffffffc) + +Oper (Op3400, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 2, GN, SRW, 4) +Oper (Op3408, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 2, GN, SRW, 4) +Oper (Op3410, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 2, GN, SRW, 8) +Oper (Op3418, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 2, GN, SRW, 8) +Oper (Op3420, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 2, GN, SRW, 12) +Oper (Op3428, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 2, GN, SRW, 12) +Oper (Op3430, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 2, GN, SRW, 16) +Oper (Op3438, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 2, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3440, DoMovea, DW, SdW, ins7, DL, DR, Ca, 2, GN, SRL, 4) +Oper (Op3448, DoMovea, DW, SaW, ins7, DL, DR, Ca, 2, GN, SRL, 4) +Oper (Op3450, DoMovea, DW, SainW, ins7, DL, DR, Ca, 2, GN, SRL, 8) +Oper (Op3458, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 2, GN, SRL, 8) +Oper (Op3460, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 2, GN, SRL, 12) +Oper (Op3468, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 2, GN, SRL, 12) +Oper (Op3470, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 2, GN, SRL, 16) +Oper (Op3478, DoMovea, DW, SearW, ins7, DL, DR, Ca, 2, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3480, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 2, GN, SMW, 8) +Oper (Op3488, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 2, GN, SMW, 8) +Oper (Op3490, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 2, GN, SMW, 12) +Oper (Op3498, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 2, GN, SMW, 12) +Oper (Op34a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 2, GN, SMW, 16) +Oper (Op34a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 2, GN, SMW, 16) +Oper (Op34b0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 2, GN, SMW, 20) +Oper (Op34b8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 2, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op34c0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 2, GN, SMW, 8) +Oper (Op34c8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 2, GN, SMW, 8) +Oper (Op34d0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 2, GN, SMW, 12) +Oper (Op34d8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 2, GN, SMW, 12) +Oper (Op34e0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 2, GN, SMW, 16) +Oper (Op34e8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 2, GN, SMW, 16) +Oper (Op34f0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 2, GN, SMW, 20) +Oper (Op34f8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 2, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3500, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 2, GN, SMW, 12) +Oper (Op3508, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 2, GN, SMW, 12) +Oper (Op3510, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 2, GN, SMW, 16) +Oper (Op3518, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 2, GN, SMW, 16) +Oper (Op3520, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 2, GN, SMW, 16) +Oper (Op3528, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 2, GN, SMW, 20) +Oper (Op3530, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 2, GN, SMW, 20) +Oper (Op3538, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 2, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3540, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 2, GN, SMW, 12) +Oper (Op3548, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 2, GN, SMW, 12) +Oper (Op3550, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 2, GN, SMW, 16) +Oper (Op3558, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 2, GN, SMW, 16) +Oper (Op3560, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 2, GN, SMW, 20) +Oper (Op3568, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 2, GN, SMW, 20) +Oper (Op3570, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 2, GN, SMW, 24) +Oper (Op3578, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 2, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3580, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 2, GN, SMW, 16) +Oper (Op3588, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 2, GN, SMW, 16) +Oper (Op3590, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 2, GN, SMW, 20) +Oper (Op3598, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 2, GN, SMW, 20) +Oper (Op35a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 2, GN, SMW, 20) +Oper (Op35a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 2, GN, SMW, 24) +Oper (Op35b0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 2, GN, SMW, 24) +Oper (Op35b8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 2, GN, SMW, (cycles+21)&0xfffffffc) + +Oper (Op3600, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 3, GN, SRW, 4) +Oper (Op3608, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 3, GN, SRW, 4) +Oper (Op3610, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 3, GN, SRW, 8) +Oper (Op3618, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 3, GN, SRW, 8) +Oper (Op3620, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 3, GN, SRW, 12) +Oper (Op3628, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 3, GN, SRW, 12) +Oper (Op3630, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 3, GN, SRW, 16) +Oper (Op3638, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 3, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3640, DoMovea, DW, SdW, ins7, DL, DR, Ca, 3, GN, SRL, 4) +Oper (Op3648, DoMovea, DW, SaW, ins7, DL, DR, Ca, 3, GN, SRL, 4) +Oper (Op3650, DoMovea, DW, SainW, ins7, DL, DR, Ca, 3, GN, SRL, 8) +Oper (Op3658, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 3, GN, SRL, 8) +Oper (Op3660, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 3, GN, SRL, 12) +Oper (Op3668, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 3, GN, SRL, 12) +Oper (Op3670, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 3, GN, SRL, 16) +Oper (Op3678, DoMovea, DW, SearW, ins7, DL, DR, Ca, 3, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3680, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 3, GN, SMW, 8) +Oper (Op3688, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 3, GN, SMW, 8) +Oper (Op3690, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 3, GN, SMW, 12) +Oper (Op3698, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 3, GN, SMW, 12) +Oper (Op36a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 3, GN, SMW, 16) +Oper (Op36a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 3, GN, SMW, 16) +Oper (Op36b0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 3, GN, SMW, 20) +Oper (Op36b8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 3, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op36c0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 3, GN, SMW, 8) +Oper (Op36c8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 3, GN, SMW, 8) +Oper (Op36d0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 3, GN, SMW, 12) +Oper (Op36d8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 3, GN, SMW, 12) +Oper (Op36e0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 3, GN, SMW, 16) +Oper (Op36e8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 3, GN, SMW, 16) +Oper (Op36f0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 3, GN, SMW, 20) +Oper (Op36f8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 3, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3700, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 3, GN, SMW, 12) +Oper (Op3708, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 3, GN, SMW, 12) +Oper (Op3710, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 3, GN, SMW, 16) +Oper (Op3718, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 3, GN, SMW, 16) +Oper (Op3720, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 3, GN, SMW, 16) +Oper (Op3728, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 3, GN, SMW, 20) +Oper (Op3730, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 3, GN, SMW, 20) +Oper (Op3738, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 3, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3740, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 3, GN, SMW, 12) +Oper (Op3748, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 3, GN, SMW, 12) +Oper (Op3750, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 3, GN, SMW, 16) +Oper (Op3758, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 3, GN, SMW, 16) +Oper (Op3760, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 3, GN, SMW, 20) +Oper (Op3768, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 3, GN, SMW, 20) +Oper (Op3770, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 3, GN, SMW, 24) +Oper (Op3778, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 3, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3780, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 3, GN, SMW, 16) +Oper (Op3788, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 3, GN, SMW, 16) +Oper (Op3790, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 3, GN, SMW, 20) +Oper (Op3798, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 3, GN, SMW, 20) +Oper (Op37a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 3, GN, SMW, 20) +Oper (Op37a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 3, GN, SMW, 24) +Oper (Op37b0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 3, GN, SMW, 24) +Oper (Op37b8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 3, GN, SMW, (cycles+21)&0xfffffffc) + +Oper (Op3800, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 4, GN, SRW, 4) +Oper (Op3808, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 4, GN, SRW, 4) +Oper (Op3810, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 4, GN, SRW, 8) +Oper (Op3818, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 4, GN, SRW, 8) +Oper (Op3820, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 4, GN, SRW, 12) +Oper (Op3828, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 4, GN, SRW, 12) +Oper (Op3830, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 4, GN, SRW, 16) +Oper (Op3838, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 4, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3840, DoMovea, DW, SdW, ins7, DL, DR, Ca, 4, GN, SRL, 4) +Oper (Op3848, DoMovea, DW, SaW, ins7, DL, DR, Ca, 4, GN, SRL, 4) +Oper (Op3850, DoMovea, DW, SainW, ins7, DL, DR, Ca, 4, GN, SRL, 8) +Oper (Op3858, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 4, GN, SRL, 8) +Oper (Op3860, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 4, GN, SRL, 12) +Oper (Op3868, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 4, GN, SRL, 12) +Oper (Op3870, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 4, GN, SRL, 16) +Oper (Op3878, DoMovea, DW, SearW, ins7, DL, DR, Ca, 4, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3880, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 4, GN, SMW, 8) +Oper (Op3888, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 4, GN, SMW, 8) +Oper (Op3890, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 4, GN, SMW, 12) +Oper (Op3898, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 4, GN, SMW, 12) +Oper (Op38a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 4, GN, SMW, 16) +Oper (Op38a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 4, GN, SMW, 16) +Oper (Op38b0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 4, GN, SMW, 20) +Oper (Op38b8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 4, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op38c0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 4, GN, SMW, 8) +Oper (Op38c8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 4, GN, SMW, 8) +Oper (Op38d0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 4, GN, SMW, 12) +Oper (Op38d8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 4, GN, SMW, 12) +Oper (Op38e0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 4, GN, SMW, 16) +Oper (Op38e8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 4, GN, SMW, 16) +Oper (Op38f0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 4, GN, SMW, 20) +Oper (Op38f8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 4, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3900, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 4, GN, SMW, 12) +Oper (Op3908, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 4, GN, SMW, 12) +Oper (Op3910, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 4, GN, SMW, 16) +Oper (Op3918, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 4, GN, SMW, 16) +Oper (Op3920, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 4, GN, SMW, 16) +Oper (Op3928, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 4, GN, SMW, 20) +Oper (Op3930, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 4, GN, SMW, 20) +Oper (Op3938, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 4, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3940, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 4, GN, SMW, 12) +Oper (Op3948, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 4, GN, SMW, 12) +Oper (Op3950, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 4, GN, SMW, 16) +Oper (Op3958, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 4, GN, SMW, 16) +Oper (Op3960, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 4, GN, SMW, 20) +Oper (Op3968, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 4, GN, SMW, 20) +Oper (Op3970, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 4, GN, SMW, 24) +Oper (Op3978, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 4, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3980, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 4, GN, SMW, 16) +Oper (Op3988, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 4, GN, SMW, 16) +Oper (Op3990, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 4, GN, SMW, 20) +Oper (Op3998, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 4, GN, SMW, 20) +Oper (Op39a0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 4, GN, SMW, 20) +Oper (Op39a8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 4, GN, SMW, 24) +Oper (Op39b0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 4, GN, SMW, 24) +Oper (Op39b8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 4, GN, SMW, (cycles+21)&0xfffffffc) + +Oper (Op3a00, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 5, GN, SRW, 4) +Oper (Op3a08, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 5, GN, SRW, 4) +Oper (Op3a10, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 5, GN, SRW, 8) +Oper (Op3a18, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 5, GN, SRW, 8) +Oper (Op3a20, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 5, GN, SRW, 12) +Oper (Op3a28, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 5, GN, SRW, 12) +Oper (Op3a30, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 5, GN, SRW, 16) +Oper (Op3a38, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 5, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3a40, DoMovea, DW, SdW, ins7, DL, DR, Ca, 5, GN, SRL, 4) +Oper (Op3a48, DoMovea, DW, SaW, ins7, DL, DR, Ca, 5, GN, SRL, 4) +Oper (Op3a50, DoMovea, DW, SainW, ins7, DL, DR, Ca, 5, GN, SRL, 8) +Oper (Op3a58, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 5, GN, SRL, 8) +Oper (Op3a60, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 5, GN, SRL, 12) +Oper (Op3a68, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 5, GN, SRL, 12) +Oper (Op3a70, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 5, GN, SRL, 16) +Oper (Op3a78, DoMovea, DW, SearW, ins7, DL, DR, Ca, 5, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3a80, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 5, GN, SMW, 8) +Oper (Op3a88, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 5, GN, SMW, 8) +Oper (Op3a90, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 5, GN, SMW, 12) +Oper (Op3a98, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 5, GN, SMW, 12) +Oper (Op3aa0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 5, GN, SMW, 16) +Oper (Op3aa8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 5, GN, SMW, 16) +Oper (Op3ab0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 5, GN, SMW, 20) +Oper (Op3ab8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 5, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3ac0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 5, GN, SMW, 8) +Oper (Op3ac8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 5, GN, SMW, 8) +Oper (Op3ad0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 5, GN, SMW, 12) +Oper (Op3ad8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 5, GN, SMW, 12) +Oper (Op3ae0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 5, GN, SMW, 16) +Oper (Op3ae8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 5, GN, SMW, 16) +Oper (Op3af0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 5, GN, SMW, 20) +Oper (Op3af8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 5, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3b00, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 5, GN, SMW, 12) +Oper (Op3b08, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 5, GN, SMW, 12) +Oper (Op3b10, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 5, GN, SMW, 16) +Oper (Op3b18, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 5, GN, SMW, 16) +Oper (Op3b20, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 5, GN, SMW, 16) +Oper (Op3b28, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 5, GN, SMW, 20) +Oper (Op3b30, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 5, GN, SMW, 20) +Oper (Op3b38, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 5, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3b40, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 5, GN, SMW, 12) +Oper (Op3b48, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 5, GN, SMW, 12) +Oper (Op3b50, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 5, GN, SMW, 16) +Oper (Op3b58, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 5, GN, SMW, 16) +Oper (Op3b60, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 5, GN, SMW, 20) +Oper (Op3b68, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 5, GN, SMW, 20) +Oper (Op3b70, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 5, GN, SMW, 24) +Oper (Op3b78, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 5, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3b80, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 5, GN, SMW, 16) +Oper (Op3b88, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 5, GN, SMW, 16) +Oper (Op3b90, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 5, GN, SMW, 20) +Oper (Op3b98, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 5, GN, SMW, 20) +Oper (Op3ba0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 5, GN, SMW, 20) +Oper (Op3ba8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 5, GN, SMW, 24) +Oper (Op3bb0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 5, GN, SMW, 24) +Oper (Op3bb8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 5, GN, SMW, (cycles+21)&0xfffffffc) + +Oper (Op3c00, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 6, GN, SRW, 4) +Oper (Op3c08, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 6, GN, SRW, 4) +Oper (Op3c10, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 6, GN, SRW, 8) +Oper (Op3c18, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 6, GN, SRW, 8) +Oper (Op3c20, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 6, GN, SRW, 12) +Oper (Op3c28, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 6, GN, SRW, 12) +Oper (Op3c30, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 6, GN, SRW, 16) +Oper (Op3c38, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 6, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3c40, DoMovea, DW, SdW, ins7, DL, DR, Ca, 6, GN, SRL, 4) +Oper (Op3c48, DoMovea, DW, SaW, ins7, DL, DR, Ca, 6, GN, SRL, 4) +Oper (Op3c50, DoMovea, DW, SainW, ins7, DL, DR, Ca, 6, GN, SRL, 8) +Oper (Op3c58, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 6, GN, SRL, 8) +Oper (Op3c60, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 6, GN, SRL, 12) +Oper (Op3c68, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 6, GN, SRL, 12) +Oper (Op3c70, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 6, GN, SRL, 16) +Oper (Op3c78, DoMovea, DW, SearW, ins7, DL, DR, Ca, 6, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3c80, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 6, GN, SMW, 8) +Oper (Op3c88, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 6, GN, SMW, 8) +Oper (Op3c90, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 6, GN, SMW, 12) +Oper (Op3c98, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 6, GN, SMW, 12) +Oper (Op3ca0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 6, GN, SMW, 16) +Oper (Op3ca8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 6, GN, SMW, 16) +Oper (Op3cb0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 6, GN, SMW, 20) +Oper (Op3cb8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 6, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3cc0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 6, GN, SMW, 8) +Oper (Op3cc8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 6, GN, SMW, 8) +Oper (Op3cd0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 6, GN, SMW, 12) +Oper (Op3cd8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 6, GN, SMW, 12) +Oper (Op3ce0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 6, GN, SMW, 16) +Oper (Op3ce8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 6, GN, SMW, 16) +Oper (Op3cf0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 6, GN, SMW, 20) +Oper (Op3cf8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 6, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3d00, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 6, GN, SMW, 12) +Oper (Op3d08, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 6, GN, SMW, 12) +Oper (Op3d10, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 6, GN, SMW, 16) +Oper (Op3d18, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 6, GN, SMW, 16) +Oper (Op3d20, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 6, GN, SMW, 16) +Oper (Op3d28, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 6, GN, SMW, 20) +Oper (Op3d30, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 6, GN, SMW, 20) +Oper (Op3d38, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 6, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3d40, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 6, GN, SMW, 12) +Oper (Op3d48, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 6, GN, SMW, 12) +Oper (Op3d50, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 6, GN, SMW, 16) +Oper (Op3d58, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 6, GN, SMW, 16) +Oper (Op3d60, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 6, GN, SMW, 20) +Oper (Op3d68, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 6, GN, SMW, 20) +Oper (Op3d70, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 6, GN, SMW, 24) +Oper (Op3d78, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 6, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3d80, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 6, GN, SMW, 16) +Oper (Op3d88, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 6, GN, SMW, 16) +Oper (Op3d90, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 6, GN, SMW, 20) +Oper (Op3d98, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 6, GN, SMW, 20) +Oper (Op3da0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 6, GN, SMW, 20) +Oper (Op3da8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 6, GN, SMW, 24) +Oper (Op3db0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 6, GN, SMW, 24) +Oper (Op3db8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 6, GN, SMW, (cycles+21)&0xfffffffc) + +Oper (Op3e00, DoMoveW, DW, SdW, ins7, DW, DR, Cd, 7, GN, SRW, 4) +Oper (Op3e08, DoMoveW, DW, SaW, ins7, DW, DR, Cd, 7, GN, SRW, 4) +Oper (Op3e10, DoMoveW, DW, SainW, ins7, DW, DR, Cd, 7, GN, SRW, 8) +Oper (Op3e18, DoMoveW, DW, SaipW, ins7, DW, DR, Cd, 7, GN, SRW, 8) +Oper (Op3e20, DoMoveW, DW, SmaiW, ins7, DW, DR, Cd, 7, GN, SRW, 12) +Oper (Op3e28, DoMoveW, DW, SdaiW, ins7, DW, DR, Cd, 7, GN, SRW, 12) +Oper (Op3e30, DoMoveW, DW, SaixW, ins7, DW, DR, Cd, 7, GN, SRW, 16) +Oper (Op3e38, DoMoveW, DW, SearW, ins7, DW, DR, Cd, 7, GN, SRW, (cycles+11)&0xfffffffc) +Oper (Op3e40, DoMovea, DW, SdW, ins7, DL, DR, Ca, 7, GN, SRL, 4) +Oper (Op3e48, DoMovea, DW, SaW, ins7, DL, DR, Ca, 7, GN, SRL, 4) +Oper (Op3e50, DoMovea, DW, SainW, ins7, DL, DR, Ca, 7, GN, SRL, 8) +Oper (Op3e58, DoMovea, DW, SaipW, ins7, DL, DR, Ca, 7, GN, SRL, 8) +Oper (Op3e60, DoMovea, DW, SmaiW, ins7, DL, DR, Ca, 7, GN, SRL, 12) +Oper (Op3e68, DoMovea, DW, SdaiW, ins7, DL, DR, Ca, 7, GN, SRL, 12) +Oper (Op3e70, DoMovea, DW, SaixW, ins7, DL, DR, Ca, 7, GN, SRL, 16) +Oper (Op3e78, DoMovea, DW, SearW, ins7, DL, DR, Ca, 7, GN, SRL, (cycles+11)&0xfffffffc) +Oper (Op3e80, DoMoveW, DW, SdW, ins7, DW, DA, Cain, 7, GN, SMW, 8) +Oper (Op3e88, DoMoveW, DW, SaW, ins7, DW, DA, Cain, 7, GN, SMW, 8) +Oper (Op3e90, DoMoveW, DW, SainW, ins7, DW, DA, Cain, 7, GN, SMW, 12) +Oper (Op3e98, DoMoveW, DW, SaipW, ins7, DW, DA, Cain, 7, GN, SMW, 12) +Oper (Op3ea0, DoMoveW, DW, SmaiW, ins7, DW, DA, Cain, 7, GN, SMW, 16) +Oper (Op3ea8, DoMoveW, DW, SdaiW, ins7, DW, DA, Cain, 7, GN, SMW, 16) +Oper (Op3eb0, DoMoveW, DW, SaixW, ins7, DW, DA, Cain, 7, GN, SMW, 20) +Oper (Op3eb8, DoMoveW, DW, SearW, ins7, DW, DA, Cain, 7, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3ec0, DoMoveW, DW, SdW, ins7, DW, DA, CaipW, 7, GN, SMW, 8) +Oper (Op3ec8, DoMoveW, DW, SaW, ins7, DW, DA, CaipW, 7, GN, SMW, 8) +Oper (Op3ed0, DoMoveW, DW, SainW, ins7, DW, DA, CaipW, 7, GN, SMW, 12) +Oper (Op3ed8, DoMoveW, DW, SaipW, ins7, DW, DA, CaipW, 7, GN, SMW, 12) +Oper (Op3ee0, DoMoveW, DW, SmaiW, ins7, DW, DA, CaipW, 7, GN, SMW, 16) +Oper (Op3ee8, DoMoveW, DW, SdaiW, ins7, DW, DA, CaipW, 7, GN, SMW, 16) +Oper (Op3ef0, DoMoveW, DW, SaixW, ins7, DW, DA, CaipW, 7, GN, SMW, 20) +Oper (Op3ef8, DoMoveW, DW, SearW, ins7, DW, DA, CaipW, 7, GN, SMW, (cycles+15)&0xfffffffc) +Oper (Op3f00, DoMoveW, DW, SdW, ins7, DW, DA, CmaiW, 7, GN, SMW, 12) +Oper (Op3f08, DoMoveW, DW, SaW, ins7, DW, DA, CmaiW, 7, GN, SMW, 12) +Oper (Op3f10, DoMoveW, DW, SainW, ins7, DW, DA, CmaiW, 7, GN, SMW, 16) +Oper (Op3f18, DoMoveW, DW, SaipW, ins7, DW, DA, CmaiW, 7, GN, SMW, 16) +Oper (Op3f20, DoMoveW, DW, SmaiW, ins7, DW, DA, CmaiW, 7, GN, SMW, 16) +Oper (Op3f28, DoMoveW, DW, SdaiW, ins7, DW, DA, CmaiW, 7, GN, SMW, 20) +Oper (Op3f30, DoMoveW, DW, SaixW, ins7, DW, DA, CmaiW, 7, GN, SMW, 20) +Oper (Op3f38, DoMoveW, DW, SearW, ins7, DW, DA, CmaiW, 7, GN, SMW, (cycles+17)&0xfffffffc) +Oper (Op3f40, DoMoveW, DW, SdW, ins7, DW, DA, Fdai, 7, GN, SMW, 12) +Oper (Op3f48, DoMoveW, DW, SaW, ins7, DW, DA, Fdai, 7, GN, SMW, 12) +Oper (Op3f50, DoMoveW, DW, SainW, ins7, DW, DA, Fdai, 7, GN, SMW, 16) +Oper (Op3f58, DoMoveW, DW, SaipW, ins7, DW, DA, Fdai, 7, GN, SMW, 16) +Oper (Op3f60, DoMoveW, DW, SmaiW, ins7, DW, DA, Fdai, 7, GN, SMW, 20) +Oper (Op3f68, DoMoveW, DW, SdaiW, ins7, DW, DA, Cdai, 7, GN, SMW, 20) +Oper (Op3f70, DoMoveW, DW, SaixW, ins7, DW, DA, Cdai, 7, GN, SMW, 24) +Oper (Op3f78, DoMoveW, DW, SearW, ins7, DW, DA, Cdai, 7, GN, SMW, (cycles+19)&0xfffffffc) +Oper (Op3f80, DoMoveW, DW, SdW, ins7, DW, DA, Faix, 7, GN, SMW, 16) +Oper (Op3f88, DoMoveW, DW, SaW, ins7, DW, DA, Faix, 7, GN, SMW, 16) +Oper (Op3f90, DoMoveW, DW, SainW, ins7, DW, DA, Faix, 7, GN, SMW, 20) +Oper (Op3f98, DoMoveW, DW, SaipW, ins7, DW, DA, Faix, 7, GN, SMW, 20) +Oper (Op3fa0, DoMoveW, DW, SmaiW, ins7, DW, DA, Faix, 7, GN, SMW, 20) +Oper (Op3fa8, DoMoveW, DW, SdaiW, ins7, DW, DA, Caix, 7, GN, SMW, 24) +Oper (Op3fb0, DoMoveW, DW, SaixW, ins7, DW, DA, Caix, 7, GN, SMW, 24) +Oper (Op3fb8, DoMoveW, DW, SearW, ins7, DW, DA, Caix, 7, GN, SMW, (cycles+21)&0xfffffffc) + +Oper (Op7000, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 0, GN, SRL, 4) +Oper (Op7200, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 1, GN, SRL, 4) +Oper (Op7400, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 2, GN, SRL, 4) +Oper (Op7600, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 3, GN, SRL, 4) +Oper (Op7800, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 4, GN, SRL, 4) +Oper (Op7a00, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 5, GN, SRL, 4) +Oper (Op7c00, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 6, GN, SRL, 4) +Oper (Op7e00, DoMoveL, DL, SNQ, 0, DL, DR, Cd, 7, GN, SRL, 4) diff --git a/MCUME_esp32/espcastaway/main/68korigbad/op68kshift.cpp b/MCUME_esp32/espcastaway/main/68korigbad/op68kshift.cpp new file mode 100755 index 0000000..1b03f12 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/op68kshift.cpp @@ -0,0 +1,864 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - 68k shift instructions +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 22.06.2002 JH V-flag after ASL was broken in some special cases. +* 09.07.2002 JH ROXL/ROXR: X-flag not modified when shift count is 0. +* 10.07.2002 JH other shift ops: X-flag not modified when shift count is 0. +* 10.09.2002 JH Bugfix: ROXL.L +* 15.09.2002 JH Minor SR/Bcc/Scc optimization. Fixed V-Flag for ASL.L. +* Wrapped 68k operand types in typedefs. +* 01.10.2002 JH Bugfix: -(Ax) and (Ax)+ addressing modes were swapped. +* *** Many thx to olivencia@wanado.fr for finding this!! *** +* 02.10.2002 JH SetV simplified for ASL. +*/ +#ifndef PROTOH +static char sccsid[] = "$Id: op68kshift.c,v 1.10 2002/10/05 08:25:08 jhoenig Exp $"; +#include "68000.h" +#include "op68k.h" + +#define addcycles cycles+=source<<1; + +#define DoAslB(target,source) \ + source&=0x3f; \ + addcycles \ + if (source> 0) {\ + register uint32 cvnz=0;\ + register uint32 tgt=target< 0) {\ + register uint32 cvnz=0;\ + register uint32 tgt=target<0) {\ + register uint32 cvnz=0;\ + register uint32 tgt=target<<(source-1);\ + if (tgt&0x80000000) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\ + tgt<<=1;\ + if ((((uint32)target)>>31)!=(tgt>>31)) cvnz+=Vflag;\ + target=tgt;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ + } else {\ + ClrCVSetNZ(target);\ +} + +#define DoAsr(target,source) \ + source&=0x3f; \ + addcycles \ + if (source>0) {\ + register uint32 cvnz=0;\ + target >>= source - 1;\ + if (target & 0x1) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\ + target >>= 1;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ + } else {\ + ClrCVSetNZ(target);\ +} + +#define DoAsrB(target,source) DoAsr(target,source) +#define DoAsrW(target,source) DoAsr(target,source) +#define DoAsrL(target,source) DoAsr(target,source) + +#define DoLslB(target,source) \ + source&=0x3f; \ + addcycles \ + if (source>0) {\ + register uint32 cvnz=0;\ + register uint32 tgt=target<0) {\ + register uint32 cvnz=0;\ + register uint32 tgt=target< 0) {\ + register uint32 cvnz=0;\ + target <<= source - 1;\ + if (target & 0x80000000) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\ + target <<= 1;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ + } else {\ + ClrCVSetNZ(target);\ + } + +#define DoLsr(target,source,type) \ + source&=0x3f; \ + addcycles \ + if (source> 0) {\ + register uint32 cvnz=0;\ + if (target&(1<<(source-1))) {cvnz+=Cflag; ForceX(1);} else ForceX(0);\ + target=((type)target)>>source;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ + } else {\ + ClrCVSetNZ(target);\ + } + +#define DoLsrB(target,source) DoLsr(target,source,uint8) +#define DoLsrW(target,source) DoLsr(target,source,uint16) +#define DoLsrL(target,source) DoLsr(target,source,uint32) + + +#define DoRoxlB(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + SetC(GetX());\ + } else {\ + register uint16 tgt1, tgt2;\ + source %= 9;\ + tgt1 = (uint8) target;\ + tgt1 |= (uint16) (GetX()) << 8;\ + tgt2 = tgt1;\ + tgt2 >>= (9 - source);\ + tgt1 <<= source;\ + tgt1 |= tgt2;\ + SetXC ((tgt1 >> 8) & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRoxlW(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + SetC(GetX());\ + } else {\ + register uint32 tgt1, tgt2;\ + source %= 17;\ + tgt1 = (uint16) target;\ + tgt1 |= (uint32) (GetX()) << 16;\ + tgt2 = tgt1;\ + tgt2 >>= (17 - source);\ + tgt1 <<= source;\ + tgt1 |= tgt2;\ + SetXC ((tgt1 >> 16) & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRoxlL(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + SetC(GetX());\ + } else {\ + register uint32 tgt1, tgt2;\ + source %= 33;\ + tgt2 = tgt1 = (uint32) target;\ + if (source != 0) {\ + tgt1 <<= 1;\ + tgt1 |= (uint32) (GetX());\ + tgt1 <<= (source - 1);\ + tgt2 >>= (32 - source);\ + SetXC (tgt2 & 0x1);\ + tgt2 >>= 1;\ + tgt1 |= tgt2;\ + target = tgt1;\ + }\ + }\ + SetNZ (target);\ +} + +#define DoRoxrB(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + SetC(GetX());\ + } else {\ + register uint16 tgt1, tgt2;\ + source %= 9;\ + tgt1 = (uint8) target;\ + tgt1 |= (uint16) (GetX()) << 8;\ + tgt2 = tgt1;\ + tgt2 <<= (9 - source);\ + tgt1 >>= source;\ + tgt1 |= tgt2;\ + SetXC ((tgt1 >> 8) & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRoxrW(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + SetC(GetX());\ + } else {\ + register uint32 tgt1, tgt2;\ + source %= 17;\ + tgt1 = (uint16) target;\ + tgt1 |= (uint32) (GetX()) << 16;\ + tgt2 = tgt1;\ + tgt2 <<= (17 - source);\ + tgt1 >>= source;\ + tgt1 |= tgt2;\ + SetXC ((tgt1 >> 16) & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRoxrL(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + SetC(GetX());\ + } else {\ + register uint32 tgt1, tgt2;\ + source %= 33;\ + tgt2 = tgt1 = (uint32) target;\ + if (source != 0) {\ + tgt2 <<= 1;\ + tgt2 |= (uint32) (GetX());\ + tgt2 <<= (32 - source);\ + tgt1 >>= (source - 1);\ + SetXC (tgt1 & 0x1);\ + tgt1 >>= 1;\ + tgt1 |= tgt2;\ + target = tgt1;\ + }\ + }\ + SetNZ (target);\ +} + +#define DoRolB(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + ForceC (0);\ + } else {\ + register uint8 tgt1, tgt2;\ + source &= 0x7;\ + tgt2 = tgt1 = target;\ + tgt2 >>= (8 - source);\ + tgt1 <<= source;\ + tgt1 |= tgt2;\ + SetC (tgt1 & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRolW(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + ForceC (0);\ + } else {\ + register uint16 tgt1, tgt2;\ + source &= 0xf;\ + tgt2 = tgt1 = target;\ + tgt2 >>= (16 - source);\ + tgt1 <<= source;\ + tgt1 |= tgt2;\ + SetC (tgt1 & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRolL(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + ForceC (0);\ + } else {\ + register uint32 tgt1, tgt2;\ + source &= 0x1f;\ + tgt2 = tgt1 = (uint32) target;\ + tgt2 >>= (32 - source);\ + tgt1 <<= source;\ + tgt1 |= tgt2;\ + SetC (tgt1 & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRorB(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + ForceC (0);\ + } else {\ + register uint8 tgt1, tgt2;\ + source &= 0x7;\ + tgt2 = tgt1 = target;\ + tgt2 <<= (8 - source);\ + tgt1 >>= source;\ + tgt1 |= tgt2;\ + SetC ((tgt1 >> 7) & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRorW(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + ForceC (0);\ + } else {\ + register uint16 tgt1, tgt2;\ + source &= 0xf;\ + tgt2 = tgt1 = target;\ + tgt2 <<= (16 - source);\ + tgt1 >>= source;\ + tgt1 |= tgt2;\ + SetC ((tgt1 >> 15) & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#define DoRorL(target,source) {\ + source &= 0x3f;\ + addcycles \ + ForceV (0);\ + if (source == 0) {\ + ForceC (0);\ + } else {\ + register uint32 tgt1, tgt2;\ + source &= 0x1f;\ + tgt2 = tgt1 = target;\ + tgt2 <<= (32 - source);\ + tgt1 >>= source;\ + tgt1 |= tgt2;\ + SetC ((tgt1 >> 31) & 0x1);\ + target = tgt1;\ + }\ + SetNZ (target);\ +} + +#endif + +Oper (Ope000, DoAsrB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope008, DoLsrB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope010, DoRoxrB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope018, DoRorB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope020, DoAsrB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope028, DoLsrB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope030, DoRoxrB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope038, DoRorB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope040, DoAsrW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope048, DoLsrW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope050, DoRoxrW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope058, DoRorW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope060, DoAsrW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope068, DoLsrW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope070, DoRoxrW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope078, DoRorW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope080, DoAsrL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope088, DoLsrL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope090, DoRoxrL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope098, DoRorL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope0a0, DoAsrL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope0a8, DoLsrL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope0b0, DoRoxrL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope0b8, DoRorL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope100, DoAslB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope108, DoLslB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope110, DoRoxlB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope118, DoRolB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope120, DoAslB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope128, DoLslB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope130, DoRoxlB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope138, DoRolB, DB, SdB, 0, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope140, DoAslW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope148, DoLslW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope150, DoRoxlW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope158, DoRolW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope160, DoAslW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope168, DoLslW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope170, DoRoxlW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope178, DoRolW, DW, SdW, 0, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope180, DoAslL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope188, DoLslL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope190, DoRoxlL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope198, DoRolL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope1a0, DoAslL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope1a8, DoLslL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope1b0, DoRoxlL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope1b8, DoRolL, DL, SdL, 0, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope200, DoAsrB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope208, DoLsrB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope210, DoRoxrB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope218, DoRorB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope220, DoAsrB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope228, DoLsrB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope230, DoRoxrB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope238, DoRorB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope240, DoAsrW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope248, DoLsrW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope250, DoRoxrW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope258, DoRorW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope260, DoAsrW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope268, DoLsrW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope270, DoRoxrW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope278, DoRorW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope280, DoAsrL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope288, DoLsrL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope290, DoRoxrL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope298, DoRorL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope2a0, DoAsrL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope2a8, DoLsrL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope2b0, DoRoxrL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope2b8, DoRorL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope300, DoAslB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope308, DoLslB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope310, DoRoxlB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope318, DoRolB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope320, DoAslB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope328, DoLslB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope330, DoRoxlB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope338, DoRolB, DB, SdB, 1, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope340, DoAslW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope348, DoLslW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope350, DoRoxlW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope358, DoRolW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope360, DoAslW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope368, DoLslW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope370, DoRoxlW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope378, DoRolW, DW, SdW, 1, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope380, DoAslL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope388, DoLslL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope390, DoRoxlL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope398, DoRolL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope3a0, DoAslL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope3a8, DoLslL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope3b0, DoRoxlL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope3b8, DoRolL, DL, SdL, 1, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope400, DoAsrB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope408, DoLsrB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope410, DoRoxrB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope418, DoRorB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope420, DoAsrB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope428, DoLsrB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope430, DoRoxrB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope438, DoRorB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope440, DoAsrW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope448, DoLsrW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope450, DoRoxrW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope458, DoRorW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope460, DoAsrW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope468, DoLsrW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope470, DoRoxrW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope478, DoRorW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope480, DoAsrL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope488, DoLsrL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope490, DoRoxrL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope498, DoRorL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope4a0, DoAsrL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope4a8, DoLsrL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope4b0, DoRoxrL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope4b8, DoRorL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope500, DoAslB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope508, DoLslB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope510, DoRoxlB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope518, DoRolB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope520, DoAslB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope528, DoLslB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope530, DoRoxlB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope538, DoRolB, DB, SdB, 2, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope540, DoAslW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope548, DoLslW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope550, DoRoxlW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope558, DoRolW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope560, DoAslW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope568, DoLslW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope570, DoRoxlW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope578, DoRolW, DW, SdW, 2, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope580, DoAslL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope588, DoLslL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope590, DoRoxlL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope598, DoRolL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope5a0, DoAslL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope5a8, DoLslL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope5b0, DoRoxlL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope5b8, DoRolL, DL, SdL, 2, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope600, DoAsrB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope608, DoLsrB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope610, DoRoxrB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope618, DoRorB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope620, DoAsrB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope628, DoLsrB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope630, DoRoxrB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope638, DoRorB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope640, DoAsrW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope648, DoLsrW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope650, DoRoxrW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope658, DoRorW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope660, DoAsrW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope668, DoLsrW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope670, DoRoxrW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope678, DoRorW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope680, DoAsrL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope688, DoLsrL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope690, DoRoxrL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope698, DoRorL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope6a0, DoAsrL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope6a8, DoLsrL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope6b0, DoRoxrL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope6b8, DoRorL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope700, DoAslB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope708, DoLslB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope710, DoRoxlB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope718, DoRolB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope720, DoAslB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope728, DoLslB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope730, DoRoxlB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope738, DoRolB, DB, SdB, 3, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope740, DoAslW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope748, DoLslW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope750, DoRoxlW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope758, DoRolW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope760, DoAslW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope768, DoLslW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope770, DoRoxlW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope778, DoRolW, DW, SdW, 3, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope780, DoAslL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope788, DoLslL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope790, DoRoxlL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope798, DoRolL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope7a0, DoAslL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope7a8, DoLslL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope7b0, DoRoxlL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope7b8, DoRolL, DL, SdL, 3, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope800, DoAsrB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope808, DoLsrB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope810, DoRoxrB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope818, DoRorB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope820, DoAsrB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope828, DoLsrB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope830, DoRoxrB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope838, DoRorB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope840, DoAsrW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope848, DoLsrW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope850, DoRoxrW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope858, DoRorW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope860, DoAsrW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope868, DoLsrW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope870, DoRoxrW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope878, DoRorW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope880, DoAsrL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope888, DoLsrL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope890, DoRoxrL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope898, DoRorL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope8a0, DoAsrL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope8a8, DoLsrL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope8b0, DoRoxrL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope8b8, DoRorL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope900, DoAslB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope908, DoLslB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope910, DoRoxlB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope918, DoRolB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope920, DoAslB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope928, DoLslB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope930, DoRoxlB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope938, DoRolB, DB, SdB, 4, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Ope940, DoAslW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope948, DoLslW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope950, DoRoxlW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope958, DoRolW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope960, DoAslW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope968, DoLslW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope970, DoRoxlW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope978, DoRolW, DW, SdW, 4, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Ope980, DoAslL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope988, DoLslL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope990, DoRoxlL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope998, DoRolL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope9a0, DoAslL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope9a8, DoLslL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope9b0, DoRoxlL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Ope9b8, DoRolL, DL, SdL, 4, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Opea00, DoAsrB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea08, DoLsrB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea10, DoRoxrB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea18, DoRorB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea20, DoAsrB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea28, DoLsrB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea30, DoRoxrB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea38, DoRorB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opea40, DoAsrW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea48, DoLsrW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea50, DoRoxrW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea58, DoRorW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea60, DoAsrW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea68, DoLsrW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea70, DoRoxrW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea78, DoRorW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opea80, DoAsrL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opea88, DoLsrL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opea90, DoRoxrL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opea98, DoRorL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeaa0, DoAsrL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeaa8, DoLsrL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeab0, DoRoxrL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeab8, DoRorL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Opeb00, DoAslB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb08, DoLslB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb10, DoRoxlB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb18, DoRolB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb20, DoAslB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb28, DoLslB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb30, DoRoxlB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb38, DoRolB, DB, SdB, 5, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opeb40, DoAslW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb48, DoLslW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb50, DoRoxlW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb58, DoRolW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb60, DoAslW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb68, DoLslW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb70, DoRoxlW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb78, DoRolW, DW, SdW, 5, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opeb80, DoAslL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeb88, DoLslL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeb90, DoRoxlL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeb98, DoRolL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeba0, DoAslL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeba8, DoLslL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opebb0, DoRoxlL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opebb8, DoRolL, DL, SdL, 5, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Opec00, DoAsrB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec08, DoLsrB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec10, DoRoxrB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec18, DoRorB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec20, DoAsrB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec28, DoLsrB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec30, DoRoxrB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec38, DoRorB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opec40, DoAsrW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec48, DoLsrW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec50, DoRoxrW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec58, DoRorW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec60, DoAsrW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec68, DoLsrW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec70, DoRoxrW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec78, DoRorW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opec80, DoAsrL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opec88, DoLsrL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opec90, DoRoxrL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opec98, DoRorL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeca0, DoAsrL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeca8, DoLsrL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opecb0, DoRoxrL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opecb8, DoRorL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Oped00, DoAslB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped08, DoLslB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped10, DoRoxlB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped18, DoRolB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped20, DoAslB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped28, DoLslB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped30, DoRoxlB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped38, DoRolB, DB, SdB, 6, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Oped40, DoAslW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped48, DoLslW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped50, DoRoxlW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped58, DoRolW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped60, DoAslW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped68, DoLslW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped70, DoRoxlW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped78, DoRolW, DW, SdW, 6, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Oped80, DoAslL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Oped88, DoLslL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Oped90, DoRoxlL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Oped98, DoRolL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeda0, DoAslL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeda8, DoLslL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opedb0, DoRoxlL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opedb8, DoRolL, DL, SdL, 6, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Opee00, DoAsrB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee08, DoLsrB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee10, DoRoxrB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee18, DoRorB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee20, DoAsrB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee28, DoLsrB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee30, DoRoxrB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee38, DoRorB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opee40, DoAsrW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee48, DoLsrW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee50, DoRoxrW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee58, DoRorW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee60, DoAsrW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee68, DoLsrW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee70, DoRoxrW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee78, DoRorW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opee80, DoAsrL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opee88, DoLsrL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opee90, DoRoxrL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opee98, DoRorL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeea0, DoAsrL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeea8, DoLsrL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeeb0, DoRoxrL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opeeb8, DoRorL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Opef00, DoAslB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef08, DoLslB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef10, DoRoxlB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef18, DoRolB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef20, DoAslB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef28, DoLslB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef30, DoRoxlB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef38, DoRolB, DB, SdB, 7, DB, DR, Cd, ins7, GRB, SRB, (cycles+9)&0xfffffffc) +Oper (Opef40, DoAslW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef48, DoLslW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef50, DoRoxlW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef58, DoRolW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef60, DoAslW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef68, DoLslW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef70, DoRoxlW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef78, DoRolW, DW, SdW, 7, DW, DR, Cd, ins7, GRW, SRW, (cycles+9)&0xfffffffc) +Oper (Opef80, DoAslL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opef88, DoLslL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opef90, DoRoxlL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opef98, DoRolL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opefa0, DoAslL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opefa8, DoLslL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opefb0, DoRoxlL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) +Oper (Opefb8, DoRolL, DL, SdL, 7, DL, DR, Cd, ins7, GRL, SRL, (cycles+11)&0xfffffffc) + +Oper (Ope0d0, DoAsrW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope0d8, DoAsrW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope0e0, DoAsrW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope0e8, DoAsrW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope0f0, DoAsrW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope0f8, DoAsrW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + +Oper (Ope1d0, DoAslW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope1d8, DoAslW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope1e0, DoAslW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope1e8, DoAslW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope1f0, DoAslW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope1f8, DoAslW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + +Oper (Ope2d0, DoLsrW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope2d8, DoLsrW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope2e0, DoLsrW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope2e8, DoLsrW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope2f0, DoLsrW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope2f8, DoLsrW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + +Oper (Ope3d0, DoLslW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope3d8, DoLslW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope3e0, DoLslW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope3e8, DoLslW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope3f0, DoLslW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope3f8, DoLslW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + +Oper (Ope4d0, DoRoxrW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope4d8, DoRoxrW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope4e0, DoRoxrW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope4e8, DoRoxrW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope4f0, DoRoxrW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope4f8, DoRoxrW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + +Oper (Ope5d0, DoRoxlW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope5d8, DoRoxlW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope5e0, DoRoxlW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope5e8, DoRoxlW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope5f0, DoRoxlW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope5f8, DoRoxlW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + +Oper (Ope6d0, DoRorW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope6d8, DoRorW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope6e0, DoRorW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope6e8, DoRorW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope6f0, DoRorW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope6f8, DoRorW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + +Oper (Ope7d0, DoRolW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Ope7d8, DoRolW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Ope7e0, DoRolW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Ope7e8, DoRolW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Ope7f0, DoRolW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Ope7f8, DoRolW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) + diff --git a/MCUME_esp32/espcastaway/main/68korigbad/op68ksub.cpp b/MCUME_esp32/espcastaway/main/68korigbad/op68ksub.cpp new file mode 100755 index 0000000..0154772 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/op68ksub.cpp @@ -0,0 +1,810 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - 68k subtract instructions +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 10.07.2002 JH Fixed Z-Flag for SUBX +* 08.10.2002 JH Fixed Z-Flag for ADD.B 0x80+0x80 and Add.W 0x8000+0x8000. +*/ +#ifndef PROTOH +static char sccsid[] = "$Id: op68ksub.c,v 1.3 2002/10/08 00:18:02 jhoenig Exp $"; +#include "68000.h" +#include "op68k.h" + +/* +* Opfuncs. +*/ + +#define DoSubB(target,source) \ +{register int32 tgt, cvnz=0;\ + tgt = target - source;\ + if ((uint32) source > (uint32) target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\ + target = tgt;\ + if (tgt!=target) cvnz+=Vflag;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoSubW(target,source) \ +{register int32 tgt, cvnz=0;\ + tgt = target - source;\ + if ((uint32) source > (uint32) target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\ + target = tgt;\ + if (tgt!=target) cvnz+=Vflag;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoSubL(target,source) \ + /* Overflow precondition: source has different sign */\ +{register int32 precon=(target>>31)-(source>>31), cvnz=0;\ + if ((uint32) source > (uint32) target) {ForceX(1); cvnz+=Cflag;} else ForceX(0);\ + target -= source;\ + /* target and source now have same sign: overflow! */\ + if (precon && (target>>31)==(source>>31)) cvnz+=Vflag;\ + if (target==0) cvnz+=Zflag;\ + else if (target<0) cvnz+=Nflag;\ + ForceCVNZ(cvnz);\ +}; + +#define DoSuba(target,source) target -= source; + +#define DoSubx(target,source) \ + /* Overflow precondition: source has different sign */\ +{register int32 precon=(target>>31)-(source>>31);\ + if (GetX ()) {\ + SetXC ((uint32) source >= (uint32) target);\ + target -= source;\ + target -= 1;\ + } else {\ + SetXC ((uint32) source > (uint32) target);\ + target -= source;\ +}\ + /* target and source now have same sign: overflow! */\ + SetV(precon && (target>>31)==(source>>31));\ + ZeroZ(target!=0);\ +SetN(target < 0);}; +#endif + + +Oper (Op9000, DoSubB, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4) +Oper (Op9010, DoSubB, DB, SainB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Op9018, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 0, GRB, SRB, 8) +Oper (Op9020, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Op9028, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 0, GRB, SRB, 12) +Oper (Op9030, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 0, GRB, SRB, 16) +Oper (Op9038, DoSubB, DB, SearB, ins7, DB, DR, Cd, 0, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9040, DoSubW, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Op9048, DoSubW, DW, SaW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Op9050, DoSubW, DW, SainW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Op9058, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 0, GRW, SRW, 8) +Oper (Op9060, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Op9068, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 0, GRW, SRW, 12) +Oper (Op9070, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 0, GRW, SRW, 16) +Oper (Op9078, DoSubW, DW, SearW, ins7, DW, DR, Cd, 0, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9080, DoSubL, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Op9088, DoSubL, DL, SaL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Op9090, DoSubL, DL, SainL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Op9098, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Op90a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 16) +Oper (Op90a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Op90b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 0, GRL, SRL, 20) +Oper (Op90b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 0, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op90c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Op90c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Op90d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 0, GRL, SRL, 12) +Oper (Op90d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 0, GRL, SRL, 12) +Oper (Op90e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Op90e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Op90f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 0, GRL, SRL, 20) +Oper (Op90f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 0, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9100, DoSubx, DB, SdB, ins7, DB, DR, Cd, 0, GRB, SRB, 4) +Oper (Op9108, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 0, GMB, SMB, 20) +Oper (Op9110, DoSubB, DB, SdB, 0, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9118, DoSubB, DB, SdB, 0, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9120, DoSubB, DB, SdB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9128, DoSubB, DB, SdB, 0, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9130, DoSubB, DB, SdB, 0, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9138, DoSubB, DB, SdB, 0, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9140, DoSubx, DW, SdW, ins7, DW, DR, Cd, 0, GRW, SRW, 4) +Oper (Op9148, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 0, GMW, SMW, 20) +Oper (Op9150, DoSubW, DW, SdW, 0, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9158, DoSubW, DW, SdW, 0, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9160, DoSubW, DW, SdW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9168, DoSubW, DW, SdW, 0, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9170, DoSubW, DW, SdW, 0, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9178, DoSubW, DW, SdW, 0, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9180, DoSubx, DL, SdL, ins7, DL, DR, Cd, 0, GRL, SRL, 8) +Oper (Op9188, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 0, GML, SML, 32) +Oper (Op9190, DoSubL, DL, SdL, 0, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9198, DoSubL, DL, SdL, 0, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op91a0, DoSubL, DL, SdL, 0, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op91a8, DoSubL, DL, SdL, 0, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op91b0, DoSubL, DL, SdL, 0, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op91b8, DoSubL, DL, SdL, 0, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op91c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Op91c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 0, GRL, SRL, 8) +Oper (Op91d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Op91d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Op91e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 0, GRL, SRL, 16) +Oper (Op91e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 0, GRL, SRL, 20) +Oper (Op91f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 0, GRL, SRL, 20) +Oper (Op91f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 0, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op9200, DoSubB, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4) +Oper (Op9210, DoSubB, DB, SainB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Op9218, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 1, GRB, SRB, 8) +Oper (Op9220, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Op9228, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 1, GRB, SRB, 12) +Oper (Op9230, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 1, GRB, SRB, 16) +Oper (Op9238, DoSubB, DB, SearB, ins7, DB, DR, Cd, 1, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9240, DoSubW, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Op9248, DoSubW, DW, SaW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Op9250, DoSubW, DW, SainW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Op9258, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 1, GRW, SRW, 8) +Oper (Op9260, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Op9268, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 1, GRW, SRW, 12) +Oper (Op9270, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 1, GRW, SRW, 16) +Oper (Op9278, DoSubW, DW, SearW, ins7, DW, DR, Cd, 1, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9280, DoSubL, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Op9288, DoSubL, DL, SaL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Op9290, DoSubL, DL, SainL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Op9298, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Op92a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 16) +Oper (Op92a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Op92b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 1, GRL, SRL, 20) +Oper (Op92b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 1, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op92c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Op92c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Op92d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 1, GRL, SRL, 12) +Oper (Op92d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 1, GRL, SRL, 12) +Oper (Op92e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Op92e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Op92f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 1, GRL, SRL, 20) +Oper (Op92f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 1, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9300, DoSubx, DB, SdB, ins7, DB, DR, Cd, 1, GRB, SRB, 4) +Oper (Op9308, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 1, GMB, SMB, 20) +Oper (Op9310, DoSubB, DB, SdB, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9318, DoSubB, DB, SdB, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9320, DoSubB, DB, SdB, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9328, DoSubB, DB, SdB, 1, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9330, DoSubB, DB, SdB, 1, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9338, DoSubB, DB, SdB, 1, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9340, DoSubx, DW, SdW, ins7, DW, DR, Cd, 1, GRW, SRW, 4) +Oper (Op9348, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 1, GMW, SMW, 20) +Oper (Op9350, DoSubW, DW, SdW, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9358, DoSubW, DW, SdW, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9360, DoSubW, DW, SdW, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9368, DoSubW, DW, SdW, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9370, DoSubW, DW, SdW, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9378, DoSubW, DW, SdW, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9380, DoSubx, DL, SdL, ins7, DL, DR, Cd, 1, GRL, SRL, 8) +Oper (Op9388, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 1, GML, SML, 32) +Oper (Op9390, DoSubL, DL, SdL, 1, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9398, DoSubL, DL, SdL, 1, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op93a0, DoSubL, DL, SdL, 1, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op93a8, DoSubL, DL, SdL, 1, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op93b0, DoSubL, DL, SdL, 1, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op93b8, DoSubL, DL, SdL, 1, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op93c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Op93c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 1, GRL, SRL, 8) +Oper (Op93d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Op93d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Op93e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 1, GRL, SRL, 16) +Oper (Op93e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 1, GRL, SRL, 20) +Oper (Op93f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 1, GRL, SRL, 20) +Oper (Op93f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 1, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op9400, DoSubB, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4) +Oper (Op9410, DoSubB, DB, SainB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Op9418, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 2, GRB, SRB, 8) +Oper (Op9420, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Op9428, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 2, GRB, SRB, 12) +Oper (Op9430, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 2, GRB, SRB, 16) +Oper (Op9438, DoSubB, DB, SearB, ins7, DB, DR, Cd, 2, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9440, DoSubW, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Op9448, DoSubW, DW, SaW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Op9450, DoSubW, DW, SainW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Op9458, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 2, GRW, SRW, 8) +Oper (Op9460, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Op9468, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 2, GRW, SRW, 12) +Oper (Op9470, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 2, GRW, SRW, 16) +Oper (Op9478, DoSubW, DW, SearW, ins7, DW, DR, Cd, 2, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9480, DoSubL, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Op9488, DoSubL, DL, SaL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Op9490, DoSubL, DL, SainL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Op9498, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Op94a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 16) +Oper (Op94a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Op94b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 2, GRL, SRL, 20) +Oper (Op94b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 2, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op94c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Op94c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Op94d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 2, GRL, SRL, 12) +Oper (Op94d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 2, GRL, SRL, 12) +Oper (Op94e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Op94e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Op94f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 2, GRL, SRL, 20) +Oper (Op94f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 2, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9500, DoSubx, DB, SdB, ins7, DB, DR, Cd, 2, GRB, SRB, 4) +Oper (Op9508, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 2, GMB, SMB, 20) +Oper (Op9510, DoSubB, DB, SdB, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9518, DoSubB, DB, SdB, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9520, DoSubB, DB, SdB, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9528, DoSubB, DB, SdB, 2, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9530, DoSubB, DB, SdB, 2, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9538, DoSubB, DB, SdB, 2, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9540, DoSubx, DW, SdW, ins7, DW, DR, Cd, 2, GRW, SRW, 4) +Oper (Op9548, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 2, GMW, SMW, 20) +Oper (Op9550, DoSubW, DW, SdW, 2, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9558, DoSubW, DW, SdW, 2, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9560, DoSubW, DW, SdW, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9568, DoSubW, DW, SdW, 2, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9570, DoSubW, DW, SdW, 2, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9578, DoSubW, DW, SdW, 2, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9580, DoSubx, DL, SdL, ins7, DL, DR, Cd, 2, GRL, SRL, 8) +Oper (Op9588, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 2, GML, SML, 32) +Oper (Op9590, DoSubL, DL, SdL, 2, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9598, DoSubL, DL, SdL, 2, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op95a0, DoSubL, DL, SdL, 2, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op95a8, DoSubL, DL, SdL, 2, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op95b0, DoSubL, DL, SdL, 2, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op95b8, DoSubL, DL, SdL, 2, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op95c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Op95c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 2, GRL, SRL, 8) +Oper (Op95d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Op95d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Op95e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 2, GRL, SRL, 16) +Oper (Op95e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 2, GRL, SRL, 20) +Oper (Op95f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 2, GRL, SRL, 20) +Oper (Op95f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 2, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op9600, DoSubB, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4) +Oper (Op9610, DoSubB, DB, SainB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Op9618, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 3, GRB, SRB, 8) +Oper (Op9620, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Op9628, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 3, GRB, SRB, 12) +Oper (Op9630, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 3, GRB, SRB, 16) +Oper (Op9638, DoSubB, DB, SearB, ins7, DB, DR, Cd, 3, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9640, DoSubW, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Op9648, DoSubW, DW, SaW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Op9650, DoSubW, DW, SainW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Op9658, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 3, GRW, SRW, 8) +Oper (Op9660, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Op9668, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 3, GRW, SRW, 12) +Oper (Op9670, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 3, GRW, SRW, 16) +Oper (Op9678, DoSubW, DW, SearW, ins7, DW, DR, Cd, 3, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9680, DoSubL, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Op9688, DoSubL, DL, SaL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Op9690, DoSubL, DL, SainL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Op9698, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Op96a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 16) +Oper (Op96a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Op96b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 3, GRL, SRL, 20) +Oper (Op96b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 3, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op96c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Op96c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Op96d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 3, GRL, SRL, 12) +Oper (Op96d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 3, GRL, SRL, 12) +Oper (Op96e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Op96e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Op96f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 3, GRL, SRL, 20) +Oper (Op96f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 3, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9700, DoSubx, DB, SdB, ins7, DB, DR, Cd, 3, GRB, SRB, 4) +Oper (Op9708, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 3, GMB, SMB, 20) +Oper (Op9710, DoSubB, DB, SdB, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9718, DoSubB, DB, SdB, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9720, DoSubB, DB, SdB, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9728, DoSubB, DB, SdB, 3, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9730, DoSubB, DB, SdB, 3, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9738, DoSubB, DB, SdB, 3, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9740, DoSubx, DW, SdW, ins7, DW, DR, Cd, 3, GRW, SRW, 4) +Oper (Op9748, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 3, GMW, SMW, 20) +Oper (Op9750, DoSubW, DW, SdW, 3, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9758, DoSubW, DW, SdW, 3, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9760, DoSubW, DW, SdW, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9768, DoSubW, DW, SdW, 3, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9770, DoSubW, DW, SdW, 3, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9778, DoSubW, DW, SdW, 3, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9780, DoSubx, DL, SdL, ins7, DL, DR, Cd, 3, GRL, SRL, 8) +Oper (Op9788, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 3, GML, SML, 32) +Oper (Op9790, DoSubL, DL, SdL, 3, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9798, DoSubL, DL, SdL, 3, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op97a0, DoSubL, DL, SdL, 3, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op97a8, DoSubL, DL, SdL, 3, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op97b0, DoSubL, DL, SdL, 3, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op97b8, DoSubL, DL, SdL, 3, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op97c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Op97c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 3, GRL, SRL, 8) +Oper (Op97d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Op97d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Op97e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 3, GRL, SRL, 16) +Oper (Op97e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 3, GRL, SRL, 20) +Oper (Op97f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 3, GRL, SRL, 20) +Oper (Op97f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 3, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op9800, DoSubB, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4) +Oper (Op9810, DoSubB, DB, SainB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Op9818, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 4, GRB, SRB, 8) +Oper (Op9820, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Op9828, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 4, GRB, SRB, 12) +Oper (Op9830, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 4, GRB, SRB, 16) +Oper (Op9838, DoSubB, DB, SearB, ins7, DB, DR, Cd, 4, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9840, DoSubW, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Op9848, DoSubW, DW, SaW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Op9850, DoSubW, DW, SainW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Op9858, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 4, GRW, SRW, 8) +Oper (Op9860, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Op9868, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 4, GRW, SRW, 12) +Oper (Op9870, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 4, GRW, SRW, 16) +Oper (Op9878, DoSubW, DW, SearW, ins7, DW, DR, Cd, 4, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9880, DoSubL, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Op9888, DoSubL, DL, SaL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Op9890, DoSubL, DL, SainL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Op9898, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Op98a0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 16) +Oper (Op98a8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Op98b0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 4, GRL, SRL, 20) +Oper (Op98b8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 4, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op98c0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Op98c8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Op98d0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 4, GRL, SRL, 12) +Oper (Op98d8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 4, GRL, SRL, 12) +Oper (Op98e0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Op98e8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Op98f0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 4, GRL, SRL, 20) +Oper (Op98f8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 4, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9900, DoSubx, DB, SdB, ins7, DB, DR, Cd, 4, GRB, SRB, 4) +Oper (Op9908, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 4, GMB, SMB, 20) +Oper (Op9910, DoSubB, DB, SdB, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9918, DoSubB, DB, SdB, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9920, DoSubB, DB, SdB, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9928, DoSubB, DB, SdB, 4, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9930, DoSubB, DB, SdB, 4, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9938, DoSubB, DB, SdB, 4, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9940, DoSubx, DW, SdW, ins7, DW, DR, Cd, 4, GRW, SRW, 4) +Oper (Op9948, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 4, GMW, SMW, 20) +Oper (Op9950, DoSubW, DW, SdW, 4, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9958, DoSubW, DW, SdW, 4, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9960, DoSubW, DW, SdW, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9968, DoSubW, DW, SdW, 4, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9970, DoSubW, DW, SdW, 4, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9978, DoSubW, DW, SdW, 4, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9980, DoSubx, DL, SdL, ins7, DL, DR, Cd, 4, GRL, SRL, 8) +Oper (Op9988, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 4, GML, SML, 32) +Oper (Op9990, DoSubL, DL, SdL, 4, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9998, DoSubL, DL, SdL, 4, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op99a0, DoSubL, DL, SdL, 4, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op99a8, DoSubL, DL, SdL, 4, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op99b0, DoSubL, DL, SdL, 4, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op99b8, DoSubL, DL, SdL, 4, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op99c0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Op99c8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 4, GRL, SRL, 8) +Oper (Op99d0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Op99d8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Op99e0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 4, GRL, SRL, 16) +Oper (Op99e8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 4, GRL, SRL, 20) +Oper (Op99f0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 4, GRL, SRL, 20) +Oper (Op99f8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 4, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op9a00, DoSubB, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4) +Oper (Op9a10, DoSubB, DB, SainB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Op9a18, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 5, GRB, SRB, 8) +Oper (Op9a20, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Op9a28, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 5, GRB, SRB, 12) +Oper (Op9a30, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 5, GRB, SRB, 16) +Oper (Op9a38, DoSubB, DB, SearB, ins7, DB, DR, Cd, 5, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9a40, DoSubW, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Op9a48, DoSubW, DW, SaW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Op9a50, DoSubW, DW, SainW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Op9a58, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 5, GRW, SRW, 8) +Oper (Op9a60, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Op9a68, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 5, GRW, SRW, 12) +Oper (Op9a70, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 5, GRW, SRW, 16) +Oper (Op9a78, DoSubW, DW, SearW, ins7, DW, DR, Cd, 5, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9a80, DoSubL, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Op9a88, DoSubL, DL, SaL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Op9a90, DoSubL, DL, SainL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Op9a98, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Op9aa0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 16) +Oper (Op9aa8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Op9ab0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 5, GRL, SRL, 20) +Oper (Op9ab8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 5, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op9ac0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Op9ac8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Op9ad0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 5, GRL, SRL, 12) +Oper (Op9ad8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 5, GRL, SRL, 12) +Oper (Op9ae0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Op9ae8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Op9af0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 5, GRL, SRL, 20) +Oper (Op9af8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 5, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9b00, DoSubx, DB, SdB, ins7, DB, DR, Cd, 5, GRB, SRB, 4) +Oper (Op9b08, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 5, GMB, SMB, 20) +Oper (Op9b10, DoSubB, DB, SdB, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9b18, DoSubB, DB, SdB, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9b20, DoSubB, DB, SdB, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9b28, DoSubB, DB, SdB, 5, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9b30, DoSubB, DB, SdB, 5, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9b38, DoSubB, DB, SdB, 5, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9b40, DoSubx, DW, SdW, ins7, DW, DR, Cd, 5, GRW, SRW, 4) +Oper (Op9b48, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 5, GMW, SMW, 20) +Oper (Op9b50, DoSubW, DW, SdW, 5, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9b58, DoSubW, DW, SdW, 5, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9b60, DoSubW, DW, SdW, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9b68, DoSubW, DW, SdW, 5, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9b70, DoSubW, DW, SdW, 5, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9b78, DoSubW, DW, SdW, 5, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9b80, DoSubx, DL, SdL, ins7, DL, DR, Cd, 5, GRL, SRL, 8) +Oper (Op9b88, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 5, GML, SML, 32) +Oper (Op9b90, DoSubL, DL, SdL, 5, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9b98, DoSubL, DL, SdL, 5, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op9ba0, DoSubL, DL, SdL, 5, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op9ba8, DoSubL, DL, SdL, 5, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op9bb0, DoSubL, DL, SdL, 5, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op9bb8, DoSubL, DL, SdL, 5, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op9bc0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Op9bc8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 5, GRL, SRL, 8) +Oper (Op9bd0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Op9bd8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Op9be0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 5, GRL, SRL, 16) +Oper (Op9be8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 5, GRL, SRL, 20) +Oper (Op9bf0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 5, GRL, SRL, 20) +Oper (Op9bf8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 5, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op9c00, DoSubB, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4) +Oper (Op9c10, DoSubB, DB, SainB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Op9c18, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 6, GRB, SRB, 8) +Oper (Op9c20, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Op9c28, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 6, GRB, SRB, 12) +Oper (Op9c30, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 6, GRB, SRB, 16) +Oper (Op9c38, DoSubB, DB, SearB, ins7, DB, DR, Cd, 6, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9c40, DoSubW, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Op9c48, DoSubW, DW, SaW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Op9c50, DoSubW, DW, SainW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Op9c58, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 6, GRW, SRW, 8) +Oper (Op9c60, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Op9c68, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 6, GRW, SRW, 12) +Oper (Op9c70, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 6, GRW, SRW, 16) +Oper (Op9c78, DoSubW, DW, SearW, ins7, DW, DR, Cd, 6, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9c80, DoSubL, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Op9c88, DoSubL, DL, SaL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Op9c90, DoSubL, DL, SainL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Op9c98, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Op9ca0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 16) +Oper (Op9ca8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Op9cb0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 6, GRL, SRL, 20) +Oper (Op9cb8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 6, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op9cc0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Op9cc8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Op9cd0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 6, GRL, SRL, 12) +Oper (Op9cd8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 6, GRL, SRL, 12) +Oper (Op9ce0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Op9ce8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Op9cf0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 6, GRL, SRL, 20) +Oper (Op9cf8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 6, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9d00, DoSubx, DB, SdB, ins7, DB, DR, Cd, 6, GRB, SRB, 4) +Oper (Op9d08, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB, 6, GMB, SMB, 20) +Oper (Op9d10, DoSubB, DB, SdB, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9d18, DoSubB, DB, SdB, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9d20, DoSubB, DB, SdB, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9d28, DoSubB, DB, SdB, 6, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9d30, DoSubB, DB, SdB, 6, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9d38, DoSubB, DB, SdB, 6, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9d40, DoSubx, DW, SdW, ins7, DW, DR, Cd, 6, GRW, SRW, 4) +Oper (Op9d48, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 6, GMW, SMW, 20) +Oper (Op9d50, DoSubW, DW, SdW, 6, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9d58, DoSubW, DW, SdW, 6, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9d60, DoSubW, DW, SdW, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9d68, DoSubW, DW, SdW, 6, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9d70, DoSubW, DW, SdW, 6, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9d78, DoSubW, DW, SdW, 6, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9d80, DoSubx, DL, SdL, ins7, DL, DR, Cd, 6, GRL, SRL, 8) +Oper (Op9d88, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 6, GML, SML, 32) +Oper (Op9d90, DoSubL, DL, SdL, 6, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9d98, DoSubL, DL, SdL, 6, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op9da0, DoSubL, DL, SdL, 6, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op9da8, DoSubL, DL, SdL, 6, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op9db0, DoSubL, DL, SdL, 6, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op9db8, DoSubL, DL, SdL, 6, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op9dc0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Op9dc8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 6, GRL, SRL, 8) +Oper (Op9dd0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Op9dd8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Op9de0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 6, GRL, SRL, 16) +Oper (Op9de8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 6, GRL, SRL, 20) +Oper (Op9df0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 6, GRL, SRL, 20) +Oper (Op9df8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 6, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op9e00, DoSubB, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4) +Oper (Op9e10, DoSubB, DB, SainB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Op9e18, DoSubB, DB, SaipB, ins7, DB, DR, Cd, 7, GRB, SRB, 8) +Oper (Op9e20, DoSubB, DB, SmaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Op9e28, DoSubB, DB, SdaiB, ins7, DB, DR, Cd, 7, GRB, SRB, 12) +Oper (Op9e30, DoSubB, DB, SaixB, ins7, DB, DR, Cd, 7, GRB, SRB, 16) +Oper (Op9e38, DoSubB, DB, SearB, ins7, DB, DR, Cd, 7, GRB, SRB, (cycles+11)&0xfffffffc) +Oper (Op9e40, DoSubW, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Op9e48, DoSubW, DW, SaW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Op9e50, DoSubW, DW, SainW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Op9e58, DoSubW, DW, SaipW, ins7, DW, DR, Cd, 7, GRW, SRW, 8) +Oper (Op9e60, DoSubW, DW, SmaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Op9e68, DoSubW, DW, SdaiW, ins7, DW, DR, Cd, 7, GRW, SRW, 12) +Oper (Op9e70, DoSubW, DW, SaixW, ins7, DW, DR, Cd, 7, GRW, SRW, 16) +Oper (Op9e78, DoSubW, DW, SearW, ins7, DW, DR, Cd, 7, GRW, SRW, (cycles+11)&0xfffffffc) +Oper (Op9e80, DoSubL, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Op9e88, DoSubL, DL, SaL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Op9e90, DoSubL, DL, SainL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Op9e98, DoSubL, DL, SaipL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Op9ea0, DoSubL, DL, SmaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 16) +Oper (Op9ea8, DoSubL, DL, SdaiL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Op9eb0, DoSubL, DL, SaixL, ins7, DL, DR, Cd, 7, GRL, SRL, 20) +Oper (Op9eb8, DoSubL, DL, SearL, ins7, DL, DR, Cd, 7, GRL, SRL, (cycles+19)&0xfffffffc) +Oper (Op9ec0, DoSuba, DL, SdW, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Op9ec8, DoSuba, DL, SaW, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Op9ed0, DoSuba, DL, SainW, ins7, DL, DR, Ca, 7, GRL, SRL, 12) +Oper (Op9ed8, DoSuba, DL, SaipW, ins7, DL, DR, Ca, 7, GRL, SRL, 12) +Oper (Op9ee0, DoSuba, DL, SmaiW, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Op9ee8, DoSuba, DL, SdaiW, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Op9ef0, DoSuba, DL, SaixW, ins7, DL, DR, Ca, 7, GRL, SRL, 20) +Oper (Op9ef8, DoSuba, DL, SearW, ins7, DL, DR, Ca, 7, GRL, SRL, (cycles+15)&0xfffffffc) + +Oper (Op9f00, DoSubx, DB, SdB, ins7, DB, DR, Cd, 7, GRB, SRB, 4) +Oper (Op9f08, DoSubx, DB, SmaiB, ins7, DB, DA, CmaiB15, 7, GMB, SMB, 20) +Oper (Op9f10, DoSubB, DB, SdB, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op9f18, DoSubB, DB, SdB, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op9f20, DoSubB, DB, SdB, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op9f28, DoSubB, DB, SdB, 7, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op9f30, DoSubB, DB, SdB, 7, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op9f38, DoSubB, DB, SdB, 7, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op9f40, DoSubx, DW, SdW, ins7, DW, DR, Cd, 7, GRW, SRW, 4) +Oper (Op9f48, DoSubx, DW, SmaiW, ins7, DW, DA, CmaiW, 7, GMW, SMW, 20) +Oper (Op9f50, DoSubW, DW, SdW, 7, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op9f58, DoSubW, DW, SdW, 7, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op9f60, DoSubW, DW, SdW, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op9f68, DoSubW, DW, SdW, 7, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op9f70, DoSubW, DW, SdW, 7, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op9f78, DoSubW, DW, SdW, 7, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op9f80, DoSubx, DL, SdL, ins7, DL, DR, Cd, 7, GRL, SRL, 8) +Oper (Op9f88, DoSubx, DL, SmaiL, ins7, DL, DA, CmaiL, 7, GML, SML, 32) +Oper (Op9f90, DoSubL, DL, SdL, 7, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op9f98, DoSubL, DL, SdL, 7, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op9fa0, DoSubL, DL, SdL, 7, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op9fa8, DoSubL, DL, SdL, 7, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op9fb0, DoSubL, DL, SdL, 7, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op9fb8, DoSubL, DL, SdL, 7, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) +Oper (Op9fc0, DoSuba, DL, SdL, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Op9fc8, DoSuba, DL, SaL, ins7, DL, DR, Ca, 7, GRL, SRL, 8) +Oper (Op9fd0, DoSuba, DL, SainL, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Op9fd8, DoSuba, DL, SaipL, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Op9fe0, DoSuba, DL, SmaiL, ins7, DL, DR, Ca, 7, GRL, SRL, 16) +Oper (Op9fe8, DoSuba, DL, SdaiL, ins7, DL, DR, Ca, 7, GRL, SRL, 20) +Oper (Op9ff0, DoSuba, DL, SaixL, ins7, DL, DR, Ca, 7, GRL, SRL, 20) +Oper (Op9ff8, DoSuba, DL, SearL, ins7, DL, DR, Ca, 7, GRL, SRL, (cycles+19)&0xfffffffc) + +Oper (Op0400, DoSubB, DB, SimmB, 0, DB, DR, Cd, ins7, GRB, SRB, 8) +Oper (Op0410, DoSubB, DB, SimmB, 0, DB, DA, Cain, ins7, GMB, SMB, 16) +Oper (Op0418, DoSubB, DB, SimmB, 0, DB, DA, CaipB, ins7, GMB, SMB, 16) +Oper (Op0420, DoSubB, DB, SimmB, 0, DB, DA, CmaiB, ins7, GMB, SMB, 20) +Oper (Op0428, DoSubB, DB, SimmB, 0, DB, DA, Cdai, ins7, GMB, SMB, 20) +Oper (Op0430, DoSubB, DB, SimmB, 0, DB, DA, Caix, ins7, GMB, SMB, 24) +Oper (Op0438, DoSubB, DB, SimmB, 0, DB, DA, Ceaw, ins7, GMB, SMB, (cycles+23)&0xfffffffc) +Oper (Op0440, DoSubW, DW, SimmW, 0, DW, DR, Cd, ins7, GRW, SRW, 8) +Oper (Op0450, DoSubW, DW, SimmW, 0, DW, DA, Cain, ins7, GMW, SMW, 16) +Oper (Op0458, DoSubW, DW, SimmW, 0, DW, DA, CaipW, ins7, GMW, SMW, 16) +Oper (Op0460, DoSubW, DW, SimmW, 0, DW, DA, CmaiW, ins7, GMW, SMW, 20) +Oper (Op0468, DoSubW, DW, SimmW, 0, DW, DA, Cdai, ins7, GMW, SMW, 20) +Oper (Op0470, DoSubW, DW, SimmW, 0, DW, DA, Caix, ins7, GMW, SMW, 24) +Oper (Op0478, DoSubW, DW, SimmW, 0, DW, DA, Ceaw, ins7, GMW, SMW, (cycles+23)&0xfffffffc) +Oper (Op0480, DoSubL, DL, SimmL, 0, DL, DR, Cd, ins7, GRL, SRL, 16) +Oper (Op0490, DoSubL, DL, SimmL, 0, DL, DA, Cain, ins7, GML, SML, 28) +Oper (Op0498, DoSubL, DL, SimmL, 0, DL, DA, CaipL, ins7, GML, SML, 28) +Oper (Op04a0, DoSubL, DL, SimmL, 0, DL, DA, CmaiL, ins7, GML, SML, 32) +Oper (Op04a8, DoSubL, DL, SimmL, 0, DL, DA, Cdai, ins7, GML, SML, 32) +Oper (Op04b0, DoSubL, DL, SimmL, 0, DL, DA, Caix, ins7, GML, SML, 36) +Oper (Op04b8, DoSubL, DL, SimmL, 0, DL, DA, Ceaw, ins7, GML, SML, (cycles+35)&0xfffffffc) + +Oper (Op5100, DoSubB, DB, Ss, 8, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5110, DoSubB, DB, Ss, 8, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5118, DoSubB, DB, Ss, 8, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5120, DoSubB, DB, Ss, 8, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5128, DoSubB, DB, Ss, 8, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5130, DoSubB, DB, Ss, 8, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5138, DoSubB, DB, Ss, 8, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5140, DoSubW, DW, Ss, 8, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5148, DoSuba, DL, Ss, 8, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5150, DoSubW, DW, Ss, 8, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5158, DoSubW, DW, Ss, 8, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5160, DoSubW, DW, Ss, 8, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5168, DoSubW, DW, Ss, 8, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5170, DoSubW, DW, Ss, 8, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5178, DoSubW, DW, Ss, 8, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5180, DoSubL, DL, Ss, 8, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5188, DoSuba, DL, Ss, 8, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5190, DoSubL, DL, Ss, 8, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5198, DoSubL, DL, Ss, 8, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op51a0, DoSubL, DL, Ss, 8, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op51a8, DoSubL, DL, Ss, 8, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op51b0, DoSubL, DL, Ss, 8, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op51b8, DoSubL, DL, Ss, 8, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5300, DoSubB, DB, Ss, 1, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5310, DoSubB, DB, Ss, 1, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5318, DoSubB, DB, Ss, 1, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5320, DoSubB, DB, Ss, 1, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5328, DoSubB, DB, Ss, 1, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5330, DoSubB, DB, Ss, 1, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5338, DoSubB, DB, Ss, 1, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5340, DoSubW, DW, Ss, 1, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5348, DoSuba, DL, Ss, 1, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5350, DoSubW, DW, Ss, 1, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5358, DoSubW, DW, Ss, 1, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5360, DoSubW, DW, Ss, 1, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5368, DoSubW, DW, Ss, 1, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5370, DoSubW, DW, Ss, 1, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5378, DoSubW, DW, Ss, 1, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5380, DoSubL, DL, Ss, 1, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5388, DoSuba, DL, Ss, 1, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5390, DoSubL, DL, Ss, 1, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5398, DoSubL, DL, Ss, 1, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op53a0, DoSubL, DL, Ss, 1, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op53a8, DoSubL, DL, Ss, 1, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op53b0, DoSubL, DL, Ss, 1, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op53b8, DoSubL, DL, Ss, 1, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5500, DoSubB, DB, Ss, 2, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5510, DoSubB, DB, Ss, 2, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5518, DoSubB, DB, Ss, 2, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5520, DoSubB, DB, Ss, 2, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5528, DoSubB, DB, Ss, 2, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5530, DoSubB, DB, Ss, 2, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5538, DoSubB, DB, Ss, 2, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5540, DoSubW, DW, Ss, 2, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5548, DoSuba, DL, Ss, 2, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5550, DoSubW, DW, Ss, 2, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5558, DoSubW, DW, Ss, 2, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5560, DoSubW, DW, Ss, 2, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5568, DoSubW, DW, Ss, 2, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5570, DoSubW, DW, Ss, 2, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5578, DoSubW, DW, Ss, 2, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5580, DoSubL, DL, Ss, 2, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5588, DoSuba, DL, Ss, 2, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5590, DoSubL, DL, Ss, 2, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5598, DoSubL, DL, Ss, 2, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op55a0, DoSubL, DL, Ss, 2, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op55a8, DoSubL, DL, Ss, 2, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op55b0, DoSubL, DL, Ss, 2, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op55b8, DoSubL, DL, Ss, 2, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5700, DoSubB, DB, Ss, 3, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5710, DoSubB, DB, Ss, 3, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5718, DoSubB, DB, Ss, 3, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5720, DoSubB, DB, Ss, 3, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5728, DoSubB, DB, Ss, 3, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5730, DoSubB, DB, Ss, 3, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5738, DoSubB, DB, Ss, 3, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5740, DoSubW, DW, Ss, 3, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5748, DoSuba, DL, Ss, 3, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5750, DoSubW, DW, Ss, 3, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5758, DoSubW, DW, Ss, 3, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5760, DoSubW, DW, Ss, 3, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5768, DoSubW, DW, Ss, 3, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5770, DoSubW, DW, Ss, 3, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5778, DoSubW, DW, Ss, 3, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5780, DoSubL, DL, Ss, 3, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5788, DoSuba, DL, Ss, 3, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5790, DoSubL, DL, Ss, 3, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5798, DoSubL, DL, Ss, 3, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op57a0, DoSubL, DL, Ss, 3, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op57a8, DoSubL, DL, Ss, 3, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op57b0, DoSubL, DL, Ss, 3, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op57b8, DoSubL, DL, Ss, 3, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5900, DoSubB, DB, Ss, 4, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5910, DoSubB, DB, Ss, 4, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5918, DoSubB, DB, Ss, 4, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5920, DoSubB, DB, Ss, 4, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5928, DoSubB, DB, Ss, 4, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5930, DoSubB, DB, Ss, 4, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5938, DoSubB, DB, Ss, 4, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5940, DoSubW, DW, Ss, 4, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5948, DoSuba, DL, Ss, 4, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5950, DoSubW, DW, Ss, 4, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5958, DoSubW, DW, Ss, 4, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5960, DoSubW, DW, Ss, 4, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5968, DoSubW, DW, Ss, 4, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5970, DoSubW, DW, Ss, 4, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5978, DoSubW, DW, Ss, 4, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5980, DoSubL, DL, Ss, 4, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5988, DoSuba, DL, Ss, 4, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5990, DoSubL, DL, Ss, 4, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5998, DoSubL, DL, Ss, 4, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op59a0, DoSubL, DL, Ss, 4, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op59a8, DoSubL, DL, Ss, 4, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op59b0, DoSubL, DL, Ss, 4, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op59b8, DoSubL, DL, Ss, 4, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5b00, DoSubB, DB, Ss, 5, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5b10, DoSubB, DB, Ss, 5, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5b18, DoSubB, DB, Ss, 5, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5b20, DoSubB, DB, Ss, 5, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5b28, DoSubB, DB, Ss, 5, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5b30, DoSubB, DB, Ss, 5, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5b38, DoSubB, DB, Ss, 5, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5b40, DoSubW, DW, Ss, 5, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5b48, DoSuba, DL, Ss, 5, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5b50, DoSubW, DW, Ss, 5, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5b58, DoSubW, DW, Ss, 5, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5b60, DoSubW, DW, Ss, 5, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5b68, DoSubW, DW, Ss, 5, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5b70, DoSubW, DW, Ss, 5, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5b78, DoSubW, DW, Ss, 5, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5b80, DoSubL, DL, Ss, 5, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5b88, DoSuba, DL, Ss, 5, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5b90, DoSubL, DL, Ss, 5, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5b98, DoSubL, DL, Ss, 5, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op5ba0, DoSubL, DL, Ss, 5, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op5ba8, DoSubL, DL, Ss, 5, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op5bb0, DoSubL, DL, Ss, 5, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op5bb8, DoSubL, DL, Ss, 5, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5d00, DoSubB, DB, Ss, 6, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5d10, DoSubB, DB, Ss, 6, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5d18, DoSubB, DB, Ss, 6, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5d20, DoSubB, DB, Ss, 6, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5d28, DoSubB, DB, Ss, 6, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5d30, DoSubB, DB, Ss, 6, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5d38, DoSubB, DB, Ss, 6, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5d40, DoSubW, DW, Ss, 6, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5d48, DoSuba, DL, Ss, 6, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5d50, DoSubW, DW, Ss, 6, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5d58, DoSubW, DW, Ss, 6, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5d60, DoSubW, DW, Ss, 6, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5d68, DoSubW, DW, Ss, 6, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5d70, DoSubW, DW, Ss, 6, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5d78, DoSubW, DW, Ss, 6, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5d80, DoSubL, DL, Ss, 6, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5d88, DoSuba, DL, Ss, 6, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5d90, DoSubL, DL, Ss, 6, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5d98, DoSubL, DL, Ss, 6, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op5da0, DoSubL, DL, Ss, 6, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op5da8, DoSubL, DL, Ss, 6, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op5db0, DoSubL, DL, Ss, 6, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op5db8, DoSubL, DL, Ss, 6, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) + +Oper (Op5f00, DoSubB, DB, Ss, 7, DB, DR, Cd, ins7, GRB, SRB, 4) +Oper (Op5f10, DoSubB, DB, Ss, 7, DB, DA, Cain, ins7, GMB, SMB, 12) +Oper (Op5f18, DoSubB, DB, Ss, 7, DB, DA, CaipB, ins7, GMB, SMB, 12) +Oper (Op5f20, DoSubB, DB, Ss, 7, DB, DA, CmaiB, ins7, GMB, SMB, 16) +Oper (Op5f28, DoSubB, DB, Ss, 7, DB, DA, Fdai, ins7, GMB, SMB, 16) +Oper (Op5f30, DoSubB, DB, Ss, 7, DB, DA, Faix, ins7, GMB, SMB, 20) +Oper (Op5f38, DoSubB, DB, Ss, 7, DB, DA, Feaw, ins7, GMB, SMB, (cycles+19)&0xfffffffc) +Oper (Op5f40, DoSubW, DW, Ss, 7, DW, DR, Cd, ins7, GRW, SRW, 4) +Oper (Op5f48, DoSuba, DL, Ss, 7, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5f50, DoSubW, DW, Ss, 7, DW, DA, Cain, ins7, GMW, SMW, 12) +Oper (Op5f58, DoSubW, DW, Ss, 7, DW, DA, CaipW, ins7, GMW, SMW, 12) +Oper (Op5f60, DoSubW, DW, Ss, 7, DW, DA, CmaiW, ins7, GMW, SMW, 16) +Oper (Op5f68, DoSubW, DW, Ss, 7, DW, DA, Fdai, ins7, GMW, SMW, 16) +Oper (Op5f70, DoSubW, DW, Ss, 7, DW, DA, Faix, ins7, GMW, SMW, 20) +Oper (Op5f78, DoSubW, DW, Ss, 7, DW, DA, Feaw, ins7, GMW, SMW, (cycles+19)&0xfffffffc) +Oper (Op5f80, DoSubL, DL, Ss, 7, DL, DR, Cd, ins7, GRL, SRL, 8) +Oper (Op5f88, DoSuba, DL, Ss, 7, DL, DR, Ca, ins7, GRL, SRL, 8) +Oper (Op5f90, DoSubL, DL, Ss, 7, DL, DA, Cain, ins7, GML, SML, 20) +Oper (Op5f98, DoSubL, DL, Ss, 7, DL, DA, CaipL, ins7, GML, SML, 20) +Oper (Op5fa0, DoSubL, DL, Ss, 7, DL, DA, CmaiL, ins7, GML, SML, 24) +Oper (Op5fa8, DoSubL, DL, Ss, 7, DL, DA, Fdai, ins7, GML, SML, 24) +Oper (Op5fb0, DoSubL, DL, Ss, 7, DL, DA, Faix, ins7, GML, SML, 28) +Oper (Op5fb8, DoSubL, DL, Ss, 7, DL, DA, Feaw, ins7, GML, SML, (cycles+27)&0xfffffffc) diff --git a/MCUME_esp32/espcastaway/main/68korigbad/operin.h b/MCUME_esp32/espcastaway/main/68korigbad/operin.h new file mode 100755 index 0000000..8fe87c2 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/operin.h @@ -0,0 +1 @@ +#define operin unsigned long *reg diff --git a/MCUME_esp32/espcastaway/main/68korigbad/proto.h b/MCUME_esp32/espcastaway/main/68korigbad/proto.h new file mode 100755 index 0000000..afc3d3d --- /dev/null +++ b/MCUME_esp32/espcastaway/main/68korigbad/proto.h @@ -0,0 +1,99 @@ +/* + * proto.h - FAST 68000 emulator instruction prototypes + * Version 1.0 + * Copyright (C) 1994, 1995 Joachim Hönig + * (hoenig@informatik.uni-erlangen.de) + * + * This file is part of FAST, the Fine Atari ST Emulator. + * + * FAST is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * FAST is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with FAST; see the file COPYING. If not, write to + * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Prototypes of all 68000 opcodes defined in op68k*.c + */ + +#include "operin.h" + +#undef Oper +#define Oper(a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12) \ + extern unsigned long a1(operin); + +#define PROTOH + +#include "op68kadd.cpp" +#include "op68karith.cpp" +#include "op68ksub.cpp" +#include "op68klogop.cpp" +#include "op68kmisc.cpp" +#include "op68kmove.cpp" +#include "op68kshift.cpp" + +extern unsigned long Op4840(operin); /* SWAP */ +extern unsigned long Op4848(operin); /* BKPT */ +extern unsigned long Op4880(operin); /* EXT.W */ +extern unsigned long Op4890(operin); /* MOVEM.W to (ax) */ +extern unsigned long Op48a0(operin); /* MOVEM.W to -(ax) */ +extern unsigned long Op48a8(operin); /* MOVEM.W to d(ax) */ +extern unsigned long Op48b0(operin); /* MOVEM.W to d(ax,rx) */ +extern unsigned long Op48b8(operin); /* MOVEM.W to w l */ +extern unsigned long Op48c0(operin); /* EXT.L */ +extern unsigned long Op48d0(operin); /* MOVEM.L to (ax) */ +extern unsigned long Op48e0(operin); /* MOVEM.L to -(ax) */ +extern unsigned long Op48e8(operin); /* MOVEM.L to d(ax) */ +extern unsigned long Op48f0(operin); /* MOVEM.L to d(ax,rx) */ +extern unsigned long Op48f8(operin); /* MOVEM.L to w l */ +extern unsigned long Op4c90(operin); /* MOVEM.W from (ax) */ +extern unsigned long Op4c98(operin); /* MOVEM.W from (ax)+ */ +extern unsigned long Op4ca8(operin); /* MOVEM.W from d(ax) */ +extern unsigned long Op4cb0(operin); /* MOVEM.W from d(ax,rx) */ +extern unsigned long Op4cb8(operin); /* MOVEM.W from ea */ +extern unsigned long Op4cd0(operin); /* MOVEM.L from (ax) */ +extern unsigned long Op4cd8(operin); /* MOVEM.L from (ax)+ */ +extern unsigned long Op4ce8(operin); /* MOVEM.L from d(ax) */ +extern unsigned long Op4cf0(operin); /* MOVEM.L from d(ax,rx) */ +extern unsigned long Op4cf8(operin); /* MOVEM.L from ea */ +extern unsigned long Op4e40(operin); /* TRAP */ +extern unsigned long Op4e50(operin); /* LINK */ +extern unsigned long Op4e58(operin); /* UNLK */ +extern unsigned long Op4e60(operin); /* MOVE ax,usp */ +extern unsigned long Op4e68(operin); /* MOVE usp,ax */ +extern unsigned long Op4e70(operin); /* RESET, NOP, STOP, RTE, + * RTD, RTS, TRAPV, RTR */ +extern unsigned long Op4e78(operin); /* MOVEC */ + +extern unsigned long Opc140(operin); /* EXG */ +extern unsigned long Opc148(operin); /* EXG */ +extern unsigned long Opc188(operin); /* EXG */ +extern unsigned long Opc340(operin); /* EXG */ +extern unsigned long Opc348(operin); /* EXG */ +extern unsigned long Opc388(operin); /* EXG */ +extern unsigned long Opc540(operin); /* EXG */ +extern unsigned long Opc548(operin); /* EXG */ +extern unsigned long Opc588(operin); /* EXG */ +extern unsigned long Opc740(operin); /* EXG */ +extern unsigned long Opc748(operin); /* EXG */ +extern unsigned long Opc788(operin); /* EXG */ +extern unsigned long Opc940(operin); /* EXG */ +extern unsigned long Opc948(operin); /* EXG */ +extern unsigned long Opc988(operin); /* EXG */ +extern unsigned long Opcb40(operin); /* EXG */ +extern unsigned long Opcb48(operin); /* EXG */ +extern unsigned long Opcb88(operin); /* EXG */ +extern unsigned long Opcd40(operin); /* EXG */ +extern unsigned long Opcd48(operin); /* EXG */ +extern unsigned long Opcd88(operin); /* EXG */ +extern unsigned long Opcf40(operin); /* EXG */ +extern unsigned long Opcf48(operin); /* EXG */ +extern unsigned long Opcf88(operin); /* EXG */ diff --git a/MCUME_esp32/espcastaway/main/AudioPlaySystem.cpp b/MCUME_esp32/espcastaway/main/AudioPlaySystem.cpp new file mode 100644 index 0000000..c3f0697 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/AudioPlaySystem.cpp @@ -0,0 +1,290 @@ +extern "C" { +#include "emuapi.h" +} + +#ifdef HAS_SND +#include "AudioPlaySystem.h" +#include "esp_system.h" + +#define USE_I2S 1 + +#ifdef USE_I2S +#include "esp_event.h" +#include "driver/i2s.h" +#include "freertos/queue.h" +#include "string.h" +#define I2S_NUM ((i2s_port_t)0) +//static QueueHandle_t queue; +#else +#include "esp32-hal-timer.h" +#include "esp32-hal-dac.h" +static int32_t LastPlayPos=0; +volatile int32_t NextPlayPos=0; +volatile uint8_t DacPin; +uint16_t LastDacValue; +hw_timer_t * timer = NULL; +#endif + +volatile uint16_t *Buffer; +volatile uint16_t BufferSize; + + +static const short square[]={ +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +}; + +const short noise[] { +-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,-32767,32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,-32767,-32767, +32767,-32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767,-32767, +32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,32767,32767,-32767,32767,-32767,32767,-32767,-32767, +32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,32767,-32767,32767,-32767,-32767, +}; + +#define NOISEBSIZE 0x100 + +typedef struct +{ + unsigned int spos; + unsigned int sinc; + unsigned int vol; +} Channel; + +volatile bool playing = false; + + +static Channel chan[6] = { + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0} }; + + +static void snd_Reset(void) +{ + chan[0].vol = 0; + chan[1].vol = 0; + chan[2].vol = 0; + chan[3].vol = 0; + chan[4].vol = 0; + chan[5].vol = 0; + chan[0].sinc = 0; + chan[1].sinc = 0; + chan[2].sinc = 0; + chan[3].sinc = 0; + chan[4].sinc = 0; + chan[5].sinc = 0; +} + +#ifdef CUSTOM_SND +//extern "C" { +void SND_Process(void *sndbuffer, int sndn); +//} +#endif + + +static void snd_Mixer16(uint16_t * stream, int len ) +{ + if (playing) + { +#ifdef CUSTOM_SND + SND_Process((void*)stream, len); +#else + int i; + long s; + //len = len >> 1; + + short v0=chan[0].vol; + short v1=chan[1].vol; + short v2=chan[2].vol; + short v3=chan[3].vol; + short v4=chan[4].vol; + short v5=chan[5].vol; + for (i=0;i>8)&0x3f]) ); + s+= ( v1*(square[(chan[1].spos>>8)&0x3f]) ); + s+= ( v2*(square[(chan[2].spos>>8)&0x3f]) ); + s+= ( v3*(noise[(chan[3].spos>>8)&(NOISEBSIZE-1)]) ); + s+= ( v4*(noise[(chan[4].spos>>8)&(NOISEBSIZE-1)]) ); + s+= ( v5*(noise[(chan[5].spos>>8)&(NOISEBSIZE-1)]) ); + *stream++ = int16_t((s>>11)); + chan[0].spos += chan[0].sinc; + chan[1].spos += chan[1].sinc; + chan[2].spos += chan[2].sinc; + chan[3].spos += chan[3].sinc; + chan[4].spos += chan[4].sinc; + chan[5].spos += chan[5].sinc; + } +#endif + } +} + +#ifdef USE_I2S +#else +void IRAM_ATTR onTimer() +{ + // Sound playing code, plays whatever's in the buffer continuously. Big change from previous versions + if(LastDacValue!=Buffer[NextPlayPos]) // Send value to DAC only of changed since last value else no need + { + // value to DAC has changed, send to actual hardware, else we just leave setting as is as it's not changed + LastDacValue=Buffer[NextPlayPos]; + dacWrite(DacPin,uint8_t((LastDacValue>>8)+127)); // write out the data + } + Buffer[NextPlayPos]=0; // Reset this buffer byte back to silence + NextPlayPos++; // Move play pos to next byte in buffer + if(NextPlayPos==BufferSize) // If gone past end of buffer, + NextPlayPos=0; // set back to beginning +} + +#endif + +void AudioPlaySystem::begin(void) +{ +#ifdef USE_I2S + Buffer = (uint16_t *)malloc(DEFAULT_SAMPLESIZE*4); //16bits, L+R + uint16_t * dst=(uint16_t *)Buffer; + for (int i=0; i>1; + } +} + +void AudioPlaySystem::step(void) +{ +#ifdef USE_I2S + int left=DEFAULT_SAMPLERATE/50; + + while(left) { + int n=DEFAULT_SAMPLESIZE; + if (n>left) n=left; + snd_Mixer16((uint16_t*)Buffer, n); + //16 bit mono -> 16 bit r+l + for (int i=n-1; i>=0; i--) { + Buffer[i*2+1]=Buffer[i]+32767; + Buffer[i*2]=Buffer[i]+32767; + } + i2s_write_bytes(I2S_NUM, (const void*)Buffer, n*4, portMAX_DELAY); + left-=n; + } +#else + + int32_t CurPos=NextPlayPos; + int32_t samples; + if (CurPos > LastPlayPos) { + snd_Mixer16((uint16_t *)&Buffer[LastPlayPos], CurPos-LastPlayPos); + samples = CurPos-LastPlayPos; + } + else { + snd_Mixer16((uint16_t *)&Buffer[LastPlayPos], BufferSize-LastPlayPos); + snd_Mixer16((uint16_t *)&Buffer[0], CurPos); + samples = BufferSize-LastPlayPos; + samples += CurPos; + } + LastPlayPos = CurPos; + //printf("sam %d\n",bytes); +#endif +} +#endif + + diff --git a/MCUME_esp32/espcastaway/main/AudioPlaySystem.h b/MCUME_esp32/espcastaway/main/AudioPlaySystem.h new file mode 100644 index 0000000..c1e918f --- /dev/null +++ b/MCUME_esp32/espcastaway/main/AudioPlaySystem.h @@ -0,0 +1,23 @@ +#ifndef audioplaysystem_h_ +#define audioplaysystem_h_ + +#define DEFAULT_SAMPLESIZE 512 // 22050/50=443 samples per 20ms +#define DEFAULT_SAMPLERATE 22050 + +class AudioPlaySystem +{ +public: +AudioPlaySystem(void) { begin(); } + void begin(void); + void setSampleParameters(float clockfreq, float samplerate); + void reset(void); + void start(void); + void stop(void); + bool isPlaying(void); + void sound(int C, int F, int V); + void buzz(int size, int val); + void step(void); +}; + + +#endif diff --git a/MCUME_esp32/espcastaway/main/blitter.cpp b/MCUME_esp32/espcastaway/main/blitter.cpp new file mode 100755 index 0000000..3225e12 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/blitter.cpp @@ -0,0 +1,211 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* blitter.c - ST blitter chip emulation +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 09.06.2002 JH Renamed io.c to st.c again (io.h conflicts with system headers) +* 02.10.2002 JH use uint16 etc. +*/ +static char sccsid[] = "$Id: blitter.c,v 1.3 2002/10/02 22:44:51 jhoenig Exp $"; +#include +#include "config.h" +#include "st.h" +#include "mem.h" +#include "m68k_intrf.h" + +#define FXSR 0x80 +#define NFSR 0x40 +#define SKEW 0x0f +#define BUSY 0x80 +#define HOG 0x40 +#define SMUDGE 0x20 +#define LINENO 0x0f + +void bitblt(void) +{ + uint32 blt_src_in; + uint16 blt_src_out, blt_hop_out, blt_dst_in, blt_dst_out, mask_out; + int xc, yc, lineno, last, first; +#if (VERBOSE & 0x8) + DBG_OUT ("bitblt: Start\n"); + DBG_OUT ("HALFT[] 0x%04x-%04x-%04x-%04x\n", (uint16) blt_halftone[0], blt_halftone[1], blt_halftone[2], blt_halftone[3]); + DBG_OUT ("Y COUNT 0x%04x\n", (uint16) blt_y_cnt); + DBG_OUT ("X COUNT 0x%04x\n", (uint16) blt_x_cnt); + DBG_OUT ("X S INC 0x%04x\n", (uint16) blt_src_x_inc); + DBG_OUT ("Y S INC 0x%04x\n", (uint16) blt_src_y_inc); + DBG_OUT ("X D INC 0x%04x\n", (uint16) blt_dst_x_inc); + DBG_OUT ("Y D INC 0x%04x\n", (uint16) blt_dst_y_inc); + DBG_OUT ("ENDMASK 0x%04x-%04x-%04x\n", (uint16) blt_end_1, (uint16) blt_end_2, (uint16) blt_end_3); + DBG_OUT ("S_ADDR 0x%08lx\n", blt_src_addr); + DBG_OUT ("D_ADDR 0x%08lx\n", blt_dst_addr); + DBG_OUT ("HOP=%01d, OP=%02d\n", blt_hop & 0x3, blt_op & 0xf); + DBG_OUT ("HOPline=%02d\n", blt_status & 0xf); + DBG_OUT ("NFSR=%d, FXSR=%d, SKEW=%02d\n", (blt_skew & NFSR) != 0, + (blt_skew & FXSR) != 0, + (blt_skew & SKEW)); +#endif + yc = (blt_y_cnt == 0) ? 65536 : blt_y_cnt; + while (yc-- > 0) { + xc = (blt_x_cnt == 0) ? 65536 : blt_x_cnt; + first = 1; + blt_src_in = 0; + /* next line to get rid of obnoxious compiler warnings */ + blt_src_out = blt_hop_out = blt_dst_out = 0; + while (xc-- > 0) { + last = (xc == 0); + if ((blt_hop & 0x03) >= 2) { + /* read source into blt_src_in */ + if (blt_src_x_inc >= 0) { + if (first && (blt_skew & FXSR)) { + blt_src_in = (GetMemW (blt_src_addr) << 16); + blt_src_addr += blt_src_x_inc; + } else { + blt_src_in <<= 16; + } + if (last && (blt_skew & NFSR)) { + blt_src_addr -= blt_src_x_inc; + } else { + blt_src_in |= (uint16) GetMemW (blt_src_addr); + if (!last) { + blt_src_addr += blt_src_x_inc; + } + } + } else { + if (first && (blt_skew & FXSR)) { + blt_src_in = (uint16) GetMemW (blt_src_addr); + blt_src_addr +=blt_src_x_inc; + } else { + blt_src_in >>= 16; + } + if (last && (blt_skew & NFSR)) { + blt_src_addr -= blt_src_x_inc; + } else { + blt_src_in |= (GetMemW (blt_src_addr) << 16); + if (!last) { + blt_src_addr += blt_src_x_inc; + } + } + } + /* shift blt_skew times into blt_src_out */ + blt_src_out = blt_src_in >> (blt_skew & SKEW); +#if (VERBOSE & 0x8) + DBG_OUT ("%04x ", blt_src_out); +#endif + } + /* halftone OP */ + lineno = ((blt_status & SMUDGE) ? blt_src_out : blt_status) & LINENO; + switch (blt_hop & 0x3) { + case 0: + blt_hop_out = 0xffff; + break; + case 1: + blt_hop_out = blt_halftone[lineno]; + break; + case 2: + blt_hop_out = blt_src_out; + break; + case 3: + blt_hop_out = blt_src_out & blt_halftone[lineno]; + break; + } + /* read destination into blt_dst_in */ + blt_dst_in = GetMemW (blt_dst_addr); + /* op into blt_dst_out */ + switch (blt_op & 0xf) { + case 0: + blt_dst_out = 0; + break; + case 1: + blt_dst_out = blt_hop_out & blt_dst_in; + break; + case 2: + blt_dst_out = blt_hop_out & ~blt_dst_in; + break; + case 3: + blt_dst_out = blt_hop_out; + break; + case 4: + blt_dst_out = ~blt_hop_out & blt_dst_in; + break; + case 5: + blt_dst_out = blt_dst_in; + break; + case 6: + blt_dst_out = blt_hop_out ^ blt_dst_in; + break; + case 7: + blt_dst_out = blt_hop_out | blt_dst_in; + break; + case 8: + blt_dst_out = ~blt_hop_out & ~blt_dst_in; + break; + case 9: + blt_dst_out = ~blt_hop_out ^ blt_dst_in; + break; + case 0xa: + blt_dst_out = ~blt_dst_in; + break; + case 0xb: + blt_dst_out = blt_hop_out | ~blt_dst_in; + break; + case 0xc: + blt_dst_out = ~blt_hop_out; + break; + case 0xd: + blt_dst_out = ~blt_hop_out | blt_dst_in; + break; + case 0xe: + blt_dst_out = ~blt_hop_out | ~blt_dst_in; + break; + case 0xf: + blt_dst_out = 0xffff; + break; + } + /* and endmask */ + if (first) { + mask_out = (blt_dst_out & blt_end_1) | (blt_dst_in & ~blt_end_1); + } else if (last) { + mask_out = (blt_dst_out & blt_end_3) | (blt_dst_in & ~blt_end_3); + } else { + mask_out = (blt_dst_out & blt_end_2) | (blt_dst_in & ~blt_end_2); + } + SetMemW (blt_dst_addr, mask_out); + if (!last) { + blt_dst_addr += blt_dst_x_inc; + } + first = 0; + } +#if (VERBOSE & 0x8) + DBG_OUT ("\n"); +#endif + blt_status = (blt_status + ((blt_dst_y_inc >= 0) ? 1 : 15)) & 0xef; + blt_src_addr += blt_src_y_inc; + blt_dst_addr += blt_dst_y_inc; + } + /* blt_status &= ~BUSY; */ + blt_y_cnt = 0; +#if (VERBOSE & 0x8) + DBG_OUT ("bitblt: End\n"); + DBG_OUT ("HALFT[] 0x%04x-%04x-%04x-%04x\n", (uint16) blt_halftone[0], blt_halftone[1], blt_halftone[2], blt_halftone[3]); + DBG_OUT ("Y COUNT 0x%04x\n", (uint16) blt_y_cnt); + DBG_OUT ("X COUNT 0x%04x\n", (uint16) blt_x_cnt); + DBG_OUT ("X S INC 0x%04x\n", (uint16) blt_src_x_inc); + DBG_OUT ("Y S INC 0x%04x\n", (uint16) blt_src_y_inc); + DBG_OUT ("X D INC 0x%04x\n", (uint16) blt_dst_x_inc); + DBG_OUT ("Y D INC 0x%04x\n", (uint16) blt_dst_y_inc); + DBG_OUT ("ENDMASK 0x%04x-%04x-%04x\n", (uint16) blt_end_1, (uint16) blt_end_2, (uint16) blt_end_3); + DBG_OUT ("S_ADDR 0x%08lx\n", blt_src_addr); + DBG_OUT ("D_ADDR 0x%08lx\n", blt_dst_addr); + DBG_OUT ("HOP=%01d, OP=%02d\n", blt_hop & 0x3, blt_op & 0xf); + DBG_OUT ("HOPline=%02d\n", blt_status & 0xf); + DBG_OUT ("NFSR=%d, FXSR=%d, SKEW=%02d\n", (blt_skew & NFSR) != 0, + (blt_skew & FXSR) != 0, + (blt_skew & SKEW)); +#endif +} diff --git a/MCUME_esp32/espcastaway/main/bmpjoy.h b/MCUME_esp32/espcastaway/main/bmpjoy.h new file mode 100644 index 0000000..def4d7c --- /dev/null +++ b/MCUME_esp32/espcastaway/main/bmpjoy.h @@ -0,0 +1,40 @@ +const uint16_t bmpjoy[] = { +0x001e,0x0026,0x0000,0x0000,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x0000,0x0000, +0x0000,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xf4d2,0xeaea,0xe227,0xe268,0xebce,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x0000, +0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xeaa9,0xe984,0xe164,0xd964,0xe184,0xe1a4,0xe1a5,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c, +0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xe207,0xe984,0xe206,0xe2e9,0xe267,0xd964,0xd9a5,0xd984,0xf1a5,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c, +0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xebef,0xe984,0xe288,0xeb8b,0xeb0a,0xe247,0xd984,0xd984,0xd9a5,0xe1a5,0xe1c6,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c, +0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xd9c6,0xe1c5,0xeb8b,0xe247,0xd943,0xd964,0xd984,0xd984,0xd984,0xd9a5,0xe9a5,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c, +0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xe164,0xe268,0xeb4b,0xd964,0xd984,0xd984,0xd984,0xd984,0xd984,0xd9a5,0xe9a5,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c, +0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xe184,0xe206,0xe247,0xd984,0xd984,0xd984,0xd984,0xd984,0xd984,0xd9a5,0xe9a5,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c, +0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0xd9a5,0xd984,0xd964,0xd984,0xd984,0xd984,0xd984,0xd984,0xd984,0xd9a5,0xe9a5,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c, +0x247c,0x247c,0x247c,0x247c,0x247c,0x18e3,0x18e3,0x18e3,0x18e3,0xeb2b,0xe9a5,0xd9a5,0xd984,0xd984,0xd984,0xd984,0xd984,0xd984,0xd9a5,0xe1a4,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x247c,0x247c,0x247c,0x247c,0x247c, +0x247c,0x247c,0x247c,0x247c,0x18e3,0xe71c,0xdefc,0xdedb,0xdefc,0x18e3,0xe184,0xd984,0xd9a5,0xd984,0xd984,0xd984,0xd984,0xd9a5,0xe143,0x18e3,0xdf1c,0xdedb,0xdedb,0xdefb,0xe71c,0x18e3,0x247c,0x247c,0x247c,0x247c, +0x247c,0x247c,0x247c,0x18e3,0xbe18,0xbe19,0xbe18,0xbe18,0xbe18,0xb619,0x18e3,0xe143,0xd943,0xd984,0xd984,0xd984,0xd964,0xe122,0x18e3,0xad96,0xbe19,0xbe18,0xbe18,0xbe18,0xbe19,0xbe18,0x18e3,0x1c5d,0x247c,0x247c, +0x247c,0x247c,0x18e3,0xbe18,0xbdf8,0xadb7,0xadb7,0xadb7,0xb5b7,0xb5b7,0xadf8,0x18e3,0xd269,0xd9a5,0xd963,0xd984,0xda07,0x18e3,0xadb7,0xadb7,0xb5b7,0xadb7,0xadb7,0xadb7,0xadb7,0xbdf8,0xbe18,0x18e3,0x247c,0x247c, +0x247c,0x247c,0x18e3,0xb5b7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xad96,0xadf8,0xbe18,0xe69a,0xe618,0xee79,0xce59,0xadf8,0xadb7,0xad97,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0x18e3,0x247c,0x247c, +0x247c,0x247c,0x18e3,0xadb7,0xad97,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xb5d7,0x9d15,0x8493,0xdf5d,0xe79e,0xefdf,0xadb7,0x8493,0xb5b7,0xb5b7,0xad97,0xadb7,0xad97,0xadb7,0xadb7,0xad97,0xadb7,0x18e3,0x247c,0x247c, +0x247c,0x247c,0x18e3,0xadb7,0xadb7,0xadb7,0xadb7,0xad97,0xadb7,0xadb7,0x7c52,0x4b2e,0x5b90,0xdf3c,0xe75d,0xf79e,0x9515,0x42ed,0x63d0,0x9d55,0xb5b7,0xad96,0xadb7,0xad97,0xadb7,0xadb7,0xadb7,0x18e3,0x247c,0x247c, +0x247c,0x247c,0x18e3,0xadb7,0xadb7,0xadb7,0xad97,0xadb7,0xadb7,0x6bf1,0x4b2e,0x4b2e,0x532e,0xdf1c,0xe75d,0xefbe,0x8cb3,0x42ac,0x534f,0x534f,0x9d15,0xb5b7,0xad96,0xadb7,0xadb7,0xadb7,0xadb7,0x18e3,0x247c,0x247c, +0x247c,0x247c,0x18e3,0xadb7,0xadb7,0xadb7,0xad96,0xb5d7,0x7c52,0x4b0e,0x532e,0x322a,0x428b,0xdf1c,0xe75d,0xf7be,0x8472,0x29a8,0x4aed,0x534f,0x5b6f,0xad76,0xadb7,0xad97,0xad97,0xadb7,0xadb7,0x18e3,0x247c,0x247c, +0x247c,0x247c,0x18e3,0xadb7,0xad97,0xad97,0xb5b7,0x9d35,0x534f,0x534f,0x3a4a,0x31e8,0x42ab,0xdf1c,0xe75d,0xf7be,0x8472,0x29c8,0x3a29,0x4b0d,0x4b2e,0x7c52,0xb5d7,0xad96,0xadb7,0xadb7,0xadb7,0x18e3,0x247c,0x247c, +0x247c,0x247c,0x18e3,0xadb7,0xadb7,0xad96,0xb5d7,0x7c52,0x4b2e,0x4aed,0x3209,0x3209,0x428b,0xdf1c,0xe75d,0xf7be,0x8472,0x29c8,0x3a29,0x3a6a,0x534f,0x5b8f,0xad96,0xadb7,0xad97,0xadb7,0xadb7,0x18e3,0x247c,0x247c, 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+0x247c,0x247c,0x18e3,0xb5d7,0xb5b7,0xadb7,0xadb7,0xb576,0xadd7,0xad97,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xad96,0xce7a,0xe75d,0xe75d,0xce9a,0xad96,0xadb7,0xb5b7,0xb5b7,0x18e3,0x247c,0x247c, +0x247c,0x247c,0x18e3,0xd6bb,0xbe18,0xadb7,0xadb7,0xadb7,0xad96,0xadb7,0xad97,0xad97,0xad97,0xad97,0xad97,0xad97,0xad97,0xadb7,0xad97,0xb5d7,0xbe18,0xadb7,0xad76,0xadb7,0xadb7,0xbe18,0xd6bb,0x18e3,0x247c,0x247c, +0x247c,0x247c,0x247c,0x18e3,0xd6bb,0xbdf8,0xb5b7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xad96,0xad96,0xadb7,0xadb7,0xb5b7,0xbdf8,0xd6bb,0x18e3,0x247c,0x247c,0x247c, +0x247c,0x247c,0x247c,0x247c,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x247c,0x247c,0x247c,0x247c, +0x0000,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x0000, +0x0000,0x0000,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x0000,0x0000}; + diff --git a/MCUME_esp32/espcastaway/main/bmpvbar.h b/MCUME_esp32/espcastaway/main/bmpvbar.h new file mode 100644 index 0000000..22dd775 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/bmpvbar.h @@ -0,0 +1,151 @@ +const uint16_t bmpvbar[] = { +0x0020,0x0094, +0x0000,0x0000,0x0000,0xad96,0xdf3d,0xd6fc,0xd6fc,0xd6fd,0xd6fd,0xd71d,0xdf1d,0xd71d,0xd71c,0xd71d,0xd71d,0xd71d,0xd71d,0xd71d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf3d,0xbe18,0x0000,0x0000,0x0000,0x0861, +0x0000,0x0000,0xbe39,0xcedc,0xb63b,0xadfa,0xadfb,0xadfb,0xadfb,0xadfb,0xae1b,0xae1b,0xae1b,0xae1b,0xae1b,0xae1b,0xae3b,0xae3b,0xae3b,0xae3b,0xb63b,0xb63b,0xb63c,0xb63c,0xb65c,0xb65c,0xb65c,0xc69c,0xd71d,0x5b0c,0x0000,0x0861, +0x0000,0x0000,0xcedd,0xa5da,0x7d19,0x74d9,0x74da,0x74fa,0x74fa,0x74fa,0x74fa,0x751a,0x751a,0x751a,0x753a,0x753b,0x7d3b,0x7d3b,0x7d5b,0x7d5b,0x7d5b,0x7d7b,0x7d7b,0x7d7b,0x7d9c,0x7d9c,0x8ddb,0x9e1b,0xae7b,0xd71d,0x0000,0x0861, +0x0000,0xdf3d,0xa5fb,0x74da,0x4c59,0x445a,0x3c5a,0x447b,0x447b,0x447b,0x449b,0x449b,0x44bb,0x44bb,0x44db,0x4cdb,0x4cdc,0x4cfc,0x4cfc,0x4d1c,0x4d1c,0x4d3c,0x4d3c,0x555d,0x555d,0x557c,0x65bc,0x7dfb,0x961b,0xbe9c,0xad96,0x0861, +0x0000,0xc69b,0x7d1a,0x443a,0x345b,0x2c7c,0x2c7c,0x349c,0x349c,0x34bc,0x34bc,0x34dc,0x34dc,0x3cfd,0x3cfd,0x3cfd,0x3d1d,0x3d1d,0x453d,0x455e,0x455e,0x455e,0x457e,0x4d9e,0x4d9e,0x55be,0x5dfd,0x761c,0x8e1c,0xa63b,0xd6fc,0x0861, +0xad96,0xadfa,0x5c59,0x2c3b,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x453e,0x455e,0x457e,0x457e,0x457e,0x459f,0x4dbf,0x4dbf,0x55de,0x5dfe,0x6e1d,0x8e5d,0x9e3c,0xbe9c,0x8430, +0xd6fd,0x8d39,0x3c1a,0x2c5c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x55fe,0x65fe,0x8e7e,0x9e7d,0xae5c,0xdf3d, +0xcebc,0x74b9,0x343b,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x5dfe,0x7e5e,0x9e9e,0xa65c,0xd6fd, +0xc67c,0x5c5a,0x2c3b,0x247c,0x249c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x4dde,0x55de,0x763f,0x9e9e,0xa65c,0xcedc, +0xbe5b,0x543a,0x245c,0x247c,0x2c9c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x4dde,0x55de,0x661f,0xa69e,0xae5b,0xcedc, +0xbe3b,0x543a,0x245c,0x2c7c,0x2c9c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbf,0x55de,0x55fe,0x5e1e,0xa69d,0xb65b,0xcebc, +0xbe3a,0x543a,0x245c,0x2c7c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbe,0x55de,0x55fe,0x5dfe,0xa69d,0xb65b,0xcebc, +0xbe3a,0x545a,0x245c,0x2c7c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbe,0x55de,0x55fe,0x5dfe,0xa69e,0xb67b,0xc6bc, +0xbe3a,0x5459,0x2c5c,0x2c7c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1d,0x3d1d,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x55be,0x4dde,0x55ff,0x5e1f,0xa69e,0xb67c,0xc6bc, +0xbe3a,0x5459,0x2c5c,0x2c7d,0x2c7d,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1d,0x3d1e,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x55be,0x4ddf,0x55ff,0x661f,0xa6be,0xb67c,0xc6bc, +0xbe3a,0x5459,0x245c,0x2c7c,0x2c9c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x351d,0x3d1e,0x3d1e,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459f,0x4d9f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c9c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x351e,0x3d1e,0x3d1e,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459f,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x351e,0x3d1e,0x3d1e,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459f,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1e,0x3d3e,0x453e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d3d,0x3d3e,0x453e,0x455e,0x457e,0x457e,0x459e,0x459e,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x3cdd,0x3cfd,0x3d1d,0x3d3d,0x3d3d,0x3d3d,0x453e,0x455e,0x455e,0x457e,0x459e,0x459e,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, 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By default, it will take the sources in the +# src/ directory, compile them and link them into lib(subdirectory_name).a +# in the build directory. This behaviour is entirely configurable, +# please read the ESP-IDF documents if you need to do this. +# + +#COMPONENT_ADD_INCLUDEDIRS := . 68korig +#COMPONENT_SRCDIRS := . 68korig +#CPPFLAGS += -fpermissive -O3 -ffast-math -Wno-error=sequence-point +COMPONENT_ADD_INCLUDEDIRS := . 68kfame +COMPONENT_SRCDIRS := . 68kfame +CPPFLAGS += -O3 -ffast-math -DUSE_FAME_CORE_C -DUSE_FAME_CORE -DFAME_GLOBAL_CONTEXT + +CPPFLAGS += #-DNO_SOUND #-DEMULATED_JOYSTICK -DUSE_SHORT_SLICE -DUSE_DOUBLE_BUFFER +CPPFLAGS += -Wno-error=maybe-uninitialized -Wno-error=parentheses + diff --git a/MCUME_esp32/espcastaway/main/config.h b/MCUME_esp32/espcastaway/main/config.h new file mode 100755 index 0000000..b5d666b --- /dev/null +++ b/MCUME_esp32/espcastaway/main/config.h @@ -0,0 +1,129 @@ +/* + * Castaway + * (C) 1994 - 2002 Joachim Hoenig, Martin Doering + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ +#ifndef CONFIGH +#define CONFIGH +/* + * Environment Configuration + */ +#if !defined(USE_BIG_ENDIAN) && !defined(USE_LITTLE_ENDIAN) +#define USE_LITTLE_ENDIAN +#endif + +#ifndef INLINE +#define INLINE static __inline__ +#endif + + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +/* + * compiler representation of M68000 .B .W .L operands + */ +#ifndef __cplusplus +typedef signed char bool; +#endif +#ifndef DREAMCAST +typedef signed char int8; +typedef signed short int16; +typedef signed long int32; +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned long uint32; +#else +#include +#endif + +/* + * Atari ST emulator defaults + */ +#define MEMBASE 0x00000000L +#ifndef MEMSIZE +#define MEMSIZE 0x00100000L /* default memsize 1 Mb */ +//#define MEMSIZE 0x00040000L /* default memsize 1 Mb */ +#endif +#define CARBASE 0x00fa0000L +#define CARSIZE 0x00020000L /* 128k cartridge */ +#define ROMBASE 0x00fc0000L +#define ROMBASE2 0x00e00000L +#define ROMSIZE 0x00030000L /* 192k */ +#define ROMSIZE2 0x00040000L /* 256k */ +#define IOBASE 0x00ff8000L +#define IOSIZE 0x00008000L /* 32k */ +#define SVADDR 0x00000800L + + +#define MONITOR 2 /* 0=color 320x200 or 2=monochrome 640x400 */ +#define SIDES 2 /* disk sides */ +#define TRACKS 80 /* tracks on disk */ +#define SECTORS 9 /* sectors per track */ +#define SECSIZE 512 /* byte per sector */ +#define TIMER 0 /* 0=normal (200Hz), 2=slow (100Hz) */ +#define NO_BLITTER +#define NO_RTC /* Do not emulate Real-Time-Clock */ +//#define CHKADDRESSERR /* if set, unaligned access will raise an address +// error (slower, but expected behaviour) */ +//#define CHKTRACE /* if set, the trace bit works (slower). */ +//#define NATFEAT /* if set, native features are supported */ + +#undef DEBUG /* Debug */ + +#ifndef USE_BIG_ENDIAN +#define BYTES_SWAP 1 +#endif + +#undef DISASS +#undef DBGTRACE +#undef DETECT_PREFETCH + +/* + * Debug options + */ +#ifdef DEBUG +#ifndef CHKADDRESSERR +#define CHKADDRESSERR /* force address error checking */ +#endif +#define VERBOSE 0x1 /* ~INT, IO, ~BLITTER */ +#define TRACEBACK 2000 /* 68k traceback buffer size */ +#undef INTERNALTRACE /* trace 68k operation internal execution */ +#define DBG_OUT if (verb_on) printf +#define DBG_STOP if (stop_on) Stop +#define NO_TIMER +/* special DEBUG action on traps */ +#define ON_TRAP(number) if (number == 33) {stop_on++;}; +/* special DEBUG action on R/W access to an unmapped address */ +#define ON_UNMAPPED(address, value) +/* special DEBUG action on unmapped I/O access */ +#define ON_NOIO(offset, value) +/* special DEBUG action on write access */ +#define ON_WRITE(address, value) +extern int trace_on; +extern int stop_on; +extern int verb_on; +extern void SaveState(unsigned short inst); +extern void Stop(void); +#else /* not DEBUG */ +#define ON_TRAP(number) +#define ON_UNMAPPED(address, value) +#define ON_NOIO(address, value) +#define ON_WRITE(address, value) +// # define ON_TRAP(number) if (number == 33 && GetMemW(areg[7]) == 0x4c) { TraceStop(); } +#endif +#endif + +#ifdef DEBUG_FAME_FFLUSH +#undef DEBUG_FAME_FFLUSH +#define DEBUG_FAME_FFLUSH fflush(stdout) +#else +#define DEBUG_FAME_FFLUSH +#endif diff --git a/MCUME_esp32/espcastaway/main/dcastaway.h b/MCUME_esp32/espcastaway/main/dcastaway.h new file mode 100755 index 0000000..8848986 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/dcastaway.h @@ -0,0 +1,18 @@ +#include +#include +#include + + +#include "config.h" + +//extern void do_events (void) ; + +extern int emulating; +extern int nScreenRefreshRate; +extern int draw_border, maybe_border; +extern unsigned screen_pitch, screen_width, screen_height; +extern unsigned cyclenext; +extern unsigned vid_adr_cycleyet; +extern unsigned char *vid_cycle; + + diff --git a/MCUME_esp32/espcastaway/main/emu.cpp b/MCUME_esp32/espcastaway/main/emu.cpp new file mode 100644 index 0000000..1a14bc1 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/emu.cpp @@ -0,0 +1,580 @@ +#include +#include +#include +extern "C" { +#include "emuapi.h" +} +#include "config.h" +#include "st.h" +#include "mem.h" +#include "m68k_intrf.h" +#ifndef NO_SOUND +#include "sound.h" +#endif +#include "tossw12.h" + + +int8 *membase; +int8 *rombase; + + +int hbl = 0; +int end_visible_screen = 264; +int hsync = 0; +int vsyncpend = 0, hsyncpend = 0; + +int exmousex=160,exmousey=100,MouseRelease1=0,MouseRelease2=0; +int CompleteSndBufIdx; + + +int waitstate=0; +int dcastaway_disc_writed[2] = { 0 , 0 }; +int dcastaway_disc_for_write[2] = { 0 , 0 }; +int draw_border=0, maybe_border=0; +unsigned cyclenext=512; +unsigned vid_adr_cycleyet=0; + +#ifndef USE_FAME_CORE +unsigned IO_CYCLE=0; +#endif +static unsigned char vid_cycles_pal[1024]; +static unsigned char vid_cycles_ntsc[1024]; +unsigned char *vid_cycle=(unsigned char *)&vid_cycles_pal; + +int readdsk=1; +extern unsigned char fdc_motor; + +#ifndef NO_SOUND +void SND_Process(void *stream, int len) { + Sound_UpdateFromCallBack16((short *)stream, len); +} +#endif + + +static unsigned short line[320]; + +#define PALMULT8(x) ((x)<<5) +#define RGBVAL16(r,g,b) ( (((r>>3)&0x1f)<<11) | (((g>>2)&0x3f)<<5) | (((b>>3)&0x1f)<<0) ) + +extern signed char videobuf[32768]; + +void Redraw16 ( int row, int vid_adr ) { + + static unsigned short palmap [ 16 ]; + //Source address +// register unsigned short *line_i = (unsigned short *)(&membase[vid_adr]); + register unsigned short *line_i = (unsigned short *)(&videobuf[row*160]); + register unsigned short *line_o= &line[0]; + + //Build paletter + if (vid_flag) { + unsigned char i, r, g, b; + for (i = 0; i < 16; i++) { + b = PALMULT8 ( (vid_col[i] & 0x7) ); + g = PALMULT8 ( ((vid_col[i] >> 4) & 0x7) ); + r = PALMULT8 ( ((vid_col[i] >> 8) & 0x7) ); + palmap [ i ] = RGBVAL16(r,g,b); + } + vid_flag=0; + } + + register int col; + register int bit; + for (col=0; col<20; col++) { + register unsigned short pl0=*line_i++,pl1=*line_i++,pl2=*line_i++,pl3=*line_i++; + for (bit=15;bit>=0;bit--) { + int ind = (pl0 >> bit) & 0x1; + ind += ((pl1 >> bit) & 0x1)<<1; + ind += ((pl2 >> bit) & 0x1)<<2; + ind += ((pl3 >> bit) & 0x1)<<3; + *line_o++ = palmap [ ind ]; + } + } + + emu_DrawLine16(&line[0], 320, 200, row); +} + +void Redraw16_med ( int row, int vid_adr ) { + static unsigned short palmap [ 4 ]; + //Source address +// register unsigned short *line_i = (unsigned short *)(&membase[vid_adr]); + register unsigned short *line_i = (unsigned short *)(&videobuf[row*160]); + register unsigned short *line_o= &line[0]; + + //Build paletter + if (vid_flag) { + unsigned char i, r, g, b; + for (i = 0; i < 4; i++) { + b = PALMULT8 ( (vid_col[i] & 0x7) ); + g = PALMULT8 ( ((vid_col[i] >> 4) & 0x7) ); + r = PALMULT8 ( ((vid_col[i] >> 8) & 0x7) ); + palmap [ i ] = RGBVAL16(r,g,b); + } + //palmap [ 0 ] = RGBVAL16(0xff,0xff,0xff); + vid_flag=0; + } + + register int col; + register int bit; + for (col=0; col<40; col++) { + register unsigned short pl0=*line_i++,pl1=*line_i++; + for (bit=15;bit>=0;bit--) { + int ind = (pl0 >> bit) & 0x1; + ind += ((pl1 >> bit) & 0x1)<<1; + if (bit & 0x01) + *line_o++ = palmap [ ind ]; + } + } + + emu_DrawLine16(&line[0], 320, 200, row); +} + + +static int mouse_x = 160; +static int mouse_y = 100; +static int prev_key = 0; +static int prev_j = 0; + +static int hk=0; +static int k=0; +static bool isMouse = true; +static int joynum = 1; + +void mac_Input(int bClick) { + //if (bClick & MASK_KEY_USER1) { + // printf("selected %d\n", isMouse); + // if (isMouse) isMouse=false; + // else isMouse=true; + //} + hk = emu_ReadI2CKeyboard(); + k = emu_ReadKeys(); +} + +static void do_events(void) +{ + //int hk = emu_ReadI2CKeyboard(); + if ( (hk != 0) && (hk != prev_key) ) { + prev_key = hk; + IkbdKeyPress ( hk ); + //printf("press %d\n", hk); + } else { + if (prev_key) { + //printf("release %d\n", prev_key); + IkbdKeyRelease ( prev_key | 0x80 ); + prev_key = 0; + } + } + + + //int k = emu_ReadKeys(); + //if (k) printf("keys 0x%04X\n",k); + if (isMouse) + { + if (( k & MASK_JOY1_RIGHT) || ( k & MASK_JOY2_RIGHT)) { + if ( mouse_x < 320 ) { + mouse_x += 1; + IkbdMouseMotion ( mouse_x, mouse_y ); + } + } + else if (( k & MASK_JOY1_LEFT) || ( k & MASK_JOY2_LEFT)) { + if ( mouse_x > 1 ) { + mouse_x -= 1; + IkbdMouseMotion ( mouse_x, mouse_y ); + } + } + else if (( k & MASK_JOY1_UP) || ( k & MASK_JOY2_UP)) { + if ( mouse_y > 1 ) { + mouse_y -= 1; + IkbdMouseMotion ( mouse_x, mouse_y ); + } + } + else if (( k & MASK_JOY1_DOWN) || ( k & MASK_JOY2_DOWN)) { + if ( mouse_y < 200 ) { + mouse_y += 1; + IkbdMouseMotion ( mouse_x, mouse_y ); + } + } + if ( /*( k & MASK_JOY1_BTN) ||*/ ( k & MASK_JOY2_BTN) ){ + IkbdMousePress(2); + } + else { + IkbdMouseRelease(2); + } + } + else + { + int j = 0; + if (( k & MASK_JOY1_RIGHT) || ( k & MASK_JOY2_RIGHT)) { + j |= 0x08; + } + if (( k & MASK_JOY1_LEFT) || ( k & MASK_JOY2_LEFT)) { + j |= 0x04; + } + if (( k & MASK_JOY1_UP) || ( k & MASK_JOY2_UP)) { + j |= 0x01; + } + if (( k & MASK_JOY1_DOWN) || ( k & MASK_JOY2_DOWN)) { + j |= 0x02; + } + if ( k & MASK_JOY2_BTN) { + printf("fire\n"); + j |= 0x80; + } + if (j != prev_j) IkbdJoystickChange(joynum,j); + prev_j = j; + } + IkbdLoop(); +} + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#include "esp_system.h" + + + + +void mac_Init(void) +{ + + membase = (int8*) heap_caps_malloc(MEMSIZE,MALLOC_CAP_SPIRAM); + //membase = (int8*) malloc(MEMSIZE); + if (!membase)printf("malloc failed\n"); + rombase=(int8 *)&tos[0]-ROMBASE; + (void) memcpy (membase, &tos[0], 8); + + + //extern unsigned char *msabuff; + extern unsigned char *disc[2]; + //msabuff = (uint8*) heap_caps_malloc(1050L*1024L,MALLOC_CAP_SPIRAM); + //disc [ 0 ] = (uint8*) heap_caps_malloc ( 1050L*1024L,MALLOC_CAP_SPIRAM ); + //disc [ 1 ] = (uint8*) heap_caps_malloc ( 10L*1024L,MALLOC_CAP_SPIRAM ); + disc [ 0 ] = (uint8*) malloc ( 256 ); + disc [ 1 ] = (uint8*) malloc ( 256 ); + + +//#define DISKA "/sdcard/st/med_009.st" //"800ATARI.st" /* Disk A pathname */ +//#define DISKB "/sdcard/st/A_004.MSA"//"boot" //"A_000.MSA" //"disk.st" /* Disk B pathname */ +} + +void mac_Start(char * filename) +{ + + strncpy (disk[0].name, filename, sizeof(disk[0].name)); + + printf("Init loading disk %s\n",disk[0].name); + //MemClean(); + initialize_memmap(); + //MemInit(); + FDCInit(0); + //FDCeject(0); + FDCeject(1); + IkbdReset(); + IOInit(); +#ifndef NO_SOUND + Sound_Init(); +#endif + HWReset(); /* CPU Reset */ + + printf("Init done\n"); +} + + +void mac_Step(void) +{ + int delay_fdc_motor=0; + unsigned long cycleco=0; + unsigned long oldpend,newpend; + hsync=0; + hbl=0; + vsyncpend=0; + hsyncpend=0; + + + int running = 1; + /* Event loop */ + while (running) + { + + +#ifndef USE_FAME_CORE + recalc_int = 0; +#endif + cycleco=cpu_loop(cyclenext); + cycleco+=waitstate; + waitstate=0; +#ifndef NO_SOUND + SoundCycles+=cycleco; +#endif + //MFP timer A delay mode + if (mfp_ascale>1) { + mfp_acount-=mfp_ascale*cycleco; + if (mfp_acount<=0) { + do {mfp_acount+=mfp_tadr;} while (mfp_acount<=0); + oldpend=mfp_ipra; newpend=(oldpend|0x20)&mfp_iera; + if (newpend!=oldpend) {mfp_ipra=newpend; + #ifndef USE_FAME_CORE + recalc_int=1; + #endif + } + } + #ifdef USE_SHORT_SLICE + cyclenext=4+(mfp_acount/mfp_ascale); + #endif + } + #ifdef USE_SHORT_SLICE + else + cyclenext=512; + #endif + //MFP timer B delay mode + if (mfp_bscale>1) { + mfp_bcount-=mfp_bscale*cycleco; + if (mfp_bcount<=0) { + do {mfp_bcount+=mfp_tbdr;} while (mfp_bcount<=0); + oldpend=mfp_ipra; newpend=(oldpend|0x1)&mfp_iera; + if (newpend!=oldpend) {mfp_ipra=newpend; + #ifndef USE_FAME_CORE + recalc_int=1; + #endif + } + } + #ifdef USE_SHORT_SLICE + { + int n=4+(mfp_bcount/mfp_bscale); + if (n1) { + mfp_ccount-=mfp_cscale*cycleco; + if (mfp_ccount<=0) { + do {mfp_ccount+=mfp_tcdr;} while (mfp_ccount<=0); + oldpend=mfp_iprb; newpend=(oldpend|0x20)&mfp_ierb; + if (newpend!=oldpend) {mfp_iprb=newpend; + #ifndef USE_FAME_CORE + recalc_int=1; + #endif + } + } + #ifdef USE_SHORT_SLICE + { + int n=4+(mfp_ccount/mfp_cscale); + if (n1) { + mfp_dcount-=mfp_dscale*cycleco; + if (mfp_dcount<=0) { + do {mfp_dcount+=mfp_tddr;} while (mfp_dcount<=0); + oldpend=mfp_iprb; newpend=(oldpend|0x10)&mfp_ierb; + if (newpend!=oldpend) {mfp_iprb=newpend; + #ifndef USE_FAME_CORE + recalc_int=1; + #endif + } + } + #ifdef USE_SHORT_SLICE + { + int n=4+(mfp_dcount/mfp_dscale); + if (n=313) + { +// printf("hbl%d\n",hbl); + emu_DrawVsync(); + + do_events(); + Sound_Update_VBL(); + running=0; +#ifdef HAS_SDL + SDL_Delay(20); +#endif + + + hbl=0; + //Generate vsync interrupt +#ifndef USE_FAME_CORE + vsyncpend=1; recalc_int=1; +#else + Interrupt(AUTOINT4, 4); +#endif + //Do fdc spinup + if (fdc_motor){ + if (delay_fdc_motor>150) { + fdc_status &= ~0x80; + delay_fdc_motor=0; + fdc_motor=0; + } + else delay_fdc_motor++; + } + } + } + + + //Recalculate interrupts? +#ifndef USE_FAME_CORE + if (recalc_int==1) +#endif + { + int mfp_int; + mfp_int=0; + if (6>GetI()) { + //Mfp interrupt + { + int n, number; + uint16 imr, ipr, isr, irr; + int in_request; + //Find in_request and in_service + imr = (mfp_imra<<8)+mfp_imrb; + ipr = (mfp_ipra<<8)+mfp_iprb; + irr = imr & ipr; + isr = (mfp_isra<<8) + mfp_isrb; + //in_request higher than in_service? + if (irr>isr) { + //Find highest set bit + for (in_request = 15; in_request > 0; in_request--) { + if (irr & 0x8000) break; + irr <<= 1; + } + isr = 1 << in_request; + //Set interrupt in service bits in MFP + if (mfp_ivr & 0x8) { + mfp_isra |= isr >> 8; + mfp_isrb |= isr; + }else{ + mfp_isra &= (~isr) >> 8; + mfp_isrb &= ~isr; + } + //Clear interrupt pending bits in MFP + mfp_ipra &= ~(isr >> 8); + mfp_iprb &= ~isr; + //Pass interrupt to cpu + number = in_request | (mfp_ivr & 0xf0); + Interrupt(number, 6); + mfp_int=1; + } + } + } +#ifndef USE_FAME_CORE + if (!mfp_int){ + if (vsyncpend==1 && 4>GetI()) { + Interrupt(AUTOINT4, 4); + vsyncpend=0; + }else if (hsyncpend==1 && 2>GetI()) { + Interrupt(AUTOINT2, 2); + hsyncpend=0; + } + } + + if (!vsyncpend&&!hsyncpend) recalc_int=0; +#endif + } + + } + +} + + + + + + diff --git a/MCUME_esp32/espcastaway/main/emu.h b/MCUME_esp32/espcastaway/main/emu.h new file mode 100644 index 0000000..3aa56ff --- /dev/null +++ b/MCUME_esp32/espcastaway/main/emu.h @@ -0,0 +1,4 @@ +extern void mac_Init(void); +extern void mac_Step(void); +extern void mac_Start(char * filename); +extern void mac_Input(int bClick); diff --git a/MCUME_esp32/espcastaway/main/emuapi.cpp b/MCUME_esp32/espcastaway/main/emuapi.cpp new file mode 100644 index 0000000..50014ff --- /dev/null +++ b/MCUME_esp32/espcastaway/main/emuapi.cpp @@ -0,0 +1,1112 @@ +#define KEYMAP_PRESENT 1 + +#include +#include +#include +#include + +extern "C" { + #include "emuapi.h" + #include "iopins.h" +} + +#include "ili9341_t3dma.h" +//#include "logo.h" +#include "bmpjoy.h" +#include "bmpvbar.h" + +#include "esp_event.h" +#include "esp_vfs_fat.h" +#include "driver/sdspi_host.h" +#include +#include +#include + +#ifdef HAS_I2CKBD +#ifdef USE_WIRE +#include "Wire.h" +#else +#include +#define ACK_CHECK_EN 0x1 /*!< I2C master will check ack from slave*/ +#define ACK_CHECK_DIS 0x0 /*!< I2C master will not check ack from slave */ +#define ACK_VAL 0x0 /*!< I2C ack value */ +#define NACK_VAL 0x1 /*!< I2C nack value */ +#endif + +#define I2C_FREQ_HZ 400000 /*!< I2C master clock frequency */ +static bool i2cKeyboardPresent = false; +#endif + + +extern ILI9341_t3DMA tft; + +static char romspath[64]; +static int calMinX=-1,calMinY=-1,calMaxX=-1,calMaxY=-1; +static sdmmc_card_t* card; +const uint16_t deflogo[] = { + 0x0000,0x0000 +}; +static const uint16_t * logo = deflogo; + +#define CALIBRATION_FILE "/sdcard/cal.cfg" + +#define MAX_FILENAME_SIZE 28 +#define MAX_MENULINES (MKEY_L9) +#define TEXT_HEIGHT 16 +#define TEXT_WIDTH 8 +#define MENU_FILE_XOFFSET (6*TEXT_WIDTH) +#define MENU_FILE_YOFFSET (2*TEXT_HEIGHT) +#define MENU_FILE_W (MAX_FILENAME_SIZE*TEXT_WIDTH) +#define MENU_FILE_H (MAX_MENULINES*TEXT_HEIGHT) +#define MENU_FILE_FGCOLOR RGBVAL16(0xff,0xff,0xff) +#define MENU_FILE_BGCOLOR RGBVAL16(0x00,0x00,0x20) +#define MENU_JOYS_YOFFSET (12*TEXT_HEIGHT) +#define MENU_VBAR_XOFFSET (0*TEXT_WIDTH) +#define MENU_VBAR_YOFFSET (MENU_FILE_YOFFSET) + + +#define MKEY_L1 1 +#define MKEY_L2 2 +#define MKEY_L3 3 +#define MKEY_L4 4 +#define MKEY_L5 5 +#define MKEY_L6 6 +#define MKEY_L7 7 +#define MKEY_L8 8 +#define MKEY_L9 9 +#define MKEY_UP 20 +#define MKEY_DOWN 21 +#define MKEY_JOY 22 + + +const unsigned short menutouchareas[] = { + TAREA_XY,MENU_FILE_XOFFSET,MENU_FILE_YOFFSET, + TAREA_WH,MENU_FILE_W, TEXT_HEIGHT, + TAREA_NEW_COL,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT, + + TAREA_XY,MENU_VBAR_XOFFSET,MENU_VBAR_YOFFSET, + TAREA_WH,32,48, + TAREA_NEW_COL, 72,72,8,40, + + TAREA_END}; + +const unsigned short menutouchactions[] = { + MKEY_L1,MKEY_L2,MKEY_L3,MKEY_L4,MKEY_L5,MKEY_L6,MKEY_L7,MKEY_L8,MKEY_L9, + MKEY_UP,MKEY_DOWN,ACTION_NONE,MKEY_JOY}; + + +static bool menuOn=true; +static bool callibrationOn=false; +static int callibrationStep=0; +static bool menuRedraw=true; +static int nbFiles=0; +static int curFile=0; +static int topFile=0; +static char selection[MAX_FILENAME_SIZE+1]=""; +static uint8_t prev_zt=0; + +static int readNbFiles(void) { + int totalFiles = 0; + + DIR* dir = opendir(romspath); + while (true) { + struct dirent* de = readdir(dir); + if (!de) { + // no more files + break; + } + if (de->d_type == DT_REG) { + totalFiles++; + } + else if (de->d_type == DT_DIR) { + if ( (strcmp(de->d_name,".")) && (strcmp(de->d_name,"..")) ) { + totalFiles++; + } + } + } + closedir(dir); + return totalFiles; +} + +static char captureTouchZone(const unsigned short * areas, const unsigned short * actions, int *rx, int *ry, int *rw, int * rh) { + uint16_t xt=0; + uint16_t yt=0; + uint16_t zt=0; + bool hDir=true; + + if (tft.isTouching()) + { + if (prev_zt == 0) { + prev_zt =1; + tft.readCal(&xt,&yt,&zt); + if (zt<1000) { + prev_zt=0; + return ACTION_NONE; + } + int i=0; + int k=0; + int y2=0, y1=0; + int x2=0, x1=0; + int x=KEYBOARD_X,y=KEYBOARD_Y; + int w=TAREA_W_DEF,h=TAREA_H_DEF; + uint8_t s; + while ( (s=areas[i++]) != TAREA_END ) { + if (s == TAREA_XY) { + x = areas[i++]; + y = areas[i++]; + x2 = x; + y2 = y; + } + else if (s == TAREA_WH) { + w = areas[i++]; + h = areas[i++]; + } + else if (s == TAREA_NEW_ROW) { + hDir = true; + y1 = y2; + y2 = y1 + h; + x2 = x; + } + else if (s == TAREA_NEW_COL) { + hDir = false; + x1 = x2; + x2 = x1 + w; + y2 = y; + } + else { + if (hDir) { + x1 = x2; + x2 = x1+s; + } else { + y1 = y2; + y2 = y1+s; + } + if ( (yt >= y1) && (yt < y2) && (xt >= x1) && (xt < x2) ) { + *rx = x1; + *ry = y1; + *rw = x2-x1; + *rh = y2-y1; + return (actions[k]); + } + k++; + } + } + } + prev_zt =1; + } else { + prev_zt=0; + } + + return ACTION_NONE; +} + +void toggleMenu(bool on) { + if (on) { + callibrationOn=false; + menuOn=true; + menuRedraw=true; + tft.fillScreenNoDma(RGBVAL16(0x00,0x00,0x00)); + tft.drawTextNoDma(0,0, TITLE, RGBVAL16(0x00,0xff,0xff), RGBVAL16(0x00,0x00,0xff), true); + tft.drawSpriteNoDma(MENU_VBAR_XOFFSET,MENU_VBAR_YOFFSET,(uint16_t*)bmpvbar); + } else { + menuOn = false; + } +} + + +static void callibrationInit(void) +{ + callibrationOn=true; + menuOn=false; + callibrationStep = 0; + calMinX=0,calMinY=0,calMaxX=0,calMaxY=0; + tft.fillScreenNoDma(RGBVAL16(0xff,0xff,0xff)); + tft.drawTextNoDma(0,100, " Callibration process:", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,116, " Hit the red cross at each corner", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,0, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + prev_zt = 1; +} + +static void readCallibration(void) +{ + FILE * file = fopen(CALIBRATION_FILE, "rb"); + if (file) { + fscanf(file,"%d %d %d %d\n",&calMinX,&calMinY,&calMaxX,&calMaxY); + fclose(file); + printf("Current callibration params: %d %d %d %d\n",calMinX,calMinY,calMaxX,calMaxY); + } + else { + printf("Callibration read error\n"); + } + tft.callibrateTouch(calMinX,calMinY,calMaxX,calMaxY); +} + +static void writeCallibration(void) +{ + tft.callibrateTouch(calMinX,calMinY,calMaxX,calMaxY); + FILE * file = fopen(CALIBRATION_FILE, "wb"); + if (file) { + fprintf(file,"%d %d %d %d\n",calMinX,calMinY,calMaxX,calMaxY); + fclose(file); + } + else { + printf("Callibration write error\n"); + } +} + + +bool callibrationActive(void) +{ + return (callibrationOn); +} + + + +int handleCallibration(uint16_t bClick) { + uint16_t xt=0; + uint16_t yt=0; + uint16_t zt=0; + if (tft.isTouching()) { + if (prev_zt == 0) { + prev_zt = 1; + tft.readRaw(&xt,&yt,&zt); + if (zt < 1000) { + return 0; + } + switch (callibrationStep) + { + case 0: + callibrationStep++; + tft.drawTextNoDma(0,0, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(ILI9341_TFTREALWIDTH-8,0, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMinX += xt; + calMinY += yt; + break; + case 1: + callibrationStep++; + tft.drawTextNoDma(ILI9341_TFTREALWIDTH-8,0, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(ILI9341_TFTREALWIDTH-8,ILI9341_TFTREALHEIGHT-16, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMaxX += xt; + calMinY += yt; + break; + case 2: + callibrationStep++; + tft.drawTextNoDma(ILI9341_TFTREALWIDTH-8,ILI9341_TFTREALHEIGHT-16, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,ILI9341_TFTREALHEIGHT-16, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMaxX += xt; + calMaxY += yt; + break; + case 3: + tft.fillScreenNoDma(RGBVAL16(0xff,0xff,0xff)); + tft.drawTextNoDma(0,100, " Callibration done!", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,116, " (Click center to exit)", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + callibrationStep++; + calMinX += xt; + calMaxY += yt; + break; + case 4: + if ( (xt > (ILI9341_TFTREALWIDTH/4)) && (xt < (ILI9341_TFTREALWIDTH*3)/4) + && (yt > (ILI9341_TFTREALHEIGHT/4)) && (yt < (ILI9341_TFTREALHEIGHT*3)/4) ) { + calMinX /= 2; + calMinY /= 2; + calMaxX /= 2; + calMaxY /= 2; + writeCallibration(); + toggleMenu(true); + } + else { + callibrationInit(); + } + break; + + } + vTaskDelay(100 / portTICK_PERIOD_MS); + } + } + else { + prev_zt = 0; + } + return 1; +} + + + +bool menuActive(void) +{ + return (menuOn); +} + +int handleMenu(uint16_t bClick) +{ + int action = ACTION_NONE; + + char newpath[80]; + strcpy(newpath, romspath); + strcat(newpath, "/"); + strcat(newpath, selection); + + struct stat st; + bool newPathIsDir = false; + if(stat(newpath,&st) == 0) + if((st.st_mode & S_IFDIR) != 0) + newPathIsDir = true; + + int rx=0,ry=0,rw=0,rh=0; + char c = captureTouchZone(menutouchareas, menutouchactions, &rx,&ry,&rw,&rh); + if ( ( (bClick & MASK_JOY2_BTN) || (bClick & MASK_KEY_USER1) ) && (newPathIsDir) ) { + menuRedraw=true; + strcpy(romspath,newpath); + curFile = 0; + nbFiles = readNbFiles(); + } + else if ( (c >= MKEY_L1) && (c <= MKEY_L9) ) { + if ( (topFile+(int)c-1) <= (nbFiles-1) ) + { + curFile = topFile + (int)c -1; + menuRedraw=true; + //tft.drawRectNoDma( rx,ry,rw,rh, KEYBOARD_HIT_COLOR ); + } + } + else if ( (bClick & MASK_JOY2_BTN) ) { + menuRedraw=true; + action = ACTION_RUNTFT; + } + else if (bClick & MASK_JOY2_UP) { + if (curFile!=0) { + menuRedraw=true; + curFile--; + } + } + else if ( (bClick & MASK_JOY2_RIGHT) || (c == MKEY_UP) ) { + if ((curFile-9)>=0) { + menuRedraw=true; + curFile -= 9; + } else if (curFile!=0) { + menuRedraw=true; + curFile--; + } + } + else if (bClick & MASK_JOY2_DOWN) { + if ((curFile<(nbFiles-1)) && (nbFiles)) { + curFile++; + menuRedraw=true; + } + } + else if ( (bClick & MASK_JOY2_LEFT) || (c == MKEY_DOWN) ) { + if ((curFile<(nbFiles-9)) && (nbFiles)) { + curFile += 9; + menuRedraw=true; + } + else if ((curFile<(nbFiles-1)) && (nbFiles)) { + curFile++; + menuRedraw=true; + } + } + else if ( (bClick & MASK_KEY_USER1) || (c == MKEY_JOY) ) { + emu_SwapJoysticks(0); + menuRedraw=true; + } + + + if (menuRedraw && nbFiles) { + + int fileIndex = 0; + DIR* dir = opendir(romspath); + tft.drawRectNoDma(MENU_FILE_XOFFSET,MENU_FILE_YOFFSET, MENU_FILE_W, MENU_FILE_H, MENU_FILE_BGCOLOR); +// if (curFile <= (MAX_MENULINES/2-1)) topFile=0; +// else topFile=curFile-(MAX_MENULINES/2); + if (curFile <= (MAX_MENULINES-1)) topFile=0; + else topFile=curFile-(MAX_MENULINES/2); + + int i=0; + while (id_type == DT_REG) || ((de->d_type == DT_DIR) && (strcmp(de->d_name,".")) && (strcmp(de->d_name,"..")) ) ) { + if (fileIndex >= topFile) { + if ((i+topFile) < nbFiles ) { + if ((i+topFile)==curFile) { + tft.drawTextNoDma(MENU_FILE_XOFFSET,i*TEXT_HEIGHT+MENU_FILE_YOFFSET, de->d_name, RGBVAL16(0xff,0xff,0x00), RGBVAL16(0xff,0x00,0x00), true); + strcpy(selection,de->d_name); + } + else { + tft.drawTextNoDma(MENU_FILE_XOFFSET,i*TEXT_HEIGHT+MENU_FILE_YOFFSET, de->d_name, MENU_FILE_FGCOLOR, MENU_FILE_BGCOLOR, true); + } + } + i++; + } + fileIndex++; + } + } + closedir(dir); + + tft.drawSpriteNoDma(0,MENU_JOYS_YOFFSET,(uint16_t*)bmpjoy); + tft.drawTextNoDma(48,MENU_JOYS_YOFFSET+8, (emu_SwapJoysticks(1)?(char*)"SWAP=1":(char*)"SWAP=0"), RGBVAL16(0x00,0xff,0xff), RGBVAL16(0xff,0x00,0x00), false); + + menuRedraw=false; + } + + + return (action); +} + +char * menuSelection(void) +{ + static char nnewpath[80]; + strcpy(nnewpath, romspath); + strcat(nnewpath, "/"); + strcat(nnewpath, selection); + return (nnewpath); +} + +#ifdef HAS_I2CKBD +#ifdef USE_WIRE +#else +static esp_err_t i2c_master_read_slave_reg(i2c_port_t i2c_num, uint8_t i2c_addr, uint8_t* data_rd, size_t size) +{ + if (size == 0) { + return ESP_OK; + } + i2c_cmd_handle_t cmd = i2c_cmd_link_create(); + i2c_master_start(cmd); + i2c_master_write_byte(cmd, ( i2c_addr << 1 ) | I2C_MASTER_READ, ACK_CHECK_EN); + if (size > 1) { + i2c_master_read(cmd, data_rd, size - 1, (i2c_ack_type_t)ACK_VAL); + } + i2c_master_read_byte(cmd, data_rd + size - 1, (i2c_ack_type_t)NACK_VAL); + i2c_master_stop(cmd); + esp_err_t ret = i2c_master_cmd_begin(i2c_num, cmd, 1000 / portTICK_RATE_MS); + i2c_cmd_link_delete(cmd); + return ret; +} +#endif +#endif + + +void emu_init(void) +{ + + esp_err_t ret = 0; + + printf("mounting sd...\n"); + + sdmmc_host_t host = SDSPI_HOST_DEFAULT(); + host.max_freq_khz = 10000; + //host.slot = HSPI_HOST; + + sdspi_slot_config_t slot_config = SDSPI_SLOT_CONFIG_DEFAULT(); + slot_config.gpio_miso = SPIN_NUM_MISO; + slot_config.gpio_mosi = SPIN_NUM_MOSI; + slot_config.gpio_sck = SPIN_NUM_CLK; + slot_config.gpio_cs = SPIN_NUM_CS; + slot_config.dma_channel = 2; + + + esp_vfs_fat_sdmmc_mount_config_t mount_config = { + .format_if_mount_failed = false, + .max_files = 5, + .allocation_unit_size = 16 * 1024 + }; + + + + while((ret = esp_vfs_fat_sdmmc_mount("/sdcard", &host, &slot_config, &mount_config, &card)) != ESP_OK) { + printf("retrying\n"); + vTaskDelay(500 / portTICK_PERIOD_MS); + } + + strcpy(romspath,"/sdcard/"); + strcat(romspath,ROMSDIR); + printf("dir is : %s\n",romspath); + + nbFiles = readNbFiles(); + printf("SD initialized, files found: %d\n",nbFiles); + +/* + tft.touchBegin(); +*/ + + + emu_InitJoysticks(); +/* + readCallibration(); + + if ((tft.isTouching()) || (emu_ReadKeys() & MASK_JOY2_BTN) ) { + callibrationInit(); + } else { +*/ + toggleMenu(true); +/* + } +*/ + +#ifdef HAS_I2CKBD + uint8_t msg[7]={0,0,0,0,0,0,0}; + +#ifdef USE_WIRE + Wire.begin(I2C_SDA_IO, I2C_SCL_IO); + Wire.requestFrom(8, 7, I2C_FREQ_HZ); // request 5 bytes from slave device #8 + int i = 0; + int hitindex=-1; + while (Wire.available() && (i<7) ) { // slave may send less than requested + uint8_t b = Wire.read(); // receive a byte + if (b != 0xff) hitindex=i; + msg[i++] = b; + } +#else + int i2c_master_port = I2C_NUM_1; + i2c_config_t conf; + conf.mode = I2C_MODE_MASTER; + conf.sda_io_num = I2C_SDA_IO; + conf.sda_pullup_en = GPIO_PULLUP_ENABLE; + conf.scl_io_num = I2C_SCL_IO; + conf.scl_pullup_en = GPIO_PULLUP_ENABLE; + conf.master.clk_speed = I2C_FREQ_HZ; + i2c_param_config((i2c_port_t)i2c_master_port, &conf); + if (i2c_driver_install((i2c_port_t)i2c_master_port, conf.mode,0, 0, 0) != ESP_OK) + printf("I2C Failed initialized\n"); + + if (i2c_master_read_slave_reg( I2C_NUM_1, 8, &msg[0], 7 ) != ESP_OK) + printf("I2C Failed \n"); +#endif + + + + + if ( (msg[0] == 0xff) && (msg[1] == 0xff) && + (msg[2] == 0xff) && (msg[3] == 0xff) && + (msg[4] == 0xff) && (msg[5] == 0xff) && (msg[6] == 0xff)) { + i2cKeyboardPresent = true; + printf("i2C keyboard found\n"); + } + +#endif +} + + +void emu_printf(char * text) +{ + printf("%s\n",text); +} + + +void emu_printi(int val) +{ + printf("%d\n",val); +} + +void * emu_Malloc(int size) +{ + void * retval = malloc(size); + if (!retval) { + printf("failled to allocate %d\n",size); + } + else { + printf("could allocate %d\n",size); + } + + return retval; +} + +void emu_Free(void * pt) +{ + free(pt); +} + + +static FILE * lastfileOpened; + + +int emu_FileOpen(char * filename) +{ + int retval = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + //printf("FileOpen...%s\n",filepath); + + lastfileOpened = fopen(filepath, "rb"); + if (lastfileOpened) { + retval = 1; + } + else { + //printf("FileOpen failed\n"); + } + return (retval); +} + +int emu_FileRead(char * buf, int size) +{ + int retval = fread(buf, 1, size, lastfileOpened); + if (retval != size) { + printf("FileRead failed\n"); + } + return (retval); +} + +unsigned char emu_FileGetc(void) { + unsigned char c; + int retval = fread(&c, 1, 1, lastfileOpened); + if (retval != 1) { + printf("emu_FileGetc failed\n"); + } + return c; +} + + +void emu_FileClose(void) +{ + fclose(lastfileOpened); +} + +int emu_FileSize(char * filename) +{ + int filesize=0; + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + printf("FileSize...%s\n",filepath); + + FILE * file = fopen(filepath, "rb"); + if (file) { + fseek(file, 0L, SEEK_END); + filesize = ftell(file); + //fseek(file, 0L, SEEK_SET); + printf("filesize is...%d\n",filesize); + fclose(file); + } + + return(filesize); +} + +int emu_FileSeek(int seek) +{ + fseek(lastfileOpened, seek, SEEK_SET); + return (seek); +} + +int emu_LoadFile(char * filename, char * buf, int size) +{ + int filesize = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + printf("LoadFile...%s\n",filepath); + + filesize = emu_FileSize(filename); + FILE * file = fopen(filepath, "rb"); + if (file) { + if (size >= filesize) + { + if (fread(buf, 1, filesize, file) != filesize) { + printf("File read failed\n"); + } + } + fclose(file); + } + + return(filesize); +} + +int emu_LoadFileSeek(char * filename, char * buf, int size, int seek) +{ + int filesize = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + printf("LoadFileSeek...%d bytes at %d from %s\n",size,seek,filepath); + + FILE * file = fopen(filepath, "rb"); + if (file) { + fseek(file, seek, SEEK_SET); + if (fread(buf, size, 1, file) != size) { + printf("File read failed\n"); + } + fclose(file); + } + + return(filesize); +} + +static int keypadval=0; +static bool joySwapped = false; +static uint16_t bLastState; +static int xRef; +static int yRef; + +int emu_ReadAnalogJoyX(int min, int max) +{ + int val; //adc1_get_raw((adc1_channel_t)PIN_JOY2_A1X); + adc2_get_raw((adc2_channel_t)PIN_JOY2_A1X, ADC_WIDTH_BIT_12,&val); + //printf("refX:%d X:%d\n",xRef,val); + val = val-xRef; + //val = ((val*140)/100); + if ( (val > -xRef/4) && (val < xRef/4) ) val = 0; +#if INVX + val = xRef-val; +#else + val = val+xRef; +#endif + + return (val*(max-min))/(xRef*2); +} + +int emu_ReadAnalogJoyY(int min, int max) +{ + int val; //= adc1_get_raw((adc1_channel_t)PIN_JOY2_A2Y); + adc2_get_raw((adc2_channel_t)PIN_JOY2_A2Y, ADC_WIDTH_BIT_12,&val); + //printf("refY:%d Y:%d\n",yRef,val); + val = val-yRef; + //val = ((val*120)/100); + if ( (val > -yRef/4) && (val < yRef/4) ) val = 0; +#if INVY + val = yRef-val; +#else + val = val+yRef; +#endif + return (val*(max-min))/(yRef*2); +} + + +static uint16_t readAnalogJoystick(void) +{ + uint16_t joysval = 0; + + int xReading = emu_ReadAnalogJoyX(0,256); + if (xReading > 128) joysval |= MASK_JOY2_LEFT; + else if (xReading < 128) joysval |= MASK_JOY2_RIGHT; + + int yReading = emu_ReadAnalogJoyY(0,256); + if (yReading < 128) joysval |= MASK_JOY2_UP; + else if (yReading > 128) joysval |= MASK_JOY2_DOWN; + +#ifdef PIN_JOY2_BTN + joysval |= ((gpio_get_level((gpio_num_t)PIN_JOY2_BTN) == 1) ? 0 : MASK_JOY2_BTN); +#endif + + return (joysval); +} + + +int emu_SwapJoysticks(int statusOnly) { + if (!statusOnly) { + if (joySwapped) { + joySwapped = false; + } + else { + joySwapped = true; + } + } + return(joySwapped?1:0); +} + +int emu_GetPad(void) +{ + return(keypadval|((joySwapped?1:0)<<7)); +} + +int emu_ReadKeys(void) +{ + uint16_t retval; + uint16_t j1 = readAnalogJoystick(); + + uint16_t j2 = 0; + + if (joySwapped) { + retval = ((j1 << 8) | j2); + } + else { + retval = ((j2 << 8) | j1); + } + +#ifdef PIN_KEY_USER1 + if (gpio_get_level((gpio_num_t)PIN_KEY_USER1) == 0 ) retval |= MASK_KEY_USER1; +#endif +#ifdef PIN_KEY_USER2 + if (gpio_get_level((gpio_num_t)PIN_KEY_USER2) == 0 ) retval |= MASK_KEY_USER2; +#endif +#ifdef PIN_KEY_USER3 + if (gpio_get_level((gpio_num_t)PIN_KEY_USER3) == 0 ) retval |= MASK_KEY_USER3; +#endif +#ifdef PIN_KEY_USER4 + if (gpio_get_level((gpio_num_t)PIN_KEY_USER4) == 0 ) retval |= MASK_KEY_USER4; +#endif + + //printf("%d\n",retval); + return (retval); +} + +unsigned short emu_DebounceLocalKeys(void) +{ + uint16_t bCurState = emu_ReadKeys(); + uint16_t bClick = bCurState & ~bLastState; + bLastState = bCurState; + + return (bClick); +} + + +int emu_ReadI2CKeyboard(void) { + int retval=0; +#ifdef HAS_I2CKBD + if (i2cKeyboardPresent) { + uint8_t msg[7]; +#ifdef USE_WIRE + Wire.requestFrom(8, 7, I2C_FREQ_HZ); // request 5 bytes from slave device #8 + int i = 0; + int hitindex=-1; + while (Wire.available() && (i<7) ) { // slave may send less than requested + uint8_t b = Wire.read(); // receive a byte + if (b != 0xff) hitindex=i; + msg[i++] = b; + } +#else + if (i2c_master_read_slave_reg( I2C_NUM_1, 8, &msg[0], 7 ) != ESP_OK) + printf("I2C Failed \n"); + int hitindex=-1; + int i = 0; + while (i<7) { + if (msg[i] != 0xff) hitindex=i; + i++; + } +#endif + //printf("I2C 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X\n", + // msg[0],msg[1],msg[2],msg[3],msg[4],msg[5],msg[6]); + if ((hitindex >=0 ) && (hitindex <=6 )) { + unsigned short match = ((~msg[hitindex])&0x00FF) | (hitindex<<8); + for (i=0; i=1) && (c <= ACTION_MAXKBDVAL) ) { + keypadval = c; + keyPressCount = 10; + vTaskDelay(50 / portTICK_PERIOD_MS); + vkeyRefresh = true; + exitVkbd = true; + } + else if (c == ACTION_EXITKBD) { + vkeyRefresh = true; + exitVkbd = true; + } + } + } + + if (vkeyRefresh) { + vkeyRefresh = false; + tft.drawSpriteNoDma(0,0,(uint16_t*)logo, rx, ry, rw, rh); + } + + if ( (exitVkbd) && (vkbActive) ) { + if (!vkbKeepOn) { + toggleVirtualkeyboard(false); + } + else { + toggleVirtualkeyboard(true); + } + } +} + +int emu_setKeymap(int index) { + if (index) { + //logo = ; + //keysw = ; + } + else { + //logo = ; + //keysw = ; + } + return 0; +} + + + +static unsigned short palette16[PALETTE_SIZE]; +static int fskip=0; + +void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index) +{ + if (index +#define TITLE " ATARIST Emulator " +#define ROMSDIR "st" + +#define emu_Init(ROM) {mac_Init(); mac_Start(ROM); } +#define emu_Step(x) { mac_Step(); } +#define emu_Input(x) { mac_Input(x); } + +#define VID_FRAME_SKIP 0x3 +#define PALETTE_SIZE 16 +#define SINGLELINE_RENDERING 1 +#define TFT_VBUFFER_YCROP 0 + +#define ACTION_NONE 0 +#define ACTION_MAXKBDVAL 225 +#define ACTION_EXITKBD 128 +#define ACTION_RUNTFT 129 + +#ifdef KEYMAP_PRESENT + +#define TAREA_W_DEF 32 +#define TAREA_H_DEF 32 +#define TAREA_END 255 +#define TAREA_NEW_ROW 254 +#define TAREA_NEW_COL 253 +#define TAREA_XY 252 +#define TAREA_WH 251 + +#define KEYBOARD_X 16 +#define KEYBOARD_Y 32 +#define KEYBOARD_KEY_H 30 +#define KEYBOARD_KEY_W 28 +#define KEYBOARD_HIT_COLOR RGBVAL16(0xff,0x00,0x00) + +const unsigned short keysw[]= +{ TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + //TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_END}; + +const unsigned short keys[]={ + +59, 60, 61, 62, 63, 64, 65, 66, 67, 68, +109,110,111,112,106,107,108,17,18,19, +20,21,22,23,24,25,26,27,28,29, +30,31,32,33,34,35,36,37,38,57 }; + + + + +#ifdef HAS_I2CKBD +const unsigned short i2ckeys[] = { + 0X0080,0X0008,0X0180,0X0108,0X0280,0X0208,0X0380,0X0308,0X0480,0X0408, + 0X0040,0X0004,0X0140,0X0104,0X0240,0X0204,0X0340,0X0304,0X0440,0X0404, + 0X0020,0X0002,0X0120,0X0102,0X0220,0X0202,0X0320,0X0302,0X0420,0X0402, + 0X0010,0X0001,0X0110,0X0101,0X0210,0X0201,0X0310,0X0301,0X0410,0X0401 }; + //0X0580,0X0540,0X0520,0X0510,0X0508,0X0504,0X0502,0X0501,0X0680,0X0640 }; +#endif + +#endif + +#define MASK_JOY2_RIGHT 0x0001 +#define MASK_JOY2_LEFT 0x0002 +#define MASK_JOY2_UP 0x0004 +#define MASK_JOY2_DOWN 0x0008 +#define MASK_JOY2_BTN 0x0010 +#define MASK_KEY_USER1 0x0020 +#define MASK_KEY_USER2 0x0040 +#define MASK_KEY_USER3 0x0080 +#define MASK_JOY1_RIGHT 0x0100 +#define MASK_JOY1_LEFT 0x0200 +#define MASK_JOY1_UP 0x0400 +#define MASK_JOY1_DOWN 0x0800 +#define MASK_JOY1_BTN 0x1000 +#define MASK_KEY_USER4 0x2000 + + +extern void emu_init(void); +extern void emu_printf(char * text); +extern void emu_printi(int val); +extern void * emu_Malloc(int size); +extern void emu_Free(void * pt); + +extern int emu_FileOpen(char * filename); +extern int emu_FileRead(char * buf, int size); +extern unsigned char emu_FileGetc(void); +extern int emu_FileSeek(int seek); +extern void emu_FileClose(void); +extern int emu_FileSize(char * filename); +extern int emu_LoadFile(char * filename, char * buf, int size); +extern int emu_LoadFileSeek(char * filename, char * buf, int size, int seek); + +extern void emu_InitJoysticks(void); +extern int emu_SwapJoysticks(int statusOnly); +extern unsigned short emu_DebounceLocalKeys(void); +extern int emu_ReadKeys(void); +extern int emu_GetPad(void); +extern int emu_ReadAnalogJoyX(int min, int max); +extern int emu_ReadAnalogJoyY(int min, int max); +extern int emu_ReadI2CKeyboard(void); +extern int emu_setKeymap(int index); + +extern void emu_sndInit(); +extern void emu_sndPlaySound(int chan, int volume, int freq); +extern void emu_sndPlayBuzz(int size, int val); + +extern void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index); +extern void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride); +extern void emu_DrawLine(unsigned char * VBuf, int width, int height, int line); +extern void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line); +extern void emu_DrawVsync(void); +extern int emu_FrameSkip(void); + + +#endif + + + + diff --git a/MCUME_esp32/espcastaway/main/fdc.cpp b/MCUME_esp32/espcastaway/main/fdc.cpp new file mode 100755 index 0000000..35244a5 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/fdc.cpp @@ -0,0 +1,520 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* fdc.c - wd1772/dma emulation +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 0.02.00 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 09.06.2002 0.02.00 JH Renamed io.c to st.c again (io.h conflicts with system headers) +*/ +static char sccsid[] = "$Id: fdc.c,v 1.2 2002/06/08 23:31:58 jhoenig Exp $"; +#include +#include +#include +#include "config.h" +#include "st.h" + +#define FLOPPY 1 + +#define DISKNULL \ + "\0\0\0\0\0\0\0\0\0\0" \ + "\0\0\0\0\0\0\0\0\0\0" \ + "\0\0\0\0\0\0\0\0\0\0" \ + "\0\0\0\0\0\0\0\0\0\0" \ + "\0\0\0\0\0\0\0\0\0\0" \ + "\0\0\0\0\0\0\0\0\0\0" \ + "\0\0\0\0\0\0\0\0\0\0" \ + "\0\0\0\0\0\0\0\0\0" + +int fdc_commands_executed=0; + +extern int dcastaway_disc_writed[2]; +void dcastaway_disc_initsave(unsigned num); + +/* +* FDC Registers +*/ +extern int readdsk; +unsigned char fdc_data, fdc_track, fdc_sector, fdc_status, fdc_command, fdc_motor; +unsigned char fdc_int = 0; +char fdcdir=1; +unsigned char disk_ejected[2]={0,1}; +unsigned char disk_changed[2]; +struct Disk disk[2] = { + { NULL, DISKNULL, 0, SIDES, TRACKS, SECTORS, SECSIZE }, + { NULL, DISKNULL, 0, SIDES, TRACKS, SECTORS, SECSIZE }, +}; + +typedef struct { + uint16 ID; // Word ID marker, should be $0E0F + uint16 SectorsPerTrack; // Word Sectors per track + uint16 Sides; // Word Sides (0 or 1; add 1 to this to get correct number of sides) + uint16 StartingTrack; // Word Starting track (0-based) + uint16 EndingTrack; // Word Ending track (0-based) +} MSAHEADERSTRUCT; +#define STMemory_Swap68000Int(val) ((val<<8)|(val>>8)) + + +unsigned char *msabuff; +unsigned char *disc[2]; + +int discpos[2]; + +int discread(unsigned char *buf,int a,int len,int discn) +{ + int i; + uint8 val1,val2,*dbuf; + dbuf=buf; + for (i=0;i(1050*1024)){ + return -1; + } + discpos[discn]=pos; + return 0; +} + + +int MSA_UnCompress(unsigned char *pBuffer) +{ + MSAHEADERSTRUCT *pMSAHeader; + unsigned char *pMSAImageBuffer,*pImageBuffer; + unsigned char Byte,Data; + int ImageSize = 0; + int i,Track,Side,DataLength,NumBytesUnCompressed,RunLength; + for (i=0;i<1050*1024;i++) msabuff[i]=pBuffer[i]; + // Is an '.msa' file?? Check header + pMSAHeader = (MSAHEADERSTRUCT *)msabuff; + if (pMSAHeader->ID==0x0F0E) { + // First swap 'header' words around to PC format - easier later on + pMSAHeader->SectorsPerTrack = STMemory_Swap68000Int(pMSAHeader->SectorsPerTrack); + pMSAHeader->Sides = STMemory_Swap68000Int(pMSAHeader->Sides); + pMSAHeader->StartingTrack = STMemory_Swap68000Int(pMSAHeader->StartingTrack); + pMSAHeader->EndingTrack = STMemory_Swap68000Int(pMSAHeader->EndingTrack); + + // Set pointers + pImageBuffer = (unsigned char *)pBuffer; + pMSAImageBuffer = (unsigned char *)((unsigned long)msabuff+sizeof(MSAHEADERSTRUCT)); + + // Uncompress to memory as '.ST' disc image - NOTE assumes 512 bytes per sector(use NUMBYTESPERSECTOR define)!!! + for(Track=pMSAHeader->StartingTrack; Track<(pMSAHeader->EndingTrack+1); Track++) { + for(Side=0; Side<(pMSAHeader->Sides+1); Side++) { + // Uncompress MSA Track, first check if is not compressed + DataLength = ((uint16)(*pMSAImageBuffer)<<8)|((uint16)(*(pMSAImageBuffer+1))&0xff); + pMSAImageBuffer += sizeof(short int); + if (DataLength==(512*pMSAHeader->SectorsPerTrack)) { + // No compression on track, simply copy and continue + memcpy(pImageBuffer,pMSAImageBuffer,512*pMSAHeader->SectorsPerTrack); + pImageBuffer += 512*pMSAHeader->SectorsPerTrack; + pMSAImageBuffer += DataLength; + } + else { + // Uncompress track + NumBytesUnCompressed = 0; + while(NumBytesUnCompressed<(512*pMSAHeader->SectorsPerTrack)) { + Byte = *pMSAImageBuffer++; + if (Byte!=0xE5) { // Compressed header?? + *pImageBuffer++ = Byte; // No, just copy byte + NumBytesUnCompressed++; + } + else { + Data = *pMSAImageBuffer++; // Byte to copy + RunLength =((uint16)(*pMSAImageBuffer)<<8)|((uint16)(*(pMSAImageBuffer+1))&0xff); // For length + // Limit length to size of track, incorrect images may overflow + if ( (RunLength+NumBytesUnCompressed)>(512*pMSAHeader->SectorsPerTrack) ) + RunLength = (512*pMSAHeader->SectorsPerTrack)-NumBytesUnCompressed; + pMSAImageBuffer += sizeof(short int); + for(i=0; i (500*1024)) calcsides = 2; + else calcsides = 1; + if (!(((len/calcsides)/512)%9)&&(((len/calcsides)/512)/9)<86) calcsectors=9; + else if (!(((len/calcsides)/512)%10)&&(((len/calcsides)/512)/10)<86) calcsectors=10; + else if (!(((len/calcsides)/512)%11)&&(((len/calcsides)/512)/11)<86) calcsectors=11; + else if (!(((len/calcsides)/512)%12)) calcsectors=12; + calctracks =((len/calcsides)/512)/calcsectors; + + if (disk[i].sides!=calcsides||disk[i].sectors!=calcsectors||disk[i].tracks!=calctracks){ + if (disk[i].sides==calcsides&&disk[i].sectors==calcsectors){ + disk[i].tracks=calctracks; + badbootsector=0; + }else{ + disk[i].sides=calcsides; + disk[i].tracks=calctracks; + disk[i].sectors=calcsectors; + badbootsector=(i<<24)|(calcsides<<16)|(calctracks<<8)|(calcsectors); + } + + }else{ + badbootsector=0; + } + disk_ejected[i]=0; + disk_changed[i]=1; + fdc_status |= 0x40; + disk[i].head = 0; + fdc_track = 0; + } + + //dcastaway_disc_initsave(i); + + return badbootsector; +} + +void FDCchange(int i){ + disk[(i>>24)&0xff].sides=(i>>16)&0xff; + disk[(i>>24)&0xff].tracks=(i>>8)&0xff; + disk[(i>>24)&0xff].sectors=i&0xff; +} + +void FDCeject(int num){ + int i; + for (i=0;i<1050*1024;i++) disc[num][i]=0; + disk[num].file = NULL; + sprintf(disk[num].name,"disk%01d",num); + disk[num].sides = SIDES; + disk[num].tracks = TRACKS; + disk[num].sectors = SECTORS; + disk[num].secsize = 512; + disk_ejected[num]=1; + fdc_status |= 0x40; +} + +void FDCCommand(void) +{ + static char motor = 1; + int sides, drives; + long address; /* dma target/source address */ + long offset; /* offset in disk file */ + unsigned long count; /* number of byte to transfer */ + char *buffer; + int n; + + if (fdc_commands_executed<64) + fdc_commands_executed++; + /* DMA target/source address */ + address = (dma_adrh << 16) + (dma_adrm << 8) + dma_adrl; + /* if (address>MEMSIZE){ + #ifdef DISASS + StartDisass(); + exit(1); + #endif + fdc_status |= 0x10; + return; + + + + } + */ + buffer = (char *)(membase + address); + /* status of side select and drive select lines */ + sides = (~psg[14]) & 0x1; + drives = (~psg[14]) & 0x6; + if (disk_ejected[drives>>2]==1) drives=2; + switch (drives) { + case 2: /* Drive A */ + drives = 0; + break; + case 4: /* Drive B */ + drives = 1; + break; + case 6: /* both, error */ + case 0: /* no drive selected */ + drives = -1; + break; + } + fdc_status = 0; /* clear fdc status */ + +#if FLOPPY + + if (fdc_command < 0x80) { /* TYPE-I fdc commands */ + if (drives >= 0) { /* drive selected */ + switch (fdc_command & 0xf0) { + case 0x00: /* RESTORE */ + disk[drives].head = 0; + fdc_track = 0; + break; + case 0x10: /* SEEK */ + disk[drives].head += (fdc_data - fdc_track); + fdc_track = fdc_data; + if (disk[drives].head < 0 + || disk[drives].head >= disk[drives].tracks) + disk[drives].head = 0; + break; + case 0x30: /* STEP */ + fdc_track += fdcdir; + case 0x20: + disk[drives].head += fdcdir; + break; + case 0x50: /* STEP-IN */ + fdc_track++; + case 0x40: + if (disk[drives].head < disk[drives].tracks) + disk[drives].head++; + fdcdir = 1; + break; + case 0x70: /* STEP-OUT */ + fdc_track--; + case 0x60: + if (disk[drives].head > 0) + disk[drives].head--; + fdcdir = -1; + break; + } + if (disk[drives].head == 0) { + fdc_status |= 0x4; + } + if (disk[drives].head != fdc_track && fdc_command & 0x4) { /* Verify? */ + fdc_status |= 0x10; + } + if (motor) { + fdc_status |= 0x20; /* spin-up flag */ + } + } else { /* no drive selected */ + fdc_status |= 0x10; + } + } else if ((fdc_command & 0xf0) == 0xd0) { /* FORCE INTERRUPT */ + if (fdc_command == 0xd8) { + fdc_int = 1; + } else if (fdc_command == 0xd0) { + fdc_int = 0; + } + } else { /* OTHERS */ + if (drives >= 0) { /* drive selected */ + /* offset within floppy-file */ + offset = disk[drives].secsize * + (((disk[drives].sectors * disk[drives].sides * disk[drives].head)) + + (disk[drives].sectors * sides) + (fdc_sector - 1)); + switch (fdc_command & 0xf0) { + case 0x80: /* READ SECTOR */ + count = 512; + if (!discseek (drives, offset, 0)) { + if (address> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + break; + } + }else{ + address += count; + dma_adrl = address & 0xff; + dma_adrm = (address >> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + mfp_gpip |= 0x20; + fdc_status |= 0x1; + break; + } + } + fdc_status |= 0x10; + dma_sr = 1; + break; + case 0x90: /* READ SECTOR multiple */ + count = dma_scr * 512; + if (count+(fdc_sector-1)*512>disk[drives].sectors*512) count=disk[drives].sectors*512-(fdc_sector-1)*512; + if (!discseek (drives, offset, 0)) { + if (address> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + fdc_sector += count/disk[drives].secsize; + break; + } + }else{ + address += count; + dma_adrl = address & 0xff; + dma_adrm = (address >> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + mfp_gpip |= 0x20; + fdc_status |= 0x1; + break; + } + } + fdc_status |= 0x10; + dma_sr = 1; + break; + case 0xa0: /* WRITE SECTOR */ + count = dma_scr * 512; + if (!discseek (drives, offset, 0)) { + if (count == discwrite ((unsigned char *)buffer, 1, count, drives)) { + address += count; + dma_adrl = address & 0xff; + dma_adrm = (address >> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + break; + } + } + fdc_status |= 0x10; + dma_sr = 1; + break; + case 0xb0: /* WRITE SECTOR multiple */ + count = dma_scr * 512; + if (!discseek (drives, offset, 0)) { + if (count == discwrite ((unsigned char *)buffer, 1, count, drives)) { + address += count; + dma_adrl = address & 0xff; + dma_adrm = (address >> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + fdc_sector += dma_scr * (512 / disk[drives].secsize); + break; + } + } + fdc_status |= 0x10; + dma_sr = 1; + break; + case 0xc0: /* READ ADDRESS */ + fdc_status |= 0x10; + break; + case 0xe0: /* READ TRACK */ + count = disk[drives].sectors * 512; + offset = disk[drives].secsize * + (((disk[drives].sectors * disk[drives].sides * disk[drives].head)) + + (disk[drives].sectors * sides)); + if (!discseek (drives, offset, 0)) { + if (address> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + break; + } + }else{ + address += 302; + dma_adrl = address & 0xff; + dma_adrm = (address >> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + mfp_gpip |= 0x20; + fdc_status |= 0x1; + break; + } + } + fdc_status |= 0x10; + dma_sr = 1; + break; + case 0xf0: /* WRITE TRACK */ + fdc_status |= 0x10; + break; + } + if (disk[drives].head != fdc_track) { + fdc_status |= 0x10; + } + } else { + fdc_status |= 0x10; /* no drive selected */ + } + } +#endif + if (motor) { + fdc_status |= 0x80; /* motor on flag */ + fdc_motor=1; + } + if (!(fdc_status & 0x01)) { /* not busy */ + mfp_iprb |= (0x80 & mfp_ierb); /* Request Interrupt */ + mfp_gpip &= ~0x20; + } +} diff --git a/MCUME_esp32/espcastaway/main/fdc.cpp_new b/MCUME_esp32/espcastaway/main/fdc.cpp_new new file mode 100644 index 0000000..c81a19f --- /dev/null +++ b/MCUME_esp32/espcastaway/main/fdc.cpp_new @@ -0,0 +1,549 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* fdc.c - wd1772/dma emulation +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 0.02.00 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 09.06.2002 0.02.00 JH Renamed io.c to st.c again (io.h conflicts with system headers) +*/ +static char sccsid[] = "$Id: fdc.c,v 1.2 2002/06/08 23:31:58 jhoenig Exp $"; +#include +#include +#include +#include "config.h" +#include "st.h" + +//#define MEMDISC 1 +#define DISK 1 + +#define DISKNULL \ + "\0\0\0\0\0\0\0\0\0\0" \ + "\0\0\0\0\0\0\0\0\0\0" \ + "\0\0\0\0\0\0\0\0\0\0" \ + "\0\0\0\0\0\0\0\0\0\0" \ + "\0\0\0\0\0\0\0\0\0\0" \ + "\0\0\0\0\0\0\0\0\0\0" \ + "\0\0\0\0\0\0\0\0\0\0" \ + "\0\0\0\0\0\0\0\0\0" + +int fdc_commands_executed=0; + +extern int dcastaway_disc_writed[2]; +void dcastaway_disc_initsave(unsigned num); + +/* +* FDC Registers +*/ +extern int readdsk; +unsigned char fdc_data, fdc_track, fdc_sector, fdc_status, fdc_command, fdc_motor; +unsigned char fdc_int = 0; +char fdcdir=1; +unsigned char disk_ejected[2]={0,1}; +unsigned char disk_changed[2]; +struct Disk disk[2] = { + { NULL, DISKNULL, 0, SIDES, TRACKS, SECTORS, SECSIZE }, + { NULL, DISKNULL, 0, SIDES, TRACKS, SECTORS, SECSIZE }, +}; + +typedef struct { + uint16 ID; // Word ID marker, should be $0E0F + uint16 SectorsPerTrack; // Word Sectors per track + uint16 Sides; // Word Sides (0 or 1; add 1 to this to get correct number of sides) + uint16 StartingTrack; // Word Starting track (0-based) + uint16 EndingTrack; // Word Ending track (0-based) +} MSAHEADERSTRUCT; +#define STMemory_Swap68000Int(val) ((val<<8)|(val>>8)) + + +unsigned char *msabuff; +unsigned char *disc[2]; + +int discpos[2]; + +int discread(unsigned char *buf,int a,int len,int discn) +{ + int i; + uint8 val1,val2,*dbuf; + dbuf=buf; +#ifdef MEMDISC + for (i=0;i(1050*1024)){ + return -1; + } + discpos[discn]=pos; +#ifdef MEMDISC +#else + if (disk[discn].file) fseek(disk[discn].file,pos,SEEK_SET); +#endif + return 0; +} + + +int MSA_UnCompress(unsigned char *pBuffer) +{ + MSAHEADERSTRUCT *pMSAHeader; + unsigned char *pMSAImageBuffer,*pImageBuffer; + unsigned char Byte,Data; + int ImageSize = 0; + int i,Track,Side,DataLength,NumBytesUnCompressed,RunLength; + for (i=0;i<1050*1024;i++) msabuff[i]=pBuffer[i]; + // Is an '.msa' file?? Check header + pMSAHeader = (MSAHEADERSTRUCT *)msabuff; + if (pMSAHeader->ID==0x0F0E) { + // First swap 'header' words around to PC format - easier later on + pMSAHeader->SectorsPerTrack = STMemory_Swap68000Int(pMSAHeader->SectorsPerTrack); + pMSAHeader->Sides = STMemory_Swap68000Int(pMSAHeader->Sides); + pMSAHeader->StartingTrack = STMemory_Swap68000Int(pMSAHeader->StartingTrack); + pMSAHeader->EndingTrack = STMemory_Swap68000Int(pMSAHeader->EndingTrack); + + // Set pointers + pImageBuffer = (unsigned char *)pBuffer; + pMSAImageBuffer = (unsigned char *)((unsigned long)msabuff+sizeof(MSAHEADERSTRUCT)); + + // Uncompress to memory as '.ST' disc image - NOTE assumes 512 bytes per sector(use NUMBYTESPERSECTOR define)!!! + for(Track=pMSAHeader->StartingTrack; Track<(pMSAHeader->EndingTrack+1); Track++) { + for(Side=0; Side<(pMSAHeader->Sides+1); Side++) { + // Uncompress MSA Track, first check if is not compressed + DataLength = ((uint16)(*pMSAImageBuffer)<<8)|((uint16)(*(pMSAImageBuffer+1))&0xff); + pMSAImageBuffer += sizeof(short int); + if (DataLength==(512*pMSAHeader->SectorsPerTrack)) { + // No compression on track, simply copy and continue + memcpy(pImageBuffer,pMSAImageBuffer,512*pMSAHeader->SectorsPerTrack); + pImageBuffer += 512*pMSAHeader->SectorsPerTrack; + pMSAImageBuffer += DataLength; + } + else { + // Uncompress track + NumBytesUnCompressed = 0; + while(NumBytesUnCompressed<(512*pMSAHeader->SectorsPerTrack)) { + Byte = *pMSAImageBuffer++; + if (Byte!=0xE5) { // Compressed header?? + *pImageBuffer++ = Byte; // No, just copy byte + NumBytesUnCompressed++; + } + else { + Data = *pMSAImageBuffer++; // Byte to copy + RunLength =((uint16)(*pMSAImageBuffer)<<8)|((uint16)(*(pMSAImageBuffer+1))&0xff); // For length + // Limit length to size of track, incorrect images may overflow + if ( (RunLength+NumBytesUnCompressed)>(512*pMSAHeader->SectorsPerTrack) ) + RunLength = (512*pMSAHeader->SectorsPerTrack)-NumBytesUnCompressed; + pMSAImageBuffer += sizeof(short int); + for(i=0; i (500*1024)) calcsides = 2; + else calcsides = 1; + if (!(((len/calcsides)/512)%9)&&(((len/calcsides)/512)/9)<86) calcsectors=9; + else if (!(((len/calcsides)/512)%10)&&(((len/calcsides)/512)/10)<86) calcsectors=10; + else if (!(((len/calcsides)/512)%11)&&(((len/calcsides)/512)/11)<86) calcsectors=11; + else if (!(((len/calcsides)/512)%12)) calcsectors=12; + calctracks =((len/calcsides)/512)/calcsectors; + + if (disk[i].sides!=calcsides||disk[i].sectors!=calcsectors||disk[i].tracks!=calctracks){ + if (disk[i].sides==calcsides&&disk[i].sectors==calcsectors){ + disk[i].tracks=calctracks; + badbootsector=0; + }else{ + disk[i].sides=calcsides; + disk[i].tracks=calctracks; + disk[i].sectors=calcsectors; + badbootsector=(i<<24)|(calcsides<<16)|(calctracks<<8)|(calcsectors); + } + + }else{ + badbootsector=0; + } + disk_ejected[i]=0; + disk_changed[i]=1; + fdc_status |= 0x40; + disk[i].head = 0; + fdc_track = 0; + } + + //dcastaway_disc_initsave(i); + + return badbootsector; +} + +void FDCchange(int i){ + disk[(i>>24)&0xff].sides=(i>>16)&0xff; + disk[(i>>24)&0xff].tracks=(i>>8)&0xff; + disk[(i>>24)&0xff].sectors=i&0xff; +} + +void FDCeject(int num){ + int i; + +#ifdef MEMDISC + for (i=0;i<1050*1024;i++) disc[num][i]=0; +#endif + disk[num].file = NULL; + sprintf(disk[num].name,"disk%01d",num); + disk[num].sides = SIDES; + disk[num].tracks = TRACKS; + disk[num].sectors = SECTORS; + disk[num].secsize = 512; + disk_ejected[num]=1; + fdc_status |= 0x40; +} + +void FDCCommand(void) +{ + static char motor = 1; + int sides, drives; + long address; /* dma target/source address */ + long offset; /* offset in disk file */ + unsigned long count; /* number of byte to transfer */ + char *buffer; + int n; + + if (fdc_commands_executed<64) + fdc_commands_executed++; + /* DMA target/source address */ + address = (dma_adrh << 16) + (dma_adrm << 8) + dma_adrl; + /* if (address>MEMSIZE){ + #ifdef DISASS + StartDisass(); + exit(1); + #endif + fdc_status |= 0x10; + return; + + + + } + */ + buffer = (char *)(membase + address); + /* status of side select and drive select lines */ + sides = (~psg[14]) & 0x1; + drives = (~psg[14]) & 0x6; + if (disk_ejected[drives>>2]==1) drives=2; + switch (drives) { + case 2: /* Drive A */ + drives = 0; + break; + case 4: /* Drive B */ + drives = 1; + break; + case 6: /* both, error */ + case 0: /* no drive selected */ + drives = -1; + break; + } + fdc_status = 0; /* clear fdc status */ + +#if DISK + + if (fdc_command < 0x80) { /* TYPE-I fdc commands */ + if (drives >= 0) { /* drive selected */ + switch (fdc_command & 0xf0) { + case 0x00: /* RESTORE */ + disk[drives].head = 0; + fdc_track = 0; + break; + case 0x10: /* SEEK */ + disk[drives].head += (fdc_data - fdc_track); + fdc_track = fdc_data; + if (disk[drives].head < 0 + || disk[drives].head >= disk[drives].tracks) + disk[drives].head = 0; + break; + case 0x30: /* STEP */ + fdc_track += fdcdir; + case 0x20: + disk[drives].head += fdcdir; + break; + case 0x50: /* STEP-IN */ + fdc_track++; + case 0x40: + if (disk[drives].head < disk[drives].tracks) + disk[drives].head++; + fdcdir = 1; + break; + case 0x70: /* STEP-OUT */ + fdc_track--; + case 0x60: + if (disk[drives].head > 0) + disk[drives].head--; + fdcdir = -1; + break; + } + if (disk[drives].head == 0) { + fdc_status |= 0x4; + } + if (disk[drives].head != fdc_track && fdc_command & 0x4) { /* Verify? */ + fdc_status |= 0x10; + } + if (motor) { + fdc_status |= 0x20; /* spin-up flag */ + } + } else { /* no drive selected */ + fdc_status |= 0x10; + } + } else if ((fdc_command & 0xf0) == 0xd0) { /* FORCE INTERRUPT */ + if (fdc_command == 0xd8) { + fdc_int = 1; + } else if (fdc_command == 0xd0) { + fdc_int = 0; + } + } else { /* OTHERS */ + if (drives >= 0) { /* drive selected */ + /* offset within floppy-file */ + offset = disk[drives].secsize * + (((disk[drives].sectors * disk[drives].sides * disk[drives].head)) + + (disk[drives].sectors * sides) + (fdc_sector - 1)); + switch (fdc_command & 0xf0) { + case 0x80: /* READ SECTOR */ + count = 512; + if (!discseek (drives, offset, 0)) { + if (address> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + break; + } + }else{ + address += count; + dma_adrl = address & 0xff; + dma_adrm = (address >> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + mfp_gpip |= 0x20; + fdc_status |= 0x1; + break; + } + } + fdc_status |= 0x10; + dma_sr = 1; + break; + case 0x90: /* READ SECTOR multiple */ + count = dma_scr * 512; + if (count+(fdc_sector-1)*512>disk[drives].sectors*512) count=disk[drives].sectors*512-(fdc_sector-1)*512; + if (!discseek (drives, offset, 0)) { + if (address> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + fdc_sector += count/disk[drives].secsize; + break; + } + }else{ + address += count; + dma_adrl = address & 0xff; + dma_adrm = (address >> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + mfp_gpip |= 0x20; + fdc_status |= 0x1; + break; + } + } + fdc_status |= 0x10; + dma_sr = 1; + break; + case 0xa0: /* WRITE SECTOR */ + count = dma_scr * 512; + if (!discseek (drives, offset, 0)) { + if (count == discwrite ((unsigned char *)buffer, 1, count, drives)) { + address += count; + dma_adrl = address & 0xff; + dma_adrm = (address >> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + break; + } + } + fdc_status |= 0x10; + dma_sr = 1; + break; + case 0xb0: /* WRITE SECTOR multiple */ + count = dma_scr * 512; + if (!discseek (drives, offset, 0)) { + if (count == discwrite ((unsigned char *)buffer, 1, count, drives)) { + address += count; + dma_adrl = address & 0xff; + dma_adrm = (address >> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + fdc_sector += dma_scr * (512 / disk[drives].secsize); + break; + } + } + fdc_status |= 0x10; + dma_sr = 1; + break; + case 0xc0: /* READ ADDRESS */ + fdc_status |= 0x10; + break; + case 0xe0: /* READ TRACK */ + count = disk[drives].sectors * 512; + offset = disk[drives].secsize * + (((disk[drives].sectors * disk[drives].sides * disk[drives].head)) + + (disk[drives].sectors * sides)); + if (!discseek (drives, offset, 0)) { + if (address> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + break; + } + }else{ + address += 302; + dma_adrl = address & 0xff; + dma_adrm = (address >> 8) & 0xff; + dma_adrh = (address >> 16) & 0xff; + dma_scr = 0; + dma_sr = 1; + mfp_gpip |= 0x20; + fdc_status |= 0x1; + break; + } + } + fdc_status |= 0x10; + dma_sr = 1; + break; + case 0xf0: /* WRITE TRACK */ + fdc_status |= 0x10; + break; + } + if (disk[drives].head != fdc_track) { + fdc_status |= 0x10; + } + } else { + fdc_status |= 0x10; /* no drive selected */ + } + } +#endif + if (motor) { + fdc_status |= 0x80; /* motor on flag */ + fdc_motor=1; + } + if (!(fdc_status & 0x01)) { /* not busy */ + mfp_iprb |= (0x80 & mfp_ierb); /* Request Interrupt */ + mfp_gpip &= ~0x20; + } +} diff --git a/MCUME_esp32/espcastaway/main/font8x8.h b/MCUME_esp32/espcastaway/main/font8x8.h new file mode 100644 index 0000000..bab272e --- /dev/null +++ b/MCUME_esp32/espcastaway/main/font8x8.h @@ -0,0 +1,136 @@ + +// Font: c64_lower.64c + +const unsigned char font8x8[128][8] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0000 (nul) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0001 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0002 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0003 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0004 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0005 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0006 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0007 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0008 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0009 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000A + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000B + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000C + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000E + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000F + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0010 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0011 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0012 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0013 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0014 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0015 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0016 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0017 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0018 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0019 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001A + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001B + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001C + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001E + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001F + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0020 (space) + { 0x18, 0x3C, 0x3C, 0x18, 0x18, 0x00, 0x18, 0x00}, // U+0021 (!) + { 0x36, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0022 (") + { 0x36, 0x36, 0x7F, 0x36, 0x7F, 0x36, 0x36, 0x00}, // U+0023 (#) + { 0x0C, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x0C, 0x00}, // U+0024 ($) + { 0x00, 0x63, 0x33, 0x18, 0x0C, 0x66, 0x63, 0x00}, // U+0025 (%) + { 0x1C, 0x36, 0x1C, 0x6E, 0x3B, 0x33, 0x6E, 0x00}, // U+0026 (&) + { 0x06, 0x06, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0027 (') + { 0x18, 0x0C, 0x06, 0x06, 0x06, 0x0C, 0x18, 0x00}, // U+0028 (() + { 0x06, 0x0C, 0x18, 0x18, 0x18, 0x0C, 0x06, 0x00}, // U+0029 ()) + { 0x00, 0x66, 0x3C, 0xFF, 0x3C, 0x66, 0x00, 0x00}, // U+002A (*) + { 0x00, 0x0C, 0x0C, 0x3F, 0x0C, 0x0C, 0x00, 0x00}, // U+002B (+) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x06}, // U+002C (,) + { 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00}, // U+002D (-) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00}, // U+002E (.) + { 0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x01, 0x00}, // U+002F (/) + { 0x3E, 0x63, 0x73, 0x7B, 0x6F, 0x67, 0x3E, 0x00}, // U+0030 (0) + { 0x0C, 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x3F, 0x00}, // U+0031 (1) + { 0x1E, 0x33, 0x30, 0x1C, 0x06, 0x33, 0x3F, 0x00}, // U+0032 (2) + { 0x1E, 0x33, 0x30, 0x1C, 0x30, 0x33, 0x1E, 0x00}, // U+0033 (3) + { 0x38, 0x3C, 0x36, 0x33, 0x7F, 0x30, 0x78, 0x00}, // U+0034 (4) + { 0x3F, 0x03, 0x1F, 0x30, 0x30, 0x33, 0x1E, 0x00}, // U+0035 (5) + { 0x1C, 0x06, 0x03, 0x1F, 0x33, 0x33, 0x1E, 0x00}, // U+0036 (6) + { 0x3F, 0x33, 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x00}, // U+0037 (7) + { 0x1E, 0x33, 0x33, 0x1E, 0x33, 0x33, 0x1E, 0x00}, // U+0038 (8) + { 0x1E, 0x33, 0x33, 0x3E, 0x30, 0x18, 0x0E, 0x00}, // U+0039 (9) + { 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x00}, // U+003A (:) + { 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x06}, // U+003B (//) + { 0x18, 0x0C, 0x06, 0x03, 0x06, 0x0C, 0x18, 0x00}, // U+003C (<) + { 0x00, 0x00, 0x3F, 0x00, 0x00, 0x3F, 0x00, 0x00}, // U+003D (=) + { 0x06, 0x0C, 0x18, 0x30, 0x18, 0x0C, 0x06, 0x00}, // U+003E (>) + { 0x1E, 0x33, 0x30, 0x18, 0x0C, 0x00, 0x0C, 0x00}, // U+003F (?) + { 0x3E, 0x63, 0x7B, 0x7B, 0x7B, 0x03, 0x1E, 0x00}, // U+0040 (@) + { 0x0C, 0x1E, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x00}, // U+0041 (A) + { 0x3F, 0x66, 0x66, 0x3E, 0x66, 0x66, 0x3F, 0x00}, // U+0042 (B) + { 0x3C, 0x66, 0x03, 0x03, 0x03, 0x66, 0x3C, 0x00}, // U+0043 (C) + { 0x1F, 0x36, 0x66, 0x66, 0x66, 0x36, 0x1F, 0x00}, // U+0044 (D) + { 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x46, 0x7F, 0x00}, // U+0045 (E) + { 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x06, 0x0F, 0x00}, // U+0046 (F) + { 0x3C, 0x66, 0x03, 0x03, 0x73, 0x66, 0x7C, 0x00}, // U+0047 (G) + { 0x33, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x33, 0x00}, // U+0048 (H) + { 0x1E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0049 (I) + { 0x78, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E, 0x00}, // U+004A (J) + { 0x67, 0x66, 0x36, 0x1E, 0x36, 0x66, 0x67, 0x00}, // U+004B (K) + { 0x0F, 0x06, 0x06, 0x06, 0x46, 0x66, 0x7F, 0x00}, // U+004C (L) + { 0x63, 0x77, 0x7F, 0x7F, 0x6B, 0x63, 0x63, 0x00}, // U+004D (M) + { 0x63, 0x67, 0x6F, 0x7B, 0x73, 0x63, 0x63, 0x00}, // U+004E (N) + { 0x1C, 0x36, 0x63, 0x63, 0x63, 0x36, 0x1C, 0x00}, // U+004F (O) + { 0x3F, 0x66, 0x66, 0x3E, 0x06, 0x06, 0x0F, 0x00}, // U+0050 (P) + { 0x1E, 0x33, 0x33, 0x33, 0x3B, 0x1E, 0x38, 0x00}, // U+0051 (Q) + { 0x3F, 0x66, 0x66, 0x3E, 0x36, 0x66, 0x67, 0x00}, // U+0052 (R) + { 0x1E, 0x33, 0x07, 0x0E, 0x38, 0x33, 0x1E, 0x00}, // U+0053 (S) + { 0x3F, 0x2D, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0054 (T) + { 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x3F, 0x00}, // U+0055 (U) + { 0x33, 0x33, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00}, // U+0056 (V) + { 0x63, 0x63, 0x63, 0x6B, 0x7F, 0x77, 0x63, 0x00}, // U+0057 (W) + { 0x63, 0x63, 0x36, 0x1C, 0x1C, 0x36, 0x63, 0x00}, // U+0058 (X) + { 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x0C, 0x1E, 0x00}, // U+0059 (Y) + { 0x7F, 0x63, 0x31, 0x18, 0x4C, 0x66, 0x7F, 0x00}, // U+005A (Z) + { 0x1E, 0x06, 0x06, 0x06, 0x06, 0x06, 0x1E, 0x00}, // U+005B ([) + { 0x03, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x40, 0x00}, // U+005C (\) + { 0x1E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1E, 0x00}, // U+005D (]) + { 0x08, 0x1C, 0x36, 0x63, 0x00, 0x00, 0x00, 0x00}, // U+005E (^) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF}, // U+005F (_) + { 0x0C, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0060 (`) + { 0x00, 0x00, 0x1E, 0x30, 0x3E, 0x33, 0x6E, 0x00}, // U+0061 (a) + { 0x07, 0x06, 0x06, 0x3E, 0x66, 0x66, 0x3B, 0x00}, // U+0062 (b) + { 0x00, 0x00, 0x1E, 0x33, 0x03, 0x33, 0x1E, 0x00}, // U+0063 (c) + { 0x38, 0x30, 0x30, 0x3e, 0x33, 0x33, 0x6E, 0x00}, // U+0064 (d) + { 0x00, 0x00, 0x1E, 0x33, 0x3f, 0x03, 0x1E, 0x00}, // U+0065 (e) + { 0x1C, 0x36, 0x06, 0x0f, 0x06, 0x06, 0x0F, 0x00}, // U+0066 (f) + { 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x1F}, // U+0067 (g) + { 0x07, 0x06, 0x36, 0x6E, 0x66, 0x66, 0x67, 0x00}, // U+0068 (h) + { 0x0C, 0x00, 0x0E, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0069 (i) + { 0x30, 0x00, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E}, // U+006A (j) + { 0x07, 0x06, 0x66, 0x36, 0x1E, 0x36, 0x67, 0x00}, // U+006B (k) + { 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+006C (l) + { 0x00, 0x00, 0x33, 0x7F, 0x7F, 0x6B, 0x63, 0x00}, // U+006D (m) + { 0x00, 0x00, 0x1F, 0x33, 0x33, 0x33, 0x33, 0x00}, // U+006E (n) + { 0x00, 0x00, 0x1E, 0x33, 0x33, 0x33, 0x1E, 0x00}, // U+006F (o) + { 0x00, 0x00, 0x3B, 0x66, 0x66, 0x3E, 0x06, 0x0F}, // U+0070 (p) + { 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x78}, // U+0071 (q) + { 0x00, 0x00, 0x3B, 0x6E, 0x66, 0x06, 0x0F, 0x00}, // U+0072 (r) + { 0x00, 0x00, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x00}, // U+0073 (s) + { 0x08, 0x0C, 0x3E, 0x0C, 0x0C, 0x2C, 0x18, 0x00}, // U+0074 (t) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x33, 0x6E, 0x00}, // U+0075 (u) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00}, // U+0076 (v) + { 0x00, 0x00, 0x63, 0x6B, 0x7F, 0x7F, 0x36, 0x00}, // U+0077 (w) + { 0x00, 0x00, 0x63, 0x36, 0x1C, 0x36, 0x63, 0x00}, // U+0078 (x) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x3E, 0x30, 0x1F}, // U+0079 (y) + { 0x00, 0x00, 0x3F, 0x19, 0x0C, 0x26, 0x3F, 0x00}, // U+007A (z) + { 0x38, 0x0C, 0x0C, 0x07, 0x0C, 0x0C, 0x38, 0x00}, // U+007B ({) + { 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x00}, // U+007C (|) + { 0x07, 0x0C, 0x0C, 0x38, 0x0C, 0x0C, 0x07, 0x00}, // U+007D (}) + { 0x6E, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+007E (~) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} // U+007F +}; + + diff --git a/MCUME_esp32/espcastaway/main/go.cpp b/MCUME_esp32/espcastaway/main/go.cpp new file mode 100644 index 0000000..f12a314 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/go.cpp @@ -0,0 +1,113 @@ +#include "go.h" + +extern "C" { + #include "emuapi.h" + #include "iopins.h" +} + +#include "esp_event.h" + +#include "keyboard_osd.h" +#include "ili9341_t3dma.h" +#ifdef HAS_SND +#include "AudioPlaySystem.h" +#endif + +#include "emu.h" + + +ILI9341_t3DMA tft = ILI9341_t3DMA(PIN_NUM_CS, PIN_NUM_DC, -1, PIN_NUM_MOSI, PIN_NUM_CLK, PIN_NUM_MISO, TPIN_NUM_CS, TPIN_NUM_IRQ); +#ifdef HAS_SND +AudioPlaySystem audio; +#endif + + +static void spi_task(void *args) +{ + while(true) { + tft.refresh(); + } +} + +static void input_task(void *args) +{ + while(true) { + + /* + if ((emu_ReadKeys() & (MASK_KEY_USER1+MASK_KEY_USER2)) == (MASK_KEY_USER1+MASK_KEY_USER2)) { + printf("rebooting\n"); + esp_restart(); + } + */ + + uint16_t bClick = emu_DebounceLocalKeys(); + /* + if (bClick & MASK_KEY_USER2) { + printf("%d\n",emu_SwapJoysticks(1)); + emu_SwapJoysticks(0); + } + else + */ + { + emu_Input(bClick); + } +#ifdef HAS_SND + audio.step(); +#endif + vTaskDelay(20 / portTICK_PERIOD_MS); + } +} + +static void main_step() { + if (menuActive()) { + uint16_t bClick = emu_DebounceLocalKeys(); + int action = handleMenu(bClick); + char * filename = menuSelection(); + if (action == ACTION_RUNTFT) { +#ifdef HAS_SND + audio.begin(); + audio.start(); +#endif + toggleMenu(false); + tft.fillScreenNoDma( RGBVAL16(0x00,0x00,0x00) ); + xTaskCreatePinnedToCore(input_task, "inputthread", 4096, NULL, 2, NULL, 0); + emu_Init(filename); + } + //vTaskDelay(20 / portTICK_PERIOD_MS); + } + else { + emu_Step(); + } +} + + +void setup(void) +{ + printf("Starting emulator\n"); + + tft.begin(); + //tft.flipscreen(true); + tft.start(); + tft.refresh(); + + emu_init(); + + xTaskCreatePinnedToCore(spi_task, "spithread", 4096, NULL, 1, NULL, 0); + //vTaskPrioritySet(NULL, tskIDLE_PRIORITY+1); + //toggleMenu(false); + //xTaskCreatePinnedToCore(input_task, "inputthread", 4096, NULL, 2, NULL, 0); + + //emu_Init("filename"); + +} + +void loop(void) +{ + unsigned long t = esp_timer_get_time(); + main_step(); + //printf("%d\n",(int)((esp_timer_get_time()-t)/1000)); +} + + + + diff --git a/MCUME_esp32/espcastaway/main/go.h b/MCUME_esp32/espcastaway/main/go.h new file mode 100644 index 0000000..12c65e0 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/go.h @@ -0,0 +1,8 @@ +#ifdef __cplusplus +extern "C" { +#endif +void setup(void); +void loop(void); +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/MCUME_esp32/espcastaway/main/ikbd.cpp b/MCUME_esp32/espcastaway/main/ikbd.cpp new file mode 100644 index 0000000..52abbe8 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/ikbd.cpp @@ -0,0 +1,814 @@ +/* + * Castaway + * (C) 1994 - 2002 Martin Doering, Joachim Hoenig + * + * ikbd.c - ST keyboard processor emulator (german keymap) + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + * + * revision history + * 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring + * 09.06.2002 JH Renamed io.c to st.c again (io.h conflicts with system headers) + * 16.06.2002 JH New function: IkbdQueryBuffer(). X11 keysym conversion removed. + * 29.10.2002 JH Added joystick interrogation mode and Joystick functions. + */ +static char sccsid[] = "$Id: ikbd.c,v 1.5 2003/03/07 20:24:15 mdoering Exp $"; +#include +#ifndef DREAMCAST +#include +#else +#include +#endif +#include "config.h" +#include "st.h" +#include "mem.h" +#include "m68k_intrf.h" + +#define max(A,B) ((A>B)?A:B) + + +void IkbdMouse(void); + +struct _mouse mouse; +struct _joystick joystick; +unsigned char inbuff[IBS]; +unsigned char outbuff[OBS]; +int inbuffi = 0; +int outbuffi = 0; + +static unsigned char prevbut=0x2|0x8; + +int ikbd_pulling=0; +int ikbd_direct=0; +static unsigned ikbd_writed=6; +static int ikbd_pause = 0; +static int mouse_xabs=0; +static int mouse_yabs=0; +static int mouse_dx=0; +static int mouse_dy=0; + +void IkbdRecv(unsigned char inchar) +{ +#ifdef DEBUG_IKBD + printf ("IkbdRecv: 0x%X (inbuffi=%i)\n", inchar, inbuffi); fflush(stdout); +#endif + ikbd_pulling=0; + if (inbuffi == IBS) { +#ifdef DEBUG_IKBD + printf ("IkbdRecv: Input buffer overrun!\n"); fflush(stdout); +#endif + inbuffi = 0; + } + inbuff[inbuffi++] = inchar; + switch (inbuff[0]) { + case 0x07: /* set mouse button action */ + if (inbuffi == 2) { + inbuffi = 0; + mouse.button_action = inbuff[1]; + } + break; + case 0x08: /* set relative mouse position reporting */ + inbuffi = 0; + mouse.mode = 1; + break; + case 0x09: /* set absolute mouse positioning */ + if (inbuffi == 5) { + mouse.mode = 2; + mouse.xmax = (inbuff[1] << 8) | inbuff[2]; + mouse.ymax = (inbuff[3] << 8) | inbuff[4]; + inbuffi = 0; + } + break; + case 0x0a: /* set mouse keycode mode */ + if (inbuffi == 3) { + mouse.mode = 3; + mouse.xkcm = inbuff[1]; + mouse.ykcm = inbuff[2]; + inbuffi = 0; + } + break; + case 0x0b: /* set mouse threshold */ + if (inbuffi == 3) { + mouse.xth = inbuff[1]; + mouse.yth = inbuff[2]; + inbuffi = 0; + } + break; + case 0x0c: /* set mouse scale */ + if (inbuffi == 3) { + mouse.xscale = inbuff[1]; + mouse.yscale = inbuff[2]; + inbuffi = 0; + } + break; + case 0x0d: /* interrogate mouse position */ + inbuffi=0; + if ((outbuffi+6) > (OBS - 1)) + break; + + if (mouse_xabs>mouse.xmax) mouse_xabs=mouse.xmax; + else if (mouse_xabs<0) mouse_xabs=0; + if (mouse_yabs>mouse.ymax) mouse_yabs=mouse.ymax; + else if (mouse_yabs<0) mouse_yabs=0; + + if (ikbd_writed>=6) + { + ikbd_writed=0; + unsigned char but=0,tmprev; + if(mouse.buttons&1) + but|=1; + else + but|=2; + if (mouse.buttons&2) + but|=4; + else + but|=8; + + tmprev=prevbut; + prevbut = but; + but &= ~tmprev; + + IkbdSend (0xf7); + IkbdSend (but); + IkbdSend ((mouse_xabs >> 8)&0xff); + IkbdSend (mouse_xabs&0xff); + IkbdSend ((mouse_yabs >> 8)&0xff); + IkbdSend ((mouse_yabs)&0xff); + mouse.flag = 1; + } + break; + case 0x0e: /* load mouse position */ + if (inbuffi == 6) { + inbuffi = 0; + mouse.x = (inbuff[2] << 8) | inbuff[3]; + mouse.y = (inbuff[4] << 8) | inbuff[5]; + } + break; + case 0x0f: /* set Y=0 at bottom */ + inbuffi = 0; + mouse.yinv = 1; + break; + case 0x10: /* set Y=0 at top */ + inbuffi = 0; + mouse.yinv = 0; + break; + case 0x11: /* resume */ + inbuffi = 0; +/* + ikbd_pause = 0; +*/ + break; +#if 0 + case 0x00: /* ??? */ + inbuffi = 0; + ikbd_direct = 0; + break; +#endif + case 0x12: /* disable mouse */ + inbuffi = 0; +#if 0 + if (!ikbd_direct) + mouse.mode = 0; + else + mouse.mode = 2; +#else + mouse.mode = 0; + ikbd_direct = 1; +#endif + break; + case 0x13: /* ikbd_pause output */ + inbuffi = 0; +/* + ikbd_pause = 1; +*/ + break; + case 0x14: /* set joystick event reporting */ + inbuffi = 0; + ikbd_direct = 1; + joystick.mode = inbuff[0]; + break; + case 0x15: /* set joystick interrogation mode */ + inbuffi = 0; + ikbd_direct = 0; + joystick.mode = inbuff[0]; + break; + case 0x16: /* joystick interrogation */ + inbuffi = 0; + IkbdSend(0xfd); + IkbdSend(joystick.state1); + IkbdSend(joystick.state0); + ikbd_pulling=1; + break; + case 0x17: /* set joystick monitoring */ + if (inbuffi == 2) { + inbuffi = 0; + joystick.rate = inbuff[1]; + joystick.mode = inbuff[0]; + } + break; + case 0x18: /* set fire button monitoring */ + inbuffi = 0; + joystick.mode = inbuff[0]; + break; + case 0x19: /* set joystick keycode mode */ + if (inbuffi == 7) { + inbuffi = 0; + joystick.mode = inbuff[0]; + } + break; + case 0x1a: /* disable joysticks */ + if (!mouse.mode) + mouse.mode=2; + inbuffi = 0; + joystick.mode = inbuff[0]; + ikbd_direct = 1; + break; + case 0x1b: /* time-of-day clock set */ + if (inbuffi == 7) { + inbuffi = 0; + } + break; + case 0x1c: /* interrogate time-of-day clock */ + inbuffi = 0; + IkbdSend (0xfc); + IkbdSend (0x0); + IkbdSend (0x0); + IkbdSend (0x0); + IkbdSend (0x0); + IkbdSend (0x0); + IkbdSend (0x0); + break; + case 0x20: /* memory load */ + if (inbuffi == 4) { + inbuffi = 0; + } + break; + case 0x21: /* memory read */ + if (inbuffi == 3) { + inbuffi = 0; + } + break; + case 0x22: /* controller execute */ + if (inbuffi == 3) { + inbuffi = 0; + } + break; + case 0x80: /* reset */ + if (inbuffi == 2) + { + IkbdSend (0xf0); + inbuffi = 0; + ikbd_direct = 0; + mouse.buttons = 0; + mouse.stbuttons = 0; + switch (vid_shiftmode) { + case 0: + mouse.stx = 160; + mouse.sty = 100; + break; + case 1: + mouse.stx = 320; + mouse.sty = 100; + break; + case 2: + mouse.stx = 320; + mouse.sty = 200; + break; + } + } + break; + case 0x87: /* request button action */ + inbuffi = 0; + IkbdSend (0x07); + IkbdSend (mouse.button_action); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + break; + case 0x88: /* request mouse mode */ + case 0x89: + case 0x8a: + switch (mouse.mode) { + case 1: + IkbdSend (0x08); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + break; + case 2: + IkbdSend (0x09); + IkbdSend (mouse.xmax >> 8); + IkbdSend (mouse.xmax); + IkbdSend (mouse.ymax >> 8); + IkbdSend (mouse.ymax); + IkbdSend (0); + IkbdSend (0); + break; + case 3: + IkbdSend (0x09); + IkbdSend (mouse.xkcm); + IkbdSend (mouse.ykcm); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + break; + } + inbuffi = 0; + mouse.mode = 1; + break; + case 0x8b: /* request mouse threshold */ + IkbdSend (0x0b); + IkbdSend (mouse.xth); + IkbdSend (mouse.yth); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + inbuffi = 0; + break; + case 0x8c: /* request mouse scale */ + IkbdSend (0x0b); + IkbdSend (mouse.xscale); + IkbdSend (mouse.yscale); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + inbuffi = 0; + break; + case 0x8f: /* request mouse vertical coordinates */ + case 0x90: + if (mouse.yinv) + IkbdSend (0x0f); + else + IkbdSend (0x10); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + inbuffi = 0; + break; + case 0x92: /* disable mouse */ + if (mouse.mode) + IkbdSend (0); + else + IkbdSend (0x12); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + inbuffi = 0; + break; + case 0x94: /* request joystick mode */ + case 0x95: + case 0x99: /* set joystick keycode mode */ + switch (joystick.mode) { + case 0x14: + case 0x15: + IkbdSend (joystick.mode); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + break; + case 0x19: + IkbdSend (0x19); + IkbdSend (joystick.rx); + IkbdSend (joystick.ry); + IkbdSend (joystick.tx); + IkbdSend (joystick.ty); + IkbdSend (joystick.vx); + IkbdSend (joystick.vy); + break; + } + inbuffi = 0; + break; + case 0x9a: /* request joystick availability */ + if (joystick.mode != 0x1a) + IkbdSend (0); + else + IkbdSend (0x1a); + IkbdSend (joystick.rx); + IkbdSend (joystick.ry); + IkbdSend (joystick.tx); + IkbdSend (joystick.ty); + IkbdSend (joystick.vx); + IkbdSend (joystick.vy); + inbuffi = 0; + break; + default: + inbuffi = 0; + } +} + +void IkbdSend (unsigned char outchar) +{ +#ifdef DEBUG_IKBD + printf("IkbdSend(0x%X)\n",outchar); fflush(stdout); +#endif + if (outbuffi < (OBS - 1)) + outbuff[outbuffi++] = outchar; +} + + + +/* + * This function tests if there is still + * Ikbd Output waiting to be written + */ +int IkbdQueryBuffer(void) +{ + return ((mouse.flag || outbuffi > 0) && !ikbd_pause); +} + +void IkbdWriteBuffer(void) +{ + if (mouse.flag && (outbuffi < (OBS / 2))) { + IkbdMouse (); + } + + if (outbuffi > 0 && !ikbd_pause && (acia1_sr & 0x1) == 0) { + ikbd_writed++; + acia1_sr |= 1; + if (acia1_cr & 0x80) { /* receiver interrupt enabled? */ + acia1_sr |= 0x80; + mfp_gpip &= (~0x10); + } + acia1_dr = outbuff[0]; + memcpy (&outbuff[0], &outbuff[1], (OBS - 1)); + outbuffi--; + } + +} + +void IkbdKeyPress (unsigned short keysym) +{ +#ifdef DEBUG_IKBD + printf("IkbdKeyPress(%X)\n",keysym); fflush(stdout); +#endif + IkbdSend (keysym); +} + +void IkbdKeyRelease (unsigned short keysym) +{ +#ifdef DEBUG_IKBD + printf("IkbdKeyRelease(%X)\n",keysym); fflush(stdout); +#endif + IkbdSend (0x80 | keysym); +} + +void IkbdMouse(void) +{ + int dx,dy; + mouse.flag = 0; + switch (mouse.mode) { + + case 1: + dx = mouse.x - mouse.stx; + dy = mouse.y - mouse.sty; + if (dx > 127) { + dx = 127; + mouse.flag = 1; + } + if (dx < -127) { + dx = -127; + mouse.flag = 1; + } + if (dy > 127) { + dy = 127; + mouse.flag = 1; + } + if (dy < -127) { + dy = -127; + mouse.flag = 1; + } + if (mouse.stbuttons != mouse.buttons + || max (dx, -dx) > mouse.xth || max (dy, -dy) > mouse.yth) { + mouse.stbuttons = mouse.buttons; + mouse.stx = mouse.stx + dx; + mouse.sty = mouse.sty + dy; + if (mouse.stx <= 0) { + mouse.stx = 0; + dx = -127; + } + if (mouse.sty <= 0) { + mouse.sty = 0; + dy = -127; + } + switch (vid_shiftmode) { + case 0: + if (mouse.stx >= 319) { + mouse.stx = 319; + dx = 127; + } + if (mouse.sty >= 199) { + mouse.sty = 199; + dy = 127; + } + break; + case 1: + if (mouse.stx >= 639) { + mouse.stx = 639; + dx = 127; + } + if (mouse.sty >= 199) { + mouse.sty = 199; + dy = 127; + } + break; + case 2: + if (mouse.stx >= 639) { + mouse.stx = 639; + dx = 127; + } + if (mouse.sty >= 399) { + mouse.sty = 399; + dy = 127; + } + break; + } + IkbdSend (0xf8 | mouse.buttons); + IkbdSend (dx); + IkbdSend (dy); + } +#ifdef DEBUG_IKBD + printf ("Mouse1: x %d, y %d, dx %d, dy %d, but %d\n", mouse.stx, mouse.sty, dx, dy, mouse.buttons); fflush(stdout); +#endif + break; + + case 2: +//if (mouse.x>mouse.xmax) mouse.x=mouse.xmax; +//if (mouse.y>mouse.ymax) mouse.y=mouse.ymax; +#ifdef DEBUG_IKBD + puts("MOUSE MODE NOT SUPPORTED YET"); fflush(stdout); +#endif +// break; + +//case 0: + case 3: + if ((mouse.stbuttons&0x3) != (mouse.buttons&0x3)) + { + if ((mouse.stbuttons&0x1) != (mouse.buttons&0x1)) + { + if (mouse.stbuttons&0x1) + { + IkbdSend(0xF5); + IkbdSend(0xF5); + } + else + { + IkbdSend(0x75); + IkbdSend(0x75); + } + } + else + if ((mouse.stbuttons&0x2) != (mouse.buttons&02)) + { + if (mouse.stbuttons&0x2) + { + IkbdSend(0xF4); + IkbdSend(0xF4); + } + else + { + IkbdSend(0x74); + IkbdSend(0x74); + } + } + mouse.stbuttons = mouse.buttons; + } + { + int i; + dx = mouse_dx; + dy = mouse_dy; + for(i=0;i<10;i++) + { + if (dx<0) + { + IkbdSend(75); + IkbdSend(75|0x80); + dx++; + } + else if (dx>0) + { + IkbdSend(77); + IkbdSend(77|0x80); + dx--; + } + if (dy<0) + { + IkbdSend(72); + IkbdSend(72|0x80); + dy++; + } + else if (dy>0) + { + IkbdSend(80); + IkbdSend(80|0x80); + dy--; + } + } + } + mouse_dx = mouse_dy = 0; +#ifdef DEBUG_IKBD + printf ("Mouse0: x %d, y %d, dx %d, dy %d, but %d\n", mouse.stx, mouse.sty, dx, dy, mouse.buttons); fflush(stdout); +#endif + break; +#ifdef DEBUG_IKBD + default: + puts("MOUSE MODE ERROR"); fflush(stdout); +#endif + } +} + +void IkbdMouseMotion (int x, int y, int dx, int dy) +{ + static int xant=0, yant=0; + + mouse_xabs=x; + mouse_yabs=y; + mouse_dx=dx; + mouse_dy=dy; + switch (vid_shiftmode) { + case 1: + mouse.x += (x-xant); + if (mouse.x < 0) + mouse.x = 0; + else + if (mouse.x > 640) + mouse.x = 639; + mouse.y += (y-yant); + if (mouse.y < 0) + mouse.y = 0; + else + if (mouse.y>200) + mouse.y=199; + break; + case 0: + mouse.x += (x-xant); + if (mouse.x < 0) + mouse.x = 0; + else + if (mouse.x > 320) + mouse.x = 319; + mouse.y += (y-yant); + if (mouse.y < 0) + mouse.y = 0; + else + if (mouse.y>200) + mouse.y=199; + break; + case 2: + mouse.x += (x-xant); + if (mouse.x < 0) + mouse.x = 0; + else + if (mouse.x > 640) + mouse.x = 639; + mouse.y += (y-yant); + if (mouse.y < 0) + mouse.y = 0; + else + if (mouse.y>400) + mouse.y=399; + break; + } + mouse.flag = 1; + xant=x; + yant=y; +} + +void IkbdMousePress (int code) +{ +#ifdef DEBUG_IKBD + printf("IkbdMousePress(%X)\n",code); fflush(stdout); +#endif + mouse.buttons |= code; + IkbdMouse(); +} + +void IkbdMouseRelease (int code) +{ +#ifdef DEBUG_IKBD + printf("IkbdMouseRelease(%X)\n",code); fflush(stdout); +#endif + mouse.buttons &= ~code; + IkbdMouse(); +} + +void IkbdJoystickChange(int number, uint8 state) +{ + static uint8 joyold0=0; + static uint8 joyold1=0; +#ifdef DEBUG_IKBD + printf("IkbdJoystickChange(%i,0x%X)\n",number,state); fflush(stdout); +#endif + if (number == 0 && joystick.state0 != state) { + joystick.state0 = state; + /* TODO: only if joystick event reporting selected */ + if (!ikbd_pulling) + { + if (!ikbd_direct) + { + if ((state&0x80)!=joyold0) + { + IkbdSend(0xf8|(state>>7)); + IkbdSend(state&0x7f); + IkbdSend(0); + joyold0=state&0x80; + } + else + { + IkbdSend(0xff); + IkbdSend(state&0x7f); + } + } + else + { + IkbdSend(0xff); + IkbdSend(state); + } + } + } + if (number == 1 && joystick.state1 != state) { + joystick.state1 = state; + /* TODO: only if joystick event reporting selected */ + if (!ikbd_pulling) + { + if (!ikbd_direct) + { + if ((state&0x80)!=joyold1) + { + IkbdSend(0xfa|(state>>7)); + IkbdSend(state&0x7f); + IkbdSend(0); + joyold1=state&0x80; + } + else + { + IkbdSend(0xfe); + IkbdSend(state&0x7f); + } + } + else + { + IkbdSend(0xfe); + IkbdSend(state); + } + } + } +} + + +void Ikbd_Reset(void) +{ + //SDL_Event event; + //SDL_Delay(333); + //while(SDL_PollEvent(&event)) + // SDL_Delay(20); + IkbdSend(0x80); + IkbdSend(0xff); + IkbdSend(0x80); + acia1_cr=150; + acia1_sr=0; + acia1_dr=240; + acia2_cr=149; + acia2_sr=0; + acia2_dr=0; + inbuffi = 0; + outbuffi = 0; + ikbd_pause = 0; + ikbd_pulling=0; + ikbd_direct=0; + mouse.mode = 1; + prevbut=0x2|0x8; + ikbd_writed=6; +} + +void IkbdReset(void) +{ + Ikbd_Reset(); +} + +void IkbdLoop(void) +{ +} + +void IkbdMouseMotion(int x, int y) +{ + IkbdMouseMotion(x,y,1,1); +} + diff --git a/MCUME_esp32/espcastaway/main/ikbd.cpp__ b/MCUME_esp32/espcastaway/main/ikbd.cpp__ new file mode 100644 index 0000000..cfa6b5b --- /dev/null +++ b/MCUME_esp32/espcastaway/main/ikbd.cpp__ @@ -0,0 +1,519 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* ikbd.c - ST keyboard processor emulator (german keymap) +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 0.02.00 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 09.06.2002 0.02.00 JH Renamed io.c to st.c again (io.h conflicts with system headers) +* 16.06.2002 0.02.00 JH New function: IkbdQueryBuffer(). X11 keysym conversion removed. +*/ +static char sccsid[] = "$Id: ikbd.c,v 1.3 2002/06/16 23:16:09 jhoenig Exp $"; +//#include "winbase.h" +#include +#include +#include "config.h" +#include "st.h" +#define IBS 10 /* Ikbd input buffer size */ +#define OBS 20 /* Ikbd output buffer size */ + + +extern char Msg[400]; +extern FILE* logfile; +extern int exmousex,exmousey; +int pause = 0; +struct _mouse mouse; +struct _joystick joystick; + +extern unsigned char joynum; +unsigned char inbuff[IBS]; +unsigned char outbuff[OBS]; +int inbuffi = 0; +int outbuffi = 0; +int oldjoystate =0; +int joytick=0; +unsigned char Buttons; +//SYSTEMTIME SystemTime; +unsigned char TempButtons=0x0a; +unsigned char PrevButtons; + +unsigned char Misc_ConvertToBCD(unsigned short int Value) +{ + return( ((Value&0xf0)>>4)*10 + (Value&0x0f) ); +} + +void IkbdRecv(unsigned char inchar) +{ +#ifdef DEBUG + fprintf (stderr, "IkbdRecv: %d\n", inchar); +#endif + if (inbuffi == IBS) { + fprintf (stderr, "IkbdRecv: Input buffer overrun!\n"); + inbuffi = 0; + } + inbuff[inbuffi++] = inchar; + switch (inbuff[0]) { + case 0x07: /* set mouse button action */ + if (inbuffi == 2) { + inbuffi = 0; + mouse.button_action = inbuff[1]; + } + break; + case 0x08: /* set relative mouse position reporting */ + inbuffi = 0; + mouse.mode = 1; + break; + case 0x09: /* set absolute mouse positioning */ + if (inbuffi == 5) { + mouse.mode = 2; + mouse.xmax = (inbuff[1] << 8) | inbuff[2]; + mouse.ymax = (inbuff[3] << 8) | inbuff[4]; + mouse.x=mouse.xmax/2; + mouse.y=mouse.ymax/2; + inbuffi = 0; + } + break; + case 0x0a: /* set mouse keycode mode */ + if (inbuffi == 3) { + mouse.mode = 3; + mouse.xkcm = inbuff[1]; + mouse.ykcm = inbuff[2]; + inbuffi = 0; + } + break; + case 0x0b: /* set mouse threshold */ + if (inbuffi == 3) { + mouse.xth = inbuff[1]; + mouse.yth = inbuff[2]; + inbuffi = 0; + } + break; + case 0x0c: /* set mouse scale */ + if (inbuffi == 3) { + mouse.xscale = inbuff[1]; + mouse.yscale = inbuff[2]; + inbuffi = 0; + } + break; + case 0x0d: /* interrogate mouse position */ + + if (outbuffi < (OBS -6)){ + inbuffi = 0; + /* Test buttons */ + Buttons = 0; + /* Set buttons to show if up/down */ + if (mouse.stbuttons&1) Buttons |= 0x01; else Buttons |= 0x02; + if (mouse.stbuttons&2) Buttons |= 0x04; else Buttons |= 0x08; + + /* Mask off it didn't send last time */ + PrevButtons = TempButtons; + TempButtons = Buttons; + Buttons &= ~PrevButtons; +//printf("xy %d %d\n", mouse.stx,mouse.sty); + + IkbdSend (0xf7); + IkbdSend (Buttons); + IkbdSend (mouse.stx >> 8); + IkbdSend (mouse.stx); + IkbdSend (mouse.sty >> 8); + IkbdSend (mouse.sty); + } + break; + + case 0x0e: /* load mouse position */ + if (inbuffi == 6) { + inbuffi = 0; + mouse.x = exmousex = mouse.stx = (inbuff[2] << 8) | inbuff[3]; + mouse.y = exmousey = mouse.sty = (inbuff[4] << 8) | inbuff[5]; + } + break; + case 0x0f: /* set Y=0 at bottom */ + inbuffi = 0; + mouse.yinv = 1; + break; + case 0x10: /* set Y=0 at top */ + inbuffi = 0; + mouse.yinv = 0; + break; + case 0x11: /* resume */ + inbuffi = 0; + pause = 0; + break; + case 0x12: /* disable mouse */ + inbuffi = 0; + //mouse.mode = 0; + break; + case 0x13: /* pause output */ + inbuffi = 0; + //pause = 1; + break; + case 0x14: /* set joystick event reporting */ + inbuffi = 0; + joystick.mode = 1; + break; + case 0x15: /* set joystick interrogation mode */ + inbuffi = 0; + joystick.mode = 2; + break; + case 0x16: /* joystick interrogation */ + inbuffi = 0; + IkbdSend (0xfd); + IkbdSend (0); + IkbdSend (oldjoystate); + break; + case 0x17: /* set joystick monitoring */ + if (inbuffi == 2) { + inbuffi = 0; + joystick.rate = inbuff[1]; + joystick.mode = 4; + } + break; + case 0x18: /* set fire button monitoring */ + inbuffi = 0; + joystick.mode = 5; + break; + case 0x19: /* set joystick keycode mode */ + if (inbuffi == 7) { + inbuffi = 0; + joystick.mode = 3; + } + break; + case 0x1a: /* disable joysticks */ + inbuffi = 0; + // joystick.mode = 0; + break; + case 0x1b: /* time-of-day clock set */ + if (inbuffi == 7) { + inbuffi = 0; + } + break; + case 0x1c: /* interrogate time-of-day clock */ + inbuffi = 0; + IkbdSend (0xfc); + IkbdSend (0x0); + IkbdSend (0x0); + IkbdSend (0x0); + IkbdSend (0x0); + IkbdSend (0x0); + IkbdSend (0x0); + break; + case 0x20: /* memory load */ + case 0x21: /* memory read */ + case 0x22: /* controller execute */ + inbuffi = 0; + break; + case 0x80: /* reset */ + if (inbuffi == 2) { + IkbdSend (0xf0); + inbuffi = 0; + mouse.buttons = mouse.stbuttons = 0; + switch (vid_shiftmode) { + case 0: + mouse.x = exmousex = mouse.stx = 160; + mouse.y = exmousey = mouse.sty = 100; + break; + case 1: + mouse.x = exmousex = mouse.stx = 320; + mouse.y = exmousey = mouse.sty = 100; + break; + case 2: + mouse.x = exmousex = mouse.stx = 320; + mouse.y = exmousey = mouse.sty = 200; + break; + } + } + break; + case 0x87: /* request button action */ + IkbdSend (0x07); + IkbdSend (mouse.button_action); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + break; + case 0x88: /* request mouse mode */ + case 0x89: + case 0x8a: + switch (mouse.mode) { + case 1: + IkbdSend (0x08); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + break; + case 2: + IkbdSend (0x09); + IkbdSend (mouse.xmax >> 8); + IkbdSend (mouse.xmax); + IkbdSend (mouse.ymax >> 8); + IkbdSend (mouse.ymax); + IkbdSend (0); + IkbdSend (0); + break; + case 3: + IkbdSend (0x09); + IkbdSend (mouse.xkcm); + IkbdSend (mouse.ykcm); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + break; + } + inbuffi = 0; + mouse.mode = 1; + break; + case 0x8b: /* request mouse threshold */ + IkbdSend (0x0b); + IkbdSend (mouse.xth); + IkbdSend (mouse.yth); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + inbuffi = 0; + break; + case 0x8c: /* request mouse scale */ + IkbdSend (0x0b); + IkbdSend (mouse.xscale); + IkbdSend (mouse.yscale); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + inbuffi = 0; + break; + case 0x8f: /* request mouse vertical coordinates */ + case 0x90: + if (mouse.yinv) + IkbdSend (0x0f); + else + IkbdSend (0x10); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + inbuffi = 0; + break; + case 0x92: /* disable mouse */ + if (mouse.mode) + IkbdSend (0); + else + IkbdSend (0x12); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + inbuffi = 0; + break; + case 0x94: /* request joystick mode */ + case 0x95: + case 0x99: /* set joystick keycode mode */ + inbuffi = 0; + switch (joystick.mode) { + case 1: + IkbdSend (0x14); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + break; + case 2: + IkbdSend (0x15); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + IkbdSend (0); + break; + case 3: + IkbdSend (0x19); + IkbdSend (joystick.rx); + IkbdSend (joystick.ry); + IkbdSend (joystick.tx); + IkbdSend (joystick.ty); + IkbdSend (joystick.vx); + IkbdSend (joystick.vy); + break; + } + inbuffi = 0; + break; + case 0x9a: /* request joystick availability */ + if (joystick.mode) + IkbdSend (0); + else + IkbdSend (0x1a); + IkbdSend (joystick.rx); + IkbdSend (joystick.ry); + IkbdSend (joystick.tx); + IkbdSend (joystick.ty); + IkbdSend (joystick.vx); + IkbdSend (joystick.vy); + inbuffi = 0; + break; + } +} + +void IkbdSend (unsigned char outchar) +{ +#ifdef DEBUG + fprintf (stderr, "IkbdSend: %d\n", outchar); +#endif + if (outbuffi < (OBS - 1)) { + outbuff[outbuffi++] = outchar; + } +} + +void IkbdWriteBuffer(void) +{ +/* +if (mouse.flag && (outbuffi < (OBS / 2))) { +IkbdMouse (); +} +if (joystick.mode==4) IkbdJoystick(); + */ + if (outbuffi>0 && !pause && (acia1_sr & 0x1) == 0) { + acia1_sr |= 1; + if (acia1_cr & 0x80) { /* receiver interrupt enabled? */ + acia1_sr |= 0x80; + mfp_gpip &= (~0x10); + } + acia1_dr = outbuff[0]; + memcpy (&outbuff[0], &outbuff[1], (OBS - 1)); + outbuffi--; + } +} + +void IkbdKeyPress (unsigned short keysym) { + IkbdSend (keysym); +} + +void IkbdKeyRelease (unsigned short keysym) { + IkbdSend (0x80 | keysym); +} + +void IkbdMouseMotion (int x, int y) +{ + if (vid_shiftmode==1) {x+=x;} + if (vid_shiftmode==2) {x+=x; y+=y;} + mouse.x=x; mouse.y=y; +} + +void IkbdMousePress (int code) { + mouse.buttons |= code; +} + +void IkbdMouseRelease (int code) { + mouse.buttons &= ~code; +} + +void joystickevent (int joystate) +{ + //Has joystick moved? + if (joystate==oldjoystate) return; + oldjoystate=joystate; + //send fire button to mouse as well + if (mouse.mode==1 || mouse.mode==0) { + if (joystate&0x80) { + IkbdSend (0xf9); + IkbdSend (0); + IkbdSend (0); + } + else { + IkbdSend (0xf8); + IkbdSend (0); + IkbdSend (0); + } + } + //In event mode send the joystick event immediately + if (joystick.mode==1) { + IkbdSend (0xff); + IkbdSend (joystate); + } + //debug log + /* + sprintf (Msg,"\\castlog2.txt"); + logfile = fopen(Msg,"at"); + sprintf (Msg,"mousemode:%d mx:%d my:%d smx:%d smy:%d\n",mouse.mode,mouse.x,mouse.y,mouse.stx,mouse.sty); + fwrite(Msg,strlen(Msg),1,logfile); + fflush (logfile); fclose(logfile); + */ +} + +void IkbdLoop() +{ + int dx, dy; + if (mouse.mode==1) { + dx=mouse.x-mouse.stx; if (dx>127) dx=127; else if (dx<-127) dx=-127; + dy=mouse.y-mouse.sty; if (dy>127) dy=127; else if (dy<-127) dy=-127; + if (mouse.stbuttons!=mouse.buttons || dx>mouse.xth || dy>mouse.yth || -dx>mouse.xth || -dy>mouse.yth) { + if (outbuffi= 319) {mouse.stx = 319; dx = 127;} + if (mouse.sty >= 199) {mouse.sty = 199; dy = 127;} + break; + case 1: + if (mouse.stx >= 639) {mouse.stx = 639; dx = 127;} + if (mouse.sty >= 199) {mouse.sty = 199; dy = 127;} + break; + case 2: + if (mouse.stx >= 639) {mouse.stx = 639; dx = 127;} + if (mouse.sty >= 399) {mouse.sty = 399; dy = 127;} + break; + } + IkbdSend (0xf8 | (mouse.stbuttons&3)); + IkbdSend (dx); + IkbdSend (dy); + } + } + } + else { + if (mouse.x>mouse.xmax) mouse.x=mouse.xmax; + if (mouse.y>mouse.ymax) mouse.y=mouse.ymax; + mouse.stx=mouse.x; + mouse.sty=mouse.y; + mouse.stbuttons=mouse.buttons; + + } + if (joystick.mode==4) { + //Called at 200hz when joystick is in mode 4 + joytick+=2; + if (joytick>7); + IkbdSend (oldjoystate&15); + } +} + +void IkbdReset (void) +{ + joystick.mode=1; + mouse.mode=1; +} + + +void IkbdJoystickChange(int number, uint8 state) +{ + joystickevent(state); +} diff --git a/MCUME_esp32/espcastaway/main/ili9341_t3dma.cpp b/MCUME_esp32/espcastaway/main/ili9341_t3dma.cpp new file mode 100644 index 0000000..41c3a53 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/ili9341_t3dma.cpp @@ -0,0 +1,680 @@ +/* + ILI9341 SPI driver inspired from the Teensy version of Frank Bösing, 2017 +*/ + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#include "esp_system.h" +#include "driver/spi_master.h" +#include "soc/gpio_struct.h" +#include "driver/gpio.h" + +#include + +#include "ili9341_t3dma.h" +#include "font8x8.h" + + + +static spi_device_handle_t lcdspi; +static spi_transaction_t trans[MAX_SPI_TRANS]; + +static uint16_t *blocks[NR_OF_BLOCK]; +static uint8_t _rst, _cs, _dc; +static uint8_t _miso, _mosi, _clk; +static uint8_t _touch_irq, _touch_cs; + +//DRAM_ATTR static uint16_t block0[320*LINES_PER_BLOCK]; +//DRAM_ATTR static uint16_t block1[320*LINES_PER_BLOCK]; + +static const lcd_init_cmd_t ili_init_cmds[]={ + {0xEF, {0x03, 0x80, 0x02}, 3}, + {0xCF, {0x00, 0XC1, 0X30}, 3}, + {0xED, {0x64, 0x03, 0X12, 0X81}, 4}, + {0xE8, {0x85, 0x00, 0x78}, 3}, + {0xCB, {0x39, 0x2C, 0x00, 0x34, 0x02}, 5}, + {0xF7, {0x20}, 1}, + {0xEA, {0x00, 0x00}, 2}, + {ILI9341_PWCTR1, {0x23}, 1}, // Power control + {ILI9341_PWCTR2, {0x10}, 1}, // Power control + {ILI9341_VMCTR1, {0x3e, 0x28}, 2}, // VCM control + {ILI9341_VMCTR2, {0x86}, 1}, // VCM control2 + {ILI9341_MADCTL, {0x48}, 1}, // Memory Access Control + {ILI9341_PIXFMT, {0x55}, 1}, + {ILI9341_FRMCTR1, {0x00, 0x18}, 2}, + {ILI9341_DFUNCTR, {0x08, 0x82, 0x27}, 3}, // Display Function Control + {0xF2, {0x00}, 1}, // Gamma Function Disable + {ILI9341_GAMMASET, {0x01}, 1}, // Gamma curve selected + {ILI9341_GMCTRP1, {0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, + 0x4E, 0xF1, 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00}, 15}, // Set Gamma + {ILI9341_GMCTRN1, {0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, + 0x31, 0xC1, 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F}, 15}, // Set Gamma +// 3, 0xb1, 0x00, 0x1f, // FrameRate Control 61Hz + {0xb1, {0x00, 0x10}, 2}, // FrameRate Control 119Hz + {ILI9341_MADCTL, {MADCTL_MX | MADCTL_MY | MADCTL_MV | MADCTL_BGR}, 1}, + + /* Sleep out */ + {ILI9341_SLPOUT, {0}, 0x80}, + /* Display on */ + {ILI9341_DISPON, {0}, 0x80}, + + + // Area width, hight + {ILI9341_CASET, {0, 0, (ILI9341_TFTREALWIDTH)>>8, (ILI9341_TFTREALWIDTH)&0xff}, 4}, + {ILI9341_PASET, {0, 0, (ILI9341_TFTREALHEIGHT)>>8, (ILI9341_TFTREALHEIGHT)&0xff}, 4}, + + {0, {0}, 0xff}, +}; + +static void lcd_cmd(spi_device_handle_t spi, const uint8_t cmd) +{ + esp_err_t ret; + spi_transaction_t t; + memset(&t, 0, sizeof(t)); //Zero out the transaction + t.length=8; //Command is 8 bits + t.tx_buffer=&cmd; //The data is the cmd itself + t.user=(void*)0; //D/C needs to be set to 0 + t.flags=0; + ret=spi_device_polling_transmit(spi, &t); //Transmit! + assert(ret==ESP_OK); //Should have had no issues. +} + + +static void lcd_data(spi_device_handle_t spi, const uint8_t *data, int len) +{ + esp_err_t ret; + spi_transaction_t t; + if (len==0) return; //no need to send anything + memset(&t, 0, sizeof(t)); //Zero out the transaction + t.length=len*8; //Len is in bytes, transaction length is in bits. + t.tx_buffer=data; //Data + t.user=(void*)1; //D/C needs to be set to 1 + t.flags=0; + ret=spi_device_polling_transmit(spi, &t); //Transmit! + assert(ret==ESP_OK); //Should have had no issues. +} + +//This function is called (in irq context!) just before a transmission starts. It will +//set the D/C line to the value indicated in the user field. +static void lcd_spi_pre_transfer_callback(spi_transaction_t *t) +{ + int dc=(int)t->user; + gpio_set_level((gpio_num_t)_dc, dc); +} + + +//Initialize the display +static void lcd_init(spi_device_handle_t spi) +{ + //Initialize non-SPI GPIOs + gpio_set_direction((gpio_num_t)_dc, GPIO_MODE_OUTPUT); + + printf("LCD ILI9341 initialization.\n"); + //Send all the commands + + + //memcpy(ili_init_cmds, ili_init_cmdos, sizeof(ili_init_cmdos)); + int cmd=0; + while (ili_init_cmds[cmd].databytes!=0xff) { + lcd_cmd(spi, ili_init_cmds[cmd].cmd); + lcd_data(spi, ili_init_cmds[cmd].data, ili_init_cmds[cmd].databytes&0x1F); + if (ili_init_cmds[cmd].databytes&0x80) { + vTaskDelay(100 / portTICK_RATE_MS); + } + cmd++; + } + + + + //Allocate memory block buffers and DMA transactions + printf("Allocate video mem and DMA transactions\n"); + + int i=0; + trans[i].tx_data[0]=ILI9341_RAMWR; + trans[i].length=8; + trans[i].user=(void*)0; + trans[i++].flags=SPI_TRANS_USE_TXDATA; + + //blocks[0]= &block0[0]; + //blocks[1]= &block1[0]; + + int remaininglines=ILI9341_TFTREALHEIGHT; + for (int j=0; j 1)*/ blocks[j]= (uint16_t*)heap_caps_malloc(ILI9341_TFTREALWIDTH*lines_per_block*sizeof(uint16_t), MALLOC_CAP_DMA); + assert(blocks[j]!=NULL); + + trans[i].tx_buffer=blocks[j]; + trans[i].length=ILI9341_TFTREALWIDTH*2*8*lines_per_block; + trans[i].user=(void*)1; + trans[i++].flags=0; //undo SPI_TRANS_USE_TXDATA flag + + uint16_t color; + switch (j) { + case 0: + color=0xf000; + break; + case 1: + color=0x0f00; + break; + case 2: + color=0x00f0; + break; + case 3: + default: + color=0x000f; + break; + } + uint16_t * fb = blocks[j]; + for (int y=0;y>6]; + return(&block[(j&0x3F)*ILI9341_TFTREALWIDTH]); +} + + +void ILI9341_t3DMA::fillScreen(uint16_t color) { + int i,j; + color=SPI_SWAP_DATA_TX(color,16); + for (j=0; j>6]; + uint16_t * dst=&block[(j&0x3F)*ILI9341_TFTREALWIDTH]; + for (i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH]; + src=buffer; + for (i=0; i>6]; + dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH]; + src=buffer; + for (i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH+(ILI9341_TFTREALWIDTH-width)/2]; + src=buffer; + for (i=0; i>6]; + dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH+(ILI9341_TFTREALWIDTH-width)/2]; + src=buffer; + for (i=0; i height) + y += (ILI9341_TFTHEIGHT - height)/2; + uint8_t * src=buf; + uint16_t * block=blocks[y>>6]; + uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH]; + if (ILI9341_TFTWIDTH > width) + dst += (ILI9341_TFTWIDTH - width)/2; + for (int i=0; i height) + y += (ILI9341_TFTHEIGHT - height)/2; + uint16_t * src=buf; + uint16_t * block=blocks[y>>6]; + uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH]; + if (ILI9341_TFTWIDTH > width) + dst += (ILI9341_TFTWIDTH - width)/2; + for (int i=0; i>6]; + uint16_t * dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+x]; + for (i=0; i(arx+arw)) || ((x+w)(ary+arh)) || ((y+h) arx) && (x<(arx+arw)) ) { + arw = arw - (x-arx); + arx = arx + (x-arx); + } else { + bmp_offx = arx; + } + if ( ((x+w) > arx) && ((x+w)<(arx+arw)) ) { + arw -= (arx+arw-x-w); + } + if ( (y > ary) && (y<(ary+arh)) ) { + arh = arh - (y-ary); + ary = ary + (y-ary); + } else { + bmp_offy = ary; + } + if ( ((y+h) > ary) && ((y+h)<(ary+arh)) ) { + arh -= (ary+arh-y-h); + } + } + + + int l=ary; + bitmap = bitmap + bmp_offy*w + bmp_offx; + for (int row=0;row>6]; + uint16_t * dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+arx]; + bmp_ptr = (uint16_t*)bitmap; + for (int col=0;col>6]; + dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+x]; + bits = *charpt; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + l++; + } + block=blocks[l>>6]; + dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+x]; + bits = *charpt++; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + l++; + } + x +=8; + } +} + + + +// TOUCH +#define _BV(bit) (1 << (bit)) +#define XPT2046_CFG_START _BV(7) +#define XPT2046_CFG_MUX(v) ((v&0b111) << (4)) +#define XPT2046_CFG_8BIT _BV(3) +#define XPT2046_CFG_12BIT (0) +#define XPT2046_CFG_SER _BV(2) +#define XPT2046_CFG_DFR (0) +#define XPT2046_CFG_PWR(v) ((v&0b11)) +#define XPT2046_MUX_Y 0b101 +#define XPT2046_MUX_X 0b001 +#define XPT2046_MUX_Z1 0b011 +#define XPT2046_MUX_Z2 0b100 + + + +static spi_device_handle_t touchspi; + +//void ILI9341_t3DMA::touchBegin(uint8_t mosi, uint8_t miso, uint8_t clk, uint8_t cs) { +void ILI9341_t3DMA::touchBegin() { + esp_err_t ret; + + gpio_set_direction((gpio_num_t)_touch_irq, GPIO_MODE_INPUT); + gpio_set_pull_mode((gpio_num_t)_touch_irq, GPIO_PULLUP_ONLY); + + spi_device_interface_config_t devcfg; + memset(&devcfg, 0, sizeof(devcfg)); + devcfg.clock_speed_hz=2500000; + devcfg.mode=0; + devcfg.spics_io_num=_touch_cs; + devcfg.queue_size=2; + devcfg.flags = SPI_DEVICE_HALFDUPLEX ; + + /* + spi_bus_config_t buscfg; + memset(&buscfg, 0, sizeof(buscfg)); + buscfg.miso_io_num=miso; + buscfg.mosi_io_num=mosi; + buscfg.sclk_io_num=clk; + buscfg.quadwp_io_num=-1; + buscfg.quadhd_io_num=-1; + buscfg.max_transfer_sz=48; + + ret=spi_bus_initialize(HSPI_HOST, &buscfg, 2); + ESP_ERROR_CHECK(ret); + */ + + ret=spi_bus_add_device(HSPI_HOST, &devcfg, &touchspi); + ESP_ERROR_CHECK(ret); +} + + +uint16_t touch_get_data(spi_device_handle_t spi, const uint8_t cmd) +{ + spi_transaction_t t; + memset(&t, 0, sizeof(t)); //Zero out the transaction + t.length=8; //Command is 8 bits + t.tx_buffer=&cmd; //The data is the cmd itself + esp_err_t ret=spi_device_polling_transmit(spi, &t); //Transmit! + if (ret==ESP_OK) { + memset(&t, 0, sizeof(t)); + t.rxlength=8*2; + t.flags = SPI_TRANS_USE_RXDATA; + ret = spi_device_polling_transmit(spi, &t); + if (ret==ESP_OK) { + printf("touch data failed\n"); + return 0; + } + } + else { + printf("touch cmd failed\n"); + } + return *(uint16_t*)t.rx_data; +} + + + +bool ILI9341_t3DMA::isTouching() +{ + return ((gpio_get_level((gpio_num_t)_touch_irq) == 0 ? true : false)); +} + +void ILI9341_t3DMA::readRo(uint16_t * oX, uint16_t * oY, uint16_t * oZ) { + uint16_t x = 0; + uint16_t y = 0; + uint16_t z1 = 0; + uint16_t z2 = 0; + uint8_t i = 0; + int16_t xraw=0, yraw=0; + + + for(; i < 15; i++) { + y += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Y) | XPT2046_CFG_PWR(3))); + x += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_X) | XPT2046_CFG_PWR(3))); + z1 += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z1)| XPT2046_CFG_PWR(3))); + z2 += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z2)| XPT2046_CFG_PWR(3))); + } + printf("%d %d %d %d \n",x/15,y/15,z1/15,z2/15); +/* + SPI.beginTransaction(SPI_SETTING); + digitalWrite(_touch_cs, LOW); + + for(; i < 15; i++) { + // SPI requirer 32bit aliment + uint8_t buf[12] = { + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Y) | XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_X) | XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z1)| XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z2)| XPT2046_CFG_PWR(3)), 0x00, 0x00 + }; + SPI.transfer(&buf[0], &buf[0], 12); + y += (buf[1] << 8 | buf[2])>>3; + x += (buf[4] << 8 | buf[5])>>3; + z1 += (buf[7] << 8 | buf[8])>>3; + z2 += (buf[10] << 8 | buf[11])>>3; + } + */ +} + +void ILI9341_t3DMA::readRaw(uint16_t * oX, uint16_t * oY, uint16_t * oZ) { + +} + +void ILI9341_t3DMA::readCal(uint16_t * oX, uint16_t * oY, uint16_t * oZ){ + +} + +void ILI9341_t3DMA::callibrateTouch(uint16_t xMin,uint16_t yMin,uint16_t xMax,uint16_t yMax){ + +} + + diff --git a/MCUME_esp32/espcastaway/main/ili9341_t3dma.h b/MCUME_esp32/espcastaway/main/ili9341_t3dma.h new file mode 100644 index 0000000..304c5d1 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/ili9341_t3dma.h @@ -0,0 +1,154 @@ +/* + ILI9341 SPI driver inspired from the Teensy version of Frank Bösing, 2017 +*/ + +#ifndef _ILI9341_T3DMAH_ +#define _ILI9341_T3DMAH_ + + +#define FLIP_SCREEN 1 + + +#define RGBVAL32(r,g,b) ( (r<<16) | (g<<8) | b ) +#define RGBVAL16(r,g,b) ( (((r>>3)&0x1f)<<11) | (((g>>2)&0x3f)<<5) | (((b>>3)&0x1f)<<0) ) +#define RGBVAL8(r,g,b) ( (((r>>5)&0x07)<<5) | (((g>>5)&0x07)<<2) | (((b>>6)&0x3)<<0) ) + + +#define ILI9341_TFTWIDTH 320 +#define ILI9341_TFTHEIGHT 240 +#define ILI9341_TFTREALWIDTH 320 +#define ILI9341_TFTREALHEIGHT 240 + + +#define ILI9341_NOP 0x00 +#define ILI9341_SWRESET 0x01 +#define ILI9341_RDDID 0x04 +#define ILI9341_RDDST 0x09 + +#define ILI9341_SLPIN 0x10 +#define ILI9341_SLPOUT 0x11 +#define ILI9341_PTLON 0x12 +#define ILI9341_NORON 0x13 + +#define ILI9341_RDMODE 0x0A +#define ILI9341_RDMADCTL 0x0B +#define ILI9341_RDPIXFMT 0x0C +#define ILI9341_RDIMGFMT 0x0D +#define ILI9341_RDSELFDIAG 0x0F + +#define ILI9341_INVOFF 0x20 +#define ILI9341_INVON 0x21 +#define ILI9341_GAMMASET 0x26 +#define ILI9341_DISPOFF 0x28 +#define ILI9341_DISPON 0x29 + +#define ILI9341_CASET 0x2A +#define ILI9341_PASET 0x2B +#define ILI9341_RAMWR 0x2C +#define ILI9341_RAMRD 0x2E + +#define ILI9341_PTLAR 0x30 +#define ILI9341_MADCTL 0x36 +#define ILI9341_VSCRSADD 0x37 +#define ILI9341_PIXFMT 0x3A + +#define ILI9341_FRMCTR1 0xB1 +#define ILI9341_FRMCTR2 0xB2 +#define ILI9341_FRMCTR3 0xB3 +#define ILI9341_INVCTR 0xB4 +#define ILI9341_DFUNCTR 0xB6 + +#define ILI9341_PWCTR1 0xC0 +#define ILI9341_PWCTR2 0xC1 +#define ILI9341_PWCTR3 0xC2 +#define ILI9341_PWCTR4 0xC3 +#define ILI9341_PWCTR5 0xC4 +#define ILI9341_VMCTR1 0xC5 +#define ILI9341_VMCTR2 0xC7 + +#define ILI9341_RDID1 0xDA +#define ILI9341_RDID2 0xDB +#define ILI9341_RDID3 0xDC +#define ILI9341_RDID4 0xDD + +#define ILI9341_GMCTRP1 0xE0 +#define ILI9341_GMCTRN1 0xE1 + +#define MADCTL_MY 0x80 +#define MADCTL_MX 0x40 +#define MADCTL_MV 0x20 +#define MADCTL_ML 0x10 +#define MADCTL_RGB 0x00 +#define MADCTL_BGR 0x08 +#define MADCTL_MH 0x04 + +#ifdef __cplusplus + + +#define MAX_SPI_TRANS 7 +#define NR_OF_BLOCK 4 +#define LINES_PER_BLOCK 64 //(ILI9341_TFTREALHEIGHT/4) + +typedef struct { + uint8_t cmd; + uint8_t data[16]; + uint8_t databytes; //No of data in data; bit 7 = delay after set; 0xFF = end of cmds. +} lcd_init_cmd_t; + + +class ILI9341_t3DMA +{ + public: + ILI9341_t3DMA(uint8_t _CS = 17, uint8_t _DC = 18, uint8_t _RST = 255, uint8_t _MOSI=23, uint8_t _CLK=18, uint8_t _MISO=19, uint8_t touch_cs=32, uint8_t touch_irq=33); + + //void setFrameBuffer(uint16_t * fb); + //static uint16_t * getFrameBuffer(void); + + void begin(void); + void flipscreen(bool flip); + bool isflipped(void); + void start(void); + void refresh(void); + void refreshPrepare(void); + void refreshFinish(void); + //void stop(); + //void wait(void); + uint16_t * getLineBuffer(int j); + + void fillScreen(uint16_t color); + void writeScreen(int width, int height, int stride, uint8_t *buffer, uint16_t *palette16); + void writeLine(int width, int height, int stride, uint8_t *buffer, uint16_t *palette16); + void writeLine(int width, int height, int stride, uint16_t *buffer); + void drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color); + void drawSprite(int16_t x, int16_t y, const uint16_t *bitmap); + void drawSprite(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh); + void drawText(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize); + + void fillScreenNoDma(uint16_t color) { fillScreen(color); }; + void drawSpriteNoDma(int16_t x, int16_t y, const uint16_t *bitmap) { drawSprite(x,y,bitmap); }; + void drawSpriteNoDma(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh) { drawSprite(x,y,bitmap,croparx,cropary,croparw,croparh); }; + void drawRectNoDma(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color) { drawRect(x,y,w,h,color); }; + void drawTextNoDma(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize) { drawText(x,y,text,fgcolor,bgcolor,doublesize); }; + + /* + void writeScreenNoDma(const uint16_t *pcolors); + void drawPixel(int16_t x, int16_t y, uint16_t color); + uint16_t getPixel(int16_t x, int16_t y); + */ + + + void touchBegin(); + void readRo(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + bool isTouching(); + void readRaw(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + void readCal(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + void callibrateTouch(uint16_t xMin,uint16_t yMin,uint16_t xMax,uint16_t yMax); + + protected: + bool flipped=false; + void enableTouchIrq(); +}; + +#endif +#endif + diff --git a/MCUME_esp32/espcastaway/main/iopins.h b/MCUME_esp32/espcastaway/main/iopins.h new file mode 100644 index 0000000..1233f58 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/iopins.h @@ -0,0 +1,60 @@ +#ifndef IOPINS_H +#define IOPINS_H + + +// ILI9341 +//#define PIN_NUM_CS (gpio_num_t)15 +//#define PIN_NUM_CLK (gpio_num_t)14 +//#define PIN_NUM_MISO (gpio_num_t)12 +//#define PIN_NUM_MOSI (gpio_num_t)13 +//#define PIN_NUM_DC (gpio_num_t)16 + +#define TPIN_NUM_CS (gpio_num_t)32 +#define TPIN_NUM_IRQ (gpio_num_t)33 + + +#define PIN_NUM_CS (gpio_num_t)22 //17 +#define PIN_NUM_CLK (gpio_num_t)18 +#define PIN_NUM_MISO (gpio_num_t)19 +#define PIN_NUM_MOSI (gpio_num_t)23 +#define PIN_NUM_DC (gpio_num_t)21 + +// SD card SPI +#define SPIN_NUM_CS (gpio_num_t)15 +#define SPIN_NUM_CLK (gpio_num_t)14 +#define SPIN_NUM_MISO (gpio_num_t)12 +#define SPIN_NUM_MOSI (gpio_num_t)13 + + +// I2C keyboard +#define I2C_SCL_IO (gpio_num_t)5 +#define I2C_SDA_IO (gpio_num_t)4 + + +// Analog joystick (primary) for JOY2 and 5 extra buttons +#define PIN_JOY2_A1X ADC2_CHANNEL_7 // 27 //ADC1_CHANNEL_0 +#define PIN_JOY2_A2Y ADC2_CHANNEL_2 // 2 //ADC1_CHANNEL_3 +#define PIN_JOY2_BTN 32 + +#define PIN_KEY_USER1 35 +//#define PIN_KEY_USER2 34 +//#define PIN_KEY_USER3 39 +//#define PIN_KEY_USER4 36 +/* +#define PIN_KEY_ESCAPE 23 +*/ + +// Second joystick +/* +#define PIN_JOY1_BTN 30 +#define PIN_JOY1_1 16 +#define PIN_JOY1_2 17 +#define PIN_JOY1_3 18 +#define PIN_JOY1_4 19 +*/ + +#endif + + + + diff --git a/MCUME_esp32/espcastaway/main/keyboard_osd.h b/MCUME_esp32/espcastaway/main/keyboard_osd.h new file mode 100644 index 0000000..062eb4e --- /dev/null +++ b/MCUME_esp32/espcastaway/main/keyboard_osd.h @@ -0,0 +1,20 @@ + +#ifndef keyboard_osd_h_ +#define keyboard_osd_h_ + +extern bool virtualkeyboardIsActive(void); +extern void drawVirtualkeyboard(void); +extern void toggleVirtualkeyboard(bool keepOn); +extern void handleVirtualkeyboard(void); + +extern bool callibrationActive(void); +extern int handleCallibration(uint16_t bClick); + +extern bool menuActive(void); +extern char * menuSelection(void); +extern void toggleMenu(bool on); +extern int handleMenu(uint16_t bClick); + + +#endif + diff --git a/MCUME_esp32/espcastaway/main/main.c b/MCUME_esp32/espcastaway/main/main.c new file mode 100644 index 0000000..5dc5bee --- /dev/null +++ b/MCUME_esp32/espcastaway/main/main.c @@ -0,0 +1,31 @@ + +#include "freertos/FreeRTOS.h" +#include "esp_wifi.h" +#include "esp_system.h" +#include "esp_event.h" +#include "esp_event_loop.h" +#include "nvs_flash.h" +#include "driver/gpio.h" +#include "esp_partition.h" + +#include "go.h" + + +int app_main(void) +{ + printf("Test start!\n"); + + setup(); + while(1) { + loop(); + } + + for (int i = 10; i >= 0; i--) { + printf("Restarting in %d seconds...\n", i); + vTaskDelay(1000 / portTICK_PERIOD_MS); + } + printf("Restarting now.\n"); + fflush(stdout); + esp_restart(); +} + diff --git a/MCUME_esp32/espcastaway/main/mem.cpp b/MCUME_esp32/espcastaway/main/mem.cpp new file mode 100755 index 0000000..547e54c --- /dev/null +++ b/MCUME_esp32/espcastaway/main/mem.cpp @@ -0,0 +1,510 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* $File$ - memory read/write +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 30.05.2002 JH Discontinued using mmap and mprotect, now using +* Martin's memory access jump table. +* 12.06.2002 JH Correct bus error/address error exception stack frame +* 14.06.2002 JH LowRamSetX() functions improved. +* 09.07.2002 JH Now loads any 192k ROM file +* 10.07.2002 MAD Now loads any ROM file +* 16.09.2002 JH Bugfix: Word access on unmapped I/O address stacked +* two bus error stack frames. Fault address corrected. +* 08.10.2002 JH Fixed integer types. +* 27.10.2002 AG Trashed everything for more speed! mwuhahaha! +*/ + +#include +#include +#include +#ifndef DREAMCAST +#else +#include +#endif +#include "config.h" +#include "st.h" +#include "mem.h" +#include "m68k_intrf.h" + +#include "dcastaway.h" + +//int8 *membase=0; +//int8 *rombase=0; + +static unsigned rombase_pos=0; + +char rom[80]; // = ROM; +#ifdef DREAMCAST +void reinit_sdcard(void); +char rom_sd[24] = ROM_SD; +#endif +static int samvol[16]={0,0,0,1,1,1,2,3,5,7,11,17,25,38,57,85}; +extern uint32 psg[26]; +#define lastpsg psg[25] +#define sampos psg[24] + +#define OPTIMIZE_VMEM 1 + +#ifdef OPTIMIZE_VMEM +signed char videobuf[32768]; +extern uint32 vid_mem; +#endif + + + +char GetMemB(unsigned long address) +{ + address &= MEMADDRMASK; + if (address= vid_mem) && (address < (vid_mem+32768) ) ) { + *((unsigned char *)(&videobuf[(address-vid_mem)^1])) = value; + } +#endif + WriteB(address + membase, value); +} + +/* Write byte to address */ +void SetMemB (unsigned long address, unsigned char value) +{ + address &= MEMADDRMASK; + ON_WRITE(address, value); + if (address=IOBASE && address= vid_mem) && (address < (vid_mem+32768) ) ) { + *(unsigned short *)(&videobuf[address-vid_mem]) = value; + } +#endif + WriteW(address + membase, value); +} + +/* Write word, address may not be word-aligned */ +void SetMemW(unsigned long address, unsigned short value) +{ +#ifdef CHKADDRESSERR + address &= MEMADDRMASK; + if (address & 0x1){ + ExceptionGroup0(ADDRESSERR, address, 1); + return; + } +#else + address &= MEMADDRMASKS; +#endif + ON_WRITE(address, value); + if (address=IOBASE && address= vid_mem) && (address < (vid_mem+32768) ) ) { + printf("vwlmem\n"); + WriteL(&videobuf[address-vid_mem], value); + } + else +#endif + WriteL(address + membase, value); + return; + } + if (address>=IOBASE && address>8)&15; + uint32 value1=value&255; + psg[psgctrl1]=value1; + if (psgctrl1==lastpsg) sample[sampos++]=samvol[psg[8]]+samvol[psg[9]]+samvol[value1]; + else if (psgctrl1==13 || psgctrl1==12) psg_epos=0; + return; +} +address &= MEMADDRMASK; +if (address>=IOBASE && address>8)); + DoIOWB(address+2, (int8)value); + return; +} +if (address>8)); + WriteB(address+2, (int8)value); + return; +} +} + +void SetMemPL(unsigned long address, unsigned long value) +{// int8 psgctrl1,psgctrl2,value1,value2; + +if (address&0xffff03==0xff8800) { + uint32 psgctrl1=(value>>24)&15; + uint32 value1=(value>>16)&255; + psg[psgctrl1]=value1; + if (psgctrl1==lastpsg) sample[sampos++]=samvol[psg[8]]+samvol[psg[9]]+samvol[value1]; + else if (psgctrl1==13 || psgctrl1==12) psg_epos=0; + psgctrl1=(value>>8)&15; + value1=value&255; + if (psgctrl1==lastpsg) sample[sampos++]=samvol[psg[8]]+samvol[psg[9]]+samvol[value1]; + else if (psgctrl1==13 || psgctrl1==12) psg_epos=0; + return; +} +address &= MEMADDRMASK; +if (address>=IOBASE && address>24)); + DoIOWB(address+2, (int8)(value>>16)); + DoIOWB(address+4, (int8)(value>>8)); + DoIOWB(address+6, (int8)value); + return; +} +if (address>24)); + WriteB(address+2, (int8)(value>>16)); + WriteB(address+4, (int8)(value>>8)); + WriteB(address+6, (int8)value); + return; +} +} + + +#ifdef UNUSED +static void *__rombase=NULL, *__membase=NULL; + +void MemQuit(void) +{ + if (__membase) + free(__membase); + __membase=NULL; + if (__rombase) + free(__rombase); + __rombase=NULL; +} + +static void _set_dword(void *buf,unsigned dat) +{ + unsigned short *b=(unsigned short *)buf; + *b++=dat&0xffff; + *b=dat>>16; +} + +void MemClean(void) +{ + membase=(int8*)__membase; + memset(membase,0,MEMSIZE); + //savestate_init(); + memcpy (membase, ((int8*)__rombase)+rombase_pos, 8); + + _set_dword(membase+0x420,0x752019f3); + _set_dword(membase+0x43a,0x237698aa); + _set_dword(membase+0x51a,0x5555aaaa); +#if MEMSIZE==0x00080000 + _set_dword(membase+0x436,0x80000-0x8000); + _set_dword(membase+0x42e,0x80000); + WriteB(membase+0x425,1); + WriteB(rombase+0xff8000,1); + memconf=1; +#else +#if MEMSIZE==0x00100000 + _set_dword(membase+0x436,0x100000-0x8000); + _set_dword(membase+0x42e,0x100000); + WriteB(membase+0x425,5); + WriteB(rombase+0xff8000,5); + memconf=5; +#else +#if MEMSIZE==0x00200000 + _set_dword(membase+0x436,0x200000-0x8000); + _set_dword(membase+0x42e,0x200000); + WriteB(membase+0x425,2); + WriteB(rombase+0xff8000,2); + memconf=2; +#else +#if MEMSIZE==0x00400000 + _set_dword(membase+0x436,0x400000-0x8000); + _set_dword(membase+0x42e,0x400000); + WriteB(membase+0x425,0xA); + WriteB(rombase+0xff8000,0xA); + memconf=0xA; +#else +#error DCaSTaway ERROR: MEMSIZE incorrect. +#endif +#endif +#endif +#endif + _set_dword(membase+0x4c2,3); + WriteW(membase+0x4a6,2); + + //if (TosCountry) + // vid_syncmode=2; + //else + // vid_syncmode=0; +} + + +static unsigned actual_rom_crc=0; + +static unsigned rom_checksum(void) +{ + int n; + unsigned crc=0; + for(n=ROMBASE2;n(MEMADDRSIZE-ROMBASE2)) + len=(MEMADDRSIZE-ROMBASE2); + if (len<=(192*1024)) + rombase_pos=ROMBASE-ROMBASE2; + else + rombase_pos=0; + + if (!__rombase) + __rombase = calloc(1,MEMADDRSIZE-ROMBASE2); + rombase=(int8*)__rombase; + for(n=0;n<(MEMADDRSIZE-ROMBASE2);n+=2) + { + rombase[n]=0x4e; + rombase[n+1]=0x71; + } + if (len != fread(rombase+rombase_pos,1,len,roms)) + { + fclose(roms); + return 2; + } + fclose (roms); +#ifdef BYTES_SWAP + for (n=0; n<(MEMADDRSIZE-ROMBASE2); n+=2) { + val1 = rombase[n]; + val2 = rombase[n+1]; + rombase[n] = val2; + rombase[n+1] =val1; + } +#endif + /* precalculate rombase - now just address-adding happens later */ + if (rombase_pos) + { + rombase -= ROMBASE2+rombase_pos-(ROMBASE-ROMBASE2); + memcpy(rombase+ROMBASE2,rombase+ROMBASE,(MEMADDRSIZE-ROMBASE)); + } + else + { + rombase -= ROMBASE2; + memcpy(rombase+ROMBASE,rombase+ROMBASE2,(MEMADDRSIZE-ROMBASE)); + } + + TOS_FixRom((uint8 *)(((int8*)__rombase)+rombase_pos)); + + //Allocate and clear RAM + if (!__membase) + __membase = (int8*)calloc(1,MEMSIZE+0x10); + MemClean(); + actual_rom_crc=rom_checksum(); + initialize_memmap(); + return 0; +} +#endif diff --git a/MCUME_esp32/espcastaway/main/mem.h b/MCUME_esp32/espcastaway/main/mem.h new file mode 100755 index 0000000..ee7fa07 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/mem.h @@ -0,0 +1,34 @@ +/* + * Read/Write memory macros - little endian + */ +#ifdef BYTES_SWAP +#define ReadB(address) *(uint8*)((uint32)(address)^1) +#define WriteB(address,value) *(uint8*)((uint32)(address)^1)=value +#define ReadW(addr) *(uint16*)(addr) +#define WriteW(addr,value) *(uint16*)(addr)=value +#define ReadL(address) ((*(uint16*)(address))<<16)|(*(uint16*)(address+2)) +#define WriteL(address,value) WriteW(address + 2, value); WriteW(address, value>> 16) +#define ReadSL(addr) (*(uint16*)(addr))|((*(uint16*)(addr+2))<<16) +#else +#define ReadB(address) *((int8 *) (address)) +#define WriteB(address,value) *((int8 *) (address)) = (value) +//#define ReadW(addr) ((*(uint16 *)(addr) << 8) | (*(uint16 *)(addr) >> 8)) +//#define WriteW(addr,value) *((int16 *)(addr)) = ((((uint16)(value)) << 8) | (((uint16)(value)) >> 8)) +#define ReadW(addr) *(uint16*)(addr) +#define WriteW(addr,value) *(uint16*)(addr)=value +//#define ReadL(address) ((uint16) ReadW(address) << 16) | (uint16) ReadW((address) + 2) +//#define WriteL(address,value) WriteW((address) + 2, value); WriteW(address, (value) >> 16) +#define ReadL(addr) *(uint32*)(addr) +#define WriteL(addr,value) *(uint32*)(addr)=value +//#define ReadSL(addr) ((uint16)ReadW(addr))|((((uint16)ReadW(addr+2)))<<16) +#define ReadSL(addr) ((uint16)ReadW(addr+2))|((((uint16)ReadW(addr)))<<16) +#endif + +int MemInit(void); +void MemQuit(void); +void MemClean(void); +void MemReInit(void); + +extern unsigned short int TosVersion; +extern short TosCountry; +void TOS_FixRom(uint8 *TosAddress); diff --git a/MCUME_esp32/espcastaway/main/sound.cpp b/MCUME_esp32/espcastaway/main/sound.cpp new file mode 100644 index 0000000..2c76bc0 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/sound.cpp @@ -0,0 +1,493 @@ +#ifndef NO_SOUND + +#include +#include +#include + +#include "config.h" +#include "st.h" +#include "mem.h" +#include "m68k_intrf.h" + +#include "dcastaway.h" +#include "sound.h" + +#define LONGLONG long long + +#define ENVELOPE_PERIOD(Fine,Coarse) (((unsigned long)Coarse)<<8) + (unsigned long)Fine +#define NOISE_PERIOD(Freq) ((((unsigned long)Freq)&0x1f)<<11) +#define TONE_PERIOD(Fine,Coarse) ((((unsigned long)Coarse)&0x0f)<<8) + (unsigned long)Fine +#define MIXTABLE_SIZE (256*8) /* Large table, so don't overflow */ +#define TONEFREQ_SHIFT 28 /* 4.28 fixed point */ +#define NOISEFREQ_SHIFT 28 /* 4.28 fixed point */ +#define ENVFREQ_SHIFT 16 /* 16.16 fixed */ + +#define SAMPLES_BUFFER_SIZE 1024 +/* Number of generated samples per frame (eg. 44Khz=882) : */ +#define SAMPLES_PER_FRAME ((SOUND_FREQ+35)/50) +/* Frequency of generated samples: */ +#define SAMPLES_FREQ (SOUND_FREQ) +#define YM_FREQ (2000000/SAMPLES_FREQ) /* YM Frequency 2Mhz */ + +/* Original wave samples */ +/* Shape x Length(repeat 3rd/4th entries) */ +#include "tab_EnvelopeShapeValues.h" +//static const int EnvelopeShapeValues[16*1024] = { 1,2 }; +/* Use table to convert from (A+B+C) to clipped 'unsigned char' for sound buffer */ +/* -ve and +ve range */ +#include "tab_MixTable.h" +//static const char MixTable[MIXTABLE_SIZE] = { 1,2 }; +static const char *pMixTable = &MixTable[MIXTABLE_SIZE/2]; /* Signed index into above */ +/* LogTable */ +#include "tab_LogTable.h" +//static const int LogTable[256] = { 1,2 }; +#include "tab_LogTable16.h" +//static const int LogTable16[16] = { 1,2 }; +static const int *pEnvelopeLogTable = &LogTable[128]; + +/* Current sample for this time period */ +static int Envelope[SAMPLES_BUFFER_SIZE]; +static int Noise[SAMPLES_BUFFER_SIZE]; +char MixBuffer[MIXBUFFER_SIZE]; + + + +/* Frequency and time period samples */ +static unsigned long ChannelFreq[3], EnvelopeFreq, NoiseFreq; /* Current frequency of each channel A,B,C,Envelope and Noise */ +static int ChannelAmpDecayTime[3]; /* Store counter to show if amplitude is changed to generate 'samples' */ +/* Output channel data */ +static int Channel_A_Buffer[SAMPLES_BUFFER_SIZE],Channel_B_Buffer[SAMPLES_BUFFER_SIZE],Channel_C_Buffer[SAMPLES_BUFFER_SIZE]; +static int ActiveSndBufIdx; /* Current working index into above mix buffer */ +static int nSamplesToGenerate; /* How many samples are needed for this time-frame */ + +/* global values */ +bool bWriteEnvelopeFreq; /* Did write to register '13' - causes frequency reset */ +bool bWriteChannelAAmp, bWriteChannelBAmp, bWriteChannelCAmp; /* Did write to amplitude registers? */ +bool bEnvelopeFreqFlag; /* As above, but cleared each frame for YM saving */ +/* Buffer to store circular samples */ +int nGeneratedSamples; /* Generated samples since audio buffer update */ +int SoundCycles; + + +/*-----------------------------------------------------------------------*/ +/* Envelope shape table */ +typedef struct +{ + int WaveStart[4], WaveDelta[4]; +} ENVSHAPE; + + +/* Square wave look up table */ +static const int SquareWave[16] = { 127,127,127,127,127,127,127,127, -128,-128,-128,-128,-128,-128,-128,-128 }; + + +static long RandomNum; + +static __inline__ long Misc_NextLongRand(long Seed) +{ + unsigned long Lo, Hi; + + Lo = 16807 * (long)(Seed & 0xffff); + Hi = 16807 * (long)((unsigned long)Seed >> 16); + Lo += (Hi & 0x7fff) << 16; + if (Lo > 2147483647L) { + Lo &= 2147483647L; + ++Lo; + } + Lo += Hi >> 15; + if (Lo > 2147483647L) { + Lo &= 2147483647L; + ++Lo; + } + return((long)Lo); +} + +static __inline__ long Misc_GetRandom(void) +{ + RandomNum = Misc_NextLongRand(RandomNum); + if (!RandomNum) + { + RandomNum++; + return 0; + } + return(RandomNum); +} + + +/*-----------------------------------------------------------------------*/ +/* + Init sound tables and envelopes +*/ +void Sound_Init(void) +{ + Sound_Reset(); +} + + +/*-----------------------------------------------------------------------*/ +/* + Reset the sound emulation +*/ +void Sound_Reset(void) +{ + int i; + + Sound_ClearMixBuffer(); /* Clear buffer */ + + /* Clear cycle counts, buffer index and register '13' flags */ + SoundCycles = 0; + bEnvelopeFreqFlag = FALSE; + bWriteEnvelopeFreq = FALSE; + bWriteChannelAAmp = bWriteChannelBAmp = bWriteChannelCAmp = FALSE; + + /* Lock audio system before accessing variables that are also use by the callback function! */ + Audio_Lock(); + CompleteSndBufIdx = 0; + ActiveSndBufIdx = (SOUND_BUFFER_SIZE + SAMPLES_PER_FRAME) % MIXBUFFER_SIZE; + nGeneratedSamples = 0; + Audio_Unlock(); + + /* Clear frequency counter */ + for(i=0; i<3; i++) + { + ChannelFreq[i] = + ChannelAmpDecayTime[i] = 0; + } + EnvelopeFreq = NoiseFreq = 0; +} + + +/*-----------------------------------------------------------------------*/ +/* + Clear mixer buffer, where samples are stored ready to pass to sound player +*/ +void Sound_ClearMixBuffer(void) +{ + Audio_Lock(); + + Memory_Clear(MixBuffer, MIXBUFFER_SIZE); /* Clear buffer */ + + Audio_Unlock(); +} + + +/*-----------------------------------------------------------------------*/ +/* + Find how many samples to generate and store in 'nSamplesToGenerate' + Also update 'SoundCycles' to store how many we actually did so generates set amount each frame +*/ +static void Sound_SetSamplesPassed(void) +{ + int nSampleCycles; + int nSamplesPerFrame; + int Dec=1; + + /* Check how many cycles have passed, as we use this to help find out if we are playing sample data */ + + /* First, add decay to channel amplitude variables */ + if (SoundCycles>(CYCLES_PER_FRAME/4)) + Dec = 16; /* Been long time between sound writes, must be normal tone sound */ + + if (!bWriteChannelAAmp) /* Not written to amplitude, decay value */ + { + ChannelAmpDecayTime[0]-=Dec; + if (ChannelAmpDecayTime[0]<0) ChannelAmpDecayTime[0] = 0; + } + if (!bWriteChannelBAmp) + { + ChannelAmpDecayTime[1]-=Dec; + if (ChannelAmpDecayTime[1]<0) ChannelAmpDecayTime[1] = 0; + } + if (!bWriteChannelCAmp) + { + ChannelAmpDecayTime[2]-=Dec; + if (ChannelAmpDecayTime[2]<0) ChannelAmpDecayTime[2] = 0; + } + + /* 160256 cycles per VBL, 44Khz = 882 samples per VBL */ + /* 882/160256 samples per clock cycle */ + nSamplesPerFrame = SAMPLES_PER_FRAME; +#if 0 /* Use floats for calculation */ + nSamplesToGenerate = (int)( (float)SoundCycles * ((float)nSamplesPerFrame/(float)CYCLES_PER_FRAME) ); + if (nSamplesToGenerate > nSamplesPerFrame) + nSamplesToGenerate = nSamplesPerFrame; + + nSampleCycles = (int)( (float)nSamplesToGenerate / ((float)nSamplesPerFrame/(float)CYCLES_PER_FRAME) ); + SoundCycles -= nSampleCycles; +#else /* Use integers for calculation - both of these calculations should fit into 32-bit int */ + nSamplesToGenerate = SoundCycles * nSamplesPerFrame / CYCLES_PER_FRAME; +//printf("nSamplesToGenerate=%i , SoundCycles=%i\n",nSamplesToGenerate,SoundCycles); + if (nSamplesToGenerate > nSamplesPerFrame) + nSamplesToGenerate = nSamplesPerFrame; + + nSampleCycles = nSamplesToGenerate * CYCLES_PER_FRAME / nSamplesPerFrame; + SoundCycles -= nSampleCycles; +#endif +} + + +/*-----------------------------------------------------------------------*/ +/* + Generate envelope wave for this time-frame +*/ +static void Sound_GenerateEnvelope(unsigned char EnvShape, unsigned char Fine, unsigned char Coarse) +{ + const int *pEnvelopeValues; + unsigned long EnvelopePeriod,EnvelopeFreqDelta; + int i; + + /* Find envelope details */ + if (bWriteEnvelopeFreq) + EnvelopeFreq = 0; + pEnvelopeValues = &EnvelopeShapeValues[ (EnvShape&0x0f)*1024 ]; /* Envelope shape values */ + EnvelopePeriod = ENVELOPE_PERIOD((unsigned long)Fine,(unsigned long)Coarse); + + if (EnvelopePeriod==0) /* Handle div by zero */ + EnvelopeFreqDelta = 0; + else + EnvelopeFreqDelta = ((LONGLONG)YM_FREQ<>ENVFREQ_SHIFT]; /* Store envelope wave, already applied 'log' function */ + EnvelopeFreq += EnvelopeFreqDelta; + if (EnvelopeFreq&0xfe000000) + EnvelopeFreq = 0x02000000 | (EnvelopeFreq&0x01ffffff); /* Keep in range 512-1024 once past 511! */ + } +} + + +/*-----------------------------------------------------------------------*/ +/* + Generate nosie for this time-frame +*/ +static void Sound_GenerateNoise(unsigned char MixerControl, unsigned char NoiseGen) +{ + int NoiseValue; + unsigned long NoisePeriod,NoiseFreqDelta; + int i; + + NoisePeriod = NOISE_PERIOD((unsigned long)NoiseGen); + + if (NoisePeriod==0) /* Handle div by zero */ + NoiseFreqDelta = 0; + else + NoiseFreqDelta = (((LONGLONG)YM_FREQ)<>NOISEFREQ_SHIFT]<=0) /* Add to square wave at given frequency */ + NoiseValue = -NoiseValue; + + Noise[i] = NoiseValue; + NoiseFreq += NoiseFreqDelta; + } +} + + +/*-----------------------------------------------------------------------*/ +/* + Generate channel of samples for this time-frame +*/ +static void Sound_GenerateChannel(int *pBuffer, unsigned char ToneFine, unsigned char ToneCoarse,unsigned char Amplitude,unsigned char MixerControl,unsigned long *pChannelFreq,int MixMask) +{ + int *pNoise = Noise, *pEnvelope = Envelope; + unsigned long ToneFreq=*pChannelFreq; + unsigned long TonePeriod; + unsigned long ToneFreqDelta; + int i,Amp,Mix; + int ToneOutput,NoiseOutput,MixerOutput,EnvelopeOutput,AmplitudeOutput; + + TonePeriod = TONE_PERIOD((unsigned long)ToneFine,(unsigned long)ToneCoarse); + /* Find frequency of channel */ + if (TonePeriod==0) + ToneFreqDelta = 0; /* Handle div by zero */ + else + ToneFreqDelta = (((LONGLONG)YM_FREQ)<>MixMask)&9; /* Read I/O Mixer */ + + /* Check if we are trying to play a 'sample' - we need to up the volume on these as they tend to be rather quiet */ + if ((Amplitude&0x10)==0) /* Fixed level amplitude? */ + { + ChannelAmpDecayTime[MixMask]++; /* Increment counter to find out if we are playing samples... */ + if (ChannelAmpDecayTime[MixMask]>16) + ChannelAmpDecayTime[MixMask] = 16; /* And limit */ + } + + for(i=0; i>TONEFREQ_SHIFT]; + + /* Output from Noise Generator(0-255) */ + NoiseOutput = *pNoise++; + /* Output from Mixer(combines Tone+Noise) */ + switch (Mix) { + case 0: /* Has Noise and Tone */ + MixerOutput = NoiseOutput+ToneOutput; + break; + case 1: /* Has Noise */ + MixerOutput = NoiseOutput; + break; + case 8: /* Has Tone */ + MixerOutput = ToneOutput; + break; + + default: /* This is used to emulate samples - should give no output, but ST gives set tone!!?? */ + /* MixerControl gets set to give a continuous tone and then then Amplitude */ + /* of channels A,B and C get changed with all other registers in the PSG */ + /* staying as zero's. This produces the sounds from Quartet, Speech, NoiseTracker etc...! */ + MixerOutput = 127; + } + + EnvelopeOutput = pEnvelopeLogTable[*pEnvelope++]; + + if ((Amplitude&0x10)==0) + { + AmplitudeOutput = Amp; /* Fixed level amplitude */ + + /* As with most emulators, sample playback is always 'quiet'. We check to see if */ + /* the amplitude of a channel is repeatedly changing and when this is detected we */ + /* scale the volume accordingly */ + if (ChannelAmpDecayTime[MixMask]>8) + AmplitudeOutput <<= 1; /* Scale up by a factor of 2 */ + } + else + AmplitudeOutput = EnvelopeOutput; + + *pBuffer++ = (MixerOutput*AmplitudeOutput)>>8; + + ToneFreq+=ToneFreqDelta; + } + + /* Store back incremented frequency, for next call */ + *pChannelFreq = ToneFreq; +} + + +/*-----------------------------------------------------------------------*/ +/* + Generate samples for all channels during this time-frame +*/ +static void Sound_GenerateSamples(void) +{ + int *pChannelA=Channel_A_Buffer, *pChannelB=Channel_B_Buffer, *pChannelC=Channel_C_Buffer; + int i; + + /* Anything to do? */ + if (nSamplesToGenerate>0) + { + /* Generate envelope/noise samples for this time */ + Sound_GenerateEnvelope(psg[PSG_REG_ENV_SHAPE],psg[PSG_REG_ENV_FINE],psg[PSG_REG_ENV_COARSE]); + Sound_GenerateNoise(psg[PSG_REG_MIXER_CONTROL],psg[PSG_REG_NOISE_GENERATOR]); + + /* Generate 3 channels, store to separate buffer so can mix/clip */ + Sound_GenerateChannel(pChannelA,psg[PSG_REG_CHANNEL_A_FINE],psg[PSG_REG_CHANNEL_A_COARSE],psg[PSG_REG_CHANNEL_A_AMP],psg[PSG_REG_MIXER_CONTROL],&ChannelFreq[0],0); + Sound_GenerateChannel(pChannelB,psg[PSG_REG_CHANNEL_B_FINE],psg[PSG_REG_CHANNEL_B_COARSE],psg[PSG_REG_CHANNEL_B_AMP],psg[PSG_REG_MIXER_CONTROL],&ChannelFreq[1],1); + Sound_GenerateChannel(pChannelC,psg[PSG_REG_CHANNEL_C_FINE],psg[PSG_REG_CHANNEL_C_COARSE],psg[PSG_REG_CHANNEL_C_AMP],psg[PSG_REG_MIXER_CONTROL],&ChannelFreq[2],2); + + /* Mix channels together, using table to clip and also convert to 'unsigned char' */ + for(i=0; i= SOUND_BUFFER_SIZE) + return; + + nSamplesToGenerate = SOUND_BUFFER_SIZE - nGeneratedSamples; + + Sound_GenerateSamples(); +} + +void Sound_UpdateFromCallBack16(short *pBuffer, int len) +{ + int *pChannelA=Channel_A_Buffer, *pChannelB=Channel_B_Buffer, *pChannelC=Channel_C_Buffer; + int i; + + nSamplesToGenerate = len; + + /* Generate envelope/noise samples for this time */ + Sound_GenerateEnvelope(psg[PSG_REG_ENV_SHAPE],psg[PSG_REG_ENV_FINE],psg[PSG_REG_ENV_COARSE]); + Sound_GenerateNoise(psg[PSG_REG_MIXER_CONTROL],psg[PSG_REG_NOISE_GENERATOR]); + + /* Generate 3 channels, store to separate buffer so can mix/clip */ + Sound_GenerateChannel(pChannelA,psg[PSG_REG_CHANNEL_A_FINE],psg[PSG_REG_CHANNEL_A_COARSE],psg[PSG_REG_CHANNEL_A_AMP],psg[PSG_REG_MIXER_CONTROL],&ChannelFreq[0],0); + Sound_GenerateChannel(pChannelB,psg[PSG_REG_CHANNEL_B_FINE],psg[PSG_REG_CHANNEL_B_COARSE],psg[PSG_REG_CHANNEL_B_AMP],psg[PSG_REG_MIXER_CONTROL],&ChannelFreq[1],1); + Sound_GenerateChannel(pChannelC,psg[PSG_REG_CHANNEL_C_FINE],psg[PSG_REG_CHANNEL_C_COARSE],psg[PSG_REG_CHANNEL_C_AMP],psg[PSG_REG_MIXER_CONTROL],&ChannelFreq[2],2); + + /* Mix channels together, using table to clip and also convert to 'unsigned char' */ + for(i=0; i +#include +#include + +#include "config.h" + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#define MUSIC_VOLUME 64 +#ifdef DINGOO +#define SOUND_FREQ 16000 +#else +#define SOUND_FREQ 11025 //22050 +#endif + +#define SOUND_BUFFER_SIZE 1024 + +void Sound_Reset(void); +void Sound_ClearMixBuffer(void); +void Audio_EnableAudio(bool bEnable); + +enum +{ + FREQ_11Khz, + FREQ_22Khz, + FREQ_44Khz +}; + +#define MIXBUFFER_SIZE 8192 +#define SCREEN_START_CYCLE 96 /* Cycle first normal pixel appears on */ +#define SCANLINES_PER_FRAME 313 /* Number of scan lines per frame */ +#define CYCLES_PER_LINE 512 /* Cycles per horiztonal line scan */ +#define CYCLES_VBL_IN (SCREEN_START_HBL*CYCLES_PER_LINE) /* ((28+64)*CYCLES_PER_LINE) */ +#define CYCLES_PER_FRAME (SCANLINES_PER_FRAME*CYCLES_PER_LINE) /* Cycles per VBL @ 50fps = 160256 */ +#define CYCLES_PER_SEC (CYCLES_PER_FRAME*50) /* Cycles per second */ +#define CYCLES_ENDLINE (64+320+88+40) /* DE(Display Enable) */ +#define CYCLES_HBL (CYCLES_PER_LINE+96) /* Cycles for first HBL - very inaccurate on ST */ +#define CYCLES_DEBUGGER 3000 /* Check debugger every 'x' cycles */ + +enum { + PSG_REG_CHANNEL_A_FINE, // 0x0000 + PSG_REG_CHANNEL_A_COARSE, // 0x0001 + PSG_REG_CHANNEL_B_FINE, // 0x0010 + PSG_REG_CHANNEL_B_COARSE, // 0x0011 + PSG_REG_CHANNEL_C_FINE, // 0x0100 + PSG_REG_CHANNEL_C_COARSE, // 0x0101 + PSG_REG_NOISE_GENERATOR, // 0x0110 + PSG_REG_MIXER_CONTROL, // 0x0111 + PSG_REG_CHANNEL_A_AMP, // 0x1000 + PSG_REG_CHANNEL_B_AMP, // 0x1001 + PSG_REG_CHANNEL_C_AMP, // 0x1010 + PSG_REG_ENV_FINE, // 0x1011 + PSG_REG_ENV_COARSE, // 0x1100 + PSG_REG_ENV_SHAPE, // 0x1101 + PSG_REG_IO_PORTA, // 0x1110 + PSG_REG_IO_PORTB // 0x1111 +}; + +#define NUM_PSG_SOUND_REGISTERS 14 // Number of register, not including IO ports + +extern bool bSoundWorking; /* Is sound OK */ +extern volatile bool bPlayingBuffer; /* Is playing buffer? */ +extern int OutputAudioFreqIndex; /* Playback rate (11Khz,22Khz or 44Khz) */ +extern int SoundBufferSize; /* Size of sound buffer */ +extern int CompleteSndBufIdx; /* Replay-index into MixBuffer */ + +extern int SoundPlayBackFrequencies[]; + + +extern bool bWriteEnvelopeFreq,bWriteChannelAAmp,bWriteChannelBAmp,bWriteChannelCAmp; +extern bool bEnvelopeFreqFlag; +extern char MixBuffer[MIXBUFFER_SIZE]; +extern int SoundCycles; +extern int nGeneratedSamples; + +static __inline__ int Misc_LimitInt(int Value, int MinRange, int MaxRange) +{ + if (ValueMaxRange) + Value = MaxRange; + + return(Value); +} + +#define Memory_Clear(A,B) (memset(A,0,B)) + + +#define Audio_Lock() +#define Audio_Unlock() + +void Sound_UpdateFromCallBack16(short *pBuffer, int len); + +void Sound_Update_VBL(void); +void Sound_UpdateFromAudioCallBack(void); +void Sound_Init(void); +void Sound_Update(void); +void audio_init(void); +void audio_stop(void); +void audio_init_music(void); +void audio_play_wait(void); +void audio_play_click(void); +void audio_play_file(void); +void audio_play_main(void); +void audio_play_error(void); +void audio_play_goodbye(void); +void audio_play_save(void); + +#else +/* NO SOUND */ +#define Sound_Update_VBL() +#define Sound_Update() +#define audio_init_music() +#define audio_play_wait() +#define audio_play_click() +#define audio_play_file() +#define audio_play_main() +#define audio_play_error() +#define audio_play_goodbye() +#define audio_play_save() +#define audio_init() +#define audio_stop() + +#endif + +#endif diff --git a/MCUME_esp32/espcastaway/main/st.cpp b/MCUME_esp32/espcastaway/main/st.cpp new file mode 100755 index 0000000..150c40f --- /dev/null +++ b/MCUME_esp32/espcastaway/main/st.cpp @@ -0,0 +1,619 @@ +/* +* Castaway +* (C) 1994 - 2002 Martin Doering, Joachim Hoenig +* +* IO.c - ST hardware emulation +* +* This file is distributed under the GPL, version 2 or at your +* option any later version. See doc/license.txt for details. +* +* revision history +* 23.05.2002 JH FAST1.0.1 code import: KR -> ANSI, restructuring +* 09.06.2002 JH Renamed io.c to st.c again (io.h conflicts with system headers) +* 12.06.2002 JH Correct bus error/address error exception stack frame +* 14.06.2002 JH Implemented STOP, shutdown CPU after multiple bus errors. +* Removed inst parameter from CPU opcode functions. +* 20.08.2002 JH Fixed sign bug in DoIORW() and DoIORL() +* 10.09.2002 JH Bugfix: MOVE.L 0xfffa00,d0 and the like should not raise bus error +* 16.09.2002 JH Bugfix: Word access on unmapped I/O address stacked +* two bus error stack frames. Fault address corrected. +* Merged some code from JH_TOS206_patches branch. +* 02.10.2002 JH Eliminated a lot of silly bugs introduced recently. Shame on me. +No more CPU bus errors from blitter.c::bitblt(). +* 10.10.2002 JH Compatibility improvements. +*/ +static char sccsid[] = "$Id: st.c,v 1.14 2002/10/10 19:41:27 jhoenig Exp $"; +#include +#include "config.h" +#include "st.h" +#include "mem.h" +#include "m68k_intrf.h" +#include "sound.h" + +#include "dcastaway.h" + +#ifdef DEBUG +#include +#endif + + +#define VALUE_OPEN 0xff +/* +* startup display mode +*/ +int display_mode = COL4; + +/* +* I/O Registers +*/ +uint8 memconf; + +//Video shifter +uint32 vid_adr; +uint8 vid_baseh, vid_basem; +uint32 vid_mem=0x10000; +uint8 vid_syncmode=2, vid_shiftmode; +int16 vid_col[16]; +int vid_flag; + +uint16 dma_car, dma_scr, dma_sr, dma_mode; +uint8 dma_adrh, dma_adrm, dma_adrl; +uint8 mfp_gpip, mfp_aer, mfp_ddr, mfp_iera, mfp_ierb, mfp_ipra, +mfp_iprb, mfp_isra, mfp_isrb, mfp_imra, mfp_imrb, mfp_ivr, +mfp_tacr, mfp_tbcr, mfp_tcdcr, mfp_scr, mfp_ucr, mfp_rsr, mfp_tsr, mfp_udr; + + +//Mfp delay timer variables +int32 mfp_reg[12]; +#define mfp_tadr mfp_reg[0] +#define mfp_tbdr mfp_reg[1] +#define mfp_tcdr mfp_reg[2] +#define mfp_tddr mfp_reg[3] +#define mfp_acount mfp_reg[4] +#define mfp_bcount mfp_reg[5] +#define mfp_ccount mfp_reg[6] +#define mfp_dcount mfp_reg[7] +#define mfp_ascale mfp_reg[8] +#define mfp_bscale mfp_reg[9] +#define mfp_cscale mfp_reg[10] +#define mfp_dscale mfp_reg[11] + +uint8 acia1_cr, acia1_sr, acia1_dr, acia2_cr, acia2_sr, acia2_dr; + +uint16 blt_halftone[16]; +int16 blt_src_x_inc, blt_src_y_inc; +uint32 blt_src_addr; +int16 blt_end_1, blt_end_2, blt_end_3; +int16 blt_dst_x_inc, blt_dst_y_inc; +uint32 blt_dst_addr; +uint16 blt_x_cnt, blt_y_cnt; +int8 blt_hop, blt_op, blt_status, blt_skew; +int8 blt_ready; + +uint32 psg[26]; +unsigned char sample[10000]; +#define phase0 psg[16] +#define phase1 psg[17] +#define phase2 psg[18] +#define phase3 psg[19] +#define psg_epos psg[20] +#define psgcontrol psg[21] +#define phase4 psg[22] +#define nrand psg[23] +#define sampos psg[24] +#define lastpsg psg[25] + +static int samvol[16]={0,0,0,1,1,1,2,3,5,7,11,17,25,38,57,85}; +static int samvol2[4096]; + +int32 mfpcycletab[16] = {0,80402,32161,20100,6432,5025,3216,1608,1,0,0,0,0,0,0,0}; + +void IOInit(void) +{ + int n,a,b,c; + //Create sample lookup table (4096 entries) + for (a=0; a<16; a++) { + for (b=0; b<16; b++) { + for (c=0; c<16; c++) { + samvol2[(a<<8)+(b<<4)+c]=samvol[a]+samvol[b]+samvol[c]; + } + } + } + //Reset mfp variables + mfp_tadr=256<<20; mfp_tbdr=256<<20; mfp_tcdr=256<<20; mfp_tddr=256<<20; + mfp_tacr=0; mfp_tbcr=0; mfp_tcdcr=0; + mfp_acount=256<<20; mfp_bcount=256<<20; mfp_ccount=256<<20; mfp_dcount=256<<20; + mfp_ascale=0; mfp_bscale=0; mfp_cscale=0; mfp_dscale=0; + for (n=0; n<24; n++) psg[n]=0; + nrand=1; + //Other stuff + vid_baseh = 0; + vid_basem = 0; + vid_shiftmode = display_mode; + dma_sr = 1; /* DMA status ready */ + if (display_mode == MONO) { + mfp_gpip = 0x39; /* no lpr, no blt, no interrupt, monochrome */ + } else { + mfp_gpip = 0xb9; /* no lpr, no blt, no interrupt, color */ + } +#ifdef sun + act.sa_handler = Sigbus; + (void) sigaction (SIGBUS, &act, &oldsigbus); +#endif +#ifdef USE_MMAP + act.sa_handler = Sigsegv; + (void) sigaction (SIGSEGV, &act, &oldsigsegv); +#endif +} + +static void update_psg(uint8 value) { +#ifndef NO_SOUND + Sound_Update(); +#endif + //Update psg register + psg[psgcontrol]=value; + + switch(psgcontrol) + { + case 13: +#ifndef NO_SOUND + bEnvelopeFreqFlag = 1; + bWriteEnvelopeFreq = 1; +#endif + break; + case 12: + psg_epos=0; + break; + case 8: +#ifndef NO_SOUND + bWriteChannelAAmp= 1; +#endif + break; + case 9: +#ifndef NO_SOUND + bWriteChannelBAmp= 1; +#endif + break; + case 10: +#ifndef NO_SOUND + bWriteChannelCAmp= 1; +#endif + break; + } +} + +void DoIOWB(uint32 address, uint8 value) +{ + address&=0x7fff; + + //Video and dma emu + if (address<0x800) { + switch (address) { + case MEM_CONF&0x7fff: + memconf = value; + break; + case VID_BASEH&0x7fff: + vid_baseh = value; + vid_mem = (vid_baseh<<16)+(vid_basem<<8); + printf("vmem %lu\n",vid_mem); + break; + case VID_BASEM&0x7fff: + vid_basem = value; + vid_mem = (vid_baseh<<16)+(vid_basem<<8); + printf("vmem %lu\n",vid_mem); + break; + case VID_SYNCMODE&0x7fff: + vid_syncmode = value; + maybe_border++; + break; + case VID_SHIFTMODE&0x7fff: + vid_shiftmode = value; + vid_flag=1; + break; + case DMA_ADRH&0x7fff: + dma_adrh = value; + break; + case DMA_ADRM&0x7fff: + dma_adrm = value; + break; + case DMA_ADRL&0x7fff: + dma_adrl = value; + break; + } + return; + } + + //Sound emu + if (address<0x900) { +#if defined(USE_FAME_CORE) && defined(USE_MOVEM_FAME_PATCH) + static unsigned back_cycles=0; + static unsigned back_value=0; + static unsigned back_ctrl=0; + static unsigned new_value=0; +#endif + if (address<0x804) + waitstate+=1; + address&=3; + if (address==0) { + psgcontrol=value; //&15; +#if defined(USE_FAME_CORE) && defined(USE_MOVEM_FAME_PATCH) + if ((M68KCONTEXT.cycles_counter+IO_CYCLE)==back_cycles) { + psg[back_ctrl]=back_value; + update_psg(new_value); + } +#endif + }else if (address==2 && psgcontrol<16) { +#if defined(USE_FAME_CORE) && defined(USE_MOVEM_FAME_PATCH) + back_ctrl=psgcontrol; + back_value=psg[psgcontrol]; + new_value=value; +#endif + update_psg(value); + } +#if defined(USE_FAME_CORE) && defined(USE_MOVEM_FAME_PATCH) + back_cycles=IO_CYCLE+M68KCONTEXT.cycles_counter; +#endif + return; + } + + //Bus error? + if (address<0xb00) { + ExceptionGroup0(BUSERR, address|0xff8000, 0); + return; + } + + //MFP emu + if (address<0x7c00) { + waitstate+=4; + switch(address) { + case MFP_AER&0x7fff: + mfp_aer = value; + break; + case MFP_DDR&0x7fff: + mfp_ddr = value; + break; + case MFP_IERA&0x7fff: + mfp_iera = value; + mfp_ipra &= mfp_iera; + break; + case MFP_IERB&0x7fff: + mfp_ierb = value; + mfp_iprb &= mfp_ierb; + break; + case MFP_IPRA&0x7fff: + mfp_ipra &= value; + break; + case MFP_IPRB&0x7fff: + mfp_iprb &= value; + break; + case MFP_ISRA&0x7fff: + mfp_isra &= value; +#ifndef USE_FAME_CORE + recalc_int = 1; +#endif + break; + case MFP_ISRB&0x7fff: + mfp_isrb &= value; +#ifndef USE_FAME_CORE + recalc_int = 1; +#endif + break; + case MFP_IMRA&0x7fff: + mfp_imra = value; +#ifndef USE_FAME_CORE + recalc_int = 1; +#endif + break; + case MFP_IMRB&0x7fff: + mfp_imrb = value; +#ifndef USE_FAME_CORE + recalc_int = 1; +#endif + break; + case MFP_IVR&0x7fff: + mfp_ivr = value; + break; + case MFP_TACR&0x7fff: + mfp_tacr = value&15; +#if defined(USE_FAME_CORE) && defined(USE_SHORT_SLICE) + if (mfp_ascale) + m68k_stop_emulating(); +#endif + mfp_ascale = mfpcycletab[mfp_tacr]; + break; + case MFP_TBCR&0x7fff: + mfp_tbcr = value&15; +#if defined(USE_FAME_CORE) && defined(USE_SHORT_SLICE) + if (mfp_bscale) + m68k_stop_emulating(); +#endif + mfp_bscale = mfpcycletab[mfp_tbcr]; + break; + case MFP_TCDCR&0x7fff: + mfp_tcdcr = value&0x77; +#if defined(USE_FAME_CORE) && defined(USE_SHORT_SLICE) + if (mfp_cscale || mfp_dscale) + m68k_stop_emulating(); +#endif + mfp_cscale = mfpcycletab[mfp_tcdcr>>4]; + mfp_dscale = mfpcycletab[mfp_tcdcr&7]; + break; + case MFP_TADR&0x7fff: + if (value==0) mfp_tadr=256<<20; else mfp_tadr=value<<20; + if (mfp_ascale==0) mfp_acount=mfp_tadr; + break; + case MFP_TBDR&0x7fff: + if (value==0) mfp_tbdr=256<<20; else mfp_tbdr=value<<20; + if (mfp_bscale==0) mfp_bcount=mfp_tbdr; + break; + case MFP_TCDR&0x7fff: + if (value==0) mfp_tcdr=256<<20; else mfp_tcdr=value<<20; + if (mfp_cscale==0) mfp_ccount=mfp_tcdr; + break; + case MFP_TDDR&0x7fff: + if (value==0) mfp_tddr=256<<20; else mfp_tddr=value<<20; + if (mfp_dscale==0) mfp_dcount=mfp_tddr; + break; + case MFP_SCR&0x7fff: + mfp_scr = value; + break; + case MFP_UCR&0x7fff: + mfp_ucr = value; + break; + case MFP_RSR&0x7fff: + mfp_rsr = value; + break; + case MFP_TSR&0x7fff: + mfp_tsr = value; + break; + case MFP_UDR&0x7fff: + mfp_udr = value; + break; + } + return; + } + + switch(address) { + case ACIA1_SR&0x7fff: + waitstate+=8; + acia1_cr = value; + break; + case ACIA1_DR&0x7fff: + waitstate+=8; + IkbdRecv (value); + break; + case ACIA2_SR&0x7fff: + waitstate+=8; + acia2_cr = value; + break; + case ACIA2_DR&0x7fff: + waitstate+=8; + break; + } + +} + +void DoIOWW(uint32 address, uint16 value) +{ + if (address >= VID_COL0 && address <= VID_COL15) { + vid_col[(address & 0x1f) >> 1] = value&0x777; + vid_flag = 1; + return; + } + else + switch (address) { + case DMA_MODE: + dma_mode = value; + break; + case DMA_CAR: + waitstate+=4; + if (dma_mode & 0x10) dma_scr = value; + else if (dma_mode & 0x8) dma_car = value; + else { + switch (dma_mode & 0x6) { + case 0: + fdc_command = value; + FDCCommand (); + break; + case 2: + fdc_track = value; + break; + case 4: + fdc_sector = value; + break; + case 6: + fdc_data = value; + break; + } + } + break; + default: + DoIOWB(address, value>>8); + DoIOWB(address+1, value); + break; + } +} + +void DoIOWL(uint32 address, uint32 value) +{ + DoIOWW(address, value>>16); + DoIOWW(address+2, value); +} + +static __inline__ void calculate_vid_adr(void) +{ + unsigned yet=(vid_cycle[cyclenext-IO_CYCLE]-vid_adr_cycleyet)&(~3); + vid_adr+=yet; + vid_adr_cycleyet+=yet; +} + +uint8 DoIORB(uint32 address) +{ + address&=0x7fff; + + //Video and dma emu + if (address<0x800) { + switch (address) { + case MEM_CONF&0x7fff: + return memconf; + case VID_BASEH&0x7fff: + return vid_baseh; + case VID_BASEM&0x7fff: + return vid_basem; + case VID_ADRH&0x7fff: + calculate_vid_adr(); + return (unsigned char)(vid_adr>>16); + case VID_ADRM&0x7fff: + calculate_vid_adr(); + return (unsigned char)(vid_adr>>8); + case VID_ADRL&0x7fff: + calculate_vid_adr(); + return (unsigned char)(vid_adr); + case VID_SYNCMODE&0x7fff: + return vid_syncmode; + case VID_LINEWIDTH&0x7fff: + return 0xff; + case VID_SHIFTMODE&0x7fff: + return vid_shiftmode; + case DMA_ADRH&0x7fff: + return dma_adrh; + case DMA_ADRM&0x7fff: + return dma_adrm; + case DMA_ADRL&0x7fff: + return dma_adrl; + } + return VALUE_OPEN; + } + + //Sound emu + if (address<0x900) { + address&=3; + if (!address) + { + waitstate+=4; + if (psgcontrol>=16) return 0xff; + return psg[psgcontrol]; + } + else if (address<4) + waitstate++; + return VALUE_OPEN; + } + + //Bus error? + if (address<0xb00) { + ExceptionGroup0(BUSERR, address|0xff8000, 0); + return VALUE_OPEN; + } + + //MFP emu + if (address<0x7c00) { + waitstate+=4; + switch(address) { + case MFP_GPIP&0x7fff: + return mfp_gpip; + case MFP_AER&0x7fff: + return mfp_aer; + case MFP_DDR&0x7fff: + return mfp_ddr; + case MFP_IERA&0x7fff: + return mfp_iera; + case MFP_IERB&0x7fff: + return mfp_ierb; + case MFP_IPRA&0x7fff: + return mfp_ipra; + case MFP_IPRB&0x7fff: + return mfp_iprb; + case MFP_ISRA&0x7fff: + return mfp_isra; + case MFP_ISRB&0x7fff: + return mfp_isrb; + case MFP_IMRA&0x7fff: + return mfp_imra; + case MFP_IMRB&0x7fff: + return mfp_imrb; + case MFP_IVR&0x7fff: + return mfp_ivr; + case MFP_TACR&0x7fff: + return mfp_tacr; + case MFP_TBCR&0x7fff: + return mfp_tbcr; + case MFP_TCDCR&0x7fff: + return mfp_tcdcr; + case MFP_TADR&0x7fff: + return (mfp_acount+0xfffff)>>20; + case MFP_TBDR&0x7fff: + return (mfp_bcount+0xfffff)>>20; + case MFP_TCDR&0x7fff: + return (mfp_ccount+0xfffff)>>20; + case MFP_TDDR&0x7fff: + return (mfp_dcount+0xfffff)>>20; + case MFP_SCR&0x7fff: + return mfp_scr; + case MFP_UCR&0x7fff: + return mfp_ucr; + case MFP_RSR&0x7fff: + return mfp_rsr; + case MFP_TSR&0x7fff: + return mfp_tsr; + case MFP_UDR&0x7fff: + return mfp_udr; + } + return VALUE_OPEN; + } + + //Acia emu + switch(address) { + case ACIA1_SR&0x7fff: + waitstate+=8; + return 2 | acia1_sr; + case ACIA1_DR&0x7fff: + waitstate+=8; + if (!(acia1_cr & 0x20)) {acia1_sr&=0x7e; mfp_gpip|=0x10;} + return acia1_dr; + case ACIA2_SR&0x7fff: + waitstate+=8; + return 2; + case ACIA2_DR&0x7fff: + waitstate+=8; + return 1; + } + return VALUE_OPEN; + +} + +uint16 DoIORW(uint32 address) +{ + if (address >= VID_COL0 && address <= VID_COL15) { + return vid_col[(address & 0x1f) >> 1]; + } + switch (address) { + case DMA_SR: + return dma_sr; + case DMA_CAR: + waitstate+=4; + if (dma_mode & 0x10) return dma_scr; + else if (dma_mode & 0x8) return dma_car; + else { + switch (dma_mode & 0x6) { + case 0: + if (!fdc_int) mfp_gpip |= 0x20; + return fdc_status; + case 2: + return fdc_track; + case 4: + return fdc_sector; + case 6: + return fdc_data; + } + return 0; + } + default: + return (((uint32)DoIORB(address))<<8)+DoIORB(address+1); + } +} + +uint32 DoIORL(uint32 address) +{ + return (((uint32)DoIORW(address))<<16)+DoIORW(address+2); +} + diff --git a/MCUME_esp32/espcastaway/main/st.h b/MCUME_esp32/espcastaway/main/st.h new file mode 100755 index 0000000..9c9dbb5 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/st.h @@ -0,0 +1,306 @@ + /* + * Castaway + * (C) 1994 - 2002 Martin Doering, Joachim Hoenig + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ +#ifndef STH +#define STH + +#define MAX_DISC_SIZE 1050*1024 + + +/* + * I/O register addresses + */ +#define MEM_CONF 0xff8001 + +#define VID_BASEH 0xff8201 +#define VID_BASEM 0xff8203 +#define VID_ADRH 0xff8205 +#define VID_ADRM 0xff8207 +#define VID_ADRL 0xff8209 +#define VID_SYNCMODE 0xff820a +#define VID_BASEL 0xff820d +#define VID_LINEWIDTH 0xff820f +#define VID_COL0 0xff8240 +#define VID_COL1 0xff8242 +#define VID_COL2 0xff8244 +#define VID_COL3 0xff8246 +#define VID_COL4 0xff8248 +#define VID_COL5 0xff824a +#define VID_COL6 0xff824c +#define VID_COL7 0xff824e +#define VID_COL8 0xff8250 +#define VID_COL9 0xff8252 +#define VID_COL10 0xff8254 +#define VID_COL11 0xff8256 +#define VID_COL12 0xff8258 +#define VID_COL13 0xff825a +#define VID_COL14 0xff825c +#define VID_COL15 0xff825e +#define VID_SHIFTMODE 0xff8260 + +#define DMA_CAR 0xff8604 +#define DMA_SCR 0xff8604 +#define DMA_SR 0xff8606 +#define DMA_MODE 0xff8606 +#define DMA_ADRH 0xff8609 +#define DMA_ADRM 0xff860b +#define DMA_ADRL 0xff860d + +#define SND_RS 0xff8800 +#define SND_WD 0xff8802 + +#define BLT_HFT 0xff8a00 +#define BLT_SXINC 0xff8a20 +#define BLT_SYINC 0xff8a22 +#define BLT_SADR 0xff8a24 +#define BLT_END1 0xff8a28 +#define BLT_END2 0xff8a2a +#define BLT_END3 0xff8a2c +#define BLT_DXINC 0xff8a2e +#define BLT_DYINC 0xff8a30 +#define BLT_DADR 0xff8a32 +#define BLT_XCNT 0xff8a36 +#define BLT_YCNT 0xff8a38 +#define BLT_HOP 0xff8a3a +#define BLT_OP 0xff8a3b +#define BLT_STAT 0xff8a3c +#define BLT_SKEW 0xff8a3d + +#define MFP_GPIP 0xfffa01 +#define MFP_AER 0xfffa03 +#define MFP_DDR 0xfffa05 +#define MFP_IERA 0xfffa07 +#define MFP_IERB 0xfffa09 +#define MFP_IPRA 0xfffa0b +#define MFP_IPRB 0xfffa0d +#define MFP_ISRA 0xfffa0f +#define MFP_ISRB 0xfffa11 +#define MFP_IMRA 0xfffa13 +#define MFP_IMRB 0xfffa15 +#define MFP_IVR 0xfffa17 +#define MFP_TACR 0xfffa19 +#define MFP_TBCR 0xfffa1b +#define MFP_TCDCR 0xfffa1d +#define MFP_TADR 0xfffa1f +#define MFP_TBDR 0xfffa21 +#define MFP_TCDR 0xfffa23 +#define MFP_TDDR 0xfffa25 +#define MFP_SCR 0xfffa27 +#define MFP_UCR 0xfffa29 +#define MFP_RSR 0xfffa2b +#define MFP_TSR 0xfffa2d +#define MFP_UDR 0xfffa2f + +#define ACIA1_SR 0xfffc00 +#define ACIA1_DR 0xfffc02 + +#define ACIA2_SR 0xfffc04 +#define ACIA2_DR 0xfffc06 + +#define RTC_SECL 0xfffc21 +#define RTC_SECH 0xfffc23 +#define RTC_MINL 0xfffc25 +#define RTC_MINH 0xfffc27 +#define RTC_HRSL 0xfffc29 +#define RTC_HRSH 0xfffc2b +#define RTC_DAY 0xfffc2d +#define RTC_DAYL 0xfffc2f +#define RTC_DAYH 0xfffc31 +#define RTC_MONL 0xfffc33 +#define RTC_MONH 0xfffc35 +#define RTC_YRL 0xfffc37 +#define RTC_YRH 0xfffc39 +#define RTC_RES1 0xfffc3b +#define RTC_RES2 0xfffc3d +#define RTC_RES3 0xfffc3f + +#define IBS 32 +#define OBS 64 + +/* + * ROM/Cartridge file names + */ +extern char cartridge[80], rom[80]; +/* + * I/O register values + */ +extern int8 *membase; +extern int8 *rombase; +extern uint8 memconf; +extern uint8 mfp_gpip, mfp_aer, mfp_ddr, mfp_iera, mfp_ierb, mfp_ipra, mfp_iprb, + mfp_isra, mfp_isrb, mfp_imra, mfp_imrb, mfp_ivr, mfp_tacr, + mfp_tbcr, mfp_tcdcr, mfp_scr, mfp_ucr, mfp_rsr, mfp_tsr, mfp_udr; + +//Mfp delay timer variables +extern int32 mfp_reg[12]; +#define mfp_tadr mfp_reg[0] +#define mfp_tbdr mfp_reg[1] +#define mfp_tcdr mfp_reg[2] +#define mfp_tddr mfp_reg[3] +#define mfp_acount mfp_reg[4] +#define mfp_bcount mfp_reg[5] +#define mfp_ccount mfp_reg[6] +#define mfp_dcount mfp_reg[7] +#define mfp_ascale mfp_reg[8] +#define mfp_bscale mfp_reg[9] +#define mfp_cscale mfp_reg[10] +#define mfp_dscale mfp_reg[11] + +extern uint8 acia1_cr, acia1_sr, acia1_dr, acia2_cr, acia2_sr, + acia2_dr; + +extern int checkedsample; +extern int checkedsound; +//Video shifter +extern uint32 vid_adr; +extern uint8 vid_baseh, vid_basem; +extern uint32 vid_mem; +extern uint8 vid_syncmode, vid_shiftmode; +extern int16 vid_col[]; +extern int vid_flag; + + +extern uint16 dma_car, dma_scr, dma_sr, dma_mode; +extern uint8 dma_adrh, dma_adrm, dma_adrl; +extern int32 mfpcycletab[16]; + +extern uint32 psg[26]; +extern unsigned char sample[10000]; +#define phase0 psg[16] +#define phase1 psg[17] +#define phase2 psg[18] +#define phase3 psg[19] +#define psg_epos psg[20] +#define psgcontrol psg[21] +#define phase4 psg[22] +#define nrand psg[23] +#define samppos psg[24] +#define lastpsg psg[25] + +/* ikbd.c */ +extern void IkbdLoop(void); +extern void IkbdRecv(uint8); +extern void IkbdSend(uint8); +extern void IkbdWriteBuffer(void); /* write byte IKBD -> ST */ +extern void IkbdKeyPress(unsigned short keysym); /* key press */ +extern void IkbdKeyRelease(unsigned short keysym); /* key release */ +extern void IkbdMousePress(int); /* mouse button press */ +extern void IkbdMouseRelease(int); /* mouse button release */ +extern void IkbdMouseMotion(int x, int y); /* mouse movement */ +//extern void IkbdMouseMotion(int x, int y, int dx, int dy); /* mouse movement */ +extern void joystickevent(int joystate); +extern void IkbdReset(void); + + +/* fdc.c */ +extern unsigned char fdc_data, fdc_track, fdc_sector, + fdc_status, fdc_command, fdc_int; +extern unsigned char disk_ejected[2]; +extern unsigned char disk_changed[2]; +struct Disk { + FILE *file; + char name[80]; + int head; + int sides; + int tracks; + int sectors; + int secsize; + int disksize; +}; +extern struct Disk disk[2]; +extern int FDCInit(int i); +extern void FDCCommand(void); +void FDCeject(int num); +int unzipdisk(unsigned char *RomPath,unsigned char *buf); + +/* blitter.c */ +extern uint16 blt_halftone[16]; +extern int16 blt_src_x_inc, blt_src_y_inc; +extern uint32 blt_src_addr; +extern int16 blt_end_1, blt_end_2, blt_end_3; +extern int16 blt_dst_x_inc, blt_dst_y_inc; +extern uint32 blt_dst_addr; +extern uint16 blt_x_cnt, blt_y_cnt; +extern int8 blt_hop, blt_op, blt_status, blt_skew; + +extern void bitblt(void); + +/* init.c */ +extern int Init(); + +/* main.c */ +extern unsigned ips; + +/* mem.c */ +extern int MemInit(void); +extern void MemTableSet(uint32 base, uint32 size, + void (*setbyte)(uint32, uint8), + void (*setword)(uint32, uint16), + void (*setlong)(uint32, uint32 ), + uint8 (*getbyte)(uint32), + uint16 (*getword)(uint32), + uint32 (*getlong)(uint32) ); + +extern void RamSetB(uint32, uint8); +extern void RamSetW(uint32, uint16); +extern void RamSetL(uint32, uint32 ); +extern uint8 RamGetB(uint32); +extern uint16 RamGetW(uint32); +extern uint32 RamGetL(uint32); +/* + * Video shift modes + */ +#define COL4 0 +#define COL2 1 +#define MONO 2 +extern int display_mode; + +/* + * Read/Write IO Registers (return value != 0 if bus error) + */ +uint8 DoIORB(uint32 address); +uint16 DoIORW(uint32 address); +uint32 DoIORL(uint32 address); +void DoIOWB(uint32 address, uint8 value); +void DoIOWW(uint32 address, uint16 value); +void DoIOWL(uint32 address, uint32 value); + +void IOInit(void); +struct _mouse { + char buttons; /* real buttons */ + char stbuttons; /* buttons as known to st */ + int xscale, yscale; + int xmax, ymax; + int xkcm, ykcm; + int xth, yth; + int x, y; /* real mouse position */ + int stx, sty; /* mouse position st */ + int button_action; + int mode; + int yinv; + int flag; +}; + + +struct _joystick { + int mode; + int rate; + int state0; /* joystick 0 state */ + int state1; /* joystick 1 state */ + int rx, ry, tx, ty, vx, vy; +}; + + +extern struct _mouse mouse; +extern struct _joystick joystick; + +void Ikbd_Reset(void); +void IkbdJoystickChange(int number, uint8 state); +int unzipdisk(unsigned char *RomPath,unsigned char *buf); +void reset_st_video(void); + +#endif diff --git a/MCUME_esp32/espcastaway/main/tab_EnvelopeShapeValues.h b/MCUME_esp32/espcastaway/main/tab_EnvelopeShapeValues.h new file mode 100644 index 0000000..2c14a1c --- /dev/null +++ b/MCUME_esp32/espcastaway/main/tab_EnvelopeShapeValues.h @@ -0,0 +1,1026 @@ +static const int EnvelopeShapeValues[16384] = { +127,126,125,124,123,122,121,120,119,118,117,116,115,114,113,112, +111,110,109,108,107,106,105,104,103,102,101,100,99,98,97,96, +95,94,93,92,91,90,89,88,87,86,85,84,83,82,81,80, +79,78,77,76,75,74,73,72,71,70,69,68,67,66,65,64, +63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48, +47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32, +31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16, +15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0, +-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,-16, +-17,-18,-19,-20,-21,-22,-23,-24,-25,-26,-27,-28,-29,-30,-31,-32, +-33,-34,-35,-36,-37,-38,-39,-40,-41,-42,-43,-44,-45,-46,-47,-48, +-49,-50,-51,-52,-53,-54,-55,-56,-57,-58,-59,-60,-61,-62,-63,-64, +-65,-66,-67,-68,-69,-70,-71,-72,-73,-74,-75,-76,-77,-78,-79,-80, +-81,-82,-83,-84,-85,-86,-87,-88,-89,-90,-91,-92,-93,-94,-95,-96, +-97,-98,-99,-100,-101,-102,-103,-104,-105,-106,-107,-108,-109,-110,-111,-112, +-113,-114,-115,-116,-117,-118,-119,-120,-121,-122,-123,-124,-125,-126,-127,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, +127,126,125,124,123,122,121,120,119,118,117,116,115,114,113,112, +111,110,109,108,107,106,105,104,103,102,101,100,99,98,97,96, +95,94,93,92,91,90,89,88,87,86,85,84,83,82,81,80, +79,78,77,76,75,74,73,72,71,70,69,68,67,66,65,64, +63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48, +47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32, +31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16, +15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0, +-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,-16, +-17,-18,-19,-20,-21,-22,-23,-24,-25,-26,-27,-28,-29,-30,-31,-32, +-33,-34,-35,-36,-37,-38,-39,-40,-41,-42,-43,-44,-45,-46,-47,-48, +-49,-50,-51,-52,-53,-54,-55,-56,-57,-58,-59,-60,-61,-62,-63,-64, +-65,-66,-67,-68,-69,-70,-71,-72,-73,-74,-75,-76,-77,-78,-79,-80, +-81,-82,-83,-84,-85,-86,-87,-88,-89,-90,-91,-92,-93,-94,-95,-96, +-97,-98,-99,-100,-101,-102,-103,-104,-105,-106,-107,-108,-109,-110,-111,-112, +-113,-114,-115,-116,-117,-118,-119,-120,-121,-122,-123,-124,-125,-126,-127,-128, +-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128, 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a/MCUME_esp32/espcastaway/main/tosnonswap/tos12.h b/MCUME_esp32/espcastaway/main/tosnonswap/tos12.h new file mode 100644 index 0000000..d27da27 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/tosnonswap/tos12.h @@ -0,0 +1,12290 @@ +const unsigned char tos[196608] = { +0x60,0x2E,0x01,0x02,0x00,0xFC,0x00,0x30,0x00,0xFC,0x00,0x00,0x00,0x00,0x89,0x00, +0x00,0xFC,0x00,0x30,0x00,0xFE,0xFF,0xF4,0x04,0x22,0x19,0x87,0x00,0x03,0x0E,0x96, +0x00,0x00,0x7E,0x9C,0x00,0x00,0x0E,0x61,0x00,0x00,0x87,0xCE,0x00,0x00,0x00,0x00, +0x46,0xFC,0x27,0x00,0x4E,0x70,0x0C,0xB9,0xFA,0x52,0x23,0x5F,0x00,0xFA,0x00,0x00, +0x66,0x0A,0x4D,0xFA,0x00,0x08,0x4E,0xF9,0x00,0xFA,0x00,0x04,0x4D,0xFA,0x00,0x06, +0x60,0x00,0x06,0x36,0x66,0x0A,0x13,0xF9,0x00,0x00,0x04,0x24,0xFF,0xFF,0x80,0x01, +0x9B,0xCD,0x0C,0xAD,0x31,0x41,0x59,0x26,0x04,0x26,0x66,0x18,0x20,0x2D,0x04,0x2A, +0x4A,0x2D,0x04,0x2A,0x66,0x0E,0x08,0x00,0x00,0x00,0x66,0x08,0x20,0x40,0x4D,0xFA, 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+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +}; diff --git a/MCUME_esp32/espcastaway/main/tossw10.h b/MCUME_esp32/espcastaway/main/tossw10.h new file mode 100755 index 0000000..1c18d5b --- /dev/null +++ b/MCUME_esp32/espcastaway/main/tossw10.h @@ -0,0 +1,12290 @@ +const unsigned char tos[196608] = { +0x1E,0x60,0x00,0x01,0xFC,0x00,0x20,0x00,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x61, +0xFC,0x00,0x20,0x00,0xFE,0x00,0xF4,0xFF,0x06,0x02,0x86,0x19,0x03,0x00,0x46,0x0C, +0xFC,0x46,0x00,0x27,0x70,0x4E,0xB9,0x0C,0x52,0xFA,0x5F,0x23,0xFA,0x00,0x00,0x00, +0x0A,0x66,0xFA,0x4D,0x08,0x00,0xF9,0x4E,0xFA,0x00,0x04,0x00,0xFA,0x4D,0x06,0x00, +0x00,0x60,0x96,0x05,0x0A,0x66,0xF9,0x13,0x00,0x00,0x24,0x04,0xFF,0xFF,0x01,0x80, +0xCD,0x9B,0xAD,0x0C,0x41,0x31,0x26,0x59,0x26,0x04,0x18,0x66,0x2D,0x20,0x2A,0x04, +0x2D,0x4A,0x2A,0x04,0x0E,0x66,0x00,0x08,0x00,0x00,0x08,0x66,0x40,0x20,0xFA,0x4D, +0xE0,0xFF,0xD0,0x4E,0xF9,0x41,0xFF,0xFF,0x00,0x88,0xBC,0x10,0x07,0x00,0x7C,0x11, +0xC0,0x00,0x02,0x00,0xBC,0x10,0x0E,0x00,0x7C,0x11,0x07,0x00,0x02,0x00,0x3A,0x08, +0x00,0x00,0x8B,0xFF,0x10,0x67,0xFA,0x4D,0x06,0x00,0x00,0x60,0x48,0x0C,0xFC,0x13, +0x02,0x00,0xFF,0xFF,0x0A,0x82,0xF9,0x43,0xFF,0xFF,0x40,0x82,0x3C,0x30,0x0F,0x00, +0xFA,0x41,0x4C,0x05,0xD8,0x32,0xC8,0x51,0xFC,0xFF,0xFC,0x13,0x01,0x00,0xFF,0xFF, +0x01,0x82,0xFC,0x13,0x00,0x00,0xFF,0xFF,0x03,0x82,0xCD,0x9B,0x2D,0x1C,0x24,0x04, +0x2D,0x2A,0x2E,0x04,0xFA,0x4D,0x06,0x00,0x00,0x60,0xFE,0x04,0x00,0x67,0xE4,0x00, +0x46,0x42,0xFC,0x13,0x0A,0x00,0xFF,0xFF,0x01,0x80,0x7C,0x30,0x08,0x00,0xF9,0x43, +0x20,0x00,0x08,0x00,0x40,0x42,0xC0,0x30,0xC0,0x32,0x7C,0xD0,0x54,0xFA,0xFC,0xB1, +0x00,0x00,0x00,0x02,0xF0,0x66,0x3C,0x22,0x20,0x00,0x00,0x00,0x4E,0xE4,0x7C,0x30, +0x08,0x02,0xFA,0x4B,0x06,0x00,0x00,0x60,0xAA,0x04,0x20,0x67,0x7C,0x30,0x08,0x04, +0xFA,0x4B,0x06,0x00,0x00,0x60,0x9C,0x04,0x10,0x67,0x7C,0x30,0x08,0x00,0xFA,0x4B, +0x06,0x00,0x00,0x60,0x8E,0x04,0x04,0x66,0x46,0x58,0x46,0x58,0xBC,0x92,0x20,0x00, +0x00,0x00,0xC8,0x67,0xC6,0x13,0xFF,0xFF,0x01,0x80,0x79,0x28,0x00,0x00,0x08,0x00, +0xFA,0x41,0x36,0x00,0xC8,0x23,0x00,0x00,0x08,0x00,0x3C,0x36,0x55,0xFB,0x3C,0x2E, +0x02,0x00,0x00,0x00,0x47,0x20,0x48,0x22,0x00,0x34,0x2A,0x72,0x02,0x33,0x43,0xD4, +0xC9,0x51,0xFA,0xFF,0x48,0x22,0x2A,0x72,0x61,0xB0,0x0C,0x66,0x51,0x42,0x43,0xD0, +0xC9,0x51,0xF6,0xFF,0xC7,0xD1,0xDE,0x60,0xC7,0x91,0x08,0x2A,0xCC,0x23,0x00,0x00, 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new file mode 100755 index 0000000..852e0a7 --- /dev/null +++ b/MCUME_esp32/espcastaway/main/tossw12.h @@ -0,0 +1,12290 @@ +const unsigned char tos[196608] = { +0x2E,0x60,0x02,0x01,0xFC,0x00,0x30,0x00,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x89, +0xFC,0x00,0x30,0x00,0xFE,0x00,0xF4,0xFF,0x22,0x04,0x87,0x19,0x03,0x00,0x96,0x0E, +0x00,0x00,0x9C,0x7E,0x00,0x00,0x61,0x0E,0x00,0x00,0xCE,0x87,0x00,0x00,0x00,0x00, +0xFC,0x46,0x00,0x27,0x70,0x4E,0xB9,0x0C,0x52,0xFA,0x5F,0x23,0xFA,0x00,0x00,0x00, +0x0A,0x66,0xFA,0x4D,0x08,0x00,0xF9,0x4E,0xFA,0x00,0x04,0x00,0xFA,0x4D,0x06,0x00, +0x00,0x60,0x36,0x06,0x0A,0x66,0xF9,0x13,0x00,0x00,0x24,0x04,0xFF,0xFF,0x01,0x80, +0xCD,0x9B,0xAD,0x0C,0x41,0x31,0x26,0x59,0x26,0x04,0x18,0x66,0x2D,0x20,0x2A,0x04, +0x2D,0x4A,0x2A,0x04,0x0E,0x66,0x00,0x08,0x00,0x00,0x08,0x66,0x40,0x20,0xFA,0x4D, +0xE0,0xFF,0xD0,0x4E,0xF9,0x41,0xFF,0xFF,0x00,0x88,0xBC,0x10,0x07,0x00,0x7C,0x11, +0xC0,0x00,0x02,0x00,0xBC,0x10,0x0E,0x00,0x7C,0x11,0x07,0x00,0x02,0x00,0x3A,0x08, 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+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +}; diff --git a/MCUME_esp32/espcastaway/partitions.csv b/MCUME_esp32/espcastaway/partitions.csv new file mode 100755 index 0000000..79c1f89 --- /dev/null +++ b/MCUME_esp32/espcastaway/partitions.csv @@ -0,0 +1,5 @@ +# Name, Type, SubType, Offset, Size +# Note: if you change the phy_init or app partition offset, make sure to change the offset in Kconfig.projbuild +nvs, data, nvs, 0x9000, 0x6000 +phy_init, data, phy, 0xf000, 0x1000 +factory, app, factory, 0x10000, 2M, diff --git a/MCUME_esp32/espcastaway/sdkconfig b/MCUME_esp32/espcastaway/sdkconfig new file mode 100644 index 0000000..cfcca67 --- /dev/null +++ b/MCUME_esp32/espcastaway/sdkconfig @@ -0,0 +1,721 @@ +# +# Automatically generated file; DO NOT EDIT. +# Espressif IoT Development Framework Configuration +# +CONFIG_IDF_TARGET="esp32" + +# +# SDK tool configuration +# +CONFIG_TOOLPREFIX="xtensa-esp32-elf-" +CONFIG_PYTHON="python" +CONFIG_MAKE_WARN_UNDEFINED_VARIABLES=y + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +CONFIG_APP_EXCLUDE_PROJECT_VER_VAR= +CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR= + +# +# Bootloader config +# +CONFIG_LOG_BOOTLOADER_LEVEL_NONE= +CONFIG_LOG_BOOTLOADER_LEVEL_ERROR= +CONFIG_LOG_BOOTLOADER_LEVEL_WARN= +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG= +CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE= +CONFIG_LOG_BOOTLOADER_LEVEL=3 +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V= +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +CONFIG_BOOTLOADER_FACTORY_RESET= +CONFIG_BOOTLOADER_APP_TEST= +CONFIG_BOOTLOADER_WDT_ENABLE=y +CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE= +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +CONFIG_APP_ROLLBACK_ENABLE= + +# +# Security features +# +CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT= +CONFIG_SECURE_BOOT_ENABLED= +CONFIG_FLASH_ENCRYPTION_ENABLED= + +# +# Serial flasher config +# +CONFIG_ESPTOOLPY_PORT="/dev/cu.SLAB_USBtoUART" +CONFIG_ESPTOOLPY_BAUD_115200B=y +CONFIG_ESPTOOLPY_BAUD_230400B= +CONFIG_ESPTOOLPY_BAUD_921600B= +CONFIG_ESPTOOLPY_BAUD_2MB= +CONFIG_ESPTOOLPY_BAUD_OTHER= +CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 +CONFIG_ESPTOOLPY_BAUD=115200 +CONFIG_ESPTOOLPY_COMPRESSED=y +CONFIG_FLASHMODE_QIO= +CONFIG_FLASHMODE_QOUT= +CONFIG_FLASHMODE_DIO=y +CONFIG_FLASHMODE_DOUT= +CONFIG_ESPTOOLPY_FLASHMODE="dio" +CONFIG_ESPTOOLPY_FLASHFREQ_80M= +CONFIG_ESPTOOLPY_FLASHFREQ_40M=y +CONFIG_ESPTOOLPY_FLASHFREQ_26M= +CONFIG_ESPTOOLPY_FLASHFREQ_20M= +CONFIG_ESPTOOLPY_FLASHFREQ="40m" +CONFIG_ESPTOOLPY_FLASHSIZE_1MB= +CONFIG_ESPTOOLPY_FLASHSIZE_2MB= +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +CONFIG_ESPTOOLPY_FLASHSIZE_8MB= +CONFIG_ESPTOOLPY_FLASHSIZE_16MB= +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" +CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y +CONFIG_ESPTOOLPY_BEFORE_RESET=y +CONFIG_ESPTOOLPY_BEFORE_NORESET= +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +CONFIG_ESPTOOLPY_AFTER_NORESET= +CONFIG_ESPTOOLPY_AFTER="hard_reset" +CONFIG_MONITOR_BAUD_9600B= +CONFIG_MONITOR_BAUD_57600B= +CONFIG_MONITOR_BAUD_115200B=y +CONFIG_MONITOR_BAUD_230400B= +CONFIG_MONITOR_BAUD_921600B= +CONFIG_MONITOR_BAUD_2MB= +CONFIG_MONITOR_BAUD_OTHER= +CONFIG_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_MONITOR_BAUD=115200 + +# +# Partition Table +# +CONFIG_PARTITION_TABLE_SINGLE_APP= +CONFIG_PARTITION_TABLE_TWO_OTA= +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y + +# +# Compiler options +# +CONFIG_OPTIMIZATION_LEVEL_DEBUG= +CONFIG_OPTIMIZATION_LEVEL_RELEASE=y +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +CONFIG_OPTIMIZATION_ASSERTIONS_SILENT= +CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED= +CONFIG_CXX_EXCEPTIONS= +CONFIG_STACK_CHECK_NONE=y +CONFIG_STACK_CHECK_NORM= +CONFIG_STACK_CHECK_STRONG= +CONFIG_STACK_CHECK_ALL= +CONFIG_STACK_CHECK= +CONFIG_WARN_WRITE_STRINGS= +CONFIG_DISABLE_GCC8_WARNINGS= + +# +# Component config +# + +# +# Application Level Tracing +# +CONFIG_ESP32_APPTRACE_DEST_TRAX= +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_ENABLE= +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +CONFIG_AWS_IOT_SDK= + +# +# Bluetooth +# +CONFIG_BT_ENABLED= +CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0 +CONFIG_BT_RESERVE_DRAM=0 + +# +# Driver configurations +# + +# +# ADC configuration +# +CONFIG_ADC_FORCE_XPD_FSM= +CONFIG_ADC2_DISABLE_DAC=y + +# +# SPI configuration +# +CONFIG_SPI_MASTER_IN_IRAM= +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +CONFIG_SPI_SLAVE_IN_IRAM= +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y + +# +# eFuse Bit Manager +# +CONFIG_EFUSE_CUSTOM_TABLE= +CONFIG_EFUSE_VIRTUAL= +CONFIG_EFUSE_CODE_SCHEME_COMPAT_NONE= +CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4=y +CONFIG_EFUSE_CODE_SCHEME_COMPAT_REPEAT= +CONFIG_EFUSE_MAX_BLK_LEN=192 + +# +# ESP32-specific +# +CONFIG_IDF_TARGET_ESP32=y +CONFIG_ESP32_DEFAULT_CPU_FREQ_80= +CONFIG_ESP32_DEFAULT_CPU_FREQ_160= +CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y +CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240 +CONFIG_SPIRAM_SUPPORT=y + +# +# SPI RAM config +# +CONFIG_SPIRAM_BOOT_INIT=y +CONFIG_SPIRAM_IGNORE_NOTFOUND= +CONFIG_SPIRAM_USE_MEMMAP= +CONFIG_SPIRAM_USE_CAPS_ALLOC=y +CONFIG_SPIRAM_USE_MALLOC= +CONFIG_SPIRAM_TYPE_AUTO=y +CONFIG_SPIRAM_TYPE_ESPPSRAM32= +CONFIG_SPIRAM_TYPE_ESPPSRAM64= +CONFIG_SPIRAM_SIZE=-1 +CONFIG_SPIRAM_SPEED_40M=y +CONFIG_SPIRAM_MEMTEST=y +CONFIG_SPIRAM_CACHE_WORKAROUND=y +CONFIG_SPIRAM_BANKSWITCH_ENABLE=y +CONFIG_SPIRAM_BANKSWITCH_RESERVE=8 +CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST= +CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY= +CONFIG_PICO_PSRAM_CS_IO=10 +CONFIG_MEMMAP_TRACEMEM= +CONFIG_MEMMAP_TRACEMEM_TWOBANKS= +CONFIG_ESP32_TRAX= +CONFIG_TRACEMEM_RESERVE_DRAM=0x0 +CONFIG_TWO_UNIVERSAL_MAC_ADDRESS= +CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y +CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4 +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +CONFIG_IPC_TASK_STACK_SIZE=1024 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF= +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR= +CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF= +CONFIG_NEWLIB_STDIN_LINE_ENDING_LF= +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +CONFIG_NEWLIB_NANO_FORMAT= +CONFIG_CONSOLE_UART_DEFAULT=y +CONFIG_CONSOLE_UART_CUSTOM= +CONFIG_CONSOLE_UART_NONE= +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ULP_COPROC_ENABLED= +CONFIG_ULP_COPROC_RESERVE_MEM=0 +CONFIG_ESP32_PANIC_PRINT_HALT= +CONFIG_ESP32_PANIC_PRINT_REBOOT=y +CONFIG_ESP32_PANIC_SILENT_REBOOT= +CONFIG_ESP32_PANIC_GDBSTUB= +CONFIG_ESP32_DEBUG_OCDAWARE=y +CONFIG_ESP32_DEBUG_STUBS_ENABLE=y +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_INT_WDT_CHECK_CPU1=y +CONFIG_TASK_WDT=y +CONFIG_TASK_WDT_PANIC= +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +CONFIG_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_0=y +CONFIG_BROWNOUT_DET_LVL_SEL_1= +CONFIG_BROWNOUT_DET_LVL_SEL_2= +CONFIG_BROWNOUT_DET_LVL_SEL_3= +CONFIG_BROWNOUT_DET_LVL_SEL_4= +CONFIG_BROWNOUT_DET_LVL_SEL_5= +CONFIG_BROWNOUT_DET_LVL_SEL_6= +CONFIG_BROWNOUT_DET_LVL_SEL_7= +CONFIG_BROWNOUT_DET_LVL=0 +CONFIG_REDUCE_PHY_TX_POWER=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC= +CONFIG_ESP32_TIME_SYSCALL_USE_FRC1= +CONFIG_ESP32_TIME_SYSCALL_USE_NONE= +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y +CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL= +CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC= +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256= +CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP32_XTAL_FREQ_40=y +CONFIG_ESP32_XTAL_FREQ_26= +CONFIG_ESP32_XTAL_FREQ_AUTO= +CONFIG_ESP32_XTAL_FREQ=40 +CONFIG_DISABLE_BASIC_ROM_CONSOLE= +CONFIG_NO_BLOBS= +CONFIG_ESP_TIMER_PROFILING= +CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS= +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y + +# +# Wi-Fi +# +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER= +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16 +CONFIG_ESP32_WIFI_CSI_ENABLED= +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1= +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP32_WIFI_DEBUG_LOG_ENABLE= +CONFIG_ESP32_WIFI_IRAM_OPT=y + +# +# PHY +# +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION= +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 + +# +# Power Management +# +CONFIG_PM_ENABLE= + +# +# ADC-Calibration +# +CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y +CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y +CONFIG_ADC_CAL_LUT_ENABLE=y + +# +# Event Loop Library +# +CONFIG_EVENT_LOOP_PROFILING= + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS= + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y + +# +# ESP HTTPS OTA +# +CONFIG_OTA_ALLOW_HTTP= + +# +# Core dump +# +CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH= +CONFIG_ESP32_ENABLE_COREDUMP_TO_UART= +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +CONFIG_ESP32_ENABLE_COREDUMP= + +# +# Ethernet +# +CONFIG_DMA_RX_BUF_NUM=10 +CONFIG_DMA_TX_BUF_NUM=10 +CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE=y +CONFIG_EMAC_CHECK_LINK_PERIOD_MS=2000 +CONFIG_EMAC_TASK_PRIORITY=20 +CONFIG_EMAC_TASK_STACK_SIZE=3072 + +# +# FAT Filesystem support +# +CONFIG_FATFS_CODEPAGE_DYNAMIC= +CONFIG_FATFS_CODEPAGE_437=y +CONFIG_FATFS_CODEPAGE_720= +CONFIG_FATFS_CODEPAGE_737= +CONFIG_FATFS_CODEPAGE_771= +CONFIG_FATFS_CODEPAGE_775= +CONFIG_FATFS_CODEPAGE_850= +CONFIG_FATFS_CODEPAGE_852= +CONFIG_FATFS_CODEPAGE_855= +CONFIG_FATFS_CODEPAGE_857= +CONFIG_FATFS_CODEPAGE_860= +CONFIG_FATFS_CODEPAGE_861= +CONFIG_FATFS_CODEPAGE_862= +CONFIG_FATFS_CODEPAGE_863= +CONFIG_FATFS_CODEPAGE_864= +CONFIG_FATFS_CODEPAGE_865= +CONFIG_FATFS_CODEPAGE_866= +CONFIG_FATFS_CODEPAGE_869= +CONFIG_FATFS_CODEPAGE_932= +CONFIG_FATFS_CODEPAGE_936= +CONFIG_FATFS_CODEPAGE_949= +CONFIG_FATFS_CODEPAGE_950= +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_LFN_NONE= +CONFIG_FATFS_LFN_HEAP= +CONFIG_FATFS_LFN_STACK=y +CONFIG_FATFS_MAX_LFN=255 +CONFIG_FATFS_API_ENCODING_ANSI_OEM=y +CONFIG_FATFS_API_ENCODING_UTF_16= +CONFIG_FATFS_API_ENCODING_UTF_8= +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y + +# +# Modbus configuration +# +CONFIG_MB_QUEUE_LENGTH=20 +CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048 +CONFIG_MB_SERIAL_BUF_SIZE=256 +CONFIG_MB_SERIAL_TASK_PRIO=10 +CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT= +CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_MB_CONTROLLER_STACK_SIZE=4096 +CONFIG_MB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_MB_TIMER_PORT_ENABLED=y +CONFIG_MB_TIMER_GROUP=0 +CONFIG_MB_TIMER_INDEX=0 + +# +# FreeRTOS +# +CONFIG_FREERTOS_UNICORE= +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_CORETIMER_0=y +CONFIG_FREERTOS_CORETIMER_1= +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE= +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL= +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK= +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y +CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE= +CONFIG_FREERTOS_ASSERT_DISABLE= +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +CONFIG_FREERTOS_LEGACY_HOOKS= +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +CONFIG_SUPPORT_STATIC_ALLOCATION=y +CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK= +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_USE_TRACE_FACILITY= +CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS= +CONFIG_FREERTOS_DEBUG_INTERNALS= + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +CONFIG_HEAP_POISONING_LIGHT= +CONFIG_HEAP_POISONING_COMPREHENSIVE= +CONFIG_HEAP_TRACING= + +# +# libsodium +# +CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y + +# +# Log output +# +CONFIG_LOG_DEFAULT_LEVEL_NONE= +CONFIG_LOG_DEFAULT_LEVEL_ERROR= +CONFIG_LOG_DEFAULT_LEVEL_WARN= +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +CONFIG_LOG_DEFAULT_LEVEL_DEBUG= +CONFIG_LOG_DEFAULT_LEVEL_VERBOSE= +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_COLORS=y + +# +# LWIP +# +CONFIG_L2_TO_L3_COPY= +CONFIG_LWIP_IRAM_OPTIMIZATION= +CONFIG_LWIP_MAX_SOCKETS=10 +CONFIG_USE_ONLY_LWIP_SELECT= +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +CONFIG_LWIP_SO_RCVBUF= +CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 +CONFIG_LWIP_IP_FRAG= +CONFIG_LWIP_IP_REASSEMBLY= +CONFIG_LWIP_STATS= +CONFIG_LWIP_ETHARP_TRUST_IP_MAC= +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +CONFIG_LWIP_DHCP_RESTORE_LAST_IP= + +# +# DHCP server +# +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +CONFIG_LWIP_AUTOIP= +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=6 +CONFIG_TCP_MSS=1436 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5744 +CONFIG_TCP_WND_DEFAULT=5744 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES= +CONFIG_TCP_OVERSIZE_MSS=y +CONFIG_TCP_OVERSIZE_QUARTER_MSS= +CONFIG_TCP_OVERSIZE_DISABLE= + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +CONFIG_TCPIP_TASK_AFFINITY_CPU0= +CONFIG_TCPIP_TASK_AFFINITY_CPU1= +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +CONFIG_PPP_SUPPORT= + +# +# ICMP +# +CONFIG_LWIP_MULTICAST_PING= +CONFIG_LWIP_BROADCAST_PING= + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC= +CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC= +CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC= +CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384 +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN= +CONFIG_MBEDTLS_DEBUG= +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_HARDWARE_MPI= +CONFIG_MBEDTLS_HARDWARE_SHA= +CONFIG_MBEDTLS_HAVE_TIME=y +CONFIG_MBEDTLS_HAVE_TIME_DATE= +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +CONFIG_MBEDTLS_TLS_SERVER_ONLY= +CONFIG_MBEDTLS_TLS_CLIENT_ONLY= +CONFIG_MBEDTLS_TLS_DISABLED= +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +CONFIG_MBEDTLS_PSK_MODES= +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +CONFIG_MBEDTLS_SSL_PROTO_SSL3= +CONFIG_MBEDTLS_SSL_PROTO_TLS1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +CONFIG_MBEDTLS_SSL_PROTO_DTLS= +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +CONFIG_MBEDTLS_CAMELLIA_C= +CONFIG_MBEDTLS_DES_C= +CONFIG_MBEDTLS_RC4_DISABLED=y +CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT= +CONFIG_MBEDTLS_RC4_ENABLED= +CONFIG_MBEDTLS_BLOWFISH_C= +CONFIG_MBEDTLS_XTEA_C= +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +CONFIG_MBEDTLS_RIPEMD160_C= + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y + +# +# mDNS +# +CONFIG_MDNS_MAX_SERVICES=10 + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +CONFIG_MQTT_USE_CUSTOM_CONFIG= +CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED= +CONFIG_MQTT_CUSTOM_OUTBOX= + +# +# NVS +# + +# +# OpenSSL +# +CONFIG_OPENSSL_DEBUG= +CONFIG_OPENSSL_ASSERT_DO_NOTHING=y +CONFIG_OPENSSL_ASSERT_EXIT= + +# +# PThreads +# +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0= +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1= +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" + +# +# SPI Flash driver +# +CONFIG_SPI_FLASH_VERIFY_WRITE= +CONFIG_SPI_FLASH_ENABLE_COUNTERS= +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +CONFIG_SPIFFS_CACHE_STATS= +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +CONFIG_SPIFFS_GC_STATS= +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +CONFIG_SPIFFS_DBG= +CONFIG_SPIFFS_API_DBG= +CONFIG_SPIFFS_GC_DBG= +CONFIG_SPIFFS_CACHE_DBG= +CONFIG_SPIFFS_CHECK_DBG= +CONFIG_SPIFFS_TEST_VISUALISATION= + +# +# TCP/IP Adapter +# +CONFIG_IP_LOST_TIMER_INTERVAL=120 +CONFIG_TCPIP_LWIP=y + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +CONFIG_UNITY_ENABLE_COLOR= +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +CONFIG_UNITY_ENABLE_FIXTURE= + +# +# Virtual file system +# +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y + +# +# Wear Levelling +# +CONFIG_WL_SECTOR_SIZE_512= +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 diff --git a/MCUME_esp32/espcastaway/sdkconfig.old b/MCUME_esp32/espcastaway/sdkconfig.old new file mode 100644 index 0000000..e6b5dbe --- /dev/null +++ b/MCUME_esp32/espcastaway/sdkconfig.old @@ -0,0 +1,705 @@ +# +# Automatically generated file; DO NOT EDIT. +# Espressif IoT Development Framework Configuration +# +CONFIG_IDF_TARGET="esp32" + +# +# SDK tool configuration +# +CONFIG_TOOLPREFIX="xtensa-esp32-elf-" +CONFIG_PYTHON="python" +CONFIG_MAKE_WARN_UNDEFINED_VARIABLES=y + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y + +# +# Bootloader config +# +CONFIG_LOG_BOOTLOADER_LEVEL_NONE= +CONFIG_LOG_BOOTLOADER_LEVEL_ERROR= +CONFIG_LOG_BOOTLOADER_LEVEL_WARN= +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG= +CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE= +CONFIG_LOG_BOOTLOADER_LEVEL=3 +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V= +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +CONFIG_BOOTLOADER_FACTORY_RESET= +CONFIG_BOOTLOADER_APP_TEST= +CONFIG_BOOTLOADER_WDT_ENABLE=y +CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE= +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 + +# +# Security features +# +CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT= +CONFIG_SECURE_BOOT_ENABLED= +CONFIG_FLASH_ENCRYPTION_ENABLED= + +# +# Serial flasher config +# +CONFIG_ESPTOOLPY_PORT="/dev/cu.SLAB_USBtoUART" +CONFIG_ESPTOOLPY_BAUD_115200B=y +CONFIG_ESPTOOLPY_BAUD_230400B= +CONFIG_ESPTOOLPY_BAUD_921600B= +CONFIG_ESPTOOLPY_BAUD_2MB= +CONFIG_ESPTOOLPY_BAUD_OTHER= +CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 +CONFIG_ESPTOOLPY_BAUD=115200 +CONFIG_ESPTOOLPY_COMPRESSED=y +CONFIG_FLASHMODE_QIO= +CONFIG_FLASHMODE_QOUT= +CONFIG_FLASHMODE_DIO=y +CONFIG_FLASHMODE_DOUT= +CONFIG_ESPTOOLPY_FLASHMODE="dio" +CONFIG_ESPTOOLPY_FLASHFREQ_80M= +CONFIG_ESPTOOLPY_FLASHFREQ_40M=y +CONFIG_ESPTOOLPY_FLASHFREQ_26M= +CONFIG_ESPTOOLPY_FLASHFREQ_20M= +CONFIG_ESPTOOLPY_FLASHFREQ="40m" +CONFIG_ESPTOOLPY_FLASHSIZE_1MB= +CONFIG_ESPTOOLPY_FLASHSIZE_2MB= +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +CONFIG_ESPTOOLPY_FLASHSIZE_8MB= +CONFIG_ESPTOOLPY_FLASHSIZE_16MB= +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" +CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y +CONFIG_ESPTOOLPY_BEFORE_RESET=y +CONFIG_ESPTOOLPY_BEFORE_NORESET= +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +CONFIG_ESPTOOLPY_AFTER_NORESET= +CONFIG_ESPTOOLPY_AFTER="hard_reset" +CONFIG_MONITOR_BAUD_9600B= +CONFIG_MONITOR_BAUD_57600B= +CONFIG_MONITOR_BAUD_115200B=y +CONFIG_MONITOR_BAUD_230400B= +CONFIG_MONITOR_BAUD_921600B= +CONFIG_MONITOR_BAUD_2MB= +CONFIG_MONITOR_BAUD_OTHER= +CONFIG_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_MONITOR_BAUD=115200 + +# +# Partition Table +# +CONFIG_PARTITION_TABLE_SINGLE_APP= +CONFIG_PARTITION_TABLE_TWO_OTA= +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y + +# +# Compiler options +# +CONFIG_OPTIMIZATION_LEVEL_DEBUG= +CONFIG_OPTIMIZATION_LEVEL_RELEASE=y +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +CONFIG_OPTIMIZATION_ASSERTIONS_SILENT= +CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED= +CONFIG_CXX_EXCEPTIONS= +CONFIG_STACK_CHECK_NONE=y +CONFIG_STACK_CHECK_NORM= +CONFIG_STACK_CHECK_STRONG= +CONFIG_STACK_CHECK_ALL= +CONFIG_STACK_CHECK= +CONFIG_WARN_WRITE_STRINGS= +CONFIG_DISABLE_GCC8_WARNINGS= + +# +# Component config +# + +# +# Application Level Tracing +# +CONFIG_ESP32_APPTRACE_DEST_TRAX= +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_ENABLE= +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +CONFIG_AWS_IOT_SDK= + +# +# Bluetooth +# +CONFIG_BT_ENABLED= +CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0 +CONFIG_BT_RESERVE_DRAM=0 + +# +# Driver configurations +# + +# +# ADC configuration +# +CONFIG_ADC_FORCE_XPD_FSM= +CONFIG_ADC2_DISABLE_DAC=y + +# +# SPI configuration +# +CONFIG_SPI_MASTER_IN_IRAM= +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +CONFIG_SPI_SLAVE_IN_IRAM= +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y + +# +# ESP32-specific +# +CONFIG_IDF_TARGET_ESP32=y +CONFIG_ESP32_DEFAULT_CPU_FREQ_80= +CONFIG_ESP32_DEFAULT_CPU_FREQ_160= +CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y +CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240 +CONFIG_SPIRAM_SUPPORT=y + +# +# SPI RAM config +# +CONFIG_SPIRAM_BOOT_INIT=y +CONFIG_SPIRAM_IGNORE_NOTFOUND= +CONFIG_SPIRAM_USE_MEMMAP= +CONFIG_SPIRAM_USE_CAPS_ALLOC=y +CONFIG_SPIRAM_USE_MALLOC= +CONFIG_SPIRAM_TYPE_AUTO=y +CONFIG_SPIRAM_TYPE_ESPPSRAM32= +CONFIG_SPIRAM_TYPE_ESPPSRAM64= +CONFIG_SPIRAM_SIZE=-1 +CONFIG_SPIRAM_SPEED_40M=y +CONFIG_SPIRAM_MEMTEST=y +CONFIG_SPIRAM_CACHE_WORKAROUND=y +CONFIG_SPIRAM_BANKSWITCH_ENABLE=y +CONFIG_SPIRAM_BANKSWITCH_RESERVE=8 +CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST= +CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY= +CONFIG_MEMMAP_TRACEMEM= +CONFIG_MEMMAP_TRACEMEM_TWOBANKS= +CONFIG_ESP32_TRAX= +CONFIG_TRACEMEM_RESERVE_DRAM=0x0 + +# +# Core dump +# +CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH= +CONFIG_ESP32_ENABLE_COREDUMP_TO_UART= +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +CONFIG_ESP32_ENABLE_COREDUMP= +CONFIG_TWO_UNIVERSAL_MAC_ADDRESS= +CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y +CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4 +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +CONFIG_IPC_TASK_STACK_SIZE=1024 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF= +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR= +CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF= +CONFIG_NEWLIB_STDIN_LINE_ENDING_LF= +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +CONFIG_NEWLIB_NANO_FORMAT= +CONFIG_CONSOLE_UART_DEFAULT=y +CONFIG_CONSOLE_UART_CUSTOM= +CONFIG_CONSOLE_UART_NONE= +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ULP_COPROC_ENABLED= +CONFIG_ULP_COPROC_RESERVE_MEM=0 +CONFIG_ESP32_PANIC_PRINT_HALT= +CONFIG_ESP32_PANIC_PRINT_REBOOT=y +CONFIG_ESP32_PANIC_SILENT_REBOOT= +CONFIG_ESP32_PANIC_GDBSTUB= +CONFIG_ESP32_DEBUG_OCDAWARE=y +CONFIG_ESP32_DEBUG_STUBS_ENABLE=y +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_INT_WDT_CHECK_CPU1=y +CONFIG_TASK_WDT=y +CONFIG_TASK_WDT_PANIC= +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +CONFIG_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_0=y +CONFIG_BROWNOUT_DET_LVL_SEL_1= +CONFIG_BROWNOUT_DET_LVL_SEL_2= +CONFIG_BROWNOUT_DET_LVL_SEL_3= +CONFIG_BROWNOUT_DET_LVL_SEL_4= +CONFIG_BROWNOUT_DET_LVL_SEL_5= +CONFIG_BROWNOUT_DET_LVL_SEL_6= +CONFIG_BROWNOUT_DET_LVL_SEL_7= +CONFIG_BROWNOUT_DET_LVL=0 +CONFIG_REDUCE_PHY_TX_POWER=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC= +CONFIG_ESP32_TIME_SYSCALL_USE_FRC1= +CONFIG_ESP32_TIME_SYSCALL_USE_NONE= +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y +CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL= +CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC= +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256= +CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP32_XTAL_FREQ_40=y +CONFIG_ESP32_XTAL_FREQ_26= +CONFIG_ESP32_XTAL_FREQ_AUTO= +CONFIG_ESP32_XTAL_FREQ=40 +CONFIG_DISABLE_BASIC_ROM_CONSOLE= +CONFIG_NO_BLOBS= +CONFIG_ESP_TIMER_PROFILING= +CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS= +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y + +# +# Wi-Fi +# +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER= +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16 +CONFIG_ESP32_WIFI_CSI_ENABLED= +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1= +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_DEBUG_LOG_ENABLE= + +# +# PHY +# +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION= +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 + +# +# Power Management +# +CONFIG_PM_ENABLE= + +# +# ADC-Calibration +# +CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y +CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y +CONFIG_ADC_CAL_LUT_ENABLE=y + +# +# Event Loop Library +# +CONFIG_EVENT_LOOP_PROFILING= + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS= + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 + +# +# Ethernet +# +CONFIG_DMA_RX_BUF_NUM=10 +CONFIG_DMA_TX_BUF_NUM=10 +CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE=y +CONFIG_EMAC_CHECK_LINK_PERIOD_MS=2000 +CONFIG_EMAC_TASK_PRIORITY=20 +CONFIG_EMAC_TASK_STACK_SIZE=3072 + +# +# FAT Filesystem support +# +CONFIG_FATFS_CODEPAGE_DYNAMIC= +CONFIG_FATFS_CODEPAGE_437=y +CONFIG_FATFS_CODEPAGE_720= +CONFIG_FATFS_CODEPAGE_737= +CONFIG_FATFS_CODEPAGE_771= +CONFIG_FATFS_CODEPAGE_775= +CONFIG_FATFS_CODEPAGE_850= +CONFIG_FATFS_CODEPAGE_852= +CONFIG_FATFS_CODEPAGE_855= +CONFIG_FATFS_CODEPAGE_857= +CONFIG_FATFS_CODEPAGE_860= +CONFIG_FATFS_CODEPAGE_861= +CONFIG_FATFS_CODEPAGE_862= +CONFIG_FATFS_CODEPAGE_863= +CONFIG_FATFS_CODEPAGE_864= +CONFIG_FATFS_CODEPAGE_865= +CONFIG_FATFS_CODEPAGE_866= +CONFIG_FATFS_CODEPAGE_869= +CONFIG_FATFS_CODEPAGE_932= +CONFIG_FATFS_CODEPAGE_936= +CONFIG_FATFS_CODEPAGE_949= +CONFIG_FATFS_CODEPAGE_950= +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_LFN_NONE= +CONFIG_FATFS_LFN_HEAP= +CONFIG_FATFS_LFN_STACK=y +CONFIG_FATFS_MAX_LFN=255 +CONFIG_FATFS_API_ENCODING_ANSI_OEM=y +CONFIG_FATFS_API_ENCODING_UTF_16= +CONFIG_FATFS_API_ENCODING_UTF_8= +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y + +# +# Modbus configuration +# +CONFIG_MB_UART_RXD=22 +CONFIG_MB_UART_TXD=23 +CONFIG_MB_UART_RTS=18 +CONFIG_MB_QUEUE_LENGTH=20 +CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048 +CONFIG_MB_SERIAL_BUF_SIZE=256 +CONFIG_MB_SERIAL_TASK_PRIO=10 +CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT= +CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_MB_CONTROLLER_STACK_SIZE=4096 +CONFIG_MB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_MB_TIMER_PORT_ENABLED=y +CONFIG_MB_TIMER_GROUP=0 +CONFIG_MB_TIMER_INDEX=0 + +# +# FreeRTOS +# +CONFIG_FREERTOS_UNICORE= +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_CORETIMER_0=y +CONFIG_FREERTOS_CORETIMER_1= +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE= +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL= +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK= +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y +CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE= +CONFIG_FREERTOS_ASSERT_DISABLE= +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +CONFIG_FREERTOS_LEGACY_HOOKS= +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +CONFIG_SUPPORT_STATIC_ALLOCATION=y +CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK= +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_USE_TRACE_FACILITY= +CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS= +CONFIG_FREERTOS_DEBUG_INTERNALS= + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +CONFIG_HEAP_POISONING_LIGHT= +CONFIG_HEAP_POISONING_COMPREHENSIVE= +CONFIG_HEAP_TRACING= + +# +# libsodium +# +CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y + +# +# Log output +# +CONFIG_LOG_DEFAULT_LEVEL_NONE= +CONFIG_LOG_DEFAULT_LEVEL_ERROR= +CONFIG_LOG_DEFAULT_LEVEL_WARN= +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +CONFIG_LOG_DEFAULT_LEVEL_DEBUG= +CONFIG_LOG_DEFAULT_LEVEL_VERBOSE= +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_COLORS=y + +# +# LWIP +# +CONFIG_L2_TO_L3_COPY= +CONFIG_LWIP_IRAM_OPTIMIZATION= +CONFIG_LWIP_MAX_SOCKETS=10 +CONFIG_USE_ONLY_LWIP_SELECT= +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +CONFIG_LWIP_SO_RCVBUF= +CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 +CONFIG_LWIP_IP_FRAG= +CONFIG_LWIP_IP_REASSEMBLY= +CONFIG_LWIP_STATS= +CONFIG_LWIP_ETHARP_TRUST_IP_MAC= +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +CONFIG_LWIP_DHCP_RESTORE_LAST_IP= + +# +# DHCP server +# +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +CONFIG_LWIP_AUTOIP= +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=6 +CONFIG_TCP_MSS=1436 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5744 +CONFIG_TCP_WND_DEFAULT=5744 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES= +CONFIG_TCP_OVERSIZE_MSS=y +CONFIG_TCP_OVERSIZE_QUARTER_MSS= +CONFIG_TCP_OVERSIZE_DISABLE= + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +CONFIG_TCPIP_TASK_AFFINITY_CPU0= +CONFIG_TCPIP_TASK_AFFINITY_CPU1= +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +CONFIG_PPP_SUPPORT= + +# +# ICMP +# +CONFIG_LWIP_MULTICAST_PING= +CONFIG_LWIP_BROADCAST_PING= + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC= +CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC= +CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC= +CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384 +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN= +CONFIG_MBEDTLS_DEBUG= +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_HARDWARE_MPI= +CONFIG_MBEDTLS_HARDWARE_SHA= +CONFIG_MBEDTLS_HAVE_TIME=y +CONFIG_MBEDTLS_HAVE_TIME_DATE= +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +CONFIG_MBEDTLS_TLS_SERVER_ONLY= +CONFIG_MBEDTLS_TLS_CLIENT_ONLY= +CONFIG_MBEDTLS_TLS_DISABLED= +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +CONFIG_MBEDTLS_PSK_MODES= +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +CONFIG_MBEDTLS_SSL_PROTO_SSL3= +CONFIG_MBEDTLS_SSL_PROTO_TLS1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +CONFIG_MBEDTLS_SSL_PROTO_DTLS= +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +CONFIG_MBEDTLS_CAMELLIA_C= +CONFIG_MBEDTLS_DES_C= +CONFIG_MBEDTLS_RC4_DISABLED=y +CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT= +CONFIG_MBEDTLS_RC4_ENABLED= +CONFIG_MBEDTLS_BLOWFISH_C= +CONFIG_MBEDTLS_XTEA_C= +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +CONFIG_MBEDTLS_RIPEMD160_C= + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y + +# +# mDNS +# +CONFIG_MDNS_MAX_SERVICES=10 + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +CONFIG_MQTT_USE_CUSTOM_CONFIG= +CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED= +CONFIG_MQTT_CUSTOM_OUTBOX= + +# +# NVS +# + +# +# OpenSSL +# +CONFIG_OPENSSL_DEBUG= +CONFIG_OPENSSL_ASSERT_DO_NOTHING=y +CONFIG_OPENSSL_ASSERT_EXIT= + +# +# PThreads +# +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0= +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1= +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" + +# +# SPI Flash driver +# +CONFIG_SPI_FLASH_VERIFY_WRITE= +CONFIG_SPI_FLASH_ENABLE_COUNTERS= +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS= +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED= + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +CONFIG_SPIFFS_CACHE_STATS= +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +CONFIG_SPIFFS_GC_STATS= +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +CONFIG_SPIFFS_DBG= +CONFIG_SPIFFS_API_DBG= +CONFIG_SPIFFS_GC_DBG= +CONFIG_SPIFFS_CACHE_DBG= +CONFIG_SPIFFS_CHECK_DBG= +CONFIG_SPIFFS_TEST_VISUALISATION= + +# +# TCP/IP Adapter +# +CONFIG_IP_LOST_TIMER_INTERVAL=120 +CONFIG_TCPIP_LWIP=y + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +CONFIG_UNITY_ENABLE_COLOR= +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +CONFIG_UNITY_ENABLE_FIXTURE= + +# +# Virtual file system +# +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y + +# +# Wear Levelling +# +CONFIG_WL_SECTOR_SIZE_512= +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 diff --git a/MCUME_esp32/espvectrex/.DS_Store b/MCUME_esp32/espvectrex/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..b5ef1718023ea40f963a488cd8fcde6b53461506 GIT binary patch literal 6148 zcmeHK&1%~~5S~rcW~~tFLm};LFTJ@C(WE$sfN{+&uG^J0HiaHJ%A|eyKHC zGb1vOs5u01=%W^p*P`u!Wxz7<*cg!Ct_wX7FoX=->ibR4y`U$C*}{gG#tlWc8;^?~ z!0)|3Tt(jz7ynmWHmI%Z;NC(=fJc)&i&7EcDnFwvP4Z%A=NDO9cb+`mpwy-Amisvv zh)Ga{#W?STqhs0o5Eg^T*hfO7l^sSOlm6ti`TS7uB20LHq>_`kk0B?Y5*~|5M~r!# zt9b(LptM07r_Gnsskgh|Vz0gZS&L1*y|?WaYq#IbW(~Ui$~$;}HvD=yy_#Kr*9;Q8 zA(cEcIENo-R3}`*dgWVS`pdT)mA>Gs*sb~g#pp#a;;G>0INN-G^L<%dbq35YPB&Nm zp!R&00n5O>8Ibn_LzU<|%e`*uyVBBCXVAWNfQGF+rCe6o)pOP91F{w=aB4uK^y9+ zrB^ELf5aZTrfK_+J<;dG;zkcNVcS30LV-}=)C%Cu7F%8!MjZ--0-?a5fZPuWMX+|vhI)0N(i8w#VOR}q$tA=m zIo6KZ5DbjX6=<&PDF&N6#*@#h9kZdi6MOQ(9{D$UVU3RUlTIhD4WkYPLV>9Qm)2d$ z`+tYOOfkuyxS9f512&f=Yg#sr~;0I9mJyiez literal 0 HcmV?d00001 diff --git a/MCUME_esp32/espvectrex/components/Audio/.DS_Store b/MCUME_esp32/espvectrex/components/Audio/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..5008ddfcf53c02e82d7eee2e57c38e5672ef89f6 GIT binary patch literal 6148 zcmeH~Jr2S!425mzP>H1@V-^m;4Wg<&0T*E43hX&L&p$$qDprKhvt+--jT7}7np#A3 zem<@ulZcFPQ@L2!n>{z**++&mCkOWA81W14cNZlEfg7;MkzE(HCqgga^y>{tEnwC%0;vJ&^%eQ zLs35+`xjp>T0 26){ + return;//not dac pin + } + pinMode(pin, ANALOG); + uint8_t channel = pin - 25; + + + //Disable Tone + CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL1_REG, SENS_SW_TONE_EN); + + if (channel) { + //Disable Channel Tone + CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN2_M); + //Set the Dac value + SET_PERI_REG_BITS(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_DAC, value, RTC_IO_PDAC2_DAC_S); //dac_output + //Channel output enable + SET_PERI_REG_MASK(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_XPD_DAC | RTC_IO_PDAC2_DAC_XPD_FORCE); + } else { + //Disable Channel Tone + CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN1_M); + //Set the Dac value + SET_PERI_REG_BITS(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_DAC, value, RTC_IO_PDAC1_DAC_S); //dac_output + //Channel output enable + SET_PERI_REG_MASK(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_XPD_DAC | RTC_IO_PDAC1_DAC_XPD_FORCE); + } +} + +extern void dacWrite(uint8_t pin, uint8_t value) __attribute__ ((weak, alias("__dacWrite"))); diff --git a/MCUME_esp32/espvectrex/components/Audio/esp32-hal-dac.h b/MCUME_esp32/espvectrex/components/Audio/esp32-hal-dac.h new file mode 100644 index 0000000..c311be1 --- /dev/null +++ b/MCUME_esp32/espvectrex/components/Audio/esp32-hal-dac.h @@ -0,0 +1,36 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAIN_ESP32_HAL_DAC_H_ +#define MAIN_ESP32_HAL_DAC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +//#include "esp32-hal.h" +#include "driver/gpio.h" + +void dacWrite(uint8_t pin, uint8_t value); + +#ifdef __cplusplus +} +#endif + +#endif /* MAIN_ESP32_HAL_DAC_H_ */ diff --git a/MCUME_esp32/espvectrex/components/Audio/esp32-hal-timer.c b/MCUME_esp32/espvectrex/components/Audio/esp32-hal-timer.c new file mode 100644 index 0000000..17743a4 --- /dev/null +++ b/MCUME_esp32/espvectrex/components/Audio/esp32-hal-timer.c @@ -0,0 +1,293 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-timer.h" +#include "freertos/FreeRTOS.h" +#include "freertos/xtensa_api.h" +#include "freertos/task.h" +#include "rom/ets_sys.h" +#include "soc/timer_group_struct.h" +#include "soc/dport_reg.h" +#include "esp_attr.h" +#include "esp_intr.h" + +#define HWTIMER_LOCK() portENTER_CRITICAL(timer->lock) +#define HWTIMER_UNLOCK() portEXIT_CRITICAL(timer->lock) + +typedef struct { + union { + struct { + uint32_t reserved0: 10; + uint32_t alarm_en: 1; /*When set alarm is enabled*/ + uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/ + uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/ + uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/ + uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/ + uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/ + uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/ + }; + uint32_t val; + } config; + uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/ + uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/ + uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/ + uint32_t alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ + uint32_t alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ + uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/ + uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/ + uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/ +} hw_timer_reg_t; + +typedef struct hw_timer_s { + hw_timer_reg_t * dev; + uint8_t num; + uint8_t group; + uint8_t timer; + portMUX_TYPE lock; +} hw_timer_t; + +static hw_timer_t hw_timer[4] = { + {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE),0,0,0,portMUX_INITIALIZER_UNLOCKED}, + {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x0024),1,0,1,portMUX_INITIALIZER_UNLOCKED}, + {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x1000),2,1,0,portMUX_INITIALIZER_UNLOCKED}, + {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x1024),3,1,1,portMUX_INITIALIZER_UNLOCKED} +}; + +typedef void (*voidFuncPtr)(void); +static voidFuncPtr __timerInterruptHandlers[4] = {0,0,0,0}; + +void IRAM_ATTR __timerISR(void * arg){ + uint32_t s0 = TIMERG0.int_st_timers.val; + uint32_t s1 = TIMERG1.int_st_timers.val; + TIMERG0.int_clr_timers.val = s0; + TIMERG1.int_clr_timers.val = s1; + uint8_t status = (s1 & 3) << 2 | (s0 & 3); + uint8_t i = 4; + //restart the timers that should autoreload + while(i--){ + hw_timer_reg_t * dev = hw_timer[i].dev; + if((status & (1 << i)) && dev->config.autoreload){ + dev->config.alarm_en = 1; + } + } + i = 4; + //call callbacks + while(i--){ + if(__timerInterruptHandlers[i] && status & (1 << i)){ + __timerInterruptHandlers[i](); + } + } +} + +uint64_t timerRead(hw_timer_t *timer){ + timer->dev->update = 1; + uint64_t h = timer->dev->cnt_high; + uint64_t l = timer->dev->cnt_low; + return (h << 32) | l; +} + +uint64_t timerAlarmRead(hw_timer_t *timer){ + uint64_t h = timer->dev->alarm_high; + uint64_t l = timer->dev->alarm_low; + return (h << 32) | l; +} + +void timerWrite(hw_timer_t *timer, uint64_t val){ + timer->dev->load_high = (uint32_t) (val >> 32); + timer->dev->load_low = (uint32_t) (val); + timer->dev->reload = 1; +} + +void timerAlarmWrite(hw_timer_t *timer, uint64_t alarm_value, bool autoreload){ + timer->dev->alarm_high = (uint32_t) (alarm_value >> 32); + timer->dev->alarm_low = (uint32_t) alarm_value; + timer->dev->config.autoreload = autoreload; +} + +void timerSetConfig(hw_timer_t *timer, uint32_t config){ + timer->dev->config.val = config; +} + +uint32_t timerGetConfig(hw_timer_t *timer){ + return timer->dev->config.val; +} + +void timerSetCountUp(hw_timer_t *timer, bool countUp){ + timer->dev->config.increase = countUp; +} + +bool timerGetCountUp(hw_timer_t *timer){ + return timer->dev->config.increase; +} + +void timerSetAutoReload(hw_timer_t *timer, bool autoreload){ + timer->dev->config.autoreload = autoreload; +} + +bool timerGetAutoReload(hw_timer_t *timer){ + return timer->dev->config.autoreload; +} + +void timerSetDivider(hw_timer_t *timer, uint16_t divider){//2 to 65536 + if(!divider){ + divider = 0xFFFF; + } else if(divider == 1){ + divider = 2; + } + int timer_en = timer->dev->config.enable; + timer->dev->config.enable = 0; + timer->dev->config.divider = divider; + timer->dev->config.enable = timer_en; +} + +uint16_t timerGetDivider(hw_timer_t *timer){ + return timer->dev->config.divider; +} + +void timerStart(hw_timer_t *timer){ + timer->dev->config.enable = 1; +} + +void timerStop(hw_timer_t *timer){ + timer->dev->config.enable = 0; +} + +void timerRestart(hw_timer_t *timer){ + timer->dev->config.enable = 0; + timer->dev->config.enable = 1; +} + +bool timerStarted(hw_timer_t *timer){ + return timer->dev->config.enable; +} + +void timerAlarmEnable(hw_timer_t *timer){ + timer->dev->config.alarm_en = 1; +} + +void timerAlarmDisable(hw_timer_t *timer){ + timer->dev->config.alarm_en = 0; +} + +bool timerAlarmEnabled(hw_timer_t *timer){ + return timer->dev->config.alarm_en; +} + +hw_timer_t * timerBegin(uint8_t num, uint16_t divider, bool countUp){ + if(num > 3){ + return NULL; + } + hw_timer_t * timer = &hw_timer[num]; + if(timer->group) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST); + TIMERG1.int_ena.val &= ~BIT(timer->timer); + } else { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST); + TIMERG0.int_ena.val &= ~BIT(timer->timer); + } + timer->dev->config.enable = 0; + timerSetDivider(timer, divider); + timerSetCountUp(timer, countUp); + timerSetAutoReload(timer, false); + timerAttachInterrupt(timer, NULL, false); + timerWrite(timer, 0); + timer->dev->config.enable = 1; + return timer; +} + +void timerEnd(hw_timer_t *timer){ + timer->dev->config.enable = 0; + timerAttachInterrupt(timer, NULL, false); +} + +void timerAttachInterrupt(hw_timer_t *timer, void (*fn)(void), bool edge){ + static bool initialized = false; + static intr_handle_t intr_handle = NULL; + if(intr_handle){ + esp_intr_disable(intr_handle); + } + if(fn == NULL){ + timer->dev->config.level_int_en = 0; + timer->dev->config.edge_int_en = 0; + timer->dev->config.alarm_en = 0; + if(timer->num & 2){ + TIMERG1.int_ena.val &= ~BIT(timer->timer); + } else { + TIMERG0.int_ena.val &= ~BIT(timer->timer); + } + __timerInterruptHandlers[timer->num] = NULL; + } else { + __timerInterruptHandlers[timer->num] = fn; + timer->dev->config.level_int_en = edge?0:1;//When set, an alarm will generate a level type interrupt. + timer->dev->config.edge_int_en = edge?1:0;//When set, an alarm will generate an edge type interrupt. + int intr_source = 0; + if(!edge){ + if(timer->group){ + intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer->timer; + } else { + intr_source = ETS_TG0_T0_LEVEL_INTR_SOURCE + timer->timer; + } + } else { + if(timer->group){ + intr_source = ETS_TG1_T0_EDGE_INTR_SOURCE + timer->timer; + } else { + intr_source = ETS_TG0_T0_EDGE_INTR_SOURCE + timer->timer; + } + } + if(!initialized){ + initialized = true; + esp_intr_alloc(intr_source, (int)(ESP_INTR_FLAG_IRAM|ESP_INTR_FLAG_LOWMED|ESP_INTR_FLAG_EDGE), __timerISR, NULL, &intr_handle); + } else { + intr_matrix_set(esp_intr_get_cpu(intr_handle), intr_source, esp_intr_get_intno(intr_handle)); + } + if(timer->group){ + TIMERG1.int_ena.val |= BIT(timer->timer); + } else { + TIMERG0.int_ena.val |= BIT(timer->timer); + } + } + if(intr_handle){ + esp_intr_enable(intr_handle); + } +} + +void timerDetachInterrupt(hw_timer_t *timer){ + timerAttachInterrupt(timer, NULL, false); +} + +uint64_t timerReadMicros(hw_timer_t *timer){ + uint64_t timer_val = timerRead(timer); + uint16_t div = timerGetDivider(timer); + return timer_val * div / 80; +} + +double timerReadSeconds(hw_timer_t *timer){ + uint64_t timer_val = timerRead(timer); + uint16_t div = timerGetDivider(timer); + return (double)timer_val * div / 80000000; +} + +uint64_t timerAlarmReadMicros(hw_timer_t *timer){ + uint64_t timer_val = timerAlarmRead(timer); + uint16_t div = timerGetDivider(timer); + return timer_val * div / 80; +} + +double timerAlarmReadSeconds(hw_timer_t *timer){ + uint64_t timer_val = timerAlarmRead(timer); + uint16_t div = timerGetDivider(timer); + return (double)timer_val * div / 80000000; +} diff --git a/MCUME_esp32/espvectrex/components/Audio/esp32-hal-timer.h b/MCUME_esp32/espvectrex/components/Audio/esp32-hal-timer.h new file mode 100644 index 0000000..fa4e8c7 --- /dev/null +++ b/MCUME_esp32/espvectrex/components/Audio/esp32-hal-timer.h @@ -0,0 +1,72 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAIN_ESP32_HAL_TIMER_H_ +#define MAIN_ESP32_HAL_TIMER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +//#include "esp32-hal.h" +#include "freertos/FreeRTOS.h" + +struct hw_timer_s; +typedef struct hw_timer_s hw_timer_t; + +hw_timer_t * timerBegin(uint8_t timer, uint16_t divider, bool countUp); +void timerEnd(hw_timer_t *timer); + +void timerSetConfig(hw_timer_t *timer, uint32_t config); +uint32_t timerGetConfig(hw_timer_t *timer); + +void timerAttachInterrupt(hw_timer_t *timer, void (*fn)(void), bool edge); +void timerDetachInterrupt(hw_timer_t *timer); + +void timerStart(hw_timer_t *timer); +void timerStop(hw_timer_t *timer); +void timerRestart(hw_timer_t *timer); +void timerWrite(hw_timer_t *timer, uint64_t val); +void timerSetDivider(hw_timer_t *timer, uint16_t divider); +void timerSetCountUp(hw_timer_t *timer, bool countUp); +void timerSetAutoReload(hw_timer_t *timer, bool autoreload); + +bool timerStarted(hw_timer_t *timer); +uint64_t timerRead(hw_timer_t *timer); +uint64_t timerReadMicros(hw_timer_t *timer); +double timerReadSeconds(hw_timer_t *timer); +uint16_t timerGetDivider(hw_timer_t *timer); +bool timerGetCountUp(hw_timer_t *timer); +bool timerGetAutoReload(hw_timer_t *timer); + +void timerAlarmEnable(hw_timer_t *timer); +void timerAlarmDisable(hw_timer_t *timer); +void timerAlarmWrite(hw_timer_t *timer, uint64_t interruptAt, bool autoreload); + +bool timerAlarmEnabled(hw_timer_t *timer); +uint64_t timerAlarmRead(hw_timer_t *timer); +uint64_t timerAlarmReadMicros(hw_timer_t *timer); +double timerAlarmReadSeconds(hw_timer_t *timer); + + +#ifdef __cplusplus +} +#endif + +#endif /* MAIN_ESP32_HAL_TIMER_H_ */ diff --git a/MCUME_esp32/espvectrex/components/Wire/.DS_Store b/MCUME_esp32/espvectrex/components/Wire/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..5008ddfcf53c02e82d7eee2e57c38e5672ef89f6 GIT binary patch literal 6148 zcmeH~Jr2S!425mzP>H1@V-^m;4Wg<&0T*E43hX&L&p$$qDprKhvt+--jT7}7np#A3 zem<@ulZcFPQ@L2!n>{z**++&mCkOWA81W14cNZlEfg7;MkzE(HCqgga^y>{tEnwC%0;vJ&^%eQ zLs35+`xjp>T0 +#include +#include +} + +#include "esp32-hal-i2c.h" +#include "Wire.h" +//#include "Arduino.h" + + + + + +TwoWire::TwoWire(uint8_t bus_num) + :num(bus_num & 1) + ,sda(-1) + ,scl(-1) + ,i2c(NULL) + ,rxIndex(0) + ,rxLength(0) + ,rxQueued(0) + ,txIndex(0) + ,txLength(0) + ,txAddress(0) + ,txQueued(0) + ,transmitting(0) + ,last_error(I2C_ERROR_OK) + ,_timeOutMillis(50) +{} + +TwoWire::~TwoWire() +{ + flush(); + if(i2c) { + i2cRelease(i2c); + i2c=NULL; + } +} + +bool TwoWire::begin(int sdaPin, int sclPin, uint32_t frequency) +{ + if(sdaPin < 0) { // default param passed + if(num == 0) { + if(sda==-1) { + sdaPin = SDA; //use Default Pin + } else { + sdaPin = sda; // reuse prior pin + } + } else { + if(sda==-1) { + //log_e("no Default SDA Pin for Second Peripheral"); + return false; //no Default pin for Second Peripheral + } else { + sdaPin = sda; // reuse prior pin + } + } + } + + if(sclPin < 0) { // default param passed + if(num == 0) { + if(scl == -1) { + sclPin = SCL; // use Default pin + } else { + sclPin = scl; // reuse prior pin + } + } else { + if(scl == -1) { + //log_e("no Default SCL Pin for Second Peripheral"); + return false; //no Default pin for Second Peripheral + } else { + sclPin = scl; // reuse prior pin + } + } + } + + sda = sdaPin; + scl = sclPin; + i2c = i2cInit(num, sdaPin, sclPin, frequency); + if(!i2c) { + printf("I2C init failed"); + return false; + } + + flush(); + return true; + +} + +void TwoWire::setTimeOut(uint16_t timeOutMillis) +{ + _timeOutMillis = timeOutMillis; +} + +uint16_t TwoWire::getTimeOut() +{ + return _timeOutMillis; +} + +void TwoWire::setClock(uint32_t frequency) +{ + i2cSetFrequency(i2c, frequency); +} + +size_t TwoWire::getClock() +{ + return i2cGetFrequency(i2c); +} + +/* stickBreaker Nov 2017 ISR, and bigblock 64k-1 + */ +i2c_err_t TwoWire::writeTransmission(uint16_t address, uint8_t *buff, uint16_t size, bool sendStop) +{ + last_error = i2cWrite(i2c, address, buff, size, sendStop, _timeOutMillis); + return last_error; +} + +i2c_err_t TwoWire::readTransmission(uint16_t address, uint8_t *buff, uint16_t size, bool sendStop, uint32_t *readCount) +{ + last_error = i2cRead(i2c, address, buff, size, sendStop, _timeOutMillis, readCount); + return last_error; +} + +void TwoWire::beginTransmission(uint16_t address) +{ + transmitting = 1; + txAddress = address; + txIndex = txQueued; // allow multiple beginTransmission(),write(),endTransmission(false) until endTransmission(true) + txLength = txQueued; + last_error = I2C_ERROR_OK; +} + +/*stickbreaker isr + */ +uint8_t TwoWire::endTransmission(bool sendStop) // Assumes Wire.beginTransaction(), Wire.write() +{ + if(transmitting == 1) { + last_error = writeTransmission(txAddress, &txBuffer[txQueued], txLength - txQueued, sendStop); + rxIndex = 0; + rxLength = rxQueued; + rxQueued = 0; + txQueued = 0; // the SendStop=true will restart all Queueing + if(last_error == I2C_ERROR_CONTINUE){ + // txlength is howmany bytes in txbuffer have been use + txQueued = txLength; + } + } else { + last_error = I2C_ERROR_NO_BEGIN; + flush(); + } + txIndex = 0; + txLength = 0; + transmitting = 0; + return last_error; +} + +/* @stickBreaker 11/2017 fix for ReSTART timeout, ISR + */ +uint8_t TwoWire::requestFrom(uint16_t address, uint8_t size, bool sendStop) +{ + //use internal Wire rxBuffer, multiple requestFrom()'s may be pending, try to share rxBuffer + uint32_t cnt = rxQueued; // currently queued reads, next available position in rxBuffer + if(cnt < (I2C_BUFFER_LENGTH-1) && (size + cnt) <= I2C_BUFFER_LENGTH) { // any room left in rxBuffer + rxQueued += size; + } else { // no room to receive more! + //log_e("rxBuff overflow %d", cnt + size); + cnt = 0; + last_error = I2C_ERROR_MEMORY; + flush(); + return cnt; + } + + last_error = readTransmission(address, &rxBuffer[cnt], size, sendStop, &cnt); + rxIndex = 0; + rxLength = rxQueued; + rxQueued = 0; + txQueued = 0; // the SendStop=true will restart all Queueing + if(last_error != I2C_ERROR_OK){ + cnt = 0; + } + return cnt; +} + +size_t TwoWire::write(uint8_t data) +{ + if(transmitting) { + if(txLength >= I2C_BUFFER_LENGTH) { + last_error = I2C_ERROR_MEMORY; + return 0; + } + txBuffer[txIndex] = data; + ++txIndex; + txLength = txIndex; + return 1; + } + last_error = I2C_ERROR_NO_BEGIN; // no begin, not transmitting + return 0; +} + +size_t TwoWire::write(const uint8_t *data, size_t quantity) +{ + for(size_t i = 0; i < quantity; ++i) { + if(!write(data[i])) { + return i; + } + } + return quantity; + +} + +int TwoWire::available(void) +{ + int result = rxLength - rxIndex; + return result; +} + +int TwoWire::read(void) +{ + int value = -1; + if(rxIndex < rxLength) { + value = rxBuffer[rxIndex]; + ++rxIndex; + } + return value; +} + +int TwoWire::peek(void) +{ + int value = -1; + if(rxIndex < rxLength) { + value = rxBuffer[rxIndex]; + } + return value; +} + +void TwoWire::flush(void) +{ + rxIndex = 0; + rxLength = 0; + txIndex = 0; + txLength = 0; + rxQueued = 0; + txQueued = 0; + i2cFlush(i2c); // cleanup +} + +uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop) +{ + return requestFrom(static_cast(address), static_cast(quantity), static_cast(sendStop)); +} + +uint8_t TwoWire::requestFrom(uint16_t address, uint8_t quantity, uint8_t sendStop) +{ + return requestFrom(address, static_cast(quantity), static_cast(sendStop)); +} + +uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity) +{ + return requestFrom(static_cast(address), static_cast(quantity), true); +} + +uint8_t TwoWire::requestFrom(uint16_t address, uint8_t quantity) +{ + return requestFrom(address, static_cast(quantity), true); +} + +uint8_t TwoWire::requestFrom(int address, int quantity) +{ + return requestFrom(static_cast(address), static_cast(quantity), true); +} + +uint8_t TwoWire::requestFrom(int address, int quantity, int sendStop) +{ + return static_cast(requestFrom(static_cast(address), static_cast(quantity), static_cast(sendStop))); +} + +void TwoWire::beginTransmission(int address) +{ + beginTransmission(static_cast(address)); +} + +void TwoWire::beginTransmission(uint8_t address) +{ + beginTransmission(static_cast(address)); +} + +uint8_t TwoWire::endTransmission(void) +{ + return endTransmission(true); +} + +/* stickbreaker Nov2017 better error reporting + */ +uint8_t TwoWire::lastError() +{ + return (uint8_t)last_error; +} + +const char ERRORTEXT[] = + "OK\0" + "DEVICE\0" + "ACK\0" + "TIMEOUT\0" + "BUS\0" + "BUSY\0" + "MEMORY\0" + "CONTINUE\0" + "NO_BEGIN\0" + "\0"; + + +char * TwoWire::getErrorText(uint8_t err) +{ + uint8_t t = 0; + bool found = false; + char * message = (char*)&ERRORTEXT; + + while(!found && message[0]) { + found = t == err; + if(!found) { + message = message + strlen(message) + 1; + t++; + } + } + if(!found) { + return NULL; + } else { + return message; + } +} + +/*stickbreaker Dump i2c Interrupt buffer, i2c isr Debugging + */ + +uint32_t TwoWire::setDebugFlags( uint32_t setBits, uint32_t resetBits){ + return i2cDebug(i2c,setBits,resetBits); +} + +bool TwoWire::busy(void){ + return ((i2cGetStatus(i2c) & 16 )==16); +} + +TwoWire Wire = TwoWire(0); +TwoWire Wire1 = TwoWire(1); diff --git a/MCUME_esp32/espvectrex/components/Wire/Wire.h b/MCUME_esp32/espvectrex/components/Wire/Wire.h new file mode 100644 index 0000000..0420b2e --- /dev/null +++ b/MCUME_esp32/espvectrex/components/Wire/Wire.h @@ -0,0 +1,132 @@ +/* + TwoWire.h - TWI/I2C library for Arduino & Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts + Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support + Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support + Modified November 2017 by Chuck Todd to use ISR and increase stability. +*/ + +#ifndef TwoWire_h +#define TwoWire_h + +#include "esp32-hal-i2c.h" +#include "freertos/FreeRTOS.h" +#include "freertos/queue.h" + + + +#define SDA (gpio_num_t)4 +#define SCL (gpio_num_t)5 + + +#define STICKBREAKER V1.0.1 +#define I2C_BUFFER_LENGTH 128 +typedef void(*user_onRequest)(void); +typedef void(*user_onReceive)(uint8_t*, int); + +class TwoWire +{ +protected: + uint8_t num; + int8_t sda; + int8_t scl; + i2c_t * i2c; + + uint8_t rxBuffer[I2C_BUFFER_LENGTH]; + uint16_t rxIndex; + uint16_t rxLength; + uint16_t rxQueued; //@stickBreaker + + uint8_t txBuffer[I2C_BUFFER_LENGTH]; + uint16_t txIndex; + uint16_t txLength; + uint16_t txAddress; + uint16_t txQueued; //@stickbreaker + + uint8_t transmitting; + /* slave Mode, not yet Stickbreaker + static user_onRequest uReq[2]; + static user_onReceive uRcv[2]; + void onRequestService(void); + void onReceiveService(uint8_t*, int); + */ + i2c_err_t last_error; // @stickBreaker from esp32-hal-i2c.h + uint16_t _timeOutMillis; + +public: + TwoWire(uint8_t bus_num); + ~TwoWire(); + bool begin(int sda=-1, int scl=-1, uint32_t frequency=0); + + void setClock(uint32_t frequency); // change bus clock without initing hardware + size_t getClock(); // current bus clock rate in hz + + void setTimeOut(uint16_t timeOutMillis); + uint16_t getTimeOut(); + + uint8_t lastError(); + char * getErrorText(uint8_t err); + + //@stickBreaker for big blocks and ISR model + i2c_err_t writeTransmission(uint16_t address, uint8_t* buff, uint16_t size, bool sendStop=true); + i2c_err_t readTransmission(uint16_t address, uint8_t* buff, uint16_t size, bool sendStop=true, uint32_t *readCount=NULL); + + void beginTransmission(uint16_t address); + void beginTransmission(uint8_t address); + void beginTransmission(int address); + + uint8_t endTransmission(bool sendStop); + uint8_t endTransmission(void); + + uint8_t requestFrom(uint16_t address, uint8_t size, bool sendStop); + uint8_t requestFrom(uint16_t address, uint8_t size, uint8_t sendStop); + uint8_t requestFrom(uint16_t address, uint8_t size); + uint8_t requestFrom(uint8_t address, uint8_t size, uint8_t sendStop); + uint8_t requestFrom(uint8_t address, uint8_t size); + uint8_t requestFrom(int address, int size, int sendStop); + uint8_t requestFrom(int address, int size); + + size_t write(uint8_t); + size_t write(const uint8_t *, size_t); + int available(void); + int read(void); + int peek(void); + void flush(void); + + + + void onReceive( void (*)(int) ); + void onRequest( void (*)(void) ); + + uint32_t setDebugFlags( uint32_t setBits, uint32_t resetBits); + bool busy(); +}; + +extern TwoWire Wire; +extern TwoWire Wire1; + + +/* +V1.0.1 02AUG2018 First Fix after release, Correct ReSTART handling, change Debug control, change begin() + to a function, this allow reporting if bus cannot be initialized, Wire.begin() can be used to recover + a hung bus busy condition. +V0.2.2 13APR2018 preserve custom SCL,SDA,Frequency when no parameters passed to begin() +V0.2.1 15MAR2018 Hardware reset, Glitch prevention, adding destructor for second i2c testing +*/ +#endif diff --git a/MCUME_esp32/espvectrex/components/Wire/component.mk b/MCUME_esp32/espvectrex/components/Wire/component.mk new file mode 100644 index 0000000..61ff442 --- /dev/null +++ b/MCUME_esp32/espvectrex/components/Wire/component.mk @@ -0,0 +1,11 @@ +# +# Main component makefile. +# +# This Makefile can be left empty. By default, it will take the sources in the +# src/ directory, compile them and link them into lib(subdirectory_name).a +# in the build directory. This behaviour is entirely configurable, +# please read the ESP-IDF documents if you need to do this. +# + +COMPONENT_ADD_INCLUDEDIRS := . +COMPONENT_SRCDIRS := . \ No newline at end of file diff --git a/MCUME_esp32/espvectrex/components/Wire/esp32-hal-gpio.c b/MCUME_esp32/espvectrex/components/Wire/esp32-hal-gpio.c new file mode 100644 index 0000000..999113f --- /dev/null +++ b/MCUME_esp32/espvectrex/components/Wire/esp32-hal-gpio.c @@ -0,0 +1,309 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include "stdint.h" +#include "esp32-hal-gpio.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "rom/ets_sys.h" +#include "esp_attr.h" +#include "esp_intr.h" +#include "rom/gpio.h" +#include "soc/gpio_reg.h" +#include "soc/io_mux_reg.h" +#include "soc/gpio_struct.h" +#include "soc/rtc_io_reg.h" +#include "esp_system.h" + +#define ESP_REG(addr) *((volatile uint32_t *)(addr)) + +const int8_t esp32_adc2gpio[20] = {36, 37, 38, 39, 32, 33, 34, 35, -1, -1, 4, 0, 2, 15, 13, 12, 14, 27, 25, 26}; + +const DRAM_ATTR esp32_gpioMux_t esp32_gpioMux[GPIO_PIN_COUNT]={ + {0x44, 11, 11, 1}, + {0x88, -1, -1, -1}, + {0x40, 12, 12, 2}, + {0x84, -1, -1, -1}, + {0x48, 10, 10, 0}, + {0x6c, -1, -1, -1}, + {0x60, -1, -1, -1}, + {0x64, -1, -1, -1}, + {0x68, -1, -1, -1}, + {0x54, -1, -1, -1}, + {0x58, -1, -1, -1}, + {0x5c, -1, -1, -1}, + {0x34, 15, 15, 5}, + {0x38, 14, 14, 4}, + {0x30, 16, 16, 6}, + {0x3c, 13, 13, 3}, + {0x4c, -1, -1, -1}, + {0x50, -1, -1, -1}, + {0x70, -1, -1, -1}, + {0x74, -1, -1, -1}, + {0x78, -1, -1, -1}, + {0x7c, -1, -1, -1}, + {0x80, -1, -1, -1}, + {0x8c, -1, -1, -1}, + {0, -1, -1, -1}, + {0x24, 6, 18, -1}, //DAC1 + {0x28, 7, 19, -1}, //DAC2 + {0x2c, 17, 17, 7}, + {0, -1, -1, -1}, + {0, -1, -1, -1}, + {0, -1, -1, -1}, + {0, -1, -1, -1}, + {0x1c, 9, 4, 9}, + {0x20, 8, 5, 8}, + {0x14, 4, 6, -1}, + {0x18, 5, 7, -1}, + {0x04, 0, 0, -1}, + {0x08, 1, 1, -1}, + {0x0c, 2, 2, -1}, + {0x10, 3, 3, -1} +}; + +typedef void (*voidFuncPtr)(void); +typedef void (*voidFuncPtrArg)(void*); +typedef struct { + voidFuncPtr fn; + void* arg; + bool functional; +} InterruptHandle_t; +static InterruptHandle_t __pinInterruptHandlers[GPIO_PIN_COUNT] = {0,}; + +#include "driver/rtc_io.h" + +extern void IRAM_ATTR __pinMode(uint8_t pin, uint8_t mode) +{ + + if(!digitalPinIsValid(pin)) { + return; + } + + uint32_t rtc_reg = rtc_gpio_desc[pin].reg; + if(mode == ANALOG) { + if(!rtc_reg) { + return;//not rtc pin + } + //lock rtc + uint32_t reg_val = ESP_REG(rtc_reg); + if(reg_val & rtc_gpio_desc[pin].mux){ + return;//already in adc mode + } + reg_val &= ~( + (RTC_IO_TOUCH_PAD1_FUN_SEL_V << rtc_gpio_desc[pin].func) + |rtc_gpio_desc[pin].ie + |rtc_gpio_desc[pin].pullup + |rtc_gpio_desc[pin].pulldown); + ESP_REG(RTC_GPIO_ENABLE_W1TC_REG) = (1 << (rtc_gpio_desc[pin].rtc_num + RTC_GPIO_ENABLE_W1TC_S)); + ESP_REG(rtc_reg) = reg_val | rtc_gpio_desc[pin].mux; + //unlock rtc + ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioMux[pin].reg) = ((uint32_t)2 << MCU_SEL_S) | ((uint32_t)2 << FUN_DRV_S) | FUN_IE; + return; + } + + //RTC pins PULL settings + if(rtc_reg) { + //lock rtc + ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].mux); + if(mode & PULLUP) { + ESP_REG(rtc_reg) = (ESP_REG(rtc_reg) | rtc_gpio_desc[pin].pullup) & ~(rtc_gpio_desc[pin].pulldown); + } else if(mode & PULLDOWN) { + ESP_REG(rtc_reg) = (ESP_REG(rtc_reg) | rtc_gpio_desc[pin].pulldown) & ~(rtc_gpio_desc[pin].pullup); + } else { + ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].pullup | rtc_gpio_desc[pin].pulldown); + } + //unlock rtc + } + + uint32_t pinFunction = 0, pinControl = 0; + + //lock gpio + if(mode & INPUT) { + if(pin < 32) { + GPIO.enable_w1tc = ((uint32_t)1 << pin); + } else { + GPIO.enable1_w1tc.val = ((uint32_t)1 << (pin - 32)); + } + } else if(mode & OUTPUT) { + if(pin > 33){ + //unlock gpio + return;//pins above 33 can be only inputs + } else if(pin < 32) { + GPIO.enable_w1ts = ((uint32_t)1 << pin); + } else { + GPIO.enable1_w1ts.val = ((uint32_t)1 << (pin - 32)); + } + } + + if(mode & PULLUP) { + pinFunction |= FUN_PU; + } else if(mode & PULLDOWN) { + pinFunction |= FUN_PD; + } + + pinFunction |= ((uint32_t)2 << FUN_DRV_S);//what are the drivers? + pinFunction |= FUN_IE;//input enable but required for output as well? + + if(mode & (INPUT | OUTPUT)) { + pinFunction |= ((uint32_t)2 << MCU_SEL_S); + } else if(mode == SPECIAL) { + pinFunction |= ((uint32_t)(((pin)==1||(pin)==3)?0:1) << MCU_SEL_S); + } else { + pinFunction |= ((uint32_t)(mode >> 5) << MCU_SEL_S); + } + + ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioMux[pin].reg) = pinFunction; + + if(mode & OPEN_DRAIN) { + pinControl = (1 << GPIO_PIN0_PAD_DRIVER_S); + } + + GPIO.pin[pin].val = pinControl; + //unlock gpio +} + +extern void IRAM_ATTR __digitalWrite(uint8_t pin, uint8_t val) +{ + if(val) { + if(pin < 32) { + GPIO.out_w1ts = ((uint32_t)1 << pin); + } else if(pin < 34) { + GPIO.out1_w1ts.val = ((uint32_t)1 << (pin - 32)); + } + } else { + if(pin < 32) { + GPIO.out_w1tc = ((uint32_t)1 << pin); + } else if(pin < 34) { + GPIO.out1_w1tc.val = ((uint32_t)1 << (pin - 32)); + } + } +} + +extern int IRAM_ATTR __digitalRead(uint8_t pin) +{ + if(pin < 32) { + return (GPIO.in >> pin) & 0x1; + } else if(pin < 40) { + return (GPIO.in1.val >> (pin - 32)) & 0x1; + } + return 0; +} + +static intr_handle_t gpio_intr_handle = NULL; + +static void IRAM_ATTR __onPinInterrupt() +{ + uint32_t gpio_intr_status_l=0; + uint32_t gpio_intr_status_h=0; + + gpio_intr_status_l = GPIO.status; + gpio_intr_status_h = GPIO.status1.val; + GPIO.status_w1tc = gpio_intr_status_l;//Clear intr for gpio0-gpio31 + GPIO.status1_w1tc.val = gpio_intr_status_h;//Clear intr for gpio32-39 + + uint8_t pin=0; + if(gpio_intr_status_l) { + do { + if(gpio_intr_status_l & ((uint32_t)1 << pin)) { + if(__pinInterruptHandlers[pin].fn) { + if(__pinInterruptHandlers[pin].arg){ + ((voidFuncPtrArg)__pinInterruptHandlers[pin].fn)(__pinInterruptHandlers[pin].arg); + } else { + __pinInterruptHandlers[pin].fn(); + } + } + } + } while(++pin<32); + } + if(gpio_intr_status_h) { + pin=32; + do { + if(gpio_intr_status_h & ((uint32_t)1 << (pin - 32))) { + if(__pinInterruptHandlers[pin].fn) { + if(__pinInterruptHandlers[pin].arg){ + ((voidFuncPtrArg)__pinInterruptHandlers[pin].fn)(__pinInterruptHandlers[pin].arg); + } else { + __pinInterruptHandlers[pin].fn(); + } + } + } + } while(++pin + +#define NOP() asm volatile ("nop") + +unsigned long IRAM_ATTR micros() +{ + return (unsigned long) esp_timer_get_time(); +} + +unsigned long IRAM_ATTR millis() +{ + return (unsigned long) (esp_timer_get_time() / 1000); +} + +void delay(uint32_t ms) +{ + vTaskDelay(ms / portTICK_PERIOD_MS); +} + +void IRAM_ATTR delayMicroseconds(uint32_t us) +{ + uint32_t m = micros(); + if(us){ + uint32_t e = (m + us); + if(m > e){ //overflow + while(micros() > e){ + NOP(); + } + } + while(micros() < e){ + NOP(); + } + } +} +//#define I2C_DEV(i) (volatile i2c_dev_t *)((i)?DR_REG_I2C1_EXT_BASE:DR_REG_I2C_EXT_BASE) +//#define I2C_DEV(i) ((i2c_dev_t *)(REG_I2C_BASE(i))) +#define I2C_SCL_IDX(p) ((p==0)?I2CEXT0_SCL_OUT_IDX:((p==1)?I2CEXT1_SCL_OUT_IDX:0)) +#define I2C_SDA_IDX(p) ((p==0)?I2CEXT0_SDA_OUT_IDX:((p==1)?I2CEXT1_SDA_OUT_IDX:0)) + +#define DR_REG_I2C_EXT_BASE_FIXED 0x60013000 +#define DR_REG_I2C1_EXT_BASE_FIXED 0x60027000 + +/* Stickbreaker ISR mode debug support + +ENABLE_I2C_DEBUG_BUFFER + Enable debug interrupt history buffer, fifoTx history buffer. + Setting this define will result in 2570 bytes of RAM being used whenever CORE_DEBUG_LEVEL + is higher than WARNING. Unless you are debugging a problem in the I2C subsystem, + I would recommend you leave it commented out. + */ + +//#define ENABLE_I2C_DEBUG_BUFFER + +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) +#define INTBUFFMAX 64 +#define FIFOMAX 512 +static uint32_t intBuff[INTBUFFMAX][3][2]; +static uint32_t intPos[2]= {0,0}; +static uint16_t fifoBuffer[FIFOMAX]; +static uint16_t fifoPos = 0; +#endif + +// start from tools/sdk/include/soc/soc/i2c_struct.h + +typedef union { + struct { + uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ + uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ + uint32_t reserved14: 17; + uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/ + }; + uint32_t val; +} I2C_COMMAND_t; + +typedef union { + struct { + uint32_t rx_fifo_full_thrhd: 5; + uint32_t tx_fifo_empty_thrhd:5; //Config tx_fifo empty threhd value when using apb fifo access * / + uint32_t nonfifo_en: 1; //Set this bit to enble apb nonfifo access. * / + uint32_t fifo_addr_cfg_en: 1; //When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram. * / + uint32_t rx_fifo_rst: 1; //Set this bit to reset rx fifo when using apb fifo access. * / + // chuck while this bit is 1, the RX fifo is held in REST, Toggle it * / + uint32_t tx_fifo_rst: 1; //Set this bit to reset tx fifo when using apb fifo access. * / + // chuck while this bit is 1, the TX fifo is held in REST, Toggle it * / + uint32_t nonfifo_rx_thres: 6; //when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.* / + uint32_t nonfifo_tx_thres: 6; //when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data. * / + uint32_t reserved26: 6; + }; + uint32_t val; +} I2C_FIFO_CONF_t; + +typedef union { + struct { + uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/ + uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/ + uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/ + uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } I2C_FIFO_ST_t; + +// end from tools/sdk/include/soc/soc/i2c_struct.h + +// sync between dispatch(i2cProcQueue) and worker(i2c_isr_handler_default) +typedef enum { + //I2C_NONE=0, + I2C_STARTUP=1, + I2C_RUNNING, + I2C_DONE +} I2C_STAGE_t; + +typedef enum { + I2C_NONE=0, + I2C_MASTER, + I2C_SLAVE, + I2C_MASTERSLAVE +} I2C_MODE_t; + +// internal Error condition +typedef enum { + // I2C_NONE=0, + I2C_OK=1, + I2C_ERROR, + I2C_ADDR_NAK, + I2C_DATA_NAK, + I2C_ARBITRATION, + I2C_TIMEOUT +} I2C_ERROR_t; + +// i2c_event bits for EVENTGROUP bits +// needed to minimize change events, FreeRTOS Daemon overload, so ISR will only set values +// on Exit. Dispatcher will set bits for each dq before/after ISR completion +#define EVENT_ERROR_NAK (BIT(0)) +#define EVENT_ERROR (BIT(1)) +#define EVENT_ERROR_BUS_BUSY (BIT(2)) +#define EVENT_RUNNING (BIT(3)) +#define EVENT_DONE (BIT(4)) +#define EVENT_IN_END (BIT(5)) +#define EVENT_ERROR_PREV (BIT(6)) +#define EVENT_ERROR_TIMEOUT (BIT(7)) +#define EVENT_ERROR_ARBITRATION (BIT(8)) +#define EVENT_ERROR_DATA_NAK (BIT(9)) +#define EVENT_MASK 0x3F + +// control record for each dq entry +typedef union { + struct { + uint32_t addr: 16; // I2C address, if 10bit must have 0x7800 mask applied, else 8bit + uint32_t mode: 1; // transaction direction 0 write, 1 read + uint32_t stop: 1; // sendStop 0 no, 1 yes + uint32_t startCmdSent: 1; // START cmd has been added to command[] + uint32_t addrCmdSent: 1; // addr WRITE cmd has been added to command[] + uint32_t dataCmdSent: 1; // all necessary DATA(READ/WRITE) cmds added to command[] + uint32_t stopCmdSent: 1; // completed all necessary commands + uint32_t addrReq: 2; // number of addr bytes need to send address + uint32_t addrSent: 2; // number of addr bytes added to FIFO + uint32_t reserved_31: 6; + }; + uint32_t val; +} I2C_DATA_CTRL_t; + +// individual dq element +typedef struct { + uint8_t *data; // data pointer for read/write buffer + uint16_t length; // size of data buffer + uint16_t position; // current position for next char in buffer (lock, portMAX_DELAY) != pdPASS) +#define I2C_MUTEX_UNLOCK() xSemaphoreGive(i2c->lock) + +static i2c_t _i2c_bus_array[2] = { + {(volatile i2c_dev_t *)(DR_REG_I2C_EXT_BASE_FIXED), NULL, 0, -1, -1, I2C_NONE,I2C_NONE,I2C_ERROR_OK,NULL,NULL,NULL,0,0,0,0,0,0}, + {(volatile i2c_dev_t *)(DR_REG_I2C1_EXT_BASE_FIXED), NULL, 1, -1, -1,I2C_NONE,I2C_NONE,I2C_ERROR_OK,NULL,NULL,NULL,0,0,0,0,0,0} +}; +#endif + +/* + * index - command index (0 to 15) + * op_code - is the command + * byte_num - This register is to store the amounts of data that is read and written. byte_num in RSTART, STOP, END is null. + * ack_val - Each data byte is terminated by an ACK bit used to set the bit level. + * ack_exp - This bit is to set an expected ACK value for the transmitter. + * ack_check - This bit is to decide whether the transmitter checks ACK bit. 1 means yes and 0 means no. + * */ + + +/* Stickbreaker ISR mode debug support + */ +static void IRAM_ATTR i2cDumpCmdQueue(i2c_t *i2c) +{ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR)&&(defined ENABLE_I2C_DEBUG_BUFFER) + static const char * const cmdName[] ={"RSTART","WRITE","READ","STOP","END"}; + uint8_t i=0; + while(i<16) { + I2C_COMMAND_t c; + c.val=i2c->dev->command[i].val; + i++; + } +#endif +} + +/* Stickbreaker ISR mode debug support + */ +static void i2cDumpDqData(i2c_t * i2c) +{ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER) + uint16_t a=0; + char buff[140]; + I2C_DATA_QUEUE_t *tdq; + int digits=0,lenDigits=0; + a = i2c->queueCount; + while(a>0) { + digits++; + a /= 10; + } + while(aqueueCount) { // find maximum number of len decimal digits for formatting + if (i2c->dq[a].length > lenDigits ) lenDigits = i2c->dq[a].length; + a++; + } + a=0; + while(lenDigits>0){ + a++; + lenDigits /= 10; + } + lenDigits = a; + a = 0; + while(aqueueCount) { + tdq=&i2c->dq[a]; + char buf1[10],buf2[10]; + sprintf(buf1,"%0*d",lenDigits,tdq->length); + sprintf(buf2,"%0*d",lenDigits,tdq->position); + (tdq->ctrl.addr>0x100)?"10":"7", + (tdq->ctrl.addr>0x100)?(((tdq->ctrl.addr&0x600)>>1)|(tdq->ctrl.addr&0xff)):(tdq->ctrl.addr>>1), + (tdq->ctrl.mode)?'R':'W', + (tdq->ctrl.stop)?"STOP":"", + tdq->data, + buf1,buf2, + tdq->ctrl.startCmdSent,tdq->ctrl.addrCmdSent,tdq->ctrl.dataCmdSent,(tdq->ctrl.stop)?tdq->ctrl.stopCmdSent:0,tdq->ctrl.addrSent + ); + uint16_t offset = 0; + while(offsetlength) { + memset(buff,' ',140); + buff[139]='\0'; + uint16_t i = 0,j; + j=sprintf(buff,"0x%04x: ",offset); + while((i<32)&&(offset < tdq->length)) { + char ch = tdq->data[offset]; + sprintf((char*)&buff[(i*3)+41],"%02x ",ch); + if((ch<32)||(ch>126)) { + ch='.'; + } + j+=sprintf((char*)&buff[j],"%c",ch); + buff[j]=' '; + i++; + offset++; + } + } + a++; + } +#endif +} + +static void i2cDumpI2c(i2c_t * i2c) +{ +#if !CONFIG_DISABLE_HAL_LOCKS +#endif + + if(i2c->dq) { + i2cDumpDqData(i2c); + } +} + +static void i2cDumpInts(uint8_t num) +{ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + + uint32_t b; + for(uint32_t a=1; a<=INTBUFFMAX; a++) { + b=(a+intPos[num])%INTBUFFMAX; + if(intBuff[b][0][num]!=0) { + //log_i("[%02d]\t0x%04x\t0x%04x\t0x%04x\t0x%04x\t0x%08x",b,((intBuff[b][0][num]>>16)&0xFFFF),(intBuff[b][0][num]&0xFFFF),((intBuff[b][1][num]>>16)&0xFFFF),(intBuff[b][1][num]&0xFFFF),intBuff[b][2][num]); + } + } +#else +#endif +} + +static void IRAM_ATTR i2cDumpStatus(i2c_t * i2c){ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER) + typedef union { + struct { + uint32_t ack_rec: 1; /*This register stores the value of ACK bit.*/ + uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write slave.*/ + uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/ + uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes to high level.*/ + uint32_t bus_busy: 1; /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ + uint32_t slave_addressed: 1; /*when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level.*/ + uint32_t byte_trans: 1; /*This register changes to high level when one byte is transferred.*/ + uint32_t reserved7: 1; + uint32_t rx_fifo_cnt: 6; /*This register represent the amount of data need to send.*/ + uint32_t reserved14: 4; + uint32_t tx_fifo_cnt: 6; /*This register stores the amount of received data in ram.*/ + uint32_t scl_main_state_last: 3; /*This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ + uint32_t reserved27: 1; + uint32_t scl_state_last: 3; /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } status_reg; + + status_reg sr; + sr.val= i2c->dev->status_reg.val; + +#endif +} + +static void i2cDumpFifo(i2c_t * i2c){ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER) +char buf[64]; +uint16_t k = 0; +uint16_t i = fifoPos+1; + i %=FIFOMAX; +while((fifoBuffer[i]==0)&&(i!=fifoPos)){ + i++; + i %=FIFOMAX; +} +if(i != fifoPos){// actual data + do{ + if(fifoBuffer[i] & 0x8000){ // address byte + if(fifoBuffer[i] & 0x100) { // read + if(fifoBuffer[i] & 0x1) { // valid read dev id + k+= sprintf(&buf[k],"READ 0x%02X",(fifoBuffer[i]&0xff)>>1); + } else { // invalid read dev id + k+= sprintf(&buf[k],"Bad READ 0x%02X",(fifoBuffer[i]&0xff)); + } + } else { // write + if(fifoBuffer[i] & 0x1) { // bad write dev id + k+= sprintf(&buf[k],"bad WRITE 0x%02X",(fifoBuffer[i]&0xff)); + } else { // good Write + k+= sprintf(&buf[k],"WRITE 0x%02X",(fifoBuffer[i]&0xff)>>1); + } + } + } else k += sprintf(&buf[k],"% 4X ",fifoBuffer[i]); + + i++; + i %= FIFOMAX; + bool outBuffer=false; + if( fifoBuffer[i] & 0x8000){ + outBuffer=true; + k=0; + } + outBuffer = false; + if(k>50) { + k=sprintf(buf,"-> "); + } + }while( i!= fifoPos); +} +#endif +} + +static void IRAM_ATTR i2cTriggerDumps(i2c_t * i2c, uint8_t trigger, const char locus[]){ +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER) + if( trigger ){ + //log_i("%s",locus); + if(trigger & 1) i2cDumpI2c(i2c); + if(trigger & 2) i2cDumpInts(i2c->num); + if(trigger & 4) i2cDumpCmdQueue(i2c); + if(trigger & 8) i2cDumpStatus(i2c); + if(trigger & 16) i2cDumpFifo(i2c); + } +#endif +} + // end of debug support routines + +static void IRAM_ATTR i2cSetCmd(i2c_t * i2c, uint8_t index, uint8_t op_code, uint8_t byte_num, bool ack_val, bool ack_exp, bool ack_check) +{ + I2C_COMMAND_t cmd; + cmd.val=0; + cmd.ack_en = ack_check; + cmd.ack_exp = ack_exp; + cmd.ack_val = ack_val; + cmd.byte_num = byte_num; + cmd.op_code = op_code; + i2c->dev->command[index].val = cmd.val; +} + + +static void IRAM_ATTR fillCmdQueue(i2c_t * i2c, bool INTS) +{ + /* this function is called on initial i2cProcQueue() or when a I2C_END_DETECT_INT occurs + */ + uint16_t cmdIdx = 0; + uint16_t qp = i2c->queuePos; // all queues before queuePos have been completely processed, + // so look start by checking the 'current queue' so see if it needs commands added to + // hardware peripheral command list. walk through each queue entry until all queues have been + // checked + bool done; + bool needMoreCmds = false; + bool ena_rx=false; // if we add a read op, better enable Rx_Fifo IRQ + bool ena_tx=false; // if we add a Write op, better enable TX_Fifo IRQ + + while(!needMoreCmds&&(qp < i2c->queueCount)) { // check if more possible cmds + if(i2c->dq[qp].ctrl.stopCmdSent) {// marks that all required cmds[] have been added to peripheral + qp++; + } else { + needMoreCmds=true; + } + } + + done=(!needMoreCmds)||(cmdIdx>14); + + while(!done) { // fill the command[] until either 0..14 filled or out of cmds and last cmd is STOP + //CMD START + I2C_DATA_QUEUE_t *tdq=&i2c->dq[qp]; // simpler coding + + if((!tdq->ctrl.startCmdSent) && (cmdIdx < 14)) { // has this dq element's START command been added? + // (cmdIdx<14) because a START op cannot directly precede an END op, else a time out cascade occurs + i2cSetCmd(i2c, cmdIdx++, I2C_CMD_RSTART, 0, false, false, false); + tdq->ctrl.startCmdSent=1; + } + + //CMD WRITE ADDRESS + if((!done)&&(tdq->ctrl.startCmdSent)) { // have to leave room for continue(END), and START must have been sent! + if(!tdq->ctrl.addrCmdSent) { + i2cSetCmd(i2c, cmdIdx++, I2C_CMD_WRITE, tdq->ctrl.addrReq, false, false, true); //load address in cmdlist, validate (low) ack + tdq->ctrl.addrCmdSent=1; + done =(cmdIdx>14); + ena_tx=true; // tx Data necessary + } + } + + /* Can I have another Sir? + ALL CMD queues must be terminated with either END or STOP. + + If END is used, when refilling the cmd[] next time, no entries from END to [15] can be used. + AND the cmd[] must be filled starting at [0] with commands. Either fill all 15 [0]..[14] and leave the + END in [15] or include a STOP in one of the positions [0]..[14]. Any entries after a STOP are IGNORED by the StateMachine. + The END operation does not complete until ctr->trans_start=1 has been issued. + + So, only refill from [0]..[14], leave [15] for a continuation(END) if necessary. + As a corollary, once END exists in [15], you do not need to overwrite it for the + next continuation. It is never modified. But, I update it every time because it might + actually be the first time! + + 23NOV17 START cannot proceed END. if START is in[14], END cannot be in [15]. + So, if END is moved to [14], [14] and [15] can no longer be used for anything other than END. + If a START is found in [14] then a prior READ or WRITE must be expanded so that there is no START element in [14]. + */ + + if((!done)&&(tdq->ctrl.addrCmdSent)) { //room in command[] for at least One data (read/Write) cmd + uint8_t blkSize=0; // max is 255 + while(( tdq->cmdBytesNeeded > tdq->ctrl.mode )&&(!done )) { // more bytes needed and room in cmd queue, leave room for END + blkSize = (tdq->cmdBytesNeeded > 255)?255:(tdq->cmdBytesNeeded - tdq->ctrl.mode); // Last read cmd needs different ACK setting, so leave 1 byte remainder on reads + tdq->cmdBytesNeeded -= blkSize; + if(tdq->ctrl.mode==1) { //read mode + i2cSetCmd(i2c, (cmdIdx)++, I2C_CMD_READ, blkSize,false,false,false); // read cmd, this can't be the last read. + ena_rx=true; // need to enable rxFifo IRQ + } else { // write + i2cSetCmd(i2c, cmdIdx++, I2C_CMD_WRITE, blkSize, false, false, true); // check for Nak + ena_tx=true; // need to enable txFifo IRQ + } + done = cmdIdx>14; //have to leave room for END + } + + if(!done) { // buffer is not filled completely + if((tdq->ctrl.mode==1)&&(tdq->cmdBytesNeeded==1)) { //special last read byte NAK + i2cSetCmd(i2c, (cmdIdx)++, I2C_CMD_READ, 1,true,false,false); + // send NAK to mark end of read + tdq->cmdBytesNeeded=0; + done = cmdIdx > 14; + ena_rx=true; + } + } + + tdq->ctrl.dataCmdSent=(tdq->cmdBytesNeeded==0); // enough command[] to send all data + + if((!done)&&(tdq->ctrl.dataCmdSent)) { // possibly add stop + if(!tdq->ctrl.stopCmdSent){ + if(tdq->ctrl.stop) { //send a stop + i2cSetCmd(i2c, (cmdIdx)++,I2C_CMD_STOP,0,false,false,false); + done = cmdIdx > 14; + } + tdq->ctrl.stopCmdSent = 1; + } + } + } + + if((cmdIdx==14)&&(!tdq->ctrl.startCmdSent)) { + // START would have preceded END, causes SM TIMEOUT + // need to stretch out a prior WRITE or READ to two Command[] elements + done = false; // reuse it + uint16_t i = 13; // start working back until a READ/WRITE has >1 numBytes + cmdIdx =15; + while(!done) { + i2c->dev->command[i+1].val = i2c->dev->command[i].val; // push it down + if (((i2c->dev->command[i].op_code == 1)||(i2c->dev->command[i].op_code==2))) { + /* add a dummy read/write cmd[] with num_bytes set to zero,just a place holder in the cmd[]list + */ + i2c->dev->command[i].byte_num = 0; + done = true; + + } else { + if(i > 0) { + i--; + } else { // unable to stretch, fatal + i2cDumpCmdQueue(i2c); + done = true; + } + } + } + + } + + + if(cmdIdx==15) { //need continuation, even if STOP is in 14, it will not matter + // cmd buffer is almost full, Add END as a continuation feature + i2cSetCmd(i2c, (cmdIdx)++,I2C_CMD_END, 0,false,false,false); + i2c->dev->int_ena.end_detect=1; + i2c->dev->int_clr.end_detect=1; + done = true; + } + + if(!done) { + if(tdq->ctrl.stopCmdSent) { // this queue element has been completely added to command[] buffer + qp++; + if(qp < i2c->queueCount) { + tdq = &i2c->dq[qp]; + } else { + done = true; + } + } + } + + }// while(!done) + if(INTS) { // don't want to prematurely enable fifo ints until ISR is ready to handle them. + if(ena_rx) { + i2c->dev->int_ena.rx_fifo_full = 1; + } + if(ena_tx) { + i2c->dev->int_ena.tx_fifo_empty = 1; + } + } +} + +static void IRAM_ATTR fillTxFifo(i2c_t * i2c) +{ + /* + 12/01/2017 The Fifo's are independent, 32 bytes of tx and 32 bytes of Rx. + overlap is not an issue, just keep them full/empty the status_reg.xx_fifo_cnt + tells the truth. And the INT's fire correctly + */ + uint16_t a=i2c->queuePos; // currently executing dq, + bool full=!(i2c->dev->status_reg.tx_fifo_cnt<31); + uint8_t cnt; + bool rxQueueEncountered = false; + while((a < i2c->queueCount) && !full) { + I2C_DATA_QUEUE_t *tdq = &i2c->dq[a]; + cnt=0; + // add to address to fifo ctrl.addr already has R/W bit positioned correctly + if(tdq->ctrl.addrSent < tdq->ctrl.addrReq) { // need to send address bytes + if(tdq->ctrl.addrReq==2) { //10bit + if(tdq->ctrl.addrSent==0) { //10bit highbyte needs sent + if(!full) { // room in fifo + i2c->dev->fifo_data.val = ((tdq->ctrl.addr>>8)&0xFF); + cnt++; + tdq->ctrl.addrSent=1; //10bit highbyte sent + } + } + full=!(i2c->dev->status_reg.tx_fifo_cnt<31); + + if(tdq->ctrl.addrSent==1) { //10bit Lowbyte needs sent + if(!full) { // room in fifo + i2c->dev->fifo_data.val = tdq->ctrl.addr&0xFF; + cnt++; + tdq->ctrl.addrSent=2; //10bit lowbyte sent + } + } + } else { // 7bit} + if(tdq->ctrl.addrSent==0) { // 7bit Lowbyte needs sent + if(!full) { // room in fifo + i2c->dev->fifo_data.val = tdq->ctrl.addr&0xFF; + cnt++; + tdq->ctrl.addrSent=1; // 7bit lowbyte sent +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + uint16_t a = 0x8000 | tdq->ctrl.addr | (tdq->ctrl.mode<<8); + fifoBuffer[fifoPos++] = a; + fifoPos %= FIFOMAX; +#endif + } + } + } + } + // add write data to fifo + if(tdq->ctrl.mode==0) { // write + if(tdq->ctrl.addrSent == tdq->ctrl.addrReq) { //address has been sent, is Write Mode! + uint32_t moveCnt = 32 - i2c->dev->status_reg.tx_fifo_cnt; // how much room in txFifo? + while(( moveCnt>0)&&(tdq->position < tdq->length)) { +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + fifoBuffer[fifoPos++] = tdq->data[tdq->position]; + fifoPos %= FIFOMAX; +#endif + i2c->dev->fifo_data.val = tdq->data[tdq->position++]; + cnt++; + moveCnt--; + + } + } + } else { // read Queue Encountered, can't update QueuePos past this point, emptyRxfifo will do it + if( ! rxQueueEncountered ) { + rxQueueEncountered = true; + if(a > i2c->queuePos){ + i2c->queuePos = a; + } + } + } +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + + // update debug buffer tx counts + cnt += intBuff[intPos[i2c->num]][1][i2c->num]>>16; + intBuff[intPos[i2c->num]][1][i2c->num] = (intBuff[intPos[i2c->num]][1][i2c->num]&0xFFFF)|(cnt<<16); + +#endif + full=!(i2c->dev->status_reg.tx_fifo_cnt<31); + if(!full) { + a++; // check next buffer for address tx, or write data + } + } + + if(a >= i2c->queueCount ) { // disable TX IRQ, all tx Data has been queued + i2c->dev->int_ena.tx_fifo_empty= 0; + } + + i2c->dev->int_clr.tx_fifo_empty=1; +} + + +static void IRAM_ATTR emptyRxFifo(i2c_t * i2c) +{ + uint32_t d, cnt=0, moveCnt; + + moveCnt = i2c->dev->status_reg.rx_fifo_cnt;//no need to check the reg until this many are read + + while((moveCnt > 0)&&(i2c->queuePos < i2c->queueCount)){ // data to move + + I2C_DATA_QUEUE_t *tdq =&i2c->dq[i2c->queuePos]; //short cut + + while((tdq->position >= tdq->length)&&( i2c->queuePos < i2c->queueCount)){ // find were to store + i2c->queuePos++; + tdq = &i2c->dq[i2c->queuePos]; + } + + if(i2c->queuePos >= i2c->queueCount){ // bad stuff, rx data but no place to put it! + // discard + while(moveCnt>0){ + d = i2c->dev->fifo_data.val; + moveCnt--; + cnt++; + } + break; + } + + if(tdq->ctrl.mode == 1){ // read command + if(moveCnt > (tdq->length - tdq->position)) { //make sure they go in this dq + // part of these reads go into the next dq + moveCnt = (tdq->length - tdq->position); + } + } else {// error + // discard + while(moveCnt>0){ + d = i2c->dev->fifo_data.val; + moveCnt--; + cnt++; + } + break; + } + + while(moveCnt > 0) { // store data + d = i2c->dev->fifo_data.val; + moveCnt--; + cnt++; + tdq->data[tdq->position++] = (d&0xFF); + } + + moveCnt = i2c->dev->status_reg.rx_fifo_cnt; //any more out there? + } + +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&& (defined ENABLE_I2C_DEBUG_BUFFER) + // update Debug rxCount + cnt += (intBuff[intPos[i2c->num]][1][i2c->num])&0xffFF; + intBuff[intPos[i2c->num]][1][i2c->num] = (intBuff[intPos[i2c->num]][1][i2c->num]&0xFFFF0000)|cnt; +#endif +} + +static void IRAM_ATTR i2cIsrExit(i2c_t * i2c,const uint32_t eventCode,bool Fatal) +{ + + switch(eventCode) { + case EVENT_DONE: + i2c->error = I2C_OK; + break; + case EVENT_ERROR_NAK : + i2c->error =I2C_ADDR_NAK; + break; + case EVENT_ERROR_DATA_NAK : + i2c->error =I2C_DATA_NAK; + break; + case EVENT_ERROR_TIMEOUT : + i2c->error = I2C_TIMEOUT; + break; + case EVENT_ERROR_ARBITRATION: + i2c->error = I2C_ARBITRATION; + break; + default : + i2c->error = I2C_ERROR; + } + uint32_t exitCode = EVENT_DONE | eventCode |(Fatal?EVENT_ERROR:0); + if((i2c->queuePos < i2c->queueCount) && (i2c->dq[i2c->queuePos].ctrl.mode == 1)) { + emptyRxFifo(i2c); // grab last few characters + } + i2c->dev->int_ena.val = 0; // shut down interrupts + i2c->dev->int_clr.val = 0x1FFF; + i2c->stage = I2C_DONE; + i2c->exitCode = exitCode; //true eventcode + + portBASE_TYPE HPTaskAwoken = pdFALSE,xResult; + // try to notify Dispatch we are done, + // else the 50ms time out will recover the APP, just a little slower + HPTaskAwoken = pdFALSE; + xResult = xEventGroupSetBitsFromISR(i2c->i2c_event, exitCode, &HPTaskAwoken); + if(xResult == pdPASS) { + if(HPTaskAwoken==pdTRUE) { + portYIELD_FROM_ISR(); + } + } + +} + +static void IRAM_ATTR i2c_update_error_byte_cnt(i2c_t * i2c) +{ +/* i2c_update_error_byte_cnt 07/18/2018 + Only called after an error has occurred, so, most of the time this function is never used. + This function obliterates the need to interrupt monitor each byte transferred, at high bitrates + the byte interrupts were overwhelming the OS. Spurious Interrupts were being generated. + it updates errorByteCnt, errorQueue. + */ + uint16_t a=0; // start at top of DQ, count how many bytes added to tx fifo, and received from rx_fifo. + int16_t bc = 0; + I2C_DATA_QUEUE_t *tdq; + i2c->errorByteCnt = 0; + while( a < i2c->queueCount){ // add up all bytes loaded into fifo's + tdq = &i2c->dq[a]; + i2c->errorByteCnt += tdq->ctrl.addrSent; + i2c->errorByteCnt += tdq->position; + a++; + } + // now errorByteCnt contains total bytes moved into and out of FIFO's + // but, there may still be bytes waiting in Fifo's + i2c->errorByteCnt -= i2c->dev->status_reg.tx_fifo_cnt; // waiting to go out; + i2c->errorByteCnt += i2c->dev->status_reg.rx_fifo_cnt; // already received +// now walk thru DQ again, find which byte is 'current' + bc = i2c->errorByteCnt; + i2c->errorQueue = 0; + while( i2c->errorQueue < i2c->queueCount ){ + tdq = &i2c->dq[i2c->errorQueue]; + if(bc>0){ // not found yet + if( tdq->ctrl.addrSent >= bc){ // in address + bc = -1; // in address + break; + } else { + bc -= tdq->ctrl.addrSent; + if( tdq->length > bc) { // data nak + break; + } else { // count down + bc -= tdq->length; + } + } + } else break; + + i2c->errorQueue++; + } + + i2c->errorByteCnt = bc; + } + +static void IRAM_ATTR i2c_isr_handler_default(void* arg) +{ + i2c_t* p_i2c = (i2c_t*) arg; // recover data + uint32_t activeInt = p_i2c->dev->int_status.val&0x7FF; + + if(p_i2c->stage==I2C_DONE) { //get Out, can't service, not configured + p_i2c->dev->int_ena.val = 0; + p_i2c->dev->int_clr.val = 0x1FFF; +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + uint32_t raw = p_i2c->dev->int_raw.val; + //log_w("eject raw=%p, int=%p",raw,activeInt); +#endif + return; + } + while (activeInt != 0) { // Ordering of 'if(activeInt)' statements is important, don't change + + #if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + if(activeInt==(intBuff[intPos[p_i2c->num]][0][p_i2c->num]&0x1fff)) { + intBuff[intPos[p_i2c->num]][0][p_i2c->num] = (((intBuff[intPos[p_i2c->num]][0][p_i2c->num]>>16)+1)<<16)|activeInt; + } else { + intPos[p_i2c->num]++; + intPos[p_i2c->num] %= INTBUFFMAX; + intBuff[intPos[p_i2c->num]][0][p_i2c->num] = (1<<16) | activeInt; + intBuff[intPos[p_i2c->num]][1][p_i2c->num] = 0; + } + + intBuff[intPos[p_i2c->num]][2][p_i2c->num] = xTaskGetTickCountFromISR(); // when IRQ fired + +#endif + + if (activeInt & I2C_TRANS_START_INT_ST_M) { + if(p_i2c->stage==I2C_STARTUP) { + p_i2c->stage=I2C_RUNNING; + } + + activeInt &=~I2C_TRANS_START_INT_ST_M; + p_i2c->dev->int_ena.trans_start = 1; // already enabled? why Again? + p_i2c->dev->int_clr.trans_start = 1; // so that will trigger after next 'END' + } + + if (activeInt & I2C_TXFIFO_EMPTY_INT_ST) {//should this be before Trans_start? + fillTxFifo(p_i2c); //fillTxFifo will enable/disable/clear interrupt + activeInt&=~I2C_TXFIFO_EMPTY_INT_ST; + } + + if(activeInt & I2C_RXFIFO_FULL_INT_ST) { + emptyRxFifo(p_i2c); + p_i2c->dev->int_clr.rx_fifo_full=1; + p_i2c->dev->int_ena.rx_fifo_full=1; //why? + + activeInt &=~I2C_RXFIFO_FULL_INT_ST; + } + + if (activeInt & I2C_ACK_ERR_INT_ST_M) {//fatal error, abort i2c service + if (p_i2c->mode == I2C_MASTER) { + i2c_update_error_byte_cnt(p_i2c); // calc which byte caused ack Error, check if address or data + if(p_i2c->errorByteCnt < 0 ) { // address + i2cIsrExit(p_i2c,EVENT_ERROR_NAK,true); + } else { + i2cIsrExit(p_i2c,EVENT_ERROR_DATA_NAK,true); //data + } + } + return; + } + + if (activeInt & I2C_TIME_OUT_INT_ST_M) { + // let Gross timeout occur, Slave may release SCL before the configured timeout expires + // the Statemachine only has a 13.1ms max timout, some Devices >500ms + p_i2c->dev->int_clr.time_out =1; + activeInt &=~I2C_TIME_OUT_INT_ST; + // since a timeout occurred, capture the rxFifo data + emptyRxFifo(p_i2c); + p_i2c->dev->int_clr.rx_fifo_full=1; + p_i2c->dev->int_ena.rx_fifo_full=1; //why? + + } + + if (activeInt & I2C_TRANS_COMPLETE_INT_ST_M) { + p_i2c->dev->int_clr.trans_complete = 1; + i2cIsrExit(p_i2c,EVENT_DONE,false); + return; // no more work to do + /* + // how does slave mode act? + if (p_i2c->mode == I2C_SLAVE) { // STOP detected + // empty fifo + // dispatch callback + */ + } + + if (activeInt & I2C_ARBITRATION_LOST_INT_ST_M) { //fatal + i2cIsrExit(p_i2c,EVENT_ERROR_ARBITRATION,true); + return; // no more work to do + } + + if (activeInt & I2C_SLAVE_TRAN_COMP_INT_ST_M) { + p_i2c->dev->int_clr.slave_tran_comp = 1; + // need to complete this ! + } + + if (activeInt & I2C_END_DETECT_INT_ST_M) { + p_i2c->dev->int_ena.end_detect = 0; + p_i2c->dev->int_clr.end_detect = 1; + p_i2c->dev->ctr.trans_start=0; + fillCmdQueue(p_i2c,true); // enable interrupts + p_i2c->dev->ctr.trans_start=1; // go for it + activeInt&=~I2C_END_DETECT_INT_ST_M; + } + + if(activeInt) { // clear unhandled if possible? What about Disabling interrupt? + p_i2c->dev->int_clr.val = activeInt; + // disable unhandled IRQ, + p_i2c->dev->int_ena.val = p_i2c->dev->int_ena.val & (~activeInt); + } + +// activeInt = p_i2c->dev->int_status.val; // start all over if another interrupt happened +// 01AUG2018 if another interrupt happened, the OS will schedule another interrupt +// this is the source of spurious interrupts + } +} + +/* Stickbreaker added for ISR 11/2017 +functional with Silicon date=0x16042000 + */ +static i2c_err_t i2cAddQueue(i2c_t * i2c,uint8_t mode, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen,bool sendStop, bool dataOnly, EventGroupHandle_t event) +{ + // need to grab a MUTEX for exclusive Queue, + // what about if ISR is running? + + if(i2c==NULL) { + return I2C_ERROR_DEV; + } + + I2C_DATA_QUEUE_t dqx; + dqx.data = dataPtr; + dqx.length = dataLen; + dqx.position = 0; + dqx.cmdBytesNeeded = dataLen; + dqx.ctrl.val = 0; + if( dataOnly) { + /* special case to add a queue data only element. + START and devAddr will not be sent, this dq element can have a STOP. + allows multiple buffers to be used for one transaction. + sequence: normal transaction(sendStop==false), [dataonly(sendStop==false)],dataOnly(sendStop==true) + *** Currently only works with WRITE, final byte NAK an READ will cause a fail between dq buffer elements. (in progress 30JUL2018) + */ + dqx.ctrl.startCmdSent = 1; // mark as already sent + dqx.ctrl.addrCmdSent = 1; + } else { + dqx.ctrl.addrReq = ((i2cDeviceAddr&0xFC00)==0x7800)?2:1; // 10bit or 7bit address + } + dqx.ctrl.addr = i2cDeviceAddr; + dqx.ctrl.mode = mode; + dqx.ctrl.stop= sendStop; + dqx.queueEvent = event; + + if(event) { // an eventGroup exist, so, initialize it + xEventGroupClearBits(event, EVENT_MASK); // all of them + } + + if(i2c->dq!=NULL) { // expand + //log_i("expand"); + I2C_DATA_QUEUE_t* tq =(I2C_DATA_QUEUE_t*)realloc(i2c->dq,sizeof(I2C_DATA_QUEUE_t)*(i2c->queueCount +1)); + if(tq!=NULL) { // ok + i2c->dq = tq; + memmove(&i2c->dq[i2c->queueCount++],&dqx,sizeof(I2C_DATA_QUEUE_t)); + } else { // bad stuff, unable to allocate more memory! + return I2C_ERROR_MEMORY; + } + } else { // first Time + //log_i("new"); + i2c->queueCount=0; + i2c->dq =(I2C_DATA_QUEUE_t*)malloc(sizeof(I2C_DATA_QUEUE_t)); + if(i2c->dq!=NULL) { + memmove(&i2c->dq[i2c->queueCount++],&dqx,sizeof(I2C_DATA_QUEUE_t)); + } else { + return I2C_ERROR_MEMORY; + } + } + return I2C_ERROR_OK; +} + +i2c_err_t i2cAddQueueWrite(i2c_t * i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen,bool sendStop,EventGroupHandle_t event) +{ + return i2cAddQueue(i2c,0,i2cDeviceAddr,dataPtr,dataLen,sendStop,false,event); +} + +i2c_err_t i2cAddQueueRead(i2c_t * i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen,bool sendStop,EventGroupHandle_t event) +{ + //10bit read is kind of weird, first you do a 0byte Write with 10bit + // address, then a ReSTART then a 7bit Read using the the upper 7bit + + // readBit. + + // this might cause an internal register pointer problem with 10bit + // devices, But, Don't have any to test against. + // this is the Industry Standard specification. + + if((i2cDeviceAddr &0xFC00)==0x7800) { // ten bit read + i2c_err_t err = i2cAddQueue(i2c,0,i2cDeviceAddr,NULL,0,false,false,event); + if(err==I2C_ERROR_OK) { + return i2cAddQueue(i2c,1,(i2cDeviceAddr>>8),dataPtr,dataLen,sendStop,false,event); + } else { + return err; + } + } + return i2cAddQueue(i2c,1,i2cDeviceAddr,dataPtr,dataLen,sendStop,false,event); +} + +i2c_err_t i2cProcQueue(i2c_t * i2c, uint32_t *readCount, uint16_t timeOutMillis) +{ + /* do the hard stuff here + install ISR if necessary + setup EventGroup + handle bus busy? + */ + //log_e("procQueue i2c=%p",&i2c); + if(readCount){ //total reads accomplished in all queue elements + *readCount = 0; + } + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + if(i2c->debugFlags & 0xff000000) i2cTriggerDumps(i2c,(i2c->debugFlags>>24),"before ProcQueue"); + if (i2c->dev->status_reg.bus_busy) { // return error, let TwoWire() handle resetting the hardware. + /* if multi master then this if should be changed to this 03/12/2018 + if(multiMaster){// try to let the bus clear by its self + uint32_t timeOutTick = millis(); + while((i2c->dev->status_reg.bus_busy)&&(millis()-timeOutTickdev->status_reg.bus_busy){ // still busy, so die + */ + return I2C_ERROR_BUSY; + } + + I2C_MUTEX_LOCK(); + /* what about co-existence with SLAVE mode? + Should I check if a slaveMode xfer is in progress and hang + until it completes? + if i2c->stage == I2C_RUNNING or I2C_SLAVE_ACTIVE + */ + i2c->stage = I2C_DONE; // until ready + +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER) + for(uint16_t i=0; inum] = 0; + intBuff[i][1][i2c->num] = 0; + intBuff[i][2][i2c->num] = 0; + } + intPos[i2c->num] = 0; + fifoPos = 0; + memset(fifoBuffer,0,FIFOMAX); +#endif + // EventGroup is used to signal transmission completion from ISR + // not always reliable. Sometimes, the FreeRTOS scheduler is maxed out and refuses request + // if that happens, this call hangs until the timeout period expires, then it continues. + if(!i2c->i2c_event) { + i2c->i2c_event = xEventGroupCreate(); + } + if(i2c->i2c_event) { + xEventGroupClearBits(i2c->i2c_event, 0xFF); + } else { // failed to create EventGroup + I2C_MUTEX_UNLOCK(); + return I2C_ERROR_MEMORY; + } + + i2c_err_t reason = I2C_ERROR_OK; + i2c->mode = I2C_MASTER; + i2c->dev->ctr.trans_start=0; // Pause Machine + i2c->dev->timeout.tout = 0xFFFFF; // max 13ms + i2c->dev->int_clr.val = 0x1FFF; // kill them All! + + i2c->dev->ctr.ms_mode = 1; // master! + i2c->queuePos=0; + i2c->errorByteCnt=0; + i2c->errorQueue = 0; + uint32_t totalBytes=0; // total number of bytes to be Moved! + // convert address field to required I2C format + while(i2c->queuePos < i2c->queueCount) { // need to push these address modes upstream, to AddQueue + I2C_DATA_QUEUE_t *tdq = &i2c->dq[i2c->queuePos++]; + uint16_t taddr=0; + if(tdq->ctrl.addrReq ==2) { // 10bit address + taddr =((tdq->ctrl.addr >> 7) & 0xFE) + |tdq->ctrl.mode; + taddr = (taddr <<8) || (tdq->ctrl.addr&0xFF); + } else { // 7bit address + taddr = ((tdq->ctrl.addr<<1)&0xFE) + |tdq->ctrl.mode; + } + tdq->ctrl.addr = taddr; // all fixed with R/W bit + totalBytes += tdq->length + tdq->ctrl.addrReq; // total number of byte to be moved! + } + i2c->queuePos=0; + + fillCmdQueue(i2c,false); // don't enable Tx/RX irq's + // start adding command[], END irq will keep it full + //Data Fifo will be filled after trans_start is issued + i2c->exitCode=0; + + I2C_FIFO_CONF_t f; + f.val = i2c->dev->fifo_conf.val; + f.rx_fifo_rst = 1; // fifo in reset + f.tx_fifo_rst = 1; // fifo in reset + f.nonfifo_en = 0; // use fifo mode + f.nonfifo_tx_thres = 31; + // need to adjust threshold based on I2C clock rate, at 100k, 30 usually works, + // sometimes the emptyRx() actually moves 31 bytes + // it hasn't overflowed yet, I cannot tell if the new byte is added while + // emptyRX() is executing or before? + // let i2cSetFrequency() set thrhds + // f.rx_fifo_full_thrhd = 30; // 30 bytes before INT is issued + // f.tx_fifo_empty_thrhd = 0; + f.fifo_addr_cfg_en = 0; // no directed access + i2c->dev->fifo_conf.val = f.val; // post them all + + f.rx_fifo_rst = 0; // release fifo + f.tx_fifo_rst = 0; + i2c->dev->fifo_conf.val = f.val; // post them all + + i2c->stage = I2C_STARTUP; // everything configured, now start the I2C StateMachine, and + // As soon as interrupts are enabled, the ISR will start handling them. + // it should receive a TXFIFO_EMPTY immediately, even before it + // receives the TRANS_START + + + uint32_t interruptsEnabled = + I2C_ACK_ERR_INT_ENA | // (BIT(10)) Causes Fatal Error Exit + I2C_TRANS_START_INT_ENA | // (BIT(9)) Triggered by trans_start=1, initial,END + I2C_TIME_OUT_INT_ENA | //(BIT(8)) Trigger by SLAVE SCL stretching, NOT an ERROR + I2C_TRANS_COMPLETE_INT_ENA | // (BIT(7)) triggered by STOP, successful exit + I2C_ARBITRATION_LOST_INT_ENA | // (BIT(5)) cause fatal error exit + I2C_SLAVE_TRAN_COMP_INT_ENA | // (BIT(4)) unhandled + I2C_END_DETECT_INT_ENA | // (BIT(3)) refills cmd[] list + I2C_RXFIFO_OVF_INT_ENA | //(BIT(2)) unhandled + I2C_TXFIFO_EMPTY_INT_ENA | // (BIT(1)) triggers fillTxFifo() + I2C_RXFIFO_FULL_INT_ENA; // (BIT(0)) trigger emptyRxFifo() + + i2c->dev->int_ena.val = interruptsEnabled; + + if(!i2c->intr_handle) { // create ISR for either peripheral + // log_i("create ISR %d",i2c->num); + uint32_t ret = 0; + uint32_t flags = ESP_INTR_FLAG_IRAM | //< ISR can be called if cache is disabled + ESP_INTR_FLAG_LOWMED | //< Low and medium prio interrupts. These can be handled in C. + ESP_INTR_FLAG_SHARED; //< Reduce resource requirements, Share interrupts + + if(i2c->num) { + ret = esp_intr_alloc_intrstatus(ETS_I2C_EXT1_INTR_SOURCE, flags, (uint32_t)&i2c->dev->int_status.val, interruptsEnabled, &i2c_isr_handler_default,i2c, &i2c->intr_handle); + } else { + ret = esp_intr_alloc_intrstatus(ETS_I2C_EXT0_INTR_SOURCE, flags, (uint32_t)&i2c->dev->int_status.val, interruptsEnabled, &i2c_isr_handler_default,i2c, &i2c->intr_handle); + } + + if(ret!=ESP_OK) { + I2C_MUTEX_UNLOCK(); + return I2C_ERROR_MEMORY; + } + } + //hang until it completes. + + // how many ticks should it take to transfer totalBytes through the I2C hardware, + // add user supplied timeOutMillis to Calculated Value + + portTickType ticksTimeOut = ((totalBytes*10*1000)/(i2cGetFrequency(i2c))+timeOutMillis)/portTICK_PERIOD_MS; + + i2c->dev->ctr.trans_start=1; // go for it + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR + portTickType tBefore=xTaskGetTickCount(); +#endif + + // wait for ISR to complete the transfer, or until timeOut in case of bus fault, hardware problem + + uint32_t eBits = xEventGroupWaitBits(i2c->i2c_event,EVENT_DONE,pdFALSE,pdTRUE,ticksTimeOut); + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR + portTickType tAfter=xTaskGetTickCount(); +#endif + + + // if xEventGroupSetBitsFromISR() failed, the ISR could have succeeded but never been + // able to mark the success + + if(i2c->exitCode!=eBits) { // try to recover from O/S failure + // log_e("EventGroup Failed:%p!=%p",eBits,i2c->exitCode); + eBits=i2c->exitCode; + } + if((eBits&EVENT_ERROR)||(!(eBits & EVENT_DONE))){ // need accurate errorByteCnt for debug + i2c_update_error_byte_cnt(i2c); + } + + if(!(eBits==EVENT_DONE)&&(eBits&~(EVENT_ERROR_NAK|EVENT_ERROR_DATA_NAK|EVENT_ERROR|EVENT_DONE))) { // not only Done, therefore error, exclude ADDR NAK, DATA_NAK +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO + i2cDumpI2c(i2c); + i2cDumpInts(i2c->num); +#endif + } + + if(eBits&EVENT_DONE) { // no gross timeout + switch(i2c->error) { + case I2C_OK : + reason = I2C_ERROR_OK; + break; + case I2C_ERROR : + reason = I2C_ERROR_DEV; + break; + case I2C_ADDR_NAK: + reason = I2C_ERROR_ACK; + break; + case I2C_DATA_NAK: + reason = I2C_ERROR_ACK; + break; + case I2C_ARBITRATION: + reason = I2C_ERROR_BUS; + break; + case I2C_TIMEOUT: + reason = I2C_ERROR_TIMEOUT; + break; + default : + reason = I2C_ERROR_DEV; + } + } else { // GROSS timeout, shutdown ISR , report Timeout + i2c->stage = I2C_DONE; + i2c->dev->int_ena.val =0; + i2c->dev->int_clr.val = 0x1FFF; + i2c_update_error_byte_cnt(i2c); + if((i2c->errorByteCnt == 0)&&(i2c->errorQueue==0)) { // Bus Busy no bytes Moved + reason = I2C_ERROR_BUSY; + eBits = eBits | EVENT_ERROR_BUS_BUSY|EVENT_ERROR|EVENT_DONE; +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + //log_d(" Busy Timeout start=0x%x, end=0x%x, =%d, max=%d error=%d",tBefore,tAfter,(tAfter-tBefore),ticksTimeOut,i2c->error); + i2cDumpI2c(i2c); + i2cDumpInts(i2c->num); +#endif + } else { // just a timeout, some data made it out or in. + reason = I2C_ERROR_TIMEOUT; + eBits = eBits | EVENT_ERROR_TIMEOUT|EVENT_ERROR|EVENT_DONE; + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + //log_d(" Gross Timeout Dead start=0x%x, end=0x%x, =%d, max=%d error=%d",tBefore,tAfter,(tAfter-tBefore),ticksTimeOut,i2c->error); + i2cDumpI2c(i2c); + i2cDumpInts(i2c->num); +#endif + } + } + + /* offloading all EventGroups to dispatch, EventGroups in ISR is not always successful + 11/20/2017 + if error, need to trigger all succeeding dataQueue events with the EVENT_ERROR_PREV + 07/22/2018 + Need to use the queueEvent value to identify transaction blocks, if an error occurs, + all subsequent queue items with the same queueEvent value will receive the EVENT_ERROR_PREV. + But, ProcQue should re-queue queue items that have a different queueEvent value(different transaction) + This change will support multi-thread i2c usage. Use the queueEvent as the transaction event + identifier. + */ + uint32_t b = 0; + + while(b < i2c->queueCount) { + if(i2c->dq[b].ctrl.mode==1 && readCount) { + *readCount += i2c->dq[b].position; // number of data bytes received + } + if(b < i2c->queuePos) { // before any error + if(i2c->dq[b].queueEvent) { // this data queue element has an EventGroup + xEventGroupSetBits(i2c->dq[b].queueEvent,EVENT_DONE); + } + } else if(b == i2c->queuePos) { // last processed queue + if(i2c->dq[b].queueEvent) { // this data queue element has an EventGroup + xEventGroupSetBits(i2c->dq[b].queueEvent,eBits); + } + } else { // never processed queues + if(i2c->dq[b].queueEvent) { // this data queue element has an EventGroup + xEventGroupSetBits(i2c->dq[b].queueEvent,eBits|EVENT_ERROR_PREV); + } + } + b++; + } + if(i2c->debugFlags & 0x00ff0000) i2cTriggerDumps(i2c,(i2c->debugFlags>>16),"after ProcQueue"); + + I2C_MUTEX_UNLOCK(); + return reason; +} + +static void i2cReleaseISR(i2c_t * i2c) +{ + if(i2c->intr_handle) { + esp_intr_free(i2c->intr_handle); + i2c->intr_handle=NULL; + } +} + +static bool i2cCheckLineState(int8_t sda, int8_t scl){ + if(sda < 0 || scl < 0){ + return false;//return false since there is nothing to do + } + // if the bus is not 'clear' try the cycling SCL until SDA goes High or 9 cycles + digitalWrite(sda, HIGH); + digitalWrite(scl, HIGH); + pinMode(sda, PULLUP|OPEN_DRAIN|INPUT); + pinMode(scl, PULLUP|OPEN_DRAIN|OUTPUT); + + if(!digitalRead(sda) || !digitalRead(scl)) { // bus in busy state + //log_w("invalid state sda(%d)=%d, scl(%d)=%d", sda, digitalRead(sda), scl, digitalRead(scl)); + digitalWrite(scl, HIGH); + for(uint8_t a=0; a<9; a++) { + delayMicroseconds(5); + digitalWrite(scl, LOW); + delayMicroseconds(5); + digitalWrite(scl, HIGH); + if(digitalRead(sda)){ // bus recovered + //log_d("Recovered after %d Cycles",a+1); + break; + } + } + } + + if(!digitalRead(sda) || !digitalRead(scl)) { // bus in busy state + return false; // bus is busy + } + return true; +} + +i2c_err_t i2cAttachSCL(i2c_t * i2c, int8_t scl) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + digitalWrite(scl, HIGH); + pinMode(scl, OPEN_DRAIN | PULLUP | INPUT | OUTPUT); + pinMatrixOutAttach(scl, I2C_SCL_IDX(i2c->num), false, false); + pinMatrixInAttach(scl, I2C_SCL_IDX(i2c->num), false); + return I2C_ERROR_OK; +} + +i2c_err_t i2cDetachSCL(i2c_t * i2c, int8_t scl) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + pinMatrixOutDetach(scl, false, false); + pinMatrixInDetach(I2C_SCL_IDX(i2c->num), false, false); + pinMode(scl, INPUT | PULLUP); + return I2C_ERROR_OK; +} + +i2c_err_t i2cAttachSDA(i2c_t * i2c, int8_t sda) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + digitalWrite(sda, HIGH); + pinMode(sda, OPEN_DRAIN | PULLUP | INPUT | OUTPUT ); + pinMatrixOutAttach(sda, I2C_SDA_IDX(i2c->num), false, false); + pinMatrixInAttach(sda, I2C_SDA_IDX(i2c->num), false); + return I2C_ERROR_OK; +} + +i2c_err_t i2cDetachSDA(i2c_t * i2c, int8_t sda) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + pinMatrixOutDetach(sda, false, false); + pinMatrixInDetach(I2C_SDA_IDX(i2c->num), false, false); + pinMode(sda, INPUT | PULLUP); + return I2C_ERROR_OK; +} + +/* + * PUBLIC API + * */ +// 24Nov17 only supports Master Mode +i2c_t * i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t frequency) //before this is called, pins should be detached, else glitch +{ + //log_v("num=%d sda=%d scl=%d freq=%d",i2c_num, sda, scl, frequency); + if(i2c_num > 1) { + return NULL; + } + + i2c_t * i2c = &_i2c_bus_array[i2c_num]; + + if(i2c->sda >= 0){ + i2cDetachSDA(i2c, i2c->sda); + } + if(i2c->scl >= 0){ + i2cDetachSCL(i2c, i2c->scl); + } + i2c->sda = sda; + i2c->scl = scl; + +#if !CONFIG_DISABLE_HAL_LOCKS + if(i2c->lock == NULL) { + i2c->lock = xSemaphoreCreateMutex(); + if(i2c->lock == NULL) { + return NULL; + } + } +#endif + I2C_MUTEX_LOCK(); + + i2cReleaseISR(i2c); // ISR exists, release it before disabling hardware + + if(frequency == 0) {// don't change existing frequency + frequency = i2cGetFrequency(i2c); + if(frequency == 0) { + frequency = 100000L; // default to 100khz + } + } + + if(i2c_num == 0) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST); //reset hardware + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT0_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST);// release reset + } else { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST); //reset Hardware + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT1_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST); + } + i2c->dev->ctr.val = 0; + i2c->dev->ctr.ms_mode = 1; + i2c->dev->ctr.sda_force_out = 1 ; + i2c->dev->ctr.scl_force_out = 1 ; + i2c->dev->ctr.clk_en = 1; + + //the max clock number of receiving a data + i2c->dev->timeout.tout = 400000;//clocks max=1048575 + //disable apb nonfifo access + i2c->dev->fifo_conf.nonfifo_en = 0; + + i2c->dev->slave_addr.val = 0; + I2C_MUTEX_UNLOCK(); + + i2cSetFrequency(i2c, frequency); // reconfigure + + if(!i2cCheckLineState(i2c->sda, i2c->scl)){ + return NULL; + } + + if(i2c->sda >= 0){ + i2cAttachSDA(i2c, i2c->sda); + } + if(i2c->scl >= 0){ + i2cAttachSCL(i2c, i2c->scl); + } + return i2c; +} + +void i2cRelease(i2c_t *i2c) // release all resources, power down peripheral +{ + I2C_MUTEX_LOCK(); + + if(i2c->sda >= 0){ + i2cDetachSDA(i2c, i2c->sda); + } + if(i2c->scl >= 0){ + i2cDetachSCL(i2c, i2c->scl); + } + + i2cReleaseISR(i2c); + + if(i2c->i2c_event) { + vEventGroupDelete(i2c->i2c_event); + i2c->i2c_event = NULL; + } + + i2cFlush(i2c); + + // reset the I2C hardware and shut off the clock, power it down. + if(i2c->num == 0) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST); //reset hardware + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT0_CLK_EN); // shutdown hardware + } else { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST); //reset Hardware + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT1_CLK_EN); // shutdown Hardware + } + + I2C_MUTEX_UNLOCK(); +} + +i2c_err_t i2cFlush(i2c_t * i2c) +{ + if(i2c==NULL) { + return I2C_ERROR_DEV; + } + i2cTriggerDumps(i2c,i2c->debugFlags & 0xff, "FLUSH"); + + // need to grab a MUTEX for exclusive Queue, + // what out if ISR is running? + i2c_err_t rc=I2C_ERROR_OK; + if(i2c->dq!=NULL) { + // log_i("free"); + // what about EventHandle? + free(i2c->dq); + i2c->dq = NULL; + } + i2c->queueCount=0; + i2c->queuePos=0; + // release Mutex + return rc; +} + +i2c_err_t i2cWrite(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis){ + i2c_err_t last_error = i2cAddQueueWrite(i2c, address, buff, size, sendStop, NULL); + + if(last_error == I2C_ERROR_OK) { //queued + if(sendStop) { //now actually process the queued commands, including READs + last_error = i2cProcQueue(i2c, NULL, timeOutMillis); + if(last_error == I2C_ERROR_BUSY) { // try to clear the bus + if(i2cInit(i2c->num, i2c->sda, i2c->scl, 0)) { + last_error = i2cProcQueue(i2c, NULL, timeOutMillis); + } + } + i2cFlush(i2c); + } else { // stop not received, so wait for I2C stop, + last_error = I2C_ERROR_CONTINUE; + } + } + return last_error; +} + +i2c_err_t i2cRead(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis, uint32_t *readCount){ + i2c_err_t last_error=i2cAddQueueRead(i2c, address, buff, size, sendStop, NULL); + + if(last_error == I2C_ERROR_OK) { //queued + if(sendStop) { //now actually process the queued commands, including READs + last_error = i2cProcQueue(i2c, readCount, timeOutMillis); + if(last_error == I2C_ERROR_BUSY) { // try to clear the bus + if(i2cInit(i2c->num, i2c->sda, i2c->scl, 0)) { + last_error = i2cProcQueue(i2c, readCount, timeOutMillis); + } + } + i2cFlush(i2c); + } else { // stop not received, so wait for I2C stop, + last_error = I2C_ERROR_CONTINUE; + } + } + return last_error; +} + +i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed) +{ + if(i2c == NULL) { + return I2C_ERROR_DEV; + } + I2C_FIFO_CONF_t f; + + uint32_t period = (APB_CLK_FREQ/clk_speed) / 2; + uint32_t halfPeriod = period/2; + uint32_t quarterPeriod = period/4; + + I2C_MUTEX_LOCK(); + + // Adjust Fifo thresholds based on frequency + f.val = i2c->dev->fifo_conf.val; + uint32_t a = (clk_speed / 50000L )+1; + if (a > 24) a=24; + f.rx_fifo_full_thrhd = 32 - a; + f.tx_fifo_empty_thrhd = a; + i2c->dev->fifo_conf.val = f.val; // set thresholds + //log_v("Fifo threshold=%d",a); + + //the clock num during SCL is low level + i2c->dev->scl_low_period.period = period; + //the clock num during SCL is high level + i2c->dev->scl_high_period.period = period; + + //the clock num between the negedge of SDA and negedge of SCL for start mark + i2c->dev->scl_start_hold.time = halfPeriod; + //the clock num between the posedge of SCL and the negedge of SDA for restart mark + i2c->dev->scl_rstart_setup.time = halfPeriod; + + //the clock num after the STOP bit's posedge + i2c->dev->scl_stop_hold.time = halfPeriod; + //the clock num between the posedge of SCL and the posedge of SDA + i2c->dev->scl_stop_setup.time = halfPeriod; + + //the clock num I2C used to hold the data after the negedge of SCL. + i2c->dev->sda_hold.time = quarterPeriod; + //the clock num I2C used to sample data on SDA after the posedge of SCL + i2c->dev->sda_sample.time = quarterPeriod; + I2C_MUTEX_UNLOCK(); + return I2C_ERROR_OK; +} + +uint32_t i2cGetFrequency(i2c_t * i2c) +{ + if(i2c == NULL) { + return 0; + } + uint32_t result = 0; + uint32_t old_count = (i2c->dev->scl_low_period.period+i2c->dev->scl_high_period.period); + if(old_count>0) { + result = APB_CLK_FREQ / old_count; + } else { + result = 0; + } + return result; +} + + +uint32_t i2cDebug(i2c_t * i2c, uint32_t setBits, uint32_t resetBits){ + if(i2c != NULL) { + i2c->debugFlags = ((i2c->debugFlags | setBits) & ~resetBits); + return i2c->debugFlags; + } + return 0; + + } + +uint32_t i2cGetStatus(i2c_t * i2c){ + if(i2c != NULL){ + return i2c->dev->status_reg.val; + } + else return 0; +} +/* todo + 22JUL18 + need to add multi-thread capability, use dq.queueEvent as the group marker. When multiple threads + transactions are present in the same queue, and an error occurs, abort all succeeding unserviced transactions + with the same dq.queueEvent value. Succeeding unserviced transactions with different dq.queueEvent values + can be re-queued and processed independently. + 30JUL18 complete data only queue elements, this will allow transfers to use multiple data blocks, + */ + diff --git a/MCUME_esp32/espvectrex/components/Wire/esp32-hal-i2c.h b/MCUME_esp32/espvectrex/components/Wire/esp32-hal-i2c.h new file mode 100644 index 0000000..1a696ac --- /dev/null +++ b/MCUME_esp32/espvectrex/components/Wire/esp32-hal-i2c.h @@ -0,0 +1,82 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// modified Nov 2017 by Chuck Todd to support Interrupt Driven I/O + +#ifndef _ESP32_HAL_I2C_H_ +#define _ESP32_HAL_I2C_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/event_groups.h" + +// External Wire.h equivalent error Codes +typedef enum { + I2C_ERROR_OK=0, + I2C_ERROR_DEV, + I2C_ERROR_ACK, + I2C_ERROR_TIMEOUT, + I2C_ERROR_BUS, + I2C_ERROR_BUSY, + I2C_ERROR_MEMORY, + I2C_ERROR_CONTINUE, + I2C_ERROR_NO_BEGIN +} i2c_err_t; + +struct i2c_struct_t; +typedef struct i2c_struct_t i2c_t; + +i2c_t * i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t clk_speed); +void i2cRelease(i2c_t *i2c); // free ISR, Free DQ, Power off peripheral clock. Must call i2cInit() to recover +i2c_err_t i2cWrite(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis); +i2c_err_t i2cRead(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis, uint32_t *readCount); +i2c_err_t i2cFlush(i2c_t *i2c); +i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed); +uint32_t i2cGetFrequency(i2c_t * i2c); +uint32_t i2cGetStatus(i2c_t * i2c); // Status register of peripheral + +//Functions below should be used only if well understood +//Might be deprecated and removed in future +i2c_err_t i2cAttachSCL(i2c_t * i2c, int8_t scl); +i2c_err_t i2cDetachSCL(i2c_t * i2c, int8_t scl); +i2c_err_t i2cAttachSDA(i2c_t * i2c, int8_t sda); +i2c_err_t i2cDetachSDA(i2c_t * i2c, int8_t sda); + +//Stickbreakers ISR Support +i2c_err_t i2cProcQueue(i2c_t *i2c, uint32_t *readCount, uint16_t timeOutMillis); +i2c_err_t i2cAddQueueWrite(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen, bool SendStop, EventGroupHandle_t event); +i2c_err_t i2cAddQueueRead(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen, bool SendStop, EventGroupHandle_t event); + +//stickbreaker debug support +uint32_t i2cDebug(i2c_t *, uint32_t setBits, uint32_t resetBits); +// Debug actions have 3 currently defined locus +// 0xXX------ : at entry of ProcQueue +// 0x--XX---- : at exit of ProcQueue +// 0x------XX : at entry of Flush +// +// bit 0 causes DumpI2c to execute +// bit 1 causes DumpInts to execute +// bit 2 causes DumpCmdqueue to execute +// bit 3 causes DumpStatus to execute +// bit 4 causes DumpFifo to execute + +#ifdef __cplusplus +} +#endif + +#endif /* _ESP32_HAL_I2C_H_ */ diff --git a/MCUME_esp32/espvectrex/components/Wire/esp32-hal-matrix.c b/MCUME_esp32/espvectrex/components/Wire/esp32-hal-matrix.c new file mode 100644 index 0000000..93e8849 --- /dev/null +++ b/MCUME_esp32/espvectrex/components/Wire/esp32-hal-matrix.c @@ -0,0 +1,52 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include +#include +#include "esp32-hal-matrix.h" +#include "esp_attr.h" +#include "rom/gpio.h" + + + +#define MATRIX_DETACH_OUT_SIG 0x100 +#define MATRIX_DETACH_IN_LOW_PIN 0x30 +#define MATRIX_DETACH_IN_LOW_HIGH 0x38 + +void IRAM_ATTR pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable) +{ + gpio_matrix_out(pin, function, invertOut, invertEnable); +} + +void IRAM_ATTR pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable) +{ + gpio_matrix_out(pin, MATRIX_DETACH_OUT_SIG, invertOut, invertEnable); +} + +void IRAM_ATTR pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted) +{ + gpio_matrix_in(pin, signal, inverted); +} + +void IRAM_ATTR pinMatrixInDetach(uint8_t signal, bool high, bool inverted) +{ + gpio_matrix_in(high?MATRIX_DETACH_IN_LOW_HIGH:MATRIX_DETACH_IN_LOW_PIN, signal, inverted); +} +/* +void IRAM_ATTR intrMatrixAttach(uint32_t source, uint32_t inum){ + intr_matrix_set(PRO_CPU_NUM, source, inum); +} +*/ + diff --git a/MCUME_esp32/espvectrex/components/Wire/esp32-hal-matrix.h b/MCUME_esp32/espvectrex/components/Wire/esp32-hal-matrix.h new file mode 100644 index 0000000..7feefea --- /dev/null +++ b/MCUME_esp32/espvectrex/components/Wire/esp32-hal-matrix.h @@ -0,0 +1,35 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP32_HAL_MATRIX_H_ +#define _ESP32_HAL_MATRIX_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + +//#include "esp32-hal.h" +//#include "soc/gpio_sig_map.h" + +void pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable); +void pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable); +void pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted); +void pinMatrixInDetach(uint8_t signal, bool high, bool inverted); + +#ifdef __cplusplus +} +#endif + +#endif /* COMPONENTS_ARDUHAL_INCLUDE_ESP32_HAL_MATRIX_H_ */ diff --git a/MCUME_esp32/espvectrex/flashapp.sh b/MCUME_esp32/espvectrex/flashapp.sh new file mode 100755 index 0000000..f4d569b --- /dev/null +++ b/MCUME_esp32/espvectrex/flashapp.sh @@ -0,0 +1,3 @@ +#!/bin/bash +. ${IDF_PATH}/add_path.sh +esptool.py --chip esp32 --port "/dev/cu.SLAB_USBtoUART" --baud $((230400*4)) write_flash -fs 4MB 0x10000 ../espvectrex/build/espvectrex.bin diff --git a/MCUME_esp32/espvectrex/main/.DS_Store b/MCUME_esp32/espvectrex/main/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..5008ddfcf53c02e82d7eee2e57c38e5672ef89f6 GIT binary patch literal 6148 zcmeH~Jr2S!425mzP>H1@V-^m;4Wg<&0T*E43hX&L&p$$qDprKhvt+--jT7}7np#A3 zem<@ulZcFPQ@L2!n>{z**++&mCkOWA81W14cNZlEfg7;MkzE(HCqgga^y>{tEnwC%0;vJ&^%eQ zLs35+`xjp>T0> 1; + + short v0=chan[0].vol; + short v1=chan[1].vol; + short v2=chan[2].vol; + short v3=chan[3].vol; + short v4=chan[4].vol; + short v5=chan[5].vol; + for (i=0;i>8)&0x3f]) ); + s+= ( v1*(square[(chan[1].spos>>8)&0x3f]) ); + s+= ( v2*(square[(chan[2].spos>>8)&0x3f]) ); + s+= ( v3*(noise[(chan[3].spos>>8)&(NOISEBSIZE-1)]) ); + s+= ( v4*(noise[(chan[4].spos>>8)&(NOISEBSIZE-1)]) ); + s+= ( v5*(noise[(chan[5].spos>>8)&(NOISEBSIZE-1)]) ); + *stream++ = int16_t((s>>11)); + chan[0].spos += chan[0].sinc; + chan[1].spos += chan[1].sinc; + chan[2].spos += chan[2].sinc; + chan[3].spos += chan[3].sinc; + chan[4].spos += chan[4].sinc; + chan[5].spos += chan[5].sinc; + } +#endif + } +} + +#ifdef USE_I2S +#else +void IRAM_ATTR onTimer() +{ + // Sound playing code, plays whatever's in the buffer continuously. Big change from previous versions + if(LastDacValue!=Buffer[NextPlayPos]) // Send value to DAC only of changed since last value else no need + { + // value to DAC has changed, send to actual hardware, else we just leave setting as is as it's not changed + LastDacValue=Buffer[NextPlayPos]; + dacWrite(DacPin,uint8_t((LastDacValue>>8)+127)); // write out the data + } + Buffer[NextPlayPos]=0; // Reset this buffer byte back to silence + NextPlayPos++; // Move play pos to next byte in buffer + if(NextPlayPos==BufferSize) // If gone past end of buffer, + NextPlayPos=0; // set back to beginning +} + +#endif + +void AudioPlaySystem::begin(void) +{ +#ifdef USE_I2S + Buffer = (uint16_t *)malloc(DEFAULT_SAMPLESIZE*4); //16bits, L+R + uint16_t * dst=(uint16_t *)Buffer; + for (int i=0; i>1; + } +} + +void AudioPlaySystem::step(void) +{ +#ifdef USE_I2S + int left=DEFAULT_SAMPLERATE/50; + + while(left) { + int n=DEFAULT_SAMPLESIZE; + if (n>left) n=left; + snd_Mixer16((uint16_t*)Buffer, n); + //16 bit mono -> 16 bit r+l + for (int i=n-1; i>=0; i--) { + Buffer[i*2+1]=Buffer[i]+32767; + Buffer[i*2]=Buffer[i]+32767; + } + i2s_write_bytes(I2S_NUM, (const void*)Buffer, n*4, portMAX_DELAY); + left-=n; + } +#else + + int32_t CurPos=NextPlayPos; + int32_t samples; + if (CurPos > LastPlayPos) { + snd_Mixer16((uint16_t *)&Buffer[LastPlayPos], CurPos-LastPlayPos); + samples = CurPos-LastPlayPos; + } + else { + snd_Mixer16((uint16_t *)&Buffer[LastPlayPos], BufferSize-LastPlayPos); + snd_Mixer16((uint16_t *)&Buffer[0], CurPos); + samples = BufferSize-LastPlayPos; + samples += CurPos; + } + LastPlayPos = CurPos; + //printf("sam %d\n",bytes); +#endif +} +#endif + + diff --git a/MCUME_esp32/espvectrex/main/AudioPlaySystem.h b/MCUME_esp32/espvectrex/main/AudioPlaySystem.h new file mode 100644 index 0000000..c1e918f --- /dev/null +++ b/MCUME_esp32/espvectrex/main/AudioPlaySystem.h @@ -0,0 +1,23 @@ +#ifndef audioplaysystem_h_ +#define audioplaysystem_h_ + +#define DEFAULT_SAMPLESIZE 512 // 22050/50=443 samples per 20ms +#define DEFAULT_SAMPLERATE 22050 + +class AudioPlaySystem +{ +public: +AudioPlaySystem(void) { begin(); } + void begin(void); + void setSampleParameters(float clockfreq, float samplerate); + void reset(void); + void start(void); + void stop(void); + bool isPlaying(void); + void sound(int C, int F, int V); + void buzz(int size, int val); + void step(void); +}; + + +#endif diff --git a/MCUME_esp32/espvectrex/main/bmpjoy.h b/MCUME_esp32/espvectrex/main/bmpjoy.h new file mode 100644 index 0000000..def4d7c --- /dev/null +++ b/MCUME_esp32/espvectrex/main/bmpjoy.h @@ -0,0 +1,40 @@ +const uint16_t bmpjoy[] = { +0x001e,0x0026,0x0000,0x0000,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x0000,0x0000, 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+0x247c,0x247c,0x18e3,0xd6bb,0xbe18,0xadb7,0xadb7,0xadb7,0xad96,0xadb7,0xad97,0xad97,0xad97,0xad97,0xad97,0xad97,0xad97,0xadb7,0xad97,0xb5d7,0xbe18,0xadb7,0xad76,0xadb7,0xadb7,0xbe18,0xd6bb,0x18e3,0x247c,0x247c, +0x247c,0x247c,0x247c,0x18e3,0xd6bb,0xbdf8,0xb5b7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xadb7,0xad96,0xad96,0xadb7,0xadb7,0xb5b7,0xbdf8,0xd6bb,0x18e3,0x247c,0x247c,0x247c, +0x247c,0x247c,0x247c,0x247c,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x18e3,0x247c,0x247c,0x247c,0x247c, +0x0000,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x0000, +0x0000,0x0000,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x247c,0x0000,0x0000}; + diff --git a/MCUME_esp32/espvectrex/main/bmpvbar.h b/MCUME_esp32/espvectrex/main/bmpvbar.h new file mode 100644 index 0000000..22dd775 --- /dev/null +++ b/MCUME_esp32/espvectrex/main/bmpvbar.h @@ -0,0 +1,151 @@ +const uint16_t bmpvbar[] = { +0x0020,0x0094, +0x0000,0x0000,0x0000,0xad96,0xdf3d,0xd6fc,0xd6fc,0xd6fd,0xd6fd,0xd71d,0xdf1d,0xd71d,0xd71c,0xd71d,0xd71d,0xd71d,0xd71d,0xd71d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf1d,0xdf3d,0xbe18,0x0000,0x0000,0x0000,0x0861, +0x0000,0x0000,0xbe39,0xcedc,0xb63b,0xadfa,0xadfb,0xadfb,0xadfb,0xadfb,0xae1b,0xae1b,0xae1b,0xae1b,0xae1b,0xae1b,0xae3b,0xae3b,0xae3b,0xae3b,0xb63b,0xb63b,0xb63c,0xb63c,0xb65c,0xb65c,0xb65c,0xc69c,0xd71d,0x5b0c,0x0000,0x0861, +0x0000,0x0000,0xcedd,0xa5da,0x7d19,0x74d9,0x74da,0x74fa,0x74fa,0x74fa,0x74fa,0x751a,0x751a,0x751a,0x753a,0x753b,0x7d3b,0x7d3b,0x7d5b,0x7d5b,0x7d5b,0x7d7b,0x7d7b,0x7d7b,0x7d9c,0x7d9c,0x8ddb,0x9e1b,0xae7b,0xd71d,0x0000,0x0861, +0x0000,0xdf3d,0xa5fb,0x74da,0x4c59,0x445a,0x3c5a,0x447b,0x447b,0x447b,0x449b,0x449b,0x44bb,0x44bb,0x44db,0x4cdb,0x4cdc,0x4cfc,0x4cfc,0x4d1c,0x4d1c,0x4d3c,0x4d3c,0x555d,0x555d,0x557c,0x65bc,0x7dfb,0x961b,0xbe9c,0xad96,0x0861, +0x0000,0xc69b,0x7d1a,0x443a,0x345b,0x2c7c,0x2c7c,0x349c,0x349c,0x34bc,0x34bc,0x34dc,0x34dc,0x3cfd,0x3cfd,0x3cfd,0x3d1d,0x3d1d,0x453d,0x455e,0x455e,0x455e,0x457e,0x4d9e,0x4d9e,0x55be,0x5dfd,0x761c,0x8e1c,0xa63b,0xd6fc,0x0861, +0xad96,0xadfa,0x5c59,0x2c3b,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x453e,0x455e,0x457e,0x457e,0x457e,0x459f,0x4dbf,0x4dbf,0x55de,0x5dfe,0x6e1d,0x8e5d,0x9e3c,0xbe9c,0x8430, +0xd6fd,0x8d39,0x3c1a,0x2c5c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x55fe,0x65fe,0x8e7e,0x9e7d,0xae5c,0xdf3d, +0xcebc,0x74b9,0x343b,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x5dfe,0x7e5e,0x9e9e,0xa65c,0xd6fd, +0xc67c,0x5c5a,0x2c3b,0x247c,0x249c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x4dde,0x55de,0x763f,0x9e9e,0xa65c,0xcedc, +0xbe5b,0x543a,0x245c,0x247c,0x2c9c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x4dde,0x55de,0x661f,0xa69e,0xae5b,0xcedc, +0xbe3b,0x543a,0x245c,0x2c7c,0x2c9c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbf,0x55de,0x55fe,0x5e1e,0xa69d,0xb65b,0xcebc, +0xbe3a,0x543a,0x245c,0x2c7c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbe,0x55de,0x55fe,0x5dfe,0xa69d,0xb65b,0xcebc, +0xbe3a,0x545a,0x245c,0x2c7c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d1d,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4dbe,0x55de,0x55fe,0x5dfe,0xa69e,0xb67b,0xc6bc, +0xbe3a,0x5459,0x2c5c,0x2c7c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1d,0x3d1d,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x55be,0x4dde,0x55ff,0x5e1f,0xa69e,0xb67c,0xc6bc, +0xbe3a,0x5459,0x2c5c,0x2c7d,0x2c7d,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x34fd,0x3d1d,0x3d1e,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x55be,0x4ddf,0x55ff,0x661f,0xa6be,0xb67c,0xc6bc, +0xbe3a,0x5459,0x245c,0x2c7c,0x2c9c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x351d,0x3d1e,0x3d1e,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459f,0x4d9f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c9c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x351e,0x3d1e,0x3d1e,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459f,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x351e,0x3d1e,0x3d1e,0x3d1e,0x3d3e,0x455e,0x455e,0x457e,0x457e,0x459f,0x459f,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1e,0x3d3e,0x453e,0x455e,0x455e,0x457e,0x457e,0x459e,0x459f,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x34fd,0x3cfd,0x3d1d,0x3d1d,0x3d3d,0x3d3e,0x453e,0x455e,0x457e,0x457e,0x459e,0x459e,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9c,0x2cbd,0x34bd,0x34dd,0x34dd,0x3cdd,0x3cfd,0x3d1d,0x3d3d,0x3d3d,0x3d3d,0x453e,0x455e,0x455e,0x457e,0x459e,0x459e,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34bd,0x34dd,0x34dd,0x3cfd,0x3cfd,0x3d1e,0x3d3e,0x3d3d,0x3d1d,0x3d3e,0x3d3e,0x455e,0x457e,0x459e,0x459e,0x4dbf,0x4dbf,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34bc,0x34dd,0x34fd,0x3cfd,0x3d1e,0x3d3e,0x3d3e,0x3d3d,0x3d1d,0x3d1e,0x3d3e,0x3d3e,0x455e,0x457e,0x459e,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34bc,0x34dd,0x3cfd,0x3d1d,0x453e,0x3d5e,0x3d5e,0x453d,0x451d,0x3d1d,0x351e,0x3d1e,0x3d3e,0x457e,0x459e,0x4dbf,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34dd,0x34fd,0x3d1d,0x453d,0x455e,0x457e,0x455e,0x4d3d,0x4d3d,0x3d1d,0x34fe,0x351d,0x3d1d,0x3d5e,0x457e,0x4d9f,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34dd,0x34fd,0x3d3e,0x457e,0x457e,0x457e,0x4d5d,0x5d7d,0x657d,0x451d,0x34fd,0x34fd,0x34fd,0x3d3e,0x457e,0x4d9f,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34dd,0x3d1d,0x455e,0x459e,0x459e,0x457d,0x5d5c,0x85dd,0x861d,0x5d5d,0x3cfd,0x34dd,0x34dd,0x351d,0x3d5e,0x459e,0x4dbf,0x4dbf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2c9d,0x2cbd,0x34fd,0x3d3d,0x459e,0x4dbe,0x4dbe,0x4d5d,0x757c,0xae7d,0xaebe,0x75bd,0x451d,0x34dd,0x2cbd,0x34fd,0x3d3e,0x457e,0x4dbe,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2cbd,0x2cbd,0x351d,0x455d,0x45be,0x4ddf,0x459e,0x553c,0x95db,0xcf1e,0xcf3e,0x963e,0x553d,0x34dd,0x2cbc,0x2cbd,0x3d1d,0x455d,0x4dbe,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, +0xbe3b,0x543a,0x245c,0x247c,0x2c7c,0x2c9c,0x2cbd,0x34dd,0x3d1d,0x459d,0x4dbe,0x4ddf,0x459e,0x6d5b,0xb67c,0xe79e,0xe79f,0xb6be,0x6d7d,0x3cdd,0x2c9c,0x2cbd,0x34fd,0x455d,0x4dbe,0x4ddf,0x4ddf,0x55ff,0x661f,0xa6bf,0xb67c,0xc6bc, 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By default, it will take the sources in the +# src/ directory, compile them and link them into lib(subdirectory_name).a +# in the build directory. This behaviour is entirely configurable, +# please read the ESP-IDF documents if you need to do this. +# + +CPPFLAGS += -Wno-error=parentheses -Wno-error=maybe-uninitialized #-DEMULATED_JOYSTICK -DUSE_SHORT_SLICE -DUSE_DOUBLE_BUFFER -DNO_SOUND -fno-common -fno-builtin -fno-exceptions -fstrict-aliasing -Wno-narrowing -Wno-error=unused-value -Wno-error=return-type -Wno-error=sequence-point -Wno-error=implicit-int -Wno-error=pointer-sign -Wno-error=unused-function -Wno-error=implicit-function-declaration -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-error=char-subscripts -Wno-error=attributes +#-Werror=maybe-uninitialized diff --git a/MCUME_esp32/espvectrex/main/e6809.c b/MCUME_esp32/espvectrex/main/e6809.c new file mode 100755 index 0000000..ce0e09d --- /dev/null +++ b/MCUME_esp32/espvectrex/main/e6809.c @@ -0,0 +1,2623 @@ +#include +#include "e6809.h" + +/* code assumptions: + * - it is assumed that an 'int' is at least 16 bits long. + * - a 16-bit register has valid bits only in the lower 16 bits and an + * 8-bit register has valid bits only in the lower 8 bits. the upper + * may contain garbage! + * - all reading functions are assumed to return the requested data in + * the lower bits with the unused upper bits all set to zero. + */ + +#define einline __inline + +enum { + FLAG_E = 0x80, + FLAG_F = 0x40, + FLAG_H = 0x20, + FLAG_I = 0x10, + FLAG_N = 0x08, + FLAG_Z = 0x04, + FLAG_V = 0x02, + FLAG_C = 0x01, + IRQ_NORMAL = 0, + IRQ_SYNC = 1, + IRQ_CWAI = 2 +}; + +/* index registers */ + +static unsigned reg_x; +static unsigned reg_y; + +/* user stack pointer */ + +static unsigned reg_u; + +/* hardware stack pointer */ + +static unsigned reg_s; + +/* program counter */ + +static unsigned reg_pc; + +/* accumulators */ + +static unsigned reg_a; +static unsigned reg_b; + +/* direct page register */ + +static unsigned reg_dp; + +/* condition codes */ + +static unsigned reg_cc; + +/* flag to see if interrupts should be handled (sync/cwai). */ + +static unsigned irq_status; + +static unsigned *rptr_xyus[4] = { + ®_x, + ®_y, + ®_u, + ®_s +}; + +/* user defined read and write functions */ + +unsigned char (*e6809_read8) (unsigned address); +void (*e6809_write8) (unsigned address, unsigned char data); + +/* obtain a particular condition code. returns 0 or 1. */ + +static einline unsigned get_cc (unsigned flag) +{ + return (reg_cc / flag) & 1; +} + +/* set a particular condition code to either 0 or 1. + * value parameter must be either 0 or 1. + */ + +static einline void set_cc (unsigned flag, unsigned value) +{ + reg_cc &= ~flag; + reg_cc |= value * flag; +} + +/* test carry */ + +static einline unsigned test_c (unsigned i0, unsigned i1, + unsigned r, unsigned sub) +{ + unsigned flag; + + flag = (i0 | i1) & ~r; /* one of the inputs is 1 and output is 0 */ + flag |= (i0 & i1); /* both inputs are 1 */ + flag = (flag >> 7) & 1; + flag ^= sub; /* on a sub, carry is opposite the carry of an add */ + + return flag; +} + +/* test negative */ + +static einline unsigned test_n (unsigned r) +{ + return (r >> 7) & 1; +} + +/* test for zero in lower 8 bits */ + +static einline unsigned test_z8 (unsigned r) +{ + unsigned flag; + + flag = ~r; + flag = (flag >> 4) & (flag & 0xf); + flag = (flag >> 2) & (flag & 0x3); + flag = (flag >> 1) & (flag & 0x1); + + return flag; +} + +/* test for zero in lower 16 bits */ + +static einline unsigned test_z16 (unsigned r) +{ + unsigned flag; + + flag = ~r; + flag = (flag >> 8) & (flag & 0xff); + flag = (flag >> 4) & (flag & 0xf); + flag = (flag >> 2) & (flag & 0x3); + flag = (flag >> 1) & (flag & 0x1); + + return flag; +} + +/* overflow is set whenever the sign bits of the inputs are the same + * but the sign bit of the result is not same as the sign bits of the + * inputs. + */ + +static einline unsigned test_v (unsigned i0, unsigned i1, unsigned r) +{ + unsigned flag; + + flag = ~(i0 ^ i1); /* input sign bits are the same */ + flag &= (i0 ^ r); /* input sign and output sign not same */ + flag = (flag >> 7) & 1; + + return flag; +} + +static einline unsigned get_reg_d (void) +{ + return (reg_a << 8) | (reg_b & 0xff); +} + +static einline void set_reg_d (unsigned value) +{ + reg_a = value >> 8; + reg_b = value; +} + +/* read a byte ... the returned value has the lower 8-bits set to the byte + * while the upper bits are all zero. + */ + +static einline unsigned read8 (unsigned address) +{ + return (*e6809_read8) (address & 0xffff); +} + +/* write a byte ... only the lower 8-bits of the unsigned data + * is written. the upper bits are ignored. + */ + +static einline void write8 (unsigned address, unsigned data) +{ + (*e6809_write8) (address & 0xffff, (unsigned char) data); +} + +static einline unsigned read16 (unsigned address) +{ + unsigned datahi, datalo; + + datahi = read8 (address); + datalo = read8 (address + 1); + + return (datahi << 8) | datalo; +} + +static einline void write16 (unsigned address, unsigned data) +{ + write8 (address, data >> 8); + write8 (address + 1, data); +} + +static einline void push8 (unsigned *sp, unsigned data) +{ + (*sp)--; + write8 (*sp, data); +} + +static einline unsigned pull8 (unsigned *sp) +{ + unsigned data; + + data = read8 (*sp); + (*sp)++; + + return data; +} + +static einline void push16 (unsigned *sp, unsigned data) +{ + push8 (sp, data); + push8 (sp, data >> 8); +} + +static einline unsigned pull16 (unsigned *sp) +{ + unsigned datahi, datalo; + + datahi = pull8 (sp); + datalo = pull8 (sp); + + return (datahi << 8) | datalo; +} + +/* read a byte from the address pointed to by the pc */ + +static einline unsigned pc_read8 (void) +{ + unsigned data; + + data = read8 (reg_pc); + reg_pc++; + + return data; +} + +/* read a word from the address pointed to by the pc */ + +static einline unsigned pc_read16 (void) +{ + unsigned data; + + data = read16 (reg_pc); + reg_pc += 2; + + return data; +} + +/* sign extend an 8-bit quantity into a 16-bit quantity */ + +static einline unsigned sign_extend (unsigned data) +{ + return (~(data & 0x80) + 1) | (data & 0xff); +} + +/* direct addressing, upper byte of the address comes from + * the direct page register, and the lower byte comes from the + * instruction itself. + */ + +static einline unsigned ea_direct (void) +{ + return (reg_dp << 8) | pc_read8 (); +} + +/* extended addressing, address is obtained from 2 bytes following + * the instruction. + */ + +static einline unsigned ea_extended (void) +{ + return pc_read16 (); +} + +/* indexed addressing */ + +static einline unsigned ea_indexed (unsigned *cycles) +{ + unsigned r, op, ea; + + /* post byte */ + + op = pc_read8 (); + + r = (op >> 5) & 3; + + switch (op) { + case 0x00: case 0x01: case 0x02: case 0x03: + case 0x04: case 0x05: case 0x06: case 0x07: + case 0x08: case 0x09: case 0x0a: case 0x0b: + case 0x0c: case 0x0d: case 0x0e: case 0x0f: + case 0x20: case 0x21: case 0x22: case 0x23: + case 0x24: case 0x25: case 0x26: case 0x27: + case 0x28: case 0x29: case 0x2a: case 0x2b: + case 0x2c: case 0x2d: case 0x2e: case 0x2f: + case 0x40: case 0x41: case 0x42: case 0x43: + case 0x44: case 0x45: case 0x46: case 0x47: + case 0x48: case 0x49: case 0x4a: case 0x4b: + case 0x4c: case 0x4d: case 0x4e: case 0x4f: + case 0x60: case 0x61: case 0x62: case 0x63: + case 0x64: case 0x65: case 0x66: case 0x67: + case 0x68: case 0x69: case 0x6a: case 0x6b: + case 0x6c: case 0x6d: case 0x6e: case 0x6f: + /* R, +[0, 15] */ + + ea = *rptr_xyus[r] + (op & 0xf); + (*cycles)++; + break; + case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x15: case 0x16: case 0x17: + case 0x18: case 0x19: case 0x1a: case 0x1b: + case 0x1c: case 0x1d: case 0x1e: case 0x1f: + case 0x30: case 0x31: case 0x32: case 0x33: + case 0x34: case 0x35: case 0x36: case 0x37: + case 0x38: case 0x39: case 0x3a: case 0x3b: + case 0x3c: case 0x3d: case 0x3e: case 0x3f: + case 0x50: case 0x51: case 0x52: case 0x53: + case 0x54: case 0x55: case 0x56: case 0x57: + case 0x58: case 0x59: case 0x5a: case 0x5b: + case 0x5c: case 0x5d: case 0x5e: case 0x5f: + case 0x70: case 0x71: case 0x72: case 0x73: + case 0x74: case 0x75: case 0x76: case 0x77: + case 0x78: case 0x79: case 0x7a: case 0x7b: + case 0x7c: case 0x7d: case 0x7e: case 0x7f: + /* R, +[-16, -1] */ + + ea = *rptr_xyus[r] + (op & 0xf) - 0x10; + (*cycles)++; + break; + case 0x80: case 0x81: + case 0xa0: case 0xa1: + case 0xc0: case 0xc1: + case 0xe0: case 0xe1: + /* ,R+ / ,R++ */ + + ea = *rptr_xyus[r]; + *rptr_xyus[r] += 1 + (op & 1); + *cycles += 2 + (op & 1); + break; + case 0x90: case 0x91: + case 0xb0: case 0xb1: + case 0xd0: case 0xd1: + case 0xf0: case 0xf1: + /* [,R+] ??? / [,R++] */ + + ea = read16 (*rptr_xyus[r]); + *rptr_xyus[r] += 1 + (op & 1); + *cycles += 5 + (op & 1); + break; + case 0x82: case 0x83: + case 0xa2: case 0xa3: + case 0xc2: case 0xc3: + case 0xe2: case 0xe3: + + /* ,-R / ,--R */ + + *rptr_xyus[r] -= 1 + (op & 1); + ea = *rptr_xyus[r]; + *cycles += 2 + (op & 1); + break; + case 0x92: case 0x93: + case 0xb2: case 0xb3: + case 0xd2: case 0xd3: + case 0xf2: case 0xf3: + /* [,-R] ??? / [,--R] */ + + *rptr_xyus[r] -= 1 + (op & 1); + ea = read16 (*rptr_xyus[r]); + *cycles += 5 + (op & 1); + break; + case 0x84: case 0xa4: + case 0xc4: case 0xe4: + /* ,R */ + + ea = *rptr_xyus[r]; + break; + case 0x94: case 0xb4: + case 0xd4: case 0xf4: + /* [,R] */ + + ea = read16 (*rptr_xyus[r]); + *cycles += 3; + break; + case 0x85: case 0xa5: + case 0xc5: case 0xe5: + /* B,R */ + + ea = *rptr_xyus[r] + sign_extend (reg_b); + *cycles += 1; + break; + case 0x95: case 0xb5: + case 0xd5: case 0xf5: + /* [B,R] */ + + ea = read16 (*rptr_xyus[r] + sign_extend (reg_b)); + *cycles += 4; + break; + case 0x86: case 0xa6: + case 0xc6: case 0xe6: + /* A,R */ + + ea = *rptr_xyus[r] + sign_extend (reg_a); + *cycles += 1; + break; + case 0x96: case 0xb6: + case 0xd6: case 0xf6: + /* [A,R] */ + + ea = read16 (*rptr_xyus[r] + sign_extend (reg_a)); + *cycles += 4; + break; + case 0x88: case 0xa8: + case 0xc8: case 0xe8: + /* byte,R */ + + ea = *rptr_xyus[r] + sign_extend (pc_read8 ()); + *cycles += 1; + break; + case 0x98: case 0xb8: + case 0xd8: case 0xf8: + /* [byte,R] */ + + ea = read16 (*rptr_xyus[r] + sign_extend (pc_read8 ())); + *cycles += 4; + break; + case 0x89: case 0xa9: + case 0xc9: case 0xe9: + /* word,R */ + + ea = *rptr_xyus[r] + pc_read16 (); + *cycles += 4; + break; + case 0x99: case 0xb9: + case 0xd9: case 0xf9: + /* [word,R] */ + + ea = read16 (*rptr_xyus[r] + pc_read16 ()); + *cycles += 7; + break; + case 0x8b: case 0xab: + case 0xcb: case 0xeb: + /* D,R */ + + ea = *rptr_xyus[r] + get_reg_d (); + *cycles += 4; + break; + case 0x9b: case 0xbb: + case 0xdb: case 0xfb: + /* [D,R] */ + + ea = read16 (*rptr_xyus[r] + get_reg_d ()); + *cycles += 7; + break; + case 0x8c: case 0xac: + case 0xcc: case 0xec: + /* byte, PC */ + + r = sign_extend (pc_read8 ()); + ea = reg_pc + r; + *cycles += 1; + break; + case 0x9c: case 0xbc: + case 0xdc: case 0xfc: + /* [byte, PC] */ + + r = sign_extend (pc_read8 ()); + ea = read16 (reg_pc + r); + *cycles += 4; + break; + case 0x8d: case 0xad: + case 0xcd: case 0xed: + /* word, PC */ + + r = pc_read16 (); + ea = reg_pc + r; + *cycles += 5; + break; + case 0x9d: case 0xbd: + case 0xdd: case 0xfd: + /* [word, PC] */ + + r = pc_read16 (); + ea = read16 (reg_pc + r); + *cycles += 8; + break; + case 0x9f: + /* [address] */ + + ea = read16 (pc_read16 ()); + *cycles += 5; + break; + default: + printf ("undefined post-byte\n"); + break; + } + + return ea; +} + +/* instruction: neg + * essentially (0 - data). + */ + +einline unsigned inst_neg (unsigned data) +{ + unsigned i0, i1, r; + + i0 = 0; + i1 = ~data; + r = i0 + i1 + 1; + + set_cc (FLAG_H, test_c (i0 << 4, i1 << 4, r << 4, 0)); + set_cc (FLAG_N, test_n (r)); + set_cc (FLAG_Z, test_z8 (r)); + set_cc (FLAG_V, test_v (i0, i1, r)); + set_cc (FLAG_C, test_c (i0, i1, r, 1)); + + return r; +} + +/* instruction: com */ + +einline unsigned inst_com (unsigned data) +{ + unsigned r; + + r = ~data; + + set_cc (FLAG_N, test_n (r)); + set_cc (FLAG_Z, test_z8 (r)); + set_cc (FLAG_V, 0); + set_cc (FLAG_C, 1); + + return r; +} + +/* instruction: lsr + * cannot be faked as an add or substract. + */ + +einline unsigned inst_lsr (unsigned data) +{ + unsigned r; + + r = (data >> 1) & 0x7f; + + set_cc (FLAG_N, 0); + set_cc (FLAG_Z, test_z8 (r)); + set_cc (FLAG_C, data & 1); + + return r; +} + +/* instruction: ror + * cannot be faked as an add or substract. + */ + +einline unsigned inst_ror (unsigned data) +{ + unsigned r, c; + + c = get_cc (FLAG_C); + r = ((data >> 1) & 0x7f) | (c << 7); + + set_cc (FLAG_N, test_n (r)); + set_cc (FLAG_Z, test_z8 (r)); + set_cc (FLAG_C, data & 1); + + return r; +} + +/* instruction: asr + * cannot be faked as an add or substract. + */ + +einline unsigned inst_asr (unsigned data) +{ + unsigned r; + + r = ((data >> 1) & 0x7f) | (data & 0x80); + + set_cc (FLAG_N, test_n (r)); + set_cc (FLAG_Z, test_z8 (r)); + set_cc (FLAG_C, data & 1); + + return r; +} + +/* instruction: asl + * essentially (data + data). simple addition. + */ + +einline unsigned inst_asl (unsigned data) +{ + unsigned i0, i1, r; + + i0 = data; + i1 = data; + r = i0 + i1; + + set_cc (FLAG_H, test_c (i0 << 4, i1 << 4, r << 4, 0)); + set_cc (FLAG_N, test_n (r)); + set_cc (FLAG_Z, test_z8 (r)); + set_cc (FLAG_V, test_v (i0, i1, r)); + set_cc (FLAG_C, test_c (i0, i1, r, 0)); + + return r; +} + +/* instruction: rol + * essentially (data + data + carry). addition with carry. + */ + +einline unsigned inst_rol (unsigned data) +{ + unsigned i0, i1, c, r; + + i0 = data; + i1 = data; + c = get_cc (FLAG_C); + r = i0 + i1 + c; + + set_cc (FLAG_N, test_n (r)); + set_cc (FLAG_Z, test_z8 (r)); + set_cc (FLAG_V, test_v (i0, i1, r)); + set_cc (FLAG_C, test_c (i0, i1, r, 0)); + + return r; +} + +/* instruction: dec + * essentially (data - 1). + */ + +einline unsigned inst_dec (unsigned data) +{ + unsigned i0, i1, r; + + i0 = data; + i1 = 0xff; + r = i0 + i1; + + set_cc (FLAG_N, test_n (r)); + set_cc (FLAG_Z, test_z8 (r)); + set_cc (FLAG_V, test_v (i0, i1, r)); + + return r; +} + +/* instruction: inc + * essentially (data + 1). + */ + +einline unsigned inst_inc (unsigned data) +{ + unsigned i0, i1, r; + + i0 = data; + i1 = 1; + r = i0 + i1; + + set_cc (FLAG_N, test_n (r)); + set_cc (FLAG_Z, test_z8 (r)); + set_cc (FLAG_V, test_v (i0, i1, r)); + + return r; +} + +/* instruction: tst */ + +einline void inst_tst8 (unsigned data) +{ + set_cc (FLAG_N, test_n (data)); + set_cc (FLAG_Z, test_z8 (data)); + set_cc (FLAG_V, 0); +} + +einline void inst_tst16 (unsigned data) +{ + set_cc (FLAG_N, test_n (data >> 8)); + set_cc (FLAG_Z, test_z16 (data)); + set_cc (FLAG_V, 0); +} + +/* instruction: clr */ + +einline void inst_clr (void) +{ + set_cc (FLAG_N, 0); + set_cc (FLAG_Z, 1); + set_cc (FLAG_V, 0); + set_cc (FLAG_C, 0); +} + +/* instruction: suba/subb */ + +einline unsigned inst_sub8 (unsigned data0, unsigned data1) +{ + unsigned i0, i1, r; + + i0 = data0; + i1 = ~data1; + r = i0 + i1 + 1; + + set_cc (FLAG_H, test_c (i0 << 4, i1 << 4, r << 4, 0)); + set_cc (FLAG_N, test_n (r)); + set_cc (FLAG_Z, test_z8 (r)); + set_cc (FLAG_V, test_v (i0, i1, r)); + set_cc (FLAG_C, test_c (i0, i1, r, 1)); + + return r; +} + +/* instruction: sbca/sbcb/cmpa/cmpb. + * only 8-bit version, 16-bit version not needed. + */ + +einline unsigned inst_sbc (unsigned data0, unsigned data1) +{ + unsigned i0, i1, c, r; + + i0 = data0; + i1 = ~data1; + c = 1 - get_cc (FLAG_C); + r = i0 + i1 + c; + + set_cc (FLAG_H, test_c (i0 << 4, i1 << 4, r << 4, 0)); + set_cc (FLAG_N, test_n (r)); + set_cc (FLAG_Z, test_z8 (r)); + set_cc (FLAG_V, test_v (i0, i1, r)); + set_cc (FLAG_C, test_c (i0, i1, r, 1)); + + return r; +} + +/* instruction: anda/andb/bita/bitb. + * only 8-bit version, 16-bit version not needed. + */ + +einline unsigned inst_and (unsigned data0, unsigned data1) +{ + unsigned r; + + r = data0 & data1; + + inst_tst8 (r); + + return r; +} + +/* instruction: eora/eorb. + * only 8-bit version, 16-bit version not needed. + */ + +einline unsigned inst_eor (unsigned data0, unsigned data1) +{ + unsigned r; + + r = data0 ^ data1; + + inst_tst8 (r); + + return r; +} + +/* instruction: adca/adcb + * only 8-bit version, 16-bit version not needed. + */ + +einline unsigned inst_adc (unsigned data0, unsigned data1) +{ + unsigned i0, i1, c, r; + + i0 = data0; + i1 = data1; + c = get_cc (FLAG_C); + r = i0 + i1 + c; + + set_cc (FLAG_H, test_c (i0 << 4, i1 << 4, r << 4, 0)); + set_cc (FLAG_N, test_n (r)); + set_cc (FLAG_Z, test_z8 (r)); + set_cc (FLAG_V, test_v (i0, i1, r)); + set_cc (FLAG_C, test_c (i0, i1, r, 0)); + + return r; +} + +/* instruction: ora/orb. + * only 8-bit version, 16-bit version not needed. + */ + +einline unsigned inst_or (unsigned data0, unsigned data1) +{ + unsigned r; + + r = data0 | data1; + + inst_tst8 (r); + + return r; +} + +/* instruction: adda/addb */ + +einline unsigned inst_add8 (unsigned data0, unsigned data1) +{ + unsigned i0, i1, r; + + i0 = data0; + i1 = data1; + r = i0 + i1; + + set_cc (FLAG_H, test_c (i0 << 4, i1 << 4, r << 4, 0)); + set_cc (FLAG_N, test_n (r)); + set_cc (FLAG_Z, test_z8 (r)); + set_cc (FLAG_V, test_v (i0, i1, r)); + set_cc (FLAG_C, test_c (i0, i1, r, 0)); + + return r; +} + +/* instruction: addd */ + +einline unsigned inst_add16 (unsigned data0, unsigned data1) +{ + unsigned i0, i1, r; + + i0 = data0; + i1 = data1; + r = i0 + i1; + + set_cc (FLAG_N, test_n (r >> 8)); + set_cc (FLAG_Z, test_z16 (r)); + set_cc (FLAG_V, test_v (i0 >> 8, i1 >> 8, r >> 8)); + set_cc (FLAG_C, test_c (i0 >> 8, i1 >> 8, r >> 8, 0)); + + return r; +} + +/* instruction: subd */ + +einline unsigned inst_sub16 (unsigned data0, unsigned data1) +{ + unsigned i0, i1, r; + + i0 = data0; + i1 = ~data1; + r = i0 + i1 + 1; + + set_cc (FLAG_N, test_n (r >> 8)); + set_cc (FLAG_Z, test_z16 (r)); + set_cc (FLAG_V, test_v (i0 >> 8, i1 >> 8, r >> 8)); + set_cc (FLAG_C, test_c (i0 >> 8, i1 >> 8, r >> 8, 1)); + + return r; +} + +/* instruction: 8-bit offset branch */ + +einline void inst_bra8 (unsigned test, unsigned op, unsigned *cycles) +{ + unsigned offset, mask; + + offset = pc_read8 (); + + /* trying to avoid an if statement */ + + mask = (test ^ (op & 1)) - 1; /* 0xffff when taken, 0 when not taken */ + reg_pc += sign_extend (offset) & mask; + + *cycles += 3; +} + +/* instruction: 16-bit offset branch */ + +einline void inst_bra16 (unsigned test, unsigned op, unsigned *cycles) +{ + unsigned offset, mask; + + offset = pc_read16 (); + + /* trying to avoid an if statement */ + + mask = (test ^ (op & 1)) - 1; /* 0xffff when taken, 0 when not taken */ + reg_pc += offset & mask; + + *cycles += 5 - mask; +} + +/* instruction: pshs/pshu */ + +einline void inst_psh (unsigned op, unsigned *sp, + unsigned data, unsigned *cycles) +{ + if (op & 0x80) { + push16 (sp, reg_pc); + *cycles += 2; + } + + if (op & 0x40) { + /* either s or u */ + push16 (sp, data); + *cycles += 2; + } + + if (op & 0x20) { + push16 (sp, reg_y); + *cycles += 2; + } + + if (op & 0x10) { + push16 (sp, reg_x); + *cycles += 2; + } + + if (op & 0x08) { + push8 (sp, reg_dp); + *cycles += 1; + } + + if (op & 0x04) { + push8 (sp, reg_b); + *cycles += 1; + } + + if (op & 0x02) { + push8 (sp, reg_a); + *cycles += 1; + } + + if (op & 0x01) { + push8 (sp, reg_cc); + *cycles += 1; + } +} + +/* instruction: puls/pulu */ + +einline void inst_pul (unsigned op, unsigned *sp, unsigned *osp, + unsigned *cycles) +{ + if (op & 0x01) { + reg_cc = pull8 (sp); + *cycles += 1; + } + + if (op & 0x02) { + reg_a = pull8 (sp); + *cycles += 1; + } + + if (op & 0x04) { + reg_b = pull8 (sp); + *cycles += 1; + } + + if (op & 0x08) { + reg_dp = pull8 (sp); + *cycles += 1; + } + + if (op & 0x10) { + reg_x = pull16 (sp); + *cycles += 2; + } + + if (op & 0x20) { + reg_y = pull16 (sp); + *cycles += 2; + } + + if (op & 0x40) { + /* either s or u */ + *osp = pull16 (sp); + *cycles += 2; + } + + if (op & 0x80) { + reg_pc = pull16 (sp); + *cycles += 2; + } +} + +einline unsigned exgtfr_read (unsigned reg) +{ + unsigned data; + + switch (reg) { + case 0x0: + data = get_reg_d (); + break; + case 0x1: + data = reg_x; + break; + case 0x2: + data = reg_y; + break; + case 0x3: + data = reg_u; + break; + case 0x4: + data = reg_s; + break; + case 0x5: + data = reg_pc; + break; + case 0x8: + data = 0xff00 | reg_a; + break; + case 0x9: + data = 0xff00 | reg_b; + break; + case 0xa: + data = 0xff00 | reg_cc; + break; + case 0xb: + data = 0xff00 | reg_dp; + break; + default: + data = 0xffff; + printf ("illegal exgtfr reg %.1x\n", reg); + break; + } + + return data; +} + +einline void exgtfr_write (unsigned reg, unsigned data) +{ + switch (reg) { + case 0x0: + set_reg_d (data); + break; + case 0x1: + reg_x = data; + break; + case 0x2: + reg_y = data; + break; + case 0x3: + reg_u = data; + break; + case 0x4: + reg_s = data; + break; + case 0x5: + reg_pc = data; + break; + case 0x8: + reg_a = data; + break; + case 0x9: + reg_b = data; + break; + case 0xa: + reg_cc = data; + break; + case 0xb: + reg_dp = data; + break; + default: + printf ("illegal exgtfr reg %.1x\n", reg); + break; + } +} + +/* instruction: exg */ + +einline void inst_exg (void) +{ + unsigned op, tmp; + + op = pc_read8 (); + + tmp = exgtfr_read (op & 0xf); + exgtfr_write (op & 0xf, exgtfr_read (op >> 4)); + exgtfr_write (op >> 4, tmp); +} + +/* instruction: tfr */ + +einline void inst_tfr (void) +{ + unsigned op; + + op = pc_read8 (); + + exgtfr_write (op & 0xf, exgtfr_read (op >> 4)); +} + +/* reset the 6809 */ + +void e6809_reset (void) +{ + reg_x = 0; + reg_y = 0; + reg_u = 0; + reg_s = 0; + + reg_a = 0; + reg_b = 0; + + reg_dp = 0; + + reg_cc = FLAG_I | FLAG_F; + irq_status = IRQ_NORMAL; + + reg_pc = read16 (0xfffe); +} + +/* execute a single instruction or handle interrupts and return */ + +unsigned e6809_sstep (unsigned irq_i, unsigned irq_f) +{ + unsigned op; + unsigned cycles = 0; + unsigned ea, i0, i1, r; + + if (irq_f) { + if (get_cc (FLAG_F) == 0) { + if (irq_status != IRQ_CWAI) { + set_cc (FLAG_E, 0); + inst_psh (0x81, ®_s, reg_u, &cycles); + } + + set_cc (FLAG_I, 1); + set_cc (FLAG_F, 1); + + reg_pc = read16 (0xfff6); + irq_status = IRQ_NORMAL; + cycles += 7; + } else { + if (irq_status == IRQ_SYNC) { + irq_status = IRQ_NORMAL; + } + } + } + + if (irq_i) { + if (get_cc (FLAG_I) == 0) { + if (irq_status != IRQ_CWAI) { + set_cc (FLAG_E, 1); + inst_psh (0xff, ®_s, reg_u, &cycles); + } + + set_cc (FLAG_I, 1); + + reg_pc = read16 (0xfff8); + irq_status = IRQ_NORMAL; + cycles += 7; + } else { + if (irq_status == IRQ_SYNC) { + irq_status = IRQ_NORMAL; + } + } + } + + if (irq_status != IRQ_NORMAL) { + return cycles + 1; + } + + op = pc_read8 (); + + switch (op) { + /* page 0 instructions */ + + /* neg, nega, negb */ + case 0x00: + ea = ea_direct (); + r = inst_neg (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x40: + reg_a = inst_neg (reg_a); + cycles += 2; + break; + case 0x50: + reg_b = inst_neg (reg_b); + cycles += 2; + break; + case 0x60: + ea = ea_indexed (&cycles); + r = inst_neg (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x70: + ea = ea_extended (); + r = inst_neg (read8 (ea)); + write8 (ea, r); + cycles += 7; + break; + /* com, coma, comb */ + case 0x03: + ea = ea_direct (); + r = inst_com (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x43: + reg_a = inst_com (reg_a); + cycles += 2; + break; + case 0x53: + reg_b = inst_com (reg_b); + cycles += 2; + break; + case 0x63: + ea = ea_indexed (&cycles); + r = inst_com (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x73: + ea = ea_extended (); + r = inst_com (read8 (ea)); + write8 (ea, r); + cycles += 7; + break; + /* lsr, lsra, lsrb */ + case 0x04: + ea = ea_direct (); + r = inst_lsr (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x44: + reg_a = inst_lsr (reg_a); + cycles += 2; + break; + case 0x54: + reg_b = inst_lsr (reg_b); + cycles += 2; + break; + case 0x64: + ea = ea_indexed (&cycles); + r = inst_lsr (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x74: + ea = ea_extended (); + r = inst_lsr (read8 (ea)); + write8 (ea, r); + cycles += 7; + break; + /* ror, rora, rorb */ + case 0x06: + ea = ea_direct (); + r = inst_ror (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x46: + reg_a = inst_ror (reg_a); + cycles += 2; + break; + case 0x56: + reg_b = inst_ror (reg_b); + cycles += 2; + break; + case 0x66: + ea = ea_indexed (&cycles); + r = inst_ror (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x76: + ea = ea_extended (); + r = inst_ror (read8 (ea)); + write8 (ea, r); + cycles += 7; + break; + /* asr, asra, asrb */ + case 0x07: + ea = ea_direct (); + r = inst_asr (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x47: + reg_a = inst_asr (reg_a); + cycles += 2; + break; + case 0x57: + reg_b = inst_asr (reg_b); + cycles += 2; + break; + case 0x67: + ea = ea_indexed (&cycles); + r = inst_asr (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x77: + ea = ea_extended (); + r = inst_asr (read8 (ea)); + write8 (ea, r); + cycles += 7; + break; + /* asl, asla, aslb */ + case 0x08: + ea = ea_direct (); + r = inst_asl (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x48: + reg_a = inst_asl (reg_a); + cycles += 2; + break; + case 0x58: + reg_b = inst_asl (reg_b); + cycles += 2; + break; + case 0x68: + ea = ea_indexed (&cycles); + r = inst_asl (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x78: + ea = ea_extended (); + r = inst_asl (read8 (ea)); + write8 (ea, r); + cycles += 7; + break; + /* rol, rola, rolb */ + case 0x09: + ea = ea_direct (); + r = inst_rol (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x49: + reg_a = inst_rol (reg_a); + cycles += 2; + break; + case 0x59: + reg_b = inst_rol (reg_b); + cycles += 2; + break; + case 0x69: + ea = ea_indexed (&cycles); + r = inst_rol (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x79: + ea = ea_extended (); + r = inst_rol (read8 (ea)); + write8 (ea, r); + cycles += 7; + break; + /* dec, deca, decb */ + case 0x0a: + ea = ea_direct (); + r = inst_dec (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x4a: + reg_a = inst_dec (reg_a); + cycles += 2; + break; + case 0x5a: + reg_b = inst_dec (reg_b); + cycles += 2; + break; + case 0x6a: + ea = ea_indexed (&cycles); + r = inst_dec (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x7a: + ea = ea_extended (); + r = inst_dec (read8 (ea)); + write8 (ea, r); + cycles += 7; + break; + /* inc, inca, incb */ + case 0x0c: + ea = ea_direct (); + r = inst_inc (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x4c: + reg_a = inst_inc (reg_a); + cycles += 2; + break; + case 0x5c: + reg_b = inst_inc (reg_b); + cycles += 2; + break; + case 0x6c: + ea = ea_indexed (&cycles); + r = inst_inc (read8 (ea)); + write8 (ea, r); + cycles += 6; + break; + case 0x7c: + ea = ea_extended (); + r = inst_inc (read8 (ea)); + write8 (ea, r); + cycles += 7; + break; + /* tst, tsta, tstb */ + case 0x0d: + ea = ea_direct (); + inst_tst8 (read8 (ea)); + cycles += 6; + break; + case 0x4d: + inst_tst8 (reg_a); + cycles += 2; + break; + case 0x5d: + inst_tst8 (reg_b); + cycles += 2; + break; + case 0x6d: + ea = ea_indexed (&cycles); + inst_tst8 (read8 (ea)); + cycles += 6; + break; + case 0x7d: + ea = ea_extended (); + inst_tst8 (read8 (ea)); + cycles += 7; + break; + /* jmp */ + case 0x0e: + reg_pc = ea_direct (); + cycles += 3; + break; + case 0x6e: + reg_pc = ea_indexed (&cycles); + cycles += 3; + break; + case 0x7e: + reg_pc = ea_extended (); + cycles += 4; + break; + /* clr */ + case 0x0f: + ea = ea_direct (); + inst_clr (); + write8 (ea, 0); + cycles += 6; + break; + case 0x4f: + inst_clr (); + reg_a = 0; + cycles += 2; + break; + case 0x5f: + inst_clr (); + reg_b = 0; + cycles += 2; + break; + case 0x6f: + ea = ea_indexed (&cycles); + inst_clr (); + write8 (ea, 0); + cycles += 6; + break; + case 0x7f: + ea = ea_extended (); + inst_clr (); + write8 (ea, 0); + cycles += 7; + break; + /* suba */ + case 0x80: + reg_a = inst_sub8 (reg_a, pc_read8 ()); + cycles += 2; + break; + case 0x90: + ea = ea_direct (); + reg_a = inst_sub8 (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xa0: + ea = ea_indexed (&cycles); + reg_a = inst_sub8 (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xb0: + ea = ea_extended (); + reg_a = inst_sub8 (reg_a, read8 (ea)); + cycles += 5; + break; + /* subb */ + case 0xc0: + reg_b = inst_sub8 (reg_b, pc_read8 ()); + cycles += 2; + break; + case 0xd0: + ea = ea_direct (); + reg_b = inst_sub8 (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xe0: + ea = ea_indexed (&cycles); + reg_b = inst_sub8 (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xf0: + ea = ea_extended (); + reg_b = inst_sub8 (reg_b, read8 (ea)); + cycles += 5; + break; + /* cmpa */ + case 0x81: + inst_sub8 (reg_a, pc_read8 ()); + cycles += 2; + break; + case 0x91: + ea = ea_direct (); + inst_sub8 (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xa1: + ea = ea_indexed (&cycles); + inst_sub8 (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xb1: + ea = ea_extended (); + inst_sub8 (reg_a, read8 (ea)); + cycles += 5; + break; + /* cmpb */ + case 0xc1: + inst_sub8 (reg_b, pc_read8 ()); + cycles += 2; + break; + case 0xd1: + ea = ea_direct (); + inst_sub8 (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xe1: + ea = ea_indexed (&cycles); + inst_sub8 (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xf1: + ea = ea_extended (); + inst_sub8 (reg_b, read8 (ea)); + cycles += 5; + break; + /* sbca */ + case 0x82: + reg_a = inst_sbc (reg_a, pc_read8 ()); + cycles += 2; + break; + case 0x92: + ea = ea_direct (); + reg_a = inst_sbc (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xa2: + ea = ea_indexed (&cycles); + reg_a = inst_sbc (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xb2: + ea = ea_extended (); + reg_a = inst_sbc (reg_a, read8 (ea)); + cycles += 5; + break; + /* sbcb */ + case 0xc2: + reg_b = inst_sbc (reg_b, pc_read8 ()); + cycles += 2; + break; + case 0xd2: + ea = ea_direct (); + reg_b = inst_sbc (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xe2: + ea = ea_indexed (&cycles); + reg_b = inst_sbc (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xf2: + ea = ea_extended (); + reg_b = inst_sbc (reg_b, read8 (ea)); + cycles += 5; + break; + /* anda */ + case 0x84: + reg_a = inst_and (reg_a, pc_read8 ()); + cycles += 2; + break; + case 0x94: + ea = ea_direct (); + reg_a = inst_and (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xa4: + ea = ea_indexed (&cycles); + reg_a = inst_and (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xb4: + ea = ea_extended (); + reg_a = inst_and (reg_a, read8 (ea)); + cycles += 5; + break; + /* andb */ + case 0xc4: + reg_b = inst_and (reg_b, pc_read8 ()); + cycles += 2; + break; + case 0xd4: + ea = ea_direct (); + reg_b = inst_and (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xe4: + ea = ea_indexed (&cycles); + reg_b = inst_and (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xf4: + ea = ea_extended (); + reg_b = inst_and (reg_b, read8 (ea)); + cycles += 5; + break; + /* bita */ + case 0x85: + inst_and (reg_a, pc_read8 ()); + cycles += 2; + break; + case 0x95: + ea = ea_direct (); + inst_and (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xa5: + ea = ea_indexed (&cycles); + inst_and (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xb5: + ea = ea_extended (); + inst_and (reg_a, read8 (ea)); + cycles += 5; + break; + /* bitb */ + case 0xc5: + inst_and (reg_b, pc_read8 ()); + cycles += 2; + break; + case 0xd5: + ea = ea_direct (); + inst_and (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xe5: + ea = ea_indexed (&cycles); + inst_and (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xf5: + ea = ea_extended (); + inst_and (reg_b, read8 (ea)); + cycles += 5; + break; + /* lda */ + case 0x86: + reg_a = pc_read8 (); + inst_tst8 (reg_a); + cycles += 2; + break; + case 0x96: + ea = ea_direct (); + reg_a = read8 (ea); + inst_tst8 (reg_a); + cycles += 4; + break; + case 0xa6: + ea = ea_indexed (&cycles); + reg_a = read8 (ea); + inst_tst8 (reg_a); + cycles += 4; + break; + case 0xb6: + ea = ea_extended (); + reg_a = read8 (ea); + inst_tst8 (reg_a); + cycles += 5; + break; + /* ldb */ + case 0xc6: + reg_b = pc_read8 (); + inst_tst8 (reg_b); + cycles += 2; + break; + case 0xd6: + ea = ea_direct (); + reg_b = read8 (ea); + inst_tst8 (reg_b); + cycles += 4; + break; + case 0xe6: + ea = ea_indexed (&cycles); + reg_b = read8 (ea); + inst_tst8 (reg_b); + cycles += 4; + break; + case 0xf6: + ea = ea_extended (); + reg_b = read8 (ea); + inst_tst8 (reg_b); + cycles += 5; + break; + /* sta */ + case 0x97: + ea = ea_direct (); + write8 (ea, reg_a); + inst_tst8 (reg_a); + cycles += 4; + break; + case 0xa7: + ea = ea_indexed (&cycles); + write8 (ea, reg_a); + inst_tst8 (reg_a); + cycles += 4; + break; + case 0xb7: + ea = ea_extended (); + write8 (ea, reg_a); + inst_tst8 (reg_a); + cycles += 5; + break; + /* stb */ + case 0xd7: + ea = ea_direct (); + write8 (ea, reg_b); + inst_tst8 (reg_b); + cycles += 4; + break; + case 0xe7: + ea = ea_indexed (&cycles); + write8 (ea, reg_b); + inst_tst8 (reg_b); + cycles += 4; + break; + case 0xf7: + ea = ea_extended (); + write8 (ea, reg_b); + inst_tst8 (reg_b); + cycles += 5; + break; + /* eora */ + case 0x88: + reg_a = inst_eor (reg_a, pc_read8 ()); + cycles += 2; + break; + case 0x98: + ea = ea_direct (); + reg_a = inst_eor (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xa8: + ea = ea_indexed (&cycles); + reg_a = inst_eor (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xb8: + ea = ea_extended (); + reg_a = inst_eor (reg_a, read8 (ea)); + cycles += 5; + break; + /* eorb */ + case 0xc8: + reg_b = inst_eor (reg_b, pc_read8 ()); + cycles += 2; + break; + case 0xd8: + ea = ea_direct (); + reg_b = inst_eor (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xe8: + ea = ea_indexed (&cycles); + reg_b = inst_eor (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xf8: + ea = ea_extended (); + reg_b = inst_eor (reg_b, read8 (ea)); + cycles += 5; + break; + /* adca */ + case 0x89: + reg_a = inst_adc (reg_a, pc_read8 ()); + cycles += 2; + break; + case 0x99: + ea = ea_direct (); + reg_a = inst_adc (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xa9: + ea = ea_indexed (&cycles); + reg_a = inst_adc (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xb9: + ea = ea_extended (); + reg_a = inst_adc (reg_a, read8 (ea)); + cycles += 5; + break; + /* adcb */ + case 0xc9: + reg_b = inst_adc (reg_b, pc_read8 ()); + cycles += 2; + break; + case 0xd9: + ea = ea_direct (); + reg_b = inst_adc (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xe9: + ea = ea_indexed (&cycles); + reg_b = inst_adc (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xf9: + ea = ea_extended (); + reg_b = inst_adc (reg_b, read8 (ea)); + cycles += 5; + break; + /* ora */ + case 0x8a: + reg_a = inst_or (reg_a, pc_read8 ()); + cycles += 2; + break; + case 0x9a: + ea = ea_direct (); + reg_a = inst_or (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xaa: + ea = ea_indexed (&cycles); + reg_a = inst_or (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xba: + ea = ea_extended (); + reg_a = inst_or (reg_a, read8 (ea)); + cycles += 5; + break; + /* orb */ + case 0xca: + reg_b = inst_or (reg_b, pc_read8 ()); + cycles += 2; + break; + case 0xda: + ea = ea_direct (); + reg_b = inst_or (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xea: + ea = ea_indexed (&cycles); + reg_b = inst_or (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xfa: + ea = ea_extended (); + reg_b = inst_or (reg_b, read8 (ea)); + cycles += 5; + break; + /* adda */ + case 0x8b: + reg_a = inst_add8 (reg_a, pc_read8 ()); + cycles += 2; + break; + case 0x9b: + ea = ea_direct (); + reg_a = inst_add8 (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xab: + ea = ea_indexed (&cycles); + reg_a = inst_add8 (reg_a, read8 (ea)); + cycles += 4; + break; + case 0xbb: + ea = ea_extended (); + reg_a = inst_add8 (reg_a, read8 (ea)); + cycles += 5; + break; + /* addb */ + case 0xcb: + reg_b = inst_add8 (reg_b, pc_read8 ()); + cycles += 2; + break; + case 0xdb: + ea = ea_direct (); + reg_b = inst_add8 (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xeb: + ea = ea_indexed (&cycles); + reg_b = inst_add8 (reg_b, read8 (ea)); + cycles += 4; + break; + case 0xfb: + ea = ea_extended (); + reg_b = inst_add8 (reg_b, read8 (ea)); + cycles += 5; + break; + /* subd */ + case 0x83: + set_reg_d (inst_sub16 (get_reg_d (), pc_read16 ())); + cycles += 4; + break; + case 0x93: + ea = ea_direct (); + set_reg_d (inst_sub16 (get_reg_d (), read16 (ea))); + cycles += 6; + break; + case 0xa3: + ea = ea_indexed (&cycles); + set_reg_d (inst_sub16 (get_reg_d (), read16 (ea))); + cycles += 6; + break; + case 0xb3: + ea = ea_extended (); + set_reg_d (inst_sub16 (get_reg_d (), read16 (ea))); + cycles += 7; + break; + /* cmpx */ + case 0x8c: + inst_sub16 (reg_x, pc_read16 ()); + cycles += 4; + break; + case 0x9c: + ea = ea_direct (); + inst_sub16 (reg_x, read16 (ea)); + cycles += 6; + break; + case 0xac: + ea = ea_indexed (&cycles); + inst_sub16 (reg_x, read16 (ea)); + cycles += 6; + break; + case 0xbc: + ea = ea_extended (); + inst_sub16 (reg_x, read16 (ea)); + cycles += 7; + break; + /* ldx */ + case 0x8e: + reg_x = pc_read16 (); + inst_tst16 (reg_x); + cycles += 3; + break; + case 0x9e: + ea = ea_direct (); + reg_x = read16 (ea); + inst_tst16 (reg_x); + cycles += 5; + break; + case 0xae: + ea = ea_indexed (&cycles); + reg_x = read16 (ea); + inst_tst16 (reg_x); + cycles += 5; + break; + case 0xbe: + ea = ea_extended (); + reg_x = read16 (ea); + inst_tst16 (reg_x); + cycles += 6; + break; + /* ldu */ + case 0xce: + reg_u = pc_read16 (); + inst_tst16 (reg_u); + cycles += 3; + break; + case 0xde: + ea = ea_direct (); + reg_u = read16 (ea); + inst_tst16 (reg_u); + cycles += 5; + break; + case 0xee: + ea = ea_indexed (&cycles); + reg_u = read16 (ea); + inst_tst16 (reg_u); + cycles += 5; + break; + case 0xfe: + ea = ea_extended (); + reg_u = read16 (ea); + inst_tst16 (reg_u); + cycles += 6; + break; + /* stx */ + case 0x9f: + ea = ea_direct (); + write16 (ea, reg_x); + inst_tst16 (reg_x); + cycles += 5; + break; + case 0xaf: + ea = ea_indexed (&cycles); + write16 (ea, reg_x); + inst_tst16 (reg_x); + cycles += 5; + break; + case 0xbf: + ea = ea_extended (); + write16 (ea, reg_x); + inst_tst16 (reg_x); + cycles += 6; + break; + /* stu */ + case 0xdf: + ea = ea_direct (); + write16 (ea, reg_u); + inst_tst16 (reg_u); + cycles += 5; + break; + case 0xef: + ea = ea_indexed (&cycles); + write16 (ea, reg_u); + inst_tst16 (reg_u); + cycles += 5; + break; + case 0xff: + ea = ea_extended (); + write16 (ea, reg_u); + inst_tst16 (reg_u); + cycles += 6; + break; + /* addd */ + case 0xc3: + set_reg_d (inst_add16 (get_reg_d (), pc_read16 ())); + cycles += 4; + break; + case 0xd3: + ea = ea_direct (); + set_reg_d (inst_add16 (get_reg_d (), read16 (ea))); + cycles += 6; + break; + case 0xe3: + ea = ea_indexed (&cycles); + set_reg_d (inst_add16 (get_reg_d (), read16 (ea))); + cycles += 6; + break; + case 0xf3: + ea = ea_extended (); + set_reg_d (inst_add16 (get_reg_d (), read16 (ea))); + cycles += 7; + break; + /* ldd */ + case 0xcc: + set_reg_d (pc_read16 ()); + inst_tst16 (get_reg_d ()); + cycles += 3; + break; + case 0xdc: + ea = ea_direct (); + set_reg_d (read16 (ea)); + inst_tst16 (get_reg_d ()); + cycles += 5; + break; + case 0xec: + ea = ea_indexed (&cycles); + set_reg_d (read16 (ea)); + inst_tst16 (get_reg_d ()); + cycles += 5; + break; + case 0xfc: + ea = ea_extended (); + set_reg_d (read16 (ea)); + inst_tst16 (get_reg_d ()); + cycles += 6; + break; + /* std */ + case 0xdd: + ea = ea_direct (); + write16 (ea, get_reg_d ()); + inst_tst16 (get_reg_d ()); + cycles += 5; + break; + case 0xed: + ea = ea_indexed (&cycles); + write16 (ea, get_reg_d ()); + inst_tst16 (get_reg_d ()); + cycles += 5; + break; + case 0xfd: + ea = ea_extended (); + write16 (ea, get_reg_d ()); + inst_tst16 (get_reg_d ()); + cycles += 6; + break; + /* nop */ + case 0x12: + cycles += 2; + break; + /* mul */ + case 0x3d: + r = (reg_a & 0xff) * (reg_b & 0xff); + set_reg_d (r); + + set_cc (FLAG_Z, test_z16 (r)); + set_cc (FLAG_C, (r >> 7) & 1); + + cycles += 11; + break; + /* bra */ + case 0x20: + /* brn */ + case 0x21: + inst_bra8 (0, op, &cycles); + break; + /* bhi */ + case 0x22: + /* bls */ + case 0x23: + inst_bra8 (get_cc (FLAG_C) | get_cc (FLAG_Z), op, &cycles); + break; + /* bhs/bcc */ + case 0x24: + /* blo/bcs */ + case 0x25: + inst_bra8 (get_cc (FLAG_C), op, &cycles); + break; + /* bne */ + case 0x26: + /* beq */ + case 0x27: + inst_bra8 (get_cc (FLAG_Z), op, &cycles); + break; + /* bvc */ + case 0x28: + /* bvs */ + case 0x29: + inst_bra8 (get_cc (FLAG_V), op, &cycles); + break; + /* bpl */ + case 0x2a: + /* bmi */ + case 0x2b: + inst_bra8 (get_cc (FLAG_N), op, &cycles); + break; + /* bge */ + case 0x2c: + /* blt */ + case 0x2d: + inst_bra8 (get_cc (FLAG_N) ^ get_cc (FLAG_V), op, &cycles); + break; + /* bgt */ + case 0x2e: + /* ble */ + case 0x2f: + inst_bra8 (get_cc (FLAG_Z) | + (get_cc (FLAG_N) ^ get_cc (FLAG_V)), op, &cycles); + break; + /* lbra */ + case 0x16: + r = pc_read16 (); + reg_pc += r; + cycles += 5; + break; + /* lbsr */ + case 0x17: + r = pc_read16 (); + push16 (®_s, reg_pc); + reg_pc += r; + cycles += 9; + break; + /* bsr */ + case 0x8d: + r = pc_read8 (); + push16 (®_s, reg_pc); + reg_pc += sign_extend (r); + cycles += 7; + break; + /* jsr */ + case 0x9d: + ea = ea_direct (); + push16 (®_s, reg_pc); + reg_pc = ea; + cycles += 7; + break; + case 0xad: + ea = ea_indexed (&cycles); + push16 (®_s, reg_pc); + reg_pc = ea; + cycles += 7; + break; + case 0xbd: + ea = ea_extended (); + push16 (®_s, reg_pc); + reg_pc = ea; + cycles += 8; + break; + /* leax */ + case 0x30: + reg_x = ea_indexed (&cycles); + set_cc (FLAG_Z, test_z16 (reg_x)); + cycles += 4; + break; + /* leay */ + case 0x31: + reg_y = ea_indexed (&cycles); + set_cc (FLAG_Z, test_z16 (reg_y)); + cycles += 4; + break; + /* leas */ + case 0x32: + reg_s = ea_indexed (&cycles); + cycles += 4; + break; + /* leau */ + case 0x33: + reg_u = ea_indexed (&cycles); + cycles += 4; + break; + /* pshs */ + case 0x34: + inst_psh (pc_read8 (), ®_s, reg_u, &cycles); + cycles += 5; + break; + /* puls */ + case 0x35: + inst_pul (pc_read8 (), ®_s, ®_u, &cycles); + cycles += 5; + break; + /* pshu */ + case 0x36: + inst_psh (pc_read8 (), ®_u, reg_s, &cycles); + cycles += 5; + break; + /* pulu */ + case 0x37: + inst_pul (pc_read8 (), ®_u, ®_s, &cycles); + cycles += 5; + break; + /* rts */ + case 0x39: + reg_pc = pull16 (®_s); + cycles += 5; + break; + /* abx */ + case 0x3a: + reg_x += reg_b & 0xff; + cycles += 3; + break; + /* orcc */ + case 0x1a: + reg_cc |= pc_read8 (); + cycles += 3; + break; + /* andcc */ + case 0x1c: + reg_cc &= pc_read8 (); + cycles += 3; + break; + /* sex */ + case 0x1d: + set_reg_d (sign_extend (reg_b)); + set_cc (FLAG_N, test_n (reg_a)); + set_cc (FLAG_Z, test_z16 (get_reg_d ())); + cycles += 2; + break; + /* exg */ + case 0x1e: + inst_exg (); + cycles += 8; + break; + /* tfr */ + case 0x1f: + inst_tfr (); + cycles += 6; + break; + /* rti */ + case 0x3b: + if (get_cc (FLAG_E)) { + inst_pul (0xff, ®_s, ®_u, &cycles); + } else { + inst_pul (0x81, ®_s, ®_u, &cycles); + } + + cycles += 3; + break; + /* swi */ + case 0x3f: + set_cc (FLAG_E, 1); + inst_psh (0xff, ®_s, reg_u, &cycles); + set_cc (FLAG_I, 1); + set_cc (FLAG_F, 1); + reg_pc = read16 (0xfffa); + cycles += 7; + break; + /* sync */ + case 0x13: + irq_status = IRQ_SYNC; + cycles += 2; + break; + /* daa */ + case 0x19: + i0 = reg_a; + i1 = 0; + + if ((reg_a & 0x0f) > 0x09 || get_cc (FLAG_H) == 1) { + i1 |= 0x06; + } + + if ((reg_a & 0xf0) > 0x80 && (reg_a & 0x0f) > 0x09) { + i1 |= 0x60; + } + + if ((reg_a & 0xf0) > 0x90 || get_cc (FLAG_C) == 1) { + i1 |= 0x60; + } + + reg_a = i0 + i1; + + set_cc (FLAG_N, test_n (reg_a)); + set_cc (FLAG_Z, test_z8 (reg_a)); + set_cc (FLAG_V, 0); + set_cc (FLAG_C, test_c (i0, i1, reg_a, 0)); + cycles += 2; + break; + /* cwai */ + case 0x3c: + reg_cc &= pc_read8 (); + set_cc (FLAG_E, 1); + inst_psh (0xff, ®_s, reg_u, &cycles); + irq_status = IRQ_CWAI; + cycles += 4; + break; + + /* page 1 instructions */ + + case 0x10: + op = pc_read8 (); + + switch (op) { + /* lbra */ + case 0x20: + /* lbrn */ + case 0x21: + inst_bra16 (0, op, &cycles); + break; + /* lbhi */ + case 0x22: + /* lbls */ + case 0x23: + inst_bra16 (get_cc (FLAG_C) | get_cc (FLAG_Z), op, &cycles); + break; + /* lbhs/lbcc */ + case 0x24: + /* lblo/lbcs */ + case 0x25: + inst_bra16 (get_cc (FLAG_C), op, &cycles); + break; + /* lbne */ + case 0x26: + /* lbeq */ + case 0x27: + inst_bra16 (get_cc (FLAG_Z), op, &cycles); + break; + /* lbvc */ + case 0x28: + /* lbvs */ + case 0x29: + inst_bra16 (get_cc (FLAG_V), op, &cycles); + break; + /* lbpl */ + case 0x2a: + /* lbmi */ + case 0x2b: + inst_bra16 (get_cc (FLAG_N), op, &cycles); + break; + /* lbge */ + case 0x2c: + /* lblt */ + case 0x2d: + inst_bra16 (get_cc (FLAG_N) ^ get_cc (FLAG_V), op, &cycles); + break; + /* lbgt */ + case 0x2e: + /* lble */ + case 0x2f: + inst_bra16 (get_cc (FLAG_Z) | + (get_cc (FLAG_N) ^ get_cc (FLAG_V)), op, &cycles); + break; + /* cmpd */ + case 0x83: + inst_sub16 (get_reg_d (), pc_read16 ()); + cycles += 5; + break; + case 0x93: + ea = ea_direct (); + inst_sub16 (get_reg_d (), read16 (ea)); + cycles += 7; + break; + case 0xa3: + ea = ea_indexed (&cycles); + inst_sub16 (get_reg_d (), read16 (ea)); + cycles += 7; + break; + case 0xb3: + ea = ea_extended (); + inst_sub16 (get_reg_d (), read16 (ea)); + cycles += 8; + break; + /* cmpy */ + case 0x8c: + inst_sub16 (reg_y, pc_read16 ()); + cycles += 5; + break; + case 0x9c: + ea = ea_direct (); + inst_sub16 (reg_y, read16 (ea)); + cycles += 7; + break; + case 0xac: + ea = ea_indexed (&cycles); + inst_sub16 (reg_y, read16 (ea)); + cycles += 7; + break; + case 0xbc: + ea = ea_extended (); + inst_sub16 (reg_y, read16 (ea)); + cycles += 8; + break; + /* ldy */ + case 0x8e: + reg_y = pc_read16 (); + inst_tst16 (reg_y); + cycles += 4; + break; + case 0x9e: + ea = ea_direct (); + reg_y = read16 (ea); + inst_tst16 (reg_y); + cycles += 6; + break; + case 0xae: + ea = ea_indexed (&cycles); + reg_y = read16 (ea); + inst_tst16 (reg_y); + cycles += 6; + break; + case 0xbe: + ea = ea_extended (); + reg_y = read16 (ea); + inst_tst16 (reg_y); + cycles += 7; + break; + /* sty */ + case 0x9f: + ea = ea_direct (); + write16 (ea, reg_y); + inst_tst16 (reg_y); + cycles += 6; + break; + case 0xaf: + ea = ea_indexed (&cycles); + write16 (ea, reg_y); + inst_tst16 (reg_y); + cycles += 6; + break; + case 0xbf: + ea = ea_extended (); + write16 (ea, reg_y); + inst_tst16 (reg_y); + cycles += 7; + break; + /* lds */ + case 0xce: + reg_s = pc_read16 (); + inst_tst16 (reg_s); + cycles += 4; + break; + case 0xde: + ea = ea_direct (); + reg_s = read16 (ea); + inst_tst16 (reg_s); + cycles += 6; + break; + case 0xee: + ea = ea_indexed (&cycles); + reg_s = read16 (ea); + inst_tst16 (reg_s); + cycles += 6; + break; + case 0xfe: + ea = ea_extended (); + reg_s = read16 (ea); + inst_tst16 (reg_s); + cycles += 7; + break; + /* sts */ + case 0xdf: + ea = ea_direct (); + write16 (ea, reg_s); + inst_tst16 (reg_s); + cycles += 6; + break; + case 0xef: + ea = ea_indexed (&cycles); + write16 (ea, reg_s); + inst_tst16 (reg_s); + cycles += 6; + break; + case 0xff: + ea = ea_extended (); + write16 (ea, reg_s); + inst_tst16 (reg_s); + cycles += 7; + break; + /* swi2 */ + case 0x3f: + set_cc (FLAG_E, 1); + inst_psh (0xff, ®_s, reg_u, &cycles); + reg_pc = read16 (0xfff4); + cycles += 8; + break; + default: + printf ("unknown page-1 op code: %.2x\n", op); + break; + } + + break; + + /* page 2 instructions */ + + case 0x11: + op = pc_read8 (); + + switch (op) { + /* cmpu */ + case 0x83: + inst_sub16 (reg_u, pc_read16 ()); + cycles += 5; + break; + case 0x93: + ea = ea_direct (); + inst_sub16 (reg_u, read16 (ea)); + cycles += 7; + break; + case 0xa3: + ea = ea_indexed (&cycles); + inst_sub16 (reg_u, read16 (ea)); + cycles += 7; + break; + case 0xb3: + ea = ea_extended (); + inst_sub16 (reg_u, read16 (ea)); + cycles += 8; + break; + /* cmps */ + case 0x8c: + inst_sub16 (reg_s, pc_read16 ()); + cycles += 5; + break; + case 0x9c: + ea = ea_direct (); + inst_sub16 (reg_s, read16 (ea)); + cycles += 7; + break; + case 0xac: + ea = ea_indexed (&cycles); + inst_sub16 (reg_s, read16 (ea)); + cycles += 7; + break; + case 0xbc: + ea = ea_extended (); + inst_sub16 (reg_s, read16 (ea)); + cycles += 8; + break; + /* swi3 */ + case 0x3f: + set_cc (FLAG_E, 1); + inst_psh (0xff, ®_s, reg_u, &cycles); + reg_pc = read16 (0xfff2); + cycles += 8; + break; + default: + printf ("unknown page-2 op code: %.2x\n", op); + break; + } + + break; + + default: + printf ("unknown page-0 op code: %.2x\n", op); + break; + } + + return cycles; +} + diff --git a/MCUME_esp32/espvectrex/main/e6809.h b/MCUME_esp32/espvectrex/main/e6809.h new file mode 100755 index 0000000..43c205f --- /dev/null +++ b/MCUME_esp32/espvectrex/main/e6809.h @@ -0,0 +1,12 @@ +#ifndef __E6809_H +#define __E6809_H + +/* user defined read and write functions */ + +extern unsigned char (*e6809_read8) (unsigned address); +extern void (*e6809_write8) (unsigned address, unsigned char data); + +void e6809_reset (void); +unsigned e6809_sstep (unsigned irq_i, unsigned irq_f); + +#endif \ No newline at end of file diff --git a/MCUME_esp32/espvectrex/main/e8910.c b/MCUME_esp32/espvectrex/main/e8910.c new file mode 100755 index 0000000..3044111 --- /dev/null +++ b/MCUME_esp32/espvectrex/main/e8910.c @@ -0,0 +1,537 @@ +#include +#include +#include +//#include "SDL.h" + +#define SOUND_FREQ 22050 +#define SOUND_SAMPLE 1024 + +/*************************************************************************** + + ay8910.c + + + Emulation of the AY-3-8910 / YM2149 sound chip. + + Based on various code snippets by Ville Hallik, Michael Cuddy, + Tatsuyuki Satoh, Fabrice Frances, Nicola Salmoria. + +***************************************************************************/ + +#define MAX_OUTPUT 0x0fff +//#define MAX_OUTPUT 0x7f + +#define STEP3 1 +#define STEP2 length +#define STEP 2 + + +typedef int INT32; +typedef unsigned int UINT32; +typedef char INT8; +typedef unsigned char UINT8; + +struct AY8910 { + int index; + int ready; + unsigned *Regs; + INT32 lastEnable; + INT32 PeriodA,PeriodB,PeriodC,PeriodN,PeriodE; + INT32 CountA,CountB,CountC,CountN,CountE; + UINT32 VolA,VolB,VolC,VolE; + UINT8 EnvelopeA,EnvelopeB,EnvelopeC; + UINT8 OutputA,OutputB,OutputC,OutputN; + INT8 CountEnv; + UINT8 Hold,Alternate,Attack,Holding; + INT32 RNG; + unsigned int VolTable[32]; + +} PSG; + +/* register id's */ +#define AY_AFINE (0) +#define AY_ACOARSE (1) +#define AY_BFINE (2) +#define AY_BCOARSE (3) +#define AY_CFINE (4) +#define AY_CCOARSE (5) +#define AY_NOISEPER (6) +#define AY_ENABLE (7) +#define AY_AVOL (8) +#define AY_BVOL (9) +#define AY_CVOL (10) +#define AY_EFINE (11) +#define AY_ECOARSE (12) +#define AY_ESHAPE (13) + +#define AY_PORTA (14) +#define AY_PORTB (15) + +void e8910_write(int r, int v) +{ + int old; + + if (PSG.Regs == NULL) return; + PSG.Regs[r] = v; + + /* A note about the period of tones, noise and envelope: for speed reasons,*/ + /* we count down from the period to 0, but careful studies of the chip */ + /* output prove that it instead counts up from 0 until the counter becomes */ + /* greater or equal to the period. This is an important difference when the*/ + /* program is rapidly changing the period to modulate the sound. */ + /* To compensate for the difference, when the period is changed we adjust */ + /* our internal counter. */ + /* Also, note that period = 0 is the same as period = 1. This is mentioned */ + /* in the YM2203 data sheets. However, this does NOT apply to the Envelope */ + /* period. In that case, period = 0 is half as period = 1. */ + switch( r ) + { + case AY_AFINE: + case AY_ACOARSE: + PSG.Regs[AY_ACOARSE] &= 0x0f; + old = PSG.PeriodA; + PSG.PeriodA = (PSG.Regs[AY_AFINE] + 256 * PSG.Regs[AY_ACOARSE]) * STEP3; + if (PSG.PeriodA == 0) PSG.PeriodA = STEP3; + PSG.CountA += PSG.PeriodA - old; + if (PSG.CountA <= 0) PSG.CountA = 1; + break; + case AY_BFINE: + case AY_BCOARSE: + PSG.Regs[AY_BCOARSE] &= 0x0f; + old = PSG.PeriodB; + PSG.PeriodB = (PSG.Regs[AY_BFINE] + 256 * PSG.Regs[AY_BCOARSE]) * STEP3; + if (PSG.PeriodB == 0) PSG.PeriodB = STEP3; + PSG.CountB += PSG.PeriodB - old; + if (PSG.CountB <= 0) PSG.CountB = 1; + break; + case AY_CFINE: + case AY_CCOARSE: + PSG.Regs[AY_CCOARSE] &= 0x0f; + old = PSG.PeriodC; + PSG.PeriodC = (PSG.Regs[AY_CFINE] + 256 * PSG.Regs[AY_CCOARSE]) * STEP3; + if (PSG.PeriodC == 0) PSG.PeriodC = STEP3; + PSG.CountC += PSG.PeriodC - old; + if (PSG.CountC <= 0) PSG.CountC = 1; + break; + case AY_NOISEPER: + PSG.Regs[AY_NOISEPER] &= 0x1f; + old = PSG.PeriodN; + PSG.PeriodN = PSG.Regs[AY_NOISEPER] * STEP3; + if (PSG.PeriodN == 0) PSG.PeriodN = STEP3; + PSG.CountN += PSG.PeriodN - old; + if (PSG.CountN <= 0) PSG.CountN = 1; + break; + case AY_ENABLE: + PSG.lastEnable = PSG.Regs[AY_ENABLE]; + break; + case AY_AVOL: + PSG.Regs[AY_AVOL] &= 0x1f; + PSG.EnvelopeA = PSG.Regs[AY_AVOL] & 0x10; + PSG.VolA = PSG.EnvelopeA ? PSG.VolE : PSG.VolTable[PSG.Regs[AY_AVOL] ? PSG.Regs[AY_AVOL]*2+1 : 0]; + break; + case AY_BVOL: + PSG.Regs[AY_BVOL] &= 0x1f; + PSG.EnvelopeB = PSG.Regs[AY_BVOL] & 0x10; + PSG.VolB = PSG.EnvelopeB ? PSG.VolE : PSG.VolTable[PSG.Regs[AY_BVOL] ? PSG.Regs[AY_BVOL]*2+1 : 0]; + break; + case AY_CVOL: + PSG.Regs[AY_CVOL] &= 0x1f; + PSG.EnvelopeC = PSG.Regs[AY_CVOL] & 0x10; + PSG.VolC = PSG.EnvelopeC ? PSG.VolE : PSG.VolTable[PSG.Regs[AY_CVOL] ? PSG.Regs[AY_CVOL]*2+1 : 0]; + break; + case AY_EFINE: + case AY_ECOARSE: + old = PSG.PeriodE; + PSG.PeriodE = ((PSG.Regs[AY_EFINE] + 256 * PSG.Regs[AY_ECOARSE])) * STEP3; + //if (PSG.PeriodE == 0) PSG.PeriodE = STEP3 / 2; + if (PSG.PeriodE == 0) PSG.PeriodE = STEP3; + PSG.CountE += PSG.PeriodE - old; + if (PSG.CountE <= 0) PSG.CountE = 1; + break; + case AY_ESHAPE: + /* envelope shapes: + C AtAlH + 0 0 x x \___ + + 0 1 x x /___ + + 1 0 0 0 \\\\ + + 1 0 0 1 \___ + + 1 0 1 0 \/\/ + ___ + 1 0 1 1 \ + + 1 1 0 0 //// + ___ + 1 1 0 1 / + + 1 1 1 0 /\/\ + + 1 1 1 1 /___ + + The envelope counter on the AY-3-8910 has 16 steps. On the YM2149 it + has twice the steps, happening twice as fast. Since the end result is + just a smoother curve, we always use the YM2149 behaviour. + */ + PSG.Regs[AY_ESHAPE] &= 0x0f; + PSG.Attack = (PSG.Regs[AY_ESHAPE] & 0x04) ? 0x1f : 0x00; + if ((PSG.Regs[AY_ESHAPE] & 0x08) == 0) + { + /* if Continue = 0, map the shape to the equivalent one which has Continue = 1 */ + PSG.Hold = 1; + PSG.Alternate = PSG.Attack; + } + else + { + PSG.Hold = PSG.Regs[AY_ESHAPE] & 0x01; + PSG.Alternate = PSG.Regs[AY_ESHAPE] & 0x02; + } + PSG.CountE = PSG.PeriodE; + PSG.CountEnv = 0x1f; + PSG.Holding = 0; + PSG.VolE = PSG.VolTable[PSG.CountEnv ^ PSG.Attack]; + if (PSG.EnvelopeA) PSG.VolA = PSG.VolE; + if (PSG.EnvelopeB) PSG.VolB = PSG.VolE; + if (PSG.EnvelopeC) PSG.VolC = PSG.VolE; + break; + case AY_PORTA: + break; + case AY_PORTB: + break; + } +} + +static void +e8910_callback(void *userdata, UINT8 *stream, int length) +{ + (void) userdata; + + int outn; + UINT8* buf1 = stream; + + /* hack to prevent us from hanging when starting filtered outputs */ + if (!PSG.ready) + { + memset(stream, 0, length * sizeof(*stream)); + return; + } + + length = length * 2; + + /* The 8910 has three outputs, each output is the mix of one of the three */ + /* tone generators and of the (single) noise generator. The two are mixed */ + /* BEFORE going into the DAC. The formula to mix each channel is: */ + /* (ToneOn | ToneDisable) & (NoiseOn | NoiseDisable). */ + /* Note that this means that if both tone and noise are disabled, the output */ + /* is 1, not 0, and can be modulated changing the volume. */ + + + /* If the channels are disabled, set their output to 1, and increase the */ + /* counter, if necessary, so they will not be inverted during this update. */ + /* Setting the output to 1 is necessary because a disabled channel is locked */ + /* into the ON state (see above); and it has no effect if the volume is 0. */ + /* If the volume is 0, increase the counter, but don't touch the output. */ + if (PSG.Regs[AY_ENABLE] & 0x01) + { + if (PSG.CountA <= STEP2) PSG.CountA += STEP2; + PSG.OutputA = 1; + } + else if (PSG.Regs[AY_AVOL] == 0) + { + /* note that I do count += length, NOT count = length + 1. You might think */ + /* it's the same since the volume is 0, but doing the latter could cause */ + /* interferencies when the program is rapidly modulating the volume. */ + if (PSG.CountA <= STEP2) PSG.CountA += STEP2; + } + if (PSG.Regs[AY_ENABLE] & 0x02) + { + if (PSG.CountB <= STEP2) PSG.CountB += STEP2; + PSG.OutputB = 1; + } + else if (PSG.Regs[AY_BVOL] == 0) + { + if (PSG.CountB <= STEP2) PSG.CountB += STEP2; + } + if (PSG.Regs[AY_ENABLE] & 0x04) + { + if (PSG.CountC <= STEP2) PSG.CountC += STEP2; + PSG.OutputC = 1; + } + else if (PSG.Regs[AY_CVOL] == 0) + { + if (PSG.CountC <= STEP2) PSG.CountC += STEP2; + } + + /* for the noise channel we must not touch OutputN - it's also not necessary */ + /* since we use outn. */ + if ((PSG.Regs[AY_ENABLE] & 0x38) == 0x38) /* all off */ + if (PSG.CountN <= STEP2) PSG.CountN += STEP2; + + outn = (PSG.OutputN | PSG.Regs[AY_ENABLE]); + + /* buffering loop */ + while (length > 0) + { + unsigned vol; + int left = 2; + /* vola, volb and volc keep track of how long each square wave stays */ + /* in the 1 position during the sample period. */ + + int vola,volb,volc; + vola = volb = volc = 0; + + do + { + int nextevent; + + if (PSG.CountN < left) nextevent = PSG.CountN; + else nextevent = left; + + if (outn & 0x08) + { + if (PSG.OutputA) vola += PSG.CountA; + PSG.CountA -= nextevent; + /* PeriodA is the half period of the square wave. Here, in each */ + /* loop I add PeriodA twice, so that at the end of the loop the */ + /* square wave is in the same status (0 or 1) it was at the start. */ + /* vola is also incremented by PeriodA, since the wave has been 1 */ + /* exactly half of the time, regardless of the initial position. */ + /* If we exit the loop in the middle, OutputA has to be inverted */ + /* and vola incremented only if the exit status of the square */ + /* wave is 1. */ + while (PSG.CountA <= 0) + { + PSG.CountA += PSG.PeriodA; + if (PSG.CountA > 0) + { + PSG.OutputA ^= 1; + if (PSG.OutputA) vola += PSG.PeriodA; + break; + } + PSG.CountA += PSG.PeriodA; + vola += PSG.PeriodA; + } + if (PSG.OutputA) vola -= PSG.CountA; + } + else + { + PSG.CountA -= nextevent; + while (PSG.CountA <= 0) + { + PSG.CountA += PSG.PeriodA; + if (PSG.CountA > 0) + { + PSG.OutputA ^= 1; + break; + } + PSG.CountA += PSG.PeriodA; + } + } + + if (outn & 0x10) + { + if (PSG.OutputB) volb += PSG.CountB; + PSG.CountB -= nextevent; + while (PSG.CountB <= 0) + { + PSG.CountB += PSG.PeriodB; + if (PSG.CountB > 0) + { + PSG.OutputB ^= 1; + if (PSG.OutputB) volb += PSG.PeriodB; + break; + } + PSG.CountB += PSG.PeriodB; + volb += PSG.PeriodB; + } + if (PSG.OutputB) volb -= PSG.CountB; + } + else + { + PSG.CountB -= nextevent; + while (PSG.CountB <= 0) + { + PSG.CountB += PSG.PeriodB; + if (PSG.CountB > 0) + { + PSG.OutputB ^= 1; + break; + } + PSG.CountB += PSG.PeriodB; + } + } + + if (outn & 0x20) + { + if (PSG.OutputC) volc += PSG.CountC; + PSG.CountC -= nextevent; + while (PSG.CountC <= 0) + { + PSG.CountC += PSG.PeriodC; + if (PSG.CountC > 0) + { + PSG.OutputC ^= 1; + if (PSG.OutputC) volc += PSG.PeriodC; + break; + } + PSG.CountC += PSG.PeriodC; + volc += PSG.PeriodC; + } + if (PSG.OutputC) volc -= PSG.CountC; + } + else + { + PSG.CountC -= nextevent; + while (PSG.CountC <= 0) + { + PSG.CountC += PSG.PeriodC; + if (PSG.CountC > 0) + { + PSG.OutputC ^= 1; + break; + } + PSG.CountC += PSG.PeriodC; + } + } + + PSG.CountN -= nextevent; + if (PSG.CountN <= 0) + { + /* Is noise output going to change? */ + if ((PSG.RNG + 1) & 2) /* (bit0^bit1)? */ + { + PSG.OutputN = ~PSG.OutputN; + outn = (PSG.OutputN | PSG.Regs[AY_ENABLE]); + } + + /* The Random Number Generator of the 8910 is a 17-bit shift */ + /* register. The input to the shift register is bit0 XOR bit3 */ + /* (bit0 is the output). This was verified on AY-3-8910 and YM2149 chips. */ + + /* The following is a fast way to compute bit17 = bit0^bit3. */ + /* Instead of doing all the logic operations, we only check */ + /* bit0, relying on the fact that after three shifts of the */ + /* register, what now is bit3 will become bit0, and will */ + /* invert, if necessary, bit14, which previously was bit17. */ + if (PSG.RNG & 1) PSG.RNG ^= 0x24000; /* This version is called the "Galois configuration". */ + PSG.RNG >>= 1; + PSG.CountN += PSG.PeriodN; + } + + left -= nextevent; + } while (left > 0); + + /* update envelope */ + if (PSG.Holding == 0) + { + PSG.CountE -= STEP; + if (PSG.CountE <= 0) + { + do + { + PSG.CountEnv--; + PSG.CountE += PSG.PeriodE; + } while (PSG.CountE <= 0); + + /* check envelope current position */ + if (PSG.CountEnv < 0) + { + if (PSG.Hold) + { + if (PSG.Alternate) + PSG.Attack ^= 0x1f; + PSG.Holding = 1; + PSG.CountEnv = 0; + } + else + { + /* if CountEnv has looped an odd number of times (usually 1), */ + /* invert the output. */ + if (PSG.Alternate && (PSG.CountEnv & 0x20)) + PSG.Attack ^= 0x1f; + + PSG.CountEnv &= 0x1f; + } + } + + PSG.VolE = PSG.VolTable[PSG.CountEnv ^ PSG.Attack]; + /* reload volume */ + if (PSG.EnvelopeA) PSG.VolA = PSG.VolE; + if (PSG.EnvelopeB) PSG.VolB = PSG.VolE; + if (PSG.EnvelopeC) PSG.VolC = PSG.VolE; + } + } + + vol = (vola * PSG.VolA + volb * PSG.VolB + volc * PSG.VolC) / (3 * STEP); + if (--length & 1) *(buf1++) = vol >> 8; + } +} + + +static void +e8910_build_mixer_table() +{ + int i; + double out; + + /* calculate the volume->voltage conversion table */ + /* The AY-3-8910 has 16 levels, in a logarithmic scale (3dB per STEP) */ + /* The YM2149 still has 16 levels for the tone generators, but 32 for */ + /* the envelope generator (1.5dB per STEP). */ + out = MAX_OUTPUT; + for (i = 31;i > 0;i--) + { + PSG.VolTable[i] = (unsigned)(out + 0.5); /* round to nearest */ + out /= 1.188502227; /* = 10 ^ (1.5/20) = 1.5dB */ + } + PSG.VolTable[0] = 0; +} + + +extern unsigned snd_regs[16]; + +void +e8910_init_sound() +{ + // SDL audio stuff + //SDL_AudioSpec reqSpec; + //SDL_AudioSpec givenSpec; + + PSG.Regs = snd_regs; + PSG.RNG = 1; + PSG.OutputA = 0; + PSG.OutputB = 0; + PSG.OutputC = 0; + PSG.OutputN = 0xff; + e8910_build_mixer_table(); + PSG.ready = 1; + + // set up audio buffering + //reqSpec.freq = SOUND_FREQ; // Audio frequency in samples per second + //reqSpec.format = AUDIO_U8; // Audio data format + //reqSpec.channels = 1; // Number of channels: 1 mono, 2 stereo + //reqSpec.samples = SOUND_SAMPLE; // Audio buffer size in samples + //reqSpec.callback = e8910_callback; // Callback function for filling the audio buffer + //reqSpec.userdata = NULL; + /* Open the audio device */ + //if ( SDL_OpenAudio(&reqSpec, &givenSpec) < 0 ){ + // fprintf(stderr, "Couldn't open audio: %s\n", SDL_GetError()); + // exit(-1); + //} + +# if 0 + fprintf(stdout, "samples:%d format=%x freq=%d\n", givenSpec.samples, givenSpec.format, givenSpec.freq); +# endif + + // Start playing audio + //SDL_PauseAudio(0); +} + +void +e8910_done_sound() +{ + //SDL_CloseAudio(); +} + diff --git a/MCUME_esp32/espvectrex/main/e8910.h b/MCUME_esp32/espvectrex/main/e8910.h new file mode 100755 index 0000000..5547598 --- /dev/null +++ b/MCUME_esp32/espvectrex/main/e8910.h @@ -0,0 +1,8 @@ +#ifndef __E8910_H +#define __E8910_H + +void e8910_init_sound(); +void e8910_done_sound(); +void e8910_write(int r, int v); + +#endif diff --git a/MCUME_esp32/espvectrex/main/emu.cpp b/MCUME_esp32/espvectrex/main/emu.cpp new file mode 100644 index 0000000..89e815f --- /dev/null +++ b/MCUME_esp32/espvectrex/main/emu.cpp @@ -0,0 +1,280 @@ +#include + +extern "C" { +#include "emuapi.h" +#include "osint.h" +#include "e8910.h" +#include "vecx.h" +} + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#include "esp_system.h" + + +extern long * vector_hash; +extern vector_t * vectors_set; + + +//#define USE_BYTEFB 1 + +#ifdef USE_BYTEFB +#define vbufsize 256*256 +unsigned char * vbuf; +#else +#define vbufsize 32*256 +unsigned char vbuf[vbufsize]; +static unsigned short line[256]; +#endif + + +void vec_Init(void) +{ + for(int i = 0; i < PALETTE_SIZE; i++){ + emu_SetPaletteEntry(i,i,i,i); + } + + vector_hash = (long*) heap_caps_malloc(VECTOR_HASH*sizeof(long),MALLOC_CAP_SPIRAM); //malloc (MEMSIZE); + if (!vector_hash)printf("SPI RAM malloc failed\n"); + vectors_set = (vector_t*) heap_caps_malloc(2 * VECTOR_CNT*sizeof(vector_t),MALLOC_CAP_SPIRAM); //malloc (MEMSIZE); + if (!vectors_set)printf("SPI RAM malloc failed\n"); + +#ifdef USE_BYTEFB + vbuf = (unsigned char*) heap_caps_malloc(vbufsize,MALLOC_CAP_SPIRAM); //malloc (MEMSIZE); + if (!vbuf)printf("SPI RAM Vbuf malloc failed\n"); +#endif + + vecx_reset(); + e8910_init_sound(); +} + + + +static int k=0; + +void vec_Input(int bClick) { + //if (bClick & MASK_KEY_USER1) { + // printf("selected %d\n", isMouse); + // if (isMouse) isMouse=false; + // else isMouse=true; + //} + k = emu_ReadKeys(); +} + +#ifdef USE_BYTEFB +#define myPixel(x,y,c) vbuf[(y)*256+(x)]=c; +#else +const unsigned char bitsmask[8] = {0x80,0x40,0x20,0x10,0x8,0x4,0x2,0x1}; +#define myPixel(x,y,c) vbuf[(y)*32+((x)>>3)]|=bitsmask[(x)&7]; +#endif + + +/* +static void dummyline(int x1,int y1, int x2, int y2, unsigned char c ) +{ + vbuf[y1*256+x1]=c; + vbuf[y2*256+x2]=c; +} +*/ + +static void sline(int x, int y, int x2, int y2, unsigned char c) { + bool yLonger=false; + int incrementVal, endVal; + int shortLen=y2-y; + int longLen=x2-x; + + if (shortLen == longLen) { + myPixel(x,y,c); + return; + } + + if (abs(shortLen)>abs(longLen)) { + int swap=shortLen; + shortLen=longLen; + longLen=swap; + yLonger=true; + } + endVal=longLen; + if (longLen<0) { + incrementVal=-1; + longLen=-longLen; + } else incrementVal=1; + + int decInc; + if (longLen==0) decInc=0; + else decInc = (shortLen << 16) / longLen; + int j=0; + if (yLonger) { + for (int i=0;i!=endVal;i+=incrementVal) { + myPixel(x+(j >> 16),y+i,c); + j+=decInc; + } + } else { + for (int i=0;i!=endVal;i+=incrementVal) { + myPixel(x+i,y+(j >> 16),c); + j+=decInc; + } + } +} + + +static void fline(int x, int y, int x2, int y2, unsigned char c) { + bool yLonger=false; + int shortLen=y2-y; + int longLen=x2-x; + + if (shortLen == longLen) { + myPixel(x,y,c); + return; + } + if (abs(shortLen)>abs(longLen)) { + int swap=shortLen; + shortLen=longLen; + longLen=swap; + yLonger=true;; + } + int decInc; + if (longLen==0) decInc=0; + else decInc = (shortLen << 8) / longLen; + + if (yLonger) { + if (longLen>0) { + longLen+=y; + for (int j=0x80+(x<<8);y<=longLen;++y) { + myPixel(j >> 8,y,c); + j+=decInc; + } + return; + } + longLen+=y; + for (int j=0x80+(x<<8);y>=longLen;--y) { + myPixel(j >> 8,y,c); + j-=decInc; + } + return; + } + + if (longLen>0) { + longLen+=x; + for (int j=0x80+(y<<8);x<=longLen;++x) { + myPixel(x,j >> 8,c); + j+=decInc; + } + return; + } + longLen+=x; + for (int j=0x80+(y<<8);x>=longLen;--x) { + myPixel(x,j >> 8,c); + j-=decInc; + } + +} + + +#define min(x,y) ((x>8)]; + for(int x = 0; x < 32; x++){ + unsigned char b=*vbufpt++; + if (b&0x80) line[pix++]=0xffff; + else line[pix++]=0x0000; + if (b&0x40) line[pix++]=0xffff; + else line[pix++]=0x0000; + if (b&0x20) line[pix++]=0xffff; + else line[pix++]=0x0000; + if (b&0x10) line[pix++]=0xffff; + else line[pix++]=0x0000; + if (b&0x8) line[pix++]=0xffff; + else line[pix++]=0x0000; + if (b&0x4) line[pix++]=0xffff; + else line[pix++]=0x0000; + if (b&0x2) line[pix++]=0xffff; + else line[pix++]=0x0000; + if (b&0x1) line[pix++]=0xffff; + else line[pix++]=0x0000; + } + emu_DrawLine16(&line[0], 256, 240, y); + ymul += yinc; + } +#endif +} + + + +void vec_Step(void) +{ + vecx_emu(1500*20); + + alg_jch0 = 0x80; + alg_jch1 = 0x80; + snd_regs[14] |= 0x0f; + if (( k & MASK_JOY1_RIGHT) || ( k & MASK_JOY2_RIGHT)) { + alg_jch0 = 0x00; + } + else if (( k & MASK_JOY1_LEFT) || ( k & MASK_JOY2_LEFT)) { + alg_jch0 = 0xff; + } + else if (( k & MASK_JOY1_UP) || ( k & MASK_JOY2_UP)) { + alg_jch1 = 0xff; + } + else if (( k & MASK_JOY1_DOWN) || ( k & MASK_JOY2_DOWN)) { + alg_jch1 = 0x00; + } + else if ( (k & MASK_JOY1_BTN) || ( k & MASK_JOY2_BTN) ) { + snd_regs[14] &= ~0x01; + } + else if ( k & MASK_KEY_USER1) { + snd_regs[14] &= ~0x02; + } + else if ( k & MASK_KEY_USER2) { + snd_regs[14] &= ~0x04; + } +} + +void vec_Start(char * filename) +{ + memset(cart, 0, sizeof (cart)); + + int romsize = emu_FileSize(filename); + if (emu_FileOpen(filename)) { + if (emu_FileRead((char*)cart, romsize) != romsize ) { + printf("could not load rom %s\n",filename); + } + emu_FileClose(); + } + +} + diff --git a/MCUME_esp32/espvectrex/main/emu.h b/MCUME_esp32/espvectrex/main/emu.h new file mode 100644 index 0000000..f1d2d47 --- /dev/null +++ b/MCUME_esp32/espvectrex/main/emu.h @@ -0,0 +1,4 @@ +extern void vec_Init(void); +extern void vec_Step(void); +extern void vec_Start(char * filename); +extern void vec_Input(int bClick); diff --git a/MCUME_esp32/espvectrex/main/emuapi.cpp b/MCUME_esp32/espvectrex/main/emuapi.cpp new file mode 100644 index 0000000..adb82d9 --- /dev/null +++ b/MCUME_esp32/espvectrex/main/emuapi.cpp @@ -0,0 +1,1113 @@ +#define KEYMAP_PRESENT 1 + +#include +#include +#include +#include + +extern "C" { + #include "emuapi.h" + #include "iopins.h" +} + +#include "ili9341_t3dma.h" +//#include "logo.h" +#include "bmpjoy.h" +#include "bmpvbar.h" + +#include "esp_event.h" +#include "esp_vfs_fat.h" +#include "driver/sdspi_host.h" +#include +#include +#include + +#ifdef HAS_I2CKBD +#ifdef USE_WIRE +#include "Wire.h" +#else +#include +#define ACK_CHECK_EN 0x1 /*!< I2C master will check ack from slave*/ +#define ACK_CHECK_DIS 0x0 /*!< I2C master will not check ack from slave */ +#define ACK_VAL 0x0 /*!< I2C ack value */ +#define NACK_VAL 0x1 /*!< I2C nack value */ +#endif + +#define I2C_FREQ_HZ 400000 /*!< I2C master clock frequency */ +static bool i2cKeyboardPresent = false; +#endif + + +extern ILI9341_t3DMA tft; + +static char romspath[64]; +static int calMinX=-1,calMinY=-1,calMaxX=-1,calMaxY=-1; +static sdmmc_card_t* card; +const uint16_t deflogo[] = { + 0x0000,0x0000 +}; +static const uint16_t * logo = deflogo; + +#define CALIBRATION_FILE "/sdcard/cal.cfg" + +#define MAX_FILENAME_SIZE 28 +#define MAX_MENULINES (MKEY_L9) +#define TEXT_HEIGHT 16 +#define TEXT_WIDTH 8 +#define MENU_FILE_XOFFSET (6*TEXT_WIDTH) +#define MENU_FILE_YOFFSET (2*TEXT_HEIGHT) +#define MENU_FILE_W (MAX_FILENAME_SIZE*TEXT_WIDTH) +#define MENU_FILE_H (MAX_MENULINES*TEXT_HEIGHT) +#define MENU_FILE_FGCOLOR RGBVAL16(0xff,0xff,0xff) +#define MENU_FILE_BGCOLOR RGBVAL16(0x00,0x00,0x20) +#define MENU_JOYS_YOFFSET (12*TEXT_HEIGHT) +#define MENU_VBAR_XOFFSET (0*TEXT_WIDTH) +#define MENU_VBAR_YOFFSET (MENU_FILE_YOFFSET) + + +#define MKEY_L1 1 +#define MKEY_L2 2 +#define MKEY_L3 3 +#define MKEY_L4 4 +#define MKEY_L5 5 +#define MKEY_L6 6 +#define MKEY_L7 7 +#define MKEY_L8 8 +#define MKEY_L9 9 +#define MKEY_UP 20 +#define MKEY_DOWN 21 +#define MKEY_JOY 22 + + +const unsigned short menutouchareas[] = { + TAREA_XY,MENU_FILE_XOFFSET,MENU_FILE_YOFFSET, + TAREA_WH,MENU_FILE_W, TEXT_HEIGHT, + TAREA_NEW_COL,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT, + + TAREA_XY,MENU_VBAR_XOFFSET,MENU_VBAR_YOFFSET, + TAREA_WH,32,48, + TAREA_NEW_COL, 72,72,8,40, + + TAREA_END}; + +const unsigned short menutouchactions[] = { + MKEY_L1,MKEY_L2,MKEY_L3,MKEY_L4,MKEY_L5,MKEY_L6,MKEY_L7,MKEY_L8,MKEY_L9, + MKEY_UP,MKEY_DOWN,ACTION_NONE,MKEY_JOY}; + + +static bool menuOn=true; +static bool callibrationOn=false; +static int callibrationStep=0; +static bool menuRedraw=true; +static int nbFiles=0; +static int curFile=0; +static int topFile=0; +static char selection[MAX_FILENAME_SIZE+1]=""; +static uint8_t prev_zt=0; + +static int readNbFiles(void) { + int totalFiles = 0; + + DIR* dir = opendir(romspath); + while (true) { + struct dirent* de = readdir(dir); + if (!de) { + // no more files + break; + } + if (de->d_type == DT_REG) { + totalFiles++; + } + else if (de->d_type == DT_DIR) { + if ( (strcmp(de->d_name,".")) && (strcmp(de->d_name,"..")) ) { + totalFiles++; + } + } + } + closedir(dir); + return totalFiles; +} + +static char captureTouchZone(const unsigned short * areas, const unsigned short * actions, int *rx, int *ry, int *rw, int * rh) { + uint16_t xt=0; + uint16_t yt=0; + uint16_t zt=0; + bool hDir=true; + + if (tft.isTouching()) + { + if (prev_zt == 0) { + prev_zt =1; + tft.readCal(&xt,&yt,&zt); + if (zt<1000) { + prev_zt=0; + return ACTION_NONE; + } + int i=0; + int k=0; + int y2=0, y1=0; + int x2=0, x1=0; + int x=KEYBOARD_X,y=KEYBOARD_Y; + int w=TAREA_W_DEF,h=TAREA_H_DEF; + uint8_t s; + while ( (s=areas[i++]) != TAREA_END ) { + if (s == TAREA_XY) { + x = areas[i++]; + y = areas[i++]; + x2 = x; + y2 = y; + } + else if (s == TAREA_WH) { + w = areas[i++]; + h = areas[i++]; + } + else if (s == TAREA_NEW_ROW) { + hDir = true; + y1 = y2; + y2 = y1 + h; + x2 = x; + } + else if (s == TAREA_NEW_COL) { + hDir = false; + x1 = x2; + x2 = x1 + w; + y2 = y; + } + else { + if (hDir) { + x1 = x2; + x2 = x1+s; + } else { + y1 = y2; + y2 = y1+s; + } + if ( (yt >= y1) && (yt < y2) && (xt >= x1) && (xt < x2) ) { + *rx = x1; + *ry = y1; + *rw = x2-x1; + *rh = y2-y1; + return (actions[k]); + } + k++; + } + } + } + prev_zt =1; + } else { + prev_zt=0; + } + + return ACTION_NONE; +} + +void toggleMenu(bool on) { + if (on) { + callibrationOn=false; + menuOn=true; + menuRedraw=true; + tft.fillScreenNoDma(RGBVAL16(0x00,0x00,0x00)); + tft.drawTextNoDma(0,0, TITLE, RGBVAL16(0x00,0xff,0xff), RGBVAL16(0x00,0x00,0xff), true); + tft.drawSpriteNoDma(MENU_VBAR_XOFFSET,MENU_VBAR_YOFFSET,(uint16_t*)bmpvbar); + } else { + menuOn = false; + } +} + + +static void callibrationInit(void) +{ + callibrationOn=true; + menuOn=false; + callibrationStep = 0; + calMinX=0,calMinY=0,calMaxX=0,calMaxY=0; + tft.fillScreenNoDma(RGBVAL16(0xff,0xff,0xff)); + tft.drawTextNoDma(0,100, " Callibration process:", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,116, " Hit the red cross at each corner", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,0, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + prev_zt = 1; +} + +static void readCallibration(void) +{ + FILE * file = fopen(CALIBRATION_FILE, "rb"); + if (file) { + fscanf(file,"%d %d %d %d\n",&calMinX,&calMinY,&calMaxX,&calMaxY); + fclose(file); + printf("Current callibration params: %d %d %d %d\n",calMinX,calMinY,calMaxX,calMaxY); + } + else { + printf("Callibration read error\n"); + } + tft.callibrateTouch(calMinX,calMinY,calMaxX,calMaxY); +} + +static void writeCallibration(void) +{ + tft.callibrateTouch(calMinX,calMinY,calMaxX,calMaxY); + FILE * file = fopen(CALIBRATION_FILE, "wb"); + if (file) { + fprintf(file,"%d %d %d %d\n",calMinX,calMinY,calMaxX,calMaxY); + fclose(file); + } + else { + printf("Callibration write error\n"); + } +} + + +bool callibrationActive(void) +{ + return (callibrationOn); +} + + + +int handleCallibration(uint16_t bClick) { + uint16_t xt=0; + uint16_t yt=0; + uint16_t zt=0; + if (tft.isTouching()) { + if (prev_zt == 0) { + prev_zt = 1; + tft.readRaw(&xt,&yt,&zt); + if (zt < 1000) { + return 0; + } + switch (callibrationStep) + { + case 0: + callibrationStep++; + tft.drawTextNoDma(0,0, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(ILI9341_TFTREALWIDTH-8,0, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMinX += xt; + calMinY += yt; + break; + case 1: + callibrationStep++; + tft.drawTextNoDma(ILI9341_TFTREALWIDTH-8,0, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(ILI9341_TFTREALWIDTH-8,ILI9341_TFTREALHEIGHT-16, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMaxX += xt; + calMinY += yt; + break; + case 2: + callibrationStep++; + tft.drawTextNoDma(ILI9341_TFTREALWIDTH-8,ILI9341_TFTREALHEIGHT-16, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,ILI9341_TFTREALHEIGHT-16, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMaxX += xt; + calMaxY += yt; + break; + case 3: + tft.fillScreenNoDma(RGBVAL16(0xff,0xff,0xff)); + tft.drawTextNoDma(0,100, " Callibration done!", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,116, " (Click center to exit)", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + callibrationStep++; + calMinX += xt; + calMaxY += yt; + break; + case 4: + if ( (xt > (ILI9341_TFTREALWIDTH/4)) && (xt < (ILI9341_TFTREALWIDTH*3)/4) + && (yt > (ILI9341_TFTREALHEIGHT/4)) && (yt < (ILI9341_TFTREALHEIGHT*3)/4) ) { + calMinX /= 2; + calMinY /= 2; + calMaxX /= 2; + calMaxY /= 2; + writeCallibration(); + toggleMenu(true); + } + else { + callibrationInit(); + } + break; + + } + vTaskDelay(100 / portTICK_PERIOD_MS); + } + } + else { + prev_zt = 0; + } + return 1; +} + + + +bool menuActive(void) +{ + return (menuOn); +} + +int handleMenu(uint16_t bClick) +{ + int action = ACTION_NONE; + + char newpath[80]; + strcpy(newpath, romspath); + strcat(newpath, "/"); + strcat(newpath, selection); + + struct stat st; + bool newPathIsDir = false; + if(stat(newpath,&st) == 0) + if((st.st_mode & S_IFDIR) != 0) + newPathIsDir = true; + + int rx=0,ry=0,rw=0,rh=0; + char c = captureTouchZone(menutouchareas, menutouchactions, &rx,&ry,&rw,&rh); + if ( ( (bClick & MASK_JOY2_BTN) || (bClick & MASK_KEY_USER1) ) && (newPathIsDir) ) { + menuRedraw=true; + strcpy(romspath,newpath); + curFile = 0; + nbFiles = readNbFiles(); + } + else if ( (c >= MKEY_L1) && (c <= MKEY_L9) ) { + if ( (topFile+(int)c-1) <= (nbFiles-1) ) + { + curFile = topFile + (int)c -1; + menuRedraw=true; + //tft.drawRectNoDma( rx,ry,rw,rh, KEYBOARD_HIT_COLOR ); + } + } + else if ( (bClick & MASK_JOY2_BTN) ) { + menuRedraw=true; + action = ACTION_RUNTFT; + } + else if (bClick & MASK_JOY2_UP) { + if (curFile!=0) { + menuRedraw=true; + curFile--; + } + } + else if ( (bClick & MASK_JOY2_RIGHT) || (c == MKEY_UP) ) { + if ((curFile-9)>=0) { + menuRedraw=true; + curFile -= 9; + } else if (curFile!=0) { + menuRedraw=true; + curFile--; + } + } + else if (bClick & MASK_JOY2_DOWN) { + if ((curFile<(nbFiles-1)) && (nbFiles)) { + curFile++; + menuRedraw=true; + } + } + else if ( (bClick & MASK_JOY2_LEFT) || (c == MKEY_DOWN) ) { + if ((curFile<(nbFiles-9)) && (nbFiles)) { + curFile += 9; + menuRedraw=true; + } + else if ((curFile<(nbFiles-1)) && (nbFiles)) { + curFile++; + menuRedraw=true; + } + } + else if ( (bClick & MASK_KEY_USER1) || (c == MKEY_JOY) ) { + emu_SwapJoysticks(0); + menuRedraw=true; + } + + + if (menuRedraw && nbFiles) { + + int fileIndex = 0; + DIR* dir = opendir(romspath); + tft.drawRectNoDma(MENU_FILE_XOFFSET,MENU_FILE_YOFFSET, MENU_FILE_W, MENU_FILE_H, MENU_FILE_BGCOLOR); +// if (curFile <= (MAX_MENULINES/2-1)) topFile=0; +// else topFile=curFile-(MAX_MENULINES/2); + if (curFile <= (MAX_MENULINES-1)) topFile=0; + else topFile=curFile-(MAX_MENULINES/2); + + int i=0; + while (id_type == DT_REG) || ((de->d_type == DT_DIR) && (strcmp(de->d_name,".")) && (strcmp(de->d_name,"..")) ) ) { + if (fileIndex >= topFile) { + if ((i+topFile) < nbFiles ) { + if ((i+topFile)==curFile) { + tft.drawTextNoDma(MENU_FILE_XOFFSET,i*TEXT_HEIGHT+MENU_FILE_YOFFSET, de->d_name, RGBVAL16(0xff,0xff,0x00), RGBVAL16(0xff,0x00,0x00), true); + strcpy(selection,de->d_name); + } + else { + tft.drawTextNoDma(MENU_FILE_XOFFSET,i*TEXT_HEIGHT+MENU_FILE_YOFFSET, de->d_name, MENU_FILE_FGCOLOR, MENU_FILE_BGCOLOR, true); + } + } + i++; + } + fileIndex++; + } + } + closedir(dir); + + tft.drawSpriteNoDma(0,MENU_JOYS_YOFFSET,(uint16_t*)bmpjoy); + tft.drawTextNoDma(48,MENU_JOYS_YOFFSET+8, (emu_SwapJoysticks(1)?(char*)"SWAP=1":(char*)"SWAP=0"), RGBVAL16(0x00,0xff,0xff), RGBVAL16(0xff,0x00,0x00), false); + + menuRedraw=false; + } + + + return (action); +} + +char * menuSelection(void) +{ + //static char nnewpath[80]; + //strcpy(nnewpath, romspath); + //strcat(nnewpath, "/"); + //strcat(nnewpath, selection); + //return (nnewpath); + return (selection); +} + +#ifdef HAS_I2CKBD +#ifdef USE_WIRE +#else +static esp_err_t i2c_master_read_slave_reg(i2c_port_t i2c_num, uint8_t i2c_addr, uint8_t* data_rd, size_t size) +{ + if (size == 0) { + return ESP_OK; + } + i2c_cmd_handle_t cmd = i2c_cmd_link_create(); + i2c_master_start(cmd); + i2c_master_write_byte(cmd, ( i2c_addr << 1 ) | I2C_MASTER_READ, ACK_CHECK_EN); + if (size > 1) { + i2c_master_read(cmd, data_rd, size - 1, (i2c_ack_type_t)ACK_VAL); + } + i2c_master_read_byte(cmd, data_rd + size - 1, (i2c_ack_type_t)NACK_VAL); + i2c_master_stop(cmd); + esp_err_t ret = i2c_master_cmd_begin(i2c_num, cmd, 1000 / portTICK_RATE_MS); + i2c_cmd_link_delete(cmd); + return ret; +} +#endif +#endif + + +void emu_init(void) +{ + + esp_err_t ret = 0; + + printf("mounting sd...\n"); + + sdmmc_host_t host = SDSPI_HOST_DEFAULT(); + host.max_freq_khz = 10000; + //host.slot = HSPI_HOST; + + sdspi_slot_config_t slot_config = SDSPI_SLOT_CONFIG_DEFAULT(); + slot_config.gpio_miso = SPIN_NUM_MISO; + slot_config.gpio_mosi = SPIN_NUM_MOSI; + slot_config.gpio_sck = SPIN_NUM_CLK; + slot_config.gpio_cs = SPIN_NUM_CS; + slot_config.dma_channel = 2; + + + esp_vfs_fat_sdmmc_mount_config_t mount_config = { + .format_if_mount_failed = false, + .max_files = 5, + .allocation_unit_size = 16 * 1024 + }; + + + + while((ret = esp_vfs_fat_sdmmc_mount("/sdcard", &host, &slot_config, &mount_config, &card)) != ESP_OK) { + printf("retrying\n"); + vTaskDelay(500 / portTICK_PERIOD_MS); + } + + strcpy(romspath,"/sdcard/"); + strcat(romspath,ROMSDIR); + printf("dir is : %s\n",romspath); + + nbFiles = readNbFiles(); + printf("SD initialized, files found: %d\n",nbFiles); + +/* + tft.touchBegin(); +*/ + + + emu_InitJoysticks(); +/* + readCallibration(); + + if ((tft.isTouching()) || (emu_ReadKeys() & MASK_JOY2_BTN) ) { + callibrationInit(); + } else { +*/ + toggleMenu(true); +/* + } +*/ + +#ifdef HAS_I2CKBD + uint8_t msg[7]={0,0,0,0,0,0,0}; + +#ifdef USE_WIRE + Wire.begin(I2C_SDA_IO, I2C_SCL_IO); + Wire.requestFrom(8, 7, I2C_FREQ_HZ); // request 5 bytes from slave device #8 + int i = 0; + int hitindex=-1; + while (Wire.available() && (i<7) ) { // slave may send less than requested + uint8_t b = Wire.read(); // receive a byte + if (b != 0xff) hitindex=i; + msg[i++] = b; + } +#else + int i2c_master_port = I2C_NUM_1; + i2c_config_t conf; + conf.mode = I2C_MODE_MASTER; + conf.sda_io_num = I2C_SDA_IO; + conf.sda_pullup_en = GPIO_PULLUP_ENABLE; + conf.scl_io_num = I2C_SCL_IO; + conf.scl_pullup_en = GPIO_PULLUP_ENABLE; + conf.master.clk_speed = I2C_FREQ_HZ; + i2c_param_config((i2c_port_t)i2c_master_port, &conf); + if (i2c_driver_install((i2c_port_t)i2c_master_port, conf.mode,0, 0, 0) != ESP_OK) + printf("I2C Failed initialized\n"); + + if (i2c_master_read_slave_reg( I2C_NUM_1, 8, &msg[0], 7 ) != ESP_OK) + printf("I2C Failed \n"); +#endif + + + + + if ( (msg[0] == 0xff) && (msg[1] == 0xff) && + (msg[2] == 0xff) && (msg[3] == 0xff) && + (msg[4] == 0xff) && (msg[5] == 0xff) && (msg[6] == 0xff)) { + i2cKeyboardPresent = true; + printf("i2C keyboard found\n"); + } + +#endif +} + + +void emu_printf(char * text) +{ + printf("%s\n",text); +} + + +void emu_printi(int val) +{ + printf("%d\n",val); +} + +void * emu_Malloc(int size) +{ + void * retval = malloc(size); + if (!retval) { + printf("failled to allocate %d\n",size); + } + else { + printf("could allocate %d\n",size); + } + + return retval; +} + +void emu_Free(void * pt) +{ + free(pt); +} + + +static FILE * lastfileOpened; + + +int emu_FileOpen(char * filename) +{ + int retval = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + //printf("FileOpen...%s\n",filepath); + + lastfileOpened = fopen(filepath, "rb"); + if (lastfileOpened) { + retval = 1; + } + else { + //printf("FileOpen failed\n"); + } + return (retval); +} + +int emu_FileRead(char * buf, int size) +{ + int retval = fread(buf, 1, size, lastfileOpened); + if (retval != size) { + printf("FileRead failed\n"); + } + return (retval); +} + +unsigned char emu_FileGetc(void) { + unsigned char c; + int retval = fread(&c, 1, 1, lastfileOpened); + if (retval != 1) { + printf("emu_FileGetc failed\n"); + } + return c; +} + + +void emu_FileClose(void) +{ + fclose(lastfileOpened); +} + +int emu_FileSize(char * filename) +{ + int filesize=0; + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + printf("FileSize...%s\n",filepath); + + FILE * file = fopen(filepath, "rb"); + if (file) { + fseek(file, 0L, SEEK_END); + filesize = ftell(file); + //fseek(file, 0L, SEEK_SET); + printf("filesize is...%d\n",filesize); + fclose(file); + } + + return(filesize); +} + +int emu_FileSeek(int seek) +{ + fseek(lastfileOpened, seek, SEEK_SET); + return (seek); +} + +int emu_LoadFile(char * filename, char * buf, int size) +{ + int filesize = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + printf("LoadFile...%s\n",filepath); + + filesize = emu_FileSize(filename); + FILE * file = fopen(filepath, "rb"); + if (file) { + if (size >= filesize) + { + if (fread(buf, 1, filesize, file) != filesize) { + printf("File read failed\n"); + } + } + fclose(file); + } + + return(filesize); +} + +int emu_LoadFileSeek(char * filename, char * buf, int size, int seek) +{ + int filesize = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + printf("LoadFileSeek...%d bytes at %d from %s\n",size,seek,filepath); + + FILE * file = fopen(filepath, "rb"); + if (file) { + fseek(file, seek, SEEK_SET); + if (fread(buf, size, 1, file) != size) { + printf("File read failed\n"); + } + fclose(file); + } + + return(filesize); +} + +static int keypadval=0; +static bool joySwapped = false; +static uint16_t bLastState; +static int xRef; +static int yRef; + +int emu_ReadAnalogJoyX(int min, int max) +{ + int val; //adc1_get_raw((adc1_channel_t)PIN_JOY2_A1X); + adc2_get_raw((adc2_channel_t)PIN_JOY2_A1X, ADC_WIDTH_BIT_12,&val); + //printf("refX:%d X:%d\n",xRef,val); + val = val-xRef; + //val = ((val*140)/100); + if ( (val > -xRef/4) && (val < xRef/4) ) val = 0; +#if INVX + val = xRef-val; +#else + val = val+xRef; +#endif + + return (val*(max-min))/(xRef*2); +} + +int emu_ReadAnalogJoyY(int min, int max) +{ + int val; //= adc1_get_raw((adc1_channel_t)PIN_JOY2_A2Y); + adc2_get_raw((adc2_channel_t)PIN_JOY2_A2Y, ADC_WIDTH_BIT_12,&val); + //printf("refY:%d Y:%d\n",yRef,val); + val = val-yRef; + //val = ((val*120)/100); + if ( (val > -yRef/4) && (val < yRef/4) ) val = 0; +#if INVY + val = yRef-val; +#else + val = val+yRef; +#endif + return (val*(max-min))/(yRef*2); +} + + +static uint16_t readAnalogJoystick(void) +{ + uint16_t joysval = 0; + + int xReading = emu_ReadAnalogJoyX(0,256); + if (xReading > 128) joysval |= MASK_JOY2_LEFT; + else if (xReading < 128) joysval |= MASK_JOY2_RIGHT; + + int yReading = emu_ReadAnalogJoyY(0,256); + if (yReading < 128) joysval |= MASK_JOY2_UP; + else if (yReading > 128) joysval |= MASK_JOY2_DOWN; + +#ifdef PIN_JOY2_BTN + joysval |= ((gpio_get_level((gpio_num_t)PIN_JOY2_BTN) == 1) ? 0 : MASK_JOY2_BTN); +#endif + + return (joysval); +} + + +int emu_SwapJoysticks(int statusOnly) { + if (!statusOnly) { + if (joySwapped) { + joySwapped = false; + } + else { + joySwapped = true; + } + } + return(joySwapped?1:0); +} + +int emu_GetPad(void) +{ + return(keypadval|((joySwapped?1:0)<<7)); +} + +int emu_ReadKeys(void) +{ + uint16_t retval; + uint16_t j1 = readAnalogJoystick(); + + uint16_t j2 = 0; + + if (joySwapped) { + retval = ((j1 << 8) | j2); + } + else { + retval = ((j2 << 8) | j1); + } + +#ifdef PIN_KEY_USER1 + if (gpio_get_level((gpio_num_t)PIN_KEY_USER1) == 0 ) retval |= MASK_KEY_USER1; +#endif +#ifdef PIN_KEY_USER2 + if (gpio_get_level((gpio_num_t)PIN_KEY_USER2) == 0 ) retval |= MASK_KEY_USER2; +#endif +#ifdef PIN_KEY_USER3 + if (gpio_get_level((gpio_num_t)PIN_KEY_USER3) == 0 ) retval |= MASK_KEY_USER3; +#endif +#ifdef PIN_KEY_USER4 + if (gpio_get_level((gpio_num_t)PIN_KEY_USER4) == 0 ) retval |= MASK_KEY_USER4; +#endif + + //printf("%d\n",retval); + return (retval); +} + +unsigned short emu_DebounceLocalKeys(void) +{ + uint16_t bCurState = emu_ReadKeys(); + uint16_t bClick = bCurState & ~bLastState; + bLastState = bCurState; + + return (bClick); +} + + +int emu_ReadI2CKeyboard(void) { + int retval=0; +#ifdef HAS_I2CKBD + if (i2cKeyboardPresent) { + uint8_t msg[7]; +#ifdef USE_WIRE + Wire.requestFrom(8, 7, I2C_FREQ_HZ); // request 5 bytes from slave device #8 + int i = 0; + int hitindex=-1; + while (Wire.available() && (i<7) ) { // slave may send less than requested + uint8_t b = Wire.read(); // receive a byte + if (b != 0xff) hitindex=i; + msg[i++] = b; + } +#else + if (i2c_master_read_slave_reg( I2C_NUM_1, 8, &msg[0], 7 ) != ESP_OK) + printf("I2C Failed \n"); + int hitindex=-1; + int i = 0; + while (i<7) { + if (msg[i] != 0xff) hitindex=i; + i++; + } +#endif + //printf("I2C 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X\n", + // msg[0],msg[1],msg[2],msg[3],msg[4],msg[5],msg[6]); + if ((hitindex >=0 ) && (hitindex <=6 )) { + unsigned short match = ((~msg[hitindex])&0x00FF) | (hitindex<<8); + for (i=0; i=1) && (c <= ACTION_MAXKBDVAL) ) { + keypadval = c; + keyPressCount = 10; + vTaskDelay(50 / portTICK_PERIOD_MS); + vkeyRefresh = true; + exitVkbd = true; + } + else if (c == ACTION_EXITKBD) { + vkeyRefresh = true; + exitVkbd = true; + } + } + } + + if (vkeyRefresh) { + vkeyRefresh = false; + tft.drawSpriteNoDma(0,0,(uint16_t*)logo, rx, ry, rw, rh); + } + + if ( (exitVkbd) && (vkbActive) ) { + if (!vkbKeepOn) { + toggleVirtualkeyboard(false); + } + else { + toggleVirtualkeyboard(true); + } + } +} + +int emu_setKeymap(int index) { + if (index) { + //logo = ; + //keysw = ; + } + else { + //logo = ; + //keysw = ; + } + return 0; +} + + + +static unsigned short palette16[PALETTE_SIZE]; +static int fskip=0; + +void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index) +{ + if (index +#define TITLE " Vectrex Emulator " +#define ROMSDIR "vectrex" + +#define emu_Init(ROM) {vec_Init(); vec_Start(ROM);} +#define emu_Step(x) {vec_Step();} +#define emu_Input(x) { vec_Input(x); } + +#define VID_FRAME_SKIP 0x0 +#define PALETTE_SIZE 128 +#define SINGLELINE_RENDERING 1 +#define TFT_VBUFFER_YCROP 0 + +#define ACTION_NONE 0 +#define ACTION_MAXKBDVAL 225 +#define ACTION_EXITKBD 128 +#define ACTION_RUNTFT 129 + +#ifdef KEYMAP_PRESENT + +#define TAREA_W_DEF 32 +#define TAREA_H_DEF 32 +#define TAREA_END 255 +#define TAREA_NEW_ROW 254 +#define TAREA_NEW_COL 253 +#define TAREA_XY 252 +#define TAREA_WH 251 + +#define KEYBOARD_X 16 +#define KEYBOARD_Y 32 +#define KEYBOARD_KEY_H 30 +#define KEYBOARD_KEY_W 28 +#define KEYBOARD_HIT_COLOR RGBVAL16(0xff,0x00,0x00) + +const unsigned short keysw[]= +{ TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + //TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_END}; + +const unsigned short keys[]={ +'1','2','3','4','5','6','7','8','9',0xFF09, +'Q','W','E','R','T','Y','U','I','O','P', +'A','S','D','F','G','H','J','K','L', 0xFF0D, +'Z','X','C','V','B','N','M',',','.',' ' }; + + + + +#ifdef HAS_I2CKBD +const unsigned short i2ckeys[] = { + 0X0080,0X0008,0X0180,0X0108,0X0280,0X0208,0X0380,0X0308,0X0480,0X0408, + 0X0040,0X0004,0X0140,0X0104,0X0240,0X0204,0X0340,0X0304,0X0440,0X0404, + 0X0020,0X0002,0X0120,0X0102,0X0220,0X0202,0X0320,0X0302,0X0420,0X0402, + 0X0010,0X0001,0X0110,0X0101,0X0210,0X0201,0X0310,0X0301,0X0410,0X0401 }; + //0X0580,0X0540,0X0520,0X0510,0X0508,0X0504,0X0502,0X0501,0X0680,0X0640 }; +#endif + +#endif + +#define MASK_JOY2_RIGHT 0x0001 +#define MASK_JOY2_LEFT 0x0002 +#define MASK_JOY2_UP 0x0004 +#define MASK_JOY2_DOWN 0x0008 +#define MASK_JOY2_BTN 0x0010 +#define MASK_KEY_USER1 0x0020 +#define MASK_KEY_USER2 0x0040 +#define MASK_KEY_USER3 0x0080 +#define MASK_JOY1_RIGHT 0x0100 +#define MASK_JOY1_LEFT 0x0200 +#define MASK_JOY1_UP 0x0400 +#define MASK_JOY1_DOWN 0x0800 +#define MASK_JOY1_BTN 0x1000 +#define MASK_KEY_USER4 0x2000 + + +extern void emu_init(void); +extern void emu_printf(char * text); +extern void emu_printi(int val); +extern void * emu_Malloc(int size); +extern void emu_Free(void * pt); + +extern int emu_FileOpen(char * filename); +extern int emu_FileRead(char * buf, int size); +extern unsigned char emu_FileGetc(void); +extern int emu_FileSeek(int seek); +extern void emu_FileClose(void); +extern int emu_FileSize(char * filename); +extern int emu_LoadFile(char * filename, char * buf, int size); +extern int emu_LoadFileSeek(char * filename, char * buf, int size, int seek); + +extern void emu_InitJoysticks(void); +extern int emu_SwapJoysticks(int statusOnly); +extern unsigned short emu_DebounceLocalKeys(void); +extern int emu_ReadKeys(void); +extern int emu_GetPad(void); +extern int emu_ReadAnalogJoyX(int min, int max); +extern int emu_ReadAnalogJoyY(int min, int max); +extern int emu_ReadI2CKeyboard(void); +extern int emu_setKeymap(int index); + +extern void emu_sndInit(); +extern void emu_sndPlaySound(int chan, int volume, int freq); +extern void emu_sndPlayBuzz(int size, int val); + +extern void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index); +extern void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride); +extern void emu_DrawLine(unsigned char * VBuf, int width, int height, int line); +extern void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line); +extern void emu_DrawVsync(void); +extern int emu_FrameSkip(void); + + +#endif + + + + diff --git a/MCUME_esp32/espvectrex/main/font8x8.h b/MCUME_esp32/espvectrex/main/font8x8.h new file mode 100644 index 0000000..bab272e --- /dev/null +++ b/MCUME_esp32/espvectrex/main/font8x8.h @@ -0,0 +1,136 @@ + +// Font: c64_lower.64c + +const unsigned char font8x8[128][8] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0000 (nul) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0001 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0002 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0003 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0004 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0005 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0006 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0007 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0008 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0009 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000A + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000B + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000C + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000E + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000F + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0010 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0011 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0012 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0013 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0014 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0015 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0016 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0017 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0018 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0019 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001A + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001B + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001C + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001E + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001F + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0020 (space) + { 0x18, 0x3C, 0x3C, 0x18, 0x18, 0x00, 0x18, 0x00}, // U+0021 (!) + { 0x36, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0022 (") + { 0x36, 0x36, 0x7F, 0x36, 0x7F, 0x36, 0x36, 0x00}, // U+0023 (#) + { 0x0C, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x0C, 0x00}, // U+0024 ($) + { 0x00, 0x63, 0x33, 0x18, 0x0C, 0x66, 0x63, 0x00}, // U+0025 (%) + { 0x1C, 0x36, 0x1C, 0x6E, 0x3B, 0x33, 0x6E, 0x00}, // U+0026 (&) + { 0x06, 0x06, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0027 (') + { 0x18, 0x0C, 0x06, 0x06, 0x06, 0x0C, 0x18, 0x00}, // U+0028 (() + { 0x06, 0x0C, 0x18, 0x18, 0x18, 0x0C, 0x06, 0x00}, // U+0029 ()) + { 0x00, 0x66, 0x3C, 0xFF, 0x3C, 0x66, 0x00, 0x00}, // U+002A (*) + { 0x00, 0x0C, 0x0C, 0x3F, 0x0C, 0x0C, 0x00, 0x00}, // U+002B (+) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x06}, // U+002C (,) + { 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00}, // U+002D (-) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00}, // U+002E (.) + { 0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x01, 0x00}, // U+002F (/) + { 0x3E, 0x63, 0x73, 0x7B, 0x6F, 0x67, 0x3E, 0x00}, // U+0030 (0) + { 0x0C, 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x3F, 0x00}, // U+0031 (1) + { 0x1E, 0x33, 0x30, 0x1C, 0x06, 0x33, 0x3F, 0x00}, // U+0032 (2) + { 0x1E, 0x33, 0x30, 0x1C, 0x30, 0x33, 0x1E, 0x00}, // U+0033 (3) + { 0x38, 0x3C, 0x36, 0x33, 0x7F, 0x30, 0x78, 0x00}, // U+0034 (4) + { 0x3F, 0x03, 0x1F, 0x30, 0x30, 0x33, 0x1E, 0x00}, // U+0035 (5) + { 0x1C, 0x06, 0x03, 0x1F, 0x33, 0x33, 0x1E, 0x00}, // U+0036 (6) + { 0x3F, 0x33, 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x00}, // U+0037 (7) + { 0x1E, 0x33, 0x33, 0x1E, 0x33, 0x33, 0x1E, 0x00}, // U+0038 (8) + { 0x1E, 0x33, 0x33, 0x3E, 0x30, 0x18, 0x0E, 0x00}, // U+0039 (9) + { 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x00}, // U+003A (:) + { 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x06}, // U+003B (//) + { 0x18, 0x0C, 0x06, 0x03, 0x06, 0x0C, 0x18, 0x00}, // U+003C (<) + { 0x00, 0x00, 0x3F, 0x00, 0x00, 0x3F, 0x00, 0x00}, // U+003D (=) + { 0x06, 0x0C, 0x18, 0x30, 0x18, 0x0C, 0x06, 0x00}, // U+003E (>) + { 0x1E, 0x33, 0x30, 0x18, 0x0C, 0x00, 0x0C, 0x00}, // U+003F (?) + { 0x3E, 0x63, 0x7B, 0x7B, 0x7B, 0x03, 0x1E, 0x00}, // U+0040 (@) + { 0x0C, 0x1E, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x00}, // U+0041 (A) + { 0x3F, 0x66, 0x66, 0x3E, 0x66, 0x66, 0x3F, 0x00}, // U+0042 (B) + { 0x3C, 0x66, 0x03, 0x03, 0x03, 0x66, 0x3C, 0x00}, // U+0043 (C) + { 0x1F, 0x36, 0x66, 0x66, 0x66, 0x36, 0x1F, 0x00}, // U+0044 (D) + { 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x46, 0x7F, 0x00}, // U+0045 (E) + { 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x06, 0x0F, 0x00}, // U+0046 (F) + { 0x3C, 0x66, 0x03, 0x03, 0x73, 0x66, 0x7C, 0x00}, // U+0047 (G) + { 0x33, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x33, 0x00}, // U+0048 (H) + { 0x1E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0049 (I) + { 0x78, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E, 0x00}, // U+004A (J) + { 0x67, 0x66, 0x36, 0x1E, 0x36, 0x66, 0x67, 0x00}, // U+004B (K) + { 0x0F, 0x06, 0x06, 0x06, 0x46, 0x66, 0x7F, 0x00}, // U+004C (L) + { 0x63, 0x77, 0x7F, 0x7F, 0x6B, 0x63, 0x63, 0x00}, // U+004D (M) + { 0x63, 0x67, 0x6F, 0x7B, 0x73, 0x63, 0x63, 0x00}, // U+004E (N) + { 0x1C, 0x36, 0x63, 0x63, 0x63, 0x36, 0x1C, 0x00}, // U+004F (O) + { 0x3F, 0x66, 0x66, 0x3E, 0x06, 0x06, 0x0F, 0x00}, // U+0050 (P) + { 0x1E, 0x33, 0x33, 0x33, 0x3B, 0x1E, 0x38, 0x00}, // U+0051 (Q) + { 0x3F, 0x66, 0x66, 0x3E, 0x36, 0x66, 0x67, 0x00}, // U+0052 (R) + { 0x1E, 0x33, 0x07, 0x0E, 0x38, 0x33, 0x1E, 0x00}, // U+0053 (S) + { 0x3F, 0x2D, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0054 (T) + { 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x3F, 0x00}, // U+0055 (U) + { 0x33, 0x33, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00}, // U+0056 (V) + { 0x63, 0x63, 0x63, 0x6B, 0x7F, 0x77, 0x63, 0x00}, // U+0057 (W) + { 0x63, 0x63, 0x36, 0x1C, 0x1C, 0x36, 0x63, 0x00}, // U+0058 (X) + { 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x0C, 0x1E, 0x00}, // U+0059 (Y) + { 0x7F, 0x63, 0x31, 0x18, 0x4C, 0x66, 0x7F, 0x00}, // U+005A (Z) + { 0x1E, 0x06, 0x06, 0x06, 0x06, 0x06, 0x1E, 0x00}, // U+005B ([) + { 0x03, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x40, 0x00}, // U+005C (\) + { 0x1E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1E, 0x00}, // U+005D (]) + { 0x08, 0x1C, 0x36, 0x63, 0x00, 0x00, 0x00, 0x00}, // U+005E (^) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF}, // U+005F (_) + { 0x0C, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0060 (`) + { 0x00, 0x00, 0x1E, 0x30, 0x3E, 0x33, 0x6E, 0x00}, // U+0061 (a) + { 0x07, 0x06, 0x06, 0x3E, 0x66, 0x66, 0x3B, 0x00}, // U+0062 (b) + { 0x00, 0x00, 0x1E, 0x33, 0x03, 0x33, 0x1E, 0x00}, // U+0063 (c) + { 0x38, 0x30, 0x30, 0x3e, 0x33, 0x33, 0x6E, 0x00}, // U+0064 (d) + { 0x00, 0x00, 0x1E, 0x33, 0x3f, 0x03, 0x1E, 0x00}, // U+0065 (e) + { 0x1C, 0x36, 0x06, 0x0f, 0x06, 0x06, 0x0F, 0x00}, // U+0066 (f) + { 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x1F}, // U+0067 (g) + { 0x07, 0x06, 0x36, 0x6E, 0x66, 0x66, 0x67, 0x00}, // U+0068 (h) + { 0x0C, 0x00, 0x0E, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0069 (i) + { 0x30, 0x00, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E}, // U+006A (j) + { 0x07, 0x06, 0x66, 0x36, 0x1E, 0x36, 0x67, 0x00}, // U+006B (k) + { 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+006C (l) + { 0x00, 0x00, 0x33, 0x7F, 0x7F, 0x6B, 0x63, 0x00}, // U+006D (m) + { 0x00, 0x00, 0x1F, 0x33, 0x33, 0x33, 0x33, 0x00}, // U+006E (n) + { 0x00, 0x00, 0x1E, 0x33, 0x33, 0x33, 0x1E, 0x00}, // U+006F (o) + { 0x00, 0x00, 0x3B, 0x66, 0x66, 0x3E, 0x06, 0x0F}, // U+0070 (p) + { 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x78}, // U+0071 (q) + { 0x00, 0x00, 0x3B, 0x6E, 0x66, 0x06, 0x0F, 0x00}, // U+0072 (r) + { 0x00, 0x00, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x00}, // U+0073 (s) + { 0x08, 0x0C, 0x3E, 0x0C, 0x0C, 0x2C, 0x18, 0x00}, // U+0074 (t) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x33, 0x6E, 0x00}, // U+0075 (u) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00}, // U+0076 (v) + { 0x00, 0x00, 0x63, 0x6B, 0x7F, 0x7F, 0x36, 0x00}, // U+0077 (w) + { 0x00, 0x00, 0x63, 0x36, 0x1C, 0x36, 0x63, 0x00}, // U+0078 (x) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x3E, 0x30, 0x1F}, // U+0079 (y) + { 0x00, 0x00, 0x3F, 0x19, 0x0C, 0x26, 0x3F, 0x00}, // U+007A (z) + { 0x38, 0x0C, 0x0C, 0x07, 0x0C, 0x0C, 0x38, 0x00}, // U+007B ({) + { 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x00}, // U+007C (|) + { 0x07, 0x0C, 0x0C, 0x38, 0x0C, 0x0C, 0x07, 0x00}, // U+007D (}) + { 0x6E, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+007E (~) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} // U+007F +}; + + diff --git a/MCUME_esp32/espvectrex/main/go.cpp b/MCUME_esp32/espvectrex/main/go.cpp new file mode 100644 index 0000000..0933fa9 --- /dev/null +++ b/MCUME_esp32/espvectrex/main/go.cpp @@ -0,0 +1,112 @@ +#include "go.h" + +extern "C" { + #include "emuapi.h" + #include "iopins.h" +} + +#include "esp_event.h" + +#include "keyboard_osd.h" +#include "ili9341_t3dma.h" +#ifdef HAS_SND +#include "AudioPlaySystem.h" +#endif + +#include "emu.h" + + +ILI9341_t3DMA tft = ILI9341_t3DMA(PIN_NUM_CS, PIN_NUM_DC, -1, PIN_NUM_MOSI, PIN_NUM_CLK, PIN_NUM_MISO, TPIN_NUM_CS, TPIN_NUM_IRQ); +#ifdef HAS_SND +AudioPlaySystem audio; +#endif + + +static void spi_task(void *args) +{ + while(true) { + tft.refresh(); + } +} + +static void input_task(void *args) +{ + while(true) { + /* + if ((emu_ReadKeys() & (MASK_KEY_USER1+MASK_KEY_USER2)) == (MASK_KEY_USER1+MASK_KEY_USER2)) { + printf("rebooting\n"); + esp_restart(); + } + */ + + uint16_t bClick = emu_DebounceLocalKeys(); + /* + if (bClick & MASK_KEY_USER2) { + printf("%d\n",emu_SwapJoysticks(1)); + emu_SwapJoysticks(0); + } + else + */ + { + emu_Input(bClick); + } +#ifdef HAS_SND + audio.step(); +#endif + vTaskDelay(20 / portTICK_PERIOD_MS); + } +} + +static void main_step() { + if (menuActive()) { + uint16_t bClick = emu_DebounceLocalKeys(); + int action = handleMenu(bClick); + char * filename = menuSelection(); + if (action == ACTION_RUNTFT) { +#ifdef HAS_SND + audio.begin(); + audio.start(); +#endif + toggleMenu(false); + tft.fillScreenNoDma( RGBVAL16(0x00,0x00,0x00) ); + xTaskCreatePinnedToCore(input_task, "inputthread", 4096, NULL, 2, NULL, 0); + emu_Init(filename); + } + //vTaskDelay(20 / portTICK_PERIOD_MS); + } + else { + emu_Step(); + } +} + + +void setup(void) +{ + printf("Starting emulator\n"); + + tft.begin(); + //tft.flipscreen(true); + tft.start(); + tft.refresh(); + + emu_init(); + + xTaskCreatePinnedToCore(spi_task, "spithread", 4096, NULL, 1, NULL, 0); + //vTaskPrioritySet(NULL, tskIDLE_PRIORITY+1); + //toggleMenu(false); + //xTaskCreatePinnedToCore(input_task, "inputthread", 4096, NULL, 2, NULL, 0); + + //emu_Init("filename"); + +} + +void loop(void) +{ + unsigned long t = esp_timer_get_time(); + main_step(); + //printf("%d\n",(int)((esp_timer_get_time()-t)/1000)); +} + + + + diff --git a/MCUME_esp32/espvectrex/main/go.h b/MCUME_esp32/espvectrex/main/go.h new file mode 100644 index 0000000..12c65e0 --- /dev/null +++ b/MCUME_esp32/espvectrex/main/go.h @@ -0,0 +1,8 @@ +#ifdef __cplusplus +extern "C" { +#endif +void setup(void); +void loop(void); +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/MCUME_esp32/espvectrex/main/ili9341_t3dma.cpp b/MCUME_esp32/espvectrex/main/ili9341_t3dma.cpp new file mode 100644 index 0000000..1d92aff --- /dev/null +++ b/MCUME_esp32/espvectrex/main/ili9341_t3dma.cpp @@ -0,0 +1,680 @@ +/* + ILI9341 SPI driver inspired from the Teensy version of Frank Bösing, 2017 +*/ + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#include "esp_system.h" +#include "driver/spi_master.h" +#include "soc/gpio_struct.h" +#include "driver/gpio.h" + +#include + +#include "ili9341_t3dma.h" +#include "font8x8.h" + + + +static spi_device_handle_t lcdspi; +static spi_transaction_t trans[MAX_SPI_TRANS]; + +static uint16_t *blocks[NR_OF_BLOCK]; +static uint8_t _rst, _cs, _dc; +static uint8_t _miso, _mosi, _clk; +static uint8_t _touch_irq, _touch_cs; + +//DRAM_ATTR static uint16_t block0[320*LINES_PER_BLOCK]; +//DRAM_ATTR static uint16_t block1[320*LINES_PER_BLOCK]; + +static const lcd_init_cmd_t ili_init_cmds[]={ + {0xEF, {0x03, 0x80, 0x02}, 3}, + {0xCF, {0x00, 0XC1, 0X30}, 3}, + {0xED, {0x64, 0x03, 0X12, 0X81}, 4}, + {0xE8, {0x85, 0x00, 0x78}, 3}, + {0xCB, {0x39, 0x2C, 0x00, 0x34, 0x02}, 5}, + {0xF7, {0x20}, 1}, + {0xEA, {0x00, 0x00}, 2}, + {ILI9341_PWCTR1, {0x23}, 1}, // Power control + {ILI9341_PWCTR2, {0x10}, 1}, // Power control + {ILI9341_VMCTR1, {0x3e, 0x28}, 2}, // VCM control + {ILI9341_VMCTR2, {0x86}, 1}, // VCM control2 + {ILI9341_MADCTL, {0x48}, 1}, // Memory Access Control + {ILI9341_PIXFMT, {0x55}, 1}, + {ILI9341_FRMCTR1, {0x00, 0x18}, 2}, + {ILI9341_DFUNCTR, {0x08, 0x82, 0x27}, 3}, // Display Function Control + {0xF2, {0x00}, 1}, // Gamma Function Disable + {ILI9341_GAMMASET, {0x01}, 1}, // Gamma curve selected + {ILI9341_GMCTRP1, {0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, + 0x4E, 0xF1, 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00}, 15}, // Set Gamma + {ILI9341_GMCTRN1, {0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, + 0x31, 0xC1, 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F}, 15}, // Set Gamma +// 3, 0xb1, 0x00, 0x1f, // FrameRate Control 61Hz + {0xb1, {0x00, 0x10}, 2}, // FrameRate Control 119Hz + {ILI9341_MADCTL, {MADCTL_MX | MADCTL_MY | MADCTL_MV | MADCTL_BGR}, 1}, + + /* Sleep out */ + {ILI9341_SLPOUT, {0}, 0x80}, + /* Display on */ + {ILI9341_DISPON, {0}, 0x80}, + + + // Area width, hight + {ILI9341_CASET, {0, 0, (ILI9341_TFTREALWIDTH)>>8, (ILI9341_TFTREALWIDTH)&0xff}, 4}, + {ILI9341_PASET, {0, 0, (ILI9341_TFTREALHEIGHT)>>8, (ILI9341_TFTREALHEIGHT)&0xff}, 4}, + + {0, {0}, 0xff}, +}; + +static void lcd_cmd(spi_device_handle_t spi, const uint8_t cmd) +{ + esp_err_t ret; + spi_transaction_t t; + memset(&t, 0, sizeof(t)); //Zero out the transaction + t.length=8; //Command is 8 bits + t.tx_buffer=&cmd; //The data is the cmd itself + t.user=(void*)0; //D/C needs to be set to 0 + t.flags=0; + ret=spi_device_polling_transmit(spi, &t); //Transmit! + assert(ret==ESP_OK); //Should have had no issues. +} + + +static void lcd_data(spi_device_handle_t spi, const uint8_t *data, int len) +{ + esp_err_t ret; + spi_transaction_t t; + if (len==0) return; //no need to send anything + memset(&t, 0, sizeof(t)); //Zero out the transaction + t.length=len*8; //Len is in bytes, transaction length is in bits. + t.tx_buffer=data; //Data + t.user=(void*)1; //D/C needs to be set to 1 + t.flags=0; + ret=spi_device_polling_transmit(spi, &t); //Transmit! + assert(ret==ESP_OK); //Should have had no issues. +} + +//This function is called (in irq context!) just before a transmission starts. It will +//set the D/C line to the value indicated in the user field. +static void lcd_spi_pre_transfer_callback(spi_transaction_t *t) +{ + int dc=(int)t->user; + gpio_set_level((gpio_num_t)_dc, dc); +} + + +//Initialize the display +static void lcd_init(spi_device_handle_t spi) +{ + //Initialize non-SPI GPIOs + gpio_set_direction((gpio_num_t)_dc, GPIO_MODE_OUTPUT); + + printf("LCD ILI9341 initialization.\n"); + //Send all the commands + + + //memcpy(ili_init_cmds, ili_init_cmdos, sizeof(ili_init_cmdos)); + int cmd=0; + while (ili_init_cmds[cmd].databytes!=0xff) { + lcd_cmd(spi, ili_init_cmds[cmd].cmd); + lcd_data(spi, ili_init_cmds[cmd].data, ili_init_cmds[cmd].databytes&0x1F); + if (ili_init_cmds[cmd].databytes&0x80) { + vTaskDelay(100 / portTICK_RATE_MS); + } + cmd++; + } + + + + //Allocate memory block buffers and DMA transactions + printf("Allocate video mem and DMA transactions\n"); + + int i=0; + trans[i].tx_data[0]=ILI9341_RAMWR; + trans[i].length=8; + trans[i].user=(void*)0; + trans[i++].flags=SPI_TRANS_USE_TXDATA; + + //blocks[0]= &block0[0]; + //blocks[1]= &block1[0]; + + int remaininglines=ILI9341_TFTREALHEIGHT; + for (int j=0; j 1)*/ blocks[j]= (uint16_t*)heap_caps_malloc(ILI9341_TFTREALWIDTH*lines_per_block*sizeof(uint16_t), MALLOC_CAP_DMA); + assert(blocks[j]!=NULL); + + trans[i].tx_buffer=blocks[j]; + trans[i].length=ILI9341_TFTREALWIDTH*2*8*lines_per_block; + trans[i].user=(void*)1; + trans[i++].flags=0; //undo SPI_TRANS_USE_TXDATA flag + + uint16_t color; + switch (j) { + case 0: + color=0xf000; + break; + case 1: + color=0x0f00; + break; + case 2: + color=0x00f0; + break; + case 3: + default: + color=0x000f; + break; + } + uint16_t * fb = blocks[j]; + for (int y=0;y>6]; + return(&block[(j&0x3F)*ILI9341_TFTREALWIDTH]); +} + + +void ILI9341_t3DMA::fillScreen(uint16_t color) { + int i,j; + color=SPI_SWAP_DATA_TX(color,16); + for (j=0; j>6]; + uint16_t * dst=&block[(j&0x3F)*ILI9341_TFTREALWIDTH]; + for (i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH]; + src=buffer; + for (i=0; i>6]; + dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH]; + src=buffer; + for (i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH+(ILI9341_TFTREALWIDTH-width)/2]; + src=buffer; + for (i=0; i>6]; + dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH+(ILI9341_TFTREALWIDTH-width)/2]; + src=buffer; + for (i=0; i height) + y += (ILI9341_TFTHEIGHT - height)/2; + uint8_t * src=buf; + uint16_t * block=blocks[y>>6]; + uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH]; + if (ILI9341_TFTWIDTH > width) + dst += (ILI9341_TFTWIDTH - width)/2; + for (int i=0; i height) + y += (ILI9341_TFTHEIGHT - height)/2; + uint16_t * src=buf; + uint16_t * block=blocks[y>>6]; + uint16_t * dst=&block[(y&0x3F)*ILI9341_TFTREALWIDTH]; + if (ILI9341_TFTWIDTH > width) + dst += (ILI9341_TFTWIDTH - width)/2; + for (int i=0; i>6]; + uint16_t * dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+x]; + for (i=0; i(arx+arw)) || ((x+w)(ary+arh)) || ((y+h) arx) && (x<(arx+arw)) ) { + arw = arw - (x-arx); + arx = arx + (x-arx); + } else { + bmp_offx = arx; + } + if ( ((x+w) > arx) && ((x+w)<(arx+arw)) ) { + arw -= (arx+arw-x-w); + } + if ( (y > ary) && (y<(ary+arh)) ) { + arh = arh - (y-ary); + ary = ary + (y-ary); + } else { + bmp_offy = ary; + } + if ( ((y+h) > ary) && ((y+h)<(ary+arh)) ) { + arh -= (ary+arh-y-h); + } + } + + + int l=ary; + bitmap = bitmap + bmp_offy*w + bmp_offx; + for (int row=0;row>6]; + uint16_t * dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+arx]; + bmp_ptr = (uint16_t*)bitmap; + for (int col=0;col>6]; + dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+x]; + bits = *charpt; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + l++; + } + block=blocks[l>>6]; + dst=&block[(l&0x3F)*ILI9341_TFTREALWIDTH+x]; + bits = *charpt++; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + l++; + } + x +=8; + } +} + + + +// TOUCH +#define _BV(bit) (1 << (bit)) +#define XPT2046_CFG_START _BV(7) +#define XPT2046_CFG_MUX(v) ((v&0b111) << (4)) +#define XPT2046_CFG_8BIT _BV(3) +#define XPT2046_CFG_12BIT (0) +#define XPT2046_CFG_SER _BV(2) +#define XPT2046_CFG_DFR (0) +#define XPT2046_CFG_PWR(v) ((v&0b11)) +#define XPT2046_MUX_Y 0b101 +#define XPT2046_MUX_X 0b001 +#define XPT2046_MUX_Z1 0b011 +#define XPT2046_MUX_Z2 0b100 + + + +static spi_device_handle_t touchspi; + +//void ILI9341_t3DMA::touchBegin(uint8_t mosi, uint8_t miso, uint8_t clk, uint8_t cs) { +void ILI9341_t3DMA::touchBegin() { + esp_err_t ret; + + gpio_set_direction((gpio_num_t)_touch_irq, GPIO_MODE_INPUT); + gpio_set_pull_mode((gpio_num_t)_touch_irq, GPIO_PULLUP_ONLY); + + spi_device_interface_config_t devcfg; + memset(&devcfg, 0, sizeof(devcfg)); + devcfg.clock_speed_hz=2500000; + devcfg.mode=0; + devcfg.spics_io_num=_touch_cs; + devcfg.queue_size=2; + devcfg.flags = SPI_DEVICE_HALFDUPLEX ; + + /* + spi_bus_config_t buscfg; + memset(&buscfg, 0, sizeof(buscfg)); + buscfg.miso_io_num=miso; + buscfg.mosi_io_num=mosi; + buscfg.sclk_io_num=clk; + buscfg.quadwp_io_num=-1; + buscfg.quadhd_io_num=-1; + buscfg.max_transfer_sz=48; + + ret=spi_bus_initialize(HSPI_HOST, &buscfg, 2); + ESP_ERROR_CHECK(ret); + */ + + ret=spi_bus_add_device(HSPI_HOST, &devcfg, &touchspi); + ESP_ERROR_CHECK(ret); +} + + +uint16_t touch_get_data(spi_device_handle_t spi, const uint8_t cmd) +{ + spi_transaction_t t; + memset(&t, 0, sizeof(t)); //Zero out the transaction + t.length=8; //Command is 8 bits + t.tx_buffer=&cmd; //The data is the cmd itself + esp_err_t ret=spi_device_polling_transmit(spi, &t); //Transmit! + if (ret==ESP_OK) { + memset(&t, 0, sizeof(t)); + t.rxlength=8*2; + t.flags = SPI_TRANS_USE_RXDATA; + ret = spi_device_polling_transmit(spi, &t); + if (ret==ESP_OK) { + printf("touch data failed\n"); + return 0; + } + } + else { + printf("touch cmd failed\n"); + } + return *(uint16_t*)t.rx_data; +} + + + +bool ILI9341_t3DMA::isTouching() +{ + return ((gpio_get_level((gpio_num_t)_touch_irq) == 0 ? true : false)); +} + +void ILI9341_t3DMA::readRo(uint16_t * oX, uint16_t * oY, uint16_t * oZ) { + uint16_t x = 0; + uint16_t y = 0; + uint16_t z1 = 0; + uint16_t z2 = 0; + uint8_t i = 0; + int16_t xraw=0, yraw=0; + + + for(; i < 15; i++) { + y += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Y) | XPT2046_CFG_PWR(3))); + x += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_X) | XPT2046_CFG_PWR(3))); + z1 += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z1)| XPT2046_CFG_PWR(3))); + z2 += touch_get_data(touchspi, (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z2)| XPT2046_CFG_PWR(3))); + } + printf("%d %d %d %d \n",x/15,y/15,z1/15,z2/15); +/* + SPI.beginTransaction(SPI_SETTING); + digitalWrite(_touch_cs, LOW); + + for(; i < 15; i++) { + // SPI requirer 32bit aliment + uint8_t buf[12] = { + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Y) | XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_X) | XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z1)| XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z2)| XPT2046_CFG_PWR(3)), 0x00, 0x00 + }; + SPI.transfer(&buf[0], &buf[0], 12); + y += (buf[1] << 8 | buf[2])>>3; + x += (buf[4] << 8 | buf[5])>>3; + z1 += (buf[7] << 8 | buf[8])>>3; + z2 += (buf[10] << 8 | buf[11])>>3; + } + */ +} + +void ILI9341_t3DMA::readRaw(uint16_t * oX, uint16_t * oY, uint16_t * oZ) { + +} + +void ILI9341_t3DMA::readCal(uint16_t * oX, uint16_t * oY, uint16_t * oZ){ + +} + +void ILI9341_t3DMA::callibrateTouch(uint16_t xMin,uint16_t yMin,uint16_t xMax,uint16_t yMax){ + +} + + diff --git a/MCUME_esp32/espvectrex/main/ili9341_t3dma.h b/MCUME_esp32/espvectrex/main/ili9341_t3dma.h new file mode 100644 index 0000000..a0c80f3 --- /dev/null +++ b/MCUME_esp32/espvectrex/main/ili9341_t3dma.h @@ -0,0 +1,154 @@ +/* + ILI9341 SPI driver inspired from the Teensy version of Frank Bösing, 2017 +*/ + +#ifndef _ILI9341_T3DMAH_ +#define _ILI9341_T3DMAH_ + + +#define FLIP_SCREEN 1 + + +#define RGBVAL32(r,g,b) ( (r<<16) | (g<<8) | b ) +#define RGBVAL16(r,g,b) ( (((r>>3)&0x1f)<<11) | (((g>>2)&0x3f)<<5) | (((b>>3)&0x1f)<<0) ) +#define RGBVAL8(r,g,b) ( (((r>>5)&0x07)<<5) | (((g>>5)&0x07)<<2) | (((b>>6)&0x3)<<0) ) + + +#define ILI9341_TFTWIDTH 256 +#define ILI9341_TFTHEIGHT 240 +#define ILI9341_TFTREALWIDTH 320 +#define ILI9341_TFTREALHEIGHT 240 + + +#define ILI9341_NOP 0x00 +#define ILI9341_SWRESET 0x01 +#define ILI9341_RDDID 0x04 +#define ILI9341_RDDST 0x09 + +#define ILI9341_SLPIN 0x10 +#define ILI9341_SLPOUT 0x11 +#define ILI9341_PTLON 0x12 +#define ILI9341_NORON 0x13 + +#define ILI9341_RDMODE 0x0A +#define ILI9341_RDMADCTL 0x0B +#define ILI9341_RDPIXFMT 0x0C +#define ILI9341_RDIMGFMT 0x0D +#define ILI9341_RDSELFDIAG 0x0F + +#define ILI9341_INVOFF 0x20 +#define ILI9341_INVON 0x21 +#define ILI9341_GAMMASET 0x26 +#define ILI9341_DISPOFF 0x28 +#define ILI9341_DISPON 0x29 + +#define ILI9341_CASET 0x2A +#define ILI9341_PASET 0x2B +#define ILI9341_RAMWR 0x2C +#define ILI9341_RAMRD 0x2E + +#define ILI9341_PTLAR 0x30 +#define ILI9341_MADCTL 0x36 +#define ILI9341_VSCRSADD 0x37 +#define ILI9341_PIXFMT 0x3A + +#define ILI9341_FRMCTR1 0xB1 +#define ILI9341_FRMCTR2 0xB2 +#define ILI9341_FRMCTR3 0xB3 +#define ILI9341_INVCTR 0xB4 +#define ILI9341_DFUNCTR 0xB6 + +#define ILI9341_PWCTR1 0xC0 +#define ILI9341_PWCTR2 0xC1 +#define ILI9341_PWCTR3 0xC2 +#define ILI9341_PWCTR4 0xC3 +#define ILI9341_PWCTR5 0xC4 +#define ILI9341_VMCTR1 0xC5 +#define ILI9341_VMCTR2 0xC7 + +#define ILI9341_RDID1 0xDA +#define ILI9341_RDID2 0xDB +#define ILI9341_RDID3 0xDC +#define ILI9341_RDID4 0xDD + +#define ILI9341_GMCTRP1 0xE0 +#define ILI9341_GMCTRN1 0xE1 + +#define MADCTL_MY 0x80 +#define MADCTL_MX 0x40 +#define MADCTL_MV 0x20 +#define MADCTL_ML 0x10 +#define MADCTL_RGB 0x00 +#define MADCTL_BGR 0x08 +#define MADCTL_MH 0x04 + +#ifdef __cplusplus + + +#define MAX_SPI_TRANS 7 +#define NR_OF_BLOCK 4 +#define LINES_PER_BLOCK 64 //(ILI9341_TFTREALHEIGHT/4) + +typedef struct { + uint8_t cmd; + uint8_t data[16]; + uint8_t databytes; //No of data in data; bit 7 = delay after set; 0xFF = end of cmds. +} lcd_init_cmd_t; + + +class ILI9341_t3DMA +{ + public: + ILI9341_t3DMA(uint8_t _CS = 17, uint8_t _DC = 18, uint8_t _RST = 255, uint8_t _MOSI=23, uint8_t _CLK=18, uint8_t _MISO=19, uint8_t touch_cs=32, uint8_t touch_irq=33); + + //void setFrameBuffer(uint16_t * fb); + //static uint16_t * getFrameBuffer(void); + + void begin(void); + void flipscreen(bool flip); + bool isflipped(void); + void start(void); + void refresh(void); + void refreshPrepare(void); + void refreshFinish(void); + //void stop(); + //void wait(void); + uint16_t * getLineBuffer(int j); + + void fillScreen(uint16_t color); + void writeScreen(int width, int height, int stride, uint8_t *buffer, uint16_t *palette16); + void writeLine(int width, int height, int stride, uint8_t *buffer, uint16_t *palette16); + void writeLine(int width, int height, int stride, uint16_t *buffer); + void drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color); + void drawSprite(int16_t x, int16_t y, const uint16_t *bitmap); + void drawSprite(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh); + void drawText(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize); + + void fillScreenNoDma(uint16_t color) { fillScreen(color); }; + void drawSpriteNoDma(int16_t x, int16_t y, const uint16_t *bitmap) { drawSprite(x,y,bitmap); }; + void drawSpriteNoDma(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh) { drawSprite(x,y,bitmap,croparx,cropary,croparw,croparh); }; + void drawRectNoDma(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color) { drawRect(x,y,w,h,color); }; + void drawTextNoDma(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize) { drawText(x,y,text,fgcolor,bgcolor,doublesize); }; + + /* + void writeScreenNoDma(const uint16_t *pcolors); + void drawPixel(int16_t x, int16_t y, uint16_t color); + uint16_t getPixel(int16_t x, int16_t y); + */ + + + void touchBegin(); + void readRo(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + bool isTouching(); + void readRaw(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + void readCal(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + void callibrateTouch(uint16_t xMin,uint16_t yMin,uint16_t xMax,uint16_t yMax); + + protected: + bool flipped=false; + void enableTouchIrq(); +}; + +#endif +#endif + diff --git a/MCUME_esp32/espvectrex/main/iopins.h b/MCUME_esp32/espvectrex/main/iopins.h new file mode 100644 index 0000000..703f6e1 --- /dev/null +++ b/MCUME_esp32/espvectrex/main/iopins.h @@ -0,0 +1,59 @@ +#ifndef IOPINS_H +#define IOPINS_H + +// ILI9341 +//#define PIN_NUM_CS (gpio_num_t)15 +//#define PIN_NUM_CLK (gpio_num_t)14 +//#define PIN_NUM_MISO (gpio_num_t)12 +//#define PIN_NUM_MOSI (gpio_num_t)13 +//#define PIN_NUM_DC (gpio_num_t)16 + +#define TPIN_NUM_CS (gpio_num_t)32 +#define TPIN_NUM_IRQ (gpio_num_t)33 + + +#define PIN_NUM_CS (gpio_num_t)22 //17 +#define PIN_NUM_CLK (gpio_num_t)18 +#define PIN_NUM_MISO (gpio_num_t)19 +#define PIN_NUM_MOSI (gpio_num_t)23 +#define PIN_NUM_DC (gpio_num_t)21 + +// SD card SPI +#define SPIN_NUM_CS (gpio_num_t)15 +#define SPIN_NUM_CLK (gpio_num_t)14 +#define SPIN_NUM_MISO (gpio_num_t)12 +#define SPIN_NUM_MOSI (gpio_num_t)13 + + +// I2C keyboard +#define I2C_SCL_IO (gpio_num_t)5 +#define I2C_SDA_IO (gpio_num_t)4 + + +// Analog joystick (primary) for JOY2 and 5 extra buttons +#define PIN_JOY2_A1X ADC2_CHANNEL_7 // 27 //ADC1_CHANNEL_0 +#define PIN_JOY2_A2Y ADC2_CHANNEL_2 // 2 //ADC1_CHANNEL_3 +#define PIN_JOY2_BTN 32 + +#define PIN_KEY_USER1 35 +#define PIN_KEY_USER2 34 +#define PIN_KEY_USER3 39 +#define PIN_KEY_USER4 36 +/* +#define PIN_KEY_ESCAPE 23 +*/ + +// Second joystick +/* +#define PIN_JOY1_BTN 30 +#define PIN_JOY1_1 16 +#define PIN_JOY1_2 17 +#define PIN_JOY1_3 18 +#define PIN_JOY1_4 19 +*/ + +#endif + + + + diff --git a/MCUME_esp32/espvectrex/main/keyboard_osd.h b/MCUME_esp32/espvectrex/main/keyboard_osd.h new file mode 100644 index 0000000..062eb4e --- /dev/null +++ b/MCUME_esp32/espvectrex/main/keyboard_osd.h @@ -0,0 +1,20 @@ + +#ifndef keyboard_osd_h_ +#define keyboard_osd_h_ + +extern bool virtualkeyboardIsActive(void); +extern void drawVirtualkeyboard(void); +extern void toggleVirtualkeyboard(bool keepOn); +extern void handleVirtualkeyboard(void); + +extern bool callibrationActive(void); +extern int handleCallibration(uint16_t bClick); + +extern bool menuActive(void); +extern char * menuSelection(void); +extern void toggleMenu(bool on); +extern int handleMenu(uint16_t bClick); + + +#endif + diff --git a/MCUME_esp32/espvectrex/main/main.c b/MCUME_esp32/espvectrex/main/main.c new file mode 100644 index 0000000..5dc5bee --- /dev/null +++ b/MCUME_esp32/espvectrex/main/main.c @@ -0,0 +1,31 @@ + +#include "freertos/FreeRTOS.h" +#include "esp_wifi.h" +#include "esp_system.h" +#include "esp_event.h" +#include "esp_event_loop.h" +#include "nvs_flash.h" +#include "driver/gpio.h" +#include "esp_partition.h" + +#include "go.h" + + +int app_main(void) +{ + printf("Test start!\n"); + + setup(); + while(1) { + loop(); + } + + for (int i = 10; i >= 0; i--) { + printf("Restarting in %d seconds...\n", i); + vTaskDelay(1000 / portTICK_PERIOD_MS); + } + printf("Restarting now.\n"); + fflush(stdout); + esp_restart(); +} + diff --git a/MCUME_esp32/espvectrex/main/osint.h b/MCUME_esp32/espvectrex/main/osint.h new file mode 100755 index 0000000..ede1ce6 --- /dev/null +++ b/MCUME_esp32/espvectrex/main/osint.h @@ -0,0 +1,8 @@ +#ifndef __OSINT_H +#define __OSINT_H + +/*extern char gbuffer[1024];*/ + +void osint_render (void); + +#endif diff --git a/MCUME_esp32/espvectrex/main/rom.h b/MCUME_esp32/espvectrex/main/rom.h new file mode 100644 index 0000000..898e4f7 --- /dev/null +++ b/MCUME_esp32/espvectrex/main/rom.h @@ -0,0 +1,514 @@ +const unsigned char rom[8192] = { +0xED,0x77,0xF8,0x50,0x30,0xE8,0x4D,0x49,0x4E,0x45,0x80,0xF8,0x50,0x00,0xDE,0x53, +0x54,0x4F,0x52,0x4D,0x80,0x00,0x8E,0xC8,0x83,0x6F,0x80,0x8C,0xCB,0xC5,0x26,0xF9, +0xBD,0xE8,0xE3,0x7C,0xC8,0x24,0x86,0xBB,0xB7,0xC8,0x80,0x8E,0x01,0x01,0xBF,0xC8, +0x81,0x8E,0xC8,0x83,0x6F,0x80,0x8C,0xCB,0x70,0x26,0xF9,0x20,0x00,0xBD,0xF1,0xAF, +0xCC,0x02,0x00,0xBD,0xF7,0xA9,0x0A,0x79,0x0F,0x56,0x0F,0x9B,0x8E,0xC8,0xA8,0xBD, +0xF8,0x4F,0x8E,0xC8,0xAF,0xBD,0xF8,0x4F,0x8E,0xC8,0xF9,0xBD,0xF8,0x4F,0xCC,0x00, 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unsigned via_t1lh; +static unsigned via_t1pb7; /* timer 1 controlled version of pb7 */ +static unsigned via_t2on; /* is timer 2 on? */ +static unsigned via_t2int; /* are timer 2 interrupts allowed? */ +static unsigned via_t2c; +static unsigned via_t2ll; +static unsigned via_sr; +static unsigned via_srb; /* number of bits shifted so far */ +static unsigned via_src; /* shift counter */ +static unsigned via_srclk; +static unsigned via_acr; +static unsigned via_pcr; +static unsigned via_ifr; +static unsigned via_ier; +static unsigned via_ca2; +static unsigned via_cb2h; /* basic handshake version of cb2 */ +static unsigned via_cb2s; /* version of cb2 controlled by the shift register */ + +/* analog devices */ + +static unsigned alg_rsh; /* zero ref sample and hold */ +static unsigned alg_xsh; /* x sample and hold */ +static unsigned alg_ysh; /* y sample and hold */ +static unsigned alg_zsh; /* z sample and hold */ +unsigned alg_jch0; /* joystick direction channel 0 */ +unsigned alg_jch1; /* joystick direction channel 1 */ +unsigned alg_jch2; /* joystick direction channel 2 */ +unsigned alg_jch3; /* joystick direction channel 3 */ +static unsigned alg_jsh; /* joystick sample and hold */ + +static unsigned alg_compare; + +static long alg_dx; /* delta x */ +static long alg_dy; /* delta y */ +static long alg_curr_x; /* current x position */ +static long alg_curr_y; /* current y position */ + + +static unsigned alg_vectoring; /* are we drawing a vector right now? */ +static long alg_vector_x0; +static long alg_vector_y0; +static long alg_vector_x1; +static long alg_vector_y1; +static long alg_vector_dx; +static long alg_vector_dy; +static unsigned char alg_vector_color; + +long vector_draw_cnt; +long vector_erse_cnt; +vector_t * vectors_set; //[2 * VECTOR_CNT]; +vector_t *vectors_draw; +vector_t *vectors_erse; + +//static long vector_hash[VECTOR_HASH]; +long * vector_hash; +static long fcycles; + +/* update the snd chips internal registers when via_ora/via_orb changes */ + +static einline void snd_update (void) +{ + switch (via_orb & 0x18) { + case 0x00: + /* the sound chip is disabled */ + break; + case 0x08: + /* the sound chip is sending data */ + break; + case 0x10: + /* the sound chip is recieving data */ + + if (snd_select != 14) { + snd_regs[snd_select] = via_ora; + e8910_write(snd_select, via_ora); + } + + break; + case 0x18: + /* the sound chip is latching an address */ + + if ((via_ora & 0xf0) == 0x00) { + snd_select = via_ora & 0x0f; + } + + break; + } +} + +/* update the various analog values when orb is written. */ + +static einline void alg_update (void) +{ + switch (via_orb & 0x06) { + case 0x00: + alg_jsh = alg_jch0; + + if ((via_orb & 0x01) == 0x00) { + /* demultiplexor is on */ + alg_ysh = alg_xsh; + } + + break; + case 0x02: + alg_jsh = alg_jch1; + + if ((via_orb & 0x01) == 0x00) { + /* demultiplexor is on */ + alg_rsh = alg_xsh; + } + + break; + case 0x04: + alg_jsh = alg_jch2; + + if ((via_orb & 0x01) == 0x00) { + /* demultiplexor is on */ + + if (alg_xsh > 0x80) { + alg_zsh = alg_xsh - 0x80; + } else { + alg_zsh = 0; + } + } + + break; + case 0x06: + /* sound output line */ + alg_jsh = alg_jch3; + break; + } + + /* compare the current joystick direction with a reference */ + + if (alg_jsh > alg_xsh) { + alg_compare = 0x20; + } else { + alg_compare = 0; + } + + /* compute the new "deltas" */ + + alg_dx = (long) alg_xsh - (long) alg_rsh; + alg_dy = (long) alg_rsh - (long) alg_ysh; +} + +/* update IRQ and bit-7 of the ifr register after making an adjustment to + * ifr. + */ + +static einline void int_update (void) +{ + if ((via_ifr & 0x7f) & (via_ier & 0x7f)) { + via_ifr |= 0x80; + } else { + via_ifr &= 0x7f; + } +} + +unsigned char read8 (unsigned address) +{ + unsigned char data; + + if ((address & 0xe000) == 0xe000) { + /* rom */ + + data = rom[address & 0x1fff]; + } else if ((address & 0xe000) == 0xc000) { + if (address & 0x800) { + /* ram */ + + data = ram[address & 0x3ff]; + } else if (address & 0x1000) { + /* io */ + + switch (address & 0xf) { + case 0x0: + /* compare signal is an input so the value does not come from + * via_orb. + */ + + if (via_acr & 0x80) { + /* timer 1 has control of bit 7 */ + + data = (unsigned char) ((via_orb & 0x5f) | via_t1pb7 | alg_compare); + } else { + /* bit 7 is being driven by via_orb */ + + data = (unsigned char) ((via_orb & 0xdf) | alg_compare); + } + + break; + case 0x1: + /* register 1 also performs handshakes if necessary */ + + if ((via_pcr & 0x0e) == 0x08) { + /* if ca2 is in pulse mode or handshake mode, then it + * goes low whenever ira is read. + */ + + via_ca2 = 0; + } + + /* fall through */ + + case 0xf: + if ((via_orb & 0x18) == 0x08) { + /* the snd chip is driving port a */ + + data = (unsigned char) snd_regs[snd_select]; + } else { + data = (unsigned char) via_ora; + } + + break; + case 0x2: + data = (unsigned char) via_ddrb; + break; + case 0x3: + data = (unsigned char) via_ddra; + break; + case 0x4: + /* T1 low order counter */ + + data = (unsigned char) via_t1c; + via_ifr &= 0xbf; /* remove timer 1 interrupt flag */ + + via_t1on = 0; /* timer 1 is stopped */ + via_t1int = 0; + via_t1pb7 = 0x80; + + int_update (); + + break; + case 0x5: + /* T1 high order counter */ + + data = (unsigned char) (via_t1c >> 8); + + break; + case 0x6: + /* T1 low order latch */ + + data = (unsigned char) via_t1ll; + break; + case 0x7: + /* T1 high order latch */ + + data = (unsigned char) via_t1lh; + break; + case 0x8: + /* T2 low order counter */ + + data = (unsigned char) via_t2c; + via_ifr &= 0xdf; /* remove timer 2 interrupt flag */ + + via_t2on = 0; /* timer 2 is stopped */ + via_t2int = 0; + + int_update (); + + break; + case 0x9: + /* T2 high order counter */ + + data = (unsigned char) (via_t2c >> 8); + break; + case 0xa: + data = (unsigned char) via_sr; + via_ifr &= 0xfb; /* remove shift register interrupt flag */ + via_srb = 0; + via_srclk = 1; + + int_update (); + + break; + case 0xb: + data = (unsigned char) via_acr; + break; + case 0xc: + data = (unsigned char) via_pcr; + break; + case 0xd: + /* interrupt flag register */ + + data = (unsigned char) via_ifr; + break; + case 0xe: + /* interrupt enable register */ + + data = (unsigned char) (via_ier | 0x80); + break; + } + } + } else if (address < 0x8000) { + /* cartridge */ + + data = cart[address]; + } else { + data = 0xff; + } + + return data; +} + +void write8 (unsigned address, unsigned char data) +{ + if ((address & 0xe000) == 0xe000) { + /* rom */ + } else if ((address & 0xe000) == 0xc000) { + /* it is possible for both ram and io to be written at the same! */ + + if (address & 0x800) { + ram[address & 0x3ff] = data; + } + + if (address & 0x1000) { + switch (address & 0xf) { + case 0x0: + via_orb = data; + + snd_update (); + + alg_update (); + + if ((via_pcr & 0xe0) == 0x80) { + /* if cb2 is in pulse mode or handshake mode, then it + * goes low whenever orb is written. + */ + + via_cb2h = 0; + } + + break; + case 0x1: + /* register 1 also performs handshakes if necessary */ + + if ((via_pcr & 0x0e) == 0x08) { + /* if ca2 is in pulse mode or handshake mode, then it + * goes low whenever ora is written. + */ + + via_ca2 = 0; + } + + /* fall through */ + + case 0xf: + via_ora = data; + + snd_update (); + + /* output of port a feeds directly into the dac which then + * feeds the x axis sample and hold. + */ + + alg_xsh = data ^ 0x80; + + alg_update (); + + break; + case 0x2: + via_ddrb = data; + break; + case 0x3: + via_ddra = data; + break; + case 0x4: + /* T1 low order counter */ + + via_t1ll = data; + + break; + case 0x5: + /* T1 high order counter */ + + via_t1lh = data; + via_t1c = (via_t1lh << 8) | via_t1ll; + via_ifr &= 0xbf; /* remove timer 1 interrupt flag */ + + via_t1on = 1; /* timer 1 starts running */ + via_t1int = 1; + via_t1pb7 = 0; + + int_update (); + + break; + case 0x6: + /* T1 low order latch */ + + via_t1ll = data; + break; + case 0x7: + /* T1 high order latch */ + + via_t1lh = data; + break; + case 0x8: + /* T2 low order latch */ + + via_t2ll = data; + break; + case 0x9: + /* T2 high order latch/counter */ + + via_t2c = (data << 8) | via_t2ll; + via_ifr &= 0xdf; + + via_t2on = 1; /* timer 2 starts running */ + via_t2int = 1; + + int_update (); + + break; + case 0xa: + via_sr = data; + via_ifr &= 0xfb; /* remove shift register interrupt flag */ + via_srb = 0; + via_srclk = 1; + + int_update (); + + break; + case 0xb: + via_acr = data; + break; + case 0xc: + via_pcr = data; + + + if ((via_pcr & 0x0e) == 0x0c) { + /* ca2 is outputting low */ + + via_ca2 = 0; + } else { + /* ca2 is disabled or in pulse mode or is + * outputting high. + */ + + via_ca2 = 1; + } + + if ((via_pcr & 0xe0) == 0xc0) { + /* cb2 is outputting low */ + + via_cb2h = 0; + } else { + /* cb2 is disabled or is in pulse mode or is + * outputting high. + */ + + via_cb2h = 1; + } + + break; + case 0xd: + /* interrupt flag register */ + + via_ifr &= ~(data & 0x7f); + int_update (); + + break; + case 0xe: + /* interrupt enable register */ + + if (data & 0x80) { + via_ier |= data & 0x7f; + } else { + via_ier &= ~(data & 0x7f); + } + + int_update (); + + break; + } + } + } else if (address < 0x8000) { + /* cartridge */ + } +} + +void vecx_reset (void) +{ + unsigned r; + + /* ram */ + + for (r = 0; r < 1024; r++) { + ram[r] = r & 0xff; + } + + for (r = 0; r < 16; r++) { + snd_regs[r] = 0; + e8910_write(r, 0); + } + + /* input buttons */ + + snd_regs[14] = 0xff; + e8910_write(14, 0xff); + + snd_select = 0; + + via_ora = 0; + via_orb = 0; + via_ddra = 0; + via_ddrb = 0; + via_t1on = 0; + via_t1int = 0; + via_t1c = 0; + via_t1ll = 0; + via_t1lh = 0; + via_t1pb7 = 0x80; + via_t2on = 0; + via_t2int = 0; + via_t2c = 0; + via_t2ll = 0; + via_sr = 0; + via_srb = 8; + via_src = 0; + via_srclk = 0; + via_acr = 0; + via_pcr = 0; + via_ifr = 0; + via_ier = 0; + via_ca2 = 1; + via_cb2h = 1; + via_cb2s = 0; + + alg_rsh = 128; + alg_xsh = 128; + alg_ysh = 128; + alg_zsh = 0; + alg_jch0 = 128; + alg_jch1 = 128; + alg_jch2 = 128; + alg_jch3 = 128; + alg_jsh = 128; + + alg_compare = 0; /* check this */ + + alg_dx = 0; + alg_dy = 0; + alg_curr_x = ALG_MAX_X / 2; + alg_curr_y = ALG_MAX_Y / 2; + + alg_vectoring = 0; + + vector_draw_cnt = 0; + vector_erse_cnt = 0; + vectors_draw = vectors_set; + vectors_erse = vectors_set + VECTOR_CNT; + + fcycles = FCYCLES_INIT; + + e6809_read8 = read8; + e6809_write8 = write8; + + e6809_reset (); +} + +/* perform a single cycle worth of via emulation. + * via_sstep0 is the first postion of the emulation. + */ + +static einline void via_sstep0 (void) +{ + unsigned t2shift; + + if (via_t1on) { + via_t1c--; + + if ((via_t1c & 0xffff) == 0xffff) { + /* counter just rolled over */ + + if (via_acr & 0x40) { + /* continuous interrupt mode */ + + via_ifr |= 0x40; + int_update (); + via_t1pb7 = 0x80 - via_t1pb7; + + /* reload counter */ + + via_t1c = (via_t1lh << 8) | via_t1ll; + } else { + /* one shot mode */ + + if (via_t1int) { + via_ifr |= 0x40; + int_update (); + via_t1pb7 = 0x80; + via_t1int = 0; + } + } + } + } + + if (via_t2on && (via_acr & 0x20) == 0x00) { + via_t2c--; + + if ((via_t2c & 0xffff) == 0xffff) { + /* one shot mode */ + + if (via_t2int) { + via_ifr |= 0x20; + int_update (); + via_t2int = 0; + } + } + } + + /* shift counter */ + + via_src--; + + if ((via_src & 0xff) == 0xff) { + via_src = via_t2ll; + + if (via_srclk) { + t2shift = 1; + via_srclk = 0; + } else { + t2shift = 0; + via_srclk = 1; + } + } else { + t2shift = 0; + } + + if (via_srb < 8) { + switch (via_acr & 0x1c) { + case 0x00: + /* disabled */ + break; + case 0x04: + /* shift in under control of t2 */ + + if (t2shift) { + /* shifting in 0s since cb2 is always an output */ + + via_sr <<= 1; + via_srb++; + } + + break; + case 0x08: + /* shift in under system clk control */ + + via_sr <<= 1; + via_srb++; + + break; + case 0x0c: + /* shift in under cb1 control */ + break; + case 0x10: + /* shift out under t2 control (free run) */ + + if (t2shift) { + via_cb2s = (via_sr >> 7) & 1; + + via_sr <<= 1; + via_sr |= via_cb2s; + } + + break; + case 0x14: + /* shift out under t2 control */ + + if (t2shift) { + via_cb2s = (via_sr >> 7) & 1; + + via_sr <<= 1; + via_sr |= via_cb2s; + via_srb++; + } + + break; + case 0x18: + /* shift out under system clock control */ + + via_cb2s = (via_sr >> 7) & 1; + + via_sr <<= 1; + via_sr |= via_cb2s; + via_srb++; + + break; + case 0x1c: + /* shift out under cb1 control */ + break; + } + + if (via_srb == 8) { + via_ifr |= 0x04; + int_update (); + } + } +} + +/* perform the second part of the via emulation */ + +static einline void via_sstep1 (void) +{ + if ((via_pcr & 0x0e) == 0x0a) { + /* if ca2 is in pulse mode, then make sure + * it gets restored to '1' after the pulse. + */ + + via_ca2 = 1; + } + + if ((via_pcr & 0xe0) == 0xa0) { + /* if cb2 is in pulse mode, then make sure + * it gets restored to '1' after the pulse. + */ + + via_cb2h = 1; + } +} + + + +static einline void alg_addline (long xx0, long yy0, long xx1, long yy1, unsigned char color) +{ + unsigned long key; + long index; + + unsigned char x0=(xx0*7)/1024, x1=(xx1*7)/1024, y0=((yy0/128-32)*900)/1024, y1=((yy1/128-32)*900)/1024; +// long x0=xx0/128, x1=xx1/128, y0=yy0/128, y1=yy1/128; + + + key = (unsigned long) x0; + key = key * 31 + (unsigned long) y0; + key = key * 31 + (unsigned long) x1; + key = key * 31 + (unsigned long) y1; + key %= VECTOR_HASH; + + /* first check if the line to be drawn is in the current draw list. + * if it is, then it is not added again. + */ + + index = vector_hash[key]; + + if (index >= 0 && index < vector_draw_cnt && + x0 == vectors_draw[index].x0 && + y0 == vectors_draw[index].y0 && + x1 == vectors_draw[index].x1 && + y1 == vectors_draw[index].y1) { + vectors_draw[index].color = color; + + } else { + /* missed on the draw list, now check if the line to be drawn is in + * the erase list ... if it is, "invalidate" it on the erase list. + */ + + if (index >= 0 && index < vector_erse_cnt && + x0 == vectors_erse[index].x0 && + y0 == vectors_erse[index].y0 && + x1 == vectors_erse[index].x1 && + y1 == vectors_erse[index].y1) { + vectors_erse[index].color = VECTREX_COLORS; + } + + vectors_draw[vector_draw_cnt].x0 = x0; + vectors_draw[vector_draw_cnt].y0 = y0; + vectors_draw[vector_draw_cnt].x1 = x1; + vectors_draw[vector_draw_cnt].y1 = y1; + vectors_draw[vector_draw_cnt].color = color; + vector_hash[key] = vector_draw_cnt; + vector_draw_cnt++; + } +} + +/* perform a single cycle worth of analog emulation */ + +static einline void alg_sstep (void) +{ + long sig_dx, sig_dy; + unsigned sig_ramp; + unsigned sig_blank; + + if ((via_acr & 0x10) == 0x10) { + sig_blank = via_cb2s; + } else { + sig_blank = via_cb2h; + } + + if (via_ca2 == 0) { + /* need to force the current point to the 'orgin' so just + * calculate distance to origin and use that as dx,dy. + */ + + sig_dx = ALG_MAX_X / 2 - alg_curr_x; + sig_dy = ALG_MAX_Y / 2 - alg_curr_y; + } else { + if (via_acr & 0x80) { + sig_ramp = via_t1pb7; + } else { + sig_ramp = via_orb & 0x80; + } + + if (sig_ramp == 0) { + sig_dx = alg_dx; + sig_dy = alg_dy; + } else { + sig_dx = 0; + sig_dy = 0; + } + } + + if (alg_vectoring == 0) { + if (sig_blank == 1 && + alg_curr_x >= 0 && alg_curr_x < ALG_MAX_X && + alg_curr_y >= 0 && alg_curr_y < ALG_MAX_Y) { + + /* start a new vector */ + + alg_vectoring = 1; + alg_vector_x0 = alg_curr_x; + alg_vector_y0 = alg_curr_y; + alg_vector_x1 = alg_curr_x; + alg_vector_y1 = alg_curr_y; + alg_vector_dx = sig_dx; + alg_vector_dy = sig_dy; + alg_vector_color = (unsigned char) alg_zsh; + } + } else { + /* already drawing a vector ... check if we need to turn it off */ + + if (sig_blank == 0) { + /* blank just went on, vectoring turns off, and we've got a + * new line. + */ + + alg_vectoring = 0; + + alg_addline (alg_vector_x0, alg_vector_y0, + alg_vector_x1, alg_vector_y1, + alg_vector_color); + } else if (sig_dx != alg_vector_dx || + sig_dy != alg_vector_dy || + (unsigned char) alg_zsh != alg_vector_color) { + + /* the parameters of the vectoring processing has changed. + * so end the current line. + */ + + alg_addline (alg_vector_x0, alg_vector_y0, + alg_vector_x1, alg_vector_y1, + alg_vector_color); + + /* we continue vectoring with a new set of parameters if the + * current point is not out of limits. + */ + + if (alg_curr_x >= 0 && alg_curr_x < ALG_MAX_X && + alg_curr_y >= 0 && alg_curr_y < ALG_MAX_Y) { + alg_vector_x0 = alg_curr_x; + alg_vector_y0 = alg_curr_y; + alg_vector_x1 = alg_curr_x; + alg_vector_y1 = alg_curr_y; + alg_vector_dx = sig_dx; + alg_vector_dy = sig_dy; + alg_vector_color = (unsigned char) alg_zsh; + } else { + alg_vectoring = 0; + } + } + } + + alg_curr_x += sig_dx; + alg_curr_y += sig_dy; + + if (alg_vectoring == 1 && + alg_curr_x >= 0 && alg_curr_x < ALG_MAX_X && + alg_curr_y >= 0 && alg_curr_y < ALG_MAX_Y) { + + /* we're vectoring ... current point is still within limits so + * extend the current vector. + */ + + alg_vector_x1 = alg_curr_x; + alg_vector_y1 = alg_curr_y; + } +} + +void vecx_emu (long cycles) +{ + unsigned c, icycles; + + while (cycles > 0) { + icycles = e6809_sstep (via_ifr & 0x80, 0); + + for (c = 0; c < icycles; c++) { + via_sstep0 (); + alg_sstep (); + via_sstep1 (); + } + + cycles -= (long) icycles; + + fcycles -= (long) icycles; + + if (fcycles < 0) { + vector_t *tmp; + + fcycles += FCYCLES_INIT; + osint_render (); + + /* everything that was drawn during this pass now now enters + * the erase list for the next pass. + */ + + vector_erse_cnt = vector_draw_cnt; + vector_draw_cnt = 0; + + tmp = vectors_erse; + vectors_erse = vectors_draw; + vectors_draw = tmp; + } + } +} diff --git a/MCUME_esp32/espvectrex/main/vecx.h b/MCUME_esp32/espvectrex/main/vecx.h new file mode 100755 index 0000000..046697e --- /dev/null +++ b/MCUME_esp32/espvectrex/main/vecx.h @@ -0,0 +1,60 @@ +#ifndef __VECX_H +#define __VECX_H + +enum { + VECTREX_MHZ = 1500000, /* speed of the vectrex being emulated */ + VECTREX_COLORS = 128, /* number of possible colors ... grayscale */ + + ALG_MAX_X = 33000, + ALG_MAX_Y = 41000 +}; + + +enum { + VECTREX_PDECAY = 30, /* phosphor decay rate */ + + /* number of 6809 cycles before a frame redraw */ + + FCYCLES_INIT = VECTREX_MHZ / VECTREX_PDECAY, + + /* max number of possible vectors that maybe on the screen at one time. + * one only needs VECTREX_MHZ / VECTREX_PDECAY but we need to also store + * deleted vectors in a single table + */ + + VECTOR_CNT = VECTREX_MHZ / VECTREX_PDECAY, + + VECTOR_HASH = 65521 +}; + +typedef struct vector_type { + unsigned char x0, y0; /* start coordinate */ + unsigned char x1, y1; /* end coordinate */ + //long x0, y0; /* start coordinate */ + //long x1, y1; /* end coordinate */ + + /* color [0, VECTREX_COLORS - 1], if color = VECTREX_COLORS, then this is + * an invalid entry and must be ignored. + */ + unsigned char color; +} vector_t; + +extern const unsigned char rom[8192]; +extern unsigned char cart[32768]; + +extern unsigned snd_regs[16]; +extern unsigned alg_jch0; +extern unsigned alg_jch1; +extern unsigned alg_jch2; +extern unsigned alg_jch3; + +extern long vector_draw_cnt; +extern long vector_erse_cnt; +extern vector_t *vectors_draw; +extern vector_t *vectors_erse; + + +void vecx_reset (void); +void vecx_emu (long cycles); + +#endif diff --git a/MCUME_esp32/espvectrex/partitions.csv b/MCUME_esp32/espvectrex/partitions.csv new file mode 100755 index 0000000..79c1f89 --- /dev/null +++ b/MCUME_esp32/espvectrex/partitions.csv @@ -0,0 +1,5 @@ +# Name, Type, SubType, Offset, Size +# Note: if you change the phy_init or app partition offset, make sure to change the offset in Kconfig.projbuild +nvs, data, nvs, 0x9000, 0x6000 +phy_init, data, phy, 0xf000, 0x1000 +factory, app, factory, 0x10000, 2M, diff --git a/MCUME_esp32/espvectrex/sdkconfig b/MCUME_esp32/espvectrex/sdkconfig new file mode 100644 index 0000000..cfcca67 --- /dev/null +++ b/MCUME_esp32/espvectrex/sdkconfig @@ -0,0 +1,721 @@ +# +# Automatically generated file; DO NOT EDIT. +# Espressif IoT Development Framework Configuration +# +CONFIG_IDF_TARGET="esp32" + +# +# SDK tool configuration +# +CONFIG_TOOLPREFIX="xtensa-esp32-elf-" +CONFIG_PYTHON="python" +CONFIG_MAKE_WARN_UNDEFINED_VARIABLES=y + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +CONFIG_APP_EXCLUDE_PROJECT_VER_VAR= +CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR= + +# +# Bootloader config +# +CONFIG_LOG_BOOTLOADER_LEVEL_NONE= +CONFIG_LOG_BOOTLOADER_LEVEL_ERROR= +CONFIG_LOG_BOOTLOADER_LEVEL_WARN= +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG= +CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE= +CONFIG_LOG_BOOTLOADER_LEVEL=3 +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V= +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +CONFIG_BOOTLOADER_FACTORY_RESET= +CONFIG_BOOTLOADER_APP_TEST= +CONFIG_BOOTLOADER_WDT_ENABLE=y +CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE= +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +CONFIG_APP_ROLLBACK_ENABLE= + +# +# Security features +# +CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT= +CONFIG_SECURE_BOOT_ENABLED= +CONFIG_FLASH_ENCRYPTION_ENABLED= + +# +# Serial flasher config +# +CONFIG_ESPTOOLPY_PORT="/dev/cu.SLAB_USBtoUART" +CONFIG_ESPTOOLPY_BAUD_115200B=y +CONFIG_ESPTOOLPY_BAUD_230400B= +CONFIG_ESPTOOLPY_BAUD_921600B= +CONFIG_ESPTOOLPY_BAUD_2MB= +CONFIG_ESPTOOLPY_BAUD_OTHER= +CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 +CONFIG_ESPTOOLPY_BAUD=115200 +CONFIG_ESPTOOLPY_COMPRESSED=y +CONFIG_FLASHMODE_QIO= +CONFIG_FLASHMODE_QOUT= +CONFIG_FLASHMODE_DIO=y +CONFIG_FLASHMODE_DOUT= +CONFIG_ESPTOOLPY_FLASHMODE="dio" +CONFIG_ESPTOOLPY_FLASHFREQ_80M= +CONFIG_ESPTOOLPY_FLASHFREQ_40M=y +CONFIG_ESPTOOLPY_FLASHFREQ_26M= +CONFIG_ESPTOOLPY_FLASHFREQ_20M= +CONFIG_ESPTOOLPY_FLASHFREQ="40m" +CONFIG_ESPTOOLPY_FLASHSIZE_1MB= +CONFIG_ESPTOOLPY_FLASHSIZE_2MB= +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +CONFIG_ESPTOOLPY_FLASHSIZE_8MB= +CONFIG_ESPTOOLPY_FLASHSIZE_16MB= +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" +CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y +CONFIG_ESPTOOLPY_BEFORE_RESET=y +CONFIG_ESPTOOLPY_BEFORE_NORESET= +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +CONFIG_ESPTOOLPY_AFTER_NORESET= +CONFIG_ESPTOOLPY_AFTER="hard_reset" +CONFIG_MONITOR_BAUD_9600B= +CONFIG_MONITOR_BAUD_57600B= +CONFIG_MONITOR_BAUD_115200B=y +CONFIG_MONITOR_BAUD_230400B= +CONFIG_MONITOR_BAUD_921600B= +CONFIG_MONITOR_BAUD_2MB= +CONFIG_MONITOR_BAUD_OTHER= +CONFIG_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_MONITOR_BAUD=115200 + +# +# Partition Table +# +CONFIG_PARTITION_TABLE_SINGLE_APP= +CONFIG_PARTITION_TABLE_TWO_OTA= +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y + +# +# Compiler options +# +CONFIG_OPTIMIZATION_LEVEL_DEBUG= +CONFIG_OPTIMIZATION_LEVEL_RELEASE=y +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +CONFIG_OPTIMIZATION_ASSERTIONS_SILENT= +CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED= +CONFIG_CXX_EXCEPTIONS= +CONFIG_STACK_CHECK_NONE=y +CONFIG_STACK_CHECK_NORM= +CONFIG_STACK_CHECK_STRONG= +CONFIG_STACK_CHECK_ALL= +CONFIG_STACK_CHECK= +CONFIG_WARN_WRITE_STRINGS= +CONFIG_DISABLE_GCC8_WARNINGS= + +# +# Component config +# + +# +# Application Level Tracing +# +CONFIG_ESP32_APPTRACE_DEST_TRAX= +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_ENABLE= +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +CONFIG_AWS_IOT_SDK= + +# +# Bluetooth +# +CONFIG_BT_ENABLED= +CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0 +CONFIG_BT_RESERVE_DRAM=0 + +# +# Driver configurations +# + +# +# ADC configuration +# +CONFIG_ADC_FORCE_XPD_FSM= +CONFIG_ADC2_DISABLE_DAC=y + +# +# SPI configuration +# +CONFIG_SPI_MASTER_IN_IRAM= +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +CONFIG_SPI_SLAVE_IN_IRAM= +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y + +# +# eFuse Bit Manager +# +CONFIG_EFUSE_CUSTOM_TABLE= +CONFIG_EFUSE_VIRTUAL= +CONFIG_EFUSE_CODE_SCHEME_COMPAT_NONE= +CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4=y +CONFIG_EFUSE_CODE_SCHEME_COMPAT_REPEAT= +CONFIG_EFUSE_MAX_BLK_LEN=192 + +# +# ESP32-specific +# +CONFIG_IDF_TARGET_ESP32=y +CONFIG_ESP32_DEFAULT_CPU_FREQ_80= +CONFIG_ESP32_DEFAULT_CPU_FREQ_160= +CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y +CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240 +CONFIG_SPIRAM_SUPPORT=y + +# +# SPI RAM config +# +CONFIG_SPIRAM_BOOT_INIT=y +CONFIG_SPIRAM_IGNORE_NOTFOUND= +CONFIG_SPIRAM_USE_MEMMAP= +CONFIG_SPIRAM_USE_CAPS_ALLOC=y +CONFIG_SPIRAM_USE_MALLOC= +CONFIG_SPIRAM_TYPE_AUTO=y +CONFIG_SPIRAM_TYPE_ESPPSRAM32= +CONFIG_SPIRAM_TYPE_ESPPSRAM64= +CONFIG_SPIRAM_SIZE=-1 +CONFIG_SPIRAM_SPEED_40M=y +CONFIG_SPIRAM_MEMTEST=y +CONFIG_SPIRAM_CACHE_WORKAROUND=y +CONFIG_SPIRAM_BANKSWITCH_ENABLE=y +CONFIG_SPIRAM_BANKSWITCH_RESERVE=8 +CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST= +CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY= +CONFIG_PICO_PSRAM_CS_IO=10 +CONFIG_MEMMAP_TRACEMEM= +CONFIG_MEMMAP_TRACEMEM_TWOBANKS= +CONFIG_ESP32_TRAX= +CONFIG_TRACEMEM_RESERVE_DRAM=0x0 +CONFIG_TWO_UNIVERSAL_MAC_ADDRESS= +CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y +CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4 +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +CONFIG_IPC_TASK_STACK_SIZE=1024 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF= +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR= +CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF= +CONFIG_NEWLIB_STDIN_LINE_ENDING_LF= +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +CONFIG_NEWLIB_NANO_FORMAT= +CONFIG_CONSOLE_UART_DEFAULT=y +CONFIG_CONSOLE_UART_CUSTOM= +CONFIG_CONSOLE_UART_NONE= +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ULP_COPROC_ENABLED= +CONFIG_ULP_COPROC_RESERVE_MEM=0 +CONFIG_ESP32_PANIC_PRINT_HALT= +CONFIG_ESP32_PANIC_PRINT_REBOOT=y +CONFIG_ESP32_PANIC_SILENT_REBOOT= +CONFIG_ESP32_PANIC_GDBSTUB= +CONFIG_ESP32_DEBUG_OCDAWARE=y +CONFIG_ESP32_DEBUG_STUBS_ENABLE=y +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_INT_WDT_CHECK_CPU1=y +CONFIG_TASK_WDT=y +CONFIG_TASK_WDT_PANIC= +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +CONFIG_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_0=y +CONFIG_BROWNOUT_DET_LVL_SEL_1= +CONFIG_BROWNOUT_DET_LVL_SEL_2= +CONFIG_BROWNOUT_DET_LVL_SEL_3= +CONFIG_BROWNOUT_DET_LVL_SEL_4= +CONFIG_BROWNOUT_DET_LVL_SEL_5= +CONFIG_BROWNOUT_DET_LVL_SEL_6= +CONFIG_BROWNOUT_DET_LVL_SEL_7= +CONFIG_BROWNOUT_DET_LVL=0 +CONFIG_REDUCE_PHY_TX_POWER=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC= +CONFIG_ESP32_TIME_SYSCALL_USE_FRC1= +CONFIG_ESP32_TIME_SYSCALL_USE_NONE= +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y +CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL= +CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC= +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256= +CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP32_XTAL_FREQ_40=y +CONFIG_ESP32_XTAL_FREQ_26= +CONFIG_ESP32_XTAL_FREQ_AUTO= +CONFIG_ESP32_XTAL_FREQ=40 +CONFIG_DISABLE_BASIC_ROM_CONSOLE= +CONFIG_NO_BLOBS= +CONFIG_ESP_TIMER_PROFILING= +CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS= +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y + +# +# Wi-Fi +# +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER= +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16 +CONFIG_ESP32_WIFI_CSI_ENABLED= +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1= +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP32_WIFI_DEBUG_LOG_ENABLE= +CONFIG_ESP32_WIFI_IRAM_OPT=y + +# +# PHY +# +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION= +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 + +# +# Power Management +# +CONFIG_PM_ENABLE= + +# +# ADC-Calibration +# +CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y +CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y +CONFIG_ADC_CAL_LUT_ENABLE=y + +# +# Event Loop Library +# +CONFIG_EVENT_LOOP_PROFILING= + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS= + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y + +# +# ESP HTTPS OTA +# +CONFIG_OTA_ALLOW_HTTP= + +# +# Core dump +# +CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH= +CONFIG_ESP32_ENABLE_COREDUMP_TO_UART= +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +CONFIG_ESP32_ENABLE_COREDUMP= + +# +# Ethernet +# +CONFIG_DMA_RX_BUF_NUM=10 +CONFIG_DMA_TX_BUF_NUM=10 +CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE=y +CONFIG_EMAC_CHECK_LINK_PERIOD_MS=2000 +CONFIG_EMAC_TASK_PRIORITY=20 +CONFIG_EMAC_TASK_STACK_SIZE=3072 + +# +# FAT Filesystem support +# +CONFIG_FATFS_CODEPAGE_DYNAMIC= +CONFIG_FATFS_CODEPAGE_437=y +CONFIG_FATFS_CODEPAGE_720= +CONFIG_FATFS_CODEPAGE_737= +CONFIG_FATFS_CODEPAGE_771= +CONFIG_FATFS_CODEPAGE_775= +CONFIG_FATFS_CODEPAGE_850= +CONFIG_FATFS_CODEPAGE_852= +CONFIG_FATFS_CODEPAGE_855= +CONFIG_FATFS_CODEPAGE_857= +CONFIG_FATFS_CODEPAGE_860= +CONFIG_FATFS_CODEPAGE_861= +CONFIG_FATFS_CODEPAGE_862= +CONFIG_FATFS_CODEPAGE_863= +CONFIG_FATFS_CODEPAGE_864= +CONFIG_FATFS_CODEPAGE_865= +CONFIG_FATFS_CODEPAGE_866= +CONFIG_FATFS_CODEPAGE_869= +CONFIG_FATFS_CODEPAGE_932= +CONFIG_FATFS_CODEPAGE_936= +CONFIG_FATFS_CODEPAGE_949= +CONFIG_FATFS_CODEPAGE_950= +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_LFN_NONE= +CONFIG_FATFS_LFN_HEAP= +CONFIG_FATFS_LFN_STACK=y +CONFIG_FATFS_MAX_LFN=255 +CONFIG_FATFS_API_ENCODING_ANSI_OEM=y +CONFIG_FATFS_API_ENCODING_UTF_16= +CONFIG_FATFS_API_ENCODING_UTF_8= +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y + +# +# Modbus configuration +# +CONFIG_MB_QUEUE_LENGTH=20 +CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048 +CONFIG_MB_SERIAL_BUF_SIZE=256 +CONFIG_MB_SERIAL_TASK_PRIO=10 +CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT= +CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_MB_CONTROLLER_STACK_SIZE=4096 +CONFIG_MB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_MB_TIMER_PORT_ENABLED=y +CONFIG_MB_TIMER_GROUP=0 +CONFIG_MB_TIMER_INDEX=0 + +# +# FreeRTOS +# +CONFIG_FREERTOS_UNICORE= +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_CORETIMER_0=y +CONFIG_FREERTOS_CORETIMER_1= +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE= +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL= +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK= +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y +CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE= +CONFIG_FREERTOS_ASSERT_DISABLE= +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +CONFIG_FREERTOS_LEGACY_HOOKS= +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +CONFIG_SUPPORT_STATIC_ALLOCATION=y +CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK= +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_USE_TRACE_FACILITY= +CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS= +CONFIG_FREERTOS_DEBUG_INTERNALS= + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +CONFIG_HEAP_POISONING_LIGHT= +CONFIG_HEAP_POISONING_COMPREHENSIVE= +CONFIG_HEAP_TRACING= + +# +# libsodium +# +CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y + +# +# Log output +# +CONFIG_LOG_DEFAULT_LEVEL_NONE= +CONFIG_LOG_DEFAULT_LEVEL_ERROR= +CONFIG_LOG_DEFAULT_LEVEL_WARN= +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +CONFIG_LOG_DEFAULT_LEVEL_DEBUG= +CONFIG_LOG_DEFAULT_LEVEL_VERBOSE= +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_COLORS=y + +# +# LWIP +# +CONFIG_L2_TO_L3_COPY= +CONFIG_LWIP_IRAM_OPTIMIZATION= +CONFIG_LWIP_MAX_SOCKETS=10 +CONFIG_USE_ONLY_LWIP_SELECT= +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +CONFIG_LWIP_SO_RCVBUF= +CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 +CONFIG_LWIP_IP_FRAG= +CONFIG_LWIP_IP_REASSEMBLY= +CONFIG_LWIP_STATS= +CONFIG_LWIP_ETHARP_TRUST_IP_MAC= +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +CONFIG_LWIP_DHCP_RESTORE_LAST_IP= + +# +# DHCP server +# +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +CONFIG_LWIP_AUTOIP= +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=6 +CONFIG_TCP_MSS=1436 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5744 +CONFIG_TCP_WND_DEFAULT=5744 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES= +CONFIG_TCP_OVERSIZE_MSS=y +CONFIG_TCP_OVERSIZE_QUARTER_MSS= +CONFIG_TCP_OVERSIZE_DISABLE= + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +CONFIG_TCPIP_TASK_AFFINITY_CPU0= +CONFIG_TCPIP_TASK_AFFINITY_CPU1= +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +CONFIG_PPP_SUPPORT= + +# +# ICMP +# +CONFIG_LWIP_MULTICAST_PING= +CONFIG_LWIP_BROADCAST_PING= + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC= +CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC= +CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC= +CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384 +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN= +CONFIG_MBEDTLS_DEBUG= +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_HARDWARE_MPI= +CONFIG_MBEDTLS_HARDWARE_SHA= +CONFIG_MBEDTLS_HAVE_TIME=y +CONFIG_MBEDTLS_HAVE_TIME_DATE= +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +CONFIG_MBEDTLS_TLS_SERVER_ONLY= +CONFIG_MBEDTLS_TLS_CLIENT_ONLY= +CONFIG_MBEDTLS_TLS_DISABLED= +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +CONFIG_MBEDTLS_PSK_MODES= +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +CONFIG_MBEDTLS_SSL_PROTO_SSL3= +CONFIG_MBEDTLS_SSL_PROTO_TLS1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +CONFIG_MBEDTLS_SSL_PROTO_DTLS= +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +CONFIG_MBEDTLS_CAMELLIA_C= +CONFIG_MBEDTLS_DES_C= +CONFIG_MBEDTLS_RC4_DISABLED=y +CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT= +CONFIG_MBEDTLS_RC4_ENABLED= +CONFIG_MBEDTLS_BLOWFISH_C= +CONFIG_MBEDTLS_XTEA_C= +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +CONFIG_MBEDTLS_RIPEMD160_C= + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y + +# +# mDNS +# +CONFIG_MDNS_MAX_SERVICES=10 + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +CONFIG_MQTT_USE_CUSTOM_CONFIG= +CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED= +CONFIG_MQTT_CUSTOM_OUTBOX= + +# +# NVS +# + +# +# OpenSSL +# +CONFIG_OPENSSL_DEBUG= +CONFIG_OPENSSL_ASSERT_DO_NOTHING=y +CONFIG_OPENSSL_ASSERT_EXIT= + +# +# PThreads +# +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0= +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1= +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" + +# +# SPI Flash driver +# +CONFIG_SPI_FLASH_VERIFY_WRITE= +CONFIG_SPI_FLASH_ENABLE_COUNTERS= +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +CONFIG_SPIFFS_CACHE_STATS= +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +CONFIG_SPIFFS_GC_STATS= +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +CONFIG_SPIFFS_DBG= +CONFIG_SPIFFS_API_DBG= +CONFIG_SPIFFS_GC_DBG= +CONFIG_SPIFFS_CACHE_DBG= +CONFIG_SPIFFS_CHECK_DBG= +CONFIG_SPIFFS_TEST_VISUALISATION= + +# +# TCP/IP Adapter +# +CONFIG_IP_LOST_TIMER_INTERVAL=120 +CONFIG_TCPIP_LWIP=y + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +CONFIG_UNITY_ENABLE_COLOR= +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +CONFIG_UNITY_ENABLE_FIXTURE= + +# +# Virtual file system +# +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y + +# +# Wear Levelling +# +CONFIG_WL_SECTOR_SIZE_512= +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 diff --git a/MCUME_esp32/espvectrex/sdkconfig.old b/MCUME_esp32/espvectrex/sdkconfig.old new file mode 100644 index 0000000..e6b5dbe --- /dev/null +++ b/MCUME_esp32/espvectrex/sdkconfig.old @@ -0,0 +1,705 @@ +# +# Automatically generated file; DO NOT EDIT. +# Espressif IoT Development Framework Configuration +# +CONFIG_IDF_TARGET="esp32" + +# +# SDK tool configuration +# +CONFIG_TOOLPREFIX="xtensa-esp32-elf-" +CONFIG_PYTHON="python" +CONFIG_MAKE_WARN_UNDEFINED_VARIABLES=y + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y + +# +# Bootloader config +# +CONFIG_LOG_BOOTLOADER_LEVEL_NONE= +CONFIG_LOG_BOOTLOADER_LEVEL_ERROR= +CONFIG_LOG_BOOTLOADER_LEVEL_WARN= +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG= +CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE= +CONFIG_LOG_BOOTLOADER_LEVEL=3 +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V= +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +CONFIG_BOOTLOADER_FACTORY_RESET= +CONFIG_BOOTLOADER_APP_TEST= +CONFIG_BOOTLOADER_WDT_ENABLE=y +CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE= +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 + +# +# Security features +# +CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT= +CONFIG_SECURE_BOOT_ENABLED= +CONFIG_FLASH_ENCRYPTION_ENABLED= + +# +# Serial flasher config +# +CONFIG_ESPTOOLPY_PORT="/dev/cu.SLAB_USBtoUART" +CONFIG_ESPTOOLPY_BAUD_115200B=y +CONFIG_ESPTOOLPY_BAUD_230400B= +CONFIG_ESPTOOLPY_BAUD_921600B= +CONFIG_ESPTOOLPY_BAUD_2MB= +CONFIG_ESPTOOLPY_BAUD_OTHER= +CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 +CONFIG_ESPTOOLPY_BAUD=115200 +CONFIG_ESPTOOLPY_COMPRESSED=y +CONFIG_FLASHMODE_QIO= +CONFIG_FLASHMODE_QOUT= +CONFIG_FLASHMODE_DIO=y +CONFIG_FLASHMODE_DOUT= +CONFIG_ESPTOOLPY_FLASHMODE="dio" +CONFIG_ESPTOOLPY_FLASHFREQ_80M= +CONFIG_ESPTOOLPY_FLASHFREQ_40M=y +CONFIG_ESPTOOLPY_FLASHFREQ_26M= +CONFIG_ESPTOOLPY_FLASHFREQ_20M= +CONFIG_ESPTOOLPY_FLASHFREQ="40m" +CONFIG_ESPTOOLPY_FLASHSIZE_1MB= +CONFIG_ESPTOOLPY_FLASHSIZE_2MB= +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +CONFIG_ESPTOOLPY_FLASHSIZE_8MB= +CONFIG_ESPTOOLPY_FLASHSIZE_16MB= +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" +CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y +CONFIG_ESPTOOLPY_BEFORE_RESET=y +CONFIG_ESPTOOLPY_BEFORE_NORESET= +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +CONFIG_ESPTOOLPY_AFTER_NORESET= +CONFIG_ESPTOOLPY_AFTER="hard_reset" +CONFIG_MONITOR_BAUD_9600B= +CONFIG_MONITOR_BAUD_57600B= +CONFIG_MONITOR_BAUD_115200B=y +CONFIG_MONITOR_BAUD_230400B= +CONFIG_MONITOR_BAUD_921600B= +CONFIG_MONITOR_BAUD_2MB= +CONFIG_MONITOR_BAUD_OTHER= +CONFIG_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_MONITOR_BAUD=115200 + +# +# Partition Table +# +CONFIG_PARTITION_TABLE_SINGLE_APP= +CONFIG_PARTITION_TABLE_TWO_OTA= +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y + +# +# Compiler options +# +CONFIG_OPTIMIZATION_LEVEL_DEBUG= +CONFIG_OPTIMIZATION_LEVEL_RELEASE=y +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +CONFIG_OPTIMIZATION_ASSERTIONS_SILENT= +CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED= +CONFIG_CXX_EXCEPTIONS= +CONFIG_STACK_CHECK_NONE=y +CONFIG_STACK_CHECK_NORM= +CONFIG_STACK_CHECK_STRONG= +CONFIG_STACK_CHECK_ALL= +CONFIG_STACK_CHECK= +CONFIG_WARN_WRITE_STRINGS= +CONFIG_DISABLE_GCC8_WARNINGS= + +# +# Component config +# + +# +# Application Level Tracing +# +CONFIG_ESP32_APPTRACE_DEST_TRAX= +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_ENABLE= +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +CONFIG_AWS_IOT_SDK= + +# +# Bluetooth +# +CONFIG_BT_ENABLED= +CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0 +CONFIG_BT_RESERVE_DRAM=0 + +# +# Driver configurations +# + +# +# ADC configuration +# +CONFIG_ADC_FORCE_XPD_FSM= +CONFIG_ADC2_DISABLE_DAC=y + +# +# SPI configuration +# +CONFIG_SPI_MASTER_IN_IRAM= +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +CONFIG_SPI_SLAVE_IN_IRAM= +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y + +# +# ESP32-specific +# +CONFIG_IDF_TARGET_ESP32=y +CONFIG_ESP32_DEFAULT_CPU_FREQ_80= +CONFIG_ESP32_DEFAULT_CPU_FREQ_160= +CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y +CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240 +CONFIG_SPIRAM_SUPPORT=y + +# +# SPI RAM config +# +CONFIG_SPIRAM_BOOT_INIT=y +CONFIG_SPIRAM_IGNORE_NOTFOUND= +CONFIG_SPIRAM_USE_MEMMAP= +CONFIG_SPIRAM_USE_CAPS_ALLOC=y +CONFIG_SPIRAM_USE_MALLOC= +CONFIG_SPIRAM_TYPE_AUTO=y +CONFIG_SPIRAM_TYPE_ESPPSRAM32= +CONFIG_SPIRAM_TYPE_ESPPSRAM64= +CONFIG_SPIRAM_SIZE=-1 +CONFIG_SPIRAM_SPEED_40M=y +CONFIG_SPIRAM_MEMTEST=y +CONFIG_SPIRAM_CACHE_WORKAROUND=y +CONFIG_SPIRAM_BANKSWITCH_ENABLE=y +CONFIG_SPIRAM_BANKSWITCH_RESERVE=8 +CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST= +CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY= +CONFIG_MEMMAP_TRACEMEM= +CONFIG_MEMMAP_TRACEMEM_TWOBANKS= +CONFIG_ESP32_TRAX= +CONFIG_TRACEMEM_RESERVE_DRAM=0x0 + +# +# Core dump +# +CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH= +CONFIG_ESP32_ENABLE_COREDUMP_TO_UART= +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +CONFIG_ESP32_ENABLE_COREDUMP= +CONFIG_TWO_UNIVERSAL_MAC_ADDRESS= +CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y +CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4 +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +CONFIG_IPC_TASK_STACK_SIZE=1024 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF= +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR= +CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF= +CONFIG_NEWLIB_STDIN_LINE_ENDING_LF= +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +CONFIG_NEWLIB_NANO_FORMAT= +CONFIG_CONSOLE_UART_DEFAULT=y +CONFIG_CONSOLE_UART_CUSTOM= +CONFIG_CONSOLE_UART_NONE= +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ULP_COPROC_ENABLED= +CONFIG_ULP_COPROC_RESERVE_MEM=0 +CONFIG_ESP32_PANIC_PRINT_HALT= +CONFIG_ESP32_PANIC_PRINT_REBOOT=y +CONFIG_ESP32_PANIC_SILENT_REBOOT= +CONFIG_ESP32_PANIC_GDBSTUB= +CONFIG_ESP32_DEBUG_OCDAWARE=y +CONFIG_ESP32_DEBUG_STUBS_ENABLE=y +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_INT_WDT_CHECK_CPU1=y +CONFIG_TASK_WDT=y +CONFIG_TASK_WDT_PANIC= +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +CONFIG_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_0=y +CONFIG_BROWNOUT_DET_LVL_SEL_1= +CONFIG_BROWNOUT_DET_LVL_SEL_2= +CONFIG_BROWNOUT_DET_LVL_SEL_3= +CONFIG_BROWNOUT_DET_LVL_SEL_4= +CONFIG_BROWNOUT_DET_LVL_SEL_5= +CONFIG_BROWNOUT_DET_LVL_SEL_6= +CONFIG_BROWNOUT_DET_LVL_SEL_7= +CONFIG_BROWNOUT_DET_LVL=0 +CONFIG_REDUCE_PHY_TX_POWER=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC= +CONFIG_ESP32_TIME_SYSCALL_USE_FRC1= +CONFIG_ESP32_TIME_SYSCALL_USE_NONE= +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y +CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL= +CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC= +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256= +CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP32_XTAL_FREQ_40=y +CONFIG_ESP32_XTAL_FREQ_26= +CONFIG_ESP32_XTAL_FREQ_AUTO= +CONFIG_ESP32_XTAL_FREQ=40 +CONFIG_DISABLE_BASIC_ROM_CONSOLE= +CONFIG_NO_BLOBS= +CONFIG_ESP_TIMER_PROFILING= +CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS= +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y + +# +# Wi-Fi +# +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER= +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16 +CONFIG_ESP32_WIFI_CSI_ENABLED= +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1= +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_DEBUG_LOG_ENABLE= + +# +# PHY +# +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION= +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 + +# +# Power Management +# +CONFIG_PM_ENABLE= + +# +# ADC-Calibration +# +CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y +CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y +CONFIG_ADC_CAL_LUT_ENABLE=y + +# +# Event Loop Library +# +CONFIG_EVENT_LOOP_PROFILING= + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS= + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 + +# +# Ethernet +# +CONFIG_DMA_RX_BUF_NUM=10 +CONFIG_DMA_TX_BUF_NUM=10 +CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE=y +CONFIG_EMAC_CHECK_LINK_PERIOD_MS=2000 +CONFIG_EMAC_TASK_PRIORITY=20 +CONFIG_EMAC_TASK_STACK_SIZE=3072 + +# +# FAT Filesystem support +# +CONFIG_FATFS_CODEPAGE_DYNAMIC= +CONFIG_FATFS_CODEPAGE_437=y +CONFIG_FATFS_CODEPAGE_720= +CONFIG_FATFS_CODEPAGE_737= +CONFIG_FATFS_CODEPAGE_771= +CONFIG_FATFS_CODEPAGE_775= +CONFIG_FATFS_CODEPAGE_850= +CONFIG_FATFS_CODEPAGE_852= +CONFIG_FATFS_CODEPAGE_855= +CONFIG_FATFS_CODEPAGE_857= +CONFIG_FATFS_CODEPAGE_860= +CONFIG_FATFS_CODEPAGE_861= +CONFIG_FATFS_CODEPAGE_862= +CONFIG_FATFS_CODEPAGE_863= +CONFIG_FATFS_CODEPAGE_864= +CONFIG_FATFS_CODEPAGE_865= +CONFIG_FATFS_CODEPAGE_866= +CONFIG_FATFS_CODEPAGE_869= +CONFIG_FATFS_CODEPAGE_932= +CONFIG_FATFS_CODEPAGE_936= +CONFIG_FATFS_CODEPAGE_949= +CONFIG_FATFS_CODEPAGE_950= +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_LFN_NONE= +CONFIG_FATFS_LFN_HEAP= +CONFIG_FATFS_LFN_STACK=y +CONFIG_FATFS_MAX_LFN=255 +CONFIG_FATFS_API_ENCODING_ANSI_OEM=y +CONFIG_FATFS_API_ENCODING_UTF_16= +CONFIG_FATFS_API_ENCODING_UTF_8= +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y + +# +# Modbus configuration +# +CONFIG_MB_UART_RXD=22 +CONFIG_MB_UART_TXD=23 +CONFIG_MB_UART_RTS=18 +CONFIG_MB_QUEUE_LENGTH=20 +CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048 +CONFIG_MB_SERIAL_BUF_SIZE=256 +CONFIG_MB_SERIAL_TASK_PRIO=10 +CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT= +CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_MB_CONTROLLER_STACK_SIZE=4096 +CONFIG_MB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_MB_TIMER_PORT_ENABLED=y +CONFIG_MB_TIMER_GROUP=0 +CONFIG_MB_TIMER_INDEX=0 + +# +# FreeRTOS +# +CONFIG_FREERTOS_UNICORE= +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_CORETIMER_0=y +CONFIG_FREERTOS_CORETIMER_1= +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE= +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL= +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK= +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y +CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE= +CONFIG_FREERTOS_ASSERT_DISABLE= +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +CONFIG_FREERTOS_LEGACY_HOOKS= +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +CONFIG_SUPPORT_STATIC_ALLOCATION=y +CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK= +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_USE_TRACE_FACILITY= +CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS= +CONFIG_FREERTOS_DEBUG_INTERNALS= + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +CONFIG_HEAP_POISONING_LIGHT= +CONFIG_HEAP_POISONING_COMPREHENSIVE= +CONFIG_HEAP_TRACING= + +# +# libsodium +# +CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y + +# +# Log output +# +CONFIG_LOG_DEFAULT_LEVEL_NONE= +CONFIG_LOG_DEFAULT_LEVEL_ERROR= +CONFIG_LOG_DEFAULT_LEVEL_WARN= +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +CONFIG_LOG_DEFAULT_LEVEL_DEBUG= +CONFIG_LOG_DEFAULT_LEVEL_VERBOSE= +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_COLORS=y + +# +# LWIP +# +CONFIG_L2_TO_L3_COPY= +CONFIG_LWIP_IRAM_OPTIMIZATION= +CONFIG_LWIP_MAX_SOCKETS=10 +CONFIG_USE_ONLY_LWIP_SELECT= +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +CONFIG_LWIP_SO_RCVBUF= +CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 +CONFIG_LWIP_IP_FRAG= +CONFIG_LWIP_IP_REASSEMBLY= +CONFIG_LWIP_STATS= +CONFIG_LWIP_ETHARP_TRUST_IP_MAC= +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +CONFIG_LWIP_DHCP_RESTORE_LAST_IP= + +# +# DHCP server +# +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +CONFIG_LWIP_AUTOIP= +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=6 +CONFIG_TCP_MSS=1436 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5744 +CONFIG_TCP_WND_DEFAULT=5744 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES= +CONFIG_TCP_OVERSIZE_MSS=y +CONFIG_TCP_OVERSIZE_QUARTER_MSS= +CONFIG_TCP_OVERSIZE_DISABLE= + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +CONFIG_TCPIP_TASK_AFFINITY_CPU0= +CONFIG_TCPIP_TASK_AFFINITY_CPU1= +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +CONFIG_PPP_SUPPORT= + +# +# ICMP +# +CONFIG_LWIP_MULTICAST_PING= +CONFIG_LWIP_BROADCAST_PING= + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC= +CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC= +CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC= +CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384 +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN= +CONFIG_MBEDTLS_DEBUG= +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_HARDWARE_MPI= +CONFIG_MBEDTLS_HARDWARE_SHA= +CONFIG_MBEDTLS_HAVE_TIME=y +CONFIG_MBEDTLS_HAVE_TIME_DATE= +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +CONFIG_MBEDTLS_TLS_SERVER_ONLY= +CONFIG_MBEDTLS_TLS_CLIENT_ONLY= +CONFIG_MBEDTLS_TLS_DISABLED= +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +CONFIG_MBEDTLS_PSK_MODES= +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +CONFIG_MBEDTLS_SSL_PROTO_SSL3= +CONFIG_MBEDTLS_SSL_PROTO_TLS1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +CONFIG_MBEDTLS_SSL_PROTO_DTLS= +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +CONFIG_MBEDTLS_CAMELLIA_C= +CONFIG_MBEDTLS_DES_C= +CONFIG_MBEDTLS_RC4_DISABLED=y +CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT= +CONFIG_MBEDTLS_RC4_ENABLED= +CONFIG_MBEDTLS_BLOWFISH_C= +CONFIG_MBEDTLS_XTEA_C= +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +CONFIG_MBEDTLS_RIPEMD160_C= + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y + +# +# mDNS +# +CONFIG_MDNS_MAX_SERVICES=10 + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +CONFIG_MQTT_USE_CUSTOM_CONFIG= +CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED= +CONFIG_MQTT_CUSTOM_OUTBOX= + +# +# NVS +# + +# +# OpenSSL +# +CONFIG_OPENSSL_DEBUG= +CONFIG_OPENSSL_ASSERT_DO_NOTHING=y +CONFIG_OPENSSL_ASSERT_EXIT= + +# +# PThreads +# +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0= +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1= +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" + +# +# SPI Flash driver +# +CONFIG_SPI_FLASH_VERIFY_WRITE= +CONFIG_SPI_FLASH_ENABLE_COUNTERS= +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS= +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED= + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +CONFIG_SPIFFS_CACHE_STATS= +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +CONFIG_SPIFFS_GC_STATS= +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +CONFIG_SPIFFS_DBG= +CONFIG_SPIFFS_API_DBG= +CONFIG_SPIFFS_GC_DBG= +CONFIG_SPIFFS_CACHE_DBG= +CONFIG_SPIFFS_CHECK_DBG= +CONFIG_SPIFFS_TEST_VISUALISATION= + +# +# TCP/IP Adapter +# +CONFIG_IP_LOST_TIMER_INTERVAL=120 +CONFIG_TCPIP_LWIP=y + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +CONFIG_UNITY_ENABLE_COLOR= +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +CONFIG_UNITY_ENABLE_FIXTURE= + +# +# Virtual file system +# +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y + +# +# Wear Levelling +# +CONFIG_WL_SECTOR_SIZE_512= +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096