follow mame choice again
m68kmmu.h uses functions from m68kfpu.c which are static, so m68kfpu.c can't be compiled alone anymore if we want to keep some basic compatibility... I know, it's not super clean, but it's not my choice...! Also pmmu_translate_addr can't be inline anymore because of this (there are quite a few functions from m68kcpu.h using it, and it can be included only in m68kcpu.c !)
This commit is contained in:
Emmanuel Anne
parent
530f644bd3
commit
7efac187bd
8 changed files with 164 additions and 63 deletions
1
.gitignore
vendored
1
.gitignore
vendored
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@ -24,3 +24,4 @@ Thumbs.db
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m68kmake
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m68kops.?
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sim
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tags
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2
Makefile
2
Makefile
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@ -1,7 +1,7 @@
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# Just a basic makefile to quickly test that everyting is working, it just
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# compiles the .o and the generator
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MUSASHIFILES = m68kcpu.c m68kdasm.c m68kfpu.c
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MUSASHIFILES = m68kcpu.c m68kdasm.c
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MUSASHIGENCFILES = m68kops.c
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MUSASHIGENHFILES = m68kops.h
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MUSASHIGENERATOR = m68kmake
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@ -4,7 +4,7 @@ OSD_DOS = osd_dos.c
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OSDFILES = osd_linux.c # $(OSD_DOS)
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MAINFILES = sim.c
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MUSASHIFILES = m68kcpu.c m68kdasm.c m68kfpu.c
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MUSASHIFILES = m68kcpu.c m68kdasm.c
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MUSASHIGENCFILES = m68kops.c
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MUSASHIGENHFILES = m68kops.h
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MUSASHIGENERATOR = m68kmake
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1
example/m68kmmu.h
Symbolic link
1
example/m68kmmu.h
Symbolic link
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@ -0,0 +1 @@
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../m68kmmu.h
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@ -48,6 +48,9 @@ extern void m68ki_build_opcode_table(void);
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#include "m68kops.h"
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#include "m68kcpu.h"
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#include "m68kfpu.c"
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#include "m68kmmu.h" // uses some functions from m68kfpu.c which are static !
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/* ======================================================================== */
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/* ================================= DATA ================================= */
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/* ======================================================================== */
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@ -1020,7 +1020,7 @@ char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type);
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/* ---------------------------- Read Immediate ---------------------------- */
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#include "m68kmmu.h"
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extern uint pmmu_translate_addr(uint addr_in);
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/* Handles all immediate reads, does address error check, function code setting,
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* and prefetching if they are enabled in m68kconf.h
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@ -1204,7 +1204,6 @@ static inline void m68ki_write_32_pd_fc(uint address, uint fc, uint value)
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}
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#endif
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/* --------------------- Effective Address Calculation -------------------- */
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/* The program counter relative addressing modes cause operands to be
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@ -1482,8 +1481,6 @@ static inline void m68ki_branch_32(uint offset)
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m68ki_pc_changed(REG_PC);
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}
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/* ---------------------------- Status Register --------------------------- */
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/* Set the S flag and change the active stack pointer.
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13
m68kfpu.c
13
m68kfpu.c
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@ -1,5 +1,16 @@
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#include <math.h>
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#include "m68kcpu.h"
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#include <stdio.h>
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#include <stdarg.h>
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extern void exit(int);
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static void fatalerror(char *format, ...) {
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va_list ap;
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va_start(ap,format);
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fprintf(stderr,format,ap);
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va_end(ap);
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exit(1);
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}
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#define FPCC_N 0x08000000
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#define FPCC_Z 0x04000000
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200
m68kmmu.h
200
m68kmmu.h
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@ -6,24 +6,11 @@
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Copyright Nicola Salmoria and the MAME Team.
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Visit http://mamedev.org for licensing and usage restrictions.
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*/
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#include <stdio.h>
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#include <stdarg.h>
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extern void exit(int);
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// TODO: Remove this and replace with a non-fatal signaling mechanism
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inline void fatalerror(char *format, ...) {
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va_list ap;
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va_start(ap,format);
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fprintf(stderr,format,ap);
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va_end(ap);
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exit(1);
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}
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/*
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pmmu_translate_addr: perform 68851/68030-style PMMU address translation
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*/
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inline uint pmmu_translate_addr(uint addr_in)
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uint pmmu_translate_addr(uint addr_in)
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{
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uint32 addr_out, tbl_entry = 0, tbl_entry2, tamode = 0, tbmode = 0, tcmode = 0;
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uint root_aptr, root_limit, tofs, is, abits, bbits, cbits;
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@ -186,48 +173,149 @@ inline uint pmmu_translate_addr(uint addr_in)
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/*
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maincpu at 40804366: called unimplemented instruction f000 (cpgen)
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PMMU: tcr 80f05570 limit 7fff0003 aptr 043ffcc0 is 0
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PMMU: reading table A entries at 043ffce0
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PMMU: addr 4080438a entry 00000000 entry2 7ffffc18 mode 0 aofs 20
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680x0 PMMU: Unhandled Table A mode 0
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enable, PS = f
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tblA @ 043ffcc0:
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043ffcc0 0001fc0a 043ffcb0 => 00000019 04000019
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043ffcc8 7ffffc18 00000000
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043ffcd0 7ffffc18 00000000
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043ffcd8 7ffffc18 00000000
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043ffce0 7ffffc18 00000000
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043ffce8 7ffffc18 00000000
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043ffcf0 7ffffc18 00000000
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043ffcf8 7ffffc18 00000000
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043ffd00 7ffffc19 40000000
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043ffd08 7ffffc19 48000000
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043ffd10 7ffffc59 50000000
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043ffd18 7ffffc59 58000000
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043ffd20 7ffffc59 60000000
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043ffd28 7ffffc59 68000000
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043ffd30 7ffffc59 70000000
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043ffd38 7ffffc59 78000000
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043ffd40 7ffffc59 80000000
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043ffd48 7ffffc59 88000000
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043ffd50 7ffffc59 90000000
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043ffd58 7ffffc59 98000000
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043ffd60 7ffffc59 a0000000
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043ffd68 7ffffc59 a8000000
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043ffd70 7ffffc59 b0000000
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043ffd78 7ffffc59 b8000000
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043ffd80 7ffffc59 c0000000
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043ffd88 7ffffc59 c8000000
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043ffd90 7ffffc59 d0000000
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043ffd98 7ffffc59 d8000000
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043ffda0 7ffffc59 e0000000
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043ffda8 7ffffc59 e8000000
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043ffdb0 7ffffc59 f0000000
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043ffdb8 7ffffc59 f8000000
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m68881_mmu_ops: COP 0 MMU opcode handling
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*/
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void m68881_mmu_ops()
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{
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uint16 modes;
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uint32 ea = m68ki_cpu.ir & 0x3f;
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uint64 temp64;
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// catch the 2 "weird" encodings up front (PBcc)
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if ((m68ki_cpu.ir & 0xffc0) == 0xf0c0)
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{
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fprintf(stderr,"680x0: unhandled PBcc\n");
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return;
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}
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else if ((m68ki_cpu.ir & 0xffc0) == 0xf080)
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{
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fprintf(stderr,"680x0: unhandled PBcc\n");
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return;
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}
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else // the rest are 1111000xxxXXXXXX where xxx is the instruction family
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{
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switch ((m68ki_cpu.ir>>9) & 0x7)
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{
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case 0:
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modes = OPER_I_16();
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if ((modes & 0xfde0) == 0x2000) // PLOAD
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{
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fprintf(stderr,"680x0: unhandled PLOAD\n");
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return;
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}
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else if ((modes & 0xe200) == 0x2000) // PFLUSH
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{
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fprintf(stderr,"680x0: unhandled PFLUSH PC=%x\n", REG_PC);
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return;
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}
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else if (modes == 0xa000) // PFLUSHR
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{
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fprintf(stderr,"680x0: unhandled PFLUSHR\n");
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return;
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}
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else if (modes == 0x2800) // PVALID (FORMAT 1)
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{
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fprintf(stderr,"680x0: unhandled PVALID1\n");
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return;
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}
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else if ((modes & 0xfff8) == 0x2c00) // PVALID (FORMAT 2)
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{
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fprintf(stderr,"680x0: unhandled PVALID2\n");
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return;
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}
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else if ((modes & 0xe000) == 0x8000) // PTEST
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{
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fprintf(stderr,"680x0: unhandled PTEST\n");
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return;
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}
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else
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{
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switch ((modes>>13) & 0x7)
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{
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case 0: // MC68030/040 form with FD bit
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case 2: // MC68881 form, FD never set
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if (modes & 0x200)
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{
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switch ((modes>>10) & 7)
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{
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case 0: // translation control register
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WRITE_EA_32(ea, m68ki_cpu.mmu_tc);
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break;
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case 2: // supervisor root pointer
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WRITE_EA_64(ea, (uint64)m68ki_cpu.mmu_srp_limit<<32 | (uint64)m68ki_cpu.mmu_srp_aptr);
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break;
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case 3: // CPU root pointer
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WRITE_EA_64(ea, (uint64)m68ki_cpu.mmu_crp_limit<<32 | (uint64)m68ki_cpu.mmu_crp_aptr);
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break;
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default:
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fprintf(stderr,"680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, REG_PC);
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break;
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}
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}
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else
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{
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switch ((modes>>10) & 7)
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{
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case 0: // translation control register
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m68ki_cpu.mmu_tc = READ_EA_32(ea);
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if (m68ki_cpu.mmu_tc & 0x80000000)
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{
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m68ki_cpu.pmmu_enabled = 1;
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}
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else
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{
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m68ki_cpu.pmmu_enabled = 0;
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}
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break;
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case 2: // supervisor root pointer
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temp64 = READ_EA_64(ea);
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m68ki_cpu.mmu_srp_limit = (temp64>>32) & 0xffffffff;
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m68ki_cpu.mmu_srp_aptr = temp64 & 0xffffffff;
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break;
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case 3: // CPU root pointer
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temp64 = READ_EA_64(ea);
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m68ki_cpu.mmu_crp_limit = (temp64>>32) & 0xffffffff;
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m68ki_cpu.mmu_crp_aptr = temp64 & 0xffffffff;
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break;
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default:
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fprintf(stderr,"680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, REG_PC);
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break;
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}
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}
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break;
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case 3: // MC68030 to/from status reg
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if (modes & 0x200)
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{
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WRITE_EA_32(ea, m68ki_cpu.mmu_sr);
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}
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else
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{
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m68ki_cpu.mmu_sr = READ_EA_32(ea);
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}
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break;
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default:
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fprintf(stderr,"680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes>>13) & 0x7, modes, REG_PC);
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break;
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}
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}
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break;
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default:
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fprintf(stderr,"680x0: unknown PMMU instruction group %d\n", (m68ki_cpu.ir>>9) & 0x7);
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break;
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}
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}
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}
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