- fixed all CHK2/CMP2 instructions to support signed bounds. Previously it only worked with unsigned. Also sped up a bit
by changing | by || in Z evaluation formula
- cptrapcc opcodes are still unsupported, but if no exception occurs, at least PC is properly updated
- trapt/trapcc 16 & 32 instructions: PC is updated before exception is triggered (or if exception isn't triggered). This fixes the
return address value (just in case code returns from trap with RTE) and also the stackframe (XDAda 68040 compiler
read the data parameter to check exception type, wrong exception type is read if stackframe is incorrect)
in m68kfpu.c
- fatalerror message fprintf => vfprintf
- added address register + displacement mode (mode 5, READ_EA_FPE/WRITE_EA_FPE), also changed prototype to it can be called with this mode
from FMOVEM loop
- added immediate mode (READ_EA_FPE)
- fpgen_rm_reg (FMOVE to register): added a lot of missing condition code update (SET_CONDITION_CODES(REG_FP[dst]))
- added FSDIVS and FSMULS (easy as it's the same case as FDIV and FMUL). Updated condition codes for FDIV
- fmove_fpcr: connected softfloat 4 rounding modes to this instruction, that didn't set rounding at all, when it's
perfectly emulated in softfloat module (just added: float_rounding_mode = (REG_FPCR >> 4) & 0x3;)
- fmovem: added address register+displacement mode (READ_EA_FPE/WRITE_EA_FPE interface had to be changed)
- added FScc instruction
- note: number of cycles for the added instructions isn't exact
- fixed all CHK2/CMP2 instructions to support signed bounds. Previously it only worked with unsigned. Also sped up a bit
by changing | by || in Z evaluation formula
- cptrapcc opcodes are still unsupported, but if no exception occurs, at least PC is properly updated
- trapt/trapcc 16 & 32 instructions: PC is updated before exception is triggered (or if exception isn't triggered). This fixes the
return address value (just in case code returns from trap with RTE) and also the stackframe (XDAda 68040 compiler
read the data parameter to check exception type, wrong exception type is read if stackframe is incorrect)
m68kfpu.c:
- fatalerror message fprintf => vfprintf
- added address register + displacement mode (mode 5, READ_EA_FPE/WRITE_EA_FPE), also changed prototype to it can be called with this mode
from FMOVEM loop
- added immediate mode (READ_EA_FPE)
- fpgen_rm_reg (FMOVE to register): added a lot of missing condition code update (SET_CONDITION_CODES(REG_FP[dst]))
- added FSDIVS and FSMULS (easy as it's the same case as FDIV and FMUL). Updated condition codes for FDIV
- fmove_fpcr: connected softfloat 4 rounding modes to this instruction, that didn't set rounding at all, when it's
perfectly emulated in softfloat module (just added: float_rounding_mode = (REG_FPCR >> 4) & 0x3;)
- fmovem: added address register+displacement mode (READ_EA_FPE/WRITE_EA_FPE interface had to be changed)
- added FScc instruction
- note: number of cycles for the added instructions isn't exact
- Reworked PMMU/core interface so PMMU now sees all cop 0 instructions
- Improved disassembly of PMMU instructions
- Preliminary 68LC040 support
- Fixed disassembly for EC/LC variants of '030/'040
- Added working PMMU address translation (not feature complete, but sufficient
to boot several 68030 Macs in MESS)
- Fixed up disassembly of some PMMU instructions
- Added "68020 with 68851" CPU type
Beefed up the warnings and cleared them up.
m68kfpu.c is no longer included by m68kcpu.c.
Removed a bunch of internal function forward declarations, except for those used by macros.
Converted CRLF line endings to LF.
The cycle counts in m68k_in.c are representative for the minimum An/Dn
base case, and additional addressing mode cycle costs are added
elsewhere per mode.
But no An/Dn base case is available for MOVEM, so the data were likely
from the "address indirect" mode, causing an additional cost of 4 or 8
cycles for all addressing modes in the "." case in the table.
So we now fill the table with the cycles for a hypothetical register
base case not present for MOVEM, in order to end up with the correct
calculated cycles for the existing addressing modes.
Which always consumes 14 cycles before, but now consumes either 10 or 14
cycles, depending on if the branch was taken (10), or not (14). This is
consistent with the behaviour of the other DBcc instructions, as well as
other compared emulators.
The SUBA <ea>, An instruction (both word and long variants) must
evaluate the source operand before the destination operand (<ea> before
An), because in case of pi/pd addressing modes, the increment/decrement
side-effect to AY must happen before reading AX if both AX and AY
references the same register!
The ADDA <ea>, An instruction (both word and long variants) must
evaluate the source operand before the destination operand (<ea> before
An), because in case of pi/pd addressing modes, the increment/decrement
side-effect to AY must happen before reading AX if both AX and AY
references the same register!
Fixes cycle counts for byte sized BHI, BLS, BCC, BCS, BNE, BEQ, BVC,
BVS, BPL, BMI, BGE, BLT, BGT and BLE on the 68000 and 68010, for both
'branch taken' and 'branch not taken' cases.
MC680000UM (9th ed) Table 8-9 lists the 68000 byte sized Bcc 'branch
taken' as 10 cycles, and 'not taken' as 8 cycles. Table 9-15 lists the
corresponding 68010 times as 10 and 6 cycles.
Musashi consumes 2 fewer cycles for each case.
The M68KMAKE_TABLE_BODY should specify the cycle count for 'branch
taken', as m68k_set_cpu_type() sets up relative adjustments for 'branch
not taken', used in the 14 different bcc_8 instructions.
The relative adjustment specified in Musashi (CYC_BCC_NOTAKE_B) is -2
for the 68000, and -4 for the 68010, so M68KMAKE_TABLE_BODY should say
10, not 8 for both CPU types.
On the 68000 and 68010 shift distance affect execution time, so the
cycle cost of shifting must be taken into account. (On the 68020, shift
distance does not affect execution time.)
This commit fixes a bug in the adjustments made to the m68ki_cycles
table, for all shift operations with known shift distance (where the
shift distance is encoded in the instruction word).
Affects cycle counts for ASL/ASR, LSL/LSR, ROL/ROR, ROXL/ROXR on the
68000 and 68010.
