d5576b3797
- Added working PMMU address translation (not feature complete, but sufficient to boot several 68030 Macs in MESS) - Fixed up disassembly of some PMMU instructions - Added "68020 with 68851" CPU type
829 lines
16 KiB
C
829 lines
16 KiB
C
#include <math.h>
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#include "m68kcpu.h"
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#define FPCC_N 0x08000000
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#define FPCC_Z 0x04000000
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#define FPCC_I 0x02000000
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#define FPCC_NAN 0x01000000
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#define DOUBLE_INFINITY (unsigned long long)(0x7ff0000000000000)
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#define DOUBLE_EXPONENT (unsigned long long)(0x7ff0000000000000)
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#define DOUBLE_MANTISSA (unsigned long long)(0x000fffffffffffff)
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static inline void SET_CONDITION_CODES(fp_reg reg)
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{
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REG_FPSR &= ~(FPCC_N|FPCC_Z|FPCC_I|FPCC_NAN);
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// sign flag
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if (reg.i & (unsigned long long)(0x8000000000000000))
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{
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REG_FPSR |= FPCC_N;
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}
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// zero flag
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if ((reg.i & (unsigned long long)(0x7fffffffffffffff)) == 0)
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{
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REG_FPSR |= FPCC_Z;
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}
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// infinity flag
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if ((reg.i & (unsigned long long)(0x7fffffffffffffff)) == DOUBLE_INFINITY)
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{
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REG_FPSR |= FPCC_I;
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}
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// NaN flag
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if (((reg.i & DOUBLE_EXPONENT) == DOUBLE_EXPONENT) && ((reg.i & DOUBLE_MANTISSA) != 0))
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{
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REG_FPSR |= FPCC_NAN;
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}
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}
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static inline int TEST_CONDITION(int condition)
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{
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int n = (REG_FPSR & FPCC_N) != 0;
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int z = (REG_FPSR & FPCC_Z) != 0;
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int nan = (REG_FPSR & FPCC_NAN) != 0;
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int r = 0;
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switch (condition)
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{
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case 0x00: return 0; // False
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case 0x01: return (z); // Equal
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case 0x0e: return (!z); // Not Equal
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case 0x0f: return 1; // True
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case 0x12: return (!(nan || z || n)); // Greater Than
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case 0x13: return (z || !(nan || n)); // Greater or Equal
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case 0x14: return (n && !(nan || z)); // Less Than
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case 0x15: return (z || (n && !nan)); // Less Than or Equal
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case 0x1a: return (nan || !(n || z)); // Not Less Than or Equal
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case 0x1b: return (nan || z || !n); // Not Less Than
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case 0x1c: return (nan || (n && !z)); // Not Greater or Equal Than
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case 0x1d: return (nan || z || n); // Not Greater Than
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default: fatalerror("M68040: test_condition: unhandled condition %02X\n", condition);
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}
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return r;
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}
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static uint8 READ_EA_8(int ea)
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{
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int mode = (ea >> 3) & 0x7;
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int reg = (ea & 0x7);
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switch (mode)
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{
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case 0: // Dn
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{
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return REG_D[reg];
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}
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case 5: // (d16, An)
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{
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uint32 ea = EA_AY_DI_8();
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return m68ki_read_8(ea);
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}
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case 6: // (An) + (Xn) + d8
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{
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uint32 ea = EA_AY_IX_8();
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return m68ki_read_8(ea);
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}
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case 7:
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{
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switch (reg)
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{
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case 1: // (xxx).L
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{
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uint32 d1 = OPER_I_16();
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uint32 d2 = OPER_I_16();
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uint32 ea = (d1 << 16) | d2;
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return m68ki_read_8(ea);
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}
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case 4: // #<data>
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{
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return OPER_I_8();
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}
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default: fatalerror("MC68040: READ_EA_8: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
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}
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break;
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}
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default: fatalerror("MC68040: READ_EA_8: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
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}
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return 0;
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}
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static uint16 READ_EA_16(int ea)
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{
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int mode = (ea >> 3) & 0x7;
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int reg = (ea & 0x7);
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switch (mode)
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{
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case 0: // Dn
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{
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return (uint16)(REG_D[reg]);
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}
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case 2: // (An)
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{
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uint32 ea = REG_A[reg];
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return m68ki_read_16(ea);
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}
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case 5: // (d16, An)
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{
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uint32 ea = EA_AY_DI_16();
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return m68ki_read_16(ea);
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}
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case 6: // (An) + (Xn) + d8
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{
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uint32 ea = EA_AY_IX_16();
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return m68ki_read_16(ea);
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}
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case 7:
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{
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switch (reg)
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{
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case 1: // (xxx).L
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{
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uint32 d1 = OPER_I_16();
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uint32 d2 = OPER_I_16();
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uint32 ea = (d1 << 16) | d2;
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return m68ki_read_16(ea);
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}
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case 4: // #<data>
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{
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return OPER_I_16();
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}
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default: fatalerror("MC68040: READ_EA_16: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
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}
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break;
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}
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default: fatalerror("MC68040: READ_EA_16: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
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}
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return 0;
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}
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static uint32 READ_EA_32(int ea)
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{
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int mode = (ea >> 3) & 0x7;
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int reg = (ea & 0x7);
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switch (mode)
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{
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case 0: // Dn
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{
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return REG_D[reg];
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}
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case 2: // (An)
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{
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uint32 ea = REG_A[reg];
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return m68ki_read_32(ea);
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}
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case 3: // (An)+
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{
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uint32 ea = EA_AY_PI_32();
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return m68ki_read_32(ea);
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}
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case 5: // (d16, An)
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{
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uint32 ea = EA_AY_DI_32();
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return m68ki_read_32(ea);
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}
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case 6: // (An) + (Xn) + d8
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{
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uint32 ea = EA_AY_IX_32();
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return m68ki_read_32(ea);
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}
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case 7:
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{
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switch (reg)
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{
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case 1: // (xxx).L
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{
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uint32 d1 = OPER_I_16();
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uint32 d2 = OPER_I_16();
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uint32 ea = (d1 << 16) | d2;
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return m68ki_read_32(ea);
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}
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case 2: // (d16, PC)
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{
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uint32 ea = EA_PCDI_32();
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return m68ki_read_32(ea);
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}
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case 4: // #<data>
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{
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return OPER_I_32();
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}
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default: fatalerror("MC68040: READ_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
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}
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break;
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}
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default: fatalerror("MC68040: READ_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
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}
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return 0;
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}
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static void WRITE_EA_32(int ea, uint32 data)
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{
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int mode = (ea >> 3) & 0x7;
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int reg = (ea & 0x7);
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switch (mode)
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{
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case 0: // Dn
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{
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REG_D[reg] = data;
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break;
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}
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case 2: // (An)
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{
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uint32 ea = REG_A[reg];
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m68ki_write_32(ea, data);
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break;
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}
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case 3: // (An)+
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{
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uint32 ea = EA_AY_PI_32();
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m68ki_write_32(ea, data);
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break;
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}
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case 4: // -(An)
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{
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uint32 ea = EA_AY_PD_32();
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m68ki_write_32(ea, data);
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break;
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}
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case 5: // (d16, An)
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{
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uint32 ea = EA_AY_DI_32();
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m68ki_write_32(ea, data);
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break;
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}
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case 6: // (An) + (Xn) + d8
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{
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uint32 ea = EA_AY_IX_32();
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m68ki_write_32(ea, data);
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break;
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}
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case 7:
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{
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switch (reg)
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{
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case 1: // (xxx).L
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{
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uint32 d1 = OPER_I_16();
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uint32 d2 = OPER_I_16();
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uint32 ea = (d1 << 16) | d2;
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m68ki_write_32(ea, data);
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break;
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}
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case 2: // (d16, PC)
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{
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uint32 ea = EA_PCDI_32();
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m68ki_write_32(ea, data);
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break;
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}
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default: fatalerror("MC68040: WRITE_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
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}
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break;
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}
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default: fatalerror("MC68040: WRITE_EA_32: unhandled mode %d, reg %d, data %08X at %08X\n", mode, reg, data, REG_PC);
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}
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}
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static uint64 READ_EA_64(int ea)
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{
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int mode = (ea >> 3) & 0x7;
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int reg = (ea & 0x7);
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uint32 h1, h2;
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switch (mode)
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{
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case 2: // (An)
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{
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uint32 ea = REG_A[reg];
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h1 = m68ki_read_32(ea+0);
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h2 = m68ki_read_32(ea+4);
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return (uint64)(h1) << 32 | (uint64)(h2);
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}
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case 3: // (An)+
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{
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uint32 ea = REG_A[reg];
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REG_A[reg] += 8;
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h1 = m68ki_read_32(ea+0);
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h2 = m68ki_read_32(ea+4);
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return (uint64)(h1) << 32 | (uint64)(h2);
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}
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case 5: // (d16, An)
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{
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uint32 ea = EA_AY_DI_32();
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h1 = m68ki_read_32(ea+0);
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h2 = m68ki_read_32(ea+4);
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return (uint64)(h1) << 32 | (uint64)(h2);
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}
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case 7:
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{
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switch (reg)
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{
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case 4: // #<data>
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{
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h1 = OPER_I_32();
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h2 = OPER_I_32();
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return (uint64)(h1) << 32 | (uint64)(h2);
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}
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case 2: // (d16, PC)
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{
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uint32 ea = EA_PCDI_32();
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h1 = m68ki_read_32(ea+0);
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h2 = m68ki_read_32(ea+4);
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return (uint64)(h1) << 32 | (uint64)(h2);
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}
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default: fatalerror("MC68040: READ_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
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}
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break;
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}
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default: fatalerror("MC68040: READ_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
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}
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return 0;
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}
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static void WRITE_EA_64(int ea, uint64 data)
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{
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int mode = (ea >> 3) & 0x7;
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int reg = (ea & 0x7);
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switch (mode)
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{
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case 2: // (An)
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{
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uint32 ea = REG_A[reg];
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m68ki_write_32(ea, (uint32)(data >> 32));
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m68ki_write_32(ea, (uint32)(data));
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break;
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}
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case 4: // -(An)
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{
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uint32 ea;
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REG_A[reg] -= 8;
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ea = REG_A[reg];
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m68ki_write_32(ea+0, (uint32)(data >> 32));
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m68ki_write_32(ea+4, (uint32)(data));
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break;
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}
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case 5: // (d16, An)
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{
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uint32 ea = EA_AY_DI_32();
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m68ki_write_32(ea+0, (uint32)(data >> 32));
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m68ki_write_32(ea+4, (uint32)(data));
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break;
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}
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default: fatalerror("MC68040: WRITE_EA_64: unhandled mode %d, reg %d, data %08X%08X at %08X\n", mode, reg, (uint32)(data >> 32), (uint32)(data), REG_PC);
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}
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}
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static fp_reg READ_EA_FPE(int ea)
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{
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fp_reg r;
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int mode = (ea >> 3) & 0x7;
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int reg = (ea & 0x7);
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// TODO: convert to extended floating-point!
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switch (mode)
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{
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case 3: // (An)+
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{
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uint32 d1,d2;
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uint32 ea = REG_A[reg];
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REG_A[reg] += 12;
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d1 = m68ki_read_32(ea+0);
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d2 = m68ki_read_32(ea+4);
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// d3 = m68ki_read_32(ea+8);
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r.i = (uint64)(d1) << 32 | (uint64)(d2);
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break;
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}
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default: fatalerror("MC68040: READ_EA_FPE: unhandled mode %d, reg %d, at %08X\n", mode, reg, REG_PC);
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}
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return r;
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}
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static void WRITE_EA_FPE(int ea, fp_reg fpr)
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{
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int mode = (ea >> 3) & 0x7;
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int reg = (ea & 0x7);
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// TODO: convert to extended floating-point!
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switch (mode)
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{
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case 4: // -(An)
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{
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uint32 ea;
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REG_A[reg] -= 12;
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ea = REG_A[reg];
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m68ki_write_32(ea+0, (uint32)(fpr.i >> 32));
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m68ki_write_32(ea+4, (uint32)(fpr.i));
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m68ki_write_32(ea+8, 0);
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break;
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}
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default: fatalerror("MC68040: WRITE_EA_FPE: unhandled mode %d, reg %d, data %f at %08X\n", mode, reg, fpr.f, REG_PC);
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}
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}
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static void fpgen_rm_reg(uint16 w2)
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{
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int ea = REG_IR & 0x3f;
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int rm = (w2 >> 14) & 0x1;
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int src = (w2 >> 10) & 0x7;
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int dst = (w2 >> 7) & 0x7;
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int opmode = w2 & 0x7f;
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double source;
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if (rm)
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{
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switch (src)
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{
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case 0: // Long-Word Integer
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{
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sint32 d = READ_EA_32(ea);
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source = (double)(d);
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break;
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}
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case 1: // Single-precision Real
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{
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uint32 d = READ_EA_32(ea);
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source = (double)(*(float*)&d);
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break;
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}
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case 2: // Extended-precision Real
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{
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fatalerror("fpgen_rm_reg: extended-precision real load unimplemented at %08X\n", REG_PC-4);
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break;
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}
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case 3: // Packed-decimal Real
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{
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fatalerror("fpgen_rm_reg: packed-decimal real load unimplemented at %08X\n", REG_PC-4);
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break;
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}
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case 4: // Word Integer
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{
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sint16 d = READ_EA_16(ea);
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source = (double)(d);
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break;
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}
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case 5: // Double-precision Real
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{
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uint64 d = READ_EA_64(ea);
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source = *(double*)&d;
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break;
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}
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case 6: // Byte Integer
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{
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sint8 d = READ_EA_8(ea);
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source = (double)(d);
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break;
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}
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default: fatalerror("fmove_rm_reg: invalid source specifier at %08X\n", REG_PC-4);
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}
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}
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else
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{
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source = REG_FP[src].f;
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}
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switch (opmode)
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{
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case 0x00: // FMOVE
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{
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REG_FP[dst].f = source;
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USE_CYCLES(4);
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break;
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}
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case 0x04: // FSQRT
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{
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REG_FP[dst].f = sqrt(source);
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SET_CONDITION_CODES(REG_FP[dst]);
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USE_CYCLES(109);
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break;
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}
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case 0x18: // FABS
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{
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REG_FP[dst].f = fabs(source);
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SET_CONDITION_CODES(REG_FP[dst]);
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USE_CYCLES(3);
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break;
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}
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case 0x1a: // FNEG
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{
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REG_FP[dst].f = -source;
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SET_CONDITION_CODES(REG_FP[dst]);
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USE_CYCLES(3);
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break;
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}
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case 0x20: // FDIV
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{
|
|
REG_FP[dst].f /= source;
|
|
USE_CYCLES(43);
|
|
break;
|
|
}
|
|
case 0x22: // FADD
|
|
{
|
|
REG_FP[dst].f += source;
|
|
SET_CONDITION_CODES(REG_FP[dst]);
|
|
USE_CYCLES(9);
|
|
break;
|
|
}
|
|
case 0x23: // FMUL
|
|
{
|
|
REG_FP[dst].f *= source;
|
|
SET_CONDITION_CODES(REG_FP[dst]);
|
|
USE_CYCLES(11);
|
|
break;
|
|
}
|
|
case 0x28: // FSUB
|
|
{
|
|
REG_FP[dst].f -= source;
|
|
SET_CONDITION_CODES(REG_FP[dst]);
|
|
USE_CYCLES(9);
|
|
break;
|
|
}
|
|
case 0x38: // FCMP
|
|
{
|
|
fp_reg res;
|
|
res.f = REG_FP[dst].f - source;
|
|
SET_CONDITION_CODES(res);
|
|
USE_CYCLES(7);
|
|
break;
|
|
}
|
|
case 0x3a: // FTST
|
|
{
|
|
fp_reg res;
|
|
res.f = source;
|
|
SET_CONDITION_CODES(res);
|
|
USE_CYCLES(7);
|
|
break;
|
|
}
|
|
|
|
default: fatalerror("fpgen_rm_reg: unimplemented opmode %02X at %08X\n", opmode, REG_PC-4);
|
|
}
|
|
}
|
|
|
|
static void fmove_reg_mem(uint16 w2)
|
|
{
|
|
int ea = REG_IR & 0x3f;
|
|
int src = (w2 >> 7) & 0x7;
|
|
int dst = (w2 >> 10) & 0x7;
|
|
//int kfactor = w2 & 0x7f;
|
|
|
|
switch (dst)
|
|
{
|
|
case 0: // Long-Word Integer
|
|
{
|
|
sint32 d = (sint32)(REG_FP[src].f);
|
|
WRITE_EA_32(ea, d);
|
|
break;
|
|
}
|
|
case 1: // Single-precision Real
|
|
{
|
|
float f = (float)(REG_FP[src].f);
|
|
uint32 d = *(uint32 *)&f;
|
|
WRITE_EA_32(ea, d);
|
|
break;
|
|
}
|
|
case 2: // Extended-precision Real
|
|
{
|
|
fatalerror("fmove_reg_mem: extended-precision real store unimplemented at %08X\n", REG_PC-4);
|
|
break;
|
|
}
|
|
case 3: // Packed-decimal Real with Static K-factor
|
|
{
|
|
fatalerror("fmove_reg_mem: packed-decimal real store unimplemented at %08X\n", REG_PC-4);
|
|
break;
|
|
}
|
|
case 4: // Word Integer
|
|
{
|
|
fatalerror("fmove_reg_mem: word integer store unimplemented at %08X\n", REG_PC-4);
|
|
break;
|
|
}
|
|
case 5: // Double-precision Real
|
|
{
|
|
uint64 d = REG_FP[src].i;
|
|
WRITE_EA_64(ea, d);
|
|
break;
|
|
}
|
|
case 6: // Byte Integer
|
|
{
|
|
fatalerror("fmove_reg_mem: byte integer store unimplemented at %08X\n", REG_PC-4);
|
|
break;
|
|
}
|
|
case 7: // Packed-decimal Real with Dynamic K-factor
|
|
{
|
|
fatalerror("fmove_reg_mem: packed-decimal real store unimplemented at %08X\n", REG_PC-4);
|
|
break;
|
|
}
|
|
}
|
|
|
|
USE_CYCLES(12);
|
|
}
|
|
|
|
static void fmove_fpcr(uint16 w2)
|
|
{
|
|
int ea = REG_IR & 0x3f;
|
|
int dir = (w2 >> 13) & 0x1;
|
|
int reg = (w2 >> 10) & 0x7;
|
|
|
|
if (dir) // From system control reg to <ea>
|
|
{
|
|
switch (reg)
|
|
{
|
|
case 1: WRITE_EA_32(ea, REG_FPIAR); break;
|
|
case 2: WRITE_EA_32(ea, REG_FPSR); break;
|
|
case 4: WRITE_EA_32(ea, REG_FPCR); break;
|
|
default: fatalerror("fmove_fpcr: unknown reg %d, dir %d\n", reg, dir);
|
|
}
|
|
}
|
|
else // From <ea> to system control reg
|
|
{
|
|
switch (reg)
|
|
{
|
|
case 1: REG_FPIAR = READ_EA_32(ea); break;
|
|
case 2: REG_FPSR = READ_EA_32(ea); break;
|
|
case 4: REG_FPCR = READ_EA_32(ea); break;
|
|
default: fatalerror("fmove_fpcr: unknown reg %d, dir %d\n", reg, dir);
|
|
}
|
|
}
|
|
|
|
USE_CYCLES(10);
|
|
}
|
|
|
|
static void fmovem(uint16 w2)
|
|
{
|
|
int i;
|
|
int ea = REG_IR & 0x3f;
|
|
int dir = (w2 >> 13) & 0x1;
|
|
int mode = (w2 >> 11) & 0x3;
|
|
int reglist = w2 & 0xff;
|
|
|
|
if (dir) // From FP regs to mem
|
|
{
|
|
switch (mode)
|
|
{
|
|
case 0: // Static register list, predecrement addressing mode
|
|
{
|
|
for (i=0; i < 8; i++)
|
|
{
|
|
if (reglist & (1 << i))
|
|
{
|
|
WRITE_EA_FPE(ea, REG_FP[i]);
|
|
USE_CYCLES(2);
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
default: fatalerror("040fpu0: FMOVEM: mode %d unimplemented at %08X\n", mode, REG_PC-4);
|
|
}
|
|
}
|
|
else // From mem to FP regs
|
|
{
|
|
switch (mode)
|
|
{
|
|
case 2: // Static register list, postincrement addressing mode
|
|
{
|
|
for (i=0; i < 8; i++)
|
|
{
|
|
if (reglist & (1 << i))
|
|
{
|
|
REG_FP[7-i] = READ_EA_FPE(ea);
|
|
USE_CYCLES(2);
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
default: fatalerror("040fpu0: FMOVEM: mode %d unimplemented at %08X\n", mode, REG_PC-4);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void fbcc16(void)
|
|
{
|
|
sint32 offset;
|
|
int condition = REG_IR & 0x3f;
|
|
|
|
offset = (sint16)(OPER_I_16());
|
|
|
|
// TODO: condition and jump!!!
|
|
if (TEST_CONDITION(condition))
|
|
{
|
|
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
|
|
m68ki_branch_16(offset-2);
|
|
}
|
|
|
|
USE_CYCLES(7);
|
|
}
|
|
|
|
static void fbcc32(void)
|
|
{
|
|
sint32 offset;
|
|
int condition = REG_IR & 0x3f;
|
|
|
|
offset = OPER_I_32();
|
|
|
|
// TODO: condition and jump!!!
|
|
if (TEST_CONDITION(condition))
|
|
{
|
|
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
|
|
m68ki_branch_32(offset-4);
|
|
}
|
|
|
|
USE_CYCLES(7);
|
|
}
|
|
|
|
|
|
void m68040_fpu_op0(void)
|
|
{
|
|
switch ((REG_IR >> 6) & 0x3)
|
|
{
|
|
case 0:
|
|
{
|
|
uint16 w2 = OPER_I_16();
|
|
switch ((w2 >> 13) & 0x7)
|
|
{
|
|
case 0x0: // FPU ALU FP, FP
|
|
case 0x2: // FPU ALU ea, FP
|
|
{
|
|
fpgen_rm_reg(w2);
|
|
break;
|
|
}
|
|
|
|
case 0x3: // FMOVE FP, ea
|
|
{
|
|
fmove_reg_mem(w2);
|
|
break;
|
|
}
|
|
|
|
case 0x4: // FMOVE ea, FPCR
|
|
case 0x5: // FMOVE FPCR, ea
|
|
{
|
|
fmove_fpcr(w2);
|
|
break;
|
|
}
|
|
|
|
case 0x6: // FMOVEM ea, list
|
|
case 0x7: // FMOVEM list, ea
|
|
{
|
|
fmovem(w2);
|
|
break;
|
|
}
|
|
|
|
default: fatalerror("m68040_fpu_op0: unimplemented subop %d at %08X\n", (w2 >> 13) & 0x7, REG_PC-4);
|
|
}
|
|
break;
|
|
}
|
|
|
|
case 2: // FBcc disp16
|
|
{
|
|
fbcc16();
|
|
break;
|
|
}
|
|
case 3: // FBcc disp32
|
|
{
|
|
fbcc32();
|
|
break;
|
|
}
|
|
|
|
default: fatalerror("m68040_fpu_op0: unimplemented main op %d\n", (REG_IR >> 6) & 0x3);
|
|
}
|
|
}
|
|
|
|
void m68040_fpu_op1(void)
|
|
{
|
|
int ea = REG_IR & 0x3f;
|
|
|
|
switch ((REG_IR >> 6) & 0x3)
|
|
{
|
|
case 0: // FSAVE <ea>
|
|
{
|
|
WRITE_EA_32(ea, 0x00000000);
|
|
// TODO: correct state frame
|
|
break;
|
|
}
|
|
|
|
case 1: // FRESTORE <ea>
|
|
{
|
|
READ_EA_32(ea);
|
|
// TODO: correct state frame
|
|
break;
|
|
}
|
|
|
|
default: fatalerror("m68040_fpu_op1: unimplemented op %d at %08X\n", (REG_IR >> 6) & 0x3, REG_PC-2);
|
|
}
|
|
}
|
|
|
|
|
|
|