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Merge pull request #9986 from hathach/s3-usb-timing-workaround

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ports/espressif/supervisor/usb.c: workaround ESP32-S3 USB PHY setup (cont)
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Dan Halbert 2025-01-21 09:33:32 -05:00 committed by GitHub
commit 1dc332e553
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1 changed files with 3 additions and 33 deletions
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36
ports/espressif/supervisor/usb.c
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@ -89,49 +89,19 @@ void tud_cdc_rx_cb(uint8_t itf) {
}
#endif // CIRCUITPY_USB_DEVICE
#if defined(CONFIG_IDF_TARGET_ESP32S3)
// TEMPORARY WORKAROUND for https://github.com/hathach/tinyusb/issues/2943
#include "soc/rtc_cntl_struct.h"
#include "soc/usb_wrap_struct.h"
#endif
void init_usb_hardware(void) {
#if CIRCUITPY_USB_DEVICE
// Configure USB PHY
// TEMPORARY WORKAROUND for https://github.com/hathach/tinyusb/issues/2943
#if defined(CONFIG_IDF_TARGET_ESP32S3)
(void)phy_hdl;
periph_module_reset(PERIPH_USB_MODULE);
periph_module_enable(PERIPH_USB_MODULE);
USB_WRAP.otg_conf.pad_enable = 1;
// USB_OTG use internal PHY
USB_WRAP.otg_conf.phy_sel = 0;
// phy_sel is controlled by the following register value
RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
// phy_sel=sw_usb_phy_sel=1, USB_OTG is connected with internal PHY
RTCCNTL.usb_conf.sw_usb_phy_sel = 1;
gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
#else
usb_phy_config_t phy_conf = {
.controller = USB_PHY_CTRL_OTG,
.target = USB_PHY_TARGET_INT,
.otg_mode = USB_OTG_MODE_DEVICE,
#ifdef CONFIG_IDF_TARGET_ESP32P4
.otg_speed = USB_PHY_SPEED_HIGH,
#else
.otg_speed = USB_PHY_SPEED_FULL,
#endif
// https://github.com/hathach/tinyusb/issues/2943#issuecomment-2601888322
// Set speed to undefined (auto-detect) to avoid timing/race issue with S3 with host such as macOS
.otg_speed = USB_PHY_SPEED_UNDEFINED,
};
usb_new_phy(&phy_conf, &phy_hdl);
#endif
// Pin the USB task to the same core as CircuitPython. This way we leave
// the other core for networking.