jepler/circuitpython
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

mimxrt/flash: Swap the order of disabling IRQ and disabling the cache.

Browse source 
This change stopped problems with USB IRQ happening during flash writes.

Signed-off-by: robert-hh <robert@hammelrath.com>
This commit is contained in:
robert-hh 2025-01-26 21:39:58 +01:00 committed by Damien George
parent b251aec0fc
commit 2a80d5c68b
1 changed files with 8 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
ports/mimxrt/flash.c
View file

@ -43,14 +43,13 @@ void flash_init(void) {
__attribute__((section(".ram_functions"))) status_t flash_erase_block(uint32_t erase_addr) {
status_t status = kStatus_Fail;
SCB_CleanInvalidateDCache();
SCB_DisableDCache();
__disable_irq();
SCB_DisableDCache();
status = flexspi_nor_flash_erase_block(BOARD_FLEX_SPI, erase_addr);
__enable_irq();
SCB_EnableDCache();
__enable_irq();
return status;
}
@ -60,14 +59,13 @@ __attribute__((section(".ram_functions"))) status_t flash_erase_block(uint32_t e
__attribute__((section(".ram_functions"))) status_t flash_erase_sector(uint32_t erase_addr) {
status_t status = kStatus_Fail;
SCB_CleanInvalidateDCache();
SCB_DisableDCache();
__disable_irq();
SCB_DisableDCache();
status = flexspi_nor_flash_erase_sector(BOARD_FLEX_SPI, erase_addr);
__enable_irq();
SCB_EnableDCache();
__enable_irq();
return status;
}
@ -83,10 +81,6 @@ __attribute__((section(".ram_functions"))) status_t flash_write_block(uint32_t d
if (length == 0) {
status = kStatus_Success; // Nothing to do
} else {
SCB_CleanInvalidateDCache();
SCB_DisableDCache();
// write data in chunks not crossing a page boundary
do {
next_addr = dest_addr - (dest_addr % PAGE_SIZE_BYTES) + PAGE_SIZE_BYTES; // next page boundary
@ -96,7 +90,11 @@ __attribute__((section(".ram_functions"))) status_t flash_write_block(uint32_t d
}
__disable_irq();
SCB_DisableDCache();
status = flexspi_nor_flash_page_program(BOARD_FLEX_SPI, dest_addr, (uint32_t *)src, write_length);
SCB_EnableDCache();
__enable_irq();
// Update remaining data length
@ -106,9 +104,6 @@ __attribute__((section(".ram_functions"))) status_t flash_write_block(uint32_t d
src += write_length;
dest_addr += write_length;
} while ((length > 0) && (status == kStatus_Success));
SCB_EnableDCache();
}
return status;
}