esp32/machine_pwm: Use IDF functions to calculate resolution correctly.
This commit fixes PWM configuration across C3, C6, S2 and S3 chips, which
was broken by 6d799378ba. Without this fix
the PWM frequency is limited to a maximum of 2446Hz (on S2 at least).
Signed-off-by: Andrew Leech <andrew@alelec.net>
This commit is contained in:
parent
86c71a0307
commit
548babf8a0
1 changed files with 16 additions and 34 deletions
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@ -34,6 +34,7 @@
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#include "py/mphal.h"
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#include "driver/ledc.h"
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#include "esp_err.h"
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#include "esp_clk_tree.h"
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#include "soc/gpio_sig_map.h"
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#define PWM_DBG(...)
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@ -209,51 +210,32 @@ static void configure_channel(machine_pwm_obj_t *self) {
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static void set_freq(machine_pwm_obj_t *self, unsigned int freq, ledc_timer_config_t *timer) {
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if (freq != timer->freq_hz) {
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// Find the highest bit resolution for the requested frequency
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unsigned int i = APB_CLK_FREQ; // 80 MHz
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#if SOC_LEDC_SUPPORT_REF_TICK
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if (freq < EMPIRIC_FREQ) {
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i = REF_CLK_FREQ; // 1 MHz
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}
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#endif
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int divider = (i + freq / 2) / freq; // rounded
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if (divider == 0) {
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divider = 1;
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}
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float f = (float)i / divider; // actual frequency
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if (f <= 1.0) {
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f = 1.0;
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}
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i = (unsigned int)roundf((float)i / f);
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unsigned int res = 0;
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for (; i > 1; i >>= 1) {
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++res;
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}
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if (res == 0) {
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res = 1;
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} else if (res > HIGHEST_PWM_RES) {
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// Limit resolution to HIGHEST_PWM_RES to match units of our duty
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res = HIGHEST_PWM_RES;
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}
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// Configure the new resolution and frequency
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timer->duty_resolution = res;
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// Configure the new frequency and resolution
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timer->freq_hz = freq;
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#if SOC_LEDC_SUPPORT_XTAL_CLOCK
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#if SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
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timer->clk_cfg = LEDC_USE_PLL_DIV_CLK;
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#elif SOC_LEDC_SUPPORT_APB_CLOCK
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timer->clk_cfg = LEDC_USE_APB_CLK;
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#elif SOC_LEDC_SUPPORT_XTAL_CLOCK
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timer->clk_cfg = LEDC_USE_XTAL_CLK;
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#else
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timer->clk_cfg = LEDC_USE_APB_CLK;
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#error No supported PWM / LEDC clocks.
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#endif
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#if SOC_LEDC_SUPPORT_REF_TICK
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if (freq < EMPIRIC_FREQ) {
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timer->clk_cfg = LEDC_USE_REF_TICK;
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}
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#endif
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uint32_t src_clk_freq = 0;
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esp_err_t err = esp_clk_tree_src_get_freq_hz(timer->clk_cfg, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_freq);
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if (err != ESP_OK) {
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mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("unable to query source clock frequency %d"), (int)timer->clk_cfg);
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}
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timer->duty_resolution = ledc_find_suitable_duty_resolution(src_clk_freq, timer->freq_hz);
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// Set frequency
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esp_err_t err = ledc_timer_config(timer);
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err = ledc_timer_config(timer);
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if (err != ESP_OK) {
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if (err == ESP_FAIL) {
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mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("unreachable frequency %d"), freq);
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