diff --git a/nrf5/hal/hal_qspie.c b/nrf5/hal/hal_qspie.c
index f9e9352918..d8f86347e7 100644
--- a/nrf5/hal/hal_qspie.c
+++ b/nrf5/hal/hal_qspie.c
@@ -41,4 +41,73 @@ static const uint32_t hal_qspi_frequency_lookup[] = {
     QSPI_FREQUENCY_FREQUENCY_M32 = (0  << QSPI_IFCONFIG1_SCKFREQ_Pos), // 32 Mbps
 };
 
+void hal_qspi_master_init(NRF_QSPI_Type * p_instance, hal_qspi_init_t const * p_qspi_init)
+{
+	// configure SCK
+    QSPI_BASE->PSEL.SCK = (p_qspi_init->clk_pin << QSPI_PSEL_SCK_PIN_Pos)
+                        | (p_qspi_init->clk_pin_port << QSPI_PSEL_SCK_PORT_Pos)
+                        | (QSPI_PSEL_SCK_CONNECT_Connected << QSPI_PSEL_SCK_CONNECT_Pos);
+
+    // configure CS
+    if (p_qspi_init->use_csn) {
+        QSPI_BASE->PSEL.CSN = (p_qspi_init->clk_pin << QSPI_PSEL_CSN_PIN_Pos)
+                            | (p_qspi_init->clk_pin_port << QSPI_PSEL_CSN_PORT_Pos)
+                            | (QSPI_PSEL_CSN_CONNECT_Connected << QSPI_PSEL_CSN_CONNECT_Pos);
+    } else {
+        QSPI_BASE->PSEL.CSN = (QSPI_PSEL_CSN_CONNECT_Disconnected << QSPI_PSEL_CSN_CONNECT_Pos);
+    }
+
+    // configure MOSI/IO0, valid for all configurations
+    QSPI_BASE->PSEL.IO0 = (p_qspi_init->d0_mosi_pin << QSPI_PSEL_IO0_PIN_Pos)
+                        | (p_qspi_init->d0_mosi_pin_port << QSPI_PSEL_IO0_PORT_Pos)
+                        | (QSPI_PSEL_IO0_CONNECT_Connected << QSPI_PSEL_IO0_CONNECT_Pos);
+
+    if (p_qspi_init->data_line != HAL_QSPI_DATA_LINE_SINGLE) {
+        // configure MISO/IO1
+        QSPI_BASE->PSEL.IO1 = (p_qspi_init->d1_miso_pin << QSPI_PSEL_IO1_PIN_Pos)
+                            | (p_qspi_init->d1_miso_pin_port << QSPI_PSEL_IO1_PORT_Pos)
+                            | (QSPI_PSEL_IO1_CONNECT_Connected << QSPI_PSEL_IO1_CONNECT_Pos);
+
+        if (p_qspi_init->data_line == HAL_QSPI_DATA_LINE_QUAD)
+            // configure IO2
+            QSPI_BASE->PSEL.IO2 = (p_qspi_init->d2_pin << QSPI_PSEL_IO2_PIN_Pos)
+                                | (p_qspi_init->d2_pin_port << QSPI_PSEL_IO2_PORT_Pos)
+                                | (QSPI_PSEL_IO2_CONNECT_Connected << QSPI_PSEL_IO2_CONNECT_Pos);
+
+            // configure IO3
+            QSPI_BASE->PSEL.IO3 = (p_qspi_init->d3_pin << QSPI_PSEL_IO3_PIN_Pos)
+                                | (p_qspi_init->d3_pin_port << QSPI_PSEL_IO3_PORT_Pos)
+                                | (QSPI_PSEL_IO3_CONNECT_Connected << QSPI_PSEL_IO3_CONNECT_Pos);
+        }
+    }
+
+    uint32_t mode;
+    switch (p_spi_init->mode) {
+        case HAL_SPI_MODE_CPOL0_CPHA0:
+            mode = (QSPI_IFCONFIG1_SPIMODE_MODE0 << QSPI_IFCONFIG1_SPIMODE_Pos);
+            break;
+        case HAL_SPI_MODE_CPOL1_CPHA1:
+            mode = (QSPI_IFCONFIG1_SPIMODE_MODE3 << QSPI_IFCONFIG1_SPIMODE_Pos);
+            break;
+        default:
+            mode = 0;
+            break;
+    }
+
+    // interface config1
+    QSPI_BASE->IFCONFIG1 = hal_qspi_frequency_lookup[p_qspi_init->freq]
+                         | mode
+                         | (1 << QSPI_IFCONFIG1_SCKDELAY_Pos); // number of 16 MHz periods (62.5 ns)
+
+    QSPI_BASE->ENABLE = 1;
+}
+
+void hal_qspi_master_tx_rx(NRF_QSPI_Type  * p_instance,
+                           uint16_t         transfer_size,
+                           const uint8_t  * tx_data,
+                           uint8_t        * rx_data)
+{
+
+}
+
 #endif // HAL_QSPIE_MODULE_ENABLED
diff --git a/nrf5/hal/hal_qspie.h b/nrf5/hal/hal_qspie.h
index c62d32ac51..99c1c4cee9 100644
--- a/nrf5/hal/hal_qspie.h
+++ b/nrf5/hal/hal_qspie.h
@@ -74,11 +74,14 @@ typedef struct {
     uint8_t d2_pin;
     uint8_t d3_pin;
     uint8_t clk_pin;
+    uint8_t csn_pin;
     uint8_t d0_mosi_pin_port;
     uint8_t d1_miso_pin_port;
     uint8_t d2_pin_port;
     uint8_t d3_pin_port;
     uint8_t clk_pin_port;
+    uint8_t csn_pin_port;
+    bool use_csn;
     hal_qspi_mode_t mode;
     hal_qspi_data_line_t data_line;
     hal_qspi_clk_freq_t freq;