Python 2.7 has been EOL since January 2020.
Ubuntu oldoldlts (Focal Fossa, 20.04) has Python 3.8.
Debian oldoldstable (Buster, from 2019) has Python 3.7.
RHEL 8 (from 2019) has Python 3.6.
It's easier than ever to install a modern Python using uv.
Given this, it seems like a fine idea to drop Python 2.7 support.
Even though the build is not tested on Python as old as 3.3, I
left comments stating that "3.3+" is the baseline Python version.
However, it might make sense to bump this to e.g., 3.10, the oldest
Python 3 version used during CI. Or, using uv or another method
actually test on the oldest Python interpreter that is desirable
to support (uv goes back to Python 3.7 easily; in October 2025, the
oldest supported Python interpreter version will be 3.10)
Signed-off-by: Jeff Epler <jepler@gmail.com>
This commit adds preliminary support for ST's new STM32N6xx MCUs.
Supported features of this MCU so far are:
- basic clock tree initialisation, running at 800MHz
- fully working USB
- XSPI in memory-mapped mode
- machine.Pin
- machine.UART
- RTC and deepsleep support
- SD card
- filesystem
- ROMFS
- WiFi and BLE via cyw43-driver (SDIO backend)
Note that the N6 does not have internal flash, and has some tricky boot
sequence, so using a custom bootloader (mboot) is almost a necessity.
Signed-off-by: Damien George <damien@micropython.org>
The expressions for the `micropy_hw_hse_value` etc variables may contain
parenthesis, eg `micropy_hw_hse_value = ((25) * 1000000)`. To handle such
a case, simplify the regex and always use `eval(found)` to evaluate the
expression.
Signed-off-by: Damien George <damien@micropython.org>
This commit improves pllvalues.py to generate PLL values for H7 MCUs that
are valid (VCO in and out are in range) and extend for the entire range of
SYSCLK values up to 400MHz (up to 480MHz is currently unsupported).
This patch makes pllvalues.py generate two tables: one for when HSI is used
and one for when HSE is used. The correct table is then selected at
compile time via the existing MICROPY_HW_CLK_USE_HSI.
MCUs that have a PLLSAI can use it to generate a 48MHz clock for USB, SDIO
and RNG peripherals. In such cases the SYSCLK is not restricted to values
that allow the system PLL to generate 48MHz, but can be any frequency.
This patch allows such configurability for F7 MCUs, allowing the SYSCLK to
be set in 2MHz increments via machine.freq(). PLLSAI will only be enabled
if needed, and consumes about 1mA extra. This fine grained control of
frequency is useful to get accurate SPI baudrates, for example.
This is to keep the top-level directory clean, to make it clear what is
core and what is a port, and to allow the repository to grow with new ports
in a sustainable way.
2017-09-06 13:40:51 +10:00
Renamed from stmhal/boards/pllvalues.py (Browse further)
