Supporting readfrom_mem*(). writeto_mem() and a set of IRQs. Enabled by default for SAMD51 devices and SAMD21 devices with external flash. Tested with ItsyBitsy M4 and ItsyBitsy M0 with both on-board SoftI2C and a RP2 Pico as controller. Signed-off-by: Damien George <damien@micropython.org> Signed-off-by: robert-hh <robert@hammelrath.com>
213 lines
8.2 KiB
C
213 lines
8.2 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020-2021 Damien P. George
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* Copyright (c) 2022-2025 Robert Hammelrath
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/runtime.h"
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#include "samd_soc.h"
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#include "pin_af.h"
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#include "genhdr/pins.h"
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#define TRANSMIT (1)
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#define RECEIVE (0)
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#define NACK_RECVD (i2c->I2CS.STATUS.bit.RXNACK == 1)
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#define IRQ_AMATCH (i2c->I2CS.INTFLAG.bit.AMATCH == 1)
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#define IRQ_DRDY (i2c->I2CS.INTFLAG.bit.DRDY == 1)
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#define IRQ_STOP (i2c->I2CS.INTFLAG.bit.PREC == 1)
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#define PREPARE_ACK i2c->I2CS.CTRLB.bit.ACKACT = 0
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#define PREPARE_NACK i2c->I2CS.CTRLB.bit.ACKACT = 1
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typedef struct _machine_i2c_target_obj_t {
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mp_obj_base_t base;
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Sercom *instance;
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uint8_t id;
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uint8_t scl;
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uint8_t sda;
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uint8_t addr;
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uint8_t direction;
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} machine_i2c_target_obj_t;
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void common_i2c_target_irq_handler(int i2c_id) {
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// Handle Sercom I2C IRQ for target memory mode.
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machine_i2c_target_obj_t *self = MP_STATE_PORT(sercom_table[i2c_id]);
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machine_i2c_target_data_t *data = &machine_i2c_target_data[i2c_id];
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if (self != NULL) {
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Sercom *i2c = self->instance;
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if (IRQ_AMATCH) {
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// Address match.
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self->direction = i2c->I2CS.STATUS.bit.DIR;
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machine_i2c_target_data_addr_match(data, self->direction);
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// Send ACK
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i2c->I2CS.CTRLB.bit.CMD = 3;
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} else if (IRQ_DRDY) {
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// Data to be handled, depending in the direction
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if (self->direction == TRANSMIT) {
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machine_i2c_target_data_read_request(self, data);
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} else {
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machine_i2c_target_data_write_request(self, data);
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}
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// ACK will be sent in mp_machine_i2c_target_read_bytes/mp_machine_i2c_target_write_bytes.
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} else if (IRQ_STOP) {
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// Stop detected. Just reset the data machine.
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machine_i2c_target_data_stop(data);
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i2c->I2CS.INTFLAG.reg |= SERCOM_I2CS_INTFLAG_PREC;
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} else { // On any error clear the interrupts and reset the data state.
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machine_i2c_target_data_stop(data);
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i2c->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR | SERCOM_I2CS_INTFLAG_AMATCH |
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SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC;
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}
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}
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}
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/******************************************************************************/
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// I2CTarget port implementation
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static inline size_t mp_machine_i2c_target_get_index(machine_i2c_target_obj_t *self) {
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return self->id;
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}
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static void mp_machine_i2c_target_event_callback(machine_i2c_target_irq_obj_t *irq) {
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mp_irq_handler(&irq->base);
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}
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static size_t mp_machine_i2c_target_read_bytes(machine_i2c_target_obj_t *self, size_t len, uint8_t *buf) {
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Sercom *i2c = self->instance;
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buf[0] = i2c->I2CS.DATA.reg;
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i2c->I2CS.CTRLB.bit.CMD = 3; // send ACK
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return 1;
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}
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static size_t mp_machine_i2c_target_write_bytes(machine_i2c_target_obj_t *self, size_t len, const uint8_t *buf) {
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Sercom *i2c = self->instance;
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i2c->I2CS.DATA.reg = buf[0];
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i2c->I2CS.CTRLB.bit.CMD = 3; // send ACK
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return 1;
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}
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static inline void mp_machine_i2c_target_irq_config(machine_i2c_target_obj_t *self, unsigned int trigger) {
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(void)self;
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(void)trigger;
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}
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mp_obj_t mp_machine_i2c_target_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
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enum { ARG_id, ARG_addr, ARG_addrsize, ARG_mem, ARG_mem_addrsize, ARG_scl, ARG_sda };
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static const mp_arg_t allowed_args[] = {
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#if MICROPY_HW_DEFAULT_I2C_ID < 0
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{ MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = -1} },
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#else
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{ MP_QSTR_id, MP_ARG_INT, {.u_int = MICROPY_HW_DEFAULT_I2C_ID} },
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#endif
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{ MP_QSTR_addr, MP_ARG_REQUIRED | MP_ARG_INT },
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{ MP_QSTR_addrsize, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 7} },
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{ MP_QSTR_mem, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
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{ MP_QSTR_mem_addrsize, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 8} },
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#if defined(pin_SCL) && defined(pin_SDA)
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{ MP_QSTR_scl, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = pin_SCL} },
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{ MP_QSTR_sda, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = pin_SDA} },
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#else
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{ MP_QSTR_scl, MP_ARG_REQUIRED | MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
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{ MP_QSTR_sda, MP_ARG_REQUIRED | MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
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#endif
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};
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// Parse args.
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mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
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mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
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// Get I2C bus.
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int id = args[ARG_id].u_int;
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if (id < 0 || id >= SERCOM_INST_NUM) {
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mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("I2C(%d) doesn't exist"), id);
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}
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// Get the peripheral object.
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machine_i2c_target_obj_t *self = mp_obj_malloc_with_finaliser(machine_i2c_target_obj_t, &machine_i2c_target_type);
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self->id = id;
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self->instance = sercom_instance[id];
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// Set SCL/SDA pins.
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self->sda = pin_config_for_i2c(args[ARG_sda].u_obj, id, 0);
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self->scl = pin_config_for_i2c(args[ARG_scl].u_obj, id, 1);
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MP_STATE_PORT(sercom_table[id]) = self;
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// Get the address and initialise data.
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self->addr = args[ARG_addr].u_int;
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MP_STATE_PORT(machine_i2c_target_mem_obj)[id] = args[ARG_mem].u_obj;
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machine_i2c_target_data_t *data = &machine_i2c_target_data[id];
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machine_i2c_target_data_init(data, args[ARG_mem].u_obj, args[ARG_mem_addrsize].u_int);
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// Set up the clocks
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enable_sercom_clock(id);
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// Initialise the I2C peripheral
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Sercom *i2c = self->instance;
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// Reset the device
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i2c->I2CS.CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST;
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while (i2c->I2CS.SYNCBUSY.bit.SWRST == 1) {
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}
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// Set to slave mode, enable SCl timeout, set the address
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i2c->I2CS.CTRLA.reg = SERCOM_I2CS_CTRLA_MODE(0x04)
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| SERCOM_I2CS_CTRLA_SEXTTOEN | SERCOM_I2CS_CTRLA_LOWTOUTEN;
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i2c->I2CS.ADDR.reg = self->addr << 1;
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// Enable interrupts
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sercom_register_irq(id, &common_i2c_target_irq_handler);
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#if defined(MCU_SAMD21)
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NVIC_EnableIRQ(SERCOM0_IRQn + id);
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#elif defined(MCU_SAMD51)
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NVIC_EnableIRQ(SERCOM0_0_IRQn + 4 * id);
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NVIC_EnableIRQ(SERCOM0_0_IRQn + 4 * id + 1);
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NVIC_EnableIRQ(SERCOM0_0_IRQn + 4 * id + 2);
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NVIC_EnableIRQ(SERCOM0_0_IRQn + 4 * id + 3);
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#endif
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i2c->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY | SERCOM_I2CS_INTENSET_AMATCH |
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SERCOM_I2CS_INTENSET_PREC | SERCOM_I2CS_INTENSET_ERROR;
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// Now enable I2C.
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sercom_enable(i2c, 1);
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return MP_OBJ_FROM_PTR(self);
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}
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static void mp_machine_i2c_target_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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machine_i2c_target_obj_t *self = MP_OBJ_TO_PTR(self_in);
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mp_printf(print, "I2C(%u, scl=\"%q\", sda=\"%q\", addr=%u)",
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self->id, pin_find_by_id(self->scl)->name, pin_find_by_id(self->sda)->name,
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self->addr);
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}
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// Stop the Slave transfer and free the memory objects.
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static void mp_machine_i2c_target_deinit(machine_i2c_target_obj_t *self) {
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// Disable I2C
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sercom_enable(self->instance, 0);
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MP_STATE_PORT(sercom_table[self->id]) = NULL;
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}
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