1006ed69f0
This commit expands the Xtensa inline assembler to support most if not all opcodes available on the ESP8266 and LX3 Xtensa cores. This is meant as a stepping stone to add inline assembler support for the ESP32 and its LX6 core, along to windowed-specific opcodes and additional opcodes that are present only on the LX7 core (ESP32-S3 and later). New opcodes being added are covered by tests, and the provided tests were expanded to also include opcodes available in the existing implementation. Given that the ESP8266 space requirements are tighter than ESP32's, certain opcodes that won't be commonly used have been put behind a define to save some space in the general use case. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
119 lines
1.8 KiB
Python
119 lines
1.8 KiB
Python
@micropython.asm_xtensa
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def f1(a2):
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abs_(a2, a2)
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for value in (10, -10, 0):
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print(f1(value))
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ADDMI_TEMPLATE = """
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@micropython.asm_xtensa
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def f1(a2) -> int:
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addmi(a2, a2, {})
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print(f1(0))
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"""
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for value in (-32768, -32767, 32512, 32513, 0):
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try:
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exec(ADDMI_TEMPLATE.format(value))
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except SyntaxError as error:
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print(error)
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@micropython.asm_xtensa
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def a2(a2, a3) -> int:
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addx2(a2, a2, a3)
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@micropython.asm_xtensa
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def a4(a2, a3) -> int:
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addx4(a2, a2, a3)
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@micropython.asm_xtensa
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def a8(a2, a3) -> int:
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addx8(a2, a2, a3)
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@micropython.asm_xtensa
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def s2(a2, a3) -> int:
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subx2(a2, a2, a3)
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@micropython.asm_xtensa
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def s4(a2, a3) -> int:
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subx4(a2, a2, a3)
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@micropython.asm_xtensa
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def s8(a2, a3) -> int:
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subx8(a2, a2, a3)
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for first, second in ((100, 100), (-100, 100), (-100, -100), (100, -100)):
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print("a2", a2(first, second))
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print("a4", a4(first, second))
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print("a8", a8(first, second))
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print("s2", s2(first, second))
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print("s4", s4(first, second))
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print("s8", s8(first, second))
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@micropython.asm_xtensa
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def f5(a2) -> int:
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neg(a2, a2)
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for value in (0, -100, 100):
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print(f5(value))
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@micropython.asm_xtensa
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def f6():
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movi(a2, 0x100)
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movi(a3, 1)
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add(a2, a2, a3)
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addi(a2, a2, 1)
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addi(a2, a2, -2)
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sub(a2, a2, a3)
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print(hex(f6()))
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@micropython.asm_xtensa
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def f7():
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movi(a2, 0x10FF)
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movi(a3, 1)
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and_(a4, a2, a3)
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or_(a4, a4, a3)
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movi(a3, 0x200)
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xor(a2, a4, a3)
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print(hex(f7()))
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@micropython.asm_xtensa
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def f8(a2, a3):
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add_n(a2, a2, a3)
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print(f8(100, 200))
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@micropython.asm_xtensa
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def f9(a2):
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addi_n(a2, a2, 1)
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print(f9(100))
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@micropython.asm_xtensa
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def f10(a2, a3) -> uint:
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mull(a2, a2, a3)
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print(hex(f10(0xC0000000, 2)))
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