351 lines
12 KiB
Python
351 lines
12 KiB
Python
#!/usr/bin/env python
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import sys
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from enum import Enum, auto
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from dataclasses import dataclass, replace
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class Polarity:
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Negative = 0
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Positive = 1
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@dataclass(frozen=True)
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class VideoMode:
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pixel_clock_khz: int
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visible_width: int
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hfront_porch: int
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hsync_pulse: int
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hback_porch: int
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hsync_polarity: Polarity
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@property
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def total_width(self):
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return self.visible_width + self.hfront_porch + self.hsync_pulse + self.hback_porch
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@property
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def line_rate_khz(self):
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return self.pixel_clock_khz / self.total_width
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@property
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def line_time_us(self):
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return 1000 / self.line_rate_khz
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@property
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def visible_line_time_us(self):
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return 1000 * self.visible_width / self.pixel_clock_khz
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visible_height: int
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vfront_porch: int
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vsync_pulse: int
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vback_porch: int
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vsync_polarity: Polarity
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@property
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def total_lines(self):
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return self.visible_height + self.vfront_porch + self.vsync_pulse + self.vback_porch
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@property
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def frame_rate_hz(self):
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return self.line_rate_khz / self.total_lines * 1000
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@property
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def frame_time_ms(self):
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return 1000 / self.frame_rate_hz
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def __repr__(self):
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return f"<VideoMode {self.visible_width}x{self.visible_height} {self.line_rate_khz:.2f}kHz/{self.frame_rate_hz:.2f}Hz pclk={self.pixel_clock_khz:.0f}KHz hvis={self.visible_line_time_us:.2f}us>"
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def change_visible_pixels(mode_in, new_w, new_clock=None):
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print(mode_in)
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if new_clock is None:
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new_clock = mode_in.pixel_clock_khz * new_w / mode_in.visible_width
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new_mode = replace(mode_in,
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pixel_clock_khz = new_clock,
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visible_width = new_w,
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)
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print(new_mode)
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ratio = new_clock / mode_in.pixel_clock_khz
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new_visible_time = new_mode.visible_line_time_us
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new_line_counts = round(mode_in.total_width * ratio)
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print(new_line_counts, mode_in.total_width * ratio)
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new_pulse = round(mode_in.hsync_pulse * ratio)
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new_porch_counts = new_line_counts - new_pulse - new_w
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porch_ratio = mode_in.hfront_porch / (mode_in.hfront_porch + mode_in.hback_porch)
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new_front = round(new_porch_counts * porch_ratio)
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new_back = new_porch_counts - new_front
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print((mode_in.hfront_porch, mode_in.hsync_pulse, mode_in.hback_porch), "->", (new_front, new_pulse, new_back))
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new_mode = replace(
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new_mode,
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hfront_porch = new_front,
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hsync_pulse = new_pulse,
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hback_porch = new_back)
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print(new_mode)
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print()
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return new_mode
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def pio_hard_delay(instr, n, file):
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assert n > 0
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assert n < 128
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while n > 0:
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cycles = min(n, 32)
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print(f" {instr} [{cycles-1}]", file=file)
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n -= cycles
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print(file=file)
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def print_pio_hsync_program(program_name_base, mode, h_divisor, cycles_per_pixel, file=sys.stdout):
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net_khz = mode.pixel_clock_khz / h_divisor
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err = (mode.visible_width + mode.hfront_porch) % h_divisor
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print(f"""
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; Horizontal sync program for {mode}
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; PIO clock frequency = {mode.pixel_clock_khz:.1f}/{h_divisor}khz = {net_khz:.1f}
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;
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.program {program_name_base}_hsync_init
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pull block ; Pull from FIFO to OSR (only happens once)
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.program {program_name_base}_hsync
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.wrap_target ; Program wraps to here
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; ACTIVE + FRONTPORCH {mode.visible_width} + {mode.hfront_porch} error {err}
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mov x, osr ; Copy value from OSR to x scratch register
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activeporch:
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jmp x-- activeporch ; Remain high in active mode and front porch
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""", file=file)
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cycles, err = divmod(mode.hsync_pulse + err, h_divisor)
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print(f"syncpulse: ; {mode.hsync_pulse}/{h_divisor} clocks [actual {cycles} error {err}]", file=file)
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pio_hard_delay(f"set pins, {mode.hsync_polarity:d}", cycles, file=file)
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cycles, err = divmod(mode.hback_porch + err, h_divisor)
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print(f"backporch: ; {mode.hback_porch}/{h_divisor} clocks [actual {cycles} error {err}]", file=file)
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pio_hard_delay(f"set pins, {not mode.hsync_polarity:d}", cycles - 1, file=file)
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print(" irq 0 [1]", file=file)
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print(".wrap", file=file)
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print(f"""
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% c-sdk {{
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static inline void {program_name_base}_hsync_program_init(PIO pio, uint sm, uint offset, uint pin) {{
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pio_sm_config c = {program_name_base}_hsync_program_get_default_config(offset);
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// Map the state machine's SET pin group to one pin, namely the `pin`
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// parameter to this function.
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sm_config_set_set_pins(&c, pin, 1);
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sm_config_set_clkdiv_int_frac(&c, {cycles_per_pixel * h_divisor}, 0);
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// Set this pin's GPIO function (connect PIO to the pad)
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pio_gpio_init(pio, pin);
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// Set the pin direction to output at the PIO
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pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
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// Load our configuration, and jump to the start of the program
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pio_sm_init(pio, sm, offset, &c);
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// Set up initial state by magic
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pio_sm_put_blocking(pio, sm, {mode.visible_height}-1);
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sm_exec_sequence(pio, sm, {program_name_base}_hsync_init_program.instructions, {program_name_base}_hsync_init_program.length);
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// Set the state machine running
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pio_sm_set_enabled(pio, sm, true);
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}}
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%}}
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""", file=file)
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def pio_yloop(instr, n, label, comment, file):
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assert n <= 65
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if n < 3:
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print(f"{label}: ; {comment}", file=file)
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for i in range(n):
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print(f" {instr}", file=file)
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elif n <= 33:
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print(f" set y, {n-1 if n <= 32 else 31}", file=file)
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print(f"{label}: ; {comment}", file=file)
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print(f" {instr}", file=file)
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print(f" jmp y--, {label}", file=file)
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if n == 33:
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print(f" {instr}", file=file)
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elif n <= 65:
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print(f" set y, {(n-2)//2}", file=file)
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print(f"{label}: ; {comment}", file=file)
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print(f" {instr}", file=file)
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print(f" {instr}", file=file)
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print(f" jmp y--, {label}", file=file)
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if n & 1:
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print(f" {instr}", file=file)
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print(file=file)
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def print_pio_vsync_program(program_name_base, mode, cycles_per_pixel, file=sys.stdout):
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print(f"""
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.program {program_name_base}_vsync_init
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pull block ; Pull from FIFO to OSR (only once)
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.program {program_name_base}_vsync
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.side_set 1 opt
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; Vertical sync program for {mode}
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;
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.wrap_target ; Program wraps to here
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""", file=file)
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pio_yloop("wait 1 irq 0", mode.vfront_porch, "frontporch", f"{mode.vfront_porch} lines", file=file)
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pio_yloop(f"wait 1 irq 0 side {mode.vsync_polarity:d}", mode.vsync_pulse, "syncpulse", f"{mode.vsync_pulse} lines", file=file)
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pio_yloop(f"wait 1 irq 0 side {not mode.vsync_polarity:d}", mode.vback_porch, "backporch", f"{mode.vback_porch} lines", file=file)
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print(f"""
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; ACTIVE
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mov x, osr ; Copy value from OSR to x scratch register
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active:
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wait 1 irq 0 ; Wait for hsync to go high
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irq 1 ; Signal that we're in active mode
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jmp x-- active ; Remain in active mode, decrementing counter
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""", file=file)
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print(".wrap", file=file)
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print(f"""
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% c-sdk {{
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static inline void {program_name_base}_vsync_program_init(PIO pio, uint sm, uint offset, uint pin) {{
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pio_sm_config c = {program_name_base}_vsync_program_get_default_config(offset);
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// Map the state machine's SIDESET to one pin, namely the `pin`
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// parameter to this function.
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// sm_config_set_sideset(&c, 1, true, false);
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sm_config_set_sideset_pins(&c, pin);
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sm_config_set_sideset(&c, 2, true, false);
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sm_config_set_clkdiv_int_frac(&c, {cycles_per_pixel}, 0);
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// Set this pin's GPIO function (connect PIO to the pad)
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pio_gpio_init(pio, pin);
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// Set the pin direction to output at the PIO
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pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
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// Load our configuration, and jump to the start of the program
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pio_sm_init(pio, sm, offset, &c);
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// Set up initial state by magic
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pio_sm_put_blocking(pio, sm, {mode.visible_height}-1);
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sm_exec_sequence(pio, sm, {program_name_base}_vsync_init_program.instructions, {program_name_base}_vsync_init_program.length);
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// Set the state machine running
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pio_sm_set_enabled(pio, sm, true);
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}}
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%}}
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""", file=file)
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def print_pio_pixel_program(program_name_base, mode, out_instr, cycles_per_pixel, file=sys.stdout):
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net_khz = cycles_per_pixel * mode.pixel_clock_khz
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assert cycles_per_pixel >= 4
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print(f"""
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.program {program_name_base}_pixel_init
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pull block ; Pull from FIFO to OSR (only once)
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mov y, osr ; Copy value from OSR to y scratch register
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out null, 32 ; Clear OSR so first pixels out are right
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.program {program_name_base}_pixel
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; Pixel generator program for {mode}
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; PIO clock frequency = {cycles_per_pixel}×{mode.pixel_clock_khz}khz = {net_khz}
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.wrap_target
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top:
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set pins, 0 ; Zero RGB pins in blanking
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mov x, y ; Initialize counter variable
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wait 1 irq 1 [{cycles_per_pixel-1}] ; wait for vsync active mode
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colorout:
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{out_instr} [{cycles_per_pixel-3}]
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jmp pin, notrig
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; trig:
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in x, 32
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jmp x--, colorout
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jmp top
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notrig:
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jmp x-- colorout [1] ; Stay here thru horizontal active mode
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.wrap""", file=file)
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print(f"""
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% c-sdk {{
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enum {{ {program_name_base}_pixel_clock_khz = {mode.pixel_clock_khz}, {program_name_base}_sys_clock_khz = {cycles_per_pixel * mode.pixel_clock_khz} }};
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static inline void {program_name_base}_pixel_program_init(PIO pio, uint sm, uint offset, uint pin, uint n_pin) {{
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pio_sm_config c = {program_name_base}_pixel_program_get_default_config(offset);
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// Map the state machine's OUT & SET pins
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sm_config_set_out_pins(&c, pin, n_pin);
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sm_config_set_set_pins(&c, pin, n_pin);
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sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
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// 15 pixels (30 bits) per word, left is MSB
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sm_config_set_out_shift(&c, false, true, 30);
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// Set this pin's GPIO function (connect PIO to the pad)
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for(uint i=0; i<n_pin; i++) {{
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pio_gpio_init(pio, pin + i);
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}}
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// Set the pin direction to output at the PIO
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pio_sm_set_consecutive_pindirs(pio, sm, pin, n_pin, true);
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// Load our configuration, and jump to the start of the program
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pio_sm_init(pio, sm, offset, &c);
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// Set up register contents
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pio_sm_put_blocking(pio, sm, {mode.visible_width}-1);
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sm_exec_sequence(pio, sm, {program_name_base}_pixel_init_program.instructions, {program_name_base}_pixel_init_program.length);
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// Set the state machine running
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pio_sm_set_enabled(pio, sm, true);
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}}
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%}}
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""", file=file)
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def print_pio_preamble(file):
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print("""
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.program preamble
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% c-sdk {
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static inline void sm_exec_sequence(PIO pio, uint sm, const uint16_t *instructions, size_t len) {
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for(;len--; instructions++) {
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pio_sm_exec_wait_blocking(pio, sm, *instructions);
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}
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}
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%}
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""", file=file)
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mode_vga_640x480 = VideoMode(25_175, 640, 16, 96, 48, Polarity.Negative, 480, 10, 2, 33, Polarity.Negative)
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mode_vga_660x480 = change_visible_pixels(mode_vga_640x480, 660, 26_000)
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mode_vga_720x400 = VideoMode(28_321, 720, 18, 108, 54, Polarity.Negative, 400, 10, 2, 36, Polarity.Positive)
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mode_vga_660x400 = change_visible_pixels(mode_vga_720x400, 660, 26_000)
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if 1:
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print(mode_vga_640x480, 6*mode_vga_640x480.pixel_clock_khz)
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print(mode_vga_660x480, 6*mode_vga_660x480.pixel_clock_khz)
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print(mode_vga_720x400, 6*mode_vga_720x400.pixel_clock_khz)
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print(mode_vga_660x400, 6*mode_vga_660x400.pixel_clock_khz)
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def print_all(mode, h_divisor=1, out_instr="out pins, 2", cycles_per_pixel=6, file=sys.stdout):
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print_pio_preamble(file=file)
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program_name = f"vga_{mode.visible_width}x{mode.visible_height}_{mode.frame_rate_hz:.0f}"
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print_pio_hsync_program(program_name, mode, h_divisor, cycles_per_pixel, file=file)
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print("\n\n\n", file=file)
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print_pio_vsync_program(program_name, mode, cycles_per_pixel, file=file)
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print("\n\n\n", file=file)
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print_pio_pixel_program(program_name, mode, out_instr, cycles_per_pixel, file=file)
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with open("vga_660x480_60.pio", "wt", encoding="utf-8") as f:
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print_all(mode_vga_660x480, file=f)
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with open("vga_660x400_70.pio", "wt", encoding="utf-8") as f:
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print_all(mode_vga_660x400, file=f)
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