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208 changed files with 44834 additions and 74860 deletions

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name: CI
on: [push, pull_request]
jobs:
build:
runs-on: ubuntu-22.04
steps:
- uses: actions/checkout@v4
- name: Set environment variables
id: vars
run: |
echo "sha_short=$(git rev-parse --short HEAD)" >> $GITHUB_OUTPUT
- name: Dependency packages (apt)
run: |
sudo apt update
sudo apt -y install git gcc-arm-none-eabi python3-pip srecord stm32flash zip unzip wget
- name: Dependency packages (pip)
run: python3 -m pip install --user crcmod intelhex
- name: Build dist
run: |
export VER=${{ steps.vars.outputs.sha_short }}
make -j4 dist VER=$VER
mkdir -p _cidist
mv out/flashfloppy-$VER .
rm flashfloppy-$VER/RELEASE_NOTES
git rev-parse HEAD >flashfloppy-$VER/COMMIT
zip -r flashfloppy-$VER.zip flashfloppy-$VER
mv flashfloppy-$VER.zip _cidist/
- name: Build debug dist
run: |
export VER=${{ steps.vars.outputs.sha_short }}-debug
make -j4 dist VER=$VER level=debug
mv out/flashfloppy-$VER .
rm flashfloppy-$VER/RELEASE_NOTES
git rev-parse HEAD >flashfloppy-$VER/COMMIT
echo debug >>flashfloppy-$VER/COMMIT
zip -r flashfloppy-$VER.zip flashfloppy-$VER
mv flashfloppy-$VER.zip _cidist/
- name: Upload artifacts
uses: actions/upload-artifact@v4
with:
name: FlashFloppy.CI.${{ steps.vars.outputs.sha_short }}
path: _cidist

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on:
push:
tags:
- 'v*.*'
name: Release
jobs:
build:
runs-on: ubuntu-22.04
steps:
- uses: actions/checkout@v4
- name: Set environment variables
id: vars
run: |
echo "ver=$(echo ${{ github.ref }} | sed -e's#.*/v##')" >> $GITHUB_OUTPUT
- name: Dependency packages (apt)
run: |
sudo apt update
sudo apt -y install git gcc-arm-none-eabi python3-pip srecord stm32flash zip unzip wget
- name: Dependency packages (pip)
run: python3 -m pip install --user crcmod intelhex
- name: Build release
run: |
export VER=${{ steps.vars.outputs.ver }}
make -j4 dist VER=$VER
mv out/flashfloppy-$VER.zip .
- name: Create Release
id: create_release
uses: ncipollo/release-action@v1
with:
tag: ${{ github.ref }}
token: ${{ secrets.GITHUB_TOKEN }}
name: FlashFloppy ${{ steps.vars.outputs.ver }}
body: "[**Release Notes:**](https://github.com/keirf/flashfloppy/blob/master/RELEASE_NOTES)"
draft: false
prerelease: false
artifacts: flashfloppy-${{ steps.vars.outputs.ver }}.zip
artifactContentType: application/zip

5
.gitignore vendored
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*~
*.orig
*.rej
/out
/ext

96
COPYING
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@ -1,87 +1,25 @@
All code is licensed as follows, with these exceptions:
- src/fatfs/*
- src/usb/stm32_usbh_msc/*
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
This is free and unencumbered software released into the public domain.
These are free and unencumbered hardware designs released into the
public domain.
Anyone is free to copy, modify, publish, use, compile, sell, or
distribute this software, either in source code form or as a compiled
binary, for any purpose, commercial or non-commercial, and by any
means.
Anyone is free to copy, modify, publish, use, manufacture, sell, or
distribute these designs, in any form, for any purpose, commercial or
non-commercial, and by any means.
In jurisdictions that recognize copyright laws, the author or authors
of this software dedicate any and all copyright interest in the
software to the public domain. We make this dedication for the benefit
of the public at large and to the detriment of our heirs and
of these hardware designs dedicate any and all copyright interest in
the designs to the public domain. We make this dedication for the
benefit of the public at large and to the detriment of our heirs and
successors. We intend this dedication to be an overt act of
relinquishment in perpetuity of all present and future rights to this
software under copyright law.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
THE HARDWARE DESIGNS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
DESIGNS OR THE USE OR OTHER DEALINGS IN THE DESIGNS.
For more information, please refer to <http://unlicense.org/>
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
All code within src/fatfs/* is licensed as follows:
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
Copyright (C) 2017, ChaN, all right reserved.
FatFs module is an open source software. Redistribution and use of FatFs in
source and binary forms, with or without modification, are permitted provided
that the following condition is met:
1. Redistributions of source code must retain the above copyright notice,
this condition and the following disclaimer.
This software is provided by the copyright holder and contributors "AS IS"
and any warranties related to this software are DISCLAIMED.
The copyright owner or contributors be NOT LIABLE for any damages caused
by use of this software.
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
All code within src/usb/stm32_usbh_msc/* is licensed as follows:
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
Copyright (C) 2015 STMicroelectronics International N.V.. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted, provided that the following conditions
are met:
1. Redistribution of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of STMicroelectronics nor the names of other
contributors to this software may be used to endorse or promote
products derived from this software without specific written
permission.
4. This software, including modifications and/or derivative works of
this software, must execute solely and exclusively on
microcontroller or microprocessor devices manufactured by or for
STMicroelectronics.
5. Redistribution and use of this software other than as permitted
under this license is void and will automatically terminate your
rights under this license.
THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY
LAW. IN NO EVENT SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
For more information, and the original software license that this
license is modified from, please refer to <http://unlicense.org/>

144
Makefile
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PROJ := flashfloppy
VER := $(shell git rev-parse --short HEAD)
export FW_VER := $(VER)
PYTHON := python3
export ROOT := $(CURDIR)
.PHONY: FORCE
.DEFAULT_GOAL := all
prod-%: FORCE
$(MAKE) target mcu=$* target=bootloader level=prod
$(MAKE) target mcu=$* target=floppy level=prod
$(MAKE) target mcu=$* target=quickdisk level=prod
$(MAKE) target mcu=$* target=bl_update level=prod
$(MAKE) target mcu=$* target=io_test level=prod
debug-%: FORCE
$(MAKE) target mcu=$* target=bootloader level=debug
$(MAKE) target mcu=$* target=floppy level=debug
$(MAKE) target mcu=$* target=quickdisk level=debug
$(MAKE) target mcu=$* target=bl_update level=debug
$(MAKE) target mcu=$* target=io_test level=debug
logfile-%: FORCE
$(MAKE) target mcu=$* target=bootloader level=logfile
$(MAKE) target mcu=$* target=floppy level=logfile
$(MAKE) target mcu=$* target=quickdisk level=logfile
all-%: FORCE prod-% debug-% logfile-% ;
all: FORCE all-stm32f105 all-at32f435 ;
clean: FORCE
rm -rf out
mrproper: FORCE clean
rm -rf ext
out: FORCE
+mkdir -p out/$(mcu)/$(level)/$(target)
target: FORCE out
$(MAKE) -C out/$(mcu)/$(level)/$(target) -f $(ROOT)/Rules.mk target.bin target.hex target.dfu $(mcu)=y $(level)=y $(target)=y
HXC_FF_URL := https://www.github.com/keirf/flashfloppy-hxc-file-selector
HXC_FF_URL := $(HXC_FF_URL)/releases/download
HXC_FF_VER := v9-FF
_legacy_dist: PROJ := FF_Gotek
_legacy_dist: FORCE
$(PYTHON) $(ROOT)/scripts/mk_update.py old \
$(t)/$(PROJ)-$(VER).upd \
out/$(mcu)/$(level)/floppy/target.bin & \
$(PYTHON) $(ROOT)/scripts/mk_update.py old \
$(t)/alt/bootloader/$(PROJ)-bootloader-$(VER).upd \
out/$(mcu)/$(level)/bl_update/target.bin & \
$(PYTHON) $(ROOT)/scripts/mk_update.py old \
$(t)/alt/io-test/$(PROJ)-io-test-$(VER).upd \
out/$(mcu)/$(level)/io_test/target.bin & \
$(PYTHON) $(ROOT)/scripts/mk_update.py old \
$(t)/alt/logfile/$(PROJ)-logfile-$(VER).upd \
out/$(mcu)/logfile/floppy/target.bin & \
$(PYTHON) $(ROOT)/scripts/mk_update.py old \
$(t)/alt/quickdisk/$(PROJ)-quickdisk-$(VER).upd \
out/$(mcu)/$(level)/quickdisk/target.bin & \
$(PYTHON) $(ROOT)/scripts/mk_update.py old \
$(t)/alt/quickdisk/logfile/$(PROJ)-quickdisk-logfile-$(VER).upd \
out/$(mcu)/logfile/quickdisk/target.bin & \
wait
_dist: FORCE
cd out/$(mcu)/$(level)/floppy; \
cp -a target.dfu $(t)/dfu/$(PROJ)-$(n)-$(VER).dfu; \
cp -a target.hex $(t)/hex/$(PROJ)-$(n)-$(VER).hex
$(PYTHON) $(ROOT)/scripts/mk_update.py new \
$(t)/$(PROJ)-$(VER).upd \
out/$(mcu)/$(level)/floppy/target.bin $(mcu) & \
$(PYTHON) $(ROOT)/scripts/mk_update.py new \
$(t)/alt/bootloader/$(PROJ)-bootloader-$(VER).upd \
out/$(mcu)/$(level)/bl_update/target.bin $(mcu) & \
$(PYTHON) $(ROOT)/scripts/mk_update.py new \
$(t)/alt/io-test/$(PROJ)-io-test-$(VER).upd \
out/$(mcu)/$(level)/io_test/target.bin $(mcu) & \
$(PYTHON) $(ROOT)/scripts/mk_update.py new \
$(t)/alt/logfile/$(PROJ)-logfile-$(VER).upd \
out/$(mcu)/logfile/floppy/target.bin $(mcu) & \
$(PYTHON) $(ROOT)/scripts/mk_update.py new \
$(t)/alt/quickdisk/$(PROJ)-quickdisk-$(VER).upd \
out/$(mcu)/$(level)/quickdisk/target.bin $(mcu) & \
$(PYTHON) $(ROOT)/scripts/mk_update.py new \
$(t)/alt/quickdisk/logfile/$(PROJ)-quickdisk-logfile-$(VER).upd \
out/$(mcu)/logfile/quickdisk/target.bin $(mcu) & \
wait
dist: level := prod
dist: t := $(ROOT)/out/$(PROJ)-$(VER)
dist: FORCE all
rm -rf out/$(PROJ)-*
mkdir -p $(t)/hex
mkdir -p $(t)/dfu
mkdir -p $(t)/alt/bootloader
mkdir -p $(t)/alt/logfile
mkdir -p $(t)/alt/io-test
mkdir -p $(t)/alt/quickdisk/logfile
$(MAKE) _legacy_dist mcu=stm32f105 level=$(level) t=$(t)
$(MAKE) _dist mcu=stm32f105 n=at415-st105 level=$(level) t=$(t)
$(MAKE) _dist mcu=at32f435 n=at435 level=$(level) t=$(t)
$(PYTHON) scripts/mk_qd.py --window=6.5 $(t)/alt/quickdisk/Blank.qd
cp -a COPYING $(t)/
cp -a README $(t)/
cp -a RELEASE_NOTES $(t)/
cp -a examples $(t)/
# Clive Drive is particularly fussy about QD timings.
$(PYTHON) scripts/mk_qd.py --window=6.4 --total=7.5 --round $(t)/examples/Host/Sinclair_ZX_Spectrum/Clive_Drive/CliveDrive_Blank.qd
[ -e ext/HxC_Compat_Mode-$(HXC_FF_VER).zip ] || \
(mkdir -p ext ; cd ext ; wget -q --show-progress $(HXC_FF_URL)/$(HXC_FF_VER)/HxC_Compat_Mode-$(HXC_FF_VER).zip ; rm -rf index.html)
(cd $(t) && unzip -q ../../ext/HxC_Compat_Mode-$(HXC_FF_VER).zip)
mkdir -p $(t)/scripts
cp -a scripts/edsk* $(t)/scripts/
cp -a scripts/mk_hfe.py $(t)/scripts/
cd out && zip -r $(PROJ)-$(VER).zip $(PROJ)-$(VER)
BAUD=115200
DEV=/dev/ttyUSB0
SUDO=sudo
STM32FLASH=stm32flash
T=out/$(target)/target.hex
ocd: FORCE all
$(PYTHON) scripts/openocd/flash.py $(T)
flash: FORCE all
$(SUDO) $(STM32FLASH) -b $(BAUD) -w $(T) $(DEV)
start: FORCE
$(SUDO) $(STM32FLASH) -b $(BAUD) -g 0 $(DEV)
serial: FORCE
$(SUDO) miniterm.py $(DEV) 3000000

77
README
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FlashFloppy
===========
Keir Fraser <keir.xen@gmail.com>
https://github.com/keirf/flashfloppy
FlashFloppy [hardware]
======================
This distribution contains FlashFloppy custom firmware for Gotek and
Gotek-compatible hardware.
KiCad PCB designs for the FlashFloppy project.
FlashFloppy documentation and downloads:
https://github.com/keirf/flashfloppy/wiki/
Supported Microcontrollers
--------------------------
FlashFloppy supports two types of STM32-like microcontroller:
STM32F105 (and the compatible AT32F415)
- 72MHz Cortex-M3, 128kB Flash, 64kB RAM (AT32F415: 32kB RAM)
AT32F435
- 288MHz Cortex-M4, 256kB Flash, 384kB RAM
If you want to know which type of MCU you have, you can open your Gotek and
read the writing on the square chip on your Gotek PCB.
Firmware Programming
--------------------
If programming a factory-fresh Gotek running factory firmware, you will need
to program a HEX or DFU firmware file as explained in the wiki, linked above.
These files are located in the hex/ and dfu/ folders respectively, and you
must use the correct file for your microcontroller:
STM32F105, AT32F415
- Use file "dfu/flashfloppy-at415-st105-<ver>.dfu" (or .hex equivalent)
AT32F435
- Use file "dfu/flashfloppy-at435-<ver>.dfu" (or .hex equivalent)
Firmware Update
---------------
Once FlashFloppy has been flashed to a device (using a HEX or DFU file),
further updates can be made via an Update file on a USB drive, as described
in the wiki.
To support older versions of the FlashFloppy bootloader, two types of
Update file are included in the distribution, distinguishable by name:
FF_Gotek-*.upd: Legacy Update file
- All STM32F105/AT32F415 devices
flashfloppy-*.upd: Universal Update file
- All AT32F435 devices
- STM32F105/AT32F415 devices running a recent FlashFloppy bootloader
Each update format will only work with a device (and FlashFloppy bootloader)
that supports it. If you are unsure which to use, it is okay to copy both
Update file types to your USB drive: the bootloader will correctly load just
one of the Update file types that it supports.
Alternatively try one Update file at a time, and switch to the other type if
you see error E01 on the Gotek display.
Alternative Firmwares
---------------------
In the alt/ folder you will find (pairs of) Update files implementing
alternative firmwares. Most users can ignore these, and use only the
Update files in the root of the distribution.
The alternative firmwares include:
* alt/bootloader: Updates your Gotek bootloader
- WARNING: Proceed with caution. Read the Firmware Update page on the wiki.
* alt/io-test: Test your Gotek I/O pins if you suspect a hardware fault
* alt/quickdisk: QuickDisk emulation (see the wiki)
- If you don't know what QuickDisk is, you don't need this firmware.
* alt/logile: Firmware with debug logging to FFLOG.TXT on the USB drive
- Useful only for fault finding. Not for general use.
Redistribution
--------------
Source code, and all binary releases, are freely redistributable in
any form. Please see the the COPYING file included in this
distribution.
These designs are public domain (see the COPYING file).

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# FlashFloppy
*The #1 floppy emulator.*
![CI Badge][ci-badge]
![Downloads Badge][downloads-badge]
![Version Badge][version-badge]
<img src="https://raw.githubusercontent.com/wiki/keirf/flashfloppy/assets/banner.jpg">
**FlashFloppy** is a floppy-drive emulator for the ubiquitous
[**Gotek**][Gotek-Compatibility] hardware. Connect to retro machines just
like a real floppy drive but use disk images on a modern USB stick!
- Say goodbye to old and unreliable floppy disks
- Download and play from the disk-image archives for your retro machines
**FlashFloppy** is the **#1 floppy emulator**:
- Supports a [massive range][Host-Platforms] of retro computers, synths, and machinery
- Directly reads and writes [many image formats][Image-Formats]
- [Flexible track layout][Track-Layouts] for Raw Sector Images
- [Extremely configurable][FF.CFG-Configuration-File]
**FlashFloppy** is **Free and Open-Source Software**.
## Download
- [**Download FlashFloppy**][Downloads]
## Documentation
- [**Read the GitHub Wiki**](https://github.com/keirf/flashfloppy/wiki)
## Redistribution
Most code is public domain; the rest is MIT/BSD or Open Source friendly
(see the [COPYING](COPYING) file).
The source code, and all binary releases, are freely redistributable
in any form. Because FlashFloppy includes third-party code, you should
include or link to the [COPYING](COPYING) file in any redistribution.
This means, for example, you are free to sell and profit from Gotek
devices programmed with a binary release of FlashFloppy. However **at
a minimum** you should incorporate or link to the [COPYING](COPYING)
file on your selling page. For example:
- FlashFloppy is free software. For more information see the
[license](COPYING).
[Gotek-Compatibility]: https://github.com/keirf/flashfloppy/wiki/Gotek-Compatibility
[Host-Platforms]: https://github.com/keirf/flashfloppy/wiki/Host-Platforms
[Image-Formats]: https://github.com/keirf/flashfloppy/wiki/Image-Formats
[Track-Layouts]: https://github.com/keirf/flashfloppy/wiki/Track-Layouts
[FF.CFG-Configuration-File]: https://github.com/keirf/flashfloppy/wiki/FF.CFG-Configuration-File
[Downloads]: https://github.com/keirf/flashfloppy/wiki/Downloads
[ci-badge]: https://github.com/keirf/flashfloppy/workflows/CI/badge.svg
[downloads-badge]: https://img.shields.io/github/downloads/keirf/flashfloppy/total
[version-badge]: https://img.shields.io/github/v/release/keirf/flashfloppy

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************************************
** FlashFloppy Release Notes
** Keir Fraser <keir.xen@gmail.com>
************************************
** v3.42 - 11 January 2024
- HFEv3: Various read/write improvements
- WDATA: Merge short write pulses, and apply de-jitter/precomp
- IMG, EDSK: Stream large sector writes to flash
** v3.41 - 14 July 2023
- AT32F415: Fix timer handling since clock speed increase (v3.39).
- LCD: Faster power-on initialisation. Don't wait for display to clear.
** v3.40 - 27 June 2023
- XDF: Fix writes to side 1 of XDF disk images
- HFE: Better handling of long No Flux Areas
- QuickDisk: Reduce motor spinup time to 1 second (previously 2 seconds)
- LCD: Completely blank display when backlight is off
** v3.39 - 1 March 2023
- AT32F415: Run this MCU at 144MHz (previously 72MHz).
- HFE: Fix HFEv3 support. Support Dungeon Master & Chaos Strikes Back.
- IMG.CFG: Support mixed sector sizes per track (Ensoniq Mirage etc).
- IMG.CFG: New option img_bps= allows padding of short sectors in IMG files.
- FF.CFG: New option notify-volume= for notifying on insert/eject events.
- FF.CFG: New OLED display sub-option 'hflip' horizontally flips display.
- Various other small fixes.
** v3.38 - 4 December 2022
- AT32F435: Fix RDATA release on drive deassert
- SF7: Support Sega SF-7000 *.SF7 images
** v3.37 - 20 October 2022
- Amiga: Fix firmware crash when mounting read-only disk image
- Since v3.36 when interface=amiga and motor-delay= is configured
- Amiga: Respect MOTOR when motor-delay= is configured and disk ejected
- Previously the MOTOR signal was ignored when no disk inserted
** v3.36 - 10 October 2022
- AT32F435: Fix SD card handling on boards which support it
- FF.CFG, OSD: New options osd-columns= and osd-display-order=
- Amiga: Improved pin 34 ID/RDY emulation
- Requires AT32F435 MCU and MOR jumper strap
- Requires FF.CFG options: interface=amiga, motor-delay=500
** v3.35 - 4 August 2022
- AT32F435: Fix Quick Disk firmware
** v3.34 - 4 July 2022
- AT32F435: Fix startup to MCU spec (LDO voltage, Flash clock divisor)
- AT32F435: Cache HFE and QD image data, since there is plenty of RAM
- Allow rotary encoder on pins PA13/PA14 on any board except QFN32 MCU
- io-test: Fix io-test alt firmware for modern Gotek boards
** v3.33 - 20 June 2022
- Support new board SFRKC30.AT4.35
- Support new chip AT32F435 (288MHz M4, 256kB+ Flash, 384kB SRAM)
- New UPD file format and explanatory README: Please read!
** v3.32 - 28 May 2022
- Fix 'oled-font=8x16' option (broken in release 3.31)
- Improve drive-select ISR performance
- Fixes issues with fast Amiga accelerators
** v3.31 - 23 May 2022
- Fix Gotek drive detection with Amiga Kickstart ROM v3.2.1
- QD: FF.CFG alternative to JC jumper (no JC on SFRKC30.AT2 model)
- Place "interface=ibmpc" in FF.CFG
- OLED: New "-slow" modifier to slow down I2C bus for glitchy displays
- AUTOBOOT: Disallow writes to MBR, which can trash the USB drive
** v3.30 - 26 January 2022
- IMG.CFG: New option step= allows to specify double-step operation
- FF.CFG: New option max-cyl= allows limiting head-step range
- SFRKC30 Gotek Models: Improved rotary support on new "KC30" header
** v3.29 - 2 October 2021
- Support new Gotek board SFRKC30.AT2 using AT32F415KBU7-4 (QFN32)
- Support LQFP64 AT32F415RxT7 chips on existing "Enhanced Gotek" boards
- IMG: Fix default GAP2 for ED (eg. 2.88M) images
- IMG.CFG: New parameter gap2= to set Post-ID Gap value
** v3.28 - 2 July 2021
- Gotek model SFR1M44-U100LQD: Fix occasional rotary encoder issue
- This model uses SFRKC40.AT4.7 PCB with encoder on new pin header
- Rotary encoder would occasionally not be detected at power on
** v3.27 - 2 July 2021
- Fix v3.26 regression in button handling for GOEX hardware
** v3.26 - 24 June 2021
- Support new Gotek board SFRKC30.AT4.7
** v3.25 - 25 April 2021
- IMG, DSK: Fix track formatting on Artery microcontrollers
- Firmware would crash during format operations
** v3.24 - 15 April 2021
- Beta support for new Artery microcontrollers used on latest Gotek models
- See the wiki for more details
- https://github.com/keirf/FlashFloppy/wiki/Gotek-Compatibility
- IMG: Fix skew/interleave on MSDMF (1.68M) images
** v3.23 - 31 December 2020
- OLED/LCD: Fix missing folder name display row when inserting USB drive
- IMG.CFG: New examples for Roland, Sinclair QL, Kaypro
- IMG.CFG: Now supported in HxC-compat and indexed navigation modes
- IMG: Fix default 8-inch single-density data rate
- IMG, HFE: Support 255-cylinder image files
** v3.22 - 17 November 2020
- Fix various crashes when mounting a Flash drive with stale IMAGE_A.CFG
- FAT FS: Support filesystems for which cluster table is "too small"
- Windows and Linux will mount these volumes, thus so should we
- FF.CFG: New OLED display-type option: -inverse
- Reverse-video effect (black text on white background)
- FF.CFG: display-order= option affects normal display modes only
- Ignored in all banner and menu modes, to avoid jumbled display
- FF.CFG: Fix display-type parsing for OLED-specific options
- Ignore them unless an OLED display is explicitly configured
** v3.21 - 26 October 2020
- Support GUID Partition Table (GPT)
- Now support: GPT, MBR, and no partition table
- FatFS: Updated to R0.14, patchlevel 2
** v3.20 - 15 October 2020
- Eject Menu: Replace Clone with Copy/Paste
- Allows an image to be copied to a different folder
- Navigation mode: Copy to selected folder by holding Select for 1.5s
- FF.CFG: New option "rotary=v2" to use v2.x encoder logic
- Fixes a very few encoders which don't work with stricter v3.x logic
- FF.CFG: New option "twobutton-action=htu"
- Implements hundreds/tens/units button actions of the factory firmware
- IMG.CFG: New parameters:
- tracks: Track-scoped parameter lists (geometry can vary by track)
- h: Override default IDAM Head field
- gap4a: Override default post-index track gap
- IMG.CFG: Tag names are now case insensitive
- IMG.CFG: Tag by file size and/or name
- IMG.CFG: Implement some example configurations under examples/Host/
- IMG: Fix some of the more bizarre default track geometries
** v3.19 - 28 September 2020
- Amiga, ADF: Fix X-Copy verified writes with out-of-order sectors
- Remember the latest written sector order for current cylinder
- Forgotten after head step or disk eject but sufficient for X-Copy
- FF.CFG: New interface= options 'jppc' and 'jppc-hdout'
- jppc: pin2=nc, pin34=RDY, Japanese PC standard
- jppc-hdout: As above but pin2=HD_OUT, similar to ibmpc-hdout
- akai-s950 is retained as a legacy alias for jppc-hdout
** v3.18 - 23 September 2020
- OLED/LCD: Fix potential minor display corruption
- Only seen with 128x64 OLED displays, bottom right corner
- alt/logfile: Write FFLOG.TXT to correct folder (root or FF/)
- IMG, DSK: Various cleanups to sector-write handling
** v3.17 - 17 September 2020
- DSK: Fix infinite loop when trying to open a bad DSK image file
- Quick Disk: Restart read stream immediately after a write
- QD support now works on Sharp MZ-800
- IMG.CFG: Remove [default] stanza from example config
- Users copying the example file will no longer break their IMG files
** v3.16 - 22 August 2020
- Rotary encoder: Velocity curve during image navigation
- Fast spin of the encoder skips multiple entries per click
- LCD/OLED/OSD: Fix image name when display is wider than 24 characters
- HFE: Fix double-step HFE images (broken since v3.14a)
- HxC Compat: Strip filename extension from image name display row
** v3.15 - 23 July 2020
- New stable release series
- Improve rotary encoder robustness by sampling at 4x higher rate
** v3.14a - 15 July 2020
- Properly implement non-existent tracks as empty / unformatted
- In particular this avoids writing tracks beyond end of disk image
- See issue #309: Could corrupt HFE images
- Akai IMG: Implement track skew (faster access and fixes Oberheim DPX)
- Speaker: Rate-limit step pulses at the speaker
- Avoids high-freq chirp in Direct Access mode and Gotek-aware fast loaders
- HxC Compat, v9-FF:
- Atari ST keymap is now QWERTY
- Remove unused settings from drive setup menu
- Fix the search/filter box (Esc and Backspace keys)
** v3.13a - 13 March 2020
- FF.CFG: New option 'write-drain=eot'
- Fixes writes to Gotek on Amstrad PPC series (#320)
- FF.CFG: New option 'display-on-activity=sel'
- Turns on display whenever the Gotek drive is selected by host
- HFE: Respect double-step header flag
- Fixes 180k disk images on Amstrad PCW (#318)
** v3.12a - 7 February 2020
- IMG: Support IBM 3174 1.2M and 2.4M formats (host=ibm-3174)
- HxC: Fix HxC mode with no file selector (AUTOBOOT.HFE)
- FF OSD: Fix dual-display operation with slower OLED
- Wait for OLED to initialise when display-type=oled...
** v3.11a - 30 December 2019
- LCD/OLED: Fix subfolder name, as shown in 3- & 4-row displays
- Subfolder wasn't updated correctly when moving to parent (..) folder
** v3.10a - 28 December 2019
- Bootloader: Wait for buttons to be pressed then released...
- ...before starting firmware update process
- Avoids an infinite loop when reprogramming Bootloader itself
** v3.9a - 27 December 2019
- IMG: Fix density-select pin output for HD images
- Fixes 'pin02=dens' and 'interface=ibmpc-hdout'
- Bug has existed since v2.2a
- Rotary Encoder: Improve tracking
- Higher frequency, and better debounce algorithm
** v3.8a - 10 December 2019
- USB: Fix buffer overflow when parsing string descriptors
- Fixes crash with recent SanDisk Ultra Fit drives
- HxC Compat, v8-FF: Fixes startup crash on Atari ST
- Amiga: Fixes for "interface = amiga" setting
- TR-DOS (TRD): Fix geometry when TR-DOS header is incomplete
- Quick Disk: Larger read/write window in default blank image
- GCC9 build fixes
** v3.7a - 11 November 2019
- Quick Disk Bug Fixes
- Fix write offsets and lengths within QD track
- Filter ADF images from navigator: only QD images supported
- Extra logging in FFLOG.TXT for debug purposes
- Amiga AutoSwap new title: Gobliiiins
- Thanks to Arkadiusz Makarenko!
- https://github.com/keirf/flashfloppy-autoswap/wiki/Downloads
** v3.6a - 13 October 2019
- Quick Disk Initial Release
- New firmware and blank QD image in alt/quickdisk
- Documentation in the Wiki
- Update HxC Compat to v7-FF
- Fix failure when booted on unmodded A1200 ESCOM boards
** v3.5a - 9 October 2019
- New Main Menu: Press Prev/Next or Select with no Flash drive inserted
- Factory Reset, Firmware Update, OSD Config
- OSD: Must be updated to latest version: v1.7 or later!
- OSD: Receive Gotek button commands via I2C
- OSD: Default to 40 columns if no other display is connected
- TR-DOS (TRD): Fix geometry detection based on TR-DOS header
** v3.4a - 25 September 2019
- FF OSD support
- Bus sharing with existing LCD/OLED display
- Gotek buttons can be remoted to FF OSD for OSD configuration
** v3.3a - 8 July 2019
- FF.CFG: New Disk-Change Reset option: chgrst=delay-N
- Automatically clears the DSKCHG signal Nx0.5s after disk insertion
- chgrst=delay-3 fixes Disk Change on Ensoniq EPS synths
- Change head-step signal handling to reduce interrupt rate
- OLED/LCD: Fix current-folder display line for image-on-startup=init|static
- image-on-startup=static: The static image is now specified in INIT_A.CFG
** v3.2a - 25 June 2019
- OLED: New default layout for 128x64 displays
- LCD: Support 20x4 character displays
- LCD: Row ordering is configurable
- FF.CFG: Rename oled-text= to display-order= to reflect this
- Eject menu: Confirmation required for Delete/Clone operations
- Trackball: Reduce jitteriness by adding simple inertia
** v3.1a - 13 June 2019
- OLED: Text height and content can be configured (FF.CFG:oled-text=)
- New default for 128x64 displays presents a new third text row
- LCD/OLED: Present an action menu when an image is ejected
- Includes Clone and Delete Image operations
** v3.0a - 10 June 2019
- Disk Change Reset: Emulate explicit Reset signal of certain vintage drives
- Requires a hardware modification and FF.CFG: chgrst=pa14
- Support ZHONGJY_TECH 2.23" 128x32 displays based on SSD1305 controller
- FF.CFG: display-type=oled-128x32-ztech
** v2.13 - 7 June 2019
- HFE: Fix read buffering error
- Update HxC Compat to v6-FF
- More robust error checking on writes
** v2.12 - 2 June 2019
- HFEv3: Support flaky/weak bytes
- LCD/OLED: Improve power-on initialisation robustness
- Roland: Direct support for *.OUT images
- IO-Test: New alternative firmware to test Gotek I/O pins
- https://github.com/keirf/flashfloppy/wiki/Testing-IO-Pins
** v2.11a - 23 May 2019
- Simpler bootloader update process with all-in-one update file
- Update firmware via SD card (enhanced Goteks with SD card slot)
- FF.CFG: sort-priority= to prioritise folders vs files during navigation
- Default: Folders are listed before files
** v2.10a - 20 May 2019
- Fix breakages since v2.2a:
- host=acorn: *.ADF handling
- host=tandy-coco: *.DSK handling
** v2.9a - 17 May 2019
- FF.CFG: New option motor-delay= to provide emulation of motor behaviour
- Requires modification of a standard Gotek PCB (see Wiki: Hardware Mods)
- Debug logging: An alternative firmware is provided to log to FFLOG.TXT
- Find the alternative update file in alt/logfile/
- Use this for personal interest or as directed by me for debugging
- Not for general use!
- IMG/DSK: Better RAM handling (more space for mass-storage block cache)
- Code optimisation (MFM decode speeded up 4x)
- Small fix to generate INDEX signal when starting read near end of track
** v2.8a - 10 May 2019
- DSK, IMG: Fix small error in generated MFM data
- Increase write buffer to 32kB, enough for a full high-density track
- More reliable whole-track writes, especially to HFE images
** v2.7a - 23 April 2019
- Sort folders into alphabetical order during direct navigation
- FF.CFG: folder-sort= to modify this new default behaviour
- Fix memory corruption issues (stack overflow)
- ATR: Interleave sectors for best performance over slow SIO interface
** v2.6a - 14 April 2019
- Fix feature breakages in v2.5a
- SSD/DSD/TRD auto-extend feature
- FF.CFG: eject-on-startup=yes feature
- Update HxC Compat to v5-FF
** v2.5a - 12 April 2019
- Fragment-offsets cache implemented at the FAT filesystem layer
- Block cache implemented at the mass-storage volume layer
- Faster image selection/navigation in large folders
- Improved reliability in image handling (reduced access latencies)
- USB stick will usually stop flashing when drive is not being accessed!
- FF.CFG: New rotary input options
- 'trackball': Blackberry-style trackball
- 'buttons': Push-to-ground Prev/Next buttons
** v2.4a - 9 April 2019
- This release fixes many raw track formats (SSD, DSD, OPD, VDK, ...)
- Thanks to John Gray for bug report, and testing!
- RAW: Fix FM track generation
- FM and IAM flags not plumbed through from front-end image handlers
- RAW: Fix interleaved/skewed track generation
- Data fetch not loading sectors from image file in the right order
** v2.3a - 8 April 2019
- OLED: Auto-detect SSD1306 vs SH1106 display controller
- FF.CFG: 'display-type = ...-sh1106' is now redundant and ignored
- ATR: Fix readability of downloaded ATR images
- Invert data as it is read/written, mirroring the standard XF551 interface
- Thanks to Piotr for this report (using his XF551 clone)
** v2.2a - 5 April 2019
- New image types supported:
- XDF: 3.5" HD eXtended Disk Format (1840kB)
- ATR: Atari 8-bit
- 7-Seg LED: Improved track display.
- Remove option 'led-trk' from FF.CFG. Track display mode is always on.
- OLED: Fix horizontal offset on SH1106 128x32 displays
- IMG.CFG: 'id' parameter simplified; 'sskew' renamed 'hskew' (head skew)
** v2.1a - 26 March 2019
- IMG.CFG: Allow up to 256 sectors per track
- IMG.CFG: Split skew into per-cylinder and per-side values (cskew/sskew)
- IMG.CFG: Introduce image-file layout option (file-layout=<csv-list>):
- sequential,interleaved: Cylinder-first or side-first track ordering
- reverse-sideN: Side-N cylinders in reverse order (high to low) (N=0,1)
- sides-swapped: Ordering of disk sides is swapped in the image file
- 7-Segment LED: Display track number when an image is mounted
- FF.CFG: "display-type = led-trk"
- Displays slot number as usual during image selection/navigation
- First button press reverts to slot display; Next press begins navigation
- LCD/OLED: Display full cylinder number on displays wider than 16 columns
- Previously truncated at cylinder 99
** v2.0a - 14 March 2019
- IMG: Allow geometry to be manually configured in new file IMG.CFG
- See examples/IMG.CFG for documentation
- Multiple formats can be defined; distinguished by image name tags
- IMG: Support FM mode with Index Address Mark (IAM)
- IMG: Support auto-configuration of GAP3 (post data gap) when using IMG.CFG
- FF.CFG: Fix parsing of comma-separated values
- Indexed Mode: Allow arbitrary image name after "DSKAnnnn" prefix
- eg. DSKA0000_myimage.img, DSKA0002_another.adf
- Indexed Mode: Allow the "DSKA" prefix to be changed (FF.CFG:indexed-prefix=)
** v1.0 - 4 February 2019
- Game/demo AutoSwap-disks feature
- No manual disk swapping, at all!
- Requires patching of host software titles
- Amiga titles so far (github:keirf/flashfloppy-autoswap):
- Beneath a Steel Sky
- Indiana Jones and the Fate of Atlantis
- The Secret of Monkey Island
- Monkey Island 2: LeChuck's Revenge
- FF.CFG: New OLED display-type sib-option "-narrower"
- 16-character-wide display (c.w. "-narrow" 18-char-wide)
- PC98: Direct support for HDM image files
- HxC Compat: Small fixes to Amiga file selector
** v0.15 - 8 January 2019
- Support Enhanced Gotek with SD card connector
- Board requirements are in the wiki (Hardware Mods)
- USB drive, if inserted, takes priority over SD card
- SD card is not supported for firmware update
** v0.14 - 7 December 2018
- Direct Access: Fix broken sector writes (USB corruption)
- Primarily affected the CPC/ST file selectors (not Amiga)
- Broken since v0.12
** v0.13 - 2 December 2018
- IMG: Support Casio FZ-1 (host=casio)
- IMG: Support SC Prophet 3000 (host=akai)
- Display D-A/DA/"Host Direct Access" in host file selector
** v0.12 - 27 November 2018
- IMG: Support Nascom 1 & 2 (host=nascom)
- Direct Access: Support FM/SD access on cylinder 254
- Direct Access: Support CMD_SELECT_IMAGE (cmd #4)
- HxC Compat: Fix occasional "LBA Change Test Failed" error
- Improvements to ribbon-upside-down checks
** v0.11 - 1 November 2018
- Detect and report upside-down data ribbon cable
- FF.CFG: Configurable OLED brightness/contrast (oled-contrast=)
- FF.CFG: Configurable head settle time (head-settle-ms=)
- FF.CFG: Fix comma-separated-list parsing (eg. rotary=)
** v0.10 - 30 October 2018
- FF.CFG: Allow up/down inputs to be reversed
- Reverse original two buttons (twobutton-action=reverse)
- Reverse rotary encoder direction (rotary=reverse)
- Modified version numbering scheme and remove alpha status
** v0.9.31a - 28 October 2018
- HFE: Sanity-check critical header fields
- FF.CFG: Better docs on pin02/pin34 options
- HxC Compat: File selector updates
** v0.9.30a - 9 October 2018
- TI99: Fix V9T9/DSK double-sided images
- HxC Compat: Enter slot-based mode even with no AUTOBOOT.HFE
- HFE: Support HFEv2 images
** v0.9.29a - 17 September 2018
- New and improved image handlers:
- ST: Fix 80-cyl single-sided images
- IMG: Kaypro (host=kaypro)
- IMG: MSX fix 40-cyl/5.25" formats (host=msx)
- IMG: PC-DOS fix missing IAM (host=pc-dos)
- IMG: All: Support long sectors (>1024k)
- Indexed mode: Don't require DSKA0000 image
** v0.9.28a - 26 August 2018
- New image types supported:
- IMG: Fluke 9100 (host=fluke)
- MBD: Spectrum MB02
- LCD/OLED: Display folder names in brackets
** v0.9.27a - 27 July 2018
- Direct Navigation: Fix hidden-file and dot-file filtering
- Direct Navigation: Filter __MACOSX/ resource-fork folders
** v0.9.26a - 24 July 2018
- DSK (CPC): More fixes for copy-protected tracks
- New image types supported:
- JVC, DSK: Tandy Coco (host=tandy-coco)
- VDK: Dragon
** v0.9.25a - 18 July 2018
- DSK (Spectrum, CPC, Sam Coupe): Fix tracks with little or no data in them
- FF.CFG: New options pin02= and pin34= allow precise interface configuration
** v0.9.24a - 9 July 2018
- DSK (Spectrum, CPC, Sam Coupe): Bug fixes. Please upgrade!
** v0.9.23a - 6 July 2018
- DSK (Spectrum, CPC): Support weak-data copy protection
- Used on most of the top commercial titles
- OLED: Utilise all rows on 128x64 displays
- LCD: Support up to 40x2 displays
- SSD, DSD (BBC): Add correct sector skew across tracks
- IMG: 1680kB DMF has 2:1 sector interleave
** v0.9.22a - 20 June 2018
- OLED: Support SH1106 controller (1.3-inch displays)
- FF.CFG: display-type = oled-128x64-sh1106
- Support a wider range of rotary encoders
- FF.CFG: rotary = quarter | half | full
- New image types supported:
- D81: Commodore 64 1581
- IMG: DEC RX33, RX50 (host=dec)
** v0.9.21a - 11 June 2018
- New default 6x13 font (Codec, by Chris Cannam)
- IMG: Support MSX (host=msx)
- Accelerate the stock Gotek buttons when using a rotary encoder
- FF.CFG: "twobutton-action = rotary-fast"
- HxC-Compat File Selectors:
- New font on Amiga and Atari ST
- Faster folder navigation on Amiga
** v0.9.20a - 6 June 2018
- New image types supported:
- IMG: UKNC/DVK (Soviet PDP-11 clones) (host=uknc)
- IMG/FDI: NEC PC-98 (host=pc98)
- IMG: Common retro IBM/PC formats work out of the box
- IMG: Detect disk layout from PC DOS BPB (host=pc-dos)
- Auto-extend truncated images (SSD, DSD, TRD images only)
- "extend-image=no" disables this feature
** v0.9.19a - 1 May 2018
- Amiga: Support high-density disk images
- ADF: 1760kB images
- Generate HD-ID pattern on pin 34 (interface=amiga)
- DSK: Fixes for Sam Coupe, and others with long tracks
** v0.9.18a - 19 April 2018
- Fix HxC compatibility mode ("LBA change test failed")
- SDU: Improve geometry detection
- More bug fixes to read-data ring-buffer handling
- LED 888 Display: Show firmware version when right/up button pressed
- LCD/OLED: When browsing through images, reset scroll to start of each file
** v0.9.17a - 17 April 2018
- New image types supported:
- Acorn DFS SSD/DSD
- Acorn ADFS 'S' (160kB)
- Akai 800kB (host=akai)
- Memotech IMG (host=memotech)
- SAB Diskette Utility (SDU)
- TI-99/4A DSK/V9T9 (host=ti99)
- New interface types supported:
- Akai S950 (interface=akai-s950)
- Bug fixes to read-data ring-buffer handling
- HFE: Improve write performance (batch reads/writes up to 8 blocks)
- OLED: Increase default initialisation probe to 3s
- USB: Respect volume write-protect status
** v0.9.16a - 16 March 2018
- Support ADFS D/E/F images (suffix *.ADF, FF.CFG: host=acorn)
- Direct Access: Fix sector data CRCs
- Reliability improvements for Acorn systems (index-suppression=no)
- Rearrange floppy read/write buffering to avoid corruptions
** v0.9.15a - 9 March 2018
- UI: Fix subfolder navigation when returning to parent folder (#66)
- OLED: Auto-detect OLED displays at I2C address 0x3d
- ST: Mimic TOS by applying track skew to ST image files (#44)
- 7-Seg LED: Allow write protection to be toggled as on LCD/OLED
- Support Ensoniq DD/HD custom IMG formats (host=ensoniq)
- Support IBM PC interface with density select (interface=ibmpc-hdout)
- Direct Access: Support track with fewer than 8 data sectors (#62)
** v0.9.14a - 4 March 2018
- Fix write pipeline: record track number for delayed write processing
- General Music (GEM): New host option "host=gem" for direct IMG support
- Direct support for Spectrum Opus Discovery (OPD) image files
- HFE, ADF: Batch writeback to the USB drive where possible
- FF.CFG: Replace "index-during-seek" with "index-suppression"
- Direct Access: Restart read at correct track position after a write
** v0.9.13a - 1 March 2018
- HFE: Emulate non-standard drive speeds (eg. Sony 600 RPM drive)
- HFE: Fix single-sector writes (broken since v0.9.8a)
- Direct Access: Support up to 64-sector track (Atari ST HxC Mount)
- Direct support for Spectrum TR-DOS (TRD) image files
** v0.9.12a - 27 February 2018
- LCD/OLED: Long filenames scroll during navigation
- LCD/OLED: Make filename scrolling more configurable
- FF.CFG: {nav,display}-scroll-{rate,pause}
- Direct navigation: ".." returns to subfolder position within parent
- Fix head-seek settle time emulation
- ADF: Generate longer tracks, like a real Amiga would
** v0.9.11a - 23 February 2018
- Fix Direct-Acesss mode (as used by HxC Autoboot, broken in v0.9.10a)
** v0.9.10a - 22 February 2018
- New default OLED font 6x13 displays more text per line
- 7x16 font removed
- 8x16 font MAY be removed, let me know if you use it!!
- Narrow OLED view (default Gotek display cutout) supported
- FF.CFG: display-type = oled-128x32-narrow
- All images can be write-protected by default
- FF.CFG: write-protect = yes
- Write-protect switchable by holding eject for 2 seconds
** v0.9.9a - 19 February 2018
- Fix write problems present in v0.9.8a (issue #53)
- Support rotary encoders with proper Gray code output
- FF.CFG: rotary = none | simple | gray
** v0.9.8a - 8 February 2018
- Pipelined writes
- New writes are buffered while older ones are written to the USB drive
- More reliable write/format/disk-copy operation with slower USB drives
- FF.CFG: Allow OLED display to be rotated 180 degrees (upside down)
- display-type = oled-128x32-rotate
- FF.CFG: Support BBC Micro with 8271 controller
- Index pulses must continue during seek (index-during-seek = yes)
- Index pulses must not be delayed by seek (track-change = realtime)
** v0.9.7a - 29 January 2018
- Performance & reliability improvements (eg. Github issues #35, #44):
- Sync data read after writes, prevents host missing next sector
- FF.CFG: Sync data read after track change (track-change=instant)
- Prevents host missing the first sector
- Old behaviour is configurable (track-change=realtime)
- FF.CFG: host=akai, support Akai synths with 1.6MB HD IMG files
** v0.9.6a - 17 January 2018
- USB: Fix power-on initialisation for some USB sticks
- FAT: Write-protect image files marked with read-only attribute
- ST: Support 11-sector .ST images
** v0.9.5a - 1 December 2017
- FF.CFG: New button assignment for rotary-encoder setup
- twobutton-action = rotary
- FF.CFG: Allow navigation mode to be specified
- nav-mode = native | indexed | default
** v0.9.4a - 30 November 2017
- Automatic support for crippled 'diymore' OLED displays
- FF.CFG: New option display-probe-ms (replaces startup-delay)
- FF.CFG: New option twobutton-action allows eject on two-button press
** v0.9.3a - 22 November 2017
- DSK: Fix disk write handling
- HFE: Improve read speed for HD images, reduce buffer underruns
** v0.9.2a - 21 November 2017
- DSK: Improve handling of per-sector status codes
- Fix bugs in front-end file handling & folder navigation
** v0.9.1a - 16 November 2017
- Acorn ADFS image support (ADM, ADL) [Daniel Jameson]
- Better detection of DSK image type (CPC-DSK vs raw sector file)
** v0.9.0a - 15 November 2017
** Amstrad CPC / Spectrum +3 DSK support
- DSK directly supported for read and write. Please report any issues!
- Improved error reporting
- New FF.CFG option "startup-delay = N"
-------------------------------------------------------------------------
** v0.8.8a - 7 November 2017
- Better error reporting (filesystem, media, power, image handling)
- Optional feature enhancements for Gotek clones
- Third button (select) may be used instead of prev/next for firmware
update and factory reset
** v0.8.7a - 17 October 2017
- Start in ejected state if button pressed or image previously
ejected (when "image-on-startup = last")
- Divide the configuration flash page into multiple slots to
reduce the number of erase cycles when FF.CFG is repeatedly
modified
** v0.8.6a - 13 October 2017
- New FF.CFG option image-on-startup
- Rename LASTDISK.IDX to IMAGE_A.CFG
- If image-on-startup is a folder, go directly into image selector
** v0.8.5a - 13 October 2017
- Cache FF.CFG values in Flash memory for next power on, replacing
'factory defaults'. Restore defaults by pressing both buttons.
- Glitch filter for SIDE-select signal (Kingstener)
- Small improvements to FF.CFG option and value naming
** v0.8.4a - 11 October 2017
- Bootloader OLED Display Fix (display was not enabled in update mode)
- Integrate 7x16 OLED font into main build, configurable in FF.CFG
** v0.8.3a - 10 October 2017
- Always search for HXCSDFE.CFG/AUTOBOOT.HFE in root folder, even
when FF/ subfolder exists
** v0.8.2a - 10 October 2017
- Parse FF.CFG file (see examples/FF.CFG for options)
- LCD/OLED: Don't display bogus 'folder depth' in Autoboot mode
** v0.8.1a - 30 September 2017
- Fix config-less navigation with simple digit displays
- Respond to USB stick pull when in ejected state
- LCD/OLED: Increase activity timeout to 60 seconds
- LCD/OLED: Turn on display on drive activity
** v0.8.0a - 29 September 2017
** Subfolder support
- Navigate subfolders in config-less mode
- All config files can now be stored in FF subfolder
- LASTDISK.IDX file now stores full path to the selected image
- OLED: Display turns off after timeout (same as LCD backlight)
- Wrap slot number at 0 and max when navigating
- Easter egg for Anders Kling. Thanks for your support!
-------------------------------------------------------------------------
** v0.7.4a - 25 September 2017
- Fix RDATA handling, specifically when drive B on an Amstrad CPC.
Reported by ikonsgr (EAB / Ebay) -- Thanks!
** v0.7.3a - 24 September 2017
- HxC: Respect autoboot- and ejected-on-startup flags
- Support 3rd button for eject and for immediate (re-)insert
- Do not wrap slot number at 0 and max.
** v0.7.2a - 21 September 2017
- Fixes to track timing and index position
- Properly emulate a single-headed drive
** v0.7.1a - 21 September 2017
- HFE: HFEv3 support
- HFE: Correctly set bitcell size for writes
- HFE: Reliability fix, read whole USB-disk sectors
- ADF: Support a wider range of ADF sizes
** v0.7.0a - 19 September 2017
** IMG/ST image handling. Rotary Encoder support.
- IMG and ST image files directly supported for read and write.
Please report any issues!
- Connect a rotary encoder to use in place of directional
buttons: Thanks to Fook42 (A1K/EAB). Documentation describes
how to connect.
-------------------------------------------------------------------------
** v0.6.3a - 18 September 2017
- Remove Amiga AUTOBOOT.HFE and config files from the distribution.
The HxC original files work fine, so forking is unnecessary.
- Resync index pulse after write handling: this dramatically
speeds up FAT filesystem access in the AUTOBOOT file selectors.
- Reorganise and update the documentation.
** v0.6.2a - 13 September 2017
- Prettier 7x16 'narrow' LED font (Kingstener)
- Remember last-selected slot in no-config mode (LASTDISK.IDX file
must exist). Thanks to Fook42 (A1K/EAB).
- Ignore glitches on SIDE-select signal (fix for Eric Gustafson's A3000)
- Various fixes for file selector on Atari ST and Amstrad CPC
- Suppress index pulse when writing to USB stick. Makes slow writes
more reliable (avoids timeouts on the host).
- Optimised memory copying and clearing
** v0.6.1a - 31 August 2017
- Support 2-digit LED display
- Suppress LCD update of side number when another drive is selected
** v0.6.0a - 24 August 2017
** PC Interface Support. OLED Fixes & Narrower Font Support.
- Allow PC Floppy Interface (DSKCHG on pin 34) to be selected via a
jumper at position JC. Default interface (no jumper at JC) remains
Shugart, as compatible with many non-PC systems including Amiga.
- Kingstener: Support narrower 7x16 OLED font. Allows entire display to be
visible through the 3-digit cutout in the Gotek case. This is a separate
firmware build, update file is in distribution subfolder alt/.
- OLED reliability fixes.
-------------------------------------------------------------------------
** v0.5.0a - 15 August 2017
** Greater stability on A1200 and accelerated Amigas
- I/O latency reduced on drive select/deselect. Results in more reliable
drive detection on A1200, with and without accelerator, and on warm
and cold reboots.
-------------------------------------------------------------------------
** v0.4.4a - 14 August 2017
- Improvements to power-on initialisation: initialise the floppy
interface earlier, start on cylinder 0, and don't trigger a spurious
step command
** v0.4.3a - 13 August 2017
- Fix DSKCHG handling. Should make disk insertion more reliable,
especially on Amiga with noclick patch.
** v0.4.2a - 11 August 2017
- More efficient I2C handling for OLED and fix synch during flash
update process.
** v0.4.1a - 11 August 2017
- Improve I2C robustness
** v0.4.0a - 10 August 2017
** 128x32 I2C OLED Display support
- Support for 0.91" I2C OLED (128x32, SSD1306 controller).
- Various optimisations and bug fixes.
-------------------------------------------------------------------------
** v0.3.2a - 7 August 2017
- Fix buffer overrun in HFE image handler when cannot read data from
USB stick fast enough.
- Update the Amiga AUTOBOOT.HFE with latest changes from upstream,
and bump version number.
** v0.3.1a - 7 August 2017
- Fix buffer overflow when copying long filenames in no-config mode.
** v0.3.0a - 6 August 2017
** Config-less & indexed operation
- Operate with no AUTOBOOT.HFE (requires HXCSDFE.CFG in 'indexed
mode'): files must be called DSKA0000.HFE, DSKA0001.HFE, and so
on. ADF images are also supported.
- Operate with no HXCSDFE.CFG! Buttons will cycle through all valid
images in the USB root folder.
- Step-pulse speaker is supported on output JB. Recommend buffering
through an NPN transistor unless using a piezo speaker (high
resistance).
- Long filenames scroll on the 1602 LCD
- LCD backlight timer, scroll speed, and step speaker volume all
configured via HXCSDFE.CFG (when available)
- Hack workaround for X-Copy problems. Verified writes/copies are now
reliable!
-------------------------------------------------------------------------
** v0.2.1a - 26 July 2017
** Fixes for LCD handling
- More reliable startup
- Fix crashes and deadlocks in operation
- More efficient command transmission (one I2C transaction for
successive commands)
- Support 0x38-0x3F I2C addresses
** v0.2.a - 25 July 2017
** 1602 LCD + Drive Logic Fixes
- 1602 LCD handling: Will recognise a 1602 LCD with "I2C backpack" as
used (and connected) for the usual "HxC LCD mod". Does not yet
scroll long filenames, this will be added shortly.
- Drive Logic: Will now play nicely in multi-drive systems and make
AmigaDOS much less confused (no more DF1-3:BAD type messages!)
- The bootloader is also modified to talk to the 1602 LCD: if you
want this feature then you must also update the bootloader by doing
a full serial or USB/DFU flash of the main HEX file.
-------------------------------------------------------------------------
** v0.1a - 21 July 2017
** Initial release
- Works only as sole drive in a host system (eg disconnect external
drives!)

113
Rules.mk
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@ -1,113 +0,0 @@
TOOL_PREFIX = arm-none-eabi-
CC = $(TOOL_PREFIX)gcc
OBJCOPY = $(TOOL_PREFIX)objcopy
LD = $(TOOL_PREFIX)ld
PYTHON = python3
ifneq ($(VERBOSE),1)
TOOL_PREFIX := @$(TOOL_PREFIX)
endif
FLAGS = -g -Os -nostdlib -std=gnu99 -iquote $(ROOT)/inc
FLAGS += -Wall -Werror -Wno-format -Wdeclaration-after-statement
FLAGS += -Wstrict-prototypes -Wredundant-decls -Wnested-externs
FLAGS += -fno-common -fno-exceptions -fno-strict-aliasing
FLAGS += -mlittle-endian -mthumb -mfloat-abi=soft
FLAGS += -Wno-unused-value -ffunction-sections
## STM32F105
ifeq ($(mcu),stm32f105)
FLAGS += -mcpu=cortex-m3 -DSTM32F105=1 -DMCU=1
ifeq ($(bootloader),y)
# Debug bootloader doesn't fit in 32kB
override debug=n
override logfile=n
endif
## AT32F435
else ifeq ($(mcu),at32f435)
FLAGS += -mcpu=cortex-m4 -DAT32F435=4 -DMCU=4
endif
ifneq ($(debug),y)
FLAGS += -DNDEBUG
endif
ifeq ($(bootloader),y)
FLAGS += -DBOOTLOADER=1
endif
ifeq ($(logfile),y)
FLAGS += -DLOGFILE=1
endif
ifeq ($(quickdisk),y)
FLAGS += -DQUICKDISK=1
endif
FLAGS += -MMD -MF .$(@F).d
DEPS = .*.d
FLAGS += $(FLAGS-y)
CFLAGS += $(CFLAGS-y) $(FLAGS) -include decls.h
AFLAGS += $(AFLAGS-y) $(FLAGS) -D__ASSEMBLY__
LDFLAGS += $(LDFLAGS-y) $(FLAGS) -Wl,--gc-sections
SRCDIR := $(shell $(PYTHON) $(ROOT)/scripts/srcdir.py $(CURDIR))
include $(SRCDIR)/Makefile
SUBDIRS += $(SUBDIRS-y)
OBJS += $(OBJS-y) $(OBJS-^n) $(patsubst %,%/build.o,$(SUBDIRS))
# Force execution of pattern rules (for which PHONY cannot be directly used).
.PHONY: FORCE
FORCE:
.PHONY: clean
.SECONDARY:
build.o: $(OBJS)
$(LD) -r -o $@ $^
%/build.o: FORCE
+mkdir -p $*
$(MAKE) -f $(ROOT)/Rules.mk -C $* build.o
%.ld: $(SRCDIR)/%.ld.S $(SRCDIR)/Makefile
@echo CPP $@
$(CC) -P -E $(AFLAGS) $< -o $@
%.elf: $(OBJS) %.ld $(SRCDIR)/Makefile
@echo LD $@
$(CC) $(LDFLAGS) -T$(*F).ld $(OBJS) -o $@
chmod a-x $@
%.hex: %.elf
@echo OBJCOPY $@
$(OBJCOPY) -O ihex $< $@
chmod a-x $@
$(PYTHON) $(ROOT)/scripts/check_hex.py $@ $(mcu)
ifneq ($(bootloader),y)
srec_cat ../bootloader/target.hex -Intel $@ -Intel -o $@ -Intel
endif
%.bin: %.elf
@echo OBJCOPY $@
$(OBJCOPY) -O binary $< $@
chmod a-x $@
%.dfu: %.hex
$(PYTHON) $(ROOT)/scripts/dfu-convert.py -i $< $@
%.o: $(SRCDIR)/%.c $(SRCDIR)/Makefile
@echo CC $@
$(CC) $(CFLAGS) -c $< -o $@
%.o: $(SRCDIR)/%.S $(SRCDIR)/Makefile
@echo AS $@
$(CC) $(AFLAGS) -c $< -o $@
-include $(DEPS)

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@ -1,124 +0,0 @@
Floppy:
-------
GPIn: (all must be 5v tolerant, *=not)
PB0* DIR
PA1* STEP
PA0* SELA
PA3* SELB [Enhanced Boards only]
PB9 WGATE
PB4 SIDE
PA15 MOTOR [Enhanced Boards only]
PB15 MOTOR [Standard board mod: pin 5 of SPI Flash footprint]
GPOut:
PB7 CHNG
PB8 INDEX
PB6 TRK0
PB5 WRPROT
PB3 RDY
TimerOut:
PA7 RDATA (Timer3/2, UP:DMA1/3)
TimerIn: (must be 5v tolerant)
PA8 WDATA (Timer1/1, CC1:DMA1/2)
Debug Console:
--------------
USART1: (Rx:DMA1/5, Tx:DMA1/4)
PA9 TX
PA10 RX
Enhanced Gotek Pin Assignments:
-------------------------------
GPIn:
PA3 SELB (if unused, connect to VDD/3.3v)
PA4 USB_ENA (active-low push-pull output to power switch)
PA5 USB_FAULT (active-low open-drain signal from power switch)
PA15 MOTOR (connect to floppy pin 16, and to 5v via 1K)
PC15-12 Board ID (connect to VSS/GND selectively)
0000 = no SD card connector
0001 = includes SD card conenctor
Jumpers & Switches:
-------------------
All are OFF=floating, ON=ground. Must be pulled up.
GPIn:
PC6 JUMPER_JA / BT_SELECT
PA2 JUMPER_JB / SPEAKER
PB1 JUMPER_JC / INTF_SELECT
PC8 BT_LEFT
PC7 BT_RIGHT
PC10 J7_PIN1 / ROTARY_A(CLK)
PC11 J7_PIN2 / ROTARY_B(DT)
PA14 JTCK_SWCLK
1602 LCD Display:
-----------------
I2C2: (Tx:DMA1/4, Rx:DMA1/5)
PB10 I2C_CLK_2
PB11 I2C_DAT_2
LED Display:
------------
Custom I2C-like protocol.
TimerOut:
PB10 DISP_DAT
PB11 DISP_CLK
SD Card [Enhanced Boards only]:
-------------------------------
If unused, pull all high.
GPIn: [pulled high by firmware]
PC9 CARD_DETECT (low when card is ejected, open/nc when card inserted)
GPOut:
PB12 CS
SPI2: (Rx:DMA1/4, Tx:DMA1/5)
PB13 CK
PB14 MISO
PB15 MOSI
USB:
----
Pull the GPIOs high, they are disconnected on USB setup anyway.
PA11 USB_DM
PA12 USB_DP
Speaker (switching NPN BJT):
----------------------------
PA2 Speaker Pulse, Active High
Unused Pins
-----------
Input weak pull-up/down.
PA3-6,13,15 n/c (floats) -- pull high
PB2 n/c (floats) -- pull high
PC0-5,9,12-15 n/c (floats) -- pull high
Floppy drive 34-pin Shugart(-ish) interface. For reference:
-----------------------------------------------------------
2: <- CHNG(Amiga) / -> DENSEL(PC)
3: oo (key)
4: oo
6: oo
8: <- INDEX
10: -> SEL0
12: -> SEL1
14: -> SEL2
16: -> MTR
18: -> DIR
20: -> STEP
22: -> DKWD
24: -> DKWE
26: <- TRK0
28: <- WRPROT
30: <- DKRD
32: -> SIDE
34: <- CHNG(PC) / RDY(Amiga)
All odd pins are ground.
Supercard Pro / Kryoflux:
-------------------------
Drive the bus with high-drive octal line drivers ('244/'245).
Pins 8/26-30/34 are configured as input, with 1k pull-ups.
All other pins are *push-pull* outputs (not open collector!).
Note pin 2 is a push-pull output, we must take care not to drive it to
0V from the floppy side unless we are on a host (eg Amiga) which is
expecting to receive a signal there.

View file

@ -1,107 +0,0 @@
/*
* Circular DMA Restart Behaviour:
*
* DMA channel can be disabled/enabled and buffer-ring will continue where
* it left off *unless* CNDTR is re-initialised. In that case buffer-ring
* cursor will reset to base address. In no case does CPAR/CMAR need to be
* re-initialised.
*
* HC and TC interrupts always occur at correct place within ring buffer
* regardless of restarts.
*/
static void check(uint8_t *p, int s, int e)
{
int i;
uint8_t hc = (dma1->isr >> 10) & 1;
uint8_t tc = (dma1->isr >> 9) & 1;
printk("%u-%u(%u): [", s, e, 8-dma1->ch3.cndtr);
for (i = 0; i < 7; i++)
printk(" %c,", p[i] ? p[i]+'0'-1 : '-');
printk(" %c ] %c%c\n", p[i] ? p[i]+'0'-1 : '-', hc ? 'H' : ' ',
tc ? 'T' : ' ');
memset(p, 0, 8);
dma1->ifcr = 0xf << 8;
}
static void dma_test(void)
{
uint8_t src[8], dst[8];
int i;
uint32_t ccr = (DMA_CCR_PL_HIGH |
DMA_CCR_MSIZE_8BIT |
DMA_CCR_PSIZE_8BIT |
DMA_CCR_MINC |
DMA_CCR_PINC |
DMA_CCR_CIRC |
DMA_CCR_DIR_P2M |
DMA_CCR_HTIE |
DMA_CCR_TCIE |
DMA_CCR_EN);
for (i = 0; i < ARRAY_SIZE(src); i++)
src[i] = i+1;
memset(dst, 0, sizeof(dst));
dma1->ifcr = 0xf << 8;
dma1->ch3.cpar = (uint32_t)(unsigned long)src;
dma1->ch3.cmar = (uint32_t)(unsigned long)dst;
dma1->ch3.cndtr = ARRAY_SIZE(src);
dma1->ch3.ccr = ccr;
/* 1ms */
tim3->psc = SYSCLK_MHZ - 1;
tim3->arr = 1000;
tim3->cr2 = 0;
tim3->dier = TIM_DIER_UDE;
printk("Timer On then Off:\n");
tim3->cr1 = TIM_CR1_CEN;
while (dst[3] == 0)
cpu_relax();
tim3->cr1 = 0;
check(dst, 0, 3);
printk("Timer Disable/Enable\n");
tim3->cr1 = TIM_CR1_CEN;
while (dst[5] == 0)
cpu_relax();
tim3->cr1 = 0;
dma1->ch3.ccr = 0;
check(dst, 4, 5);
printk("... + DMA:\n");
dma1->ch3.ccr = ccr;
tim3->cr1 = TIM_CR1_CEN;
while (dst[1] == 0)
cpu_relax();
tim3->cr1 = 0;
dma1->ch3.ccr = 0;
check(dst, 6, 1);
printk("... + CNDTR Reset:\n");
dma1->ch3.cndtr = ARRAY_SIZE(src);
dma1->ch3.ccr = ccr;
tim3->cr1 = TIM_CR1_CEN;
while (dst[4] == 0)
cpu_relax();
tim3->cr1 = 0;
dma1->ch3.ccr = 0;
check(dst, 2, 4);
printk("... + CPAR/CMAR Reset:\n");
dma1->ch3.cpar = (uint32_t)(unsigned long)src;
dma1->ch3.cmar = (uint32_t)(unsigned long)dst;
dma1->ch3.ccr = ccr;
tim3->cr1 = TIM_CR1_CEN;
while (dst[1] == 0)
cpu_relax();
tim3->cr1 = 0;
dma1->ch3.ccr = 0;
check(dst, 5, 1);
printk("All done\n");
for (;;);
}

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@ -1,95 +0,0 @@
Floppy timings:
---------------
Citizen Z1DE-58A (a generic HD PC drive):
Read pulse width: low for ~400ns
INDEX pulse width: low for 2ms
STEP: latched on trailing (rising) edge
- RDDAT immediately deasserted
- TRK0 immediately deasserted
- TRK0 asserted after 3ms
- RDDAT asserted after 18ms
DSKCHG: deasserted immediately on falling edge of STEP,
even if STEP is to be ignored (eg. on min/max cyl already)
Side change: within 20us, read stream not halted meanwhile.
Cortex-M3 STM32F1xx Timings:
----------------------------
Times assume 72MHz clock (14ns cycle time)
ldr Rt,[Rn,#x] = 1cy,14ns memory; 3cy,42ns gpio
irq entry = 12cy,167ns
irq exit = 10cy,139ns
USB Reads:
----------
1 sector: 1.2 - 2.5ms
2 sector: 2.0 - 3.2ms (+0.8ms)
4 sector: 3.3 - 4.5ms (+1.3ms)
8 sector: 6.0 - 7.2ms (+2.7ms)
16 sector: 11.4 - 12.6ms (+5.4ms)
> Read time ~= 0.4-1.7ms + 0.8ms*nr_secs
USB Writes:
-----------
(Per-sector write latencies)
1 sector: 771 - 4227us (av approx 2.4ms)
2 sector: 722 - 1887us (" 1.1ms)
4 sector: 733 - 1206us (" 900us)
8 sector: 676 - 904us (" 800us)
16 sector: 643 - 743us (" 700us)
Alignment seems to make little or no difference.
BEST USB STICKS:
----------------
Lexar 32GB USB3.0 Jump Drive S75 (05DC:A205 "Lexar JumpDrive"):
HFE Write: 33ms track read, 850us write-blk, 6ms seek+write-blk
Very predictable performance, does not miss any SCP track writes
HFE Whole Track Writes: 40-100ms track read, 60-90ms track write
Somewhat erratic, misses Supercard Pro track writes
ADF write: Very predictable, 850us-3ms write-blk
Lexar 32GB USB3.0 Jump Drive S45 (05DC:A82D "Lexar USB Flash Drive"):
HFE Write: 35ms track read, 950us blk-write, 5ms seek+write-blk
Very predictable performance, does not miss any SCP track writes
HFE Whole Track Writes: 33ms track read, 31ms track write
Very predictable, does not miss any SCP writes
ADF Write: Very predictable, 850us-2ms write-blk
PROBLEMATIC STICKS:
-------------------
SanDisk 32GB Ultra Fit USB3.0 (0781:5583 "SanDisk Ultra Fit"):
PROBLEM: Sometimes consistently fails to respond
to TestUnitReady until physically re-inserted.
HFE Write: 40ms track read, 3ms write-blk, 6ms seek+write-blk
Occasional 200ms+ first write-blk after track read, misses SCP writes
HFE Whole Track Writes: 40 ms track read, 40ms track write
Very predictable, does not miss any SCP writes
ADF Write: 3ms write-blk, very predictable
THE REST OF USB:
----------------
Generic 16GB stick (058F:6366 "Generic Flash Card Reader/Writer"):
HFE Write: 35ms track read, ~4ms write-blk, ~7ms seek+write-blk
Occasional 40-70ms+ write-blk, misses Supercard Pro track writes
HFE Whole Track Writes: 35ms track read, 45ms track writes
Occasional 200ms+ writes, misses SCP track writes
ADF Write: Occasional 200ms+ writes
Kingston 16GB DataTraveler G4 (0951:1666 "Kingston DataTraveler 3.0"):
HFE Write: 37ms track read, 900us write-blk, 10ms seek+write-blk
Occasional 140ms+ write-blk, misses SCP writes
HFE Whole Track Writes: 34ms read, 34ms write, occasional 150ms+ writes
ADF Write: 2-4ms write-blk, occasional 120ms+ write-blk
SanDisk 16GB Cruzer Switch USB2 (0781:5572 "SanDisk Cruzer Switch"):
HFE Write: 35ms track read, 3ms write-blk, 6ms seek+write-blk
Occasional stretches of 10ms-90ms write-blk, misses SCP writes
HFE Whole Track Writes: 34ms read, 34ms write, occasional 190ms+ writes
ADF Write: Occasional 70ms+ writes
Toshiba 16GB TransMemory U202 USB2.0 (0930:6544 "Toshiba TransMemory"):
HFE Write: 40ms track-read, 850us-3ms write-blk, 7ms seek+write-blk
Occasional 80ms+ write-blk
HFE Whole Track Writes: 34ms read, 34ms write, occasional 100ms+ writes
ADF Write: 1-2ms write-blk, occasional 70ms+ write-blk

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@ -1,291 +0,0 @@
## FF.CFG: Example FlashFloppy Configuration File
# Place in the root folder or FF/ subfolder of your USB drive.
# NOTE: If FF/ exists, IMG.CFG must reside there, not the root folder.
# Uncommented lines below are the default settings.
# Uncommented options cannot be overridden by settings in other config files.
##
## DRIVE EMULATION
# Floppy-drive interface mode (interface pins 2 and 34)
# jc: Specified by jumper JC (open: shugart, closed: ibmpc)
# shugart: P2=DSKCHG, P34=RDY (Amiga, Atari ST, many others)
# ibmpc: P2=unused, P34=DSKCHG (IBM PC interface)
# ibmpc-hdout: P2=HD_OUT, P34=DSKCHG (not generally needed: prefer ibmpc)
# jppc: P2=unused, P34=RDY (Japanese PC standard)
# jppc-hdout: P2=HD_OUT, P34=RDY (Japanese PC alternate: prefer jppc)
# akai-s950: Legacy alias of jppc-hdout, previously used for Akai S950
# amiga: P2=DSKCHG, P34=DRIVE_ID (not generally needed: prefer shugart)
interface = jc
# Host platform: Improves image-format detection for generic types such as IMG
# acorn: Acorn ADFS
# akai: Akai (S01, S20, S950), Korg, SC Prophet 3000
# casio: Casio (FZ-1)
# dec: DEC (RX33, RX50)
# ensoniq: Ensoniq (ASR, TS, etc)
# fluke: Fluke 9100
# gem: General Music (S2, S3)
# ibm-3174: IBM 3174 Establishment Controller
# memotech: Memotech
# msx: MSX
# nascom: Nascom
# pc98: NEC PC-98
# pc-dos: PC DOS Format (geometry determined from Bios Parameter Block)
# tandy-coco: Tandy Color Computer (CoCo)
# ti99: TI-99/4A
# uknc: UKNC / DVK Soviet PDP-11
# unspecified: Common default geometries (including IBM PC)
host = unspecified
# Pins 2 & 34 output (drive->host) manual configuration
# auto: Auto-configure from interface= setting
# nc: Unused/No Connection [eg. if pin is an input (host->drive) on your host]
# low: Always 0 volts (0v)
# high: Always 5 volts (5v)
# rdy: Drive ready (Ready = 0v)
# nrdy: Logical complement of above
# dens: Density mode (High Density = 0v)
# ndens: Logical complement of above
# chg: Disk changed (Changed = 0v)
# nchg: Logical complement of above
# Values: auto, nc, low, high, rdy, nrdy, dens, ndens, chg, nchg
pin02 = auto
pin34 = auto
# Forcibly write-protect images, or respect the FAT read-only attribute?
# Values: yes | no
write-protect = no
# Maximum cylinder that can be stepped to (255 is required for access to
# Direct Access mode as used by image-selector utilities and Autoswap games).
# Values: 0 <= N <= 255
max-cyl = 255
# Filter glitches in the SIDE-select signal shorter than N microseconds
# Values: 0 <= N <= 255
side-select-glitch-filter = 0
# Rotational offset of disk after a track change
# instant: No rotation during track change
# realtime: Emulate rotation of disk while track is changing
# Values: instant | realtime
track-change = instant
# Rotational offset of disk after draining a write to Flash
# instant: No rotation
# realtime: Disk rotates in real time during drain
# eot: Disk rotates to (near) end of track
# Values: instant | realtime | eot
write-drain = instant
# Index pulses suppressed when RDATA and WDATA inactive?
# Values: yes | no
index-suppression = yes
# Milliseconds from head-step start to RDATA active.
# Values: 0 <= N <= 255
head-settle-ms = 12
# Milliseconds delay from motor-on to drive ready.
# On a standard unmodified Gotek the motor signal is not connected and a
# non-default value here will have no effect. Most systems and software do
# not care about correct motor behaviour, and default (ignore) works fine.
# Values: ignore | 0 <= N <= 1000
motor-delay = ignore
# What causes the disk-change (chg) signal to reset after disk insertion?
# step: Step command received
# pa14: CHGRST (pin 1 on old Sony drives), connected to PA14 (JTCK/SWCLK)
# delay-N: Automatically after N*0.5sec (0 <= N <= 15)
chgrst = step
##
## STARTUP / INITIALISATION
# Disk image loaded or ejected at startup?
# Values: yes | no
ejected-on-startup = no
# Which image (or folder) is selected at startup?
# last: Last-selected item at power-off (recorded in IMAGE_A.CFG)
# static: Static path specified in INIT_A.CFG
# init: First item in root folder
# Values: last | static | init
image-on-startup = last
# Time in milliseconds to attempt to probe attached display.
# You may set this to 0 if you have a 2-digit LED display attached.
# Values: 0 <= N <= 65535
display-probe-ms = 3000
##
## IMAGE NAVIGATION
# Auto-select the current file after N seconds
# N=0: disable auto-select
# Values: 0 <= N <= 255
autoselect-file-secs = 2
# Auto-select the current folder after N seconds
# N=0: disable auto-select
# Values: 0 <= N <= 255
autoselect-folder-secs = 2
# Sorting of folder entries in native navigation mode.
# always: Always sort folder entries. Large folders may be truncated.
# never: Never sort folder entries, instead presenting them in FAT order.
# small: Only sort folders which are small enough to sort in full.
# Values: always | never | small
folder-sort = always
# Priority of files vs subfolders when sorting folder entries:
# folders: Folders listed before files
# files: Files listed before folders
# none: Files and folders are not differentiated
# Values: folders | files | none
sort-priority = folders
# Navigation mode for selecting images/slots
# native: Navigate through all valid images/dirs
# indexed: Navigate through DSKA0000, DSKA0001, ...
# default: native unless overridden by HxC-compat-mode config
nav-mode = default
# When navigating slots or folder, loop at min/max?
# Values: yes | no
nav-loop = yes
# Actions of first two buttons.
# B1 | B2 | Both
# zero: Prev | Next | Slot 0
# eject: Prev | Next | Eject/Insert
# htu: +10 | +1 | +100
# rotary: Up-dir | Select/Eject/Insert | -
# rotary-fast: Prev | Next | Up-dir [Prev/Next are accelerated]
# reverse: Reverse sense of B1 and B2
# Multiple values can be separated by commas, eg twobutton-action=eject,reverse
twobutton-action = zero
# Input sensor type at the rotary-encoder inputs (pins PC10 and PC11):
# [full | half | quarter]:
# Rotary encoder, identified by fraction of a Gray-code cycle performed
# per detent/click. If default value (full) requires multiple
# clicks/detents to move position then change to half (if 2 clicks
# per move) or quarter (if 4 clicks).
# [trackball]:
# Blackberry-style trackball (eg. using Hall-effect sensors).
# [buttons]:
# Push-to-ground Prev/Next buttons.
# [reverse]:
# If the input is working in reverse, use this option to swap directions.
# [v2]:
# Use the rotary encoder logic from FlashFloppy v2.x. Use this if the
# v3 logic is too strict and results in no, or missing, movements.
# Multiple values can be separated by commas, eg rotary=quarter,reverse
# Values: none | quarter | half | full | trackball | buttons | reverse | v2
rotary = full
# Prefix for image names in indexed navigation mode. String can be empty ("").
indexed-prefix = "DSKA"
##
## DISPLAY
# Display Type.
# auto: Auto-detect (7-seg LED, LCD, OLED)
# lcd-CCxRR: CCxRR backlit LCD with I2C backpack (16<=CC<=40, 02<=RR<=04)
# oled-128xNN: 128xNN I2C OLED (NN = 32 | 64)
# -rotate: OLED view is rotated 180 degrees
# -hflip: OLED view is flipped horizontally
# -narrow[er]: OLED view is restricted to Gotek display cutout
# (-narrow: 18 chars; -narrower: 16 chars)
# -inverse: Inverse/reverse video (black text on white background)
# -ztech: ZHONGJY_TECH 2.23" 128x32 SSD1305 OLED display
# -slow: Run I2C bus slower (use this if OLED regularly blanks/corrupts)
# Values: auto | lcd-CCxRR | oled-128xNN[-rotate][-narrow[er]]...
display-type = auto
# OLED Font. Narrow and wide options.
# Narrower 6x13 font permits:
# - More characters per row
# - Use of Gotek display cutout (eg. "display-type=oled-128x32-narrow")
# Values: 6x13 | 8x16
oled-font = 6x13
# OLED contrast/brightness.
# Values: 0 <= N <= 255
oled-contrast = 143
# Text height and arrangement on LCD/OLED and on OSD, respectively.
# Comma-separated list, one entry per display row, top down.
# Each list item is a digit plus optional height specifier: [0-7][d]
# content-row: 0-3 = specified content, 7 = blank
# 0: Current image name
# 1: Status
# 2: Image/Volume info
# 3: Current subfolder name
# height-specifier: d = double height (32px, OLED only; ignored for LCD)
# Default depends on display, eg.: oled-128x32 -> 0,1 ; oled-128x64 -> 3,0d,1
# Values: [0-7][d] | default
display-order = default
osd-display-order = default
# OSD text columns. This is currently respected only when no LCD/OLED is found.
# Values: 16 <= N <= 40
osd-columns = 40
# Turn an LCD or OLED display off after N seconds of inactivity
# N=0: always off; N=255: always on
# Values: 0 <= N <= 255
display-off-secs = 60
# Switch on LCD/OLED display when there is drive activity?
# yes: Trigger on track changes and disk writes
# sel: Trigger on drive select
# no: No automatic trigger
# Values: yes | sel | no
display-on-activity = yes
# LCD/OLED long filename scroll rate in milliseconds per update
# Values: 100 <= N <= 65535
display-scroll-rate = 200
# LCD/OLED pause time at start/end of scroll, in milliseconds
# Zero means endless scroll
# Values: 0 <= N <= 65535
display-scroll-pause = 2000
# LCD/OLED long filename scroll rate during navigation (ms per update)
# Values: 0 <= N <= 65535
nav-scroll-rate = 80
# LCD/OLED long filename pause before scroll, during navigation (milliseconds)
# Values: 0 <= N <= 65535
nav-scroll-pause = 300
##
## MISCELLANEOUS
# Speaker volume for head STEP
# Values: 0 <= N <= 20
step-volume = 10
# Speaker volume for insert, eject, and slot-number notifications.
# Slot number is indicated by a sequence of beeps when an image is mounted
# iff "slotnr" is specified. The slot number is then notified by a sequence of
# long beeps (each counting +5), followed by a sequence of short beeps
# (each counting +1).
# Values: N[,slotnr] (0 <= N <= 15)
notify-volume = 0
# Report the specified version number to host software
# Values: <quoted-string> ("" means report real version)
# eg. da-report-version = "v3.0.0.0"
da-report-version = ""
# Automatically extend certain types of truncated image file (SSD,DSD,TRD)?
# Values: yes | no
extend-image = yes

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@ -1,18 +0,0 @@
## IMG.CFG for Bung Multi Game Doctor (MGD) 2.
# NOTE: The tags match on filesize alone. If you wish to define an explicit
# tagname match, you can for example add 'mgd2' to the square-bracketed tags
# to limit matches to filenames of the form *.mgd2.{img,ima,dsk}
# Images are 1756kB exactly.
[::1798144]
cyls = 80
heads = 2
tracks = 0
secs = 18
bps = 512
tracks = 1-79
secs = 11
bps = 1024
gap3 = 30

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## IMG.CFG: FlashFloppy Geometry Configuration File for Raw IMG Images
## For CompuPro 8-16 8" Floppy disks.
# Tested on a CompuPro 8-16 System using the 50-to-34 pin adapter
# board available here: https://gitlab.com/NF6X_Retrocomputing/fd50to34
#
# Make sure to set the jumpers on the fd50to34:
# * 2SIDE - Install if emulated floppy disk is double-sided.
# * MTRON - Install
#
# In FF.CFG, set interface=shugart
#
# Supports tagged IMG/IMA raw image files with self-identifying geometry.
# If you wish to use this feature, your IMG.CFG must be placed in the
# root folder or FF/ subfolder of your USB drive.
# NOTE: If FF/ exists, IMG.CFG must reside there, not the root folder.
# A badly-defined section (eg. undefined mandatory parameters) may result in
# error 31 (Bad Image).
####################################################################
## TAG in square brackets.
## Format: [<tagname>][::<filesize>]
## Matching Rules:
## 1. <tagname> matches images of the form *.<tagname>.{img,ima,dsk}
## 2. Missing (empty) tagname matches any *.{img,ima,dsk} which is untagged
## or does not match any other defined tag.
## 3. Tagnames and their matches are NOT case sensitive.
## 4. <filesize>, if specified, must exactly match the image filesize.
## 5. If an image matches no tag, FlashFloppy uses normal geometry
## auto-detection based on the host= setting in FF.CFG.
####################################################################
# Definition for standard CP/M 8" SS/DD.
#
# CP/M 8" SS/SD format is single-density (FM) with 26 128-byte
# sectors on all cylinders.
[::256256]
cyls = 77
heads = 1
rpm = 360
gap3 = 42
interleave = 1
bps = 128 ## 128-byte sectors
secs = 26
mode = fm
id = 1
####################################################################
# Definition for CompuPro 8" SS/DD.
#
# CP/M 8" SS/DD format is double-density but with a single-density
# (FM) cylinder 0.
[::625920]
cyls = 77
heads = 1
interleave = 1
rpm = 360
gap3 = 42
tracks = 0 ## Boot cylinder, head 0
bps = 128 ## Cylinder 0 has 128-byte sectors
secs = 26
mode = fm
id = 1
tracks = 1-76 ## All other cylinders
bps = 1024
secs = 8
mode = mfm
id = 1
####################################################################
# Definition for CompuPro 8" DS/SD.
#
# CP/M 8" DS/SD format is single density, 128-byte sectors.
[::512512]
cyls = 77
heads = 2
interleave = 1
rpm = 360
gap3 = 42
bps = 128
secs = 26
mode = fm
id = 1
####################################################################
# Definition for CompuPro 8" DS/DD 1024-byte sectors.
#
# CP/M 8" DS/DD format is double-density but with a single-density
# (FM) track 0.
[::1256704]
cyls = 77
heads = 2
interleave = 1
rpm = 360
gap3 = 42
tracks = 0.0 ## Boot cylinder, head 0
bps = 128 ## Cylinder 0, head 0 has 128-byte sectors
secs = 26
mode = fm
id = 1
tracks = 0.1 ## Boot cylinder, head 1
bps = 1024 ## Cylinder 0, head 1 has 1024-byte sectors
secs = 8
mode = mfm
id = 1
tracks = 1-76 ## All other cylinders
bps = 1024
secs = 8
mode = mfm
id = 1
####################################################################
# Definition for CompuPro 8" DS/DD 512-byte sectors.
#
# CP/M 8" DS/DD format is double-density but with a single-density
# (FM) track 0.
[::1178368]
cyls = 77
heads = 2
interleave = 1
rpm = 360
gap3 = 42
tracks = 0.0 ## Boot cylinder, head 0
bps = 128 ## Cylinder 0, head 0 has 128-byte sectors
secs = 26
mode = fm
id = 1
tracks = 0.1 ## Boot cylinder, head 1
bps = 512 ## Cylinder 0, head 1 has 512-byte sectors
secs = 15
mode = mfm
id = 1
tracks = 1-76 ## All other cylinders
bps = 512
secs = 15
mode = mfm
id = 1
####################################################################
# Definition for CompuPro 8" DS/DD 256-byte sectors.
#
# CP/M 8" DS/DD format is double-density but with a single-density
# (FM) track 0.
[::1021696]
cyls = 77
heads = 2
interleave = 1
rpm = 360
gap3 = 42
secs = 26
tracks = 0.0 ## Boot cylinder, head 0
bps = 128 ## Cylinder 0, head 0 has 128-byte sectors
mode = fm
id = 1
tracks = 0.1 ## Boot cylinder, head 1
bps = 256 ## Cylinder 0, head 1 has 256-byte sectors
secs = 26
mode = mfm
id = 1
tracks = 1-76 ## All other cylinders
bps = 256
secs = 26
mode = mfm
id = 1

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@ -1,16 +0,0 @@
## IMG.CFG for Dynacord ADS hosts.
# NOTE: The tags match on filesize alone. If you wish to define an explicit
# tagname match, you can for example add 'dyna' to the square-bracketed tags
# to limit matches to filenames of the form *.dyna.{img,ima,dsk}
[::1638400]
cyls = 80
heads = 2
bps = 512
secs = 20
interleave = 2
tracks = 0-79.0 ## Head 0
id = 1
tracks = 0-79.1 ## Head 1
id = 21 # Follows on from head 0 (1..20 -> 21..40)

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@ -1,39 +0,0 @@
# IMG.CFG for Ensoniq hosts
# 800kB and 1.6MB image types are also handled by FF.CFG: host=ensoniq
# NOTE: The tags match on filesize alone. If you wish to define an explicit
# tagname match, you can for example add 'ensoniq' to the square-bracketed tags
# to limit matches to filenames of the form *.ensoniq.{img,ima,dsk}
# Ensoniq 800kB DSDD
# Also handled by FF.CFG: host=ensoniq
[::819200]
cyls = 80
heads = 2
secs = 10
bps = 512
gap3 = 30
id = 0
rate = 250
# Ensoniq 1.6MB DSHD
# Also handled by FF.CFG: host=ensoniq
[::1638400]
cyls = 80
heads = 2
secs = 20
bps = 512
gap3 = 40
id = 0
rate = 500
# Ensoniq Mirage 440kB SSDD
# Mixed sector sizes *NOT* handled by FF.CFG: host=ensoniq
[::450560]
cyls = 80
heads = 1
secs = 6
bps = 1024,1024,1024,1024,1024,512
id = 0
rate = 250

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@ -1,17 +0,0 @@
## IMG.CFG for machines produced by GRiD Systems Corp.
# NOTE: The tags match on filesize alone. If you wish to define an explicit
# tagname match, you can for example add 'flex' to the square-bracketed tags
# to limit matches to filenames of the form *.flex.{img,ima,dsk}
# 360k 40-cylinder DS/DD format used by GRiD Compass
[::368640]
cyls = 40
heads = 2
bps = 512
secs = 9
mode = mfm
interleave = 5
id = 1
tracks = 0-39.1
id = 10

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@ -1,40 +0,0 @@
## IMG.CFG for Kaypro systems.
# NOTE: The tags match on filesize alone. If you wish to define an explicit
# tagname match, you can for example add 'kp' to the square-bracketed tags
# to limit matches to filenames of the form *.kp.{img,ima,dsk}
# 200kB: SSDD, 40 cyl
[::204800]
cyls = 40
heads = 1
secs = 10
bps = 512
interleave = 3
id = 0
# 400kB: DSDD, 40 cyl
[::409600]
cyls = 40
heads = 2
secs = 10
bps = 512
interleave = 3
h = 0
tracks = 0-39.0
id = 0
tracks = 0-39.1
id = 10
# 800kB: DSDD, 80 cyl
[::819200]
cyls = 80
heads = 2
secs = 10
bps = 512
interleave = 3
h = 0
tracks = 0-79.0
id = 0
tracks = 0-79.1
id = 10

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@ -1,40 +0,0 @@
## IMG.CFG for Osborne systems.
# NOTE: The tags match on filesize alone. If you wish to define an explicit
# tagname match, you can for example add 'occ1' to the square-bracketed tags
# to limit matches to filenames of the form *.occ1.{img,ima,dsk}
# Osborne 1 OCC1/1A (for units without double density upgrade fitted)
# SSSD 100Kb
[::102400]
cyls = 40
heads = 1
secs = 10
bps = 256
cskew = 2
mode = fm
iam = no
# Osborne Executive OCC2 (also OCC1/1A with double density upgrade fitted)
# SSDD 200Kb
[::204800]
cyls = 40
heads = 1
secs = 5
bps = 1024
mode = mfm
iam = yes
# Osborne Vixen OCC4 (also Executive OCC2 with double sided upgrade fitted)
# DSDD 400Kb
# Note: Multiple sizes for OCC4. Covered here with a default rule but could
# instead explicitly handle the following sizes if the square-bracket syntax
# is ever extended to support it: 409600, 409728, 409856, 419840
[]
cyls = 40
heads = 2
secs = 5
bps = 1024
cskew = 2
mode = mfm
iam = yes

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@ -1,60 +0,0 @@
## IMG.CFG for faster loading of Roland OS and System disks.
## Some Roland disks have 'sector interleave' and if this is missing (as in
## default 720kB track configuration) the OS and System Utilities can load
## approximately 5x slower than expected. The configurations below fix this.
# NOTES:
#
# 1. OS and System images must be named as described below.
#
# 2. By default 'os' and 'sys' tags apply sector interleave to all tracks.
# Some disks (eg S-330 OS disk) contain sample data with no interleave:
# They will load 2x slower than expected. If this concerns you, adjust the
# 'track=' line to cover only the tracks requiring interleave (eg. '0-8').
#
# 3. You can copy and paste the sections below to create further tags as
# needed for your specific set of OS and System disks.
# Matches 720kB images named *.os.{img,ima,dsk}.
[os::737280]
cyls = 80
heads = 2
secs = 9
bps = 512
tracks = 0-79 # This line can be adjusted
interleave = 2
hskew = 1
cskew = 2
# Matches 720kB images named *.sys.{img,ima,dsk}.
[sys::737280]
cyls = 80
heads = 2
secs = 9
bps = 512
tracks = 0-79 # This line can be adjusted
interleave = 2
hskew = 1
cskew = 2
# Matches 720kB images named *.mc.{img,ima,dsk}.
# This higher level of interleave is found on all disks for the
# Roland MC-300, MC-500 and MC-50.
[mc::737280]
cyls = 80
heads = 2
secs = 9
bps = 512
tracks = 0-79
interleave = 4
# Roland 1.44MB format may apply sector skew.
# This is as seen on a Roland MT-200.
[::1474560]
cyls = 80
heads = 2
secs = 18
bps = 512
hskew = 3
cskew = 6

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@ -1,14 +0,0 @@
# IMG.CFG for Sequential Circuits hosts
# NOTE: The tags match on filesize alone. If you wish to define an explicit
# tagname match, you can for example add 'sci' to the square-bracketed tags
# to limit matches to filenames of the form *.sci.{img,ima,dsk}
# Sequential Circuits Prophet 840kB DSDD
[::860160]
cyls = 80
heads = 2
secs = 6
bps = 1024,1024,1024,1024,1024,256
id = 0
rate = 250

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@ -1,13 +0,0 @@
## IMG.CFG for Sinclair QL ED Disks (3.2MB)
# NOTE: The tags match on filesize alone. If you wish to define an explicit
# tagname match, you can for example add 'ql' to the square-bracketed tags
# to limit matches to filenames of the form *.ql.{img,ima,dsk}
# Images are 3200kB exactly.
[::3276800]
cyls = 80
heads = 2
secs = 10
bps = 2048

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The Clive Drive controller has a 16-pin drive interface. Pins 3-12
inclusive correspond to the usual 10-pin QD interface. For reference,
see the Clive Drive schematic at:
https://speccy4ever.speccy.org/rom/clive/Clive%20Drive.pdf
Clive Controller QDD Gotek
1---------NC
2---------NC
3---------WRITE PROTECT (WRPR) 1 28
4---------WRITE DATA (WRDT) 2 22
5---------WRITE GATE 1 (WRGT1) 3 24
6---------MOTOR ON 1 (MTON1) 4 16
7---------READ DATA (RDDT) 5 30
8---------READY 6 34
9---------MEDIA SENSE (MDST) 7 2
10--------QD RESET (QDDRST) 8 20
11--------VCC +5V 9 +5v
12--------GND 10 GND
13--------MOTOR ON 2 (MTON2) NC NC
14--------WRITE GATE 2 (WRGT2) NC NC
15--------SEL IN (SELIN) NC NC
16--------NC

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## IMG.CFG for the Sandy FDD2 interface.
# Sandy FDD2 is a clone of the FDC-1 by Technology Research Ltd.
# Using a 1771 controller chip, it supports single-density (FM) recording
# only, unlike the later Beta Disk interfaces.
# *.ss40.img: Single-sided 40 cylinders.
[ss40::102400]
cyls = 40
heads = 1
secs = 10
bps = 256
mode = fm
interleave = 2
# *.ss80.img: Single-sided 80 cylinders.
[ss80::204800]
cyls = 80
heads = 1
secs = 10
bps = 256
mode = fm
interleave = 2
# *.ds40.img: Double-sided 40 cylinders.
[ds40::204800]
cyls = 40
heads = 2
secs = 10
bps = 256
mode = fm
interleave = 2
tracks = 0-39.1
h = 0
# *.ds80.img: Double-sided 80 cylinders.
[ds80::409600]
cyls = 80
heads = 2
secs = 10
bps = 256
mode = fm
interleave = 2
tracks = 0-79.1
h = 0

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## IMG.CFG for TSC Flex hosts.
# NOTE: The tags match on filesize alone. If you wish to define an explicit
# tagname match, you can for example add 'flex' to the square-bracketed tags
# to limit matches to filenames of the form *.flex.{img,ima,dsk}
# DS/DD with SD (FM) cylinder 0.
# Sector numbering and interleave is continuous across drive heads. Since
# there is no direct way to flag this, we implement it here by explicitly
# specifying head 1 track formats: with sector @id following on from head 0,
# and with @hskew shifting the first sector of side 1 the correct amount to
# simulate cross-track interleave.
[::733184]
cyls = 80
heads = 2
bps = 256 # All tracks have 256-byte sectors. Number of sectors varies.
iam = no
gap3 = 16
gap4a = 16
tracks = 0.0 ## Boot cylinder, head 0
secs = 10
mode = fm
interleave = 4
id = 1
h = 0
tracks = 0.1 ## Boot cylinder, head 1
secs = 10
mode = fm
interleave = 4
hskew = 1 # Simulates correct inter-track interleave
id = 11 # Follows on from head 0 (1..10 -> 11..20)
h = 0
tracks = 1-79.0 ## All other cylinders, head 0
secs = 18
mode = mfm
interleave = 6
id = 1
h = 1
tracks = 1-79.1 ## All other cylinders, head 1
secs = 18
mode = mfm
interleave = 6
hskew = 5 # Simulates correct inter-track interleave
id = 19 # Follows on from head 0 (1..18 -> 19..36)
h = 1
# SS/DD with SD (FM) cylinder 0.
# Definition is a simplified version of the DS/DD format.
[::366592]
cyls = 80
heads = 1
bps = 256
iam = no
gap3 = 16
gap4a = 16
id = 1
tracks = 0.0
secs = 10
mode = fm
interleave = 4
h = 0
tracks = 1-79.0
secs = 18
mode = mfm
interleave = 6
h = 1

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## IMG.CFG: Example FlashFloppy Geometry Configuration File for Raw IMG Images
# Supports tagged IMG/IMA raw image files with self-identifying geometry.
# If you wish to use this feature, your IMG.CFG must be placed in the
# root folder or FF/ subfolder of your USB drive.
# NOTE: If FF/ exists, IMG.CFG must reside there, not the root folder.
# A badly-defined section (eg. undefined mandatory parameters) may result in
# error 31 (Bad Image).
####################################################################
## TAG in square brackets.
## Format: [<tagname>][::<filesize>]
## Matching Rules:
## 1. <tagname> matches images of the form *.<tagname>.{img,ima,dsk}
## 2. Missing (empty) tagname matches any *.{img,ima,dsk} which is untagged
## or does not match any other defined tag.
## 3. Tagnames and their matches are NOT case sensitive.
## 4. <filesize>, if specified, must exactly match the image filesize.
## 5. If an image matches no tag, FlashFloppy uses normal geometry
## auto-detection based on the host= setting in FF.CFG.
# [dsdd80::737280] matches images with names of the form *.dsdd80.{img,ima,dsk}
# and with size exactly 720kB (737280 bytes).
[dsdd80::737280]
## DISK-SCOPE PARAMETERS
# Apply to the whole disk image. Cannot appear in a @tracks sub-section.
# Mandatory: Number of cylinders (1-255).
cyls = 80
# Mandatory: Number of heads (1-2).
heads = 2
# Number of drive-head steps between cylinders. Default is 1.
# step = 1
# Image file track layout. Default is "interleaved".
# Comma-separated values:
# sequential: Sequential cylinder ordering: all side 0, then side 1.
# interleaved: Interleaved cylinder ordering: c0s0, c0s1, c1s0, c1s1, ...
# reverse-sideN: Side-N cylinders are ordered from high to low (N=0,1).
# sides-swapped: Sides 0 and 1 ordering is swapped in the image file.
# eg. "sequential,reverse-side1"
# file-layout = interleaved
## TRACK-SCOPE PARAMETERS
# These can vary across tracks. By default they apply to all tracks unless
# preceded by a @tracks declaration.
# tracks = <track-list>
# Specify the tracks that the following track-scope parameters applies to.
# Format:
# track-list ::= <track-range>[,<track-list>]
# track-range ::= <cylinder>[.<head>] | <cylinder>-<cylinder>[.<head>]
# cylinder ::= [0-9][0-9]*
# head ::= 0|1
# If no head is specified in a track-range, then all heads are assumed.
# Examples:
# "0-23.1,45.0" specifies head 1 of cyls 0-23 and head 0 of cyl 45.
# "27-33" specifies all heads of cyls 27-33.
# Number of sectors per track (0-256). Default is 0.
secs = 9
# Bytes per sector (128, 256, 512, 1024, 2048, 4096, 8192).
# Mandatory if @secs is non-zero.
bps = 512
# Alternative form in which bytes per sector is specified per sector.
# The list is comma separated; no white space allowed.
# bps = 512,512,512,512,512,512,512,512,256
# Bytes per sector within the IMG file. Smaller sectors will be padded.
# The default is 0: Sectors occupy precisely their data size; No padding.
# Supported values: 0, 128, 256, 512, 1024, 2048, 4096, 8192.
# img_bps = 0
# ID of first sector on each track (0-255). Default is 1.
# Numbers may be expressed in hexadecimal with 0x prefix (eg. 0xab).
# id = 1
# Head number for all sectors on this track (auto|0|1). Default is auto.
# auto = use physical drive head number
# h = auto
# Recording mode (fm | mfm). Default is mfm.
# mode = mfm
# Sector interleave. Default is 1:1 (no interleave).
# interleave = 1
# Sector skew per cylinders. Default is 0 (no skew).
# cskew = 0
# Sector skew per head. Default is 0 (no skew).
# hskew = 0
# Rotational RPM. Default is 300.
# rpm = 300
# Post-ID Gap (auto|0-255). Default is auto.
# auto = based on recording mode and sector size.
# gap2 = auto
# Post-Data Gap (auto|0-255). Default is auto.
# auto = based on recording mode and sector size.
# gap3 = auto
# Post-Index Gap (auto|0-255). Default is auto.
# auto = based on recording mode and sector size.
# gap4a = auto
# Index Address Mark (yes | no). Default is yes.
# iam = yes
# Data rate in kHz (kbit/s) (eg. MFM DD = 250). Default is 0.
# 0 = based on recording mode and size of track.
# rate = 0
####################################################################
# An example definition for a Kaypro DS/DD 40-track image.
[kaypro-dsdd40]
cyls = 40
heads = 2
interleave = 3
secs = 10
bps = 512
tracks = 0-39.0
id = 0 # Side 0, sector IDs 0..9
tracks = 0-39.1
id = 10 # Side 1, sector IDs 10..19
####################################################################
# An example definition for TSC Flex.
#
# Flex format is double-density but with single-density (FM) cylinder 0.
# Sector numbering and interleave is continuous across drive heads. Since
# there is no direct way to flag this, we implement it here by explicitly
# specifying head 1 track formats: with sector @id following on from head 0,
# and with @hskew shifting the first sector of side 1 the correct amount to
# simulate cross-track interleave.
[flex::733184]
cyls = 80
heads = 2
bps = 256 # All tracks have 256-byte sectors. Number of sectors varies.
tracks = 0.0 ## Boot cylinder, head 0
secs = 10
mode = fm
interleave = 4
id = 1
tracks = 0.1 ## Boot cylinder, head 1
secs = 10
mode = fm
interleave = 4
hskew = 1 # Simulates correct inter-track interleave
id = 11 # Follows on from head 0 (1..10)
tracks = 1-79.0 ## All other cylinders, head 0
secs = 18
mode = mfm
interleave = 6
id = 1
tracks = 1-79.1 ## All other cylinders, head 1
secs = 18
mode = mfm
interleave = 6
hskew = 5 # Simulates correct inter-track interleave
id = 19 # Follows on from head 0 (1..18)

File diff suppressed because it is too large Load diff

File diff suppressed because it is too large Load diff

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@ -1,44 +0,0 @@
/*
* cache.h
*
* In-memory data cache.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
#if !defined(BOOTLOADER)
/* Use memory range (@start,@end) to cache data items of size @item_sz. */
struct cache *cache_init(void *start, void *end, unsigned int item_sz);
/* Look up item @id in the cache. Return a pointer to cached data, or NULL. */
const void *cache_lookup(struct cache *c, uint32_t id);
/* Update item @id with data @dat. Inserts the item if not present.*/
void cache_update(struct cache *c, uint32_t id, const void *dat);
/* Update @N items (@id..@id+@N-1) with data @dat. Calls cache_update(). */
void cache_update_N(struct cache *c, uint32_t id,
const void *dat, unsigned int N);
#else
#define cache_init(a,b,c) NULL
#define cache_lookup(a,b) NULL
#define cache_update(a,b,c) ((void)0)
#define cache_update_N(a,b,c,d) ((void)0)
#endif
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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@ -1,32 +0,0 @@
/*
* cancellation.h
*
* Asynchronously-cancellable function calls.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
struct cancellation {
uint32_t *sp;
};
#define cancellation_is_active(c) ((c)->sp != NULL)
/* Execute fn() in a wrapped cancellable environment. */
int call_cancellable_fn(struct cancellation *c, int (*fn)(void *), void *arg);
/* From IRQ content: stop running fn() and immediately return -1. */
void cancel_call(struct cancellation *c);
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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@ -1,190 +0,0 @@
/*
* config.h
*
* Configuration file parsing.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
struct opt {
const char *name;
};
struct opts {
FIL *file;
const struct opt *opts;
char *arg;
int argmax;
};
int get_next_opt(struct opts *opts);
#define OPT_eof -1
#define OPT_section -2
/* FF.CFG options structure. */
struct packed ff_cfg {
/* Bump version for every incompatible change to structure layout.
* No need to bump for new fields appended to this structure. */
#define FFCFG_VERSION 2
uint8_t version;
/* Size of this structure. This allows simple backward compatibility
* by merging old and new structures of different sizes. */
uint8_t size;
/* interface: FINTF_* interface mode */
#define FINTF_JC 255 /* mode specified by jumper JC */
uint8_t interface; /* FINTF_* interface mode */
char da_report_version[16];
uint8_t autoselect_file_secs;
uint8_t autoselect_folder_secs;
bool_t nav_loop; /* Wrap slot number at 0 and max? */
uint8_t display_off_secs;
#define DISPON_no 0
#define DISPON_yes 1
#define DISPON_sel 2
uint8_t display_on_activity;
uint16_t display_scroll_rate;
#define FONT_6x13 7
#define FONT_8x16 8
uint8_t oled_font; /* FONT_* oled font specifier */
uint8_t step_volume;
uint8_t side_select_glitch_filter;
bool_t ejected_on_startup;
#define IMGS_last 0
#define IMGS_static 1
#define IMGS_init 2
uint8_t image_on_startup;
uint16_t display_probe_ms;
#define TWOBUTTON_zero 0
#define TWOBUTTON_eject 1
#define TWOBUTTON_rotary 2
#define TWOBUTTON_rotary_fast 3
#define TWOBUTTON_htu 4
#define TWOBUTTON_mask 7
#define TWOBUTTON_reverse (1u<<7)
uint8_t twobutton_action;
#define NAVMODE_default 0
#define NAVMODE_indexed 1
#define NAVMODE_native 2
uint8_t nav_mode;
#define TRKCHG_instant 0
#define TRKCHG_realtime 1
uint8_t track_change;
#define HOST_unspecified 0
#define HOST_akai 1
#define HOST_gem 2
#define HOST_ensoniq 3
#define HOST_acorn 4
#define HOST_ti99 5
#define HOST_memotech 6
#define HOST_uknc 7
#define HOST_pc98 8
#define HOST_pc_dos 9
#define HOST_msx 10
#define HOST_dec 11
#define HOST_tandy_coco 12
#define HOST_fluke 13
#define HOST_nascom 15
#define HOST_casio 16
#define HOST_ibm_3174 17
uint8_t host;
/* Bitfields within display_type field. */
#define DISPLAY_auto 0
#define DISPLAY_lcd (1<<0)
#define DISPLAY_oled (1<<1)
/* Only if DISPLAY_oled: */
#define DISPLAY_narrower (1<<0)
#define DISPLAY_rotate (1<<2)
#define DISPLAY_narrow (1<<3)
#define DISPLAY_ztech (1<<4)
#define DISPLAY_oled_64 (1<<5)
#define DISPLAY_inverse (1<<6)
#define DISPLAY_slow (1<<7)
#define DISPLAY_hflip (1<<8)
/* Only if DISPLAY_lcd: */
#define _DISPLAY_lcd_columns 5
#define DISPLAY_lcd_columns(x) ((x)<<_DISPLAY_lcd_columns)
#define _DISPLAY_lcd_rows 11
#define DISPLAY_lcd_rows(x) ((x)<<_DISPLAY_lcd_rows)
uint16_t display_type;
#define ROT_none 0
#define ROT_full 1
#define ROT_half 3
#define ROT_quarter 2
#define ROT_trackball 4
#define ROT_buttons 5
#define ROT_typemask 15
#define ROT_v2 (1u<<6)
#define ROT_reverse (1u<<7)
uint8_t rotary;
bool_t write_protect;
uint16_t nav_scroll_rate;
uint16_t nav_scroll_pause;
uint16_t display_scroll_pause;
bool_t index_suppression;
bool_t extend_image;
#define PIN_auto 0
#define PIN_nc PIN_high
#define PIN_high (outp_nr + 1)
#define PIN_rdy (outp_rdy + 1)
#define PIN_dens (outp_hden + 1)
#define PIN_chg (outp_dskchg + 1)
#define PIN_invert 0x80
#define PIN_low (PIN_high | PIN_invert)
#define PIN_nrdy (PIN_rdy | PIN_invert)
#define PIN_ndens (PIN_dens | PIN_invert)
#define PIN_nchg (PIN_chg | PIN_invert)
uint8_t pin02, pin34;
uint8_t head_settle_ms;
uint8_t oled_contrast;
char indexed_prefix[8];
uint8_t _unused; /* never been used */
#define SORT_never 0
#define SORT_always 1
#define SORT_small 2
uint8_t folder_sort;
#define MOTOR_ignore 0xff
uint8_t motor_delay; /* / 10ms */
#define SORTPRI_folders 0
#define SORTPRI_files 1
#define SORTPRI_none 2
uint8_t sort_priority;
#define CHGRST_step 0xff
#define CHGRST_pa14 0x8e
#define CHGRST_delay(x) (x)
uint8_t chgrst;
#define DORD_default 0xffff
#define DORD_shift 4
#define DORD_row 7
#define DORD_double 8
uint16_t display_order;
#define WDRAIN_instant 0
#define WDRAIN_realtime 1
#define WDRAIN_eot 2
uint8_t write_drain;
uint8_t max_cyl;
uint16_t osd_display_order;
uint8_t osd_columns;
#define NOTIFY_volume_mask 15
#define NOTIFY_slotnr (1<<4)
uint8_t notify_volume;
};
extern struct ff_cfg ff_cfg;
extern const struct ff_cfg dfl_ff_cfg;
void flash_ff_cfg_update(void *scratch);
void flash_ff_cfg_erase(void);
void flash_ff_cfg_read(void);
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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@ -1,49 +0,0 @@
/*
* da.h
*
* Structure definitions for Direct Access protocol.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
#define DA_FIRST_CYL 254
#define DA_SD_FM_CYL (DA_FIRST_CYL + 0)
#define DA_DD_MFM_CYL (DA_FIRST_CYL + 1)
/* Direct-Access Mode: Returned in sector 0 of direct-access track. */
struct packed da_status_sector {
char sig[8];
char fw_ver[12];
uint32_t lba_base;
uint8_t cmd_cnt;
uint8_t read_cnt;
uint8_t write_cnt;
uint8_t last_cmd_status;
uint8_t write_locked;
uint8_t keys_status;
uint8_t sd_status;
uint8_t SD_WP;
uint8_t SD_CD;
uint8_t nr_sec;
uint16_t current_index;
};
/* Direct-Access Mode: Sent to us in sector 0 of direct-access track. */
struct packed da_cmd_sector {
char sig[8];
uint8_t cmd;
uint8_t param[8];
};
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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@ -1,54 +0,0 @@
/*
* decls.h
*
* Pull in all other header files in an orderly fashion. Source files include
* only this header, and only once.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
#include <stdint.h>
#include <stdarg.h>
#include <stddef.h>
#include <limits.h>
#include "types.h"
#include "mcu/common_regs.h"
#include "mcu/common.h"
#if MCU == STM32F105
#include "mcu/stm32f105_regs.h"
#include "mcu/at32f415_regs.h"
#include "mcu/stm32f105.h"
#elif MCU == AT32F435
#include "mcu/at32f435_regs.h"
#include "mcu/at32f435.h"
#endif
#include "intrinsics.h"
#include "time.h"
#include "../src/fatfs/ff.h"
#include "util.h"
#include "list.h"
#include "cache.h"
#include "da.h"
#include "hxc.h"
#include "cancellation.h"
#include "spi.h"
#include "timer.h"
#include "fs.h"
#include "floppy.h"
#include "volume.h"
#include "config.h"
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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@ -1,313 +0,0 @@
/*
* floppy.h
*
* Floppy interface control and image management.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
#define SAMPLECLK_MHZ 72
#define sampleclk_ns(x) (((x) * SAMPLECLK_MHZ) / 1000)
#define sampleclk_us(x) ((x) * SAMPLECLK_MHZ)
#define sampleclk_ms(x) ((x) * SAMPLECLK_MHZ * 1000)
#define sampleclk_stk(x) ((x) * (SAMPLECLK_MHZ / STK_MHZ))
#define stk_sampleclk(x) ((x) / (SAMPLECLK_MHZ / STK_MHZ))
#ifdef QUICKDISK
#define is_quickdisk TRUE
#else
#define is_quickdisk FALSE
#endif
#define FINTF_SHUGART 0
#define FINTF_IBMPC 1
#define FINTF_IBMPC_HDOUT 2
#define FINTF_JPPC_HDOUT 3
#define FINTF_AMIGA 4
#define FINTF_JPPC 5
#define outp_dskchg 0
#define outp_index 1
#define outp_trk0 2
#define outp_wrprot 3
#define outp_rdy 4
#define outp_hden 5
#define outp_nr 6
#define outp_unused outp_nr
#define verbose_image_log FALSE
struct adf_image {
uint32_t trk_off;
uint32_t sec_idx;
int32_t decode_pos;
uint32_t pre_idx_gap_bc;
uint32_t nr_secs;
uint32_t written_secs;
uint8_t sec_map[2][22];
};
struct hfe_image {
uint16_t tlut_base;
uint16_t trk_off;
uint16_t trk_pos, trk_len;
bool_t is_v3, double_step;
uint8_t batch_secs;
struct {
uint16_t start;
bool_t wrapped;
} write;
struct {
uint16_t off, len;
bool_t dirty;
} write_batch;
};
struct qd_image {
uint16_t tb;
uint32_t trk_off;
uint32_t trk_pos, trk_len;
uint32_t win_start, win_end;
struct {
uint32_t start;
bool_t wrapped;
} write;
struct {
uint32_t off, len;
bool_t dirty;
} write_batch;
};
struct raw_sec {
uint8_t r;
uint8_t n; /* 3 bits */
};
struct raw_trk {
uint16_t nr_sectors;
uint16_t sec_off;
uint16_t data_rate;
uint16_t rpm;
uint16_t img_bps; /* could squeeze this field into uint8_t or bitfield */
int16_t gap_2, gap_3, gap_4a;
uint8_t interleave, cskew, hskew;
uint8_t has_iam:1, is_fm:1, invert_data:1;
#define RAW_TRK_HEAD(h) ((h)+1)
uint8_t head:2;
};
struct img_image {
uint32_t trk_off, base_off;
uint16_t trk_sec, rd_sec_pos;
int32_t decode_pos;
uint16_t decode_data_pos, crc;
uint8_t layout; /* LAYOUT_* */
uint8_t post_crc_syncs;
int16_t write_sector;
uint8_t *sec_map, *trk_map;
struct raw_trk *trk, *trk_info;
struct raw_sec *sec_info, *sec_info_base;
/* If not NULL, replaces the default method for finding sector data.
* Sector data is at trk_off + file_sec_offsets[i]. */
uint32_t *file_sec_offsets;
/* Delay start of track this many bitcells past index. */
uint32_t track_delay_bc;
uint16_t gap_4;
uint32_t idx_sz, idam_sz;
uint16_t dam_sz_pre, dam_sz_post;
void *heap_bottom;
};
struct dsk_image {
uint32_t trk_off;
uint16_t trk_pos;
uint16_t rd_sec_pos;
int32_t decode_pos;
uint16_t decode_data_pos, crc;
bool_t extended;
int8_t write_sector;
uint16_t gap4;
uint32_t idx_sz, idam_sz;
uint16_t dam_sz_pre, dam_sz_post;
uint8_t rev;
};
struct directaccess {
struct da_status_sector dass;
int32_t decode_pos;
uint16_t trk_sec;
uint16_t idx_sz, idam_sz, dam_sz;
bool_t lba_set;
};
struct image_buf {
void *p;
uint32_t len;
uint32_t prod, cons;
};
struct image_bufs {
/* Buffering for bitcells being written to disk. */
struct image_buf write_bc;
/* Buffering for bitcells we generate from read_data. */
struct image_buf read_bc;
/* Staging area for writeout to mass storage. */
struct image_buf write_data;
/* Read buffer for track data to be used for generating flux pattern. */
struct image_buf read_data;
};
struct image {
/* Handler for currently-selected type of disk image. */
const struct image_handler *disk_handler;
/* Handler for current track. May differ from the primary disk handler. */
const struct image_handler *track_handler;
/* FatFS. */
FIL fp;
/* Info about image as a whole. */
uint8_t nr_cyls, nr_sides;
uint8_t step;
/* Data buffers. */
struct image_bufs bufs;
struct write {
uint32_t start; /* Ticks past index when current write started */
uint32_t bc_end; /* Final bitcell buffer index */
uint16_t dma_end; /* Final DMA buffer index */
uint16_t track; /* Track written to */
} write[8];
uint16_t wr_cons, wr_bc, wr_prod;
/* Info about current track. */
uint16_t cur_track;
uint16_t write_bc_ticks; /* SAMPLECLK ticks per bitcell in write stream */
uint32_t ticks_per_cell; /* Nr 'ticks' per bitcell in read stream. */
uint32_t tracklen_bc, cur_bc; /* Track length and cursor, in bitcells */
uint32_t tracklen_ticks; /* Timing of previous revolution, in 'ticks' */
uint32_t cur_ticks; /* Offset from index, in 'ticks' */
uint32_t ticks_since_flux; /* Ticks since last flux sample/reversal */
uint32_t write_bc_window; /* Sliding window at head of bitcell stream */
uint32_t stk_per_rev; /* Nr STK ticks per revolution. */
enum { SYNC_none=0, SYNC_fm, SYNC_mfm } sync;
union {
struct adf_image adf;
struct hfe_image hfe;
struct qd_image qd;
struct img_image img;
struct dsk_image dsk;
struct directaccess da;
};
struct slot *slot;
};
static inline struct write *get_write(struct image *im, uint16_t idx)
{
return &im->write[idx & (ARRAY_SIZE(im->write) - 1)];
}
struct image_handler {
bool_t (*open)(struct image *im);
FSIZE_t (*extend)(struct image *im);
void (*setup_track)(
struct image *im, uint16_t track, uint32_t *start_pos);
bool_t (*read_track)(struct image *im);
uint16_t (*rdata_flux)(struct image *im, uint16_t *tbuf, uint16_t nr);
bool_t (*write_track)(struct image *im);
};
/* List of supported image types. */
extern const struct image_type {
char ext[8];
const struct image_handler *handler;
} image_type[];
/* Is given file valid to open as an image? */
bool_t image_valid(FILINFO *fp);
/* Open specified image file on mass storage device. */
void image_open(struct image *im, struct slot *slot, DWORD *cltbl);
/* Extend a trunated image file. */
void image_extend(struct image *im);
/* Seek to given track and start reading track data at specified rotational
* position (specified as number of SAMPLECLK ticks past the index mark).
*
* If start_pos is NULL then the caller is in write mode and thus is not
* interested in fetching data from a particular rotational position.
*
* Returns TRUE if the config file needs to be re-read (exiting D-A mode). */
bool_t image_setup_track(
struct image *im, uint16_t track, uint32_t *start_pos);
/* Read track data into memory. Returns TRUE if any new data was read. */
bool_t image_read_track(struct image *im);
/* Generate flux timings for the RDATA timer and output pin. */
uint16_t image_rdata_flux(struct image *im, uint16_t *tbuf, uint16_t nr);
uint16_t bc_rdata_flux(struct image *im, uint16_t *tbuf, uint16_t nr);
/* Write track data from memory to mass storage. Returns TRUE if processing
* was completed for the write at the tail of the pipeline. */
bool_t image_write_track(struct image *im);
/* Rotational position of last-generated flux (SAMPLECLK ticks past index). */
uint32_t image_ticks_since_index(struct image *im);
/* MFM conversion. */
extern const uint16_t mfmtab[];
static inline uint16_t bintomfm(uint8_t x) { return mfmtab[x]; }
uint8_t mfmtobin(uint16_t x);
void mfm_to_bin(const void *in, void *out, unsigned int nr);
void mfm_ring_to_bin(const uint16_t *ring, unsigned int mask,
unsigned int idx, void *out, unsigned int nr);
#define MFM_DAM_CRC 0xe295 /* 0xa1, 0xa1, 0xa1, 0xfb */
#define FM_DAM_CRC 0xbf84 /* 0xfb */
/* FM conversion. */
#define FM_SYNC_CLK 0xc7
uint16_t fm_sync(uint8_t dat, uint8_t clk);
/* External API. */
void floppy_init(void);
bool_t floppy_ribbon_is_reversed(void);
void floppy_insert(unsigned int unit, struct slot *slot);
void floppy_cancel(void);
bool_t floppy_handle(void); /* TRUE -> re-read config file */
void floppy_set_cyl(uint8_t unit, uint8_t cyl);
struct track_info {
uint8_t cyl, side:1, sel:1, writing:1, in_da_mode:1;
};
void floppy_get_track(struct track_info *ti);
void floppy_set_fintf_mode(void);
void floppy_set_max_cyl(void);
static inline unsigned int im_nphys_cyls(struct image *im)
{
return min_t(unsigned int, im->nr_cyls * (im->step?:1), 255);
}
static inline bool_t in_da_mode(struct image *im, unsigned int cyl)
{
return cyl >= max_t(unsigned int, DA_FIRST_CYL, im_nphys_cyls(im));
}
extern uint32_t motor_chgrst_exti_mask;
void motor_chgrst_setup_exti(void);
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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@ -1,52 +0,0 @@
/*
* fs.h
*
* Error-handling wrappers around FatFS.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
FRESULT F_call_cancellable(int (*fn)(void *), void *arg);
void F_die(FRESULT fr);
FRESULT F_try_open(FIL *fp, const TCHAR *path, BYTE mode);
void F_open(FIL *fp, const TCHAR *path, BYTE mode);
void F_close(FIL *fp);
void F_read(FIL *fp, void *buff, UINT btr, UINT *br);
void F_write(FIL *fp, const void *buff, UINT btw, UINT *bw);
void F_sync(FIL *fp);
void F_lseek(FIL *fp, FSIZE_t ofs);
void F_truncate(FIL *fp);
void F_opendir(DIR *dp, const TCHAR *path);
void F_closedir(DIR *dp);
void F_readdir(DIR *dp, FILINFO *fno);
void F_findfirst(DIR *dp, FILINFO *fno, const TCHAR *path,
const TCHAR *pattern);
void F_findnext(DIR *dp, FILINFO *fno);
void F_chdir(const TCHAR *path);
#if 0
FRESULT f_mkdir(const TCHAR *path);
FRESULT f_rename(const TCHAR *path_old, const TCHAR *path_new);
FRESULT f_stat(const TCHAR *path, FILINFO *fno);
FRESULT f_chmod(const TCHAR *path, BYTE attr, BYTE mask);
FRESULT f_utime(const TCHAR *path, const FILINFO *fno);
FRESULT f_getcwd(TCHAR *buff, UINT len);
FRESULT f_getfree(const TCHAR *path, DWORD *nclst, FATFS* *fatfs);
FRESULT f_mount(FATFS *fs, const TCHAR *path, BYTE opt);
FRESULT f_unlink(const TCHAR *path);
#endif
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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@ -1,77 +0,0 @@
/*
* hxc.h
*
* Structure definitions for HxC compatibility.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
/* HXCSDFE.CFG file header. */
struct packed hxcsdfe_cfg {
char signature[16]; /* "HXCFECFGVx.y" */
uint8_t step_sound;
uint8_t ihm_sound;
uint8_t back_light_tmr;
uint8_t standby_tmr;
uint8_t disable_drive_select;
uint8_t buzzer_duty_cycle;
uint8_t number_of_slot;
uint8_t slot_index;
uint16_t update_cnt;
uint8_t load_last_floppy;
uint8_t buzzer_step_duration;
uint8_t lcd_scroll_speed;
uint8_t startup_mode;
uint8_t enable_drive_b;
uint8_t index_mode;
struct packed {
uint8_t cfg_from_cfg;
uint8_t interfacemode;
uint8_t pin02_cfg;
uint8_t pin34_cfg;
} drive[2];
uint8_t drive_b_as_motor_on;
uint8_t pad[23];
uint32_t slots_map_position;
uint32_t max_slot_number;
uint32_t slots_position;
uint32_t number_of_drive_per_slot;
uint32_t cur_slot_number;
uint32_t ihm_mode;
};
#define HXCSTARTUP_slot0 0x04
#define HXCSTARTUP_ejected 0x10
/* HXCFECFGV1.x slots start at offset 0x400: */
struct packed v1_slot {
char name[12];
uint8_t attributes;
uint32_t firstCluster;
uint32_t size;
char longName[17];
};
/* HXCFECFGV2.x slots start at sector offset 'slots_position': */
struct packed v2_slot {
char type[3];
uint8_t attributes;
uint32_t firstCluster;
uint32_t size;
char name[52];
};
#define short_slot v2_slot
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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@ -1,172 +0,0 @@
/*
* intrinsics.h
*
* Compiler intrinsics for ARMv7-M core.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
struct exception_frame {
uint32_t r0, r1, r2, r3, r12, lr, pc, psr;
};
#define _STR(x) #x
#define STR(x) _STR(x)
/* Force a compilation error if condition is true */
#define BUILD_BUG_ON(cond) ({ _Static_assert(!(cond), "!(" #cond ")"); })
#define aligned(x) __attribute__((aligned(x)))
#define packed __attribute((packed))
#define always_inline __inline__ __attribute__((always_inline))
#define noinline __attribute__((noinline))
#define likely(x) __builtin_expect(!!(x),1)
#define unlikely(x) __builtin_expect(!!(x),0)
#define illegal() asm volatile (".short 0xde00");
#define barrier() asm volatile ("" ::: "memory")
#define cpu_sync() asm volatile("dsb; isb" ::: "memory")
#define cpu_relax() asm volatile ("nop" ::: "memory")
#define sv_call(imm) asm volatile ( "svc %0" : : "i" (imm) )
#define read_special(reg) ({ \
uint32_t __x; \
asm volatile ("mrs %0,"#reg : "=r" (__x) ::); \
__x; \
})
#define write_special(reg,val) ({ \
uint32_t __x = (uint32_t)(val); \
asm volatile ("msr "#reg",%0" :: "r" (__x) :); \
})
/* CONTROL[1] == 0 => running on Master Stack (Exception Handler mode). */
#define CONTROL_SPSEL 2
#define in_exception() (!(read_special(control) & CONTROL_SPSEL))
#define global_disable_exceptions() \
asm volatile ("cpsid f; cpsid i" ::: "memory")
#define global_enable_exceptions() \
asm volatile ("cpsie f; cpsie i" ::: "memory")
/* NB. IRQ disable via CPSID/MSR is self-synchronising. No barrier needed. */
#define IRQ_global_disable() asm volatile ("cpsid i" ::: "memory")
#define IRQ_global_enable() asm volatile ("cpsie i" ::: "memory")
/* Save/restore IRQ priority levels.
* NB. IRQ disable via MSR is self-synchronising. I have confirmed this on
* Cortex-M3: any pending IRQs are handled before they are disabled by
* a BASEPRI update. Hence no barrier is needed here. */
#define IRQ_save(newpri) ({ \
uint8_t __newpri = (newpri)<<4; \
uint8_t __oldpri = read_special(basepri); \
if (!__oldpri || (__oldpri > __newpri)) \
write_special(basepri, __newpri); \
__oldpri; })
/* NB. Same as CPSIE, any pending IRQ enabled by this BASEPRI update may
* execute a couple of instructions after the MSR instruction. This has been
* confirmed on Cortex-M3. */
#define IRQ_restore(oldpri) write_special(basepri, (oldpri))
#define __DEFINE_IRQ(nr, name) \
void IRQ_##nr (void) __attribute__((alias(name)))
#define _DEFINE_IRQ(nr, name) __DEFINE_IRQ(nr, name)
#define DEFINE_IRQ(nr, name) _DEFINE_IRQ(nr, name)
/* Cortex initialisation */
void cortex_init(void);
static inline uint16_t _rev16(uint16_t x)
{
uint16_t result;
asm volatile ("rev16 %0,%1" : "=r" (result) : "r" (x));
return result;
}
static inline uint32_t _rev32(uint32_t x)
{
uint32_t result;
asm volatile ("rev %0,%1" : "=r" (result) : "r" (x));
return result;
}
static inline uint32_t _rbit32(uint32_t x)
{
uint32_t result;
asm volatile ("rbit %0,%1" : "=r" (result) : "r" (x));
return result;
}
extern void __bad_cmpxchg(volatile void *ptr, int size);
static always_inline unsigned long __cmpxchg(
volatile void *ptr, unsigned long old, unsigned long new, int size)
{
unsigned long oldval, res;
switch (size) {
case 1:
do {
asm volatile(" ldrexb %1,[%2] \n"
" movs %0,#0 \n"
" cmp %1,%3 \n"
" it eq \n"
" strexbeq %0,%4,[%2] \n"
: "=&r" (res), "=&r" (oldval)
: "r" (ptr), "Ir" (old), "r" (new)
: "memory", "cc");
} while (res);
break;
case 2:
do {
asm volatile(" ldrexh %1,[%2] \n"
" movs %0,#0 \n"
" cmp %1,%3 \n"
" it eq \n"
" strexheq %0,%4,[%2] \n"
: "=&r" (res), "=&r" (oldval)
: "r" (ptr), "Ir" (old), "r" (new)
: "memory", "cc");
} while (res);
break;
case 4:
do {
asm volatile(" ldrex %1,[%2] \n"
" movs %0,#0 \n"
" cmp %1,%3 \n"
" it eq \n"
" strexeq %0,%4,[%2] \n"
: "=&r" (res), "=&r" (oldval)
: "r" (ptr), "Ir" (old), "r" (new)
: "memory", "cc");
} while (res);
break;
default:
__bad_cmpxchg(ptr, size);
oldval = 0;
}
return oldval;
}
#define cmpxchg(ptr,o,n) \
((__typeof__(*(ptr)))__cmpxchg((ptr), \
(unsigned long)(o), \
(unsigned long)(n), \
sizeof(*(ptr))))
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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@ -1,57 +0,0 @@
/*
* list.h
*
* Doubly linked list.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
struct list_head {
struct list_head *prev, *next;
};
static inline void list_init(struct list_head *head)
{
head->prev = head;
head->next = head;
}
static inline void list_insert_head(
struct list_head *head, struct list_head *ent)
{
ent->next = head->next;
ent->prev = head;
ent->next->prev = head->next = ent;
}
static inline void list_insert_tail(
struct list_head *head, struct list_head *ent)
{
ent->prev = head->prev;
ent->next = head;
ent->prev->next = head->prev = ent;
}
static inline void list_remove(struct list_head *ent)
{
ent->next->prev = ent->prev;
ent->prev->next = ent->next;
}
static inline bool_t list_is_empty(struct list_head *head)
{
return head->next == head;
}
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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@ -1,34 +0,0 @@
/*
* at32f415_regs.h
*
* Extra registers and features of the AT32F415 that we use, over and above
* the baseline features of the STM32F105.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
#define RCC_CFGR_PLLMUL_18 ((uint32_t)0x20040000)
#define RCC_CFGR_USBPSC_3 ((uint32_t)0x08400000)
#define RCC_PLL (&rcc->cfgr2)
#define RCC_PLL_PLLCFGEN (1u<<31)
#define RCC_PLL_FREF_MASK (7u<<24)
#define RCC_PLL_FREF_8M (2u<<24)
static volatile uint32_t * const RCC_MISC2 = (uint32_t *)(RCC_BASE + 0x54);
#define RCC_MISC2_AUTOSTEP_EN (3u<< 4)
#define TIM_CR1_PMEN (1u<<10)
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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@ -1,80 +0,0 @@
/*
* at32f435.h
*
* Core and peripheral registers.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
/* C pointer types */
#define FLASH_BANK volatile struct flash_bank * const
#define SYSCFG volatile struct syscfg * const
#define DMAMUX volatile struct dmamux * const
/* C-accessible registers. */
static STK stk = (struct stk *)STK_BASE;
static SCB scb = (struct scb *)SCB_BASE;
static NVIC nvic = (struct nvic *)NVIC_BASE;
static DBG dbg = (struct dbg *)DBG_BASE;
static FLASH flash = (struct flash *)FLASH_BASE;
static PWR pwr = (struct pwr *)PWR_BASE;
static BKP bkp = (struct bkp *)BKP_BASE;
static RCC rcc = (struct rcc *)RCC_BASE;
static GPIO gpioa = (struct gpio *)GPIOA_BASE;
static GPIO gpiob = (struct gpio *)GPIOB_BASE;
static GPIO gpioc = (struct gpio *)GPIOC_BASE;
static GPIO gpiod = (struct gpio *)GPIOD_BASE;
static GPIO gpioe = (struct gpio *)GPIOE_BASE;
static GPIO gpiof = (struct gpio *)GPIOF_BASE;
static GPIO gpiog = (struct gpio *)GPIOG_BASE;
static GPIO gpioh = (struct gpio *)GPIOH_BASE;
static SYSCFG syscfg = (struct syscfg *)SYSCFG_BASE;
static EXTI exti = (struct exti *)EXTI_BASE;
static DMA dma1 = (struct dma *)DMA1_BASE;
static DMA dma2 = (struct dma *)DMA2_BASE;
static DMAMUX dmamux1 = (struct dmamux *)DMAMUX1_BASE;
static DMAMUX dmamux2 = (struct dmamux *)DMAMUX2_BASE;
static TIM tim1 = (struct tim *)TIM1_BASE;
static TIM tim2 = (struct tim *)TIM2_BASE;
static TIM tim3 = (struct tim *)TIM3_BASE;
static TIM tim4 = (struct tim *)TIM4_BASE;
static TIM tim5 = (struct tim *)TIM5_BASE;
static TIM tim6 = (struct tim *)TIM6_BASE;
static TIM tim7 = (struct tim *)TIM7_BASE;
static SPI spi1 = (struct spi *)SPI1_BASE;
static SPI spi2 = (struct spi *)SPI2_BASE;
static SPI spi3 = (struct spi *)SPI3_BASE;
static I2C i2c1 = (struct i2c *)I2C1_BASE;
static I2C i2c2 = (struct i2c *)I2C2_BASE;
static USART usart1 = (struct usart *)USART1_BASE;
static USART usart2 = (struct usart *)USART2_BASE;
static USART usart3 = (struct usart *)USART3_BASE;
static USB_OTG usb_otg = (struct usb_otg *)USB_OTG_BASE;
/* Clocks */
#define SYSCLK_MHZ 288
#define AHB_MHZ 288
#define APB1_MHZ 144
#define APB2_MHZ 144
/* GPIO */
void gpio_set_af(GPIO gpio, unsigned int pin, unsigned int af);
#define SOFTIRQ_0 85
#define SOFTIRQ_1 86
extern volatile uint32_t _reset_flag;
#define RESET_FLAG_BOOTLOADER 0xdeadbeefu
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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@ -1,421 +0,0 @@
/*
* at32f435_regs.h
*
* Core and peripheral register definitions.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
/* Power control */
struct pwr {
uint32_t cr; /* 00: Power control */
uint32_t csr; /* 04: Power control/status */
uint32_t rsvd[2];
uint32_t ldoov; /* 10: LDO output voltage */
};
#define PWR_LDOOV_1V3 (1u<<0)
#define PWR_BASE 0x40007000
/* Flash memory interface */
struct flash_bank {
uint32_t sr; /* +00: Flash status */
uint32_t cr; /* +04: Flash control */
uint32_t ar; /* +08: Flash address */
};
struct flash {
uint32_t psr; /* 00: Performance select */
uint32_t unlock1; /* 04: Bank 1 unlock */
uint32_t opt_unlock;/* 08: Option bytes unlock */
struct flash_bank bank1;
uint32_t rsvd; /* 18: - */
uint32_t obr; /* 1C: Option byte */
uint32_t epps0; /* 20: Erase/program protection */
uint32_t rsvd2[2]; /* 24-28: - */
uint32_t epps1; /* 2C: Erase/program protection */
uint32_t rsvd3[5]; /* 30-40: - */
uint32_t unlock2; /* 44: Bank 2 unlock */
uint32_t rsvd4; /* 48: - */
struct flash_bank bank2;
uint32_t contr; /* 58: Continue read */
uint32_t rsvd5; /* 5C: - */
uint32_t divr; /* 60: Divider */
};
#define FLASH_SR_EOP (1u<< 5)
#define FLASH_SR_WRPRTERR (1u<< 4)
#define FLASH_SR_PGERR (1u<< 2)
#define FLASH_SR_BSY (1u<< 0)
#define FLASH_CR_EOPIE (1u<<12)
#define FLASH_CR_ERRIE (1u<<10)
#define FLASH_CR_OPTWRE (1u<< 9)
#define FLASH_CR_LOCK (1u<< 7)
#define FLASH_CR_ERASE_STRT (1u<< 6)
#define FLASH_CR_OPTER (1u<< 5)
#define FLASH_CR_OPTPG (1u<< 4)
#define FLASH_CR_SEC_ER (1u<< 3)
#define FLASH_CR_BANK_ER (1u<< 2)
#define FLASH_CR_PG_ER (1u<< 1)
#define FLASH_CR_PG (1u<< 0)
#define FLASH_DIVR_DIV_2 (0u<< 0)
#define FLASH_DIVR_DIV_3 (1u<< 0)
#define FLASH_DIVR_DIV_4 (2u<< 0)
#define FLASH_BASE 0x40023c00
/* Reset and clock control */
struct rcc {
uint32_t cr; /* 00: Clock control */
uint32_t pllcfgr; /* 04: PLL configuration */
uint32_t cfgr; /* 08: Clock configuration */
uint32_t cir; /* 0C: Clock interrupt */
uint32_t ahb1rstr; /* 10: AHB1 peripheral reset */
uint32_t ahb2rstr; /* 14: AHB2 peripheral reset */
uint32_t ahb3rstr; /* 18: AHB3 peripheral reset */
uint32_t _unused0; /* 1C: - */
uint32_t apb1rstr; /* 20: APB1 peripheral reset */
uint32_t apb2rstr; /* 24: APB2 peripheral reset */
uint32_t _unused1; /* 28: - */
uint32_t _unused2; /* 2C: - */
uint32_t ahb1enr; /* 30: AHB1 peripheral clock enable */
uint32_t ahb2enr; /* 34: AHB2 peripheral clock enable */
uint32_t ahb3enr; /* 38: AHB3 peripheral clock enable */
uint32_t _unused3; /* 3C: - */
uint32_t apb1enr; /* 40: APB1 peripheral clock enable */
uint32_t apb2enr; /* 44: APB2 peripheral clock enable */
uint32_t _unused4; /* 48: - */
uint32_t _unused5; /* 4C: - */
uint32_t ahb1lpenr;/* 50: AHB1 peripheral clock enable (low-power mode) */
uint32_t ahb2lpenr;/* 54: AHB2 peripheral clock enable (low-power mode) */
uint32_t ahb3lpenr;/* 58: AHB3 peripheral clock enable (low-power mode) */
uint32_t _unused6; /* 5C: - */
uint32_t apb1lpenr;/* 60: APB1 peripheral clock enable (low-power mode) */
uint32_t apb2lpenr;/* 64: APB2 peripheral clock enable (low-power mode) */
uint32_t _unused7; /* 68: - */
uint32_t _unused8; /* 6C: - */
uint32_t bdcr; /* 70: Backup domain control */
uint32_t csr; /* 74: Clock control & status */
uint32_t _unused9[10]; /* 78-9C: - */
uint32_t misc1; /* A0: Misc 1 */
uint32_t misc2; /* A4: Misc 2 */
};
#define RCC_CR_PLLRDY (1u<<25)
#define RCC_CR_PLLON (1u<<24)
#define RCC_CR_CFDEN (1u<<19)
#define RCC_CR_HSEBYP (1u<<18)
#define RCC_CR_HSERDY (1u<<17)
#define RCC_CR_HSEON (1u<<16)
#define RCC_CR_HSIRDY (1u<<1)
#define RCC_CR_HSION (1u<<0)
#define RCC_PLLCFGR_PLLSRC_HSE (1<<22)
#define PLL_FR_2 1
#define RCC_PLLCFGR_PLL_FR(x) ((x)<<16)
#define RCC_PLLCFGR_PLL_NS(x) ((x)<< 6)
#define RCC_PLLCFGR_PLL_MS(x) ((x)<< 0)
#define RCC_CFGR_MCO2(x) ((x)<<30)
#define RCC_CFGR_MCO2PRE(x) ((x)<<27)
#define RCC_CFGR_USBPRE(x) ((x)<<24)
#define RCC_CFGR_MCO1(x) ((x)<<21)
#define RCC_CFGR_RTCPRE(x) ((x)<<16)
#define RCC_CFGR_PPRE2(x) ((x)<<13)
#define RCC_CFGR_PPRE1(x) ((x)<<10)
#define RCC_CFGR_HPRE(x) ((x)<< 4)
#define RCC_CFGR_SWS(x) ((x)<< 2)
#define RCC_CFGR_SW(x) ((x)<< 0)
#define RCC_AHB1ENR_OTGFS2EN (1u<<29)
#define RCC_AHB1ENR_DMA2EN (1u<<24)
#define RCC_AHB1ENR_DMA1EN (1u<<22)
#define RCC_AHB1ENR_EDMAEN (1u<<21)
#define RCC_AHB1ENR_CRCEN (1u<<12)
#define RCC_AHB1ENR_GPIOHEN (1u<< 7)
#define RCC_AHB1ENR_GPIOGEN (1u<< 6)
#define RCC_AHB1ENR_GPIOFEN (1u<< 5)
#define RCC_AHB1ENR_GPIOEEN (1u<< 4)
#define RCC_AHB1ENR_GPIODEN (1u<< 3)
#define RCC_AHB1ENR_GPIOCEN (1u<< 2)
#define RCC_AHB1ENR_GPIOBEN (1u<< 1)
#define RCC_AHB1ENR_GPIOAEN (1u<< 0)
#define RCC_AHB2ENR_OTGFS1EN (1u<< 7)
#define RCC_AHB2ENR_DVPEN (1u<< 0)
#define RCC_AHB3ENR_QSPI2EN (1u<<14)
#define RCC_AHB3ENR_QSPI1EN (1u<< 1)
#define RCC_AHB3ENR_XMCEN (1u<< 0)
#define RCC_APB1ENR_USART8EN (1u<<31)
#define RCC_APB1ENR_USART7EN (1u<<30)
#define RCC_APB1ENR_DACEN (1u<<29)
#define RCC_APB1ENR_PWREN (1u<<28)
#define RCC_APB1ENR_CAN1EN (1u<<25)
#define RCC_APB1ENR_I2C3EN (1u<<23)
#define RCC_APB1ENR_I2C2EN (1u<<22)
#define RCC_APB1ENR_I2C1EN (1u<<21)
#define RCC_APB1ENR_USART5EN (1u<<20)
#define RCC_APB1ENR_USART4EN (1u<<19)
#define RCC_APB1ENR_USART3EN (1u<<18)
#define RCC_APB1ENR_USART2EN (1u<<17)
#define RCC_APB1ENR_SPI3EN (1u<<15)
#define RCC_APB1ENR_SPI2EN (1u<<14)
#define RCC_APB1ENR_WWDGEN (1u<<11)
#define RCC_APB1ENR_TIM14EN (1u<< 8)
#define RCC_APB1ENR_TIM13EN (1u<< 7)
#define RCC_APB1ENR_TIM12EN (1u<< 6)
#define RCC_APB1ENR_TIM7EN (1u<< 5)
#define RCC_APB1ENR_TIM6EN (1u<< 4)
#define RCC_APB1ENR_TIM5EN (1u<< 3)
#define RCC_APB1ENR_TIM4EN (1u<< 2)
#define RCC_APB1ENR_TIM3EN (1u<< 1)
#define RCC_APB1ENR_TIM2EN (1u<< 0)
#define RCC_APB2ENR_ACCEN (1u<<29)
#define RCC_APB2ENR_TIM20EN (1u<<20)
#define RCC_APB2ENR_TIM11EN (1u<<18)
#define RCC_APB2ENR_TIM10EN (1u<<17)
#define RCC_APB2ENR_TIM9EN (1u<<16)
#define RCC_APB2ENR_SYSCFGEN (1u<<14)
#define RCC_APB2ENR_SPI4EN (1u<<13)
#define RCC_APB2ENR_SPI1EN (1u<<12)
#define RCC_APB2ENR_ADC3EN (1u<<10)
#define RCC_APB2ENR_ADC2EN (1u<< 9)
#define RCC_APB2ENR_ADC1EN (1u<< 8)
#define RCC_APB2ENR_USART6EN (1u<< 5)
#define RCC_APB2ENR_USART1EN (1u<< 4)
#define RCC_APB2ENR_TIM8EN (1u<< 1)
#define RCC_APB2ENR_TIM1EN (1u<< 0)
#define RCC_BDCR_BDRST (1u<<16)
#define RCC_BDCR_RTCEN (1u<<15)
#define RCC_BDCR_RTCSEL(x) ((x)<<8)
#define RCC_BDCR_LSEDRV(x) ((x)<<3)
#define RCC_BDCR_LSEBYP (1u<< 2)
#define RCC_BDCR_LSERDY (1u<< 1)
#define RCC_BDCR_LSEON (1u<< 0)
#define RCC_CSR_LPWRRSTF (1u<<31)
#define RCC_CSR_WWDGRSTF (1u<<30)
#define RCC_CSR_IWDGRSTF (1u<<29)
#define RCC_CSR_SFTRSTF (1u<<28)
#define RCC_CSR_PORRSTF (1u<<27)
#define RCC_CSR_PINRSTF (1u<<26)
#define RCC_CSR_BORRSTF (1u<<25)
#define RCC_CSR_RMVF (1u<<24)
#define RCC_CSR_LSIRDY (1u<< 1)
#define RCC_CSR_LSION (1u<< 0)
#define RCC_MISC2_USBDIV(x) ((x)<<12)
#define USBDIV_6 11
#define RCC_MISC2_AUTOSTEP (3u<< 4)
#define RCC_BASE 0x40023800
/* General-purpose I/O */
struct gpio {
uint32_t moder; /* 00: Port mode */
uint32_t otyper; /* 04: Port output type */
uint32_t odrvr; /* 08: Drive capability */
uint32_t pupdr; /* 0C: Port pull-up/pull-down */
uint32_t idr; /* 10: Port input data */
uint32_t odr; /* 14: Port output data */
uint32_t bsrr; /* 18: Port bit set/reset */
uint32_t lckr; /* 1C: Port configuration lock */
uint32_t afrl; /* 20: Alternate function low */
uint32_t afrh; /* 24: Alternate function high */
uint32_t brr; /* 28: Port bit reset */
uint32_t rsvd[4]; /* 2C-38 */
uint32_t hdrv; /* 3C: Huge current control */
};
/* 0-1: MODE, 2: OTYPE, 3-4:ODRV, 5-6:PUPD, 7:OUTPUT_LEVEL */
#define GPI_analog 0x3u
#define GPI(pupd) (0x0u|((pupd)<<5))
#define PUPD_none 0
#define PUPD_up 1
#define PUPD_down 2
#define GPI_floating GPI(PUPD_none)
#define GPI_pull_down GPI(PUPD_down)
#define GPI_pull_up GPI(PUPD_up)
#define GPO_pushpull(speed,level) (0x1u|((speed)<<3)|((level)<<7))
#define GPO_opendrain(speed,level) (0x5u|((speed)<<3)|((level)<<7))
#define AFI(pupd) (0x2u|((pupd)<<5))
#define AFO_pushpull(speed) (0x2u|((speed)<<3))
#define _AFO_pushpull(speed,level) (0x2u|((speed)<<3)|((level)<<7))
#define AFO_opendrain(speed) (0x6u|((speed)<<3))
#define _2MHz 0
#define _10MHz 0
#define _50MHz 0
#define LOW 0
#define HIGH 1
#define GPIOA_BASE 0x40020000
#define GPIOB_BASE 0x40020400
#define GPIOC_BASE 0x40020800
#define GPIOD_BASE 0x40020C00
#define GPIOE_BASE 0x40021000
#define GPIOF_BASE 0x40021400
#define GPIOG_BASE 0x40021800
#define GPIOH_BASE 0x40021C00
/* System configuration controller */
struct syscfg {
uint32_t cfg1; /* 00: Configuration 1 */
uint32_t cfg2; /* 04: Configuration 2 */
uint32_t exticr[4]; /* 08-14: External interrupt configuration #1-4 */
uint32_t _pad[5];
uint32_t uhdrv; /* 2C: Ultra high source/sink strength */
};
#define SYSCFG_BASE 0x40013800
/* EXTI */
#define EXTI_BASE 0x40013c00
/* DMA */
#define DMA1_CH1_IRQ 56
#define DMA1_CH2_IRQ 57
#define DMA1_CH3_IRQ 58
#define DMA1_CH4_IRQ 59
#define DMA1_CH5_IRQ 60
#define DMA1_CH6_IRQ 68
#define DMA1_CH7_IRQ 69
#define DMA1_BASE 0x40026400
#define DMA2_BASE 0x40026600
/* DMAMUX */
struct dmamux {
uint32_t sel; /* 00: Selection */
uint32_t cctrl[7]; /* 04-1C: Channel control */
uint32_t gctrl[4]; /* 20-2C: Generator control */
uint32_t sync_sts; /* 30: Channel synchronisation status */
uint32_t sync_clr; /* 34: Channel synchronisation clear */
uint32_t g_sts; /* 38: Generator interrupt status */
uint32_t g_clr; /* 3C: Generator interrupt clear */
};
#define DMAMUX_SEL_TBL_SEL (1u<< 0)
#define DMAMUX_CCTRL_REQSEL(x) ((x)<<0)
#define DMAMUX_REQ_I2C2_RX 18
#define DMAMUX_REQ_I2C2_TX 19
#define DMAMUX_REQ_TIM1_CH1 42
#define DMAMUX_REQ_TIM3_OVF 65
#define DMAMUX1_BASE (DMA1_BASE + 0x100)
#define DMAMUX2_BASE (DMA2_BASE + 0x100)
/* Timer */
#define TIM_CR1_PMEN (1u<<10)
#define TIM1_BASE 0x40010000
#define TIM2_BASE 0x40000000
#define TIM3_BASE 0x40000400
#define TIM4_BASE 0x40000800
#define TIM5_BASE 0x40000c00
#define TIM6_BASE 0x40001000
#define TIM7_BASE 0x40001400
#define TIM8_BASE 0x40010400
#define TIM9_BASE 0x40014000
#define TIM10_BASE 0x40014400
#define TIM11_BASE 0x40014800
#define TIM12_BASE 0x40001800
#define TIM13_BASE 0x40001c00
#define TIM14_BASE 0x40002000
/* I2C */
struct i2c {
uint32_t cr1; /* 00: Control 1 */
uint32_t cr2; /* 04: Control 2 */
uint32_t oar1; /* 08: Own address 1 */
uint32_t oar2; /* 0C: Own address 2 */
uint32_t timingr; /* 10: Timing */
uint32_t timeoutr;/* 14: Timeout */
uint32_t isr; /* 18: Interrupt status */
uint32_t icr; /* 1C: Interrupt clear */
uint32_t pecr; /* 20: PEC */
uint32_t rxdr; /* 24: Receive data */
uint32_t txdr; /* 28: Transmit data */
};
#define I2C_CR1_PECEN (1u<<23)
#define I2C_CR1_ALERTEN (1u<<22)
#define I2C_CR1_SMBDEN (1u<<21)
#define I2C_CR1_SMBHEN (1u<<20)
#define I2C_CR1_GCEN (1u<<19)
#define I2C_CR1_NOSTRETCH (1u<<17)
#define I2C_CR1_SBC (1u<<16)
#define I2C_CR1_RXDMAEN (1u<<15)
#define I2C_CR1_TXDMAEN (1u<<14)
#define I2C_CR1_ANFOFF (1u<<12)
#define I2C_CR1_DNF(x) ((x)<<8)
#define I2C_CR1_ERRIE (1u<< 7)
#define I2C_CR1_TCIE (1u<< 6)
#define I2C_CR1_STOPIE (1u<< 5)
#define I2C_CR1_NACKIE (1u<< 4)
#define I2C_CR1_ADDRIE (1u<< 3)
#define I2C_CR1_RXIE (1u<< 2)
#define I2C_CR1_TXIE (1u<< 1)
#define I2C_CR1_PE (1u<< 0)
#define I2C_CR2_PECBYTE (1u<<26)
#define I2C_CR2_AUTOEND (1u<<25)
#define I2C_CR2_RELOAD (1u<<24)
#define I2C_CR2_NBYTES(x) ((x)<<16)
#define I2C_CR2_NACK (1u<<15)
#define I2C_CR2_STOP (1u<<14)
#define I2C_CR2_START (1u<<13)
#define I2C_CR2_HEAD10R (1u<<12)
#define I2C_CR2_ADD10 (1u<<11)
#define I2C_CR2_RD_WRN (1u<<10)
#define I2C_CR2_SADD(x) ((x)<<0)
/* Based on 144MHz peripheral clock */
#define I2C_TIMING_100k 0x80504C4E
#define I2C_TIMING_400k 0x40301B28
#define I2C_SR_ERRORS 0x1f10
#define I2C_SR_BUSY (1u<<15)
#define I2C_SR_ALERT (1u<<13)
#define I2C_SR_TIMEOUT (1u<<12)
#define I2C_SR_PECERR (1u<<11)
#define I2C_SR_OVR (1u<<10)
#define I2C_SR_ARLO (1u<< 9)
#define I2C_SR_BERR (1u<< 8)
#define I2C_SR_TCR (1u<< 7)
#define I2C_SR_TC (1u<< 6)
#define I2C_SR_STOPF (1u<< 5)
#define I2C_SR_NACKF (1u<< 4)
#define I2C_SR_ADDR (1u<< 3)
#define I2C_SR_RXNE (1u<< 2)
#define I2C_SR_TXIS (1u<< 1)
#define I2C_SR_TXE (1u<< 0)
#define I2C1_BASE 0x40005400
#define I2C2_BASE 0x40005800
/* USART */
#define USART1_BASE 0x40011000
#define USART2_BASE 0x40004400
#define USART3_BASE 0x40004800
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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/*
* common.h
*
* Core and peripheral registers.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
/* C pointer types */
#define STK volatile struct stk * const
#define SCB volatile struct scb * const
#define NVIC volatile struct nvic * const
#define DBG volatile struct dbg * const
#define FLASH volatile struct flash * const
#define PWR volatile struct pwr * const
#define BKP volatile struct bkp * const
#define RCC volatile struct rcc * const
#define GPIO volatile struct gpio * const
#define EXTI volatile struct exti * const
#define DMA volatile struct dma * const
#define TIM volatile struct tim * const
#define SPI volatile struct spi * const
#define I2C volatile struct i2c * const
#define USART volatile struct usart * const
#define USB_OTG volatile struct usb_otg * const
/* NVIC table */
extern uint32_t vector_table[];
/* System */
void stm32_init(void);
void system_reset(void) __attribute__((noreturn));
extern bool_t is_artery_mcu;
/* Clocks */
#define SYSCLK (SYSCLK_MHZ * 1000000)
#define sysclk_ns(x) (((x) * SYSCLK_MHZ) / 1000)
#define sysclk_us(x) ((x) * SYSCLK_MHZ)
#define sysclk_ms(x) ((x) * SYSCLK_MHZ * 1000)
#define sysclk_stk(x) ((x) * (SYSCLK_MHZ / STK_MHZ))
/* SysTick Timer */
#define STK_MHZ (SYSCLK_MHZ / 8)
void delay_ticks(unsigned int ticks);
void delay_ns(unsigned int ns);
void delay_us(unsigned int us);
void delay_ms(unsigned int ms);
typedef uint32_t stk_time_t;
#define stk_now() (stk->val)
#define stk_diff(x,y) (((x)-(y)) & STK_MASK) /* d = y - x */
#define stk_add(x,d) (((x)-(d)) & STK_MASK) /* y = x + d */
#define stk_sub(x,d) (((x)+(d)) & STK_MASK) /* y = x - d */
#define stk_timesince(x) stk_diff(x,stk_now())
#define stk_us(x) ((x) * STK_MHZ)
#define stk_ms(x) stk_us((x) * 1000)
#define stk_sysclk(x) ((x) / (SYSCLK_MHZ / STK_MHZ))
/* NVIC */
#define IRQx_enable(x) do { \
barrier(); \
nvic->iser[(x)>>5] = 1u<<((x)&31); \
} while (0)
#define IRQx_disable(x) do { \
nvic->icer[(x)>>5] = 1u<<((x)&31); \
cpu_sync(); \
} while (0)
#define IRQx_is_enabled(x) ((nvic->iser[(x)>>5]>>((x)&31))&1)
#define IRQx_set_pending(x) (nvic->ispr[(x)>>5] = 1u<<((x)&31))
#define IRQx_clear_pending(x) (nvic->icpr[(x)>>5] = 1u<<((x)&31))
#define IRQx_is_pending(x) ((nvic->ispr[(x)>>5]>>((x)&31))&1)
#define IRQx_set_prio(x,y) (nvic->ipr[x] = (y) << 4)
#define IRQx_get_prio(x) (nvic->ipr[x] >> 4)
/* GPIO */
struct gpio;
void gpio_configure_pin(GPIO gpio, unsigned int pin, unsigned int mode);
#define gpio_write_pin(gpio, pin, level) \
((gpio)->bsrr = ((level) ? 0x1u : 0x10000u) << (pin))
#define gpio_write_pins(gpio, mask, level) \
((gpio)->bsrr = (uint32_t)(mask) << ((level) ? 0 : 16))
#define gpio_read_pin(gpio, pin) (((gpio)->idr >> (pin)) & 1)
/* EXTI */
void _exti_route(unsigned int px, unsigned int pin);
#define exti_route_pa(pin) _exti_route(0, pin)
#define exti_route_pb(pin) _exti_route(1, pin)
#define exti_route_pc(pin) _exti_route(2, pin)
/* FPEC */
void fpec_init(void);
void fpec_page_erase(uint32_t flash_address);
void fpec_write(const void *data, unsigned int size, uint32_t flash_address);
#define FLASH_PAGE_SIZE 2048
extern unsigned int flash_page_size;
extern unsigned int ram_kb;
extern uint8_t mcu_package;
enum { MCU_LQFP64=0, MCU_LQFP48, MCU_QFN32 };
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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/*
* common_regs.h
*
* Core and peripheral register definitions.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
/* SysTick timer */
struct stk {
uint32_t ctrl; /* 00: Control and status */
uint32_t load; /* 04: Reload value */
uint32_t val; /* 08: Current value */
uint32_t calib; /* 0C: Calibration value */
};
#define STK_CTRL_COUNTFLAG (1u<<16)
#define STK_CTRL_CLKSOURCE (1u<< 2)
#define STK_CTRL_TICKINT (1u<< 1)
#define STK_CTRL_ENABLE (1u<< 0)
#define STK_MASK ((1u<<24)-1)
#define STK_BASE 0xe000e010
/* System control block */
struct scb {
uint32_t cpuid; /* 00: CPUID base */
uint32_t icsr; /* 04: Interrupt control and state */
uint32_t vtor; /* 08: Vector table offset */
uint32_t aircr; /* 0C: Application interrupt and reset control */
uint32_t scr; /* 10: System control */
uint32_t ccr; /* 14: Configuration and control */
uint32_t shpr1; /* 18: System handler priority reg #1 */
uint32_t shpr2; /* 1C: system handler priority reg #2 */
uint32_t shpr3; /* 20: System handler priority reg #3 */
uint32_t shcsr; /* 24: System handler control and state */
uint32_t cfsr; /* 28: Configurable fault status */
uint32_t hfsr; /* 2C: Hard fault status */
uint32_t _unused; /* 30: - */
uint32_t mmar; /* 34: Memory management fault address */
uint32_t bfar; /* 38: Bus fault address */
};
#define SCB_CCR_STKALIGN (1u<<9)
#define SCB_CCR_BFHFNMIGN (1u<<8)
#define SCB_CCR_DIV_0_TRP (1u<<4)
#define SCB_CCR_UNALIGN_TRP (1u<<3)
#define SCB_CCR_USERSETMPEND (1u<<1)
#define SCB_CCR_NONBASETHRDENA (1u<<0)
#define SCB_SHCSR_USGFAULTENA (1u<<18)
#define SCB_SHCSR_BUSFAULTENA (1u<<17)
#define SCB_SHCSR_MEMFAULTENA (1u<<16)
#define SCB_SHCSR_SVCALLPENDED (1u<<15)
#define SCB_SHCSR_BUSFAULTPENDED (1u<<14)
#define SCB_SHCSR_MEMFAULTPENDED (1u<<13)
#define SCB_SHCSR_USGFAULTPENDED (1u<<12)
#define SCB_SHCSR_SYSTICKACT (1u<<11)
#define SCB_SHCSR_PENDSVACT (1u<<10)
#define SCB_SHCSR_MONITORACT (1u<< 8)
#define SCB_SHCSR_SVCALLACT (1u<< 7)
#define SCB_SHCSR_USGFAULTACT (1u<< 3)
#define SCB_SHCSR_BUSFAULTACT (1u<< 1)
#define SCB_SHCSR_MEMFAULTACT (1u<< 0)
#define SCB_CFSR_DIVBYZERO (1u<<25)
#define SCB_CFSR_UNALIGNED (1u<<24)
#define SCB_CFSR_NOCP (1u<<19)
#define SCB_CFSR_INVPC (1u<<18)
#define SCB_CFSR_INVSTATE (1u<<17)
#define SCB_CFSR_UNDEFINSTR (1u<<16)
#define SCB_CFSR_BFARVALID (1u<<15)
#define SCB_CFSR_STKERR (1u<<12)
#define SCB_CFSR_UNSTKERR (1u<<11)
#define SCB_CFSR_IMPRECISERR (1u<<10)
#define SCB_CFSR_PRECISERR (1u<< 9)
#define SCB_CFSR_IBUSERR (1u<< 8)
#define SCB_CFSR_MMARVALID (1u<< 7)
#define SCB_CFSR_MSTKERR (1u<< 4)
#define SCB_CFSR_MUNSTKERR (1u<< 3)
#define SCB_CFSR_DACCVIOL (1u<< 1)
#define SCB_CFSR_IACCVIOL (1u<< 0)
#define SCB_AIRCR_VECTKEY (0x05fau<<16)
#define SCB_AIRCR_SYSRESETREQ (1u<<2)
#define SCB_BASE 0xe000ed00
/* Nested vectored interrupt controller */
struct nvic {
uint32_t iser[32]; /* 00: Interrupt set-enable */
uint32_t icer[32]; /* 80: Interrupt clear-enable */
uint32_t ispr[32]; /* 100: Interrupt set-pending */
uint32_t icpr[32]; /* 180: Interrupt clear-pending */
uint32_t iabr[64]; /* 200: Interrupt active */
uint8_t ipr[100]; /* 300: Interrupt priority */
};
#define NVIC_BASE 0xe000e100
struct dbg {
uint32_t mcu_idcode; /* 00: MCU ID code */
uint32_t mcu_cr; /* 04: Debug MCU configuration */
};
#define DBG_BASE 0xe0042000
/* Backup */
struct bkp {
uint32_t _0[1]; /* 00: - */
uint32_t dr1[10]; /* 04-28: Data block #1 */
uint32_t rtccr; /* 2C: RTC clock calibration */
uint32_t cr; /* 30: Control */
uint32_t csr; /* 34: Control/status */
uint32_t _1[2]; /* 38-3C: - */
uint32_t dr2[32]; /* 40-BC: Data block #2 */
};
#define BKP_BASE 0x40006c00
/* EXTI */
struct exti {
uint32_t imr; /* 00: Interrupt mask */
uint32_t emr; /* 04: Event mask */
uint32_t rtsr; /* 08: Rising trigger selection */
uint32_t ftsr; /* 0C: Falling trigger selection */
uint32_t swier; /* 10: Software interrupt event */
uint32_t pr; /* 14: Pending */
};
/* DMA */
struct dma_chn {
uint32_t ccr; /* +00: Configuration */
uint32_t cndtr; /* +04: Number of data */
uint32_t cpar; /* +08: Peripheral address */
uint32_t cmar; /* +0C: Memory address */
uint32_t rsvd; /* +10: - */
};
struct dma {
uint32_t isr; /* 00: Interrupt status */
uint32_t ifcr; /* 04: Interrupt flag clear */
struct dma_chn ch[7];
};
/* n=1..7 */
#define DMA_ISR_TEIF(n) (8u<<(((n)-1)*4))
#define DMA_ISR_HTIF(n) (4u<<(((n)-1)*4))
#define DMA_ISR_TCIF(n) (2u<<(((n)-1)*4))
#define DMA_ISR_GIF(n) (1u<<(((n)-1)*4))
/* n=1..7 */
#define DMA_IFCR_CTEIF(n) (8u<<(((n)-1)*4))
#define DMA_IFCR_CHTIF(n) (4u<<(((n)-1)*4))
#define DMA_IFCR_CTCIF(n) (2u<<(((n)-1)*4))
#define DMA_IFCR_CGIF(n) (1u<<(((n)-1)*4))
#define DMA_CCR_MEM2MEM (1u<<14)
#define DMA_CCR_PL_LOW (0u<<12)
#define DMA_CCR_PL_MEDIUM (1u<<12)
#define DMA_CCR_PL_HIGH (2u<<12)
#define DMA_CCR_PL_V_HIGH (3u<<12)
#define DMA_CCR_MSIZE_8BIT (0u<<10)
#define DMA_CCR_MSIZE_16BIT (1u<<10)
#define DMA_CCR_MSIZE_32BIT (2u<<10)
#define DMA_CCR_PSIZE_8BIT (0u<< 8)
#define DMA_CCR_PSIZE_16BIT (1u<< 8)
#define DMA_CCR_PSIZE_32BIT (2u<< 8)
#define DMA_CCR_MINC (1u<< 7)
#define DMA_CCR_PINC (1u<< 6)
#define DMA_CCR_CIRC (1u<< 5)
#define DMA_CCR_DIR_P2M (0u<< 4)
#define DMA_CCR_DIR_M2P (1u<< 4)
#define DMA_CCR_TEIE (1u<< 3)
#define DMA_CCR_HTIE (1u<< 2)
#define DMA_CCR_TCIE (1u<< 1)
#define DMA_CCR_EN (1u<< 0)
/* Timer */
struct tim {
uint32_t cr1; /* 00: Control 1 */
uint32_t cr2; /* 04: Control 2 */
uint32_t smcr; /* 08: Slave mode control */
uint32_t dier; /* 0C: DMA/interrupt enable */
uint32_t sr; /* 10: Status */
uint32_t egr; /* 14: Event generation */
uint32_t ccmr1; /* 18: Capture/compare mode 1 */
uint32_t ccmr2; /* 1C: Capture/compare mode 2 */
uint32_t ccer; /* 20: Capture/compare enable */
uint32_t cnt; /* 24: Counter */
uint32_t psc; /* 28: Prescaler */
uint32_t arr; /* 2C: Auto-reload */
uint32_t rcr; /* 30: Repetition counter */
uint32_t ccr1; /* 34: Capture/compare 1 */
uint32_t ccr2; /* 38: Capture/compare 2 */
uint32_t ccr3; /* 3C: Capture/compare 3 */
uint32_t ccr4; /* 40: Capture/compare 4 */
uint32_t bdtr; /* 44: Break and dead-time */
uint32_t dcr; /* 48: DMA control */
uint32_t dmar; /* 4C: DMA address for full transfer */
};
#define TIM_CR1_ARPE (1u<<7)
#define TIM_CR1_DIR (1u<<4)
#define TIM_CR1_OPM (1u<<3)
#define TIM_CR1_URS (1u<<2)
#define TIM_CR1_UDIS (1u<<1)
#define TIM_CR1_CEN (1u<<0)
#define TIM_CR2_TI1S (1u<<7)
#define TIM_CR2_CCDS (1u<<3)
#define TIM_DIER_TDE (1u<<14)
#define TIM_DIER_CC4DE (1u<<12)
#define TIM_DIER_CC3DE (1u<<11)
#define TIM_DIER_CC2DE (1u<<10)
#define TIM_DIER_CC1DE (1u<<9)
#define TIM_DIER_UDE (1u<<8)
#define TIM_DIER_TIE (1u<<6)
#define TIM_DIER_CC4IE (1u<<4)
#define TIM_DIER_CC3IE (1u<<3)
#define TIM_DIER_CC2IE (1u<<2)
#define TIM_DIER_CC1IE (1u<<1)
#define TIM_DIER_UIE (1u<<0)
#define TIM_SR_CC4OF (1u<<12)
#define TIM_SR_CC3OF (1u<<11)
#define TIM_SR_CC2OF (1u<<10)
#define TIM_SR_CC1OF (1u<<9)
#define TIM_SR_TIF (1u<<6)
#define TIM_SR_CC4IF (1u<<4)
#define TIM_SR_CC3IF (1u<<3)
#define TIM_SR_CC2IF (1u<<2)
#define TIM_SR_CC1IF (1u<<1)
#define TIM_SR_UIF (1u<<0)
#define TIM_EGR_TG (1u<<6)
#define TIM_EGR_CC4G (1u<<4)
#define TIM_EGR_CC3G (1u<<3)
#define TIM_EGR_CC2G (1u<<2)
#define TIM_EGR_CC1G (1u<<1)
#define TIM_EGR_UG (1u<<0)
#define TIM_CCMR1_OC2CE (1u <<15)
#define TIM_CCMR1_OC2M(x) ((x)<<12)
#define TIM_CCMR1_OC2PE (1u <<11)
#define TIM_CCMR1_OC2FE (1u <<10)
#define TIM_CCMR1_CC2S(x) ((x)<< 8)
#define TIM_CCMR1_OC1CE (1u << 7)
#define TIM_CCMR1_OC1M(x) ((x)<< 4)
#define TIM_CCMR1_OC1PE (1u << 3)
#define TIM_CCMR1_OC1FE (1u << 2)
#define TIM_CCMR1_CC1S(x) ((x)<< 0)
#define TIM_CCMR1_IC2F(x) ((x)<<12)
#define TIM_CCMR1_IC2PSC(x) ((x)<<10)
#define TIM_CCMR1_IC1F(x) ((x)<< 4)
#define TIM_CCMR1_IC1PSC(x) ((x)<< 2)
#define TIM_CCMR2_OC4CE (1u <<15)
#define TIM_CCMR2_OC4M(x) ((x)<<12)
#define TIM_CCMR2_OC4PE (1u <<11)
#define TIM_CCMR2_OC4FE (1u <<10)
#define TIM_CCMR2_CC4S(x) ((x)<< 8)
#define TIM_CCMR2_OC3CE (1u << 7)
#define TIM_CCMR2_OC3M(x) ((x)<< 4)
#define TIM_CCMR2_OC3PE (1u << 3)
#define TIM_CCMR2_OC3FE (1u << 2)
#define TIM_CCMR2_CC3S(x) ((x)<< 0)
#define TIM_CCMR2_IC4F(x) ((x)<<12)
#define TIM_CCMR2_IC4PSC(x) ((x)<<10)
#define TIM_CCMR2_IC3F(x) ((x)<< 4)
#define TIM_CCMR2_IC3PSC(x) ((x)<< 2)
#define TIM_OCM_FROZEN (0u)
#define TIM_OCM_SET_HIGH (1u)
#define TIM_OCM_SET_LOW (2u)
#define TIM_OCM_TOGGLE (3u)
#define TIM_OCM_FORCE_LOW (4u)
#define TIM_OCM_FORCE_HIGH (5u)
#define TIM_OCM_PWM1 (6u)
#define TIM_OCM_PWM2 (7u)
#define TIM_OCM_MASK (7u)
#define TIM_CCS_OUTPUT (0u)
#define TIM_CCS_INPUT_TI1 (1u)
#define TIM_CCS_INPUT_TI2 (2u)
#define TIM_CCS_INPUT_TRC (3u)
#define TIM_CCS_MASK (3u)
#define TIM_CCER_CC4P (1u<<13)
#define TIM_CCER_CC4E (1u<<12)
#define TIM_CCER_CC3P (1u<< 9)
#define TIM_CCER_CC3E (1u<< 8)
#define TIM_CCER_CC2P (1u<< 5)
#define TIM_CCER_CC2E (1u<< 4)
#define TIM_CCER_CC1P (1u<< 1)
#define TIM_CCER_CC1E (1u<< 0)
#define TIM_BDTR_MOE (1u<<15)
#define TIM_BDTR_AOE (1u<<14)
#define TIM_BDTR_BKP (1u<<13)
#define TIM_BDTR_BKE (1u<<12)
#define TIM_BDTR_OSSR (1u<<11)
#define TIM_BDTR_OSSI (1u<<10)
#define TIM_BDTR_LOCK(x) ((x)<<8)
#define TIM_BDTR_DTG(x) ((x)<<0)
/* SPI/I2S */
struct spi {
uint32_t cr1; /* 00: Control 1 */
uint32_t cr2; /* 04: Control 2 */
uint32_t sr; /* 08: Status */
uint32_t dr; /* 0C: Data */
uint32_t crcpr; /* 10: CRC polynomial */
uint32_t rxcrcr; /* 14: RX CRC */
uint32_t txcrcr; /* 18: TX CRC */
uint32_t i2scfgr; /* 1C: I2S configuration */
uint32_t i2spr; /* 20: I2S prescaler */
};
#define SPI_BR_DIV2 0
#define SPI_BR_DIV4 1
#define SPI_BR_DIV8 2
#define SPI_BR_DIV16 3
#define SPI_BR_DIV32 4
#define SPI_BR_DIV64 5
#define SPI_BR_DIV128 6
#define SPI_BR_DIV256 7
#define SPI_BR_DIV512 8
#define SPI_BR_DIV1024 9
#define SPI_CR1_BIDIMODE (1u<<15)
#define SPI_CR1_BIDIOE (1u<<14)
#define SPI_CR1_CRCEN (1u<<13)
#define SPI_CR1_CRCNEXT (1u<<12)
#define SPI_CR1_DFF (1u<<11)
#define SPI_CR1_RXONLY (1u<<10)
#define SPI_CR1_SSM (1u<< 9)
#define SPI_CR1_SSI (1u<< 8)
#define SPI_CR1_LSBFIRST (1u<< 7)
#define SPI_CR1_SPE (1u<< 6)
#define SPI_CR1_MSTR (1u<< 2)
#define SPI_CR1_CPOL (1u<< 1)
#define SPI_CR1_CPHA (1u<< 0)
#define SPI_CR2_TXEIE (1u<< 7)
#define SPI_CR2_RXNEIE (1u<< 6)
#define SPI_CR2_ERRIE (1u<< 5)
#define SPI_CR2_SSOE (1u<< 2)
#define SPI_CR2_TXDMAEN (1u<< 1)
#define SPI_CR2_RXDMAEN (1u<< 0)
#define SPI_SR_BSY (1u<< 7)
#define SPI_SR_OVR (1u<< 6)
#define SPI_SR_MODF (1u<< 5)
#define SPI_SR_CRCERR (1u<< 4)
#define SPI_SR_USR (1u<< 3)
#define SPI_SR_CHSIDE (1u<< 2)
#define SPI_SR_TXE (1u<< 1)
#define SPI_SR_RXNE (1u<< 0)
#define SPI1_BASE 0x40013000
#define SPI2_BASE 0x40003800
#define SPI3_BASE 0x40003C00
/* USART */
struct usart {
uint32_t sr; /* 00: Status */
uint32_t dr; /* 04: Data */
uint32_t brr; /* 08: Baud rate */
uint32_t cr1; /* 0C: Control 1 */
uint32_t cr2; /* 10: Control 2 */
uint32_t cr3; /* 14: Control 3 */
uint32_t gtpr; /* 18: Guard time and prescaler */
};
#define USART_SR_CTS (1u<<9)
#define USART_SR_LBD (1u<<8)
#define USART_SR_TXE (1u<<7)
#define USART_SR_TC (1u<<6)
#define USART_SR_RXNE (1u<<5)
#define USART_SR_IDLE (1u<<4)
#define USART_SR_ORE (1u<<3)
#define USART_SR_NE (1u<<2)
#define USART_SR_FE (1u<<1)
#define USART_SR_PE (1u<<0)
#define USART_CR1_UE (1u<<13)
#define USART_CR1_M (1u<<12)
#define USART_CR1_WAKE (1u<<11)
#define USART_CR1_PCE (1u<<10)
#define USART_CR1_PS (1u<< 9)
#define USART_CR1_PEIE (1u<< 8)
#define USART_CR1_TXEIE (1u<< 7)
#define USART_CR1_TCIE (1u<< 6)
#define USART_CR1_RXNEIE (1u<< 5)
#define USART_CR1_IDLEIE (1u<< 4)
#define USART_CR1_TE (1u<< 3)
#define USART_CR1_RE (1u<< 2)
#define USART_CR1_RWU (1u<< 1)
#define USART_CR1_SBK (1u<< 0)
#define USART_CR3_CTSIE (1u<<10)
#define USART_CR3_CTSE (1u<< 9)
#define USART_CR3_RTSE (1u<< 8)
#define USART_CR3_DMAT (1u<< 7)
#define USART_CR3_DMAR (1u<< 6)
#define USART_CR3_SCEN (1u<< 5)
#define USART_CR3_NACK (1u<< 4)
#define USART_CR3_HDSEL (1u<< 3)
#define USART_CR3_IRLP (1u<< 2)
#define USART_CR3_IREN (1u<< 1)
#define USART_CR3_EIE (1u<< 0)
/* USB On-The-Go Full Speed interface */
struct usb_otg {
uint32_t gotctl; /* 00: Control and status */
uint32_t gotgint; /* 04: Interrupt */
uint32_t gahbcfg; /* 08: AHB configuration */
uint32_t gusbcfg; /* 0C: USB configuration */
uint32_t grstctl; /* 10: Reset */
uint32_t gintsts; /* 14: Core interrupt */
uint32_t gintmsk; /* 18: Interrupt mask */
uint32_t grxstsr; /* 1C: Receive status debug read */
uint32_t grxstsp; /* 20: Receive status debug pop */
uint32_t grxfsiz; /* 24: Receive FIFO size */
union {
uint32_t hnptxfsiz; /* 28: Host non-periodic transmit FIFO size */
uint32_t dieptxf0; /* 28: Endpoint 0 transmit FIFO size */
};
uint32_t hnptxsts; /* 2C: Non-periodic transmit FIFO/queue status */
uint32_t _0[2];
uint32_t gccfg; /* 38: General core configuration */
uint32_t cid; /* 3C: Core ID */
uint32_t _1[48];
uint32_t hptxfsiz; /* 100: Host periodic transmit FIFO size */
uint32_t dieptxf1; /* 104: Device IN endpoint transmit FIFO #1 size */
uint32_t dieptxf2; /* 108: Device IN endpoint transmit FIFO #2 size */
uint32_t dieptxf3; /* 10C: Device IN endpoint transmit FIFO #3 size */
uint32_t _2[188];
uint32_t hcfg; /* 400: Host configuration */
uint32_t hfir; /* 404: Host frame interval */
uint32_t hfnum; /* 408: Host frame number / frame time remaining */
uint32_t _3[1]; /* 40C: */
uint32_t hptxsts; /* 410: Host periodic transmit FIFO / queue status */
uint32_t haint; /* 414: Host all channels interrupt status */
uint32_t haintmsk; /* 418: Host all channels interrupt mask */
uint32_t _4[9];
uint32_t hprt; /* 440: Host port control and status */
uint32_t _5[47];
struct {
uint32_t charac; /* +00: Host channel-x characteristics */
uint32_t _0[1];
uint32_t intsts; /* +08: Host channel-x interrupt status */
uint32_t intmsk; /* +0C: Host channel-x interrupt mask */
uint32_t tsiz; /* +10: Host channel x transfer size */
uint32_t _1[3];
} hc[8]; /* 500..5E0: */
uint32_t _6[128];
uint32_t dcfg; /* 800: Device configuration */
uint32_t dctl; /* 804: Device control */
uint32_t dsts; /* 808: Device status */
uint32_t _7[1];
uint32_t diepmsk; /* 810: Device IN endpoint common interrupt mask */
uint32_t doepmsk; /* 814: Device OUT endpoint common interrupt mask */
uint32_t daint; /* 818: Device all endpoints interrupt status */
uint32_t daintmsk; /* 81C: Device all endpoints interrupt mask */
uint32_t _8[2];
uint32_t dvbusdis; /* 828: Device VBUS discharge time */
uint32_t dvbuspulse; /* 82C: Device VBUS pulsing time */
uint32_t _9[1];
uint32_t diepempmsk; /* 834: Device IN endpoint FIFO empty int. mask */
uint32_t _10[50];
struct {
uint32_t ctl; /* +00: Device IN endpoint-x control */
uint32_t _0[1];
uint32_t intsts; /* +08: Device IN endpoint-x interrupt status */
uint32_t _1[3];
uint32_t txfsts; /* +18: Device IN endpoint-x transmit FIFO status */
uint32_t _2[1];
} diep[4]; /* 900..960: */
uint32_t _11[96];
struct {
uint32_t ctl; /* +00: Device OUT endpoint-x control */
uint32_t _0[1];
uint32_t intsts; /* +08: Device OUT endpoint-x interrupt status */
uint32_t _1[1];
uint32_t tsiz; /* +10: Device OUT endpoint-x transmit FIFO status */
uint32_t _2[3];
} doep[4]; /* B00..B60: */
uint32_t _12[160];
uint32_t pcgcctl; /* E00: Power and clock gating control */
};
#define OTG_GAHBCFG_PTXFELVL (1u<< 8)
#define OTG_GAHBCFG_TXFELVL (1u<< 7)
#define OTG_GAHBCFG_GINTMSK (1u<< 0)
#define OTG_GUSBCFG_CTXPKT (1u<<31)
#define OTG_GUSBCFG_FDMOD (1u<<30)
#define OTG_GUSBCFG_FHMOD (1u<<29)
#define OTG_GUSBCFG_TRDT(x) ((x)<<10)
#define OTG_GUSBCFG_HNPCAP (1u<< 9)
#define OTG_GUSBCFG_SRPCAP (1u<< 8)
#define OTG_GUSBCFG_PHYSEL (1u<< 6)
#define OTG_GUSBCFG_TOCAL(x) ((x)<< 0)
/* GINTSTS and GINTMSK */
#define OTG_GINT_WKUPINT (1u<<31) /* Host + Device */
#define OTG_GINT_SRQINT (1u<<30) /* H + D */
#define OTG_GINT_DISCINT (1u<<29) /* H */
#define OTG_GINT_CIDSCHG (1u<<28) /* H + D */
#define OTG_GINT_PTXFE (1u<<26) /* H */
#define OTG_GINT_HCINT (1u<<25) /* H */
#define OTG_GINT_HPRTINT (1u<<24) /* H */
#define OTG_GINT_IPXFR (1u<<21) /* H */
#define OTG_GINT_IISOIXFR (1u<<20) /* D */
#define OTG_GINT_OEPINT (1u<<19) /* D */
#define OTG_GINT_IEPINT (1u<<18) /* D */
#define OTG_GINT_EOPF (1u<<15) /* D */
#define OTG_GINT_ISOODRP (1u<<14) /* D */
#define OTG_GINT_ENUMDNE (1u<<13) /* D */
#define OTG_GINT_USBRST (1u<<12) /* D */
#define OTG_GINT_USBSUSP (1u<<11) /* D */
#define OTG_GINT_ESUSP (1u<<10) /* D */
#define OTG_GINT_GONAKEFF (1u<< 7) /* D */
#define OTG_GINT_GINAKEFF (1u<< 6) /* D */
#define OTG_GINT_NPTXFE (1u<< 5) /* H */
#define OTG_GINT_RXFLVL (1u<< 4) /* H + D */
#define OTG_GINT_SOF (1u<< 3) /* H + D */
#define OTG_GINT_OTGINT (1u<< 2) /* H + D */
#define OTG_GINT_MMIS (1u<< 1) /* H + D */
#define OTG_GINT_CMOD (1u<< 0) /* H + D */
#define OTG_RXSTS_PKTSTS_IN (2u)
#define OTG_RXSTS_PKTSTS(r) (((r)>>17)&0xf)
#define OTG_RXSTS_BCNT(r) (((r)>>4)&0x7ff)
#define OTG_RXSTS_CHNUM(r) ((r)&0xf)
#define OTG_GCCFG_SOFOUTEN (1u<<20)
#define OTG_GCCFG_VBUSBSEN (1u<<19)
#define OTG_GCCFG_VBUSASEN (1u<<18)
#define OTG_GCCFG_PWRDWN (1u<<16)
#define OTG_HCFG_FSLSS (1u<<2)
#define OTG_HCFG_FSLSPCS (3u<<0)
#define OTG_HCFG_FSLSPCS_48 (1u<<0)
#define OTG_HCFG_FSLSPCS_6 (2u<<0)
#define OTG_HPRT_PSPD_FULL (1u<<17)
#define OTG_HPRT_PSPD_LOW (2u<<17)
#define OTG_HPRT_PSPD_MASK (1u<<17) /* read-only */
#define OTG_HPRT_PPWR (1u<<12)
#define OTG_HPRT_PRST (1u<< 8)
#define OTG_HPRT_PSUSP (1u<< 7)
#define OTG_HPRT_PRES (1u<< 6)
#define OTG_HPRT_POCCHNG (1u<< 5) /* raises HPRTINT */
#define OTG_HPRT_POCA (1u<< 4)
#define OTG_HPRT_PENCHNG (1u<< 3) /* raises HPRTINT */
#define OTG_HPRT_PENA (1u<< 2)
#define OTG_HPRT_PCDET (1u<< 1) /* raises HPRTINT */
#define OTG_HPRT_PCSTS (1u<< 0)
#define OTG_HPRT_INTS (OTG_HPRT_POCCHNG|OTG_HPRT_PENCHNG|OTG_HPRT_PCDET| \
OTG_HPRT_PENA) /* PENA is also set-to-clear */
/* HCINTSTS and HCINTMSK */
#define OTG_HCINT_DTERR (1u<<10)
#define OTG_HCINT_FRMOR (1u<< 9)
#define OTG_HCINT_BBERR (1u<< 8)
#define OTG_HCINT_TXERR (1u<< 7)
#define OTG_HCINT_NYET (1u<< 6) /* high-speed only; not STM32F10x */
#define OTG_HCINT_ACK (1u<< 5)
#define OTG_HCINT_NAK (1u<< 4)
#define OTG_HCINT_STALL (1u<< 3)
#define OTG_HCINT_CHH (1u<< 1)
#define OTG_HCINT_XFRC (1u<< 0)
#define OTG_HCCHAR_CHENA (1u<<31)
#define OTG_HCCHAR_CHDIS (1u<<30)
#define OTG_HCCHAR_ODDFRM (1u<<29)
#define OTG_HCCHAR_DAD(x) ((x)<<22)
#define OTG_HCCHAR_MCNT(x) ((x)<<20)
#define OTG_HCCHAR_ETYP_CTRL (0u<<18)
#define OTG_HCCHAR_ETYP_ISO (1u<<18)
#define OTG_HCCHAR_ETYP_BULK (2u<<18)
#define OTG_HCCHAR_ETYP_INT (3u<<18)
#define OTG_HCCHAR_LSDEV (1u<<17)
#define OTG_HCCHAR_EPDIR_OUT (0u<<15)
#define OTG_HCCHAR_EPDIR_IN (1u<<15)
#define OTG_HCCHAR_EPNUM(x) ((x)<<11)
#define OTG_HCCHAR_MPSIZ(x) ((x)<< 0)
#define OTG_HCTSIZ_DPID_DATA0 (0u<<29)
#define OTG_HCTSIZ_DPID_DATA2 (1u<<29)
#define OTG_HCTSIZ_DPID_DATA1 (2u<<29)
#define OTG_HCTSIZ_DPID_MDATA (3u<<29)
#define OTG_HCTSIZ_DPID_SETUP (3u<<29)
#define OTG_HCTSIZ_PKTCNT(x) ((x)<<19)
#define OTG_HCTSIZ_XFRSIZ(x) ((x)<< 0)
#define USB_OTG_BASE 0x50000000
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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/*
* stm32f105.h
*
* Core and peripheral registers.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
/* C pointer types */
#define AFIO volatile struct afio * const
/* C-accessible registers. */
static STK stk = (struct stk *)STK_BASE;
static SCB scb = (struct scb *)SCB_BASE;
static NVIC nvic = (struct nvic *)NVIC_BASE;
static DBG dbg = (struct dbg *)DBG_BASE;
static FLASH flash = (struct flash *)FLASH_BASE;
static PWR pwr = (struct pwr *)PWR_BASE;
static BKP bkp = (struct bkp *)BKP_BASE;
static RCC rcc = (struct rcc *)RCC_BASE;
static GPIO gpioa = (struct gpio *)GPIOA_BASE;
static GPIO gpiob = (struct gpio *)GPIOB_BASE;
static GPIO gpioc = (struct gpio *)GPIOC_BASE;
static GPIO gpiod = (struct gpio *)GPIOD_BASE;
static GPIO gpioe = (struct gpio *)GPIOE_BASE;
static GPIO gpiof = (struct gpio *)GPIOF_BASE;
static GPIO gpiog = (struct gpio *)GPIOG_BASE;
static AFIO afio = (struct afio *)AFIO_BASE;
static EXTI exti = (struct exti *)EXTI_BASE;
static DMA dma1 = (struct dma *)DMA1_BASE;
static DMA dma2 = (struct dma *)DMA2_BASE;
static TIM tim1 = (struct tim *)TIM1_BASE;
static TIM tim2 = (struct tim *)TIM2_BASE;
static TIM tim3 = (struct tim *)TIM3_BASE;
static TIM tim4 = (struct tim *)TIM4_BASE;
static TIM tim5 = (struct tim *)TIM5_BASE;
static TIM tim6 = (struct tim *)TIM6_BASE;
static TIM tim7 = (struct tim *)TIM7_BASE;
static SPI spi1 = (struct spi *)SPI1_BASE;
static SPI spi2 = (struct spi *)SPI2_BASE;
static SPI spi3 = (struct spi *)SPI3_BASE;
static I2C i2c1 = (struct i2c *)I2C1_BASE;
static I2C i2c2 = (struct i2c *)I2C2_BASE;
static USART usart1 = (struct usart *)USART1_BASE;
static USART usart2 = (struct usart *)USART2_BASE;
static USART usart3 = (struct usart *)USART3_BASE;
static USB_OTG usb_otg = (struct usb_otg *)USB_OTG_BASE;
/* Clocks */
extern unsigned int sysclk_mhz;
extern unsigned int apb1_mhz;
#define SYSCLK_MHZ sysclk_mhz
#define AHB_MHZ sysclk_mhz
#define APB1_MHZ apb1_mhz
#define APB2_MHZ 72
#define SOFTIRQ_0 43
#define SOFTIRQ_1 44
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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/*
* stm32f105_regs.h
*
* Core and peripheral register definitions.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
/* Power control */
struct pwr {
uint32_t cr; /* 00: Power control */
uint32_t csr; /* 04: Power control/status */
};
#define PWR_CR_DBP (1u<< 8)
#define PWR_BASE 0x40007000
/* Flash memory interface */
struct flash {
uint32_t acr; /* 00: Flash access control */
uint32_t keyr; /* 04: FPEC key */
uint32_t optkeyr; /* 08: Flash OPTKEY */
uint32_t sr; /* 0C: Flash status */
uint32_t cr; /* 10: Flash control */
uint32_t ar; /* 14: Flash address */
uint32_t rsvd; /* 18: - */
uint32_t obr; /* 1C: Option byte */
uint32_t wrpr; /* 20: Write protection */
};
#define FLASH_ACR_PRFTBS (1u<< 5)
#define FLASH_ACR_PRFTBE (1u<< 4)
#define FLASH_ACR_HLFCYA (1u<< 3)
#define FLASH_ACR_LATENCY(w) ((w)<<0) /* wait states */
#define FLASH_SR_EOP (1u<< 5)
#define FLASH_SR_WRPRTERR (1u<< 4)
#define FLASH_SR_PGERR (1u<< 2)
#define FLASH_SR_BSY (1u<< 0)
#define FLASH_CR_EOPIE (1u<<12)
#define FLASH_CR_ERRIE (1u<<10)
#define FLASH_CR_OPTWRE (1u<< 9)
#define FLASH_CR_LOCK (1u<< 7)
#define FLASH_CR_STRT (1u<< 6)
#define FLASH_CR_OPTER (1u<< 5)
#define FLASH_CR_OPTPG (1u<< 4)
#define FLASH_CR_MER (1u<< 2)
#define FLASH_CR_PER (1u<< 1)
#define FLASH_CR_PG (1u<< 0)
#define FLASH_BASE 0x40022000
/* Reset and clock control */
struct rcc {
uint32_t cr; /* 00: Clock control */
uint32_t cfgr; /* 04: Clock configuration */
uint32_t cir; /* 08: Clock interrupt */
uint32_t apb2rstr; /* 0C: APB2 peripheral reset */
uint32_t apb1rstr; /* 10: APB1 peripheral reset */
uint32_t ahbenr; /* 14: AHB periphernal clock enable */
uint32_t apb2enr; /* 18: APB2 peripheral clock enable */
uint32_t apb1enr; /* 1C: APB1 peripheral clock enable */
uint32_t bdcr; /* 20: Backup domain control */
uint32_t csr; /* 24: Control/status */
uint32_t ahbstr; /* 28: AHB peripheral clock reset */
uint32_t cfgr2; /* 2C: Clock configuration 2 */
};
#define RCC_CR_PLL3RDY (1u<<29)
#define RCC_CR_PLL3ON (1u<<28)
#define RCC_CR_PLL2RDY (1u<<27)
#define RCC_CR_PLL2ON (1u<<26)
#define RCC_CR_PLLRDY (1u<<25)
#define RCC_CR_PLLON (1u<<24)
#define RCC_CR_CSSON (1u<<19)
#define RCC_CR_HSEBYP (1u<<18)
#define RCC_CR_HSERDY (1u<<17)
#define RCC_CR_HSEON (1u<<16)
#define RCC_CR_HSIRDY (1u<<1)
#define RCC_CR_HSION (1u<<0)
#define RCC_CFGR_PLLMUL(x) (((x)-2)<<18)
#define RCC_CFGR_PLLXTPRE (1u<<17)
#define RCC_CFGR_PLLSRC_HSI (0u<<16)
#define RCC_CFGR_PLLSRC_PREDIV1 (1u<<16)
#define RCC_CFGR_ADCPRE_DIV8 (3u<<14)
#define RCC_CFGR_APB2PSC_2 (4u<<11)
#define RCC_CFGR_APB1PSC_2 (4u<< 8)
#define RCC_CFGR_SWS_HSI (0u<<2)
#define RCC_CFGR_SWS_HSE (1u<<2)
#define RCC_CFGR_SWS_PLL (2u<<2)
#define RCC_CFGR_SWS_MASK (3u<<2)
#define RCC_CFGR_SW_HSI (0u<<0)
#define RCC_CFGR_SW_HSE (1u<<0)
#define RCC_CFGR_SW_PLL (2u<<0)
#define RCC_CFGR_SW_MASK (3u<<0)
#define RCC_AHBENR_ETHMACRXEN (1u<<16)
#define RCC_AHBENR_ETHMACTXEN (1u<<15)
#define RCC_AHBENR_ETHMACEN (1u<<14)
#define RCC_AHBENR_OTGFSEN (1u<<12)
#define RCC_AHBENR_CRCEN (1u<< 6)
#define RCC_AHBENR_FLITFEN (1u<< 4)
#define RCC_AHBENR_SRAMEN (1u<< 2)
#define RCC_AHBENR_DMA2EN (1u<< 1)
#define RCC_AHBENR_DMA1EN (1u<< 0)
#define RCC_APB1ENR_DACEN (1u<<29)
#define RCC_APB1ENR_PWREN (1u<<28)
#define RCC_APB1ENR_BKPEN (1u<<27)
#define RCC_APB1ENR_CAN2EN (1u<<26)
#define RCC_APB1ENR_CAN1EN (1u<<25)
#define RCC_APB1ENR_I2C2EN (1u<<22)
#define RCC_APB1ENR_I2C1EN (1u<<21)
#define RCC_APB1ENR_USART5EN (1u<<20)
#define RCC_APB1ENR_USART4EN (1u<<19)
#define RCC_APB1ENR_USART3EN (1u<<18)
#define RCC_APB1ENR_USART2EN (1u<<17)
#define RCC_APB1ENR_SPI3EN (1u<<15)
#define RCC_APB1ENR_SPI2EN (1u<<14)
#define RCC_APB1ENR_WWDGEN (1u<<11)
#define RCC_APB1ENR_TIM7EN (1u<< 5)
#define RCC_APB1ENR_TIM6EN (1u<< 4)
#define RCC_APB1ENR_TIM5EN (1u<< 3)
#define RCC_APB1ENR_TIM4EN (1u<< 2)
#define RCC_APB1ENR_TIM3EN (1u<< 1)
#define RCC_APB1ENR_TIM2EN (1u<< 0)
#define RCC_APB2ENR_USART1EN (1u<<14)
#define RCC_APB2ENR_SPI1EN (1u<<12)
#define RCC_APB2ENR_TIM1EN (1u<<11)
#define RCC_APB2ENR_ADC2EN (1u<<10)
#define RCC_APB2ENR_ADC1EN (1u<< 9)
#define RCC_APB2ENR_IOPFEN (1u<< 7)
#define RCC_APB2ENR_IOPEEN (1u<< 6)
#define RCC_APB2ENR_IOPDEN (1u<< 5)
#define RCC_APB2ENR_IOPCEN (1u<< 4)
#define RCC_APB2ENR_IOPBEN (1u<< 3)
#define RCC_APB2ENR_IOPAEN (1u<< 2)
#define RCC_APB2ENR_AFIOEN (1u<< 0)
#define RCC_BASE 0x40021000
/* General-purpose I/O */
struct gpio {
uint32_t crl; /* 00: Port configuration low */
uint32_t crh; /* 04: Port configuration high */
uint32_t idr; /* 08: Port input data */
uint32_t odr; /* 0C: Port output data */
uint32_t bsrr; /* 10: Port bit set/reset */
uint32_t brr; /* 14: Port bit reset */
uint32_t lckr; /* 18: Port configuration lock */
};
#define _GPI_pulled(level) (0x8u|((level)<<4))
#define GPI_analog 0x0u
#define GPI_floating 0x4u
#define GPI_pull_down _GPI_pulled(LOW)
#define GPI_pull_up _GPI_pulled(HIGH)
#define GPO_pushpull(speed,level) (0x0u|(speed)|((level)<<4))
#define GPO_opendrain(speed,level) (0x4u|(speed)|((level)<<4))
#define AFO_pushpull(speed) (0x8u|(speed))
#define _AFO_pushpull(speed,level) (0x8u|(speed)|((level)<<4))
#define AFO_opendrain(speed) (0xcu|(speed))
#define _2MHz 2
#define _10MHz 1
#define _50MHz 3
#define LOW 0
#define HIGH 1
#define GPIOA_BASE 0x40010800
#define GPIOB_BASE 0x40010c00
#define GPIOC_BASE 0x40011000
#define GPIOD_BASE 0x40011400
#define GPIOE_BASE 0x40011800
#define GPIOF_BASE 0x40011c00
#define GPIOG_BASE 0x40012000
/* Alternative-function I/O */
struct afio {
uint32_t evcr; /* 00: Event control */
uint32_t mapr; /* 04: AF remap and debug I/O configuration */
uint32_t exticr[4]; /* 08-14: External interrupt configuration #1-4 */
uint32_t rsvd; /* 18: - */
uint32_t mapr2; /* 1C: AF remap and debug I/O configuration #2 */
};
#define AFIO_MAPR_SWJ_CFG_DISABLED (4u<<24)
#define AFIO_MAPR_TIM4_REMAP_FULL (1u<<12)
#define AFIO_MAPR_TIM3_REMAP_FULL (3u<<10)
#define AFIO_MAPR_TIM3_REMAP_PARTIAL (2u<<10)
#define AFIO_MAPR_TIM2_REMAP_FULL (3u<< 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_1 (1u<< 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_2 (2u<< 8)
#define AFIO_MAPR_TIM1_REMAP_FULL (3u<< 6)
#define AFIO_MAPR_TIM1_REMAP_PARTIAL (1u<< 6)
#define AFIO_MAPR_USART3_REMAP_FULL (3u<< 4)
#define AFIO_MAPR_USART3_REMAP_PARTIAL (1u<< 4)
#define AFIO_BASE 0x40010000
/* EXTI */
#define EXTI_BASE 0x40010400
/* DMA */
#define DMA1_CH1_IRQ 11
#define DMA1_CH2_IRQ 12
#define DMA1_CH3_IRQ 13
#define DMA1_CH4_IRQ 14
#define DMA1_CH5_IRQ 15
#define DMA1_CH6_IRQ 16
#define DMA1_CH7_IRQ 17
#define DMA1_BASE 0x40020000
#define DMA2_BASE 0x40020400
/* Timer */
#define TIM1_BASE 0x40012c00
#define TIM2_BASE 0x40000000
#define TIM3_BASE 0x40000400
#define TIM4_BASE 0x40000800
#define TIM5_BASE 0x40000c00
#define TIM6_BASE 0x40001000
#define TIM7_BASE 0x40001400
/* I2C */
struct i2c {
uint32_t cr1; /* 00: Control 1 */
uint32_t cr2; /* 04: Control 2 */
uint32_t oar1; /* 08: Own address 1 */
uint32_t oar2; /* 0C: Own address 2 */
uint32_t dr; /* 10: Data */
uint32_t sr1; /* 14: Status 1 */
uint32_t sr2; /* 18: Status 2 */
uint32_t ccr; /* 1C: Clock control */
uint32_t trise; /* 20: Rise time */
};
#define I2C_CR1_SWRST (1u<<15)
#define I2C_CR1_ALERT (1u<<13)
#define I2C_CR1_PEC (1u<<12)
#define I2C_CR1_POS (1u<<11)
#define I2C_CR1_ACK (1u<<10)
#define I2C_CR1_STOP (1u<< 9)
#define I2C_CR1_START (1u<< 8)
#define I2C_CR1_NOSTRETCH (1u<< 7)
#define I2C_CR1_ENGC (1u<< 6)
#define I2C_CR1_ENPEC (1u<< 5)
#define I2C_CR1_ENARP (1u<< 4)
#define I2C_CR1_SMBTYPE (1u<< 3)
#define I2C_CR1_SMBUS (1u<< 1)
#define I2C_CR1_PE (1u<< 0)
#define I2C_CR2_LAST (1u<<12)
#define I2C_CR2_DMAEN (1u<<11)
#define I2C_CR2_ITBUFEN (1u<<10)
#define I2C_CR2_ITEVTEN (1u<< 9)
#define I2C_CR2_ITERREN (1u<< 8)
#define I2C_CR2_FREQ(x) (x)
#define I2C_SR1_SMBALERT (1u<<15)
#define I2C_SR1_TIMEOUT (1u<<14)
#define I2C_SR1_PECERR (1u<<12)
#define I2C_SR1_OVR (1u<<11)
#define I2C_SR1_AF (1u<<10)
#define I2C_SR1_ARLO (1u<< 9)
#define I2C_SR1_BERR (1u<< 8)
#define I2C_SR1_ERRORS 0xdf00
#define I2C_SR1_TXE (1u<< 7)
#define I2C_SR1_RXNE (1u<< 6)
#define I2C_SR1_STOPF (1u<< 4)
#define I2C_SR1_ADD10 (1u<< 3)
#define I2C_SR1_BTF (1u<< 2)
#define I2C_SR1_ADDR (1u<< 1)
#define I2C_SR1_SB (1u<< 0)
#define I2C_SR1_EVENTS 0x001f
#define I2C_SR2_PEC(x) ((x)<<15)
#define I2C_SR2_DUALF (1u<< 7)
#define I2C_SR2_SMBHOST (1u<< 6)
#define I2C_SR2_SMBDEFAULT (1u<< 5)
#define I2C_SR2_GENCALL (1u<< 4)
#define I2C_SR2_TRA (1u<< 2)
#define I2C_SR2_BUSY (1u<< 1)
#define I2C_SR2_MSL (1u<< 0)
#define I2C_CCR_FS (1u<<15)
#define I2C_CCR_DUTY (1u<<14)
#define I2C_CCR_CCR(x) (x)
#define I2C1_BASE 0x40005400
#define I2C2_BASE 0x40005800
/* USART */
#define USART1_BASE 0x40013800
#define USART2_BASE 0x40004400
#define USART3_BASE 0x40004800
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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/*
* spi.h
*
* Helper functions for STM32F10x SPI interfaces.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
void spi_quiesce(SPI spi);
void spi_16bit_frame(SPI spi);
void spi_8bit_frame(SPI spi);
void spi_xmit16(SPI spi, uint16_t out);
uint16_t spi_xchg16(SPI spi, uint16_t out);
#define spi_recv16(spi) spi_xchg16(spi, 0xffffu)
#define spi_xmit8(spi, x) spi_xmit16(spi, (uint8_t)(x))
#define spi_xchg8(spi, x) (uint8_t)spi_xchg16(spi, (uint8_t)(x))
#define spi_recv8(spi) spi_xchg8(spi, 0xffu)
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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/*
* time.h
*
* System-time abstraction over STM32 STK timer.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
typedef uint32_t time_t;
#define TIME_MHZ STK_MHZ
#define time_us(x) stk_us(x)
#define time_ms(x) stk_ms(x)
#define time_stk(x) (x)
#define time_sysclk(x) stk_sysclk(x)
#define sysclk_time(x) sysclk_stk(x)
void delay_from(time_t t, unsigned int ticks);
time_t time_now(void);
#define time_diff(x,y) ((int32_t)((y)-(x))) /* d = y - x */
#define time_add(x,d) ((time_t)((x)+(d))) /* y = x + d */
#define time_sub(x,d) ((time_t)((x)-(d))) /* y = x - d */
#define time_since(x) time_diff(x, time_now())
void time_init(void);
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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/*
* timer.h
*
* Deadline-based timer callbacks.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
struct timer {
time_t deadline;
void (*cb_fn)(void *);
void *cb_dat;
struct timer *next;
};
/* Safe to call from any priority level same or lower than TIMER_IRQ_PRI. */
void timer_init(struct timer *timer, void (*cb_fn)(void *), void *cb_dat);
void timer_set(struct timer *timer, time_t deadline);
void timer_cancel(struct timer *timer);
void timers_init(void);
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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/*
* types.h
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
#ifndef NDEBUG
#define ASSERT(p) do { if (!(p)) illegal(); } while (0)
#else
#define ASSERT(p) do { if (0 && (p)) {} } while (0)
#endif
typedef char bool_t;
#define TRUE 1
#define FALSE 0
#ifndef offsetof
#define offsetof(a,b) __builtin_offsetof(a,b)
#endif
#define container_of(ptr, type, member) ({ \
typeof( ((type *)0)->member ) *__mptr = (ptr); \
(type *)( (char *)__mptr - offsetof(type,member) );})
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#define min(x,y) ({ \
const typeof(x) _x = (x); \
const typeof(y) _y = (y); \
(void) (&_x == &_y); \
_x < _y ? _x : _y; })
#define max(x,y) ({ \
const typeof(x) _x = (x); \
const typeof(y) _y = (y); \
(void) (&_x == &_y); \
_x > _y ? _x : _y; })
#define min_t(type,x,y) \
({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
#define max_t(type,x,y) \
({ type __x = (x); type __y = (y); __x > __y ? __x: __y; })
#define range_t(type,x,a,b) min_t(type, max_t(type, x, a), b)
#define m(bitnr) (1u<<(bitnr))
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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/*
* util.h
*
* Utility definitions.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
struct slot {
char name[FF_MAX_LFN+1];
char type[7];
uint8_t attributes;
uint32_t firstCluster;
uint32_t size;
uint32_t dir_sect, dir_ptr;
};
void fatfs_from_slot(FIL *file, const struct slot *slot, BYTE mode);
bool_t lba_within_fat_volume(uint32_t lba);
void filename_extension(const char *filename, char *extension, size_t size);
/* Fast memset/memcpy: Pointers must be word-aligned, count must be a non-zero
* multiple of 32 bytes. */
void memset_fast(void *s, int c, size_t n);
void memcpy_fast(void *dest, const void *src, size_t n);
void *memset(void *s, int c, size_t n);
void *memcpy(void *dest, const void *src, size_t n);
void *memmove(void *dest, const void *src, size_t n);
int memcmp(const void *s1, const void *s2, size_t n);
size_t strlen(const char *s);
size_t strnlen(const char *s, size_t maxlen);
int strcmp_ci(const char *s1, const char *s2); /* case insensitive */
int strcmp(const char *s1, const char *s2);
int strncmp(const char *s1, const char *s2, size_t n);
char *strcpy(char *dest, const char *src);
char *strchr(const char *s, int c);
char *strrchr(const char *s, int c);
int tolower(int c);
int toupper(int c);
int isspace(int c);
long int strtol(const char *nptr, char **endptr, int base);
void qsort_p(void *base, unsigned int nr,
int (*compar)(const void *, const void *));
uint32_t rand(void);
unsigned int popcount(uint32_t x);
int vsnprintf(char *str, size_t size, const char *format, va_list ap)
__attribute__ ((format (printf, 3, 0)));
int snprintf(char *str, size_t size, const char *format, ...)
__attribute__ ((format (printf, 3, 4)));
#define le16toh(x) (x)
#define le32toh(x) (x)
#define htole16(x) (x)
#define htole32(x) (x)
#define be16toh(x) _rev16(x)
#define be32toh(x) _rev32(x)
#define htobe16(x) _rev16(x)
#define htobe32(x) _rev32(x)
uint32_t udiv64(uint64_t dividend, uint32_t divisor);
/* Arena-based memory allocation */
void *arena_alloc(uint32_t sz);
uint32_t arena_total(void);
uint32_t arena_avail(void);
void arena_init(void);
/* Board-specific callouts */
void board_init(void);
#if !defined(NDEBUG) || defined(LOGFILE)
/* Log output, to serial console or logfile. */
int vprintk(const char *format, va_list ap)
__attribute__ ((format (printf, 1, 0)));
int printk(const char *format, ...)
__attribute__ ((format (printf, 1, 2)));
#else /* NDEBUG && !LOGFILE */
static inline int vprintk(const char *format, va_list ap) { return 0; }
static inline int printk(const char *format, ...) { return 0; }
#endif
#define log(f, a...) printk("%s: " f, LOG_PREFIX, ## a)
#if defined(LOGFILE)
/* Logfile management */
void logfile_flush(FIL *file);
#else /* !LOGFILE */
#define logfile_flush(f) ((void)0)
#endif
#if !defined(NDEBUG)
/* Serial console control */
void console_init(void);
void console_sync(void);
void console_crash_on_input(void);
#else /* NDEBUG */
#define console_init() ((void)0)
#define console_sync() IRQ_global_disable()
#define console_crash_on_input() ((void)0)
#endif
/* CRC-CCITT */
uint16_t crc16_ccitt(const void *buf, size_t len, uint16_t crc);
/* Display setup and identification. */
void display_init(void);
extern uint8_t display_type;
#define DT_NONE 0
#define DT_LCD_OLED 1
#define DT_LED_7SEG 2
/* Speaker. */
void speaker_init(void);
void speaker_pulse(void);
void speaker_notify_insert(unsigned int slotnr);
void speaker_notify_eject(void);
/* Display: 3-digit 7-segment display */
void led_7seg_init(void);
void led_7seg_write_raw(const uint8_t *d);
void led_7seg_write_string(const char *p);
void led_7seg_write_decimal(unsigned int val);
void led_7seg_display_setting(bool_t enable);
int led_7seg_nr_digits(void);
/* Display: I2C 16x2 LCD */
bool_t lcd_init(void);
void lcd_clear(void);
void lcd_write(int col, int row, int min, const char *str);
void lcd_backlight(bool_t on);
void lcd_sync(void);
extern uint8_t lcd_columns, lcd_rows;
/* FF OSD (On Screen Display) */
extern bool_t has_osd;
extern uint8_t osd_buttons_tx; /* Gotek -> FF_OSD */
extern uint8_t osd_buttons_rx; /* FF_OSD -> Gotek */
/* USB stack processing */
void usbh_msc_init(void);
void usbh_msc_buffer_set(uint8_t *buf);
void usbh_msc_process(void);
bool_t usbh_msc_inserted(void);
/* Navigation/UI frontend */
uint16_t get_slot_nr(void);
bool_t set_slot_nr(uint16_t slot_nr);
void set_slot_name(const char *name);
bool_t get_img_cfg(struct slot *slot);
void IRQ_rotary(void);
enum { DM_normal=0, DM_banner, DM_menu };
extern uint8_t display_mode;
extern uint8_t board_id;
extern uint8_t has_kc30_header;
/* Gotek board revisions */
#define BRDREV_Gotek_standard 0xf
#define BRDREV_Gotek_enhanced 0x0
#define BRDREV_Gotek_sd_card 0x1
#define gotek_enhanced() (board_id != BRDREV_Gotek_standard)
extern uint32_t board_rotary_exti_mask;
void board_setup_rotary_exti(void);
unsigned int board_get_rotary(void);
unsigned int board_get_buttons(void);
#define B_LEFT 1
#define B_RIGHT 2
#define B_SELECT 4
void board_jc_set_mode(unsigned int mode);
bool_t board_jc_strapped(void);
/* Build info. */
extern const char fw_ver[];
extern const char build_date[];
extern const char build_time[];
/* Text/data/BSS address ranges. */
extern char _stext[], _etext[];
extern char _smaintext[], _emaintext[];
extern char _sdat[], _edat[], _ldat[];
extern char _sbss[], _ebss[];
/* Stacks. */
extern uint32_t _thread_stacktop[], _thread_stackbottom[];
extern uint32_t _irq_stacktop[], _irq_stackbottom[];
/* Default exception handler. */
void EXC_unused(void);
/* IRQ priorities, 0 (highest) to 15 (lowest). */
#define RESET_IRQ_PRI 0
#define FLOPPY_IRQ_SEL_PRI 1
#define FLOPPY_IRQ_WGATE_PRI 2
#define FLOPPY_IRQ_STEP_PRI 3
#define TIMER_IRQ_PRI 4
#define WDATA_IRQ_PRI 7
#define RDATA_IRQ_PRI 8
#define FLOPPY_SOFTIRQ_PRI 9
#define I2C_IRQ_PRI 13
#define USB_IRQ_PRI 14
#define CONSOLE_IRQ_PRI 15
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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/*
* volume.h
*
* Volume abstraction for low-level storage drivers.
*
* Written & released by Keir Fraser <keir.xen@gmail.com>
*
* This is free and unencumbered software released into the public domain.
* See the file COPYING for more details, or visit <http://unlicense.org>.
*/
#include "../src/fatfs/diskio.h"
struct volume_ops {
DSTATUS (*initialize)(BYTE);
DSTATUS (*status)(BYTE);
DRESULT (*read)(BYTE, BYTE *, LBA_t, UINT);
DRESULT (*write)(BYTE, const BYTE *, LBA_t, UINT);
DRESULT (*ioctl)(BYTE, BYTE, void *);
bool_t (*connected)(void);
bool_t (*readonly)(void);
};
bool_t volume_connected(void);
bool_t volume_readonly(void);
void volume_cache_init(void *start, void *end);
void volume_cache_destroy(void);
void volume_cache_metadata_only(FIL *fp);
/*
* Local variables:
* mode: C
* c-file-style: "Linux"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/

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*bak
*.bck

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EESchema-DOCLIB Version 2.0
#
#End Doc Library

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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# HDR_3X5
#
DEF HDR_3X5 P 0 40 Y Y 1 F N
F0 "P" 0 0 60 H V C CNN
F1 "HDR_3X5" 0 -400 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 -100 300 -700 0 1 0 N
X ~ 1 -500 -200 200 R 50 50 1 1 I
X ~ 2 -500 -300 200 R 50 50 1 1 I
X ~ 3 -500 -400 200 R 50 50 1 1 I
X ~ 4 -500 -500 200 R 50 50 1 1 I
X ~ 5 -500 -600 200 R 50 50 1 1 I
X ~ 6 500 -600 200 L 50 50 1 1 I
X ~ 7 500 -500 200 L 50 50 1 1 I
X ~ 8 500 -400 200 L 50 50 1 1 I
X ~ 9 500 -300 200 L 50 50 1 1 I
X ~ 10 500 -200 200 L 50 50 1 1 I
X ~ 11 -200 -900 200 U 50 50 1 1 I
X ~ 12 -100 -900 200 U 50 50 1 1 I
X ~ 13 0 -900 200 U 50 50 1 1 I
X ~ 14 100 -900 200 U 50 50 1 1 I
X ~ 15 200 -900 200 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# MAPLE_MINI
#
DEF MAPLE_MINI U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "MAPLE_MINI" 0 -2250 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -550 -50 550 -2150 0 1 0 N
X VIn 1 -750 -150 200 R 50 50 1 1 P
X D0/PB11 2 -750 -250 200 R 50 50 1 1 P
X D1/PB10 3 -750 -350 200 R 50 50 1 1 P
X D2/PB2/BT1 4 -750 -450 200 R 50 50 1 1 P
X D3/PB0 5 -750 -550 200 R 50 50 1 1 P
X D4/PA7 6 -750 -650 200 R 50 50 1 1 P
X D5/PA6 7 -750 -750 200 R 50 50 1 1 P
X D6/PA5 8 -750 -850 200 R 50 50 1 1 P
X D7/PA4 9 -750 -950 200 R 50 50 1 1 P
X D8/PA3 10 -750 -1050 200 R 50 50 1 1 P
X 3V3 20 -750 -2050 200 R 50 50 1 1 P
X D21/PA14 30 750 -1150 200 L 50 50 1 1 P
X D31/PB12 40 750 -150 200 L 50 50 1 1 P
X D9/PA2 11 -750 -1150 200 R 50 50 1 1 P
X 3V3 21 750 -2050 200 L 50 50 1 1 P
X D22/PA13 31 750 -1050 200 L 50 50 1 1 P
X D10/PA1 12 -750 -1250 200 R 50 50 1 1 P
X GND 22 750 -1950 200 L 50 50 1 1 P
X D23/PA12 32 750 -950 200 L 50 50 1 1 P
X D11/PA0 13 -750 -1350 200 R 50 50 1 1 P
X D32/PB8/Btn 23 750 -1850 200 L 50 50 1 1 P
X D24/PA11 33 750 -850 200 L 50 50 1 1 P
X RESET 14 -750 -1450 200 R 50 50 1 1 P
X D15/PB7 24 750 -1750 200 L 50 50 1 1 P
X D25/PA10 34 750 -750 200 L 50 50 1 1 P
X D12/PC15 15 -750 -1550 200 R 50 50 1 1 P
X D16/PB6 25 750 -1650 200 L 50 50 1 1 P
X D26/PA9 35 750 -650 200 L 50 50 1 1 P
X D13/PC14 16 -750 -1650 200 R 50 50 1 1 P
X D17/PB5 26 750 -1550 200 L 50 50 1 1 P
X D27/PA8 36 750 -550 200 L 50 50 1 1 P
X D14/PC13 17 -750 -1750 200 R 50 50 1 1 P
X D18/PB4 27 750 -1450 200 L 50 50 1 1 P
X D28/PB15 37 750 -450 200 L 50 50 1 1 P
X VBat 18 -750 -1850 200 R 50 50 1 1 P
X D19/PB3 28 750 -1350 200 L 50 50 1 1 P
X D29/PB14 38 750 -350 200 L 50 50 1 1 P
X GND 19 -750 -1950 200 R 50 50 1 1 P
X D20/PA15 29 750 -1250 200 L 50 50 1 1 P
X D30/PB13 39 750 -250 200 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# STM32_A
#
DEF STM32_A P 0 40 Y Y 1 F N
F0 "P" 0 0 60 H V C CNN
F1 "STM32_A" 0 -1500 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 -100 300 -1400 0 1 0 N
X GND 1 -500 -200 200 R 50 50 1 1 P
X GND 2 500 -200 200 L 50 50 1 1 P
X RX 3 -500 -300 200 R 50 50 1 1 P
X TX 4 500 -300 200 L 50 50 1 1 P
X PA8 5 -500 -400 200 R 50 50 1 1 P
X PB15 6 500 -400 200 L 50 50 1 1 P
X PB14 7 -500 -500 200 R 50 50 1 1 P
X PB13 8 500 -500 200 L 50 50 1 1 P
X PB12 9 -500 -600 200 R 50 50 1 1 P
X PB11 10 500 -600 200 L 50 50 1 1 P
X PA3 20 500 -1100 200 L 50 50 1 1 P
X PB2 11 -500 -700 200 R 50 50 1 1 P
X PA0 21 -500 -1200 200 R 50 50 1 1 P
X PB10 12 500 -700 200 L 50 50 1 1 P
X PA1 22 500 -1200 200 L 50 50 1 1 P
X PB0 13 -500 -800 200 R 50 50 1 1 P
X 3V3 23 -500 -1300 200 R 50 50 1 1 P
X PB1 14 500 -800 200 L 50 50 1 1 P
X 3V3 24 500 -1300 200 L 50 50 1 1 P
X PA6 15 -500 -900 200 R 50 50 1 1 P
X PA7 16 500 -900 200 L 50 50 1 1 P
X PA4 17 -500 -1000 200 R 50 50 1 1 P
X PA5 18 500 -1000 200 L 50 50 1 1 P
X PA2 19 -500 -1100 200 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# STM32_B
#
DEF STM32_B P 0 40 Y Y 1 F N
F0 "P" 0 0 60 H V C CNN
F1 "STM32_B" 0 -1500 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 -100 300 -1400 0 1 0 N
X GND 1 -500 -200 200 R 50 50 1 1 P
X GND 2 500 -200 200 L 50 50 1 1 P
X PA12 3 -500 -300 200 R 50 50 1 1 P
X PA11 4 500 -300 200 L 50 50 1 1 P
X PA14 5 -500 -400 200 R 50 50 1 1 P
X PA13 6 500 -400 200 L 50 50 1 1 P
X PB3 7 -500 -500 200 R 50 50 1 1 P
X PA15 8 500 -500 200 L 50 50 1 1 P
X PB5 9 -500 -600 200 R 50 50 1 1 P
X PB4 10 500 -600 200 L 50 50 1 1 P
X PC15 20 500 -1100 200 L 50 50 1 1 P
X PB7 11 -500 -700 200 R 50 50 1 1 P
X NST 21 -500 -1200 200 R 50 50 1 1 P
X PB6 12 500 -700 200 L 50 50 1 1 P
X PD1 22 500 -1200 200 L 50 50 1 1 P
X PB8 13 -500 -800 200 R 50 50 1 1 P
X 3V3 23 -500 -1300 200 R 50 50 1 1 P
X BT0 14 500 -800 200 L 50 50 1 1 P
X 3V3 24 500 -1300 200 L 50 50 1 1 P
X VBAT 15 -500 -900 200 R 50 50 1 1 P
X PB9 16 500 -900 200 L 50 50 1 1 P
X PC14 17 -500 -1000 200 R 50 50 1 1 P
X PC13 18 500 -1000 200 L 50 50 1 1 P
X PD0 19 -500 -1100 200 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# TAOBAO
#
DEF TAOBAO U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "TAOBAO" 0 -2250 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -550 -50 550 -2150 0 1 0 N
X PB12 1 -750 -150 200 R 50 50 1 1 P
X PB13 2 -750 -250 200 R 50 50 1 1 P
X PB14 3 -750 -350 200 R 50 50 1 1 P
X PB15 4 -750 -450 200 R 50 50 1 1 P
X PA8 5 -750 -550 200 R 50 50 1 1 P
X PA9 6 -750 -650 200 R 50 50 1 1 P
X PA10 7 -750 -750 200 R 50 50 1 1 P
X PA11 8 -750 -850 200 R 50 50 1 1 P
X PA12 9 -750 -950 200 R 50 50 1 1 P
X PA15 10 -750 -1050 200 R 50 50 1 1 P
X 3V3 20 -750 -2050 200 R 50 50 1 1 P
X PA5 30 750 -1150 200 L 50 50 1 1 P
X GND 40 750 -150 200 L 50 50 1 1 P
X PB3 11 -750 -1150 200 R 50 50 1 1 P
X VBat 21 750 -2050 200 L 50 50 1 1 P
X PA6 31 750 -1050 200 L 50 50 1 1 P
X PB4 12 -750 -1250 200 R 50 50 1 1 P
X PC13 22 750 -1950 200 L 50 50 1 1 P
X PA7 32 750 -950 200 L 50 50 1 1 P
X PB5 13 -750 -1350 200 R 50 50 1 1 P
X PC14 23 750 -1850 200 L 50 50 1 1 P
X PB0 33 750 -850 200 L 50 50 1 1 P
X PB6 14 -750 -1450 200 R 50 50 1 1 P
X PC15 24 750 -1750 200 L 50 50 1 1 P
X PB1 34 750 -750 200 L 50 50 1 1 P
X PB7 15 -750 -1550 200 R 50 50 1 1 P
X PA0 25 750 -1650 200 L 50 50 1 1 P
X PB10 35 750 -650 200 L 50 50 1 1 P
X PB8 16 -750 -1650 200 R 50 50 1 1 P
X PA1 26 750 -1550 200 L 50 50 1 1 P
X PB11 36 750 -550 200 L 50 50 1 1 P
X PB9 17 -750 -1750 200 R 50 50 1 1 P
X PA2 27 750 -1450 200 L 50 50 1 1 P
X RST 37 750 -450 200 L 50 50 1 1 P
X VIn 18 -750 -1850 200 R 50 50 1 1 P
X PA3 28 750 -1350 200 L 50 50 1 1 P
X 3V3 38 750 -350 200 L 50 50 1 1 P
X GND 19 -750 -1950 200 R 50 50 1 1 P
X PA4 29 750 -1250 200 L 50 50 1 1 P
X GND 39 750 -250 200 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

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@ -0,0 +1,24 @@
(module C_3528 (layer F.Cu) (tedit 55A1FF89)
(descr "Capacitor SMD 3528, hand soldering")
(tags "capacitor 3528")
(attr smd)
(fp_text reference C3 (at 0 2.54) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10u (at 0 -2.54) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.556 -1.778) (end 3.556 -1.778) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.556 -1.778) (end 3.556 1.905) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.556 1.905) (end -3.556 1.905) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.556 1.905) (end -3.556 -1.778) (layer F.CrtYd) (width 0.05))
(fp_line (start 1 -1.729) (end -1 -1.729) (layer F.SilkS) (width 0.15))
(fp_line (start -1 1.729) (end 1 1.729) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -2.135 0) (size 2.6 2.6) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at 2.065 0) (size 2.6 2.6) (layers F.Cu F.Paste F.Mask))
(model Capacitors_SMD.3dshapes/C_1210_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

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(module C_Disc_P4mm (layer F.Cu) (tedit 5595554D)
(descr "Capacitor 6mm Disc, Pitch 5mm")
(tags Capacitor)
(fp_text reference REF** (at 2 -1.27) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value C_4mm (at 2.54 1.905) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.95 -2.5) (end 5.95 -2.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.95 -2.5) (end 5.95 2.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.95 2.5) (end -0.95 2.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.95 2.5) (end -0.95 -2.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.5 -2.25) (end 4.5 -2.25) (layer F.SilkS) (width 0.15))
(fp_line (start 4.5 2.25) (end -0.5 2.25) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at 0 0) (size 1.4 1.4) (drill 0.9) (layers *.Cu *.Mask F.SilkS))
(pad 2 thru_hole circle (at 4 0) (size 1.4 1.4) (drill 0.9) (layers *.Cu *.Mask F.SilkS))
(model Capacitors_ThroughHole.3dshapes/C_Disc_D6_P5.wrl
(at (xyz 0.0984252 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

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@ -0,0 +1,28 @@
(module D_SOD128 (layer F.Cu) (tedit 55A201DC)
(descr "Diode SOD-128, hand soldering")
(tags "diode 128")
(attr smd)
(fp_text reference D2 (at 0 -2.54) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TVS_5V (at 0 2.54) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.381 0) (end 0.254 -0.508) (layer F.SilkS) (width 0.15))
(fp_line (start 0.254 -0.508) (end 0.254 0.508) (layer F.SilkS) (width 0.15))
(fp_line (start -0.889 0) (end -0.381 0) (layer F.SilkS) (width 0.15))
(fp_line (start 0.254 0) (end 0.762 0) (layer F.SilkS) (width 0.15))
(fp_line (start -0.381 -0.381) (end -0.381 0.381) (layer F.SilkS) (width 0.15))
(fp_line (start 0.254 0.508) (end -0.381 0) (layer F.SilkS) (width 0.15))
(fp_line (start -4.3 -1.85) (end 4.3 -1.85) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.3 1.85) (end 4.3 1.85) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.3 -1.85) (end -4.3 1.85) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.3 -1.85) (end 4.3 1.85) (layer F.CrtYd) (width 0.05))
(pad 1 smd rect (at -2.45 0) (size 2.5 2.2) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at 2.45 0) (size 2.5 2.2) (layers F.Cu F.Paste F.Mask))
(model Capacitors_SMD.3dshapes/C_1812_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

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@ -0,0 +1,66 @@
(module MMini-DIP-40 (layer F.Cu) (tedit 54130A77)
(descr "40-lead dip package, row spacing 15.24 mm (600 mils)")
(tags "dil dip 2.54 600")
(fp_text reference U1 (at 0 -5.22) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value MAPLE_MINI (at 0 -3.72) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.05 -2.45) (end -1.05 50.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.3 -2.45) (end 16.3 50.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -2.45) (end 16.3 -2.45) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 50.75) (end 16.3 50.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.135 -2.295) (end 0.135 -1.025) (layer F.SilkS) (width 0.15))
(fp_line (start 15.105 -2.295) (end 15.105 -1.025) (layer F.SilkS) (width 0.15))
(fp_line (start 15.105 50.555) (end 15.105 49.285) (layer F.SilkS) (width 0.15))
(fp_line (start 0.135 50.555) (end 0.135 49.285) (layer F.SilkS) (width 0.15))
(fp_line (start 0.135 -2.295) (end 15.105 -2.295) (layer F.SilkS) (width 0.15))
(fp_line (start 0.135 50.555) (end 15.105 50.555) (layer F.SilkS) (width 0.15))
(fp_line (start 0.135 -1.025) (end -0.8 -1.025) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole oval (at 0 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 2 thru_hole oval (at 0 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 3 thru_hole oval (at 0 5.08) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 4 thru_hole oval (at 0 7.62) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 5 thru_hole oval (at 0 10.16) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 6 thru_hole oval (at 0 12.7) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 7 thru_hole oval (at 0 15.24) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 8 thru_hole oval (at 0 17.78) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 9 thru_hole oval (at 0 20.32) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 10 thru_hole oval (at 0 22.86) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 11 thru_hole oval (at 0 25.4) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 12 thru_hole oval (at 0 27.94) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 13 thru_hole oval (at 0 30.48) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 14 thru_hole oval (at 0 33.02) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 15 thru_hole oval (at 0 35.56) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 16 thru_hole oval (at 0 38.1) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 17 thru_hole oval (at 0 40.64) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 18 thru_hole oval (at 0 43.18) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 19 thru_hole oval (at 0 45.72) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 20 thru_hole oval (at 0 48.26) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole oval (at 15.24 48.26) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 22 thru_hole oval (at 15.24 45.72) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 23 thru_hole oval (at 15.24 43.18) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 24 thru_hole oval (at 15.24 40.64) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 25 thru_hole oval (at 15.24 38.1) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 26 thru_hole oval (at 15.24 35.56) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 27 thru_hole oval (at 15.24 33.02) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 28 thru_hole oval (at 15.24 30.48) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 29 thru_hole oval (at 15.24 27.94) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 30 thru_hole oval (at 15.24 25.4) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 31 thru_hole oval (at 15.24 22.86) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 32 thru_hole oval (at 15.24 20.32) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 33 thru_hole oval (at 15.24 17.78) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 34 thru_hole oval (at 15.24 15.24) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 35 thru_hole oval (at 15.24 12.7) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 36 thru_hole oval (at 15.24 10.16) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 37 thru_hole oval (at 15.24 7.62) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 38 thru_hole oval (at 15.24 5.08) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 39 thru_hole oval (at 15.24 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 40 thru_hole oval (at 15.24 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(model Housings_DIP.3dshapes/DIP-40_W15.24mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

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@ -0,0 +1,30 @@
(module MiniMELF_Handsoldering (layer F.Cu) (tedit 581C4CD0)
(descr "Diode Mini-MELF Handsoldering")
(tags "Diode Mini-MELF Handsoldering")
(attr smd)
(fp_text reference REF** (at 0 -2.54) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value MiniMELF_Handsoldering (at 0 2.3) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.4 -1.1) (end 3.3 -1.1) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.3 -1.1) (end 3.4 -1.1) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.4 -1.1) (end 3.4 1.1) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.4 1.1) (end -3.4 1.1) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.4 1.1) (end -3.4 -1.1) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.49958 0) (end -0.64944 0) (layer F.SilkS) (width 0.15))
(fp_line (start 0.34878 0) (end 0.54944 0) (layer F.SilkS) (width 0.15))
(fp_line (start -0.49958 0) (end -0.49958 0.7493) (layer F.SilkS) (width 0.15))
(fp_line (start -0.49958 0) (end -0.49958 -0.70104) (layer F.SilkS) (width 0.15))
(fp_line (start -0.49958 0) (end 0.34878 -0.70104) (layer F.SilkS) (width 0.15))
(fp_line (start 0.34878 -0.70104) (end 0.34878 0.70104) (layer F.SilkS) (width 0.15))
(fp_line (start 0.34878 0.70104) (end -0.49958 0) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -2.25 0) (size 2 2) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at 2.25 0) (size 2 2) (layers F.Cu F.Paste F.Mask))
(model Diodes_SMD.3dshapes/MiniMELF_Handsoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 0.3937 0.3937 0.3937))
(rotate (xyz 0 0 180))
)
)

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@ -0,0 +1,42 @@
(module Pin_Header_Straight_3x05 (layer F.Cu) (tedit 5590350D)
(descr "Through hole pin header")
(tags "pin header")
(fp_text reference REF** (at 0 -5.1) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Pin_Header_Straight_3x05 (at 0 -3.1) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.75 -1.75) (end -1.75 11.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.84 -1.75) (end 6.84 11.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.75 -1.75) (end 6.84 -1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.75 11.95) (end 6.84 11.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.35 -1.27) (end 6.35 11.43) (layer F.SilkS) (width 0.15))
(fp_line (start 6.35 11.43) (end -1.27 11.43) (layer F.SilkS) (width 0.15))
(fp_line (start -1.27 11.43) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 6.35 -1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -1.55 -1.55) (end -1.55 0) (layer F.SilkS) (width 0.15))
(pad 15 thru_hole oval (at 5.08 10.16) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 14 thru_hole oval (at 5.08 7.62) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 13 thru_hole oval (at 5.08 5.08) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 12 thru_hole oval (at 5.08 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 11 thru_hole oval (at 5.08 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 1 thru_hole rect (at 0 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 6 thru_hole oval (at 2.54 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 2 thru_hole oval (at 0 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 7 thru_hole oval (at 2.54 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 3 thru_hole oval (at 0 5.08) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 8 thru_hole oval (at 2.54 5.08) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 4 thru_hole oval (at 0 7.62) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 9 thru_hole oval (at 2.54 7.62) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 5 thru_hole oval (at 0 10.16) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(pad 10 thru_hole oval (at 2.54 10.16) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS))
(model Pin_Headers.3dshapes/Pin_Header_Straight_3x05.wrl
(at (xyz 0.05 -0.2 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)

View file

@ -0,0 +1,12 @@
(module mousebite (layer F.Cu) (tedit 551DB929)
(pad "" np_thru_hole circle (at -2 -1.2) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -2 1.2) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -1 -1.2) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -1 1.2) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 0 -1.2) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 0 1.2) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 1 -1.2) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 1 1.2) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 2 -1.2) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 2 1.2) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
)

View file

@ -0,0 +1,14 @@
REF PART DESCRIPTION RS ORDER
=== ================ ========
F1 Bourns MF-NSMF075-2 (1206) 647-8285
D1 1N4148 (through hole)
D2 NXP PTVS5V0P1UP (SOD-128) 791-9052
NXP PTVS5V0P1UTP (alternative) 791-9055
C1-C2 0.1uF ceramic disc (4mm pitch)
C3 Vishay 293D106X9020B2TE3 (3528) 684-3904
Q1 2N3904 (TO-92)
Q2 BC212L (TO-92)
U1-U2 74LS38 (DIP14) 709-2292
R1,R3-R13 1K,5%,1/8W (through hole)
R2 33R,1%,1/4W (through hole) 506-4683
P9 TE/AMP 171826-4 4-pin header 680-1225

View file

@ -0,0 +1,616 @@
EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# +5V
#
DEF +5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "+5V" 0 140 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# 74LS26
#
DEF 74LS26 U 0 30 Y Y 4 F N
F0 "U" 0 50 60 H V C CNN
F1 "74LS26" 0 -50 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS 74LS38
DRAW
X GND 7 -200 -200 0 U 40 40 0 0 W N
X VCC 14 -200 200 0 U 40 40 0 0 W N
A 100 0 200 896 -896 0 1 0 N 101 200 101 -199
P 4 0 1 0 100 200 -300 200 -300 -200 100 -200 N
X ~ 1 -600 100 300 R 60 60 1 1 I
X ~ 2 -600 -100 300 R 60 60 1 1 I
X ~ 3 600 0 300 L 60 60 1 1 C I
X ~ 4 -600 100 300 R 60 60 2 1 I
X ~ 5 -600 -100 300 R 60 60 2 1 I
X ~ 6 600 0 300 L 60 60 2 1 C I
X ~ 8 600 0 300 L 60 60 3 1 C I
X ~ 9 -600 100 300 R 60 60 3 1 I
X ~ 10 -600 -100 300 R 60 60 3 1 I
X ~ 11 600 0 300 L 60 60 4 1 C I
X ~ 12 -600 100 300 R 60 60 4 1 I
X ~ 13 -600 -100 300 R 60 60 4 1 I
A -470 0 262 495 -495 0 2 0 N -300 199 -300 -198
A -2 126 326 -897 -225 0 2 0 N 0 -199 299 2
A 4 -120 320 906 221 0 2 0 N 2 200 300 0
P 2 0 2 0 -300 -200 0 -200 N
P 2 0 2 0 -300 200 0 200 N
X ~ 1 -600 100 370 R 60 60 1 2 I I
X ~ 2 -600 -100 370 R 60 60 1 2 I I
X ~ 3 600 0 300 L 60 60 1 2 C
X ~ 4 -600 100 370 R 60 60 2 2 I I
X ~ 5 -600 -100 370 R 60 60 2 2 I I
X ~ 6 600 0 300 L 60 60 2 2 C
X ~ 8 600 0 300 L 60 60 3 2 C
X ~ 9 -600 100 370 R 60 60 3 2 I I
X ~ 10 -600 -100 370 R 60 60 3 2 I I
X ~ 11 600 0 300 L 60 60 4 2 C
X ~ 12 -600 100 370 R 60 60 4 2 I I
X ~ 13 -600 -100 370 R 60 60 4 2 I I
ENDDRAW
ENDDEF
#
# C
#
DEF C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "C" 25 -100 50 H V L CNN
F2 "" 38 -150 30 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
C?
C_????_*
C_????
SMD*_c
Capacitor*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CONN_01X03
#
DEF CONN_01X03 P 0 40 Y N 1 F N
F0 "P" 0 200 50 H V C CNN
F1 "CONN_01X03" 100 0 50 V V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
Pin_Header_Straight_1X03
Pin_Header_Angled_1X03
Socket_Strip_Straight_1X03
Socket_Strip_Angled_1X03
$ENDFPLIST
DRAW
S -50 -95 10 -105 0 1 0 N
S -50 5 10 -5 0 1 0 N
S -50 105 10 95 0 1 0 N
S -50 150 50 -150 0 1 0 N
X P1 1 -200 100 150 R 50 50 1 1 P
X P2 2 -200 0 150 R 50 50 1 1 P
X P3 3 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_01X04
#
DEF CONN_01X04 P 0 40 Y N 1 F N
F0 "P" 0 250 50 H V C CNN
F1 "CONN_01X04" 100 0 50 V V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
Pin_Header_Straight_1X04
Pin_Header_Angled_1X04
Socket_Strip_Straight_1X04
Socket_Strip_Angled_1X04
$ENDFPLIST
DRAW
S -50 -145 10 -155 0 1 0 N
S -50 -45 10 -55 0 1 0 N
S -50 55 10 45 0 1 0 N
S -50 155 10 145 0 1 0 N
S -50 200 50 -200 0 1 0 N
X P1 1 -200 150 150 R 50 50 1 1 P
X P2 2 -200 50 150 R 50 50 1 1 P
X P3 3 -200 -50 150 R 50 50 1 1 P
X P4 4 -200 -150 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X03
#
DEF CONN_02X03 P 0 1 Y N 1 F N
F0 "P" 0 200 50 H V C CNN
F1 "CONN_02X03" 0 -200 50 H V C CNN
F2 "" 0 -1200 60 H V C CNN
F3 "" 0 -1200 60 H V C CNN
$FPLIST
Pin_Header_Straight_2X03
Pin_Header_Angled_2X03
Socket_Strip_Straight_2X03
Socket_Strip_Angled_2X03
$ENDFPLIST
DRAW
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 150 100 -150 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
X P1 1 -250 100 150 R 50 50 1 1 P
X P2 2 250 100 150 L 50 50 1 1 P
X P3 3 -250 0 150 R 50 50 1 1 P
X P4 4 250 0 150 L 50 50 1 1 P
X P5 5 -250 -100 150 R 50 50 1 1 P
X P6 6 250 -100 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X04
#
DEF CONN_02X04 P 0 1 Y N 1 F N
F0 "P" 0 250 50 H V C CNN
F1 "CONN_02X04" 0 -250 50 H V C CNN
F2 "" 0 -1200 60 H V C CNN
F3 "" 0 -1200 60 H V C CNN
$FPLIST
Pin_Header_Straight_2X04
Pin_Header_Angled_2X04
Socket_Strip_Straight_2X04
Socket_Strip_Angled_2X04
$ENDFPLIST
DRAW
S -100 -145 -50 -155 0 1 0 N
S -100 -45 -50 -55 0 1 0 N
S -100 55 -50 45 0 1 0 N
S -100 155 -50 145 0 1 0 N
S -100 200 100 -200 0 1 0 N
S 50 -145 100 -155 0 1 0 N
S 50 -45 100 -55 0 1 0 N
S 50 55 100 45 0 1 0 N
S 50 155 100 145 0 1 0 N
X P1 1 -250 150 150 R 50 50 1 1 P
X P2 2 250 150 150 L 50 50 1 1 P
X P3 3 -250 50 150 R 50 50 1 1 P
X P4 4 250 50 150 L 50 50 1 1 P
X P5 5 -250 -50 150 R 50 50 1 1 P
X P6 6 250 -50 150 L 50 50 1 1 P
X P7 7 -250 -150 150 R 50 50 1 1 P
X P8 8 250 -150 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X07
#
DEF CONN_02X07 P 0 1 Y N 1 F N
F0 "P" 0 400 50 H V C CNN
F1 "CONN_02X07" 0 0 50 V V C CNN
F2 "" 0 -1200 60 H V C CNN
F3 "" 0 -1200 60 H V C CNN
$FPLIST
Pin_Header_Straight_2X07
Pin_Header_Angled_2X07
Socket_Strip_Straight_2X07
Socket_Strip_Angled_2X07
$ENDFPLIST
DRAW
S -100 -295 -50 -305 0 1 0 N
S -100 -195 -50 -205 0 1 0 N
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 205 -50 195 0 1 0 N
S -100 305 -50 295 0 1 0 N
S -100 350 100 -350 0 1 0 N
S 50 -295 100 -305 0 1 0 N
S 50 -195 100 -205 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
S 50 205 100 195 0 1 0 N
S 50 305 100 295 0 1 0 N
X P1 1 -250 300 150 R 50 50 1 1 P
X P2 2 250 300 150 L 50 50 1 1 P
X P3 3 -250 200 150 R 50 50 1 1 P
X P4 4 250 200 150 L 50 50 1 1 P
X P5 5 -250 100 150 R 50 50 1 1 P
X P6 6 250 100 150 L 50 50 1 1 P
X P7 7 -250 0 150 R 50 50 1 1 P
X P8 8 250 0 150 L 50 50 1 1 P
X P9 9 -250 -100 150 R 50 50 1 1 P
X P10 10 250 -100 150 L 50 50 1 1 P
X P11 11 -250 -200 150 R 50 50 1 1 P
X P12 12 250 -200 150 L 50 50 1 1 P
X P13 13 -250 -300 150 R 50 50 1 1 P
X P14 14 250 -300 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X17
#
DEF CONN_02X17 P 0 1 Y N 1 F N
F0 "P" 0 900 50 H V C CNN
F1 "CONN_02X17" 0 0 50 V V C CNN
F2 "" 0 -1100 60 H V C CNN
F3 "" 0 -1100 60 H V C CNN
$FPLIST
Pin_Header_Straight_2X17
Pin_Header_Angled_2X17
Socket_Strip_Straight_2X17
Socket_Strip_Angled_2X17
$ENDFPLIST
DRAW
S -100 -795 -50 -805 0 1 0 N
S -100 -695 -50 -705 0 1 0 N
S -100 -595 -50 -605 0 1 0 N
S -100 -495 -50 -505 0 1 0 N
S -100 -395 -50 -405 0 1 0 N
S -100 -295 -50 -305 0 1 0 N
S -100 -195 -50 -205 0 1 0 N
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 205 -50 195 0 1 0 N
S -100 305 -50 295 0 1 0 N
S -100 405 -50 395 0 1 0 N
S -100 505 -50 495 0 1 0 N
S -100 605 -50 595 0 1 0 N
S -100 705 -50 695 0 1 0 N
S -100 805 -50 795 0 1 0 N
S -100 850 100 -850 0 1 0 N
S 50 -795 100 -805 0 1 0 N
S 50 -695 100 -705 0 1 0 N
S 50 -595 100 -605 0 1 0 N
S 50 -495 100 -505 0 1 0 N
S 50 -395 100 -405 0 1 0 N
S 50 -295 100 -305 0 1 0 N
S 50 -195 100 -205 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
S 50 205 100 195 0 1 0 N
S 50 305 100 295 0 1 0 N
S 50 405 100 395 0 1 0 N
S 50 505 100 495 0 1 0 N
S 50 605 100 595 0 1 0 N
S 50 705 100 695 0 1 0 N
S 50 805 100 795 0 1 0 N
X P1 1 -250 800 150 R 50 50 1 1 P
X P2 2 250 800 150 L 50 50 1 1 P
X P3 3 -250 700 150 R 50 50 1 1 P
X P4 4 250 700 150 L 50 50 1 1 P
X P5 5 -250 600 150 R 50 50 1 1 P
X P6 6 250 600 150 L 50 50 1 1 P
X P7 7 -250 500 150 R 50 50 1 1 P
X P8 8 250 500 150 L 50 50 1 1 P
X P9 9 -250 400 150 R 50 50 1 1 P
X P10 10 250 400 150 L 50 50 1 1 P
X P20 20 250 -100 150 L 50 50 1 1 P
X P30 30 250 -600 150 L 50 50 1 1 P
X P11 11 -250 300 150 R 50 50 1 1 P
X P21 21 -250 -200 150 R 50 50 1 1 P
X P31 31 -250 -700 150 R 50 50 1 1 P
X P12 12 250 300 150 L 50 50 1 1 P
X P22 22 250 -200 150 L 50 50 1 1 P
X P32 32 250 -700 150 L 50 50 1 1 P
X P13 13 -250 200 150 R 50 50 1 1 P
X P23 23 -250 -300 150 R 50 50 1 1 P
X P33 33 -250 -800 150 R 50 50 1 1 P
X P14 14 250 200 150 L 50 50 1 1 P
X P24 24 250 -300 150 L 50 50 1 1 P
X P34 34 250 -800 150 L 50 50 1 1 P
X P15 15 -250 100 150 R 50 50 1 1 P
X P25 25 -250 -400 150 R 50 50 1 1 P
X P16 16 250 100 150 L 50 50 1 1 P
X P26 26 250 -400 150 L 50 50 1 1 P
X P17 17 -250 0 150 R 50 50 1 1 P
X P27 27 -250 -500 150 R 50 50 1 1 P
X P18 18 250 0 150 L 50 50 1 1 P
X P28 28 250 -500 150 L 50 50 1 1 P
X P19 19 -250 -100 150 R 50 50 1 1 P
X P29 29 -250 -600 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CP
#
DEF CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "CP" 25 -100 50 H V L CNN
F2 "" 38 -150 30 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
CP*
Elko*
TantalC*
C*elec
c_elec*
SMD*_Pol
$ENDFPLIST
DRAW
S -90 20 -90 40 0 1 0 N
S -90 20 90 20 0 1 0 N
S -70 90 -30 90 0 1 0 N
S -50 70 -50 110 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
S 90 40 -90 40 0 1 0 N
S 90 40 90 20 0 1 0 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# D
#
DEF D D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "D" 0 -100 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
Diode_*
D-Pak_TO252AA
*SingleDiode
*_Diode_*
*SingleDiode*
$ENDFPLIST
DRAW
P 2 0 1 6 -50 50 -50 -50 N
P 3 0 1 0 50 50 -50 0 50 -50 F
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# F_Small
#
DEF F_Small F 0 10 N N 1 F N
F0 "F" -40 60 50 H V L CNN
F1 "F_Small" -120 -60 50 H V L CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
CP*
SM*
$ENDFPLIST
DRAW
S -50 20 50 -20 0 1 0 N
P 2 0 1 0 -50 0 50 0 N
X ~ 1 -100 0 50 R 40 40 1 1 P
X ~ 2 100 0 50 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# GND
#
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "GND" 0 -150 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# HDR_3X5
#
DEF HDR_3X5 P 0 40 Y Y 1 F N
F0 "P" 0 0 60 H V C CNN
F1 "HDR_3X5" 0 -400 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 -100 300 -700 0 1 0 N
X ~ 1 -500 -200 200 R 50 50 1 1 I
X ~ 2 -500 -300 200 R 50 50 1 1 I
X ~ 3 -500 -400 200 R 50 50 1 1 I
X ~ 4 -500 -500 200 R 50 50 1 1 I
X ~ 5 -500 -600 200 R 50 50 1 1 I
X ~ 6 500 -600 200 L 50 50 1 1 I
X ~ 7 500 -500 200 L 50 50 1 1 I
X ~ 8 500 -400 200 L 50 50 1 1 I
X ~ 9 500 -300 200 L 50 50 1 1 I
X ~ 10 500 -200 200 L 50 50 1 1 I
X ~ 11 -200 -900 200 U 50 50 1 1 I
X ~ 12 -100 -900 200 U 50 50 1 1 I
X ~ 13 0 -900 200 U 50 50 1 1 I
X ~ 14 100 -900 200 U 50 50 1 1 I
X ~ 15 200 -900 200 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# PWR_FLAG
#
DEF PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 95 50 H I C CNN
F1 "PWR_FLAG" 0 180 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
X pwr 1 0 0 0 U 20 20 0 0 w
P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
ENDDRAW
ENDDEF
#
# Q_NPN_EBC
#
DEF Q_NPN_EBC Q 0 0 Y N 1 F N
F0 "Q" 300 50 50 H V R CNN
F1 "Q_NPN_EBC" 600 -50 50 H V R CNN
F2 "" 200 100 29 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
X E 1 100 -200 100 U 50 50 1 1 P
X B 2 -200 0 225 R 50 50 1 1 P
X C 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Q_PNP_ECB
#
DEF Q_PNP_ECB Q 0 0 Y N 1 F N
F0 "Q" 300 50 50 H V R CNN
F1 "Q_PNP_ECB" 600 -50 50 H V R CNN
F2 "" 200 100 29 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
X E 1 100 -200 100 U 50 50 1 1 P
X C 2 100 200 100 D 50 50 1 1 P
X B 3 -200 0 225 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# R
#
DEF R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "R" 0 0 50 V V C CNN
F2 "" -70 0 30 V V C CNN
F3 "" 0 0 30 H V C CNN
$FPLIST
R_*
Resistor_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 60 60 1 1 P
X ~ 2 0 -150 50 U 60 60 1 1 P
ENDDRAW
ENDDEF
#
# STM32_A
#
DEF STM32_A P 0 40 Y Y 1 F N
F0 "P" 0 0 60 H V C CNN
F1 "STM32_A" 0 -1500 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 -100 300 -1400 0 1 0 N
X GND 1 -500 -200 200 R 50 50 1 1 P
X GND 2 500 -200 200 L 50 50 1 1 P
X RX 3 -500 -300 200 R 50 50 1 1 P
X TX 4 500 -300 200 L 50 50 1 1 P
X PA8 5 -500 -400 200 R 50 50 1 1 P
X PB15 6 500 -400 200 L 50 50 1 1 P
X PB14 7 -500 -500 200 R 50 50 1 1 P
X PB13 8 500 -500 200 L 50 50 1 1 P
X PB12 9 -500 -600 200 R 50 50 1 1 P
X PB11 10 500 -600 200 L 50 50 1 1 P
X PA3 20 500 -1100 200 L 50 50 1 1 P
X PB2 11 -500 -700 200 R 50 50 1 1 P
X PA0 21 -500 -1200 200 R 50 50 1 1 P
X PB10 12 500 -700 200 L 50 50 1 1 P
X PA1 22 500 -1200 200 L 50 50 1 1 P
X PB0 13 -500 -800 200 R 50 50 1 1 P
X 3V3 23 -500 -1300 200 R 50 50 1 1 P
X PB1 14 500 -800 200 L 50 50 1 1 P
X 3V3 24 500 -1300 200 L 50 50 1 1 P
X PA6 15 -500 -900 200 R 50 50 1 1 P
X PA7 16 500 -900 200 L 50 50 1 1 P
X PA4 17 -500 -1000 200 R 50 50 1 1 P
X PA5 18 500 -1000 200 L 50 50 1 1 P
X PA2 19 -500 -1100 200 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# STM32_B
#
DEF STM32_B P 0 40 Y Y 1 F N
F0 "P" 0 0 60 H V C CNN
F1 "STM32_B" 0 -1500 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 -100 300 -1400 0 1 0 N
X GND 1 -500 -200 200 R 50 50 1 1 P
X GND 2 500 -200 200 L 50 50 1 1 P
X PA12 3 -500 -300 200 R 50 50 1 1 P
X PA11 4 500 -300 200 L 50 50 1 1 P
X PA14 5 -500 -400 200 R 50 50 1 1 P
X PA13 6 500 -400 200 L 50 50 1 1 P
X PB3 7 -500 -500 200 R 50 50 1 1 P
X PA15 8 500 -500 200 L 50 50 1 1 P
X PB5 9 -500 -600 200 R 50 50 1 1 P
X PB4 10 500 -600 200 L 50 50 1 1 P
X PC15 20 500 -1100 200 L 50 50 1 1 P
X PB7 11 -500 -700 200 R 50 50 1 1 P
X NST 21 -500 -1200 200 R 50 50 1 1 P
X PB6 12 500 -700 200 L 50 50 1 1 P
X PD1 22 500 -1200 200 L 50 50 1 1 P
X PB8 13 -500 -800 200 R 50 50 1 1 P
X 3V3 23 -500 -1300 200 R 50 50 1 1 P
X BT0 14 500 -800 200 L 50 50 1 1 P
X 3V3 24 500 -1300 200 L 50 50 1 1 P
X VBAT 15 -500 -900 200 R 50 50 1 1 P
X PB9 16 500 -900 200 L 50 50 1 1 P
X PC14 17 -500 -1000 200 R 50 50 1 1 P
X PC13 18 500 -1000 200 L 50 50 1 1 P
X PD0 19 -500 -1100 200 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# VCC
#
DEF VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VCC" 0 150 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 0 75 25 0 1 0 N
P 2 0 1 0 0 0 0 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# ZENER
#
DEF ZENER D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "ZENER" 0 -100 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
D?
SO*
SM*
$ENDFPLIST
DRAW
P 5 0 1 8 -70 50 -50 30 -50 -30 -30 -50 -30 -50 N
P 5 0 1 0 -50 0 50 50 50 -50 -50 0 -50 0 F
X K 1 -200 0 150 R 50 50 1 1 P
X A 2 200 0 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

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update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=microcontrollers
LibName13=dsp
LibName14=microchip
LibName15=analog_switches
LibName16=motorola
LibName17=texas
LibName18=intel
LibName19=audio
LibName20=interface
LibName21=digital-audio
LibName22=philips
LibName23=display
LibName24=cypress
LibName25=siliconi
LibName26=opto
LibName27=atmel
LibName28=contrib
LibName29=valves

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71
pcb/LC/150/FF-LC150.pro Normal file
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update=Fri 03 Jul 2015 05:29:28 BST
version=1
last_client=kicad
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[general]
version=1
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60
[eeschema]
version=1
LibDir=../..
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=microcontrollers
LibName13=dsp
LibName14=microchip
LibName15=analog_switches
LibName16=motorola
LibName17=texas
LibName18=intel
LibName19=audio
LibName20=interface
LibName21=digital-audio
LibName22=philips
LibName23=display
LibName24=cypress
LibName25=siliconi
LibName26=opto
LibName27=atmel
LibName28=contrib
LibName29=valves
LibName30=FF

1527
pcb/LC/150/FF-LC150.sch Normal file

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34
pcb/LC/150/README Normal file
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This project was designed using a development snapshot of KiCad.
FF-LC150
--------
KiCad project for schematic and 10cmx5cm single-board layout.
Can be opened in the KiCad project manager.
FF-LC150-bom.txt
----------------
Bill of materials for the above design, excluding pin headers
and socket strips.
FF-LC150-panel
--------------
Two-up 10x10cm panelisation of the above layout, with cutouts
and break-away mousebites. Should be opened directly in Pcbnew.
Generating Gerbers
------------------
Nothing special to note here. Some of these options are important to
follow, especially for the drill file.
Options:
Plot footprint values
Plot footprint references
Exclude PCB edge layer from other layers
Gerber Options:
Use Protel filename extensions
Format: 4.6
Drill files:
Drill Units: Inches
Zeros Format: Suppress leading zeros
Precision: 2:4
Drill Options: Minimal header
Drill Origin: Absolute

3
pcb/LC/150/fp-lib-table Normal file
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(fp_lib_table
(lib (name FF)(type KiCad)(uri "$(KIPRJMOD)/FF.pretty")(options "")(descr ""))
)

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REF PART DESCRIPTION RS ORDER
=== ================ ========
F1 Bourns MF-PSMF075X-2 (0805) 691-7516
D1 1N4148 (through hole)
D2 NXP PTVS5V0P1UP (SOD-128) 791-9052
NXP PTVS5V0P1UTP (alternative) 791-9055
C1-C2 0.1uF (0805) 390-990
C3 Vishay 293D106X9020B2TE3 (3528) 684-3904
Q1 2N3904 (TO-92)
Q2 2N3906 (TO-92)
U1 Maple Mini STM32 (DIP40)
U2-U3 74LS38 (DIP14) 709-2292
R1 33R,1%,1/4W (through hole) 506-4683
R2 10K,5%,1/8W (through hole)
R3-R16 1K,5%,1/8W (through hole)
P5 TE/AMP 171826-4 4-pin header 680-1225

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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# +5V
#
DEF +5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "+5V" 0 140 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# 74LS26
#
DEF 74LS26 U 0 30 Y Y 4 F N
F0 "U" 0 50 60 H V C CNN
F1 "74LS26" 0 -50 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS 74LS38
DRAW
X GND 7 -200 -200 0 U 40 40 0 0 W N
X VCC 14 -200 200 0 U 40 40 0 0 W N
A 100 0 200 896 -896 0 1 0 N 101 200 101 -199
P 4 0 1 0 100 200 -300 200 -300 -200 100 -200 N
X ~ 1 -600 100 300 R 60 60 1 1 I
X ~ 2 -600 -100 300 R 60 60 1 1 I
X ~ 3 600 0 300 L 60 60 1 1 C I
X ~ 4 -600 100 300 R 60 60 2 1 I
X ~ 5 -600 -100 300 R 60 60 2 1 I
X ~ 6 600 0 300 L 60 60 2 1 C I
X ~ 8 600 0 300 L 60 60 3 1 C I
X ~ 9 -600 100 300 R 60 60 3 1 I
X ~ 10 -600 -100 300 R 60 60 3 1 I
X ~ 11 600 0 300 L 60 60 4 1 C I
X ~ 12 -600 100 300 R 60 60 4 1 I
X ~ 13 -600 -100 300 R 60 60 4 1 I
A -470 0 262 495 -495 0 2 0 N -300 199 -300 -198
A -2 126 326 -897 -225 0 2 0 N 0 -199 299 2
A 4 -120 320 906 221 0 2 0 N 2 200 300 0
P 2 0 2 0 -300 -200 0 -200 N
P 2 0 2 0 -300 200 0 200 N
X ~ 1 -600 100 370 R 60 60 1 2 I I
X ~ 2 -600 -100 370 R 60 60 1 2 I I
X ~ 3 600 0 300 L 60 60 1 2 C
X ~ 4 -600 100 370 R 60 60 2 2 I I
X ~ 5 -600 -100 370 R 60 60 2 2 I I
X ~ 6 600 0 300 L 60 60 2 2 C
X ~ 8 600 0 300 L 60 60 3 2 C
X ~ 9 -600 100 370 R 60 60 3 2 I I
X ~ 10 -600 -100 370 R 60 60 3 2 I I
X ~ 11 600 0 300 L 60 60 4 2 C
X ~ 12 -600 100 370 R 60 60 4 2 I I
X ~ 13 -600 -100 370 R 60 60 4 2 I I
ENDDRAW
ENDDEF
#
# C
#
DEF C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "C" 25 -100 50 H V L CNN
F2 "" 38 -150 30 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
C?
C_????_*
C_????
SMD*_c
Capacitor*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CONN_01X04
#
DEF CONN_01X04 P 0 40 Y N 1 F N
F0 "P" 0 250 50 H V C CNN
F1 "CONN_01X04" 100 0 50 V V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
Pin_Header_Straight_1X04
Pin_Header_Angled_1X04
Socket_Strip_Straight_1X04
Socket_Strip_Angled_1X04
$ENDFPLIST
DRAW
S -50 -145 10 -155 0 1 0 N
S -50 -45 10 -55 0 1 0 N
S -50 55 10 45 0 1 0 N
S -50 155 10 145 0 1 0 N
S -50 200 50 -200 0 1 0 N
X P1 1 -200 150 150 R 50 50 1 1 P
X P2 2 -200 50 150 R 50 50 1 1 P
X P3 3 -200 -50 150 R 50 50 1 1 P
X P4 4 -200 -150 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X03
#
DEF CONN_02X03 P 0 1 Y N 1 F N
F0 "P" 0 200 50 H V C CNN
F1 "CONN_02X03" 0 -200 50 H V C CNN
F2 "" 0 -1200 60 H V C CNN
F3 "" 0 -1200 60 H V C CNN
$FPLIST
Pin_Header_Straight_2X03
Pin_Header_Angled_2X03
Socket_Strip_Straight_2X03
Socket_Strip_Angled_2X03
$ENDFPLIST
DRAW
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 150 100 -150 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
X P1 1 -250 100 150 R 50 50 1 1 P
X P2 2 250 100 150 L 50 50 1 1 P
X P3 3 -250 0 150 R 50 50 1 1 P
X P4 4 250 0 150 L 50 50 1 1 P
X P5 5 -250 -100 150 R 50 50 1 1 P
X P6 6 250 -100 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X07
#
DEF CONN_02X07 P 0 1 Y N 1 F N
F0 "P" 0 400 50 H V C CNN
F1 "CONN_02X07" 0 0 50 V V C CNN
F2 "" 0 -1200 60 H V C CNN
F3 "" 0 -1200 60 H V C CNN
$FPLIST
Pin_Header_Straight_2X07
Pin_Header_Angled_2X07
Socket_Strip_Straight_2X07
Socket_Strip_Angled_2X07
$ENDFPLIST
DRAW
S -100 -295 -50 -305 0 1 0 N
S -100 -195 -50 -205 0 1 0 N
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 205 -50 195 0 1 0 N
S -100 305 -50 295 0 1 0 N
S -100 350 100 -350 0 1 0 N
S 50 -295 100 -305 0 1 0 N
S 50 -195 100 -205 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
S 50 205 100 195 0 1 0 N
S 50 305 100 295 0 1 0 N
X P1 1 -250 300 150 R 50 50 1 1 P
X P2 2 250 300 150 L 50 50 1 1 P
X P3 3 -250 200 150 R 50 50 1 1 P
X P4 4 250 200 150 L 50 50 1 1 P
X P5 5 -250 100 150 R 50 50 1 1 P
X P6 6 250 100 150 L 50 50 1 1 P
X P7 7 -250 0 150 R 50 50 1 1 P
X P8 8 250 0 150 L 50 50 1 1 P
X P9 9 -250 -100 150 R 50 50 1 1 P
X P10 10 250 -100 150 L 50 50 1 1 P
X P11 11 -250 -200 150 R 50 50 1 1 P
X P12 12 250 -200 150 L 50 50 1 1 P
X P13 13 -250 -300 150 R 50 50 1 1 P
X P14 14 250 -300 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X17
#
DEF CONN_02X17 P 0 1 Y N 1 F N
F0 "P" 0 900 50 H V C CNN
F1 "CONN_02X17" 0 0 50 V V C CNN
F2 "" 0 -1100 60 H V C CNN
F3 "" 0 -1100 60 H V C CNN
$FPLIST
Pin_Header_Straight_2X17
Pin_Header_Angled_2X17
Socket_Strip_Straight_2X17
Socket_Strip_Angled_2X17
$ENDFPLIST
DRAW
S -100 -795 -50 -805 0 1 0 N
S -100 -695 -50 -705 0 1 0 N
S -100 -595 -50 -605 0 1 0 N
S -100 -495 -50 -505 0 1 0 N
S -100 -395 -50 -405 0 1 0 N
S -100 -295 -50 -305 0 1 0 N
S -100 -195 -50 -205 0 1 0 N
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 205 -50 195 0 1 0 N
S -100 305 -50 295 0 1 0 N
S -100 405 -50 395 0 1 0 N
S -100 505 -50 495 0 1 0 N
S -100 605 -50 595 0 1 0 N
S -100 705 -50 695 0 1 0 N
S -100 805 -50 795 0 1 0 N
S -100 850 100 -850 0 1 0 N
S 50 -795 100 -805 0 1 0 N
S 50 -695 100 -705 0 1 0 N
S 50 -595 100 -605 0 1 0 N
S 50 -495 100 -505 0 1 0 N
S 50 -395 100 -405 0 1 0 N
S 50 -295 100 -305 0 1 0 N
S 50 -195 100 -205 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
S 50 205 100 195 0 1 0 N
S 50 305 100 295 0 1 0 N
S 50 405 100 395 0 1 0 N
S 50 505 100 495 0 1 0 N
S 50 605 100 595 0 1 0 N
S 50 705 100 695 0 1 0 N
S 50 805 100 795 0 1 0 N
X P1 1 -250 800 150 R 50 50 1 1 P
X P2 2 250 800 150 L 50 50 1 1 P
X P3 3 -250 700 150 R 50 50 1 1 P
X P4 4 250 700 150 L 50 50 1 1 P
X P5 5 -250 600 150 R 50 50 1 1 P
X P6 6 250 600 150 L 50 50 1 1 P
X P7 7 -250 500 150 R 50 50 1 1 P
X P8 8 250 500 150 L 50 50 1 1 P
X P9 9 -250 400 150 R 50 50 1 1 P
X P10 10 250 400 150 L 50 50 1 1 P
X P20 20 250 -100 150 L 50 50 1 1 P
X P30 30 250 -600 150 L 50 50 1 1 P
X P11 11 -250 300 150 R 50 50 1 1 P
X P21 21 -250 -200 150 R 50 50 1 1 P
X P31 31 -250 -700 150 R 50 50 1 1 P
X P12 12 250 300 150 L 50 50 1 1 P
X P22 22 250 -200 150 L 50 50 1 1 P
X P32 32 250 -700 150 L 50 50 1 1 P
X P13 13 -250 200 150 R 50 50 1 1 P
X P23 23 -250 -300 150 R 50 50 1 1 P
X P33 33 -250 -800 150 R 50 50 1 1 P
X P14 14 250 200 150 L 50 50 1 1 P
X P24 24 250 -300 150 L 50 50 1 1 P
X P34 34 250 -800 150 L 50 50 1 1 P
X P15 15 -250 100 150 R 50 50 1 1 P
X P25 25 -250 -400 150 R 50 50 1 1 P
X P16 16 250 100 150 L 50 50 1 1 P
X P26 26 250 -400 150 L 50 50 1 1 P
X P17 17 -250 0 150 R 50 50 1 1 P
X P27 27 -250 -500 150 R 50 50 1 1 P
X P18 18 250 0 150 L 50 50 1 1 P
X P28 28 250 -500 150 L 50 50 1 1 P
X P19 19 -250 -100 150 R 50 50 1 1 P
X P29 29 -250 -600 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CP
#
DEF CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "CP" 25 -100 50 H V L CNN
F2 "" 38 -150 30 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
CP*
Elko*
TantalC*
C*elec
c_elec*
SMD*_Pol
$ENDFPLIST
DRAW
S -90 20 -90 40 0 1 0 N
S -90 20 90 20 0 1 0 N
S -70 90 -30 90 0 1 0 N
S -50 70 -50 110 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
S 90 40 -90 40 0 1 0 N
S 90 40 90 20 0 1 0 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# D
#
DEF D D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "D" 0 -100 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
Diode_*
D-Pak_TO252AA
*SingleDiode
*_Diode_*
*SingleDiode*
$ENDFPLIST
DRAW
P 2 0 1 6 -50 50 -50 -50 N
P 3 0 1 0 50 50 -50 0 50 -50 F
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# F_Small
#
DEF F_Small F 0 10 N N 1 F N
F0 "F" -40 60 50 H V L CNN
F1 "F_Small" -120 -60 50 H V L CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
CP*
SM*
$ENDFPLIST
DRAW
S -50 20 50 -20 0 1 0 N
P 2 0 1 0 -50 0 50 0 N
X ~ 1 -100 0 50 R 40 40 1 1 P
X ~ 2 100 0 50 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# GND
#
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "GND" 0 -150 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# HDR_3X5
#
DEF HDR_3X5 P 0 40 Y Y 1 F N
F0 "P" 0 0 60 H V C CNN
F1 "HDR_3X5" 0 -400 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 -100 300 -700 0 1 0 N
X ~ 1 -500 -200 200 R 50 50 1 1 I
X ~ 2 -500 -300 200 R 50 50 1 1 I
X ~ 3 -500 -400 200 R 50 50 1 1 I
X ~ 4 -500 -500 200 R 50 50 1 1 I
X ~ 5 -500 -600 200 R 50 50 1 1 I
X ~ 6 500 -600 200 L 50 50 1 1 I
X ~ 7 500 -500 200 L 50 50 1 1 I
X ~ 8 500 -400 200 L 50 50 1 1 I
X ~ 9 500 -300 200 L 50 50 1 1 I
X ~ 10 500 -200 200 L 50 50 1 1 I
X ~ 11 -200 -900 200 U 50 50 1 1 I
X ~ 12 -100 -900 200 U 50 50 1 1 I
X ~ 13 0 -900 200 U 50 50 1 1 I
X ~ 14 100 -900 200 U 50 50 1 1 I
X ~ 15 200 -900 200 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# MAPLE_MINI
#
DEF MAPLE_MINI U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "MAPLE_MINI" 0 -2250 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -550 -50 550 -2150 0 1 0 N
X VIn 1 -750 -150 200 R 50 50 1 1 P
X D0/PB11 2 -750 -250 200 R 50 50 1 1 P
X D1/PB10 3 -750 -350 200 R 50 50 1 1 P
X D2/PB2/BT1 4 -750 -450 200 R 50 50 1 1 P
X D3/PB0 5 -750 -550 200 R 50 50 1 1 P
X D4/PA7 6 -750 -650 200 R 50 50 1 1 P
X D5/PA6 7 -750 -750 200 R 50 50 1 1 P
X D6/PA5 8 -750 -850 200 R 50 50 1 1 P
X D7/PA4 9 -750 -950 200 R 50 50 1 1 P
X D8/PA3 10 -750 -1050 200 R 50 50 1 1 P
X 3V3 20 -750 -2050 200 R 50 50 1 1 P
X D21/PA14 30 750 -1150 200 L 50 50 1 1 P
X D31/PB12 40 750 -150 200 L 50 50 1 1 P
X D9/PA2 11 -750 -1150 200 R 50 50 1 1 P
X 3V3 21 750 -2050 200 L 50 50 1 1 P
X D22/PA13 31 750 -1050 200 L 50 50 1 1 P
X D10/PA1 12 -750 -1250 200 R 50 50 1 1 P
X GND 22 750 -1950 200 L 50 50 1 1 P
X D23/PA12 32 750 -950 200 L 50 50 1 1 P
X D11/PA0 13 -750 -1350 200 R 50 50 1 1 P
X D32/PB8/Btn 23 750 -1850 200 L 50 50 1 1 P
X D24/PA11 33 750 -850 200 L 50 50 1 1 P
X RESET 14 -750 -1450 200 R 50 50 1 1 P
X D15/PB7 24 750 -1750 200 L 50 50 1 1 P
X D25/PA10 34 750 -750 200 L 50 50 1 1 P
X D12/PC15 15 -750 -1550 200 R 50 50 1 1 P
X D16/PB6 25 750 -1650 200 L 50 50 1 1 P
X D26/PA9 35 750 -650 200 L 50 50 1 1 P
X D13/PC14 16 -750 -1650 200 R 50 50 1 1 P
X D17/PB5 26 750 -1550 200 L 50 50 1 1 P
X D27/PA8 36 750 -550 200 L 50 50 1 1 P
X D14/PC13 17 -750 -1750 200 R 50 50 1 1 P
X D18/PB4 27 750 -1450 200 L 50 50 1 1 P
X D28/PB15 37 750 -450 200 L 50 50 1 1 P
X VBat 18 -750 -1850 200 R 50 50 1 1 P
X D19/PB3 28 750 -1350 200 L 50 50 1 1 P
X D29/PB14 38 750 -350 200 L 50 50 1 1 P
X GND 19 -750 -1950 200 R 50 50 1 1 P
X D20/PA15 29 750 -1250 200 L 50 50 1 1 P
X D30/PB13 39 750 -250 200 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# PWR_FLAG
#
DEF PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 95 50 H I C CNN
F1 "PWR_FLAG" 0 180 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
X pwr 1 0 0 0 U 20 20 0 0 w
P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
ENDDRAW
ENDDEF
#
# Q_NPN_EBC
#
DEF Q_NPN_EBC Q 0 0 Y N 1 F N
F0 "Q" 300 50 50 H V R CNN
F1 "Q_NPN_EBC" 600 -50 50 H V R CNN
F2 "" 200 100 29 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
X E 1 100 -200 100 U 50 50 1 1 P
X B 2 -200 0 225 R 50 50 1 1 P
X C 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Q_PNP_EBC
#
DEF Q_PNP_EBC Q 0 0 Y N 1 F N
F0 "Q" 300 50 50 H V R CNN
F1 "Q_PNP_EBC" 600 -50 50 H V R CNN
F2 "" 200 100 29 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
X E 1 100 -200 100 U 50 50 1 1 P
X B 2 -200 0 225 R 50 50 1 1 I
X C 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# R
#
DEF R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "R" 0 0 50 V V C CNN
F2 "" -70 0 30 V V C CNN
F3 "" 0 0 30 H V C CNN
$FPLIST
R_*
Resistor_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 60 60 1 1 P
X ~ 2 0 -150 50 U 60 60 1 1 P
ENDDRAW
ENDDEF
#
# VCC
#
DEF VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VCC" 0 150 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 0 75 25 0 1 0 N
P 2 0 1 0 0 0 0 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# ZENER
#
DEF ZENER D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "ZENER" 0 -100 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
D?
SO*
SM*
$ENDFPLIST
DRAW
P 5 0 1 8 -70 50 -50 30 -50 -30 -30 -50 -30 -50 N
P 5 0 1 0 -50 0 50 50 50 -50 -50 0 -50 0 F
X K 1 -200 0 150 R 50 50 1 1 P
X A 2 200 0 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

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update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=microcontrollers
LibName13=dsp
LibName14=microchip
LibName15=analog_switches
LibName16=motorola
LibName17=texas
LibName18=intel
LibName19=audio
LibName20=interface
LibName21=digital-audio
LibName22=philips
LibName23=display
LibName24=cypress
LibName25=siliconi
LibName26=opto
LibName27=atmel
LibName28=contrib
LibName29=valves

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71
pcb/MM/150/FF-MM150.pro Normal file
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update=Fri 03 Jul 2015 05:29:28 BST
version=1
last_client=kicad
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[general]
version=1
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60
[eeschema]
version=1
LibDir=../..
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=microcontrollers
LibName13=dsp
LibName14=microchip
LibName15=analog_switches
LibName16=motorola
LibName17=texas
LibName18=intel
LibName19=audio
LibName20=interface
LibName21=digital-audio
LibName22=philips
LibName23=display
LibName24=cypress
LibName25=siliconi
LibName26=opto
LibName27=atmel
LibName28=contrib
LibName29=valves
LibName30=FF

1477
pcb/MM/150/FF-MM150.sch Normal file

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34
pcb/MM/150/README Normal file
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This project was designed using a development snapshot of KiCad.
FF-MM150
--------
KiCad project for schematic and 10cmx5cm single-board layout.
Can be opened in the KiCad project manager.
FF-MM150-bom.txt
----------------
Bill of materials for the above design, excluding pin headers
and socket strips.
FF-MM150-panel
--------------
Two-up 10x10cm panelisation of the above layout, with cutouts
and break-away mousebites. Should be opened directly in Pcbnew.
Generating Gerbers
------------------
Nothing special to note here. Some of these options are important to
follow, especially for the drill file.
Options:
Plot footprint values
Plot footprint references
Exclude PCB edge layer from other layers
Gerber Options:
Use Protel filename extensions
Format: 4.6
Drill files:
Drill Units: Inches
Zeros Format: Suppress leading zeros
Precision: 2:4
Drill Options: Minimal header
Drill Origin: Absolute

3
pcb/MM/150/fp-lib-table Normal file
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(fp_lib_table
(lib (name FF)(type KiCad)(uri "$(KIPRJMOD)/FF.pretty")(options "")(descr ""))
)

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@ -0,0 +1,16 @@
REF PART DESCRIPTION RS ORDER
=== ================ ========
F1 Bourns MF-PSMF075X-2 (0805) 691-7516
D1 LL4148 (MiniMELF, SOD-80)
D2 NXP PTVS5V0P1UP (SOD-128) 791-9052
NXP PTVS5V0P1UTP (alternative) 791-9055
C1-C2 0.1uF (0805) 390-990
C3 Vishay 293D106X9020B2TE3 (3528) 684-3904
Q1 MMBT3904 (SOT23)
Q2 MMBT3906 (SOT23)
U1 Maple Mini STM32 (DIP40)
U2-U3 74LS38 (SOIC14)
R1 33R,1%,1/4W (1206)
R2 10K,5%,1/8W (0805)
R3-R16 1K,5%,1/8W (0805)
P5 TE/AMP 171826-4 4-pin header 680-1225

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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# +5V
#
DEF +5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# 74LS26
#
DEF 74LS26 U 0 30 Y Y 4 F N
F0 "U" 0 50 50 H V C CNN
F1 "74LS26" 0 -50 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
ALIAS 74LS38
DRAW
X GND 7 -200 -200 0 U 40 40 0 0 W N
X VCC 14 -200 200 0 U 40 40 0 0 W N
A 100 0 200 896 -896 0 1 0 N 101 200 101 -199
P 4 0 1 0 100 200 -300 200 -300 -200 100 -200 N
X ~ 1 -600 100 300 R 50 50 1 1 I
X ~ 2 -600 -100 300 R 50 50 1 1 I
X ~ 3 600 0 300 L 50 50 1 1 C I
X ~ 4 -600 100 300 R 50 50 2 1 I
X ~ 5 -600 -100 300 R 50 50 2 1 I
X ~ 6 600 0 300 L 50 50 2 1 C I
X ~ 8 600 0 300 L 50 50 3 1 C I
X ~ 9 -600 100 300 R 50 50 3 1 I
X ~ 10 -600 -100 300 R 50 50 3 1 I
X ~ 11 600 0 300 L 50 50 4 1 C I
X ~ 12 -600 100 300 R 50 50 4 1 I
X ~ 13 -600 -100 300 R 50 50 4 1 I
A -470 0 262 495 -495 0 2 0 N -300 199 -300 -198
A -2 126 326 -897 -225 0 2 0 N 0 -199 299 2
A 4 -120 320 906 221 0 2 0 N 2 200 300 0
P 2 0 2 0 -300 -200 0 -200 N
P 2 0 2 0 -300 200 0 200 N
X ~ 1 -600 100 370 R 50 50 1 2 I I
X ~ 2 -600 -100 370 R 50 50 1 2 I I
X ~ 3 600 0 300 L 50 50 1 2 C
X ~ 4 -600 100 370 R 50 50 2 2 I I
X ~ 5 -600 -100 370 R 50 50 2 2 I I
X ~ 6 600 0 300 L 50 50 2 2 C
X ~ 8 600 0 300 L 50 50 3 2 C
X ~ 9 -600 100 370 R 50 50 3 2 I I
X ~ 10 -600 -100 370 R 50 50 3 2 I I
X ~ 11 600 0 300 L 50 50 4 2 C
X ~ 12 -600 100 370 R 50 50 4 2 I I
X ~ 13 -600 -100 370 R 50 50 4 2 I I
ENDDRAW
ENDDEF
#
# C
#
DEF C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
C?
C_????_*
C_????
SMD*_c
Capacitor*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CONN_01X04
#
DEF CONN_01X04 P 0 40 Y N 1 F N
F0 "P" 0 250 50 H V C CNN
F1 "CONN_01X04" 100 0 50 V V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
Pin_Header_Straight_1X04
Pin_Header_Angled_1X04
Socket_Strip_Straight_1X04
Socket_Strip_Angled_1X04
$ENDFPLIST
DRAW
S -50 -145 10 -155 0 1 0 N
S -50 -45 10 -55 0 1 0 N
S -50 55 10 45 0 1 0 N
S -50 155 10 145 0 1 0 N
S -50 200 50 -200 0 1 0 N
X P1 1 -200 150 150 R 50 50 1 1 P
X P2 2 -200 50 150 R 50 50 1 1 P
X P3 3 -200 -50 150 R 50 50 1 1 P
X P4 4 -200 -150 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X03
#
DEF CONN_02X03 P 0 1 Y N 1 F N
F0 "P" 0 200 50 H V C CNN
F1 "CONN_02X03" 0 -200 50 H V C CNN
F2 "" 0 -1200 50 H V C CNN
F3 "" 0 -1200 50 H V C CNN
$FPLIST
Pin_Header_Straight_2X03
Pin_Header_Angled_2X03
Socket_Strip_Straight_2X03
Socket_Strip_Angled_2X03
$ENDFPLIST
DRAW
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 150 100 -150 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
X P1 1 -250 100 150 R 50 50 1 1 P
X P2 2 250 100 150 L 50 50 1 1 P
X P3 3 -250 0 150 R 50 50 1 1 P
X P4 4 250 0 150 L 50 50 1 1 P
X P5 5 -250 -100 150 R 50 50 1 1 P
X P6 6 250 -100 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X07
#
DEF CONN_02X07 P 0 1 Y N 1 F N
F0 "P" 0 400 50 H V C CNN
F1 "CONN_02X07" 0 0 50 V V C CNN
F2 "" 0 -1200 50 H V C CNN
F3 "" 0 -1200 50 H V C CNN
$FPLIST
Pin_Header_Straight_2X07
Pin_Header_Angled_2X07
Socket_Strip_Straight_2X07
Socket_Strip_Angled_2X07
$ENDFPLIST
DRAW
S -100 -295 -50 -305 0 1 0 N
S -100 -195 -50 -205 0 1 0 N
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 205 -50 195 0 1 0 N
S -100 305 -50 295 0 1 0 N
S -100 350 100 -350 0 1 0 N
S 50 -295 100 -305 0 1 0 N
S 50 -195 100 -205 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
S 50 205 100 195 0 1 0 N
S 50 305 100 295 0 1 0 N
X P1 1 -250 300 150 R 50 50 1 1 P
X P2 2 250 300 150 L 50 50 1 1 P
X P3 3 -250 200 150 R 50 50 1 1 P
X P4 4 250 200 150 L 50 50 1 1 P
X P5 5 -250 100 150 R 50 50 1 1 P
X P6 6 250 100 150 L 50 50 1 1 P
X P7 7 -250 0 150 R 50 50 1 1 P
X P8 8 250 0 150 L 50 50 1 1 P
X P9 9 -250 -100 150 R 50 50 1 1 P
X P10 10 250 -100 150 L 50 50 1 1 P
X P11 11 -250 -200 150 R 50 50 1 1 P
X P12 12 250 -200 150 L 50 50 1 1 P
X P13 13 -250 -300 150 R 50 50 1 1 P
X P14 14 250 -300 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X17
#
DEF CONN_02X17 P 0 1 Y N 1 F N
F0 "P" 0 900 50 H V C CNN
F1 "CONN_02X17" 0 0 50 V V C CNN
F2 "" 0 -1100 50 H V C CNN
F3 "" 0 -1100 50 H V C CNN
$FPLIST
Pin_Header_Straight_2X17
Pin_Header_Angled_2X17
Socket_Strip_Straight_2X17
Socket_Strip_Angled_2X17
$ENDFPLIST
DRAW
S -100 -795 -50 -805 0 1 0 N
S -100 -695 -50 -705 0 1 0 N
S -100 -595 -50 -605 0 1 0 N
S -100 -495 -50 -505 0 1 0 N
S -100 -395 -50 -405 0 1 0 N
S -100 -295 -50 -305 0 1 0 N
S -100 -195 -50 -205 0 1 0 N
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 205 -50 195 0 1 0 N
S -100 305 -50 295 0 1 0 N
S -100 405 -50 395 0 1 0 N
S -100 505 -50 495 0 1 0 N
S -100 605 -50 595 0 1 0 N
S -100 705 -50 695 0 1 0 N
S -100 805 -50 795 0 1 0 N
S -100 850 100 -850 0 1 0 N
S 50 -795 100 -805 0 1 0 N
S 50 -695 100 -705 0 1 0 N
S 50 -595 100 -605 0 1 0 N
S 50 -495 100 -505 0 1 0 N
S 50 -395 100 -405 0 1 0 N
S 50 -295 100 -305 0 1 0 N
S 50 -195 100 -205 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
S 50 205 100 195 0 1 0 N
S 50 305 100 295 0 1 0 N
S 50 405 100 395 0 1 0 N
S 50 505 100 495 0 1 0 N
S 50 605 100 595 0 1 0 N
S 50 705 100 695 0 1 0 N
S 50 805 100 795 0 1 0 N
X P1 1 -250 800 150 R 50 50 1 1 P
X P2 2 250 800 150 L 50 50 1 1 P
X P3 3 -250 700 150 R 50 50 1 1 P
X P4 4 250 700 150 L 50 50 1 1 P
X P5 5 -250 600 150 R 50 50 1 1 P
X P6 6 250 600 150 L 50 50 1 1 P
X P7 7 -250 500 150 R 50 50 1 1 P
X P8 8 250 500 150 L 50 50 1 1 P
X P9 9 -250 400 150 R 50 50 1 1 P
X P10 10 250 400 150 L 50 50 1 1 P
X P20 20 250 -100 150 L 50 50 1 1 P
X P30 30 250 -600 150 L 50 50 1 1 P
X P11 11 -250 300 150 R 50 50 1 1 P
X P21 21 -250 -200 150 R 50 50 1 1 P
X P31 31 -250 -700 150 R 50 50 1 1 P
X P12 12 250 300 150 L 50 50 1 1 P
X P22 22 250 -200 150 L 50 50 1 1 P
X P32 32 250 -700 150 L 50 50 1 1 P
X P13 13 -250 200 150 R 50 50 1 1 P
X P23 23 -250 -300 150 R 50 50 1 1 P
X P33 33 -250 -800 150 R 50 50 1 1 P
X P14 14 250 200 150 L 50 50 1 1 P
X P24 24 250 -300 150 L 50 50 1 1 P
X P34 34 250 -800 150 L 50 50 1 1 P
X P15 15 -250 100 150 R 50 50 1 1 P
X P25 25 -250 -400 150 R 50 50 1 1 P
X P16 16 250 100 150 L 50 50 1 1 P
X P26 26 250 -400 150 L 50 50 1 1 P
X P17 17 -250 0 150 R 50 50 1 1 P
X P27 27 -250 -500 150 R 50 50 1 1 P
X P18 18 250 0 150 L 50 50 1 1 P
X P28 28 250 -500 150 L 50 50 1 1 P
X P19 19 -250 -100 150 R 50 50 1 1 P
X P29 29 -250 -600 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CP
#
DEF CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "CP" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
CP*
Elko*
TantalC*
C*elec
c_elec*
SMD*_Pol
$ENDFPLIST
DRAW
S -90 20 -90 40 0 1 0 N
S -90 20 90 20 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
S 90 40 -90 40 0 1 0 N
S 90 40 90 20 0 1 0 N
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# D
#
DEF D D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "D" 0 -100 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
Diode_*
D-Pak_TO252AA
*SingleDiode
*_Diode_*
*SingleDiode*
$ENDFPLIST
DRAW
P 2 0 1 6 -50 50 -50 -50 N
P 3 0 1 0 50 50 -50 0 50 -50 F
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# F_Small
#
DEF F_Small F 0 10 N N 1 F N
F0 "F" -40 60 50 H V L CNN
F1 "F_Small" -120 -60 50 H V L CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
CP*
SM*
$ENDFPLIST
DRAW
S -50 20 50 -20 0 1 0 N
P 2 0 1 0 -50 0 50 0 N
X ~ 1 -100 0 50 R 40 40 1 1 P
X ~ 2 100 0 50 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# GND
#
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# HDR_3X5
#
DEF HDR_3X5 P 0 40 Y Y 1 F N
F0 "P" 0 0 60 H V C CNN
F1 "HDR_3X5" 0 -400 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 -100 300 -700 0 1 0 N
X ~ 1 -500 -200 200 R 50 50 1 1 I
X ~ 2 -500 -300 200 R 50 50 1 1 I
X ~ 3 -500 -400 200 R 50 50 1 1 I
X ~ 4 -500 -500 200 R 50 50 1 1 I
X ~ 5 -500 -600 200 R 50 50 1 1 I
X ~ 6 500 -600 200 L 50 50 1 1 I
X ~ 7 500 -500 200 L 50 50 1 1 I
X ~ 8 500 -400 200 L 50 50 1 1 I
X ~ 9 500 -300 200 L 50 50 1 1 I
X ~ 10 500 -200 200 L 50 50 1 1 I
X ~ 11 -200 -900 200 U 50 50 1 1 I
X ~ 12 -100 -900 200 U 50 50 1 1 I
X ~ 13 0 -900 200 U 50 50 1 1 I
X ~ 14 100 -900 200 U 50 50 1 1 I
X ~ 15 200 -900 200 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# MAPLE_MINI
#
DEF MAPLE_MINI U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "MAPLE_MINI" 0 -2250 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -550 -50 550 -2150 0 1 0 N
X VIn 1 -750 -150 200 R 50 50 1 1 P
X D0/PB11 2 -750 -250 200 R 50 50 1 1 P
X D1/PB10 3 -750 -350 200 R 50 50 1 1 P
X D2/PB2/BT1 4 -750 -450 200 R 50 50 1 1 P
X D3/PB0 5 -750 -550 200 R 50 50 1 1 P
X D4/PA7 6 -750 -650 200 R 50 50 1 1 P
X D5/PA6 7 -750 -750 200 R 50 50 1 1 P
X D6/PA5 8 -750 -850 200 R 50 50 1 1 P
X D7/PA4 9 -750 -950 200 R 50 50 1 1 P
X D8/PA3 10 -750 -1050 200 R 50 50 1 1 P
X 3V3 20 -750 -2050 200 R 50 50 1 1 P
X D21/PA14 30 750 -1150 200 L 50 50 1 1 P
X D31/PB12 40 750 -150 200 L 50 50 1 1 P
X D9/PA2 11 -750 -1150 200 R 50 50 1 1 P
X 3V3 21 750 -2050 200 L 50 50 1 1 P
X D22/PA13 31 750 -1050 200 L 50 50 1 1 P
X D10/PA1 12 -750 -1250 200 R 50 50 1 1 P
X GND 22 750 -1950 200 L 50 50 1 1 P
X D23/PA12 32 750 -950 200 L 50 50 1 1 P
X D11/PA0 13 -750 -1350 200 R 50 50 1 1 P
X D32/PB8/Btn 23 750 -1850 200 L 50 50 1 1 P
X D24/PA11 33 750 -850 200 L 50 50 1 1 P
X RESET 14 -750 -1450 200 R 50 50 1 1 P
X D15/PB7 24 750 -1750 200 L 50 50 1 1 P
X D25/PA10 34 750 -750 200 L 50 50 1 1 P
X D12/PC15 15 -750 -1550 200 R 50 50 1 1 P
X D16/PB6 25 750 -1650 200 L 50 50 1 1 P
X D26/PA9 35 750 -650 200 L 50 50 1 1 P
X D13/PC14 16 -750 -1650 200 R 50 50 1 1 P
X D17/PB5 26 750 -1550 200 L 50 50 1 1 P
X D27/PA8 36 750 -550 200 L 50 50 1 1 P
X D14/PC13 17 -750 -1750 200 R 50 50 1 1 P
X D18/PB4 27 750 -1450 200 L 50 50 1 1 P
X D28/PB15 37 750 -450 200 L 50 50 1 1 P
X VBat 18 -750 -1850 200 R 50 50 1 1 P
X D19/PB3 28 750 -1350 200 L 50 50 1 1 P
X D29/PB14 38 750 -350 200 L 50 50 1 1 P
X GND 19 -750 -1950 200 R 50 50 1 1 P
X D20/PA15 29 750 -1250 200 L 50 50 1 1 P
X D30/PB13 39 750 -250 200 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# MMBT3904
#
DEF MMBT3904 Q 0 0 Y Y 1 F N
F0 "Q" 200 75 50 H V L CNN
F1 "MMBT3904" 200 0 50 H V L CNN
F2 "SOT-23" 200 -75 50 H V L CIN
F3 "" 0 0 50 H V L CNN
$FPLIST
SOT-23*
$ENDFPLIST
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 25 0 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
X B 1 -200 0 200 R 50 50 1 1 I
X E 2 100 -200 100 U 50 50 1 1 P
X C 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# MMBT3906
#
DEF MMBT3906 Q 0 0 Y Y 1 F N
F0 "Q" 200 75 50 H V L CNN
F1 "MMBT3906" 200 0 50 H V L CNN
F2 "SOT-23" 200 -75 50 H V L CIN
F3 "" 0 0 50 H V L CNN
$FPLIST
SOT-23*
$ENDFPLIST
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 25 0 N
P 2 0 1 0 100 -100 25 -25 N
P 2 0 1 0 100 100 25 25 N
P 3 0 1 20 25 75 25 -75 25 -75 F
P 5 0 1 0 55 -75 75 -55 35 -35 55 -75 55 -75 F
X B 1 -200 0 200 R 50 50 1 1 I
X E 2 100 -200 100 U 50 50 1 1 P
X C 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# PWR_FLAG
#
DEF PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 95 50 H I C CNN
F1 "PWR_FLAG" 0 180 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
X pwr 1 0 0 0 U 50 50 0 0 w
P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
ENDDRAW
ENDDEF
#
# R
#
DEF R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "R" 0 0 50 V V C CNN
F2 "" -70 0 50 V V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
R_*
Resistor_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# VCC
#
DEF VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VCC" 0 150 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
C 0 75 25 0 1 0 N
P 2 0 1 0 0 0 0 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# ZENER
#
DEF ZENER D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "ZENER" 0 -100 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
D?
SO*
SM*
$ENDFPLIST
DRAW
P 5 0 1 8 -70 50 -50 30 -50 -30 -30 -50 -30 -50 N
P 5 0 1 0 -50 0 50 50 50 -50 -50 0 -50 0 F
X K 1 -200 0 150 R 50 50 1 1 P
X A 2 200 0 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

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71
pcb/MM/160/FF-MM160.pro Normal file
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update=Fri 03 Jul 2015 05:29:28 BST
version=1
last_client=kicad
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[general]
version=1
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60
[eeschema]
version=1
LibDir=../..
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=microcontrollers
LibName13=dsp
LibName14=microchip
LibName15=analog_switches
LibName16=motorola
LibName17=texas
LibName18=intel
LibName19=audio
LibName20=interface
LibName21=digital-audio
LibName22=philips
LibName23=display
LibName24=cypress
LibName25=siliconi
LibName26=opto
LibName27=atmel
LibName28=contrib
LibName29=valves
LibName30=FF

1477
pcb/MM/160/FF-MM160.sch Normal file

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34
pcb/MM/160/README Normal file
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This project was designed using a development snapshot of KiCad.
FF-MM160
--------
KiCad project for schematic and 10cmx5cm single-board layout.
Can be opened in the KiCad project manager.
FF-MM160-bom.txt
----------------
Bill of materials for the above design, excluding pin headers
and socket strips.
FF-MM160-panel
--------------
Two-up 10x10cm panelisation of the above layout, with cutouts
and break-away mousebites. Should be opened directly in Pcbnew.
Generating Gerbers
------------------
Nothing special to note here. Some of these options are important to
follow, especially for the drill file.
Options:
Plot footprint values
Plot footprint references
Exclude PCB edge layer from other layers
Gerber Options:
Use Protel filename extensions
Format: 4.6
Drill files:
Drill Units: Inches
Zeros Format: Suppress leading zeros
Precision: 2:4
Drill Options: Minimal header
Drill Origin: Absolute

3
pcb/MM/160/fp-lib-table Normal file
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(fp_lib_table
(lib (name FF)(type KiCad)(uri "$(KIPRJMOD)/FF.pretty")(options "")(descr ""))
)

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REF PART DESCRIPTION RS ORDER
=== ================ ========
F1 Bourns MF-PSMF075X-2 (0805) 691-7516
D1 LL4148 (MiniMELF, SOD-80)
D2 NXP PTVS5V0P1UP (SOD-128) 791-9052
NXP PTVS5V0P1UTP (alternative) 791-9055
C1-C2 0.1uF (0805) 390-990
C3 Vishay 293D106X9020B2TE3 (3528) 684-3904
Q1 MMBT3904 (SOT23)
Q2 MMBT3906 (SOT23)
U1 "Taobao" Mini STM32 (DIP40) [*]
U2-U3 74LS38 (SOIC14)
R1 33R,1%,1/4W (1206)
R3-R14 1K,5%,1/8W (0805)
P5 TE/AMP 171826-4 4-pin header 680-1225
[*] There are many variants of this Chinese design with informal names
such as Red Pill, Blue Pill, JC-66, etc. Most have a pullup
resistor on PA12: remove it or cut the connecting trace.
For example on Blue Pill both R10 and R11 can be removed:
http://wiki.stm32duino.com/images/c/c1/Vcc-gnd.com-STM32F103C8-schematic.pdf

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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# +5V
#
DEF +5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# 74LS26
#
DEF 74LS26 U 0 30 Y Y 4 F N
F0 "U" 0 50 50 H V C CNN
F1 "74LS26" 0 -50 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
ALIAS 74LS38
DRAW
X GND 7 -200 -200 0 U 40 40 0 0 W N
X VCC 14 -200 200 0 U 40 40 0 0 W N
A 100 0 200 896 -896 0 1 0 N 101 200 101 -199
P 4 0 1 0 100 200 -300 200 -300 -200 100 -200 N
X ~ 1 -600 100 300 R 50 50 1 1 I
X ~ 2 -600 -100 300 R 50 50 1 1 I
X ~ 3 600 0 300 L 50 50 1 1 C I
X ~ 4 -600 100 300 R 50 50 2 1 I
X ~ 5 -600 -100 300 R 50 50 2 1 I
X ~ 6 600 0 300 L 50 50 2 1 C I
X ~ 8 600 0 300 L 50 50 3 1 C I
X ~ 9 -600 100 300 R 50 50 3 1 I
X ~ 10 -600 -100 300 R 50 50 3 1 I
X ~ 11 600 0 300 L 50 50 4 1 C I
X ~ 12 -600 100 300 R 50 50 4 1 I
X ~ 13 -600 -100 300 R 50 50 4 1 I
A -470 0 262 495 -495 0 2 0 N -300 199 -300 -198
A -2 126 326 -897 -225 0 2 0 N 0 -199 299 2
A 4 -120 320 906 221 0 2 0 N 2 200 300 0
P 2 0 2 0 -300 -200 0 -200 N
P 2 0 2 0 -300 200 0 200 N
X ~ 1 -600 100 370 R 50 50 1 2 I I
X ~ 2 -600 -100 370 R 50 50 1 2 I I
X ~ 3 600 0 300 L 50 50 1 2 C
X ~ 4 -600 100 370 R 50 50 2 2 I I
X ~ 5 -600 -100 370 R 50 50 2 2 I I
X ~ 6 600 0 300 L 50 50 2 2 C
X ~ 8 600 0 300 L 50 50 3 2 C
X ~ 9 -600 100 370 R 50 50 3 2 I I
X ~ 10 -600 -100 370 R 50 50 3 2 I I
X ~ 11 600 0 300 L 50 50 4 2 C
X ~ 12 -600 100 370 R 50 50 4 2 I I
X ~ 13 -600 -100 370 R 50 50 4 2 I I
ENDDRAW
ENDDEF
#
# C
#
DEF C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
C?
C_????_*
C_????
SMD*_c
Capacitor*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CONN_01X04
#
DEF CONN_01X04 P 0 40 Y N 1 F N
F0 "P" 0 250 50 H V C CNN
F1 "CONN_01X04" 100 0 50 V V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
Pin_Header_Straight_1X04
Pin_Header_Angled_1X04
Socket_Strip_Straight_1X04
Socket_Strip_Angled_1X04
$ENDFPLIST
DRAW
S -50 -145 10 -155 0 1 0 N
S -50 -45 10 -55 0 1 0 N
S -50 55 10 45 0 1 0 N
S -50 155 10 145 0 1 0 N
S -50 200 50 -200 0 1 0 N
X P1 1 -200 150 150 R 50 50 1 1 P
X P2 2 -200 50 150 R 50 50 1 1 P
X P3 3 -200 -50 150 R 50 50 1 1 P
X P4 4 -200 -150 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X02
#
DEF CONN_02X02 P 0 1 Y N 1 F N
F0 "P" 0 150 50 H V C CNN
F1 "CONN_02X02" 0 -150 50 H V C CNN
F2 "" 0 -1200 50 H V C CNN
F3 "" 0 -1200 50 H V C CNN
$FPLIST
Pin_Header_Straight_2X02
Pin_Header_Angled_2X02
Socket_Strip_Straight_2X02
Socket_Strip_Angled_2X02
$ENDFPLIST
DRAW
S -100 -45 -50 -55 0 1 0 N
S -100 55 -50 45 0 1 0 N
S -100 100 100 -100 0 1 0 N
S 50 -45 100 -55 0 1 0 N
S 50 55 100 45 0 1 0 N
X P1 1 -250 50 150 R 50 50 1 1 P
X P2 2 250 50 150 L 50 50 1 1 P
X P3 3 -250 -50 150 R 50 50 1 1 P
X P4 4 250 -50 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X03
#
DEF CONN_02X03 P 0 1 Y N 1 F N
F0 "P" 0 200 50 H V C CNN
F1 "CONN_02X03" 0 -200 50 H V C CNN
F2 "" 0 -1200 50 H V C CNN
F3 "" 0 -1200 50 H V C CNN
$FPLIST
Pin_Header_Straight_2X03
Pin_Header_Angled_2X03
Socket_Strip_Straight_2X03
Socket_Strip_Angled_2X03
$ENDFPLIST
DRAW
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 150 100 -150 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
X P1 1 -250 100 150 R 50 50 1 1 P
X P2 2 250 100 150 L 50 50 1 1 P
X P3 3 -250 0 150 R 50 50 1 1 P
X P4 4 250 0 150 L 50 50 1 1 P
X P5 5 -250 -100 150 R 50 50 1 1 P
X P6 6 250 -100 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X07
#
DEF CONN_02X07 P 0 1 Y N 1 F N
F0 "P" 0 400 50 H V C CNN
F1 "CONN_02X07" 0 0 50 V V C CNN
F2 "" 0 -1200 50 H V C CNN
F3 "" 0 -1200 50 H V C CNN
$FPLIST
Pin_Header_Straight_2X07
Pin_Header_Angled_2X07
Socket_Strip_Straight_2X07
Socket_Strip_Angled_2X07
$ENDFPLIST
DRAW
S -100 -295 -50 -305 0 1 0 N
S -100 -195 -50 -205 0 1 0 N
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 205 -50 195 0 1 0 N
S -100 305 -50 295 0 1 0 N
S -100 350 100 -350 0 1 0 N
S 50 -295 100 -305 0 1 0 N
S 50 -195 100 -205 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
S 50 205 100 195 0 1 0 N
S 50 305 100 295 0 1 0 N
X P1 1 -250 300 150 R 50 50 1 1 P
X P2 2 250 300 150 L 50 50 1 1 P
X P3 3 -250 200 150 R 50 50 1 1 P
X P4 4 250 200 150 L 50 50 1 1 P
X P5 5 -250 100 150 R 50 50 1 1 P
X P6 6 250 100 150 L 50 50 1 1 P
X P7 7 -250 0 150 R 50 50 1 1 P
X P8 8 250 0 150 L 50 50 1 1 P
X P9 9 -250 -100 150 R 50 50 1 1 P
X P10 10 250 -100 150 L 50 50 1 1 P
X P11 11 -250 -200 150 R 50 50 1 1 P
X P12 12 250 -200 150 L 50 50 1 1 P
X P13 13 -250 -300 150 R 50 50 1 1 P
X P14 14 250 -300 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X17
#
DEF CONN_02X17 P 0 1 Y N 1 F N
F0 "P" 0 900 50 H V C CNN
F1 "CONN_02X17" 0 0 50 V V C CNN
F2 "" 0 -1100 50 H V C CNN
F3 "" 0 -1100 50 H V C CNN
$FPLIST
Pin_Header_Straight_2X17
Pin_Header_Angled_2X17
Socket_Strip_Straight_2X17
Socket_Strip_Angled_2X17
$ENDFPLIST
DRAW
S -100 -795 -50 -805 0 1 0 N
S -100 -695 -50 -705 0 1 0 N
S -100 -595 -50 -605 0 1 0 N
S -100 -495 -50 -505 0 1 0 N
S -100 -395 -50 -405 0 1 0 N
S -100 -295 -50 -305 0 1 0 N
S -100 -195 -50 -205 0 1 0 N
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 205 -50 195 0 1 0 N
S -100 305 -50 295 0 1 0 N
S -100 405 -50 395 0 1 0 N
S -100 505 -50 495 0 1 0 N
S -100 605 -50 595 0 1 0 N
S -100 705 -50 695 0 1 0 N
S -100 805 -50 795 0 1 0 N
S -100 850 100 -850 0 1 0 N
S 50 -795 100 -805 0 1 0 N
S 50 -695 100 -705 0 1 0 N
S 50 -595 100 -605 0 1 0 N
S 50 -495 100 -505 0 1 0 N
S 50 -395 100 -405 0 1 0 N
S 50 -295 100 -305 0 1 0 N
S 50 -195 100 -205 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
S 50 205 100 195 0 1 0 N
S 50 305 100 295 0 1 0 N
S 50 405 100 395 0 1 0 N
S 50 505 100 495 0 1 0 N
S 50 605 100 595 0 1 0 N
S 50 705 100 695 0 1 0 N
S 50 805 100 795 0 1 0 N
X P1 1 -250 800 150 R 50 50 1 1 P
X P2 2 250 800 150 L 50 50 1 1 P
X P3 3 -250 700 150 R 50 50 1 1 P
X P4 4 250 700 150 L 50 50 1 1 P
X P5 5 -250 600 150 R 50 50 1 1 P
X P6 6 250 600 150 L 50 50 1 1 P
X P7 7 -250 500 150 R 50 50 1 1 P
X P8 8 250 500 150 L 50 50 1 1 P
X P9 9 -250 400 150 R 50 50 1 1 P
X P10 10 250 400 150 L 50 50 1 1 P
X P20 20 250 -100 150 L 50 50 1 1 P
X P30 30 250 -600 150 L 50 50 1 1 P
X P11 11 -250 300 150 R 50 50 1 1 P
X P21 21 -250 -200 150 R 50 50 1 1 P
X P31 31 -250 -700 150 R 50 50 1 1 P
X P12 12 250 300 150 L 50 50 1 1 P
X P22 22 250 -200 150 L 50 50 1 1 P
X P32 32 250 -700 150 L 50 50 1 1 P
X P13 13 -250 200 150 R 50 50 1 1 P
X P23 23 -250 -300 150 R 50 50 1 1 P
X P33 33 -250 -800 150 R 50 50 1 1 P
X P14 14 250 200 150 L 50 50 1 1 P
X P24 24 250 -300 150 L 50 50 1 1 P
X P34 34 250 -800 150 L 50 50 1 1 P
X P15 15 -250 100 150 R 50 50 1 1 P
X P25 25 -250 -400 150 R 50 50 1 1 P
X P16 16 250 100 150 L 50 50 1 1 P
X P26 26 250 -400 150 L 50 50 1 1 P
X P17 17 -250 0 150 R 50 50 1 1 P
X P27 27 -250 -500 150 R 50 50 1 1 P
X P18 18 250 0 150 L 50 50 1 1 P
X P28 28 250 -500 150 L 50 50 1 1 P
X P19 19 -250 -100 150 R 50 50 1 1 P
X P29 29 -250 -600 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CP
#
DEF CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "CP" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
CP*
Elko*
TantalC*
C*elec
c_elec*
SMD*_Pol
$ENDFPLIST
DRAW
S -90 20 -90 40 0 1 0 N
S -90 20 90 20 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
S 90 40 -90 40 0 1 0 N
S 90 40 90 20 0 1 0 N
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# D
#
DEF D D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "D" 0 -100 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
Diode_*
D-Pak_TO252AA
*SingleDiode
*_Diode_*
*SingleDiode*
$ENDFPLIST
DRAW
P 2 0 1 6 -50 50 -50 -50 N
P 3 0 1 0 50 50 -50 0 50 -50 F
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# F_Small
#
DEF F_Small F 0 10 N N 1 F N
F0 "F" -40 60 50 H V L CNN
F1 "F_Small" -120 -60 50 H V L CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
CP*
SM*
$ENDFPLIST
DRAW
S -50 20 50 -20 0 1 0 N
P 2 0 1 0 -50 0 50 0 N
X ~ 1 -100 0 50 R 40 40 1 1 P
X ~ 2 100 0 50 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# GND
#
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# HDR_3X5
#
DEF HDR_3X5 P 0 40 Y Y 1 F N
F0 "P" 0 0 60 H V C CNN
F1 "HDR_3X5" 0 -400 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 -100 300 -700 0 1 0 N
X ~ 1 -500 -200 200 R 50 50 1 1 I
X ~ 2 -500 -300 200 R 50 50 1 1 I
X ~ 3 -500 -400 200 R 50 50 1 1 I
X ~ 4 -500 -500 200 R 50 50 1 1 I
X ~ 5 -500 -600 200 R 50 50 1 1 I
X ~ 6 500 -600 200 L 50 50 1 1 I
X ~ 7 500 -500 200 L 50 50 1 1 I
X ~ 8 500 -400 200 L 50 50 1 1 I
X ~ 9 500 -300 200 L 50 50 1 1 I
X ~ 10 500 -200 200 L 50 50 1 1 I
X ~ 11 -200 -900 200 U 50 50 1 1 I
X ~ 12 -100 -900 200 U 50 50 1 1 I
X ~ 13 0 -900 200 U 50 50 1 1 I
X ~ 14 100 -900 200 U 50 50 1 1 I
X ~ 15 200 -900 200 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# MMBT3904
#
DEF MMBT3904 Q 0 0 Y Y 1 F N
F0 "Q" 200 75 50 H V L CNN
F1 "MMBT3904" 200 0 50 H V L CNN
F2 "SOT-23" 200 -75 50 H V L CIN
F3 "" 0 0 50 H V L CNN
$FPLIST
SOT-23*
$ENDFPLIST
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 25 0 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
X B 1 -200 0 200 R 50 50 1 1 I
X E 2 100 -200 100 U 50 50 1 1 P
X C 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# MMBT3906
#
DEF MMBT3906 Q 0 0 Y Y 1 F N
F0 "Q" 200 75 50 H V L CNN
F1 "MMBT3906" 200 0 50 H V L CNN
F2 "SOT-23" 200 -75 50 H V L CIN
F3 "" 0 0 50 H V L CNN
$FPLIST
SOT-23*
$ENDFPLIST
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 25 0 N
P 2 0 1 0 100 -100 25 -25 N
P 2 0 1 0 100 100 25 25 N
P 3 0 1 20 25 75 25 -75 25 -75 F
P 5 0 1 0 55 -75 75 -55 35 -35 55 -75 55 -75 F
X B 1 -200 0 200 R 50 50 1 1 I
X E 2 100 -200 100 U 50 50 1 1 P
X C 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# PWR_FLAG
#
DEF PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 95 50 H I C CNN
F1 "PWR_FLAG" 0 180 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
X pwr 1 0 0 0 U 50 50 0 0 w
P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
ENDDRAW
ENDDEF
#
# R
#
DEF R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "R" 0 0 50 V V C CNN
F2 "" -70 0 50 V V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
R_*
Resistor_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# TAOBAO
#
DEF TAOBAO U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "TAOBAO" 0 -2250 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -550 -50 550 -2150 0 1 0 N
X PB12 1 -750 -150 200 R 50 50 1 1 P
X PB13 2 -750 -250 200 R 50 50 1 1 P
X PB14 3 -750 -350 200 R 50 50 1 1 P
X PB15 4 -750 -450 200 R 50 50 1 1 P
X PA8 5 -750 -550 200 R 50 50 1 1 P
X PA9 6 -750 -650 200 R 50 50 1 1 P
X PA10 7 -750 -750 200 R 50 50 1 1 P
X PA11 8 -750 -850 200 R 50 50 1 1 P
X PA12 9 -750 -950 200 R 50 50 1 1 P
X PA15 10 -750 -1050 200 R 50 50 1 1 P
X 3V3 20 -750 -2050 200 R 50 50 1 1 P
X PA5 30 750 -1150 200 L 50 50 1 1 P
X GND 40 750 -150 200 L 50 50 1 1 P
X PB3 11 -750 -1150 200 R 50 50 1 1 P
X VBat 21 750 -2050 200 L 50 50 1 1 P
X PA6 31 750 -1050 200 L 50 50 1 1 P
X PB4 12 -750 -1250 200 R 50 50 1 1 P
X PC13 22 750 -1950 200 L 50 50 1 1 P
X PA7 32 750 -950 200 L 50 50 1 1 P
X PB5 13 -750 -1350 200 R 50 50 1 1 P
X PC14 23 750 -1850 200 L 50 50 1 1 P
X PB0 33 750 -850 200 L 50 50 1 1 P
X PB6 14 -750 -1450 200 R 50 50 1 1 P
X PC15 24 750 -1750 200 L 50 50 1 1 P
X PB1 34 750 -750 200 L 50 50 1 1 P
X PB7 15 -750 -1550 200 R 50 50 1 1 P
X PA0 25 750 -1650 200 L 50 50 1 1 P
X PB10 35 750 -650 200 L 50 50 1 1 P
X PB8 16 -750 -1650 200 R 50 50 1 1 P
X PA1 26 750 -1550 200 L 50 50 1 1 P
X PB11 36 750 -550 200 L 50 50 1 1 P
X PB9 17 -750 -1750 200 R 50 50 1 1 P
X PA2 27 750 -1450 200 L 50 50 1 1 P
X RST 37 750 -450 200 L 50 50 1 1 P
X VIn 18 -750 -1850 200 R 50 50 1 1 P
X PA3 28 750 -1350 200 L 50 50 1 1 P
X 3V3 38 750 -350 200 L 50 50 1 1 P
X GND 19 -750 -1950 200 R 50 50 1 1 P
X PA4 29 750 -1250 200 L 50 50 1 1 P
X GND 39 750 -250 200 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# VCC
#
DEF VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VCC" 0 150 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
C 0 75 25 0 1 0 N
P 2 0 1 0 0 0 0 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# ZENER
#
DEF ZENER D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "ZENER" 0 -100 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
D?
SO*
SM*
$ENDFPLIST
DRAW
P 5 0 1 8 -70 50 -50 30 -50 -30 -30 -50 -30 -50 N
P 5 0 1 0 -50 0 50 50 50 -50 -50 0 -50 0 F
X K 1 -200 0 150 R 50 50 1 1 P
X A 2 200 0 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

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@ -0,0 +1,62 @@
update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=microcontrollers
LibName13=dsp
LibName14=microchip
LibName15=analog_switches
LibName16=motorola
LibName17=texas
LibName18=intel
LibName19=audio
LibName20=interface
LibName21=digital-audio
LibName22=philips
LibName23=display
LibName24=cypress
LibName25=siliconi
LibName26=opto
LibName27=atmel
LibName28=contrib
LibName29=valves

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71
pcb/TB/160/FF-TB160.pro Normal file
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update=Fri 03 Jul 2015 05:29:28 BST
version=1
last_client=kicad
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[general]
version=1
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60
[eeschema]
version=1
LibDir=../..
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=microcontrollers
LibName13=dsp
LibName14=microchip
LibName15=analog_switches
LibName16=motorola
LibName17=texas
LibName18=intel
LibName19=audio
LibName20=interface
LibName21=digital-audio
LibName22=philips
LibName23=display
LibName24=cypress
LibName25=siliconi
LibName26=opto
LibName27=atmel
LibName28=contrib
LibName29=valves
LibName30=FF

1403
pcb/TB/160/FF-TB160.sch Normal file

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34
pcb/TB/160/README Normal file
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This project was designed using a development snapshot of KiCad.
FF-TB160
--------
KiCad project for schematic and 10cmx5cm single-board layout.
Can be opened in the KiCad project manager.
FF-TB160-bom.txt
----------------
Bill of materials for the above design, excluding pin headers
and socket strips.
FF-TB160-panel
--------------
Two-up 10x10cm panelisation of the above layout, with cutouts
and break-away mousebites. Should be opened directly in Pcbnew.
Generating Gerbers
------------------
Nothing special to note here. Some of these options are important to
follow, especially for the drill file.
Options:
Plot footprint values
Plot footprint references
Exclude PCB edge layer from other layers
Gerber Options:
Use Protel filename extensions
Format: 4.6
Drill files:
Drill Units: Inches
Zeros Format: Suppress leading zeros
Precision: 2:4
Drill Options: Minimal header
Drill Origin: Absolute

3
pcb/TB/160/fp-lib-table Normal file
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(fp_lib_table
(lib (name FF)(type KiCad)(uri "$(KIPRJMOD)/FF.pretty")(options "")(descr ""))
)

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@ -0,0 +1,23 @@
REF PART DESCRIPTION RS ORDER
=== ================ ========
F1 Bourns MF-PSMF075X-2 (0805) 691-7516
D1 LL4148 (MiniMELF, SOD-80)
D2 NXP PTVS5V0P1UP (SOD-128) 791-9052
NXP PTVS5V0P1UTP (alternative) 791-9055
C1-C2 0.1uF (0805) 390-990
C3 Vishay 293D106X9020B2TE3 (3528) 684-3904
Q1 MMBT3904 (SOT23)
Q2 MMBT3906 (SOT23)
U1 "Taobao" Mini STM32 (DIP40) [*]
U2-U3 74LS38 (SOIC14)
R1 33R,1%,1/4W (1206)
R2 4K7,5%,1/8W (0805)
R3-R14 1K,5%,1/8W (0805)
P5 TE/AMP 171826-4 4-pin header 680-1225
[*] There are many variants of this Chinese design with informal names
such as Red Pill, Blue Pill, JC-66, etc. Most have a pullup
resistor on PA12: remove it or cut the connecting trace.
For example on Blue Pill both R10 and R11 can be removed:
http://wiki.stm32duino.com/images/c/c1/Vcc-gnd.com-STM32F103C8-schematic.pdf

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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# +5V
#
DEF +5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# 74LS26
#
DEF 74LS26 U 0 30 Y Y 4 F N
F0 "U" 0 50 50 H V C CNN
F1 "74LS26" 0 -50 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
ALIAS 74LS38
DRAW
X GND 7 -200 -200 0 U 40 40 0 0 W N
X VCC 14 -200 200 0 U 40 40 0 0 W N
A 100 0 200 896 -896 0 1 0 N 101 200 101 -199
P 4 0 1 0 100 200 -300 200 -300 -200 100 -200 N
X ~ 1 -600 100 300 R 50 50 1 1 I
X ~ 2 -600 -100 300 R 50 50 1 1 I
X ~ 3 600 0 300 L 50 50 1 1 C I
X ~ 4 -600 100 300 R 50 50 2 1 I
X ~ 5 -600 -100 300 R 50 50 2 1 I
X ~ 6 600 0 300 L 50 50 2 1 C I
X ~ 8 600 0 300 L 50 50 3 1 C I
X ~ 9 -600 100 300 R 50 50 3 1 I
X ~ 10 -600 -100 300 R 50 50 3 1 I
X ~ 11 600 0 300 L 50 50 4 1 C I
X ~ 12 -600 100 300 R 50 50 4 1 I
X ~ 13 -600 -100 300 R 50 50 4 1 I
A -470 0 262 495 -495 0 2 0 N -300 199 -300 -198
A -2 126 326 -897 -225 0 2 0 N 0 -199 299 2
A 4 -120 320 906 221 0 2 0 N 2 200 300 0
P 2 0 2 0 -300 -200 0 -200 N
P 2 0 2 0 -300 200 0 200 N
X ~ 1 -600 100 370 R 50 50 1 2 I I
X ~ 2 -600 -100 370 R 50 50 1 2 I I
X ~ 3 600 0 300 L 50 50 1 2 C
X ~ 4 -600 100 370 R 50 50 2 2 I I
X ~ 5 -600 -100 370 R 50 50 2 2 I I
X ~ 6 600 0 300 L 50 50 2 2 C
X ~ 8 600 0 300 L 50 50 3 2 C
X ~ 9 -600 100 370 R 50 50 3 2 I I
X ~ 10 -600 -100 370 R 50 50 3 2 I I
X ~ 11 600 0 300 L 50 50 4 2 C
X ~ 12 -600 100 370 R 50 50 4 2 I I
X ~ 13 -600 -100 370 R 50 50 4 2 I I
ENDDRAW
ENDDEF
#
# C
#
DEF C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
C?
C_????_*
C_????
SMD*_c
Capacitor*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CONN_01X04
#
DEF CONN_01X04 P 0 40 Y N 1 F N
F0 "P" 0 250 50 H V C CNN
F1 "CONN_01X04" 100 0 50 V V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
Pin_Header_Straight_1X04
Pin_Header_Angled_1X04
Socket_Strip_Straight_1X04
Socket_Strip_Angled_1X04
$ENDFPLIST
DRAW
S -50 -145 10 -155 0 1 0 N
S -50 -45 10 -55 0 1 0 N
S -50 55 10 45 0 1 0 N
S -50 155 10 145 0 1 0 N
S -50 200 50 -200 0 1 0 N
X P1 1 -200 150 150 R 50 50 1 1 P
X P2 2 -200 50 150 R 50 50 1 1 P
X P3 3 -200 -50 150 R 50 50 1 1 P
X P4 4 -200 -150 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X02
#
DEF CONN_02X02 P 0 1 Y N 1 F N
F0 "P" 0 150 50 H V C CNN
F1 "CONN_02X02" 0 -150 50 H V C CNN
F2 "" 0 -1200 50 H V C CNN
F3 "" 0 -1200 50 H V C CNN
$FPLIST
Pin_Header_Straight_2X02
Pin_Header_Angled_2X02
Socket_Strip_Straight_2X02
Socket_Strip_Angled_2X02
$ENDFPLIST
DRAW
S -100 -45 -50 -55 0 1 0 N
S -100 55 -50 45 0 1 0 N
S -100 100 100 -100 0 1 0 N
S 50 -45 100 -55 0 1 0 N
S 50 55 100 45 0 1 0 N
X P1 1 -250 50 150 R 50 50 1 1 P
X P2 2 250 50 150 L 50 50 1 1 P
X P3 3 -250 -50 150 R 50 50 1 1 P
X P4 4 250 -50 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X03
#
DEF CONN_02X03 P 0 1 Y N 1 F N
F0 "P" 0 200 50 H V C CNN
F1 "CONN_02X03" 0 -200 50 H V C CNN
F2 "" 0 -1200 50 H V C CNN
F3 "" 0 -1200 50 H V C CNN
$FPLIST
Pin_Header_Straight_2X03
Pin_Header_Angled_2X03
Socket_Strip_Straight_2X03
Socket_Strip_Angled_2X03
$ENDFPLIST
DRAW
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 150 100 -150 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
X P1 1 -250 100 150 R 50 50 1 1 P
X P2 2 250 100 150 L 50 50 1 1 P
X P3 3 -250 0 150 R 50 50 1 1 P
X P4 4 250 0 150 L 50 50 1 1 P
X P5 5 -250 -100 150 R 50 50 1 1 P
X P6 6 250 -100 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X07
#
DEF CONN_02X07 P 0 1 Y N 1 F N
F0 "P" 0 400 50 H V C CNN
F1 "CONN_02X07" 0 0 50 V V C CNN
F2 "" 0 -1200 50 H V C CNN
F3 "" 0 -1200 50 H V C CNN
$FPLIST
Pin_Header_Straight_2X07
Pin_Header_Angled_2X07
Socket_Strip_Straight_2X07
Socket_Strip_Angled_2X07
$ENDFPLIST
DRAW
S -100 -295 -50 -305 0 1 0 N
S -100 -195 -50 -205 0 1 0 N
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 205 -50 195 0 1 0 N
S -100 305 -50 295 0 1 0 N
S -100 350 100 -350 0 1 0 N
S 50 -295 100 -305 0 1 0 N
S 50 -195 100 -205 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
S 50 205 100 195 0 1 0 N
S 50 305 100 295 0 1 0 N
X P1 1 -250 300 150 R 50 50 1 1 P
X P2 2 250 300 150 L 50 50 1 1 P
X P3 3 -250 200 150 R 50 50 1 1 P
X P4 4 250 200 150 L 50 50 1 1 P
X P5 5 -250 100 150 R 50 50 1 1 P
X P6 6 250 100 150 L 50 50 1 1 P
X P7 7 -250 0 150 R 50 50 1 1 P
X P8 8 250 0 150 L 50 50 1 1 P
X P9 9 -250 -100 150 R 50 50 1 1 P
X P10 10 250 -100 150 L 50 50 1 1 P
X P11 11 -250 -200 150 R 50 50 1 1 P
X P12 12 250 -200 150 L 50 50 1 1 P
X P13 13 -250 -300 150 R 50 50 1 1 P
X P14 14 250 -300 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X17
#
DEF CONN_02X17 P 0 1 Y N 1 F N
F0 "P" 0 900 50 H V C CNN
F1 "CONN_02X17" 0 0 50 V V C CNN
F2 "" 0 -1100 50 H V C CNN
F3 "" 0 -1100 50 H V C CNN
$FPLIST
Pin_Header_Straight_2X17
Pin_Header_Angled_2X17
Socket_Strip_Straight_2X17
Socket_Strip_Angled_2X17
$ENDFPLIST
DRAW
S -100 -795 -50 -805 0 1 0 N
S -100 -695 -50 -705 0 1 0 N
S -100 -595 -50 -605 0 1 0 N
S -100 -495 -50 -505 0 1 0 N
S -100 -395 -50 -405 0 1 0 N
S -100 -295 -50 -305 0 1 0 N
S -100 -195 -50 -205 0 1 0 N
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 205 -50 195 0 1 0 N
S -100 305 -50 295 0 1 0 N
S -100 405 -50 395 0 1 0 N
S -100 505 -50 495 0 1 0 N
S -100 605 -50 595 0 1 0 N
S -100 705 -50 695 0 1 0 N
S -100 805 -50 795 0 1 0 N
S -100 850 100 -850 0 1 0 N
S 50 -795 100 -805 0 1 0 N
S 50 -695 100 -705 0 1 0 N
S 50 -595 100 -605 0 1 0 N
S 50 -495 100 -505 0 1 0 N
S 50 -395 100 -405 0 1 0 N
S 50 -295 100 -305 0 1 0 N
S 50 -195 100 -205 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
S 50 205 100 195 0 1 0 N
S 50 305 100 295 0 1 0 N
S 50 405 100 395 0 1 0 N
S 50 505 100 495 0 1 0 N
S 50 605 100 595 0 1 0 N
S 50 705 100 695 0 1 0 N
S 50 805 100 795 0 1 0 N
X P1 1 -250 800 150 R 50 50 1 1 P
X P2 2 250 800 150 L 50 50 1 1 P
X P3 3 -250 700 150 R 50 50 1 1 P
X P4 4 250 700 150 L 50 50 1 1 P
X P5 5 -250 600 150 R 50 50 1 1 P
X P6 6 250 600 150 L 50 50 1 1 P
X P7 7 -250 500 150 R 50 50 1 1 P
X P8 8 250 500 150 L 50 50 1 1 P
X P9 9 -250 400 150 R 50 50 1 1 P
X P10 10 250 400 150 L 50 50 1 1 P
X P20 20 250 -100 150 L 50 50 1 1 P
X P30 30 250 -600 150 L 50 50 1 1 P
X P11 11 -250 300 150 R 50 50 1 1 P
X P21 21 -250 -200 150 R 50 50 1 1 P
X P31 31 -250 -700 150 R 50 50 1 1 P
X P12 12 250 300 150 L 50 50 1 1 P
X P22 22 250 -200 150 L 50 50 1 1 P
X P32 32 250 -700 150 L 50 50 1 1 P
X P13 13 -250 200 150 R 50 50 1 1 P
X P23 23 -250 -300 150 R 50 50 1 1 P
X P33 33 -250 -800 150 R 50 50 1 1 P
X P14 14 250 200 150 L 50 50 1 1 P
X P24 24 250 -300 150 L 50 50 1 1 P
X P34 34 250 -800 150 L 50 50 1 1 P
X P15 15 -250 100 150 R 50 50 1 1 P
X P25 25 -250 -400 150 R 50 50 1 1 P
X P16 16 250 100 150 L 50 50 1 1 P
X P26 26 250 -400 150 L 50 50 1 1 P
X P17 17 -250 0 150 R 50 50 1 1 P
X P27 27 -250 -500 150 R 50 50 1 1 P
X P18 18 250 0 150 L 50 50 1 1 P
X P28 28 250 -500 150 L 50 50 1 1 P
X P19 19 -250 -100 150 R 50 50 1 1 P
X P29 29 -250 -600 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CP
#
DEF CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "CP" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
CP*
Elko*
TantalC*
C*elec
c_elec*
SMD*_Pol
$ENDFPLIST
DRAW
S -90 20 -90 40 0 1 0 N
S -90 20 90 20 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
S 90 40 -90 40 0 1 0 N
S 90 40 90 20 0 1 0 N
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# D
#
DEF D D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "D" 0 -100 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
Diode_*
D-Pak_TO252AA
*SingleDiode
*_Diode_*
*SingleDiode*
$ENDFPLIST
DRAW
P 2 0 1 6 -50 50 -50 -50 N
P 3 0 1 0 50 50 -50 0 50 -50 F
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# F_Small
#
DEF F_Small F 0 10 N N 1 F N
F0 "F" -40 60 50 H V L CNN
F1 "F_Small" -120 -60 50 H V L CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
CP*
SM*
$ENDFPLIST
DRAW
S -50 20 50 -20 0 1 0 N
P 2 0 1 0 -50 0 50 0 N
X ~ 1 -100 0 50 R 40 40 1 1 P
X ~ 2 100 0 50 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# GND
#
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# HDR_3X5
#
DEF HDR_3X5 P 0 40 Y Y 1 F N
F0 "P" 0 0 60 H V C CNN
F1 "HDR_3X5" 0 -400 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 -100 300 -700 0 1 0 N
X ~ 1 -500 -200 200 R 50 50 1 1 I
X ~ 2 -500 -300 200 R 50 50 1 1 I
X ~ 3 -500 -400 200 R 50 50 1 1 I
X ~ 4 -500 -500 200 R 50 50 1 1 I
X ~ 5 -500 -600 200 R 50 50 1 1 I
X ~ 6 500 -600 200 L 50 50 1 1 I
X ~ 7 500 -500 200 L 50 50 1 1 I
X ~ 8 500 -400 200 L 50 50 1 1 I
X ~ 9 500 -300 200 L 50 50 1 1 I
X ~ 10 500 -200 200 L 50 50 1 1 I
X ~ 11 -200 -900 200 U 50 50 1 1 I
X ~ 12 -100 -900 200 U 50 50 1 1 I
X ~ 13 0 -900 200 U 50 50 1 1 I
X ~ 14 100 -900 200 U 50 50 1 1 I
X ~ 15 200 -900 200 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# MMBT3904
#
DEF MMBT3904 Q 0 0 Y Y 1 F N
F0 "Q" 200 75 50 H V L CNN
F1 "MMBT3904" 200 0 50 H V L CNN
F2 "SOT-23" 200 -75 50 H V L CIN
F3 "" 0 0 50 H V L CNN
$FPLIST
SOT-23*
$ENDFPLIST
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 25 0 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
X B 1 -200 0 200 R 50 50 1 1 I
X E 2 100 -200 100 U 50 50 1 1 P
X C 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# MMBT3906
#
DEF MMBT3906 Q 0 0 Y Y 1 F N
F0 "Q" 200 75 50 H V L CNN
F1 "MMBT3906" 200 0 50 H V L CNN
F2 "SOT-23" 200 -75 50 H V L CIN
F3 "" 0 0 50 H V L CNN
$FPLIST
SOT-23*
$ENDFPLIST
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 25 0 N
P 2 0 1 0 100 -100 25 -25 N
P 2 0 1 0 100 100 25 25 N
P 3 0 1 20 25 75 25 -75 25 -75 F
P 5 0 1 0 55 -75 75 -55 35 -35 55 -75 55 -75 F
X B 1 -200 0 200 R 50 50 1 1 I
X E 2 100 -200 100 U 50 50 1 1 P
X C 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# PWR_FLAG
#
DEF PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 95 50 H I C CNN
F1 "PWR_FLAG" 0 180 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
X pwr 1 0 0 0 U 50 50 0 0 w
P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
ENDDRAW
ENDDEF
#
# R
#
DEF R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "R" 0 0 50 V V C CNN
F2 "" -70 0 50 V V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
R_*
Resistor_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# TAOBAO
#
DEF TAOBAO U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "TAOBAO" 0 -2250 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -550 -50 550 -2150 0 1 0 N
X PB12 1 -750 -150 200 R 50 50 1 1 P
X PB13 2 -750 -250 200 R 50 50 1 1 P
X PB14 3 -750 -350 200 R 50 50 1 1 P
X PB15 4 -750 -450 200 R 50 50 1 1 P
X PA8 5 -750 -550 200 R 50 50 1 1 P
X PA9 6 -750 -650 200 R 50 50 1 1 P
X PA10 7 -750 -750 200 R 50 50 1 1 P
X PA11 8 -750 -850 200 R 50 50 1 1 P
X PA12 9 -750 -950 200 R 50 50 1 1 P
X PA15 10 -750 -1050 200 R 50 50 1 1 P
X 3V3 20 -750 -2050 200 R 50 50 1 1 P
X PA5 30 750 -1150 200 L 50 50 1 1 P
X GND 40 750 -150 200 L 50 50 1 1 P
X PB3 11 -750 -1150 200 R 50 50 1 1 P
X VBat 21 750 -2050 200 L 50 50 1 1 P
X PA6 31 750 -1050 200 L 50 50 1 1 P
X PB4 12 -750 -1250 200 R 50 50 1 1 P
X PC13 22 750 -1950 200 L 50 50 1 1 P
X PA7 32 750 -950 200 L 50 50 1 1 P
X PB5 13 -750 -1350 200 R 50 50 1 1 P
X PC14 23 750 -1850 200 L 50 50 1 1 P
X PB0 33 750 -850 200 L 50 50 1 1 P
X PB6 14 -750 -1450 200 R 50 50 1 1 P
X PC15 24 750 -1750 200 L 50 50 1 1 P
X PB1 34 750 -750 200 L 50 50 1 1 P
X PB7 15 -750 -1550 200 R 50 50 1 1 P
X PA0 25 750 -1650 200 L 50 50 1 1 P
X PB10 35 750 -650 200 L 50 50 1 1 P
X PB8 16 -750 -1650 200 R 50 50 1 1 P
X PA1 26 750 -1550 200 L 50 50 1 1 P
X PB11 36 750 -550 200 L 50 50 1 1 P
X PB9 17 -750 -1750 200 R 50 50 1 1 P
X PA2 27 750 -1450 200 L 50 50 1 1 P
X RST 37 750 -450 200 L 50 50 1 1 P
X VIn 18 -750 -1850 200 R 50 50 1 1 P
X PA3 28 750 -1350 200 L 50 50 1 1 P
X 3V3 38 750 -350 200 L 50 50 1 1 P
X GND 19 -750 -1950 200 R 50 50 1 1 P
X PA4 29 750 -1250 200 L 50 50 1 1 P
X GND 39 750 -250 200 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# VCC
#
DEF VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VCC" 0 150 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
C 0 75 25 0 1 0 N
P 2 0 1 0 0 0 0 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# ZENER
#
DEF ZENER D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "ZENER" 0 -100 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
D?
SO*
SM*
$ENDFPLIST
DRAW
P 5 0 1 8 -70 50 -50 30 -50 -30 -30 -50 -30 -50 N
P 5 0 1 0 -50 0 50 50 50 -50 -50 0 -50 0 F
X K 1 -200 0 150 R 50 50 1 1 P
X A 2 200 0 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

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71
pcb/TB/161/FF-TB161.pro Normal file
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@ -0,0 +1,71 @@
update=Fri 03 Jul 2015 05:29:28 BST
version=1
last_client=kicad
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[general]
version=1
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60
[eeschema]
version=1
LibDir=../..
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=microcontrollers
LibName13=dsp
LibName14=microchip
LibName15=analog_switches
LibName16=motorola
LibName17=texas
LibName18=intel
LibName19=audio
LibName20=interface
LibName21=digital-audio
LibName22=philips
LibName23=display
LibName24=cypress
LibName25=siliconi
LibName26=opto
LibName27=atmel
LibName28=contrib
LibName29=valves
LibName30=FF

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