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ODROID-XU android-4.2.2(JellyBean) kernel

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This commit is contained in:
codewalker 2014-07-10 12:06:26 +09:00
parent 325f14c8fe
commit 624f9409c3
58 changed files with 878 additions and 2835 deletions
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2
arch/arm/configs/odroidxu_android_defconfig
View file

@ -2180,7 +2180,7 @@ CONFIG_PVR_SGX=y
CONFIG_PVR_BUILD_RELEASE=y
# CONFIG_PVR_BUILD_DEBUG is not set
CONFIG_PVR_SGX_DVFS=y
# CONFIG_PVR_SGX_FENCE_SYNC is not set
CONFIG_PVR_SGX_ACTIVE_POWER_MANAGEMENT=y
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y

10
drivers/cpufreq/exynos5410-cpufreq.c
View file

@ -835,13 +835,11 @@ static void __init set_volt_table_CA7(void)
max_support_idx_CA7 = L7;
}
printk("\nCKKIM -> %s(%d)\n\n",__func__,__LINE__);
if (get_asv_is_bin2()) {
// exynos5410_freq_table_CA7[L1].frequency = CPUFREQ_ENTRY_INVALID;
// exynos5410_freq_table_CA7[L2].frequency = CPUFREQ_ENTRY_INVALID;
// exynos5410_freq_table_CA7[L3].frequency = CPUFREQ_ENTRY_INVALID;
// max_support_idx_CA7 = L4;
printk("\nCKKIM -> %s(%d) : Bin2 \n\n",__func__,__LINE__);
exynos5410_freq_table_CA7[L1].frequency = CPUFREQ_ENTRY_INVALID;
exynos5410_freq_table_CA7[L2].frequency = CPUFREQ_ENTRY_INVALID;
exynos5410_freq_table_CA7[L3].frequency = CPUFREQ_ENTRY_INVALID;
max_support_idx_CA7 = L4;
}
exynos5410_freq_table_CA7[L9].frequency = CPUFREQ_ENTRY_INVALID;

8
drivers/gpu/pvr/Kconfig Normal file → Executable file
View file

@ -27,9 +27,9 @@ config PVR_SGX_DVFS
help
This enables DVFS for SGX.
config PVR_SGX_FENCE_SYNC
bool "Enables Android Native fence sync for SGX"
config PVR_SGX_ACTIVE_POWER_MANAGEMENT
bool "Enables Active Power Management for SGX"
depends on PVR_SGX
default n
default y
help
This enables fence sync for SGX.
This enables active power management for SGX.

15
drivers/gpu/pvr/Makefile Normal file → Executable file
View file

@ -19,6 +19,7 @@ ccflags-y := \
-Wstrict-prototypes\
-Wno-unused-parameter\
-Wno-sign-compare\
-Werror\
-fno-strict-aliasing\
-Wno-pointer-arith\
-Os
@ -72,19 +73,19 @@ DEFINES += \
-DSUPPORT_HW_RECOVERY \
-DSUPPORT_MEMINFO_IDS \
-DSYS_SGX_ACTIVE_POWER_LATENCY_MS=50 \
-DPVR_LINUX_MEM_AREA_POOL_MAX_PAGES=5400 \
-DSUPPORT_PVRSRV_GET_DC_SYSTEM_BUFFER \
-DSUPPORT_LINUX_X86_WRITECOMBINE \
-DSUPPORT_LINUX_X86_PAT \
-DSUPPORT_LARGE_GENERAL_HEAP \
-DSUPPORT_ACTIVE_POWER_MANAGEMENT \
-DUSING_532MHZ \
-DSUPPORT_DC_CMDCOMPLETE_WHEN_NO_LONGER_DISPLAYED \
-DSUPPORT_ANDROID_SYNC \
-DUSING_640MHZ \
-DSUPPORT_SGX_HWPERF \
-DDUMP_UKERNEL_INFO_AT_TIMEOUT \
-DPVR_DISABLE_LOGGING \
-DDUMP_UKERNEL_INFO_AT_TIMEOUT
ifeq ($(CONFIG_PVR_SGX_FENCE_SYNC),y)
DEFINES += -DPVR_ANDROID_NATIVE_WINDOW_HAS_SYNC
ifeq ($(CONFIG_PVR_SGX_ACTIVE_POWER_MANAGEMENT),y)
DEFINES += \
-DSUPPORT_ACTIVE_POWER_MANAGEMENT
endif
#TODO : check this option

117
drivers/gpu/pvr/include4/pvr_sync_user.h
View file

@ -1,117 +0,0 @@
/*************************************************************************/ /*!
@File pvr_sync_user.h
@Title Userspace definitions to use the kernel sync driver
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
@Description Version numbers and strings for PVR Consumer services
components.
@License Dual MIT/GPLv2
The contents of this file are subject to the MIT license as set out below.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
Alternatively, the contents of this file may be used under the terms of
the GNU General Public License Version 2 ("GPL") in which case the provisions
of GPL are applicable instead of those above.
If you wish to allow use of your version of this file only under the terms of
GPL, and not to allow others to use your version of this file under the terms
of the MIT license, indicate your decision by deleting the provisions above
and replace them with the notice and other provisions required by GPL as set
out in the file called "GPL-COPYING" included in this distribution. If you do
not delete the provisions above, a recipient may use your version of this file
under the terms of either the MIT license or GPL.
This License is also included in this distribution in the file called
"MIT-COPYING".
EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/ /**************************************************************************/
#ifndef _PVR_SYNC_USER_H_
#define _PVR_SYNC_USER_H_
#include <linux/ioctl.h>
#ifdef __KERNEL__
#include "sgxapi_km.h"
#else
#include "sgxapi.h"
#endif
#include "servicesext.h" // PVRSRV_SYNC_DATA
#include "img_types.h"
/* This matches the sw_sync create ioctl data */
struct PVR_SYNC_CREATE_IOCTL_DATA
{
char name[32];
__s32 fence; /* fd of new fence */
/* or fd of already alloc'd fence */
__s32 allocdSyncInfo; /* If this is provided (not -1) this points to a fence allocated
* by the ALLOC_FENCE ioctl, and it's syncinfo is moved to the newly created
* fence */
};
struct PVR_SYNC_ALLOC_IOCTL_DATA
{
char name[32];
__s32 fence; /* fd of newly alloc'd fence */
};
#define PVR_SYNC_DEBUG_MAX_POINTS 3
typedef struct
{
IMG_UINT64 ui64Stamp;
IMG_UINT32 ui32WriteOpsPendingSnapshot;
}
PVR_SYNC_DEBUG;
struct PVR_SYNC_DEBUG_IOCTL_DATA
{
/* Input: Fence to acquire debug for */
int iFenceFD;
/* Output: Number of points merged into this fence */
IMG_UINT32 ui32NumPoints;
struct
{
/* Output: Metadata for sync point */
PVR_SYNC_DEBUG sMetaData;
/* Output: 'Live' sync information. */
PVRSRV_SYNC_DATA sSyncData;
}
sSync[PVR_SYNC_DEBUG_MAX_POINTS];
};
#define PVR_SYNC_IOC_MAGIC 'W'
#define PVR_SYNC_IOC_CREATE_FENCE \
_IOWR(PVR_SYNC_IOC_MAGIC, 0, struct PVR_SYNC_CREATE_IOCTL_DATA)
#define PVR_SYNC_IOC_DEBUG_FENCE \
_IOWR(PVR_SYNC_IOC_MAGIC, 1, struct PVR_SYNC_DEBUG_IOCTL_DATA)
#define PVR_SYNC_IOC_ALLOC_FENCE \
_IOWR(PVR_SYNC_IOC_MAGIC, 2, struct PVR_SYNC_ALLOC_IOCTL_DATA)
#define PVRSYNC_MODNAME "pvr_sync"
#endif /* _PVR_SYNC_USER_H_ */

6
drivers/gpu/pvr/include4/pvrversion.h
View file

@ -53,7 +53,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PVRVERSION_FAMILY "sgxddk"
#define PVRVERSION_BRANCHNAME "1.10"
#define PVRVERSION_BUILD 2359475
#define PVRVERSION_BUILD 2209507
#define PVRVERSION_BSCONTROL "SGX_DDK_Android"
#define PVRVERSION_STRING "SGX_DDK_Android sgxddk 1.10@" PVR_STR2(PVRVERSION_BUILD)
@ -61,8 +61,8 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define COPYRIGHT_TXT "Copyright (c) Imagination Technologies Ltd. All Rights Reserved."
#define PVRVERSION_BUILD_HI 235
#define PVRVERSION_BUILD_LO 9475
#define PVRVERSION_BUILD_HI 220
#define PVRVERSION_BUILD_LO 9507
#define PVRVERSION_STRING_NUMERIC PVR_STR2(PVRVERSION_MAJ) "." PVR_STR2(PVRVERSION_MIN) "." PVR_STR2(PVRVERSION_BUILD_HI) "." PVR_STR2(PVRVERSION_BUILD_LO)
#endif /* _PVRVERSION_H_ */

11
drivers/gpu/pvr/include4/services.h
View file

@ -819,9 +819,8 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceMemory2(IMG_CONST PVRSRV_DEV_DATA *psDe
#if defined(SUPPORT_ION)
PVRSRV_ERROR PVRSRVMapIonHandle(const PVRSRV_DEV_DATA *psDevData,
IMG_HANDLE hDevMemHeap,
IMG_UINT32 ui32NumFDs,
IMG_INT *paiBufferFDs,
IMG_HANDLE hDevMemHeap,
IMG_INT32 uiFD,
IMG_UINT32 ui32ChunkCount,
IMG_SIZE_T *pauiOffset,
IMG_SIZE_T *pauiSize,
@ -980,11 +979,9 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVSwapToDCBuffer2 (IMG_HANDLE hDevice,
IMG_HANDLE hBuffer,
IMG_UINT32 ui32SwapInterval,
PVRSRV_CLIENT_MEM_INFO **ppsMemInfos,
PVRSRV_CLIENT_SYNC_INFO **ppsSyncInfos,
IMG_UINT32 ui32NumMemSyncInfos,
IMG_UINT32 ui32NumMemInfos,
IMG_PVOID pvPrivData,
IMG_UINT32 ui32PrivDataLength,
IMG_HANDLE *phFence);
IMG_UINT32 ui32PrivDataLength);
IMG_IMPORT
PVRSRV_ERROR IMG_CALLCONV PVRSRVSwapToDCSystem (IMG_HANDLE hDevice,

3
drivers/gpu/pvr/include4/servicesext.h
View file

@ -645,9 +645,6 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ {
PVRSRV_PIXEL_FORMAT_RAW512 = 224,
PVRSRV_PIXEL_FORMAT_RAW1024 = 225,
/* Same as NV12 but with interleaved VU rather than interleaved UV */
PVRSRV_PIXEL_FORMAT_NV21 = 226,
PVRSRV_PIXEL_FORMAT_FORCE_I32 = 0x7fffffff
} PVRSRV_PIXEL_FORMAT;

6
drivers/gpu/pvr/include4/sgxapi_km.h
View file

@ -117,14 +117,8 @@ extern "C" {
#define SGX_MAX_SRC_SYNCS_TA 32
#define SGX_MAX_DST_SYNCS_TA 1
/* note: there is implicitly 1 3D Dst Sync */
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
/* note: only one dst sync is supported by the 2D paths */
#define SGX_MAX_SRC_SYNCS_TQ 6
#define SGX_MAX_DST_SYNCS_TQ 2
#else /* defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */
#define SGX_MAX_SRC_SYNCS_TQ 8
#define SGX_MAX_DST_SYNCS_TQ 1
#endif /* defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */
#endif

7
drivers/gpu/pvr/include4/sgxscript.h
View file

@ -42,13 +42,11 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef __SGXSCRIPT_H__
#define __SGXSCRIPT_H__
#include "sgxfeaturedefs.h"
#if defined (__cplusplus)
extern "C" {
#endif
#define SGX_MAX_INIT_COMMANDS 64
#define SGX_MAX_PRINT_COMMANDS 96
#define SGX_MAX_DEINIT_COMMANDS 16
typedef enum _SGX_INIT_OPERATION
@ -56,7 +54,6 @@ typedef enum _SGX_INIT_OPERATION
SGX_INIT_OP_ILLEGAL = 0,
SGX_INIT_OP_WRITE_HW_REG,
SGX_INIT_OP_READ_HW_REG,
SGX_INIT_OP_PRINT_HW_REG,
#if defined(PDUMP)
SGX_INIT_OP_PDUMP_HW_REG,
#endif
@ -89,10 +86,6 @@ typedef struct _SGX_INIT_SCRIPTS_
SGX_INIT_COMMAND asInitCommandsPart1[SGX_MAX_INIT_COMMANDS];
SGX_INIT_COMMAND asInitCommandsPart2[SGX_MAX_INIT_COMMANDS];
SGX_INIT_COMMAND asDeinitCommands[SGX_MAX_DEINIT_COMMANDS];
#if defined(SGX_FEATURE_MP)
SGX_INIT_COMMAND asSGXREGDebugCommandsPart1[SGX_MAX_PRINT_COMMANDS];
#endif
SGX_INIT_COMMAND *apsSGXREGDebugCommandsPart2[SGX_FEATURE_MP_CORE_COUNT_3D];
} SGX_INIT_SCRIPTS;
#if defined(__cplusplus)

10
drivers/gpu/pvr/services4/3rdparty/s3c_lcd/s3c_displayclass.c vendored
View file

@ -590,10 +590,10 @@ static PVRSRV_ERROR CreateDCSwapChain(IMG_HANDLE hDevice,
}
psSwapChain = (S3C_SWAPCHAIN *)kmalloc(sizeof(S3C_SWAPCHAIN),GFP_KERNEL);
if(!psSwapChain)
return (PVRSRV_ERROR_OUT_OF_MEMORY);
if (!psSwapChain)
return PVRSRV_ERROR_OUT_OF_MEMORY;
psBuffer = (S3C_FRAME_BUFFER*)kmalloc(sizeof(S3C_FRAME_BUFFER) * ui32BufferCount, GFP_KERNEL);
if(!psBuffer)
{
kfree(psSwapChain);
@ -1062,7 +1062,7 @@ int s3c_displayclass_init(void)
IMG_UINT32 aui32SyncCountList[DC_S3C_LCD_COMMAND_COUNT][2];
g_psLCDInfo = (S3C_LCD_DEVINFO*)kmalloc(sizeof(S3C_LCD_DEVINFO),GFP_KERNEL);
if(!g_psLCDInfo)
if (!g_psLCDInfo)
{
printk("Fail to get memory for g_psLCDInfo\n");
goto err_out;
@ -1148,7 +1148,7 @@ int s3c_displayclass_init(void)
goto err_out;
}
pfnCmdProcList[DC_FLIP_COMMAND] = (PFN_CMD_PROC)ProcessFlip;
pfnCmdProcList[DC_FLIP_COMMAND] = ProcessFlip;
aui32SyncCountList[DC_FLIP_COMMAND][0] = 0;
aui32SyncCountList[DC_FLIP_COMMAND][1] = 2;

19
drivers/gpu/pvr/services4/include/pvr_bridge.h
View file

@ -530,13 +530,11 @@ typedef struct PVRSRV_BRIDGE_IN_EXPORTDEVICEMEM_TAG
/******************************************************************************
* 'bridge in' map ion handle
*****************************************************************************/
#define ION_IMPORT_MAX_FDS 3
#define ION_IMPORT_MAX_CHUNK_COUNT 3
typedef struct _PVRSRV_BRIDGE_IN_MAP_ION_HANDLE_
{
IMG_UINT32 ui32BridgeFlags; /* Must be first member of structure */
IMG_UINT32 ui32NumFDs;
IMG_INT32 ai32BufferFDs[ION_IMPORT_MAX_FDS];
IMG_HANDLE handle;
IMG_UINT32 ui32Attribs;
IMG_UINT32 ui32ChunkCount;
IMG_SIZE_T auiOffset[ION_IMPORT_MAX_CHUNK_COUNT];
@ -1237,9 +1235,8 @@ typedef struct PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_BUFFER_TAG
} PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_BUFFER;
/******************************************************************************
* 'bridge in' swap to buffer 2
* 'bridge in' swap to buffer
*****************************************************************************/
typedef struct PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_BUFFER2_TAG
{
@ -1257,18 +1254,6 @@ typedef struct PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_BUFFER2_TAG
} PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_BUFFER2;
/******************************************************************************
* 'bridge out' swap to buffer 2
*****************************************************************************/
typedef struct PVRSRV_BRIDGE_OUT_SWAP_DISPCLASS_TO_BUFFER2_TAG
{
PVRSRV_ERROR eError;
IMG_HANDLE hFence;
} PVRSRV_BRIDGE_OUT_SWAP_DISPCLASS_TO_BUFFER2;
/******************************************************************************
* 'bridge in' swap to system buffer (primary)
*****************************************************************************/

6
drivers/gpu/pvr/services4/include/pvr_bridge_km.h
View file

@ -148,8 +148,7 @@ IMG_IMPORT
PVRSRV_ERROR PVRSRVMapIonHandleKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
IMG_HANDLE hDevCookie,
IMG_HANDLE hDevMemHeap,
IMG_UINT32 ui32NumFDs,
IMG_INT32 *pai32BufferFDs,
IMG_HANDLE hIon,
IMG_UINT32 ui32Flags,
IMG_UINT32 ui32ChunkCount,
IMG_SIZE_T *pauiOffset,
@ -281,8 +280,7 @@ PVRSRV_ERROR PVRSRVSwapToDCBuffer2KM(IMG_HANDLE hDeviceKM,
PVRSRV_KERNEL_SYNC_INFO **ppsSyncInfos,
IMG_UINT32 ui32NumMemSyncInfos,
IMG_PVOID pvPrivData,
IMG_UINT32 ui32PrivDataLength,
IMG_HANDLE *phFence);
IMG_UINT32 ui32PrivDataLength);
IMG_IMPORT
PVRSRV_ERROR PVRSRVSwapToDCSystemKM(IMG_HANDLE hDeviceKM,
IMG_HANDLE hSwapChain);

10
drivers/gpu/pvr/services4/include/servicesint.h
View file

@ -249,11 +249,6 @@ typedef struct _PVRSRV_COMMAND
allocated on back of this structure, i.e. is resident in Q */
PFN_QUEUE_COMMAND_COMPLETE pfnCommandComplete; /*!< Command complete callback */
IMG_HANDLE hCallbackData; /*!< Command complete callback data */
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
IMG_VOID *pvCleanupFence; /*!< Sync fence to 'put' after timeline inc() */
IMG_VOID *pvTimeline; /*!< Android sync timeline to inc() */
#endif
}PVRSRV_COMMAND, *PPVRSRV_COMMAND;
@ -307,11 +302,6 @@ typedef struct _PVRSRV_QUEUE_INFO_
IMG_HANDLE hMemBlock[2];
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
IMG_UINT32 ui32FenceValue; /*!< 'Target' timeline value when fence signals */
IMG_VOID *pvTimeline; /*!< Android struct sync_timeline object */
#endif
struct _PVRSRV_QUEUE_INFO_ *psNextKM; /*!< The next queue in the system */
}PVRSRV_QUEUE_INFO;

8
drivers/gpu/pvr/services4/include/sgx_ukernel_status_codes.h
View file

@ -239,14 +239,6 @@ MKTC_ST(MKTC_KICKTA_TACMD_DEBUG)
MKTC_ST(MKTC_KICKTA_FREECONTEXT)
#define MKTC_KICKTA_PIM_PATCHING 0xAD00080C
MKTC_ST(MKTC_KICKTA_PIM_PATCHING)
#define MKTC_KICKTA_TPC_CHECK_START 0xAD00080D
MKTC_ST(MKTC_KICKTA_TPC_CHECK_START)
#define MKTC_KICKTA_TPC_CHECK_END 0xAD00080E
MKTC_ST(MKTC_KICKTA_TPC_CHECK_END)
#define MKTC_KICKTA_TPC_CHECK_CORE 0xAD00080F
MKTC_ST(MKTC_KICKTA_TPC_CHECK_CORE)
#define MKTC_KICKTA_TPC_CHECK_FAIL 0xAD000810
MKTC_ST(MKTC_KICKTA_TPC_CHECK_FAIL)
#define MKTC_KICKTA_CHKPT_START_DUMMY_CS 0xAD0008A1
MKTC_ST(MKTC_KICKTA_CHKPT_START_DUMMY_CS)

12
drivers/gpu/pvr/services4/include/sgxinfo.h
View file

@ -120,6 +120,10 @@ typedef struct _SGX_BRIDGE_INIT_INFO_
IMG_HANDLE hKernelClearClipWAPSGRgnHdrMemInfo;
#endif
#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31559)
IMG_HANDLE hKernelVDMSnapShotBufferMemInfo;
IMG_HANDLE hKernelVDMCtrlStreamBufferMemInfo;
#endif
#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && \
defined(FIX_HW_BRN_33657) && defined(SUPPORT_SECURE_33657_FIX)
IMG_HANDLE hKernelVDMStateUpdateBufferMemInfo;
@ -301,10 +305,6 @@ typedef struct _PVRSRV_TRANSFER_SGX_KICK_
IMG_UINT32 ui32CCBDumpWOff;
#endif
IMG_HANDLE hDevMemContext;
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
/* Android >JB MR1 doesn't use ahSrcSyncInfo for synchronization */
IMG_INT iFenceFd;
#endif
} PVRSRV_TRANSFER_SGX_KICK, *PPVRSRV_TRANSFER_SGX_KICK;
#if defined(SGX_FEATURE_2D_HARDWARE)
@ -332,10 +332,6 @@ typedef struct _PVRSRV_2D_SGX_KICK_
IMG_UINT32 ui32CCBDumpWOff;
#endif
IMG_HANDLE hDevMemContext;
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
/* Android >JB MR1 doesn't use ahSrcSyncInfo for synchronization */
IMG_INT iFenceFd;
#endif
} PVRSRV_2D_SGX_KICK, *PPVRSRV_2D_SGX_KICK;
#endif /* defined(SGX_FEATURE_2D_HARDWARE) */
#endif /* defined(TRANSFER_QUEUE) */

113
drivers/gpu/pvr/services4/srvkm/bridged/bridged_pvr_bridge.c
View file

@ -86,11 +86,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#endif
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
#include <linux/file.h>
#include <linux/sync.h>
#endif
#include "srvkm.h"
/* FIXME: we should include an OS specific header here to allow configuration of
@ -1015,7 +1010,7 @@ PVRSRVUnmapDeviceMemoryBW(IMG_UINT32 ui32BridgeID,
PVRSRV_HANDLE_TYPE_MEM_INFO);
if(psRetOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceMemoryBW: PVRSRVLookupHandle failed %d",psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceMemoryBW: PVRSRVLookupHandle failed %d", psRetOUT->eError));
return 0;
}
@ -1033,8 +1028,8 @@ PVRSRVUnmapDeviceMemoryBW(IMG_UINT32 ui32BridgeID,
psRetOUT->eError = PVRSRVUnmapDeviceMemoryKM(psKernelMemInfo);
if(psRetOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceMemoryBW: PVRSRVUnmapDeviceMemoryKM failed %d",psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceMemoryKM: psKernelMemInfo: 0x%x",(unsigned int)psKernelMemInfo));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceMemoryBW: PVRSRVUnmapDeviceMemoryKM failed %d", psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceMemoryKM: psKernelMemInfo: 0x%x", (unsigned int)psKernelMemInfo));
return 0;
}
}
@ -1045,8 +1040,8 @@ PVRSRVUnmapDeviceMemoryBW(IMG_UINT32 ui32BridgeID,
if(psRetOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceMemoryBW: PVRSRVReleaseHandle failed %d",psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVReleaseHandle: psHandleBase: 0x%x, psKernelMemInfo: 0x%x",(unsigned int)psPerProc->psHandleBase,(unsigned int)psUnmapDevMemIN->psKernelMemInfo));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceMemoryBW: PVRSRVReleaseHandle failed %d", psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVReleaseHandle: psHandleBase: 0x%x, psKernelMemInfo: 0x%x", (unsigned int)psPerProc->psHandleBase, (unsigned int)psUnmapDevMemIN->psKernelMemInfo));
return 0;
}
return 0;
@ -1202,7 +1197,7 @@ PVRSRVUnmapDeviceClassMemoryBW(IMG_UINT32 ui32BridgeID,
PVRSRV_HANDLE_TYPE_MEM_INFO);
if(psRetOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceClassMemoryBW: PVRSRVLookupHandle failed %d",psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceClassMemoryBW: PVRSRVLookupHandle failed %d", psRetOUT->eError));
return 0;
}
@ -1210,8 +1205,8 @@ PVRSRVUnmapDeviceClassMemoryBW(IMG_UINT32 ui32BridgeID,
if(psRetOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceClassMemoryBW: PVRSRVUnmapDeviceClassMemoryKM failed %d",psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceClassMemoryKM: pvKernelMemInfo: 0x%x",(unsigned int)pvKernelMemInfo));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceClassMemoryBW: PVRSRVUnmapDeviceClassMemoryKM failed %d", psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceClassMemoryKM: pvKernelMemInfo: 0x%x", (unsigned int)pvKernelMemInfo));
return 0;
}
@ -1222,8 +1217,8 @@ PVRSRVUnmapDeviceClassMemoryBW(IMG_UINT32 ui32BridgeID,
if(psRetOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceClassMemoryBW: PVRSRVReleaseHandle failed %d",psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVReleaseHandle: psHandleBase: 0x%x, psKernelMemInfo: 0x%x",(unsigned int)psPerProc->psHandleBase,(unsigned int)psUnmapDevClassMemIN->psKernelMemInfo));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceClassMemoryBW: PVRSRVReleaseHandle failed %d", psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVReleaseHandle: psHandleBase: 0x%x, psKernelMemInfo: 0x%x", (unsigned int)psPerProc->psHandleBase, (unsigned int)psUnmapDevClassMemIN->psKernelMemInfo));
return 0;
}
return 0;
@ -1389,7 +1384,7 @@ PVRSRVUnwrapExtMemoryBW(IMG_UINT32 ui32BridgeID,
PVRSRV_HANDLE_TYPE_MEM_INFO);
if(psRetOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnwrapExtMemoryBW: PVRSRVLookupHandle failed %d",psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnwrapExtMemoryBW: PVRSRVLookupHandle failed %d", psRetOUT->eError));
return 0;
}
@ -1397,8 +1392,8 @@ PVRSRVUnwrapExtMemoryBW(IMG_UINT32 ui32BridgeID,
PVRSRVUnwrapExtMemoryKM((PVRSRV_KERNEL_MEM_INFO *)pvMemInfo);
if(psRetOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnwrapExtMemoryBW: PVRSRVUnwrapExtMemoryKM failed %d",psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnwrapExtMemoryKM: pvMemInfo: 0x%x",(unsigned int)pvMemInfo));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnwrapExtMemoryBW: PVRSRVUnwrapExtMemoryKM failed %d", psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnwrapExtMemoryKM: pvMemInfo: 0x%x", (unsigned int)pvMemInfo));
return 0;
}
@ -1409,10 +1404,11 @@ PVRSRVUnwrapExtMemoryBW(IMG_UINT32 ui32BridgeID,
if(psRetOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnwrapExtMemoryBW: PVRSRVReleaseHandle failed %d",psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVReleaseHandle: psHandleBase: 0x%x, hKernelMemInfo: 0x%x",(unsigned int)psPerProc->psHandleBase,(unsigned int)psUnwrapExtMemIN->hKernelMemInfo));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnwrapExtMemoryBW: PVRSRVReleaseHandle failed %d", psRetOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVReleaseHandle: psHandleBase: 0x%x, hKernelMemInfo: 0x%x", (unsigned int)psPerProc->psHandleBase, (unsigned int)psUnwrapExtMemIN->hKernelMemInfo));
return 0;
}
return 0;
}
#endif
@ -1450,8 +1446,7 @@ PVRSRVMapIonHandleBW(IMG_UINT32 ui32BridgeID,
psMapIonOUT->eError = PVRSRVMapIonHandleKM(psPerProc,
psMapIonIN->hDevCookie,
psMapIonIN->hDevMemHeap,
psMapIonIN->ui32NumFDs,
psMapIonIN->ai32BufferFDs,
psMapIonIN->handle,
psMapIonIN->ui32Attribs,
psMapIonIN->ui32ChunkCount,
psMapIonIN->auiOffset,
@ -1546,7 +1541,7 @@ PVRSRVUnmapIonHandleBW(IMG_UINT32 ui32BridgeID,
if(psUnmapIonOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapIonHandleBW: PVRSRVLookupHandle failed %d",psUnmapIonOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapIonHandleBW: PVRSRVLookupHandle failed %d", psUnmapIonOUT->eError));
return 0;
}
@ -1554,7 +1549,7 @@ PVRSRVUnmapIonHandleBW(IMG_UINT32 ui32BridgeID,
if(psUnmapIonOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapIonHandleBW: PVRSRVUnmapIonHandleKM failed %d",psUnmapIonOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapIonHandleBW: PVRSRVUnmapIonHandleKM failed %d", psUnmapIonOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapIonHandleKM: pvKernelMemInfo: 0x%x", (unsigned int)pvKernelMemInfo));
return 0;
}
@ -1565,10 +1560,11 @@ PVRSRVUnmapIonHandleBW(IMG_UINT32 ui32BridgeID,
PVRSRV_HANDLE_TYPE_MEM_INFO);
if(psUnmapIonOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapIonHandleBW: PVRSRVReleaseHandle failed %d",psUnmapIonOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVReleaseHandle: psHandleBase: 0x%x, psKernelMemInfo: 0x%x", (unsigned int)psPerProc->psHandleBase,(unsigned int)psUnmapIonIN->psKernelMemInfo));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapIonHandleBW: PVRSRVReleaseHandle failed %d", psUnmapIonOUT->eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVReleaseHandle: psHandleBase: 0x%x, psKernelMemInfo: 0x%x", (unsigned int)psPerProc->psHandleBase, (unsigned int)psUnmapIonIN->psKernelMemInfo));
return 0;
}
return 0;
}
#endif /* SUPPORT_ION */
@ -2896,35 +2892,34 @@ PVRSRVSwapToDCBufferBW(IMG_UINT32 ui32BridgeID,
static IMG_INT
PVRSRVSwapToDCBuffer2BW(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_BUFFER2 *psSwapDispClassBufferIN,
PVRSRV_BRIDGE_OUT_SWAP_DISPCLASS_TO_BUFFER2 *psSwapDispClassBufferOUT,
PVRSRV_BRIDGE_RETURN *psRetOUT,
PVRSRV_PER_PROCESS_DATA *psPerProc)
{
IMG_VOID *pvPrivData = IMG_NULL;
IMG_HANDLE hFence = IMG_NULL;
IMG_VOID *pvDispClassInfo;
IMG_VOID *pvSwapChain;
IMG_UINT32 i;
PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SWAP_DISPCLASS_TO_BUFFER2);
psSwapDispClassBufferOUT->eError =
psRetOUT->eError =
PVRSRVLookupHandle(psPerProc->psHandleBase,
&pvDispClassInfo,
psSwapDispClassBufferIN->hDeviceKM,
PVRSRV_HANDLE_TYPE_DISP_INFO);
if(psSwapDispClassBufferOUT->eError != PVRSRV_OK)
if(psRetOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVSwapToDCBuffer2BW: Failed to look up DISP_INFO handle"));
return 0;
}
psSwapDispClassBufferOUT->eError =
psRetOUT->eError =
PVRSRVLookupSubHandle(psPerProc->psHandleBase,
&pvSwapChain,
psSwapDispClassBufferIN->hSwapChain,
PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN,
psSwapDispClassBufferIN->hDeviceKM);
if(psSwapDispClassBufferOUT->eError != PVRSRV_OK)
if(psRetOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVSwapToDCBuffer2BW: Failed to look up DISP_BUFFER handle"));
return 0;
@ -2948,37 +2943,33 @@ PVRSRVSwapToDCBuffer2BW(IMG_UINT32 ui32BridgeID,
for (i = 0; i < psSwapDispClassBufferIN->ui32NumMemInfos; i++)
{
PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
psSwapDispClassBufferOUT->eError =
psRetOUT->eError =
PVRSRVLookupHandle(psPerProc->psHandleBase,
(IMG_PVOID *)&psKernelMemInfo,
psSwapDispClassBufferIN->ppsKernelMemInfos[i],
PVRSRV_HANDLE_TYPE_MEM_INFO);
if(psSwapDispClassBufferOUT->eError != PVRSRV_OK)
if(psRetOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVSwapToDCBuffer2BW: Failed to look up MEM_INFO handle"));
return 0;
}
psSwapDispClassBufferIN->ppsKernelMemInfos[i] = psKernelMemInfo;
#if !defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
psRetOUT->eError =
PVRSRVLookupHandle(psPerProc->psHandleBase,
(IMG_PVOID *)&psKernelSyncInfo,
psSwapDispClassBufferIN->ppsKernelSyncInfos[i],
PVRSRV_HANDLE_TYPE_SYNC_INFO);
if(psRetOUT->eError != PVRSRV_OK)
{
PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
psSwapDispClassBufferOUT->eError =
PVRSRVLookupHandle(psPerProc->psHandleBase,
(IMG_PVOID *)&psKernelSyncInfo,
psSwapDispClassBufferIN->ppsKernelSyncInfos[i],
PVRSRV_HANDLE_TYPE_SYNC_INFO);
if(psSwapDispClassBufferOUT->eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVSwapToDCBuffer2BW: Failed to look up SYNC_INFO handle"));
return 0;
}
psSwapDispClassBufferIN->ppsKernelSyncInfos[i] = psKernelSyncInfo;
PVR_DPF((PVR_DBG_ERROR, "PVRSRVSwapToDCBuffer2BW: Failed to look up SYNC_INFO handle"));
return 0;
}
#endif /* !defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */
psSwapDispClassBufferIN->ppsKernelMemInfos[i] = psKernelMemInfo;
psSwapDispClassBufferIN->ppsKernelSyncInfos[i] = psKernelSyncInfo;
}
if(psSwapDispClassBufferIN->ui32PrivDataLength > 0)
@ -3006,7 +2997,7 @@ PVRSRVSwapToDCBuffer2BW(IMG_UINT32 ui32BridgeID,
}
}
psSwapDispClassBufferOUT->eError =
psRetOUT->eError =
PVRSRVSwapToDCBuffer2KM(pvDispClassInfo,
pvSwapChain,
psSwapDispClassBufferIN->ui32SwapInterval,
@ -3014,31 +3005,15 @@ PVRSRVSwapToDCBuffer2BW(IMG_UINT32 ui32BridgeID,
psSwapDispClassBufferIN->ppsKernelSyncInfos,
psSwapDispClassBufferIN->ui32NumMemInfos,
pvPrivData,
psSwapDispClassBufferIN->ui32PrivDataLength,
&hFence);
psSwapDispClassBufferIN->ui32PrivDataLength);
if(psSwapDispClassBufferOUT->eError != PVRSRV_OK)
if(psRetOUT->eError != PVRSRV_OK)
{
OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
psSwapDispClassBufferIN->ui32PrivDataLength,
pvPrivData, IMG_NULL);
}
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
if(hFence)
{
struct sync_fence *psFence = hFence;
int fd = get_unused_fd();
sync_fence_install(psFence, fd);
psSwapDispClassBufferOUT->hFence = (IMG_HANDLE)fd;
}
else
#endif /* defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */
{
psSwapDispClassBufferOUT->hFence = (IMG_HANDLE)-1;
}
return 0;
}

84
drivers/gpu/pvr/services4/srvkm/bridged/sgx/bridged_sgx_bridge.c
View file

@ -335,7 +335,6 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
return 0;
}
#if !defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
for(i=0; i<psDoKickIN->sCCBKick.ui32NumSrcSyncs; i++)
{
psRetOUT->eError =
@ -349,8 +348,7 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
return 0;
}
}
#endif /* !defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */
#endif /* defined(SUPPORT_SGX_GENERALISED_SYNCOBJECTS) */
#endif/* #if defined(SUPPORT_SGX_GENERALISED_SYNCOBJECTS) */
if (psDoKickIN->sCCBKick.ui32NumTAStatusVals > SGX_MAX_TA_STATUS_VALS)
{
@ -989,7 +987,6 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
IMG_BOOL bReleaseFailed = IMG_FALSE;
IMG_HANDLE hDummy;
IMG_UINT32 i;
IMG_VOID *pCommands = IMG_NULL;
PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_DEVINITPART2);
@ -1012,40 +1009,6 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
return 0;
}
/* Copy debug script commands from UM to KM */
for(i = 0; i < SGX_FEATURE_MP_CORE_COUNT_3D; i++)
{
/* Allocate memory in KM */
psSGXDevInitPart2OUT->eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
SGX_MAX_PRINT_COMMANDS * sizeof(SGX_INIT_COMMAND),
(IMG_VOID **) &pCommands,
0,
"debug script commands kernel copy");
if(psSGXDevInitPart2OUT->eError != PVRSRV_OK)
{
return 0;
}
/* Copy commands */
if(CopyFromUserWrapper(psPerProc,
ui32BridgeID,
pCommands,
psSGXDevInitPart2IN->sInitInfo.sScripts.apsSGXREGDebugCommandsPart2[i],
SGX_MAX_PRINT_COMMANDS * sizeof(SGX_INIT_COMMAND)) != PVRSRV_OK)
{
OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
SGX_MAX_PRINT_COMMANDS * sizeof(SGX_INIT_COMMAND),
pCommands,
0);
return -EFAULT;
}
/* update pointer */
psSGXDevInitPart2IN->sInitInfo.sScripts.apsSGXREGDebugCommandsPart2[i] = pCommands;
}
/* Check all the meminfo handles */
eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
&hDummy,
@ -1222,6 +1185,25 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
}
#endif
#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31559)
eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
&hDummy,
psSGXDevInitPart2IN->sInitInfo.hKernelVDMSnapShotBufferMemInfo,
PVRSRV_HANDLE_TYPE_MEM_INFO);
if (eError != PVRSRV_OK)
{
bLookupFailed = IMG_TRUE;
}
eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
&hDummy,
psSGXDevInitPart2IN->sInitInfo.hKernelVDMCtrlStreamBufferMemInfo,
PVRSRV_HANDLE_TYPE_MEM_INFO);
if (eError != PVRSRV_OK)
{
bLookupFailed = IMG_TRUE;
}
#endif
#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && \
defined(FIX_HW_BRN_33657) && defined(SUPPORT_SECURE_33657_FIX)
eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
@ -1446,6 +1428,25 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
bReleaseFailed = IMG_TRUE;
}
#endif
#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31559)
eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
&psSGXDevInitPart2IN->sInitInfo.hKernelVDMSnapShotBufferMemInfo,
psSGXDevInitPart2IN->sInitInfo.hKernelVDMSnapShotBufferMemInfo,
PVRSRV_HANDLE_TYPE_MEM_INFO);
if (eError != PVRSRV_OK)
{
bReleaseFailed = IMG_TRUE;
}
eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
&psSGXDevInitPart2IN->sInitInfo.hKernelVDMCtrlStreamBufferMemInfo,
psSGXDevInitPart2IN->sInitInfo.hKernelVDMCtrlStreamBufferMemInfo,
PVRSRV_HANDLE_TYPE_MEM_INFO);
if (eError != PVRSRV_OK)
{
bReleaseFailed = IMG_TRUE;
}
#endif
#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && \
defined(FIX_HW_BRN_33657) && defined(SUPPORT_SECURE_33657_FIX)
eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
@ -1589,6 +1590,13 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
#endif
#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31559)
eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelVDMSnapShotBufferMemInfo);
bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelVDMCtrlStreamBufferMemInfo);
bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
#endif
#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && \
defined(FIX_HW_BRN_33657) && defined(SUPPORT_SECURE_33657_FIX)
eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelVDMStateUpdateBufferMemInfo);

55
drivers/gpu/pvr/services4/srvkm/common/buffer_manager.c
View file

@ -122,7 +122,7 @@ AllocMemory (BM_CONTEXT *pBMContext,
RA_ARENA *pArena = IMG_NULL;
PVR_DPF ((PVR_DBG_MESSAGE,
"AllocMemory (uSize=0x%" SIZE_T_FMT_LEN "x, ui32Flags=0x%x, align=0x%x)",
"AllocMemory (uSize=0x%x, ui32Flags=0x%x, align=0x%x)",
uSize, ui32Flags, uDevVAddrAlignment));
/*
@ -228,7 +228,7 @@ AllocMemory (BM_CONTEXT *pBMContext,
ui32PrivDataLength,
(IMG_UINTPTR_T *)&(pBuf->DevVAddr.uiAddr)))
{
PVR_DPF((PVR_DBG_ERROR, "AllocMemory: RA_Alloc(0x%" SIZE_T_FMT_LEN "x) FAILED", uSize));
PVR_DPF((PVR_DBG_ERROR, "AllocMemory: RA_Alloc(0x%x) FAILED", uSize));
return IMG_FALSE;
}
}
@ -322,7 +322,7 @@ AllocMemory (BM_CONTEXT *pBMContext,
(IMG_PVOID *)&pMapping, IMG_NULL,
"Buffer Manager Mapping") != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "AllocMemory: OSAllocMem(0x%" SIZE_T_FMT_LEN "x) FAILED", sizeof(*pMapping)));
PVR_DPF((PVR_DBG_ERROR, "AllocMemory: OSAllocMem(0x%x) FAILED", sizeof(*pMapping)));
return IMG_FALSE;
}
@ -349,7 +349,7 @@ AllocMemory (BM_CONTEXT *pBMContext,
/* output some stats */
PVR_DPF ((PVR_DBG_MESSAGE,
"AllocMemory: pMapping=%p: DevV=%08X CpuV=%p CpuP=" CPUPADDR_FMT " uSize=0x%" SIZE_T_FMT_LEN "x",
"AllocMemory: pMapping=%p: DevV=%08X CpuV=%p CpuP=" CPUPADDR_FMT " uSize=0x%x",
pMapping,
pMapping->DevVAddr.uiAddr,
pMapping->CpuVAddr,
@ -357,7 +357,7 @@ AllocMemory (BM_CONTEXT *pBMContext,
pMapping->uSize));
PVR_DPF ((PVR_DBG_MESSAGE,
"AllocMemory: pBuf=%p: DevV=%08X CpuV=%p CpuP=" CPUPADDR_FMT " uSize=0x%" SIZE_T_FMT_LEN "x",
"AllocMemory: pBuf=%p: DevV=%08X CpuV=%p CpuP=" CPUPADDR_FMT " uSize=0x%x",
pBuf,
pBuf->DevVAddr.uiAddr,
pBuf->CpuVAddr,
@ -410,8 +410,8 @@ WrapMemory (BM_HEAP *psBMHeap,
IMG_UINT32 ui32Attribs = ui32Flags & ~(PVRSRV_MEM_READ | PVRSRV_MEM_WRITE);
PVR_DPF ((PVR_DBG_MESSAGE,
"WrapMemory(psBMHeap=%p, size=0x%" SIZE_T_FMT_LEN "x, offset=0x%" SIZE_T_FMT_LEN
"x, bPhysContig=0x%x, sysPAddr=0x" SYSPADDR_FMT ", pvCPUVAddr = 0x%p, flags=0x%x)",
"WrapMemory(psBMHeap=%p, size=0x%x, offset=0x%x\
, bPhysContig=0x%x, sysPAddr=0x%x, pvCPUVAddr = 0x%p, flags=0x%x)",
psBMHeap,
uSize,
uiBaseOffset,
@ -433,7 +433,7 @@ WrapMemory (BM_HEAP *psBMHeap,
(IMG_PVOID *)&pMapping, IMG_NULL,
"Mocked-up mapping") != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "WrapMemory: OSAllocMem(0x%" SIZE_T_FMT_LEN "x) FAILED", sizeof(*pMapping)));
PVR_DPF((PVR_DBG_ERROR, "WrapMemory: OSAllocMem(0x%x) FAILED", sizeof(*pMapping)));
return IMG_FALSE;
}
@ -458,7 +458,7 @@ WrapMemory (BM_HEAP *psBMHeap,
ui32Attribs,
&pMapping->hOSMemHandle) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "WrapMemory: OSRegisterMem Phys=0x" CPUPADDR_FMT ", Size=%" SIZE_T_FMT_LEN "u) failed",
PVR_DPF((PVR_DBG_ERROR, "WrapMemory: OSRegisterMem Phys=0x" CPUPADDR_FMT ", Size=%u) failed",
pMapping->CpuPAddr.uiAddr, pMapping->uSize));
goto fail_cleanup;
}
@ -474,7 +474,7 @@ WrapMemory (BM_HEAP *psBMHeap,
ui32Attribs,
&pMapping->hOSMemHandle) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "WrapMemory: OSRegisterDiscontigMem Size=0x%" SIZE_T_FMT_LEN "u) failed",
PVR_DPF((PVR_DBG_ERROR, "WrapMemory: OSRegisterDiscontigMem Size=0x%u) failed",
pMapping->uSize));
goto fail_cleanup;
}
@ -529,7 +529,7 @@ WrapMemory (BM_HEAP *psBMHeap,
if (!bResult)
{
PVR_DPF((PVR_DBG_ERROR,
"WrapMemory: DevMemoryAlloc(0x%" SIZE_T_FMT_LEN "x) failed",
"WrapMemory: DevMemoryAlloc(0x%x) failed",
pMapping->uSize));
goto fail_cleanup;
}
@ -573,10 +573,10 @@ WrapMemory (BM_HEAP *psBMHeap,
PVR_DPF ((PVR_DBG_MESSAGE, "DevVaddr.uiAddr=%08X", DevVAddr.uiAddr));
PVR_DPF ((PVR_DBG_MESSAGE,
"WrapMemory: DevV=%08X CpuP=" CPUPADDR_FMT " uSize=0x%" SIZE_T_FMT_LEN "x",
"WrapMemory: DevV=%08X CpuP=" CPUPADDR_FMT " uSize=0x%x",
pMapping->DevVAddr.uiAddr, pMapping->CpuPAddr.uiAddr, pMapping->uSize));
PVR_DPF ((PVR_DBG_MESSAGE,
"WrapMemory: DevV=%08X CpuP=" CPUPADDR_FMT " uSize=0x%" SIZE_T_FMT_LEN "x",
"WrapMemory: DevV=%08X CpuP=" CPUPADDR_FMT " uSize=0x%x",
pBuf->DevVAddr.uiAddr, pBuf->CpuPAddr.uiAddr, uSize));
pBuf->pMapping = pMapping;
@ -1033,7 +1033,7 @@ static PVRSRV_ERROR BM_DestroyContextCallBack(IMG_PVOID pvParam,
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "BM_DestroyContextCallBack: BM_DestroyContextCallBack_AnyVaCb failed 0x%x", eError));
PVR_DPF((PVR_DBG_ERROR, "BM_DestroyContextCallBack: psBMHeap: 0x%x, psDeviceNode: 0x%x",(unsigned int)pBMContext->psBMHeap, (unsigned int)psDeviceNode));
PVR_DPF((PVR_DBG_ERROR, "BM_DestroyContextCallBack: psBMHeap: 0x%x, psDeviceNode: 0x%x", (unsigned int)pBMContext->psBMHeap, (unsigned int)psDeviceNode));
return eError;
}
/*
@ -1554,7 +1554,7 @@ BM_Alloc ( IMG_HANDLE hDevMemHeap,
ui32Flags = *pui32Flags;
PVR_DPF ((PVR_DBG_MESSAGE,
"BM_Alloc (uSize=0x%" SIZE_T_FMT_LEN "x, ui32Flags=0x%x, uDevVAddrAlignment=0x%x)",
"BM_Alloc (uSize=0x%x, ui32Flags=0x%x, uDevVAddrAlignment=0x%x)",
uSize, ui32Flags, uDevVAddrAlignment));
SysAcquireData(&psSysData);
@ -1604,7 +1604,7 @@ BM_Alloc ( IMG_HANDLE hDevMemHeap,
}
PVR_DPF ((PVR_DBG_MESSAGE,
"BM_Alloc (uSize=0x%" SIZE_T_FMT_LEN "x, ui32Flags=0x%x)",
"BM_Alloc (uSize=0x%x, ui32Flags=0x%x)",
uSize, ui32Flags));
/*
@ -1770,8 +1770,8 @@ BM_Wrap ( IMG_HANDLE hDevMemHeap,
}
PVR_DPF ((PVR_DBG_MESSAGE,
"BM_Wrap (uSize=0x%" SIZE_T_FMT_LEN "x, uOffset=0x%" SIZE_T_FMT_LEN
"x, bPhysContig=0x%x, syspAddr=0x" SYSPADDR_FMT ", pvCPUVAddr=0x%p, ui32Flags=0x%x)",
"BM_Wrap (uSize=0x%x, uOffset=0x%x \
, bPhysContig=0x%x, syspAddr=0x%x, pvCPUVAddr=0x%p, ui32Flags=0x%x)",
uSize,
uOffset,
bPhysContig,
@ -1822,7 +1822,7 @@ BM_Wrap ( IMG_HANDLE hDevMemHeap,
pBuf->pMapping->eCpuMemoryOrigin == hm_wrapped_virtaddr))
{
PVR_DPF((PVR_DBG_MESSAGE,
"BM_Wrap (Matched previous Wrap! uSize=0x%" SIZE_T_FMT_LEN "x, uOffset=0x%" SIZE_T_FMT_LEN "x, SysAddr=" SYSPADDR_FMT ")",
"BM_Wrap (Matched previous Wrap! uSize=0x%x, uOffset=0x%x, SysAddr=" SYSPADDR_FMT ")",
uSize,
uOffset,
sHashAddress.uiAddr));
@ -1883,7 +1883,7 @@ BM_Wrap ( IMG_HANDLE hDevMemHeap,
}
PVR_DPF ((PVR_DBG_MESSAGE,
"BM_Wrap (uSize=0x%" SIZE_T_FMT_LEN "x, ui32Flags=0x%x, devVAddr=%08X)",
"BM_Wrap (uSize=0x%x, ui32Flags=0x%x, devVAddr=%08X)",
uSize, ui32Flags, pBuf->DevVAddr.uiAddr));
/*
@ -2073,7 +2073,7 @@ BM_HandleToSysPaddr (BM_HANDLE hBuf)
return PhysAddr;
}
PVR_DPF ((PVR_DBG_MESSAGE, "BM_HandleToSysPaddr(h=0lx%p)=" CPUPADDR_FMT, hBuf, pBuf->CpuPAddr.uiAddr));
PVR_DPF ((PVR_DBG_MESSAGE, "BM_HandleToSysPaddr(h=0x%p)=" CPUPADDR_FMT, hBuf, pBuf->CpuPAddr.uiAddr));
return SysCpuPAddrToSysPAddr (pBuf->CpuPAddr);
}
@ -2717,8 +2717,7 @@ BM_ImportMemory (IMG_VOID *pH,
IMG_SIZE_T uDevVAddrAlignment = 0; /* ? */
PVR_DPF ((PVR_DBG_MESSAGE,
"BM_ImportMemory (pBMContext=0x%p, uRequestSize=0x%" SIZE_T_FMT_LEN
"x, ui32Flags=0x%x, uAlign=0x%" SIZE_T_FMT_LEN "x)",
"BM_ImportMemory (pBMContext=0x%p, uRequestSize=0x%x, ui32Flags=0x%x, uAlign=0x%x)",
pBMContext, uRequestSize, ui32Flags, uDevVAddrAlignment));
PVR_ASSERT (ppsMapping != IMG_NULL);
@ -2818,7 +2817,7 @@ BM_ImportMemory (IMG_VOID *pH,
&pMapping->hOSMemHandle) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,
"BM_ImportMemory: XProcWorkaroundAllocShareable(0x%" SIZE_T_FMT_LEN "x) failed",
"BM_ImportMemory: XProcWorkaroundAllocShareable(0x%x) failed",
uPSize));
goto fail_mapping_alloc;
}
@ -2862,7 +2861,7 @@ BM_ImportMemory (IMG_VOID *pH,
&pMapping->hOSMemHandle) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,
"BM_ImportMemory: XProcWorkaroundAllocShareable(0x%" SIZE_T_FMT_LEN "x) failed",
"BM_ImportMemory: XProcWorkaroundAllocShareable(0x%x) failed",
uPSize));
goto fail_mapping_alloc;
}
@ -2922,7 +2921,7 @@ BM_ImportMemory (IMG_VOID *pH,
&pMapping->hOSMemHandle) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,
"BM_ImportMemory: OSAllocPages(0x%" SIZE_T_FMT_LEN "x) failed",
"BM_ImportMemory: OSAllocPages(0x%x) failed",
uPSize));
goto fail_mapping_alloc;
}
@ -2964,7 +2963,7 @@ BM_ImportMemory (IMG_VOID *pH,
ui32PrivDataLength,
(IMG_UINTPTR_T *)&sSysPAddr.uiAddr))
{
PVR_DPF((PVR_DBG_ERROR, "BM_ImportMemory: RA_Alloc(0x%" SIZE_T_FMT_LEN "x) FAILED", uPSize));
PVR_DPF((PVR_DBG_ERROR, "BM_ImportMemory: RA_Alloc(0x%x) FAILED", uPSize));
goto fail_mapping_alloc;
}
@ -3004,7 +3003,7 @@ BM_ImportMemory (IMG_VOID *pH,
if (!bResult)
{
PVR_DPF((PVR_DBG_ERROR,
"BM_ImportMemory: DevMemoryAlloc(0x%" SIZE_T_FMT_LEN "x) failed",
"BM_ImportMemory: DevMemoryAlloc(0x%x) failed",
pMapping->uSize));
goto fail_dev_mem_alloc;
}

233
drivers/gpu/pvr/services4/srvkm/common/deviceclass.c
View file

@ -1,5 +1,4 @@
/*************************************************************************/ /*!
@File
@Title Device class services functions
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
@Description Kernel services functions for device class devices
@ -51,13 +50,13 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "lists.h"
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
#include "pvr_sync.h"
#endif
PVRSRV_ERROR AllocateDeviceID(SYS_DATA *psSysData, IMG_UINT32 *pui32DevID);
PVRSRV_ERROR FreeDeviceID(SYS_DATA *psSysData, IMG_UINT32 ui32DevID);
#if defined(SUPPORT_MISR_IN_THREAD)
void OSVSyncMISR(IMG_HANDLE, IMG_BOOL);
#endif
#if defined(SUPPORT_CUSTOM_SWAP_OPERATIONS)
IMG_VOID PVRSRVFreeCommandCompletePacketKM(IMG_HANDLE hCmdCookie,
IMG_BOOL bScheduleMISR);
@ -741,13 +740,11 @@ PVRSRV_ERROR PVRSRVCloseDCDeviceKM (IMG_HANDLE hDeviceKM)
/* Remove the item from the resman list and trigger the callback. */
eError = ResManFreeResByPtr(psDCPerContextInfo->hResItem, CLEANUP_WITH_POLL);
if(eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVCloseDCDeviceKM: ResManFreeResByPtr failed %d",eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVCloseDCDeviceKM: ResManFreeResByPtr failed %d", eError));
PVR_DPF((PVR_DBG_ERROR, "ResManFreeResByPtr: hResItem 0x%x", (unsigned int)psDCPerContextInfo->hResItem));
}
return eError;
}
@ -1110,10 +1107,9 @@ PVRSRV_ERROR PVRSRVDestroyDCSwapChainKM(IMG_HANDLE hSwapChainRef)
psSwapChainRef = hSwapChainRef;
eError = ResManFreeResByPtr(psSwapChainRef->hResItem, CLEANUP_WITH_POLL);
if(eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVDestroyDCSwapChainKM: ResManFreeResByPtr failed %d",eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVDestroyDCSwapChainKM: ResManFreeResByPtr failed %d", eError));
PVR_DPF((PVR_DBG_ERROR, "ResManFreeResByPtr: hResItem 0x%x", (unsigned int)psSwapChainRef->hResItem));
}
return eError;
@ -1175,14 +1171,6 @@ static PVRSRV_ERROR DestroyDCSwapChain(PVRSRV_DC_SWAPCHAIN *psSwapChain)
#if !defined(SUPPORT_DC_CMDCOMPLETE_WHEN_NO_LONGER_DISPLAYED)
if (psSwapChain->ppsLastSyncInfos)
{
for (i = 0; i < psSwapChain->ui32LastNumSyncInfos; i++)
{
if (psSwapChain->ppsLastSyncInfos[i])
{
PVRSRVKernelSyncInfoDecRef(psSwapChain->ppsLastSyncInfos[i], IMG_NULL);
psSwapChain->ppsLastSyncInfos[i] = IMG_NULL;
}
}
OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(PVRSRV_KERNEL_SYNC_INFO *) * psSwapChain->ui32LastNumSyncInfos,
psSwapChain->ppsLastSyncInfos, IMG_NULL);
}
@ -1222,7 +1210,7 @@ static PVRSRV_ERROR DestroyDCSwapChainRefCallBack(IMG_PVOID pvParam,
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "DestroyDCSwapChainRefCallBack: DestroyDCSwapChain Failed %d", eError));
PVR_DPF((PVR_DBG_ERROR, "DestroyDCSwapChainRefCallBack: psSwapChain 0x%x",(unsigned int)psSwapChainRef->psSwapChain));
PVR_DPF((PVR_DBG_ERROR, "DestroyDCSwapChainRefCallBack: psSwapChain 0x%x", (unsigned int)psSwapChainRef->psSwapChain));
}
}
@ -1272,6 +1260,7 @@ static PVRSRV_ERROR PVRSRVCreateDCSwapChainRefKM(PVRSRV_PER_PROCESS_DATA *psPerP
psSwapChainRef,
0,
&DestroyDCSwapChainRefCallBack);
*ppsSwapChainRef = psSwapChainRef;
return PVRSRV_OK;
@ -1298,6 +1287,7 @@ PVRSRV_ERROR PVRSRVCreateDCSwapChainKM (PVRSRV_PER_PROCESS_DATA *psPerProc,
IMG_UINT32 i;
DISPLAY_INFO sDisplayInfo;
if(!hDeviceKM
|| !psDstSurfAttrib
|| !psSrcSurfAttrib
@ -1308,14 +1298,18 @@ PVRSRV_ERROR PVRSRVCreateDCSwapChainKM (PVRSRV_PER_PROCESS_DATA *psPerProc,
return PVRSRV_ERROR_INVALID_PARAMS;
}
OSMemSet (apsSyncData, 0, sizeof(PVRSRV_SYNC_DATA *) * PVRSRV_MAX_DC_SWAPCHAIN_BUFFERS);
if (ui32BufferCount > PVRSRV_MAX_DC_SWAPCHAIN_BUFFERS)
{
PVR_DPF((PVR_DBG_ERROR,"PVRSRVCreateDCSwapChainKM: Too many buffers"));
return PVRSRV_ERROR_TOOMANYBUFFERS;
}
if (ui32BufferCount < 2)
{
PVR_DPF((PVR_DBG_ERROR,"PVRSRVCreateDCSwapChainKM: Too few buffers"));
return PVRSRV_ERROR_TOO_FEW_BUFFERS;
}
psDCInfo = DCDeviceHandleToDCInfo(hDeviceKM);
if( ui32Flags & PVRSRV_CREATE_SWAPCHAIN_QUERY )
@ -1445,7 +1439,7 @@ PVRSRV_ERROR PVRSRVCreateDCSwapChainKM (PVRSRV_PER_PROCESS_DATA *psPerProc,
psSwapChain->ui32RefCount = 1;
psSwapChain->ui32Flags = ui32Flags;
/* Save pointer in DC structure if it's shared struct */
/* Save pointer in DC structure if ti's shared struct */
if( ui32Flags & PVRSRV_CREATE_SWAPCHAIN_SHARED )
{
if(! psDCInfo->psDCSwapChainShared )
@ -1708,7 +1702,6 @@ PVRSRV_ERROR PVRSRVSwapToDCBufferKM(IMG_HANDLE hDeviceKM,
apsSrcSync,
sizeof(DISPLAYCLASS_FLIP_COMMAND) + (sizeof(IMG_RECT) * ui32ClipRectCount),
IMG_NULL,
IMG_NULL,
IMG_NULL);
if(eError != PVRSRV_OK)
{
@ -1828,26 +1821,20 @@ PVRSRV_ERROR PVRSRVSwapToDCBuffer2KM(IMG_HANDLE hDeviceKM,
PVRSRV_KERNEL_SYNC_INFO **ppsSyncInfos,
IMG_UINT32 ui32NumMemSyncInfos,
IMG_PVOID pvPrivData,
IMG_UINT32 ui32PrivDataLength,
IMG_HANDLE *phFence)
IMG_UINT32 ui32PrivDataLength)
{
IMG_UINT32 ui32NumSyncInfos = ui32NumMemSyncInfos;
PVRSRV_KERNEL_SYNC_INFO **ppsCompiledSyncInfos;
IMG_UINT32 i, ui32NumCompiledSyncInfos;
DISPLAYCLASS_FLIP_COMMAND2 *psFlipCmd;
PVRSRV_DISPLAYCLASS_INFO *psDCInfo;
PVRSRV_DC_SWAPCHAIN *psSwapChain;
PVRSRV_ERROR eError = PVRSRV_OK;
CALLBACK_DATA *psCallbackData;
PVRSRV_QUEUE_INFO *psQueue;
PVRSRV_COMMAND *psCommand;
IMG_PVOID *ppvMemInfos;
PVRSRV_ERROR eError;
SYS_DATA *psSysData;
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
struct sync_fence *apsFence[SGX_MAX_SRC_SYNCS_TA];
#endif /* defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */
if(!hDeviceKM || !hSwapChain || !ppsMemInfos || !ppsSyncInfos || ui32NumMemSyncInfos < 1)
{
PVR_DPF((PVR_DBG_ERROR,"PVRSRVSwapToDCBuffer2KM: Invalid parameters"));
@ -1896,15 +1883,6 @@ PVRSRV_ERROR PVRSRVSwapToDCBuffer2KM(IMG_HANDLE hDeviceKM,
psCallbackData->ppvMemInfos = ppvMemInfos;
psCallbackData->ui32NumMemInfos = ui32NumMemSyncInfos;
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
eError = PVRSyncFencesToSyncInfos(ppsSyncInfos, &ui32NumSyncInfos, apsFence);
if(eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PVRSRVSwapToDCBuffer2KM: PVRSyncFencesToSyncInfos failed"));
goto Exit;
}
#endif /* defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */
/* get the queue from the buffer structure */
psQueue = psSwapChain->psQueue;
@ -1912,35 +1890,21 @@ PVRSRV_ERROR PVRSRVSwapToDCBuffer2KM(IMG_HANDLE hDeviceKM,
if(psSwapChain->ppsLastSyncInfos)
{
IMG_UINT32 ui32NumUniqueSyncInfos = psSwapChain->ui32LastNumSyncInfos;
IMG_BOOL *abUnique;
IMG_UINT32 j;
if(OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
sizeof(IMG_BOOL) * psSwapChain->ui32LastNumSyncInfos,
(IMG_VOID **)&abUnique, IMG_NULL,
"Unique booleans") != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PVRSRVSwapToDCBuffer2KM: Failed to allocate space for unique booleans"));
goto Exit;
}
for(j = 0; j < psSwapChain->ui32LastNumSyncInfos; j++)
{
abUnique[j] = IMG_TRUE;
for(i = 0; i < ui32NumSyncInfos; i++)
for(i = 0; i < ui32NumMemSyncInfos; i++)
{
PVR_ASSERT(psSwapChain->ppsLastSyncInfos[j]);
PVR_ASSERT(ppsSyncInfos[i]);
if(psSwapChain->ppsLastSyncInfos[j] == ppsSyncInfos[i])
{
abUnique[j] = IMG_FALSE;
psSwapChain->ppsLastSyncInfos[j] = IMG_NULL;
ui32NumUniqueSyncInfos--;
break;
}
}
}
ui32NumCompiledSyncInfos = ui32NumSyncInfos + ui32NumUniqueSyncInfos;
ui32NumCompiledSyncInfos = ui32NumMemSyncInfos + ui32NumUniqueSyncInfos;
if(OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
sizeof(PVRSRV_KERNEL_SYNC_INFO *) * ui32NumCompiledSyncInfos,
@ -1948,108 +1912,24 @@ PVRSRV_ERROR PVRSRVSwapToDCBuffer2KM(IMG_HANDLE hDeviceKM,
"Compiled syncinfos") != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PVRSRVSwapToDCBuffer2KM: Failed to allocate space for meminfo list"));
OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
sizeof(IMG_BOOL) * psSwapChain->ui32LastNumSyncInfos,
(IMG_VOID *)abUnique, IMG_NULL);
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
for(i = 0; apsFence[i]; i++)
if(apsFence[i])
sync_fence_put(apsFence[i]);
#endif
goto Exit;
}
OSMemCopy(ppsCompiledSyncInfos, ppsSyncInfos, sizeof(PVRSRV_KERNEL_SYNC_INFO *) * ui32NumSyncInfos);
for(j = 0, i = ui32NumSyncInfos; j < psSwapChain->ui32LastNumSyncInfos; j++)
OSMemCopy(ppsCompiledSyncInfos, ppsSyncInfos, sizeof(PVRSRV_KERNEL_SYNC_INFO *) * ui32NumMemSyncInfos);
for(j = 0, i = ui32NumMemSyncInfos; j < psSwapChain->ui32LastNumSyncInfos; j++)
{
if(abUnique[j])
if(psSwapChain->ppsLastSyncInfos[j])
{
ppsCompiledSyncInfos[i] = psSwapChain->ppsLastSyncInfos[j];
i++;
}
}
OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
sizeof(IMG_BOOL) * psSwapChain->ui32LastNumSyncInfos,
(IMG_VOID *)abUnique, IMG_NULL);
}
else
#endif /* !defined(SUPPORT_DC_CMDCOMPLETE_WHEN_NO_LONGER_DISPLAYED) */
{
IMG_UINT32 j, ui32Missing = 0;
/* Older synchronization schemes would just pass down the syncinfos
* hanging off of the meminfos. So we would expect identical lists.
* However, newer drivers may send down additional synchronization
* i.e. for TQ fence operations. In such a case we need to allocate
* more space for the compiled syncinfos to ensure everything is
* ROP2 synchronized.
*/
for(j = 0; j < ui32NumSyncInfos; j++)
{
IMG_BOOL bFound = IMG_FALSE;
for(i = 0; i < ui32NumSyncInfos; i++)
{
if(ppsSyncInfos[j] == ppsMemInfos[i]->psKernelSyncInfo)
{
bFound = IMG_TRUE;
break;
}
}
if(!bFound)
ui32Missing++;
}
if(ui32Missing)
{
IMG_UINT32 k;
ui32NumCompiledSyncInfos = ui32NumSyncInfos + ui32Missing;
if(OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
sizeof(PVRSRV_KERNEL_SYNC_INFO *) * ui32NumCompiledSyncInfos,
(IMG_VOID **)&ppsCompiledSyncInfos, IMG_NULL,
"Compiled syncinfos") != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PVRSRVSwapToDCBuffer2KM: Failed to allocate space for meminfo list"));
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
for(i = 0; apsFence[i]; i++)
if(apsFence[i])
sync_fence_put(apsFence[i]);
#endif
goto Exit;
}
for(i = 0; i < ui32NumSyncInfos; i++)
{
ppsCompiledSyncInfos[i] = ppsSyncInfos[i];
}
k = i;
for(i = 0; i < ui32NumSyncInfos; i++)
{
for(j = 0; j < ui32NumSyncInfos; j++)
{
if(ppsSyncInfos[j] == ppsMemInfos[i]->psKernelSyncInfo)
break;
}
if(j == ui32NumSyncInfos)
{
/* Insert the unique one */
PVR_ASSERT(k < ui32NumCompiledSyncInfos);
ppsCompiledSyncInfos[k] = ppsMemInfos[i]->psKernelSyncInfo;
k++;
}
}
}
else
{
ppsCompiledSyncInfos = ppsSyncInfos;
ui32NumCompiledSyncInfos = ui32NumSyncInfos;
}
ppsCompiledSyncInfos = ppsSyncInfos;
ui32NumCompiledSyncInfos = ui32NumMemSyncInfos;
}
/* insert the command (header) */
@ -2063,18 +1943,7 @@ PVRSRV_ERROR PVRSRVSwapToDCBuffer2KM(IMG_HANDLE hDeviceKM,
ppsCompiledSyncInfos,
sizeof(DISPLAYCLASS_FLIP_COMMAND2),
FreePrivateData,
psCallbackData,
phFence);
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
/* InsertCommand bumped the refcount on the raw sync objects, so we
* can put the fences now. Even if the fences are deleted, the syncs
* will persist.
*/
for(i = 0; apsFence[i]; i++)
if(apsFence[i])
sync_fence_put(apsFence[i]);
#endif
psCallbackData);
if (ppsCompiledSyncInfos != ppsSyncInfos)
{
@ -2142,11 +2011,6 @@ PVRSRV_ERROR PVRSRVSwapToDCBuffer2KM(IMG_HANDLE hDeviceKM,
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PVRSRVSwapToDCBuffer2KM: Failed to submit command"));
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
sync_fence_put(psCommand->pvCleanupFence);
sync_fence_put(*phFence);
*phFence = IMG_NULL;
#endif
goto Exit;
}
@ -2161,60 +2025,34 @@ PVRSRV_ERROR PVRSRVSwapToDCBuffer2KM(IMG_HANDLE hDeviceKM,
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PVRSRVSwapToDCBuffer2KM: Failed to schedule MISR"));
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
sync_fence_put(*phFence);
*phFence = IMG_NULL;
#endif
goto Exit;
}
#if !defined(SUPPORT_DC_CMDCOMPLETE_WHEN_NO_LONGER_DISPLAYED)
/* Reallocate the syncinfo list if it was too small */
if (psSwapChain->ui32LastNumSyncInfos < ui32NumSyncInfos)
if (psSwapChain->ui32LastNumSyncInfos < ui32NumMemSyncInfos)
{
if (psSwapChain->ppsLastSyncInfos)
{
for (i = 0; i < psSwapChain->ui32LastNumSyncInfos; i++)
{
if (psSwapChain->ppsLastSyncInfos[i])
{
PVRSRVKernelSyncInfoDecRef(psSwapChain->ppsLastSyncInfos[i], IMG_NULL);
psSwapChain->ppsLastSyncInfos[i] = IMG_NULL;
}
}
OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(PVRSRV_KERNEL_SYNC_INFO *) * psSwapChain->ui32LastNumSyncInfos,
psSwapChain->ppsLastSyncInfos, IMG_NULL);
}
if(OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
sizeof(PVRSRV_KERNEL_SYNC_INFO *) * ui32NumSyncInfos,
sizeof(PVRSRV_KERNEL_SYNC_INFO *) * ui32NumMemSyncInfos,
(IMG_VOID **)&psSwapChain->ppsLastSyncInfos, IMG_NULL,
"Last syncinfos") != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PVRSRVSwapToDCBuffer2KM: Failed to allocate space for meminfo list"));
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
sync_fence_put(*phFence);
*phFence = IMG_NULL;
#endif
goto Exit;
}
}
for (i = 0; i < psSwapChain->ui32LastNumSyncInfos; i++)
{
if (psSwapChain->ppsLastSyncInfos[i])
{
PVRSRVKernelSyncInfoDecRef(psSwapChain->ppsLastSyncInfos[i], IMG_NULL);
psSwapChain->ppsLastSyncInfos[i] = IMG_NULL;
}
}
psSwapChain->ui32LastNumSyncInfos = ui32NumMemSyncInfos;
psSwapChain->ui32LastNumSyncInfos = ui32NumSyncInfos;
for(i = 0; i < ui32NumSyncInfos; i++)
for(i = 0; i < ui32NumMemSyncInfos; i++)
{
psSwapChain->ppsLastSyncInfos[i] = ppsSyncInfos[i];
PVRSRVKernelSyncInfoIncRef(psSwapChain->ppsLastSyncInfos[i], IMG_NULL);
}
#endif /* !defined(SUPPORT_DC_CMDCOMPLETE_WHEN_NO_LONGER_DISPLAYED) */
@ -2315,7 +2153,6 @@ PVRSRV_ERROR PVRSRVSwapToDCSystemKM(IMG_HANDLE hDeviceKM,
apsSrcSync,
sizeof(DISPLAYCLASS_FLIP_COMMAND),
IMG_NULL,
IMG_NULL,
IMG_NULL);
if(eError != PVRSRV_OK)
{
@ -2543,7 +2380,11 @@ IMG_BOOL PVRGetDisplayClassJTable(PVRSRV_DC_DISP2SRV_KMJTABLE *psJTable)
psJTable->pfnPVRSRVOEMFunction = &SysOEMFunction;
psJTable->pfnPVRSRVRegisterCmdProcList = &PVRSRVRegisterCmdProcListKM;
psJTable->pfnPVRSRVRemoveCmdProcList = &PVRSRVRemoveCmdProcListKM;
psJTable->pfnPVRSRVCmdComplete = &PVRSRVCommandCompleteKM;
#if defined(SUPPORT_MISR_IN_THREAD)
psJTable->pfnPVRSRVCmdComplete = &OSVSyncMISR;
#else
psJTable->pfnPVRSRVCmdComplete = &PVRSRVCommandCompleteKM;
#endif
psJTable->pfnPVRSRVRegisterSystemISRHandler = &PVRSRVRegisterSystemISRHandler;
psJTable->pfnPVRSRVRegisterPowerDevice = &PVRSRVRegisterPowerDevice;
#if defined(SUPPORT_CUSTOM_SWAP_OPERATIONS)
@ -2583,7 +2424,7 @@ PVRSRV_ERROR PVRSRVCloseBCDeviceKM (IMG_HANDLE hDeviceKM)
eError = ResManFreeResByPtr(psBCPerContextInfo->hResItem, CLEANUP_WITH_POLL);
if(eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVCloseBCDeviceKM: ResManFreeResByPtr failed %d",eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVCloseBCDeviceKM: ResManFreeResByPtr failed %d", eError));
PVR_DPF((PVR_DBG_ERROR, "ResManFreeResByPtr: hResItem 0x%x", (unsigned int)psBCPerContextInfo->hResItem));
}
return eError;

88
drivers/gpu/pvr/services4/srvkm/common/devicemem.c
View file

@ -926,8 +926,8 @@ PVRSRV_ERROR FreeMemCallBackCommon(PVRSRV_KERNEL_MEM_INFO *psMemInfo,
eError = FreeDeviceMem2(psMemInfo, eCallbackOrigin);
if(eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "FreeMemCallBackCommon: FreeDeviceMem2 Failed %d",eError));
PVR_DPF((PVR_DBG_ERROR, "FreeMemCallBackCommon: psMemInfo: 0x%x, eCallbackOrigin: 0x%x",(unsigned int)psMemInfo, eCallbackOrigin));
PVR_DPF((PVR_DBG_ERROR, "FreeMemCallBackCommon: FreeDeviceMem2 Failed %d", eError));
PVR_DPF((PVR_DBG_ERROR, "FreeMemCallBackCommon: psMemInfo: 0x%x, eCallbackOrigin: 0x%x", (unsigned int)psMemInfo, eCallbackOrigin));
}
}
@ -995,7 +995,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVFreeDeviceMemKM(IMG_HANDLE hDevCookie,
eError = ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem, CLEANUP_WITH_POLL);
if(eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVFreeDeviceMemKM: ResManFreeResByPtr failed %d",eError));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVFreeDeviceMemKM: ResManFreeResByPtr failed %d", eError));
PVR_DPF((PVR_DBG_ERROR, "ResManFreeResByPtr: hResItem 0x%x", (unsigned int)psMemInfo->sMemBlk.hResItem));
}
}
@ -1005,8 +1005,8 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVFreeDeviceMemKM(IMG_HANDLE hDevCookie,
eError = FreeDeviceMemCallBack(psMemInfo, 0, CLEANUP_WITH_POLL);
if(eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVFreeDeviceMemKM: FreeDeviceMemCallBack failed %d",eError));
PVR_DPF((PVR_DBG_ERROR, "FreeDeviceMemCallBack: psMemInfo: 0x%x",(unsigned int)psMemInfo));
PVR_DPF((PVR_DBG_ERROR, "PVRSRVFreeDeviceMemKM: FreeDeviceMemCallBack failed %d", eError));
PVR_DPF((PVR_DBG_ERROR, "FreeDeviceMemCallBack: psMemInfo: 0x%x", (unsigned int)psMemInfo));
}
}
@ -1161,7 +1161,7 @@ PVRSRV_ERROR IMG_CALLCONV _PVRSRVAllocDeviceMemKM(IMG_HANDLE hDevCookie,
if (psMemInfo->sMemBlk.hResItem == IMG_NULL)
{
eError = PVRSRV_ERROR_OUT_OF_MEMORY;
PVR_DPF ((PVR_DBG_ERROR, "_PVRSRVAllocDeviceMemKM: ResManRegisterRes failed %d",eError));
PVR_DPF ((PVR_DBG_ERROR, "_PVRSRVAllocDeviceMemKM: ResManRegisterRes failed %d", eError));
goto free_mainalloc;
}
}
@ -1293,19 +1293,10 @@ IMG_VOID PVRSRVIonBufferSyncRelease(PVRSRV_ION_SYNC_INFO *psIonSyncInfo)
@Input psPerProc : PerProcess data
@Input hDevCookie : Device node cookie
@Input hDevMemHeap : Heap ion handles are mapped into
@Input ui32NumBuffers : Number of ion handles to map. (If one handle is being
mapped, this should be 1, not 0.)
@Input phIon : Array of ui32NumBuffers ion handles (fds)
@Input hDevMemContext : Device memory context cookie
@Input hIon : Handle to ION buffer
@Input ui32Flags : Mapping flags
@Input ui32ChunkCount : If ui32NumBuffers is 1, this is the number of
"chunks" specified to be mapped into device-virtual
address space. If ui32NumBuffers > 1, it is ignored.
@Input pauiOffset : Array of offsets in device-virtual address space to map
"chunks" of physical from the ion allocation.
@Input pauiSize : Array of sizes in bytes of device-virtual address space to
map "chunks" of physical from the ion allocation.
@Input puiIonBufferSize : Size in bytes of resulting device-virtual mapping.
@Input ui32Size : Mapping size
@Output ppsKernelMemInfo: Output kernel meminfo if successful
@Return PVRSRV_ERROR :
@ -1315,8 +1306,7 @@ IMG_EXPORT
PVRSRV_ERROR PVRSRVMapIonHandleKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
IMG_HANDLE hDevCookie,
IMG_HANDLE hDevMemHeap,
IMG_UINT32 ui32NumFDs,
IMG_INT32 *pi32BufferFDs,
IMG_HANDLE hIon,
IMG_UINT32 ui32Flags,
IMG_UINT32 ui32ChunkCount,
IMG_SIZE_T *pauiOffset,
@ -1347,7 +1337,7 @@ PVRSRV_ERROR PVRSRVMapIonHandleKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
PVR_DPF((PVR_DBG_ERROR, "%s: Invalid params", __FUNCTION__));
return PVRSRV_ERROR_INVALID_PARAMS;
}
for (i=0;i<ui32ChunkCount;i++)
{
if ((pauiOffset[i] & HOST_PAGEMASK) != 0)
@ -1377,30 +1367,17 @@ PVRSRV_ERROR PVRSRVMapIonHandleKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
OSMemSet(psNewKernelMemInfo, 0, sizeof(PVRSRV_KERNEL_MEM_INFO));
/* Import the ION buffer into our ion_client and DMA map it */
eError = IonImportBufferAndAcquirePhysAddr(psPerProcEnv->psIONClient,
ui32NumFDs,
pi32BufferFDs,
&ui32PageCount,
&pasSysPhysAddr,
&psNewKernelMemInfo->pvLinAddrKM,
&hPriv,
&hUnique);
eError = IonImportBufferAndAquirePhysAddr(psPerProcEnv->psIONClient,
hIon,
&ui32PageCount,
&pasSysPhysAddr,
&psNewKernelMemInfo->pvLinAddrKM,
&hPriv,
&hUnique);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "%s: Failed to get ion buffer/buffer phys addr", __FUNCTION__));
goto exitFailedImport;
}
/*
Make sure the number of pages detected by the ion import are at least
the size of the total chunked region
*/
if(ui32PageCount * PAGE_SIZE < uiMapSize)
{
PVR_DPF((PVR_DBG_ERROR, "%s: ion allocator returned fewer page addresses "
"than specified chunk size(s)", __FUNCTION__));
eError = PVRSRV_ERROR_INVALID_PARAMS;
goto exitFailedAdjustedAlloc;
goto exitFailedHeap;
}
/*
@ -1423,7 +1400,7 @@ PVRSRV_ERROR PVRSRVMapIonHandleKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
OSMemCopy(&pasAdjustedSysPhysAddr[uiAdjustOffset],
&pasSysPhysAddr[pauiOffset[i]/HOST_PAGESIZE()],
(pauiSize[i]/HOST_PAGESIZE()) * sizeof(IMG_SYS_PHYADDR));
uiAdjustOffset += pauiSize[i]/HOST_PAGESIZE();
}
@ -1495,7 +1472,7 @@ PVRSRV_ERROR PVRSRVMapIonHandleKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
if (psNewKernelMemInfo->sMemBlk.hResItem == IMG_NULL)
{
eError = PVRSRV_ERROR_OUT_OF_MEMORY;
PVR_DPF ((PVR_DBG_ERROR, "PVRSRVMapIonHandleKM: ResManRegisterRes failed %d",eError));
PVR_DPF ((PVR_DBG_ERROR, "PVRSRVMapIonHandleKM: ResManRegisterRes failed %d", eError));
goto exitFailedResman;
}
@ -1523,7 +1500,7 @@ exitFailedWrap:
IMG_NULL);
exitFailedAdjustedAlloc:
IonUnimportBufferAndReleasePhysAddr(hPriv);
exitFailedImport:
exitFailedHeap:
OSFreeMem(PVRSRV_PAGEABLE_SELECT,
sizeof(PVRSRV_KERNEL_MEM_INFO),
psNewKernelMemInfo,
@ -1732,13 +1709,12 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVWrapExtMemoryKM(IMG_HANDLE hDevCookie,
IMG_SIZE_T uPageCount = 0;
PVR_DPF ((PVR_DBG_MESSAGE,
"PVRSRVWrapExtMemoryKM (uSize=0x%" SIZE_T_FMT_LEN "x, uPageOffset=0x%"
SIZE_T_FMT_LEN "x, bPhysContig=%d, extSysPAddr=" SYSPADDR_FMT
"PVRSRVWrapExtMemoryKM (uSize=0x%x, uPageOffset=0x%x, bPhysContig=%d, extSysPAddr=" SYSPADDR_FMT
", pvLinAddr=%p, ui32Flags=%u)",
uByteSize,
uPageOffset,
bPhysContig,
psExtSysPAddr?psExtSysPAddr->uiAddr:0x0,
psExtSysPAddr->uiAddr,
pvLinAddr,
ui32Flags));
@ -1789,18 +1765,6 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVWrapExtMemoryKM(IMG_HANDLE hDevCookie,
*/
bPhysContig = IMG_FALSE;
}
else
{
if (psExtSysPAddr)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVWrapExtMemoryKM: invalid parameter, physical address passing is not supported"));
}
else
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVWrapExtMemoryKM: invalid parameter, no address specificed"));
}
return PVRSRV_ERROR_INVALID_PARAMS;
}
/* Choose the heap to map to */
psDevMemoryInfo = &((BM_CONTEXT*)hDevMemContext)->psDeviceNode->sDevMemoryInfo;
@ -2025,8 +1989,8 @@ static PVRSRV_ERROR UnmapDeviceMemoryCallBack(IMG_PVOID pvParam,
PVRSRV_FREE_CALLBACK_ORIGIN_IMPORTER);
if(eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "UnmapDeviceMemoryCallBack: FreeMemCallBackCommon Failed %d",eError));
PVR_DPF((PVR_DBG_ERROR, "UnmapDeviceMemoryCallBack: psSrcMemInfo: 0x%x",(unsigned int)psMapData->psSrcMemInfo));
PVR_DPF((PVR_DBG_ERROR, "UnmapDeviceMemoryCallBack: FreeMemCallBackCommon Failed %d", eError));
PVR_DPF((PVR_DBG_ERROR, "UnmapDeviceMemoryCallBack: psSrcMemInfo: 0x%x", (unsigned int)psMapData->psSrcMemInfo));
}
OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(RESMAN_MAP_DEVICE_MEM_DATA), psMapData, IMG_NULL);

6
drivers/gpu/pvr/services4/srvkm/common/handle.c
View file

@ -1834,7 +1834,6 @@ PVRSRV_ERROR PVRSRVLookupHandleAnyType(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *pp
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVLookupHandleAnyType: Error looking up handle (%d)", eError));
OSDumpStack();
return eError;
}
@ -1871,7 +1870,6 @@ PVRSRV_ERROR PVRSRVLookupHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData,
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVLookupHandle: Error looking up handle (%d)", eError));
OSDumpStack();
return eError;
}
@ -1909,7 +1907,6 @@ PVRSRV_ERROR PVRSRVLookupSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvDat
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVLookupSubHandle: Error looking up subhandle (%d)", eError));
OSDumpStack();
return eError;
}
@ -1958,7 +1955,6 @@ PVRSRV_ERROR PVRSRVGetParentHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *phPare
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVGetParentHandle: Error looking up subhandle (%d)", eError));
OSDumpStack();
return eError;
}
@ -1995,7 +1991,6 @@ PVRSRV_ERROR PVRSRVLookupAndReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVLookupAndReleaseHandle: Error looking up handle (%d)", eError));
OSDumpStack();
return eError;
}
@ -2030,7 +2025,6 @@ PVRSRV_ERROR PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle,
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVReleaseHandle: Error looking up handle (%d)", eError));
OSDumpStack();
return eError;
}

7
drivers/gpu/pvr/services4/srvkm/common/hash.c
View file

@ -542,13 +542,6 @@ HASH_Remove_Extended(HASH_TABLE *pHash, IMG_VOID *pKey)
PVR_DPF((PVR_DBG_ERROR, "HASH_Remove_Extended: Null hash table"));
return 0;
}
/* S.LSI */
if (pHash->pfnHashFunc == IMG_NULL || pHash->pfnKeyComp == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "HASH_Remove_Extended: Hash table: %p, Null pfnHashFunc: %p, pfnKeyComp: %p",
pHash, pHash->pfnHashFunc, pHash->pfnKeyComp));
return 0;
}
if (pHash->pfnHashFunc == IMG_NULL || pHash->pfnKeyComp == IMG_NULL)
{

9
drivers/gpu/pvr/services4/srvkm/common/mem_debug.c
View file

@ -125,9 +125,7 @@ extern "C"
if (uSize != psInfo->uSize)
{
PVR_DPF((PVR_DBG_WARNING,
"Pointer 0x%p : supplied size was different to stored size (0x%"
SIZE_T_FMT_LEN "X != 0x%" SIZE_T_FMT_LEN "X)"
" - referenced %s:%d - allocated %s:%d",
"Pointer 0x%p : supplied size was different to stored size (0x%x != 0x%X) - referenced %s:%d - allocated %s:%d",
pvCpuVAddr, uSize, psInfo->uSize,
pszFileName, uLine,
psInfo->sFileName, psInfo->uLineNo));
@ -138,9 +136,8 @@ extern "C"
if ((0x01234567 ^ psInfo->uSizeParityCheck) != psInfo->uSize)
{
PVR_DPF((PVR_DBG_WARNING,
"Pointer 0x%p : stored size parity error (0x%"
SIZE_T_FMT_LEN "X != 0x%" SIZE_T_FMT_LEN "X)"
" - referenced %s:%d - allocated %s:%d",
"Pointer 0x%p : stored size parity error (0x%X != 0x%X) \
- referenced %s:%d - allocated %s:%d",
pvCpuVAddr, psInfo->uSize, 0x01234567 ^ psInfo->uSizeParityCheck,
pszFileName, uLine,
psInfo->sFileName, psInfo->uLineNo));

2
drivers/gpu/pvr/services4/srvkm/common/pdump_common.c
View file

@ -1505,7 +1505,7 @@ PVRSRV_ERROR PDumpPDDevPAddrKM(PVRSRV_KERNEL_MEM_INFO *psMemInfo,
eErr = PDumpOSBufprintf(hScript,
ui32MaxLenScript,
"-- LDB :%s:PA_0x" UINTPTR_FMT DEVPADDR_FMT ":0x%08X 0x%08" SIZE_T_FMT_LEN "X 0x%08X %s\r\n",
"-- LDB :%s:PA_0x" UINTPTR_FMT DEVPADDR_FMT ":0x%08X 0x%08lX 0x%08X %s\r\n",
psMMUAttrib->sDevId.pszPDumpDevName,
(IMG_UINTPTR_T)hUniqueTag1,
sDevPAddrTmp.uiAddr,

2
drivers/gpu/pvr/services4/srvkm/common/pvrsrv.c
View file

@ -1442,7 +1442,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVGetMiscInfoKM(PVRSRV_MISC_INFO *psMiscInfo)
if ((psMiscInfo->ui32StateRequest & PVRSRV_MISC_INFO_FORCE_SWAP_TO_SYSTEM_PRESENT) != 0UL)
{
// PVRSRVSetDCState(DC_STATE_FORCE_SWAP_TO_SYSTEM);
PVRSRVSetDCState(DC_STATE_FORCE_SWAP_TO_SYSTEM);
psMiscInfo->ui32StatePresent |= PVRSRV_MISC_INFO_FORCE_SWAP_TO_SYSTEM_PRESENT;
}

108
drivers/gpu/pvr/services4/srvkm/common/queue.c
View file

@ -45,27 +45,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "lists.h"
#include "ttrace.h"
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
#include <linux/sw_sync.h>
static struct sync_fence *AllocQueueFence(struct sw_sync_timeline *psTimeline, IMG_UINT32 ui32FenceValue, const char *szName)
{
struct sync_fence *psFence = IMG_NULL;
struct sync_pt *psPt;
psPt = sw_sync_pt_create(psTimeline, ui32FenceValue);
if(psPt)
{
psFence = sync_fence_create(szName, psPt);
if(!psFence)
{
sync_pt_free(psPt);
}
}
return psFence;
}
#endif /* defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */
/*
* The number of commands of each type which can be in flight at once.
*/
@ -127,7 +106,7 @@ void ProcSeqShowQueue(struct seq_file *sfile,void* el)
{
psCmd= (PVRSRV_COMMAND *)((IMG_UINTPTR_T)psQueue->pvLinQueueKM + uReadOffset);
seq_printf(sfile, "%p %p %5u %6u %3" SIZE_T_FMT_LEN "u %5u %2u %2u %3" SIZE_T_FMT_LEN "u \n",
seq_printf(sfile, "%p %p %5u %6u %3u %5u %2u %2u %3u \n",
psQueue,
psCmd,
psCmd->ui32ProcessID,
@ -449,15 +428,6 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVCreateCommandQueueKM(IMG_SIZE_T uQueueSize,
psQueueInfo->uQueueSize = uPower2QueueSize;
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
psQueueInfo->pvTimeline = sw_sync_timeline_create("pvr_queue_proc");
if(psQueueInfo->pvTimeline == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR,"PVRSRVCreateCommandQueueKM: sw_sync_timeline_create() failed"));
goto ErrorExit;
}
#endif
/* if this is the first q, create a lock resource for the q list */
if (psSysData->psQueueList == IMG_NULL)
{
@ -565,10 +535,6 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVDestroyCommandQueueKM(PVRSRV_QUEUE_INFO *psQueue
goto ErrorExit;
}
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
sync_timeline_destroy(psQueueInfo->pvTimeline);
#endif
if(psQueue == psQueueInfo)
{
psSysData->psQueueList = psQueueInfo->psNextKM;
@ -731,8 +697,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVInsertCommandKM(PVRSRV_QUEUE_INFO *psQueue,
PVRSRV_KERNEL_SYNC_INFO *apsSrcSync[],
IMG_SIZE_T uDataByteSize,
PFN_QUEUE_COMMAND_COMPLETE pfnCommandComplete,
IMG_HANDLE hCallbackData,
IMG_HANDLE *phFence)
IMG_HANDLE hCallbackData)
{
PVRSRV_ERROR eError;
PVRSRV_COMMAND *psCommand;
@ -741,10 +706,6 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVInsertCommandKM(PVRSRV_QUEUE_INFO *psQueue,
SYS_DATA *psSysData;
DEVICE_COMMAND_DATA *psDeviceCommandData;
#if !defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
PVR_UNREFERENCED_PARAMETER(phFence);
#endif
/* Check that we've got enough space in our command complete data for this command */
SysAcquireData(&psSysData);
psDeviceCommandData = psSysData->apsDeviceCommandData[ui32DevIndex];
@ -771,45 +732,6 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVInsertCommandKM(PVRSRV_QUEUE_INFO *psQueue,
return eError;
}
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
if(phFence != IMG_NULL)
{
struct sync_fence *psRetireFence, *psCleanupFence;
/* New command? New timeline target */
psQueue->ui32FenceValue++;
psRetireFence = AllocQueueFence(psQueue->pvTimeline, psQueue->ui32FenceValue, "pvr_queue_retire");
if(!psRetireFence)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVInsertCommandKM: sync_fence_create() failed"));
psQueue->ui32FenceValue--;
return PVRSRV_ERROR_INVALID_PARAMS;
}
/* This similar to the retire fence, except that it is destroyed
* when a display command completes, rather than at the whim of
* userspace. It is used to keep the timeline alive.
*/
psCleanupFence = AllocQueueFence(psQueue->pvTimeline, psQueue->ui32FenceValue, "pvr_queue_cleanup");
if(!psCleanupFence)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVInsertCommandKM: sync_fence_create() #2 failed"));
sync_fence_put(psRetireFence);
psQueue->ui32FenceValue--;
return PVRSRV_ERROR_INVALID_PARAMS;
}
psCommand->pvCleanupFence = psCleanupFence;
psCommand->pvTimeline = psQueue->pvTimeline;
*phFence = psRetireFence;
}
else
{
psCommand->pvTimeline = IMG_NULL;
}
#endif /* defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */
psCommand->ui32ProcessID = OSGetCurrentProcessIDKM();
/* setup the command */
@ -1125,11 +1047,6 @@ PVRSRV_ERROR PVRSRVProcessCommand(SYS_DATA *psSysData,
psCmdCompleteData->pfnCommandComplete = psCommand->pfnCommandComplete;
psCmdCompleteData->hCallbackData = psCommand->hCallbackData;
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
psCmdCompleteData->pvCleanupFence = psCommand->pvCleanupFence;
psCmdCompleteData->pvTimeline = psCommand->pvTimeline;
#endif
/* copy dst updates over */
psCmdCompleteData->ui32SrcSyncCount = psCommand->ui32SrcSyncCount;
for (i=0; i<psCommand->ui32SrcSyncCount; i++)
@ -1165,13 +1082,10 @@ PVRSRV_ERROR PVRSRVProcessCommand(SYS_DATA *psSysData,
*/
psCmdCompleteData->bInUse = IMG_FALSE;
eError = PVRSRV_ERROR_CMD_NOT_PROCESSED;
PVR_LOG(("Failed to submit command from queue processor, this could cause sync wedge!"));
}
else
{
/* Increment the CCB offset */
psDeviceCommandData[psCommand->CommandType].ui32CCBOffset = (ui32CCBOffset + 1) % DC_NUM_COMMANDS_PER_TYPE;
}
/* Increment the CCB offset */
psDeviceCommandData[psCommand->CommandType].ui32CCBOffset = (ui32CCBOffset + 1) % DC_NUM_COMMANDS_PER_TYPE;
return eError;
}
@ -1267,7 +1181,7 @@ PVRSRV_ERROR PVRSRVProcessQueues(IMG_BOOL bFlush)
/*!
******************************************************************************
@Function PVRSRVFreeCommandCompletePacketKM
@Function PVRSRVCommandCompleteKM
@Description Updates non-private command complete sync objects
@ -1371,14 +1285,6 @@ IMG_VOID PVRSRVCommandCompleteKM(IMG_HANDLE hCmdCookie,
psCmdCompleteData->pfnCommandComplete(psCmdCompleteData->hCallbackData);
}
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
if(psCmdCompleteData->pvTimeline)
{
sw_sync_timeline_inc(psCmdCompleteData->pvTimeline, 1);
sync_fence_put(psCmdCompleteData->pvCleanupFence);
}
#endif /* defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */
/* free command complete storage */
psCmdCompleteData->bInUse = IMG_FALSE;
@ -1392,6 +1298,8 @@ IMG_VOID PVRSRVCommandCompleteKM(IMG_HANDLE hCmdCookie,
}
/*!
******************************************************************************

66
drivers/gpu/pvr/services4/srvkm/common/ra.c
View file

@ -734,7 +734,7 @@ _InsertResourceSpan (RA_ARENA *pArena, IMG_UINTPTR_T base, IMG_SIZE_T uSize)
}
PVR_DPF ((PVR_DBG_MESSAGE,
"RA_InsertResourceSpan: arena='%s', base=0x" UINTPTR_FMT ", size=0x%" SIZE_T_FMT_LEN "x",
"RA_InsertResourceSpan: arena='%s', base=0x" UINTPTR_FMT ", size=0x%x",
pArena->name, base, uSize));
pSpanStart = _BuildSpanMarker (base, uSize);
@ -1003,8 +1003,8 @@ _AttemptAllocAligned (RA_ARENA *pArena,
aligned_base = pBT->base;
PVR_DPF ((PVR_DBG_MESSAGE,
"RA_AttemptAllocAligned: pBT-base=0x" UINTPTR_FMT " "
"pBT-size=0x%" SIZE_T_FMT_LEN "x alignedbase=0x"
UINTPTR_FMT " size=0x%" SIZE_T_FMT_LEN "x",
"pBT-size=0x%x alignedbase=0x"
UINTPTR_FMT " size=0x%x",
pBT->base,
pBT->uSize,
aligned_base,
@ -1152,7 +1152,7 @@ RA_Create (IMG_CHAR *name,
IMG_INT i;
PVR_DPF ((PVR_DBG_MESSAGE,
"RA_Create: name='%s', base=0x" UINTPTR_FMT ", uSize=0x%" SIZE_T_FMT_LEN "x, alloc=0x%p, free=0x%p",
"RA_Create: name='%s', base=0x" UINTPTR_FMT ", uSize=0x%x, alloc=0x%p, free=0x%p",
name, base, uSize, imp_alloc, imp_free));
@ -1297,7 +1297,7 @@ RA_Delete (RA_ARENA *pArena)
{
PVR_DPF ((PVR_DBG_ERROR,"RA_Delete: allocations still exist in the arena that is being destroyed"));
PVR_DPF ((PVR_DBG_ERROR,"Likely Cause: client drivers not freeing alocations before destroying devmemcontext"));
PVR_DPF ((PVR_DBG_ERROR,"RA_Delete: base = 0x" UINTPTR_FMT " size=0x%" SIZE_T_FMT_LEN "x", pBT->base, pBT->uSize));
PVR_DPF ((PVR_DBG_ERROR,"RA_Delete: base = 0x" UINTPTR_FMT " size=0x%x", pBT->base, pBT->uSize));
}
_SegmentListRemove (pArena, pBT);
@ -1353,7 +1353,7 @@ RA_TestDelete (RA_ARENA *pArena)
if (pBT->type != btt_free)
{
PVR_DPF ((PVR_DBG_ERROR,"RA_TestDelete: detected resource leak!"));
PVR_DPF ((PVR_DBG_ERROR,"RA_TestDelete: base = 0x" UINTPTR_FMT " size=0x%" SIZE_T_FMT_LEN "x", pBT->base, pBT->uSize));
PVR_DPF ((PVR_DBG_ERROR,"RA_TestDelete: base = 0x" UINTPTR_FMT " size=0x%x", pBT->base, pBT->uSize));
return IMG_FALSE;
}
}
@ -1388,7 +1388,7 @@ RA_Add (RA_ARENA *pArena, IMG_UINTPTR_T base, IMG_SIZE_T uSize)
}
PVR_DPF ((PVR_DBG_MESSAGE,
"RA_Add: name='%s', base=0x" UINTPTR_FMT ", size=0x%" SIZE_T_FMT_LEN "x", pArena->name, base, uSize));
"RA_Add: name='%s', base=0x" UINTPTR_FMT ", size=0x%x", pArena->name, base, uSize));
uSize = (uSize + pArena->uQuantum - 1) / pArena->uQuantum * pArena->uQuantum;
return ((IMG_BOOL)(_InsertResource (pArena, base, uSize) != IMG_NULL));
@ -1454,7 +1454,7 @@ RA_Alloc (RA_ARENA *pArena,
}
PVR_DPF ((PVR_DBG_MESSAGE,
"RA_Alloc: arena='%s', size=0x%" SIZE_T_FMT_LEN "x(0x%" SIZE_T_FMT_LEN "x), alignment=0x%x, offset=0x%x",
"RA_Alloc: arena='%s', size=0x%x(0x%x), alignment=0x%x, offset=0x%x",
pArena->name, uSize, uRequestSize, uAlignment, uAlignmentOffset));
/* if allocation failed then we might have an import source which
@ -1497,7 +1497,7 @@ RA_Alloc (RA_ARENA *pArena,
pArena->pImportFree(pArena->pImportHandle, import_base,
psImportMapping);
PVR_DPF ((PVR_DBG_MESSAGE,
"RA_Alloc: name='%s', size=0x%" SIZE_T_FMT_LEN "x failed!",
"RA_Alloc: name='%s', size=0x%x failed!",
pArena->name, uSize));
/* RA_Dump (arena); */
return IMG_FALSE;
@ -1526,7 +1526,7 @@ RA_Alloc (RA_ARENA *pArena,
#endif
PVR_DPF ((PVR_DBG_MESSAGE,
"RA_Alloc: name='%s', size=0x%" SIZE_T_FMT_LEN "x, *base=0x" UINTPTR_FMT " = %d",
"RA_Alloc: name='%s', size=0x%x, *base=0x" UINTPTR_FMT " = %d",
pArena->name, uSize, *base, bResult));
/* RA_Dump (pArena);
@ -1816,7 +1816,7 @@ RA_Free (RA_ARENA *pArena, IMG_UINTPTR_T base, IMG_BOOL bFreeBackingStore)
*p++ = 0xAA;
}
PVR_DPF((PVR_DBG_MESSAGE,
"BM_FREESPACE_CHECK: RA_Free Cleared %p to %p (size=0x%" SIZE_T_FMT_LEN "x)",
"BM_FREESPACE_CHECK: RA_Free Cleared %p to %p (size=0x%x)",
(IMG_BYTE*)pBT->base + SysGetDevicePhysOffset(),
endp - 1,
pBT->uSize));
@ -1963,7 +1963,7 @@ RA_Dump (RA_ARENA *pArena)
for (pBT=pArena->pHeadSegment; pBT!=IMG_NULL; pBT=pBT->pNextSegment)
{
PVR_DPF ((PVR_DBG_MESSAGE,"\tbase=0x" UINTPTR_FMT " size=0x%" SIZE_T_FMT_LEN "x type=%s",
PVR_DPF ((PVR_DBG_MESSAGE,"\tbase=0x" UINTPTR_FMT " size=0x%x type=%s",
pBT->base, pBT->uSize, _BTType (pBT->type)));
}
@ -1986,37 +1986,37 @@ static void RA_ProcSeqShowInfo(struct seq_file *sfile, void* el)
switch (off)
{
case 1:
seq_printf(sfile, "quantum\t\t\t%" SIZE_T_FMT_LEN "u\n", pArena->uQuantum);
seq_printf(sfile, "quantum\t\t\t%u\n", pArena->uQuantum);
break;
case 2:
seq_printf(sfile, "import_handle\t\t%p\n", pArena->pImportHandle);
break;
#ifdef RA_STATS
case 3:
seq_printf(sfile,"span count\t\t%" SIZE_T_FMT_LEN "u\n", pArena->sStatistics.uSpanCount);
seq_printf(sfile,"span count\t\t%u\n", pArena->sStatistics.uSpanCount);
break;
case 4:
seq_printf(sfile, "live segment count\t%" SIZE_T_FMT_LEN "u\n", pArena->sStatistics.uLiveSegmentCount);
seq_printf(sfile, "live segment count\t%u\n", pArena->sStatistics.uLiveSegmentCount);
break;
case 5:
seq_printf(sfile, "free segment count\t%" SIZE_T_FMT_LEN "u\n", pArena->sStatistics.uFreeSegmentCount);
seq_printf(sfile, "free segment count\t%u\n", pArena->sStatistics.uFreeSegmentCount);
break;
case 6:
seq_printf(sfile, "free resource count\t%" SIZE_T_FMT_LEN "u (0x%" SIZE_T_FMT_LEN "x)\n",
seq_printf(sfile, "free resource count\t%u (0x%x)\n",
pArena->sStatistics.uFreeResourceCount,
pArena->sStatistics.uFreeResourceCount);
break;
case 7:
seq_printf(sfile, "total allocs\t\t%" SIZE_T_FMT_LEN "u\n", pArena->sStatistics.uCumulativeAllocs);
seq_printf(sfile, "total allocs\t\t%u\n", pArena->sStatistics.uCumulativeAllocs);
break;
case 8:
seq_printf(sfile, "total frees\t\t%" SIZE_T_FMT_LEN "u\n", pArena->sStatistics.uCumulativeFrees);
seq_printf(sfile, "total frees\t\t%u\n", pArena->sStatistics.uCumulativeFrees);
break;
case 9:
seq_printf(sfile, "import count\t\t%" SIZE_T_FMT_LEN "u\n", pArena->sStatistics.uImportCount);
seq_printf(sfile, "import count\t\t%u\n", pArena->sStatistics.uImportCount);
break;
case 10:
seq_printf(sfile, "export count\t\t%" SIZE_T_FMT_LEN "u\n", pArena->sStatistics.uExportCount);
seq_printf(sfile, "export count\t\t%u\n", pArena->sStatistics.uExportCount);
break;
#endif
}
@ -2048,7 +2048,7 @@ static void RA_ProcSeqShowRegs(struct seq_file *sfile, void* el)
if (pBT)
{
seq_printf(sfile, "%p %" SIZE_T_FMT_LEN "x %4s %p\n",
seq_printf(sfile, "%p %x %4s %p\n",
(IMG_PVOID)pBT->base, pBT->uSize, _BTType (pBT->type),
pBT->psMapping);
}
@ -2099,7 +2099,7 @@ PVRSRV_ERROR RA_GetStats(RA_ARENA *pArena,
CHECK_SPACE(ui32StrLen);
i32Count = OSSNPrintf(pszStr, 100, " allocCB=%p freeCB=%p handle=%p quantum=%" SIZE_T_FMT_LEN "u\n",
i32Count = OSSNPrintf(pszStr, 100, " allocCB=%p freeCB=%p handle=%p quantum=%u\n",
pArena->pImportAlloc,
pArena->pImportFree,
pArena->pImportHandle,
@ -2107,43 +2107,43 @@ PVRSRV_ERROR RA_GetStats(RA_ARENA *pArena,
UPDATE_SPACE(pszStr, i32Count, ui32StrLen);
CHECK_SPACE(ui32StrLen);
i32Count = OSSNPrintf(pszStr, 100, "span count\t\t%" SIZE_T_FMT_LEN "u\n",
i32Count = OSSNPrintf(pszStr, 100, "span count\t\t%u\n",
pArena->sStatistics.uSpanCount);
UPDATE_SPACE(pszStr, i32Count, ui32StrLen);
CHECK_SPACE(ui32StrLen);
i32Count = OSSNPrintf(pszStr, 100, "live segment count\t%" SIZE_T_FMT_LEN "u\n",
i32Count = OSSNPrintf(pszStr, 100, "live segment count\t%u\n",
pArena->sStatistics.uLiveSegmentCount);
UPDATE_SPACE(pszStr, i32Count, ui32StrLen);
CHECK_SPACE(ui32StrLen);
i32Count = OSSNPrintf(pszStr, 100, "free segment count\t%" SIZE_T_FMT_LEN "u\n",
i32Count = OSSNPrintf(pszStr, 100, "free segment count\t%u\n",
pArena->sStatistics.uFreeSegmentCount);
UPDATE_SPACE(pszStr, i32Count, ui32StrLen);
CHECK_SPACE(ui32StrLen);
i32Count = OSSNPrintf(pszStr, 100, "free resource count\t%" SIZE_T_FMT_LEN "u (0x%" SIZE_T_FMT_LEN "x)\n",
i32Count = OSSNPrintf(pszStr, 100, "free resource count\t%u (0x%x)\n",
pArena->sStatistics.uFreeResourceCount,
pArena->sStatistics.uFreeResourceCount);
UPDATE_SPACE(pszStr, i32Count, ui32StrLen);
CHECK_SPACE(ui32StrLen);
i32Count = OSSNPrintf(pszStr, 100, "total allocs\t\t%" SIZE_T_FMT_LEN "u\n",
i32Count = OSSNPrintf(pszStr, 100, "total allocs\t\t%u\n",
pArena->sStatistics.uCumulativeAllocs);
UPDATE_SPACE(pszStr, i32Count, ui32StrLen);
CHECK_SPACE(ui32StrLen);
i32Count = OSSNPrintf(pszStr, 100, "total frees\t\t%" SIZE_T_FMT_LEN "u\n",
i32Count = OSSNPrintf(pszStr, 100, "total frees\t\t%u\n",
pArena->sStatistics.uCumulativeFrees);
UPDATE_SPACE(pszStr, i32Count, ui32StrLen);
CHECK_SPACE(ui32StrLen);
i32Count = OSSNPrintf(pszStr, 100, "import count\t\t%" SIZE_T_FMT_LEN "u\n",
i32Count = OSSNPrintf(pszStr, 100, "import count\t\t%u\n",
pArena->sStatistics.uImportCount);
UPDATE_SPACE(pszStr, i32Count, ui32StrLen);
CHECK_SPACE(ui32StrLen);
i32Count = OSSNPrintf(pszStr, 100, "export count\t\t%" SIZE_T_FMT_LEN "u\n",
i32Count = OSSNPrintf(pszStr, 100, "export count\t\t%u\n",
pArena->sStatistics.uExportCount);
UPDATE_SPACE(pszStr, i32Count, ui32StrLen);
@ -2170,7 +2170,7 @@ PVRSRV_ERROR RA_GetStats(RA_ARENA *pArena,
for (pBT=pArena->pHeadSegment; pBT!=IMG_NULL; pBT=pBT->pNextSegment)
{
CHECK_SPACE(ui32StrLen);
i32Count = OSSNPrintf(pszStr, 100, "\tbase=0x%p size=0x%" SIZE_T_FMT_LEN "x type=%s ref=%p\n",
i32Count = OSSNPrintf(pszStr, 100, "\tbase=0x%p size=0x%x type=%s ref=%p\n",
(void *)pBT->base,
pBT->uSize,
_BTType(pBT->type),
@ -2192,7 +2192,7 @@ PVRSRV_ERROR RA_GetStatsFreeMem(RA_ARENA *pArena,
IMG_UINT32 ui32StrLen = *pui32StrLen;
IMG_INT32 i32Count;
CHECK_SPACE(ui32StrLen);
i32Count = OSSNPrintf(pszStr, 100, "Bytes free: Arena %-30s: %" SIZE_T_FMT_LEN "u (0x%" SIZE_T_FMT_LEN "x)\n", pArena->name,
i32Count = OSSNPrintf(pszStr, 100, "Bytes free: Arena %-30s: %u (0x%x)\n", pArena->name,
pArena->sStatistics.uFreeResourceCount,
pArena->sStatistics.uFreeResourceCount);
UPDATE_SPACE(pszStr, i32Count, ui32StrLen);

12
drivers/gpu/pvr/services4/srvkm/devices/sgx/mmu.c
View file

@ -3132,7 +3132,7 @@ MMU_Alloc (MMU_HEAP *pMMUHeap,
IMG_BOOL bStatus;
PVR_DPF ((PVR_DBG_MESSAGE,
"MMU_Alloc: uSize=0x%" SIZE_T_FMT_LEN "x, flags=0x%x, align=0x%x",
"MMU_Alloc: uSize=0x%x, flags=0x%x, align=0x%x",
uSize, uFlags, uDevVAddrAlignment));
/*
@ -3595,7 +3595,7 @@ MMU_MapScatter (MMU_HEAP *pMMUHeap,
DevVAddr.uiAddr += pMMUHeap->ui32DataPageSize;
PVR_DPF ((PVR_DBG_MESSAGE,
"MMU_MapScatter: devVAddr=%x, SysAddr=" SYSPADDR_FMT ", size=0x%x/0x%" SIZE_T_FMT_LEN "x",
"MMU_MapScatter: devVAddr=%x, SysAddr=" SYSPADDR_FMT ", size=0x%x/0x%x",
DevVAddr.uiAddr, sSysAddr.uiAddr, uCount, uSize));
}
@ -3642,7 +3642,7 @@ MMU_MapPages (MMU_HEAP *pMMUHeap,
PVR_ASSERT (pMMUHeap != IMG_NULL);
PVR_DPF ((PVR_DBG_MESSAGE, "MMU_MapPages: heap:%s, heap_id:%d devVAddr=%08X, SysPAddr=" SYSPADDR_FMT ", size=0x%" SIZE_T_FMT_LEN "x",
PVR_DPF ((PVR_DBG_MESSAGE, "MMU_MapPages: heap:%s, heap_id:%d devVAddr=%08X, SysPAddr=" SYSPADDR_FMT ", size=0x%x",
pMMUHeap->psDevArena->pszName,
pMMUHeap->psDevArena->ui32HeapID,
DevVAddr.uiAddr,
@ -3734,7 +3734,7 @@ MMU_MapPagesSparse (MMU_HEAP *pMMUHeap,
PVR_ASSERT (pMMUHeap != IMG_NULL);
PVR_DPF ((PVR_DBG_MESSAGE, "MMU_MapPagesSparse: heap:%s, heap_id:%d devVAddr=%08X, SysPAddr=" SYSPADDR_FMT ", VM space=0x%" SIZE_T_FMT_LEN "x, PHYS space=0x%x",
PVR_DPF ((PVR_DBG_MESSAGE, "MMU_MapPagesSparse: heap:%s, heap_id:%d devVAddr=%08X, SysPAddr=" SYSPADDR_FMT ", VM space=0x%x, PHYS space=0x%x",
pMMUHeap->psDevArena->pszName,
pMMUHeap->psDevArena->ui32HeapID,
DevVAddr.uiAddr,
@ -3833,7 +3833,7 @@ MMU_MapShadow (MMU_HEAP *pMMUHeap,
#endif
PVR_DPF ((PVR_DBG_MESSAGE,
"MMU_MapShadow: DevVAddr:%08X, Bytes:0x%" SIZE_T_FMT_LEN "x, CPUVAddr:%p",
"MMU_MapShadow: DevVAddr:%08X, Bytes:0x%x, CPUVAddr:%p",
MapBaseDevVAddr.uiAddr,
uByteSize,
CpuVAddr));
@ -3959,7 +3959,7 @@ MMU_MapShadowSparse (MMU_HEAP *pMMUHeap,
#endif
PVR_DPF ((PVR_DBG_MESSAGE,
"MMU_MapShadowSparse: DevVAddr:%08X, VM space:0x%" SIZE_T_FMT_LEN "x, CPUVAddr:%p PHYS space:0x%x",
"MMU_MapShadowSparse: DevVAddr:%08X, VM space:0x%x, CPUVAddr:%p PHYS space:0x%x",
MapBaseDevVAddr.uiAddr,
uiSizeVM,
CpuVAddr,

4
drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxinfokm.h
View file

@ -149,6 +149,10 @@ typedef struct _PVRSRV_SGXDEV_INFO_
PPVRSRV_KERNEL_MEM_INFO psKernelHWPerfCBMemInfo; /*!< Meminfo for hardware performace circular buffer */
PPVRSRV_KERNEL_MEM_INFO psKernelTASigBufferMemInfo; /*!< Meminfo for TA signature buffer */
PPVRSRV_KERNEL_MEM_INFO psKernel3DSigBufferMemInfo; /*!< Meminfo for 3D signature buffer */
#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31559)
PPVRSRV_KERNEL_MEM_INFO psKernelVDMSnapShotBufferMemInfo; /*!< Meminfo for dummy snapshot buffer */
PPVRSRV_KERNEL_MEM_INFO psKernelVDMCtrlStreamBufferMemInfo; /*!< Meminfo for dummy control stream */
#endif
#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && \
defined(FIX_HW_BRN_33657) && defined(SUPPORT_SECURE_33657_FIX)
PPVRSRV_KERNEL_MEM_INFO psKernelVDMStateUpdateBufferMemInfo; /*!< Meminfo for state update buffer */

67
drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxinit.c
View file

@ -70,10 +70,11 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define SYS_SGX_CLOCK_SPEED (333000000)
IMG_UINT32 g_ui32HostIRQCountSample = 0;
IMG_UINT32 g_ui32HostIRQCountSample;
unsigned int *g_debug_CCB_Info_RO;
unsigned int *g_debug_CCB_Info_WO;
extern unsigned int g_debug_CCB_Info_WCNT;
#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
@ -240,6 +241,10 @@ static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc,
#endif
psDevInfo->psKernelTASigBufferMemInfo = psInitInfo->hKernelTASigBufferMemInfo;
psDevInfo->psKernel3DSigBufferMemInfo = psInitInfo->hKernel3DSigBufferMemInfo;
#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31559)
psDevInfo->psKernelVDMSnapShotBufferMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelVDMSnapShotBufferMemInfo;
psDevInfo->psKernelVDMCtrlStreamBufferMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelVDMCtrlStreamBufferMemInfo;
#endif
#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && \
defined(FIX_HW_BRN_33657) && defined(SUPPORT_SECURE_33657_FIX)
psDevInfo->psKernelVDMStateUpdateBufferMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelVDMStateUpdateBufferMemInfo;
@ -319,7 +324,7 @@ failed_allockernelccb:
static PVRSRV_ERROR SGXRunScript(PVRSRV_SGXDEV_INFO *psDevInfo, SGX_INIT_COMMAND *psScript, IMG_UINT32 ui32NumInitCommands)
{
IMG_UINT32 ui32PC, ui32RegVal;
IMG_UINT32 ui32PC;
SGX_INIT_COMMAND *psComm;
for (ui32PC = 0, psComm = psScript;
@ -344,14 +349,6 @@ static PVRSRV_ERROR SGXRunScript(PVRSRV_SGXDEV_INFO *psDevInfo, SGX_INIT_COMMAND
#endif
break;
}
case SGX_INIT_OP_PRINT_HW_REG:
{
ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, psComm->sReadHWReg.ui32Offset);
PVR_LOG((" (SGXREG) 0x%08X : 0x%08X", psComm->sReadHWReg.ui32Offset, ui32RegVal));
break;
}
#if defined(PDUMP)
case SGX_INIT_OP_PDUMP_HW_REG:
{
@ -1038,7 +1035,6 @@ static PVRSRV_ERROR DevDeInitSGX (IMG_VOID *pvDeviceNode)
PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO*)psDeviceNode->pvDevice;
PVRSRV_ERROR eError;
IMG_UINT32 ui32Heap;
IMG_UINT32 ui32Count;
DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap;
SGX_DEVICE_MAP *psSGXDeviceMap;
@ -1147,19 +1143,8 @@ static PVRSRV_ERROR DevDeInitSGX (IMG_VOID *pvDeviceNode)
}
}
#endif /* #ifdef SGX_FEATURE_HOST_PORT */
/* Deallocate KM mem allocated for debug script commands */
for (ui32Count = 0; ui32Count < SGX_FEATURE_MP_CORE_COUNT_3D; ui32Count++)
{
if(psDevInfo->sScripts.apsSGXREGDebugCommandsPart2[ui32Count])
{
OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
SGX_MAX_PRINT_COMMANDS * sizeof(SGX_INIT_COMMAND),
psDevInfo->sScripts.apsSGXREGDebugCommandsPart2[ui32Count],
0);
}
}
/* DeAllocate devinfo */
OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
sizeof(PVRSRV_SGXDEV_INFO),
@ -1383,7 +1368,7 @@ IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo,
#endif
PVR_LOG((" Host Ctl flags= %08x", ui32CtlFlags));
}
if (psSGXHostCtl->ui32AssertFail != 0)
{
PVR_LOG(("SGX Microkernel assert fail: 0x%08X", psSGXHostCtl->ui32AssertFail));
@ -1519,7 +1504,6 @@ IMG_VOID HWRecoveryResetSGX (PVRSRV_DEVICE_NODE *psDeviceNode,
IMG_UINT32 ui32CallerID)
{
PVRSRV_ERROR eError;
IMG_UINT32 ui32Count;
PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO*)psDeviceNode->pvDevice;
SGXMKIF_HOST_CTL *psSGXHostCtl = (SGXMKIF_HOST_CTL *)psDevInfo->psSGXHostCtl;
@ -1548,27 +1532,6 @@ IMG_VOID HWRecoveryResetSGX (PVRSRV_DEVICE_NODE *psDeviceNode,
psSGXHostCtl->ui32InterruptClearFlags |= PVRSRV_USSE_EDM_INTERRUPT_HWR;
PVR_LOG(("HWRecoveryResetSGX: SGX Hardware Recovery triggered"));
/* Run SGXREGDebug scripts */
#if defined(SGX_FEATURE_MP)
PVR_LOG(("(HYD)"));
eError = SGXRunScript(psDevInfo, psDevInfo->sScripts.asSGXREGDebugCommandsPart1, SGX_MAX_PRINT_COMMANDS);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"HWRecoveryResetSGX: SGXREGDebugCommandsPart1 SGXRunScript failed (%d)", eError));
}
#endif
for (ui32Count = 0; ui32Count < SGX_FEATURE_MP_CORE_COUNT_3D; ui32Count++)
{
PVR_LOG(("(P%u)",ui32Count));
eError = SGXRunScript(psDevInfo, psDevInfo->sScripts.apsSGXREGDebugCommandsPart2[ui32Count], SGX_MAX_PRINT_COMMANDS);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"HWRecoveryResetSGX: SGXREGDebugCommandsPart2 SGXRunScript failed (%d)", eError));
}
}
/* Scripts end */
#if defined(SUPPORT_HWRECOVERY_TRACE_LIMIT)
/*
@ -1863,7 +1826,7 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData)
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32EventClear2);
/*
Sample the current count from the uKernel _after_ we've cleared the
Sample the current count from the uKernel _before_ we clear the
interrupt.
*/
g_ui32HostIRQCountSample = psDevInfo->psSGXHostCtl->ui32InterruptCount;
@ -3320,14 +3283,6 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
case SGX_MISC_INFO_DUMP_DEBUG_INFO_FORCE_REGS:
{
if(!OSProcHasPrivSrvInit())
{
PVR_DPF((PVR_DBG_ERROR, "Insufficient privileges to dump SGX "
"debug info with registers"));
return PVRSRV_ERROR_INVALID_MISCINFO;
}
PVR_LOG(("User requested SGX debug info"));
/* Dump SGX debug data to the kernel log. */

67
drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxkick.c
View file

@ -53,10 +53,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "sgxutils.h"
#include "ttrace.h"
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
#include "pvr_sync.h"
#endif
/*!
******************************************************************************
@ -239,41 +235,7 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
}
#else /* SUPPORT_SGX_GENERALISED_SYNCOBJECTS */
/* texture dependencies */
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
eError = PVRSyncPatchCCBKickSyncInfos(psCCBKick->ahSrcKernelSyncInfo,
psTACmd->asSrcSyncs,
&psCCBKick->ui32NumSrcSyncs);
if(eError != PVRSRV_OK)
{
/* We didn't kick yet, or perform PDUMP processing, so we should
* be able to trivially roll back any changes made to the sync
* data. If we don't do this, we'll wedge services cleanup.
*/
if (psCCBKick->h3DSyncInfo != IMG_NULL)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->h3DSyncInfo;
psSyncInfo->psSyncData->ui32ReadOpsPending--;
}
if (psCCBKick->hTASyncInfo != IMG_NULL)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->hTASyncInfo;
psSyncInfo->psSyncData->ui32ReadOpsPending--;
}
if (psCCBKick->hTA3DSyncInfo && psCCBKick->bTADependency)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->hTA3DSyncInfo;
psSyncInfo->psSyncData->ui32WriteOpsPending--;
}
PVR_DPF((PVR_DBG_ERROR, "SGXDoKickKM: PVRSyncPatchCCBKickSyncInfos failed."));
PVR_TTRACE(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_FUNCTION_EXIT,
KICK_TOKEN_DOKICK);
return eError;
}
#else /* defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */
psTACmd->ui32NumSrcSyncs = psCCBKick->ui32NumSrcSyncs;
for (i=0; i<psCCBKick->ui32NumSrcSyncs; i++)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *) psCCBKick->ahSrcKernelSyncInfo[i];
@ -289,9 +251,7 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
/* Copy ui32WriteOpsPending snapshot into the CCB. */
psTACmd->asSrcSyncs[i].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending;
}
#endif /* defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */
psTACmd->ui32NumSrcSyncs = psCCBKick->ui32NumSrcSyncs;
#endif /* defined(SUPPORT_SGX_GENERALISED_SYNCOBJECTS) */
#endif/* SUPPORT_SGX_GENERALISED_SYNCOBJECTS */
if (psCCBKick->bFirstKickOrResume && psCCBKick->ui32NumDstSyncObjects > 0)
{
@ -546,25 +506,6 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
MAKEUNIQUETAG(psCCBMemInfo));
}
if (psCCBKick->hTA3DSyncInfo != IMG_NULL)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->hTA3DSyncInfo;
PDUMPCOMMENT("Modify TA/3D dependency WOpPendingVal\r\n");
PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal,
psCCBMemInfo,
psCCBKick->ui32CCBDumpWOff + offsetof(SGXMKIF_CMDTA_SHARED, sTA3DDependency.ui32WriteOpsPendingVal),
sizeof(IMG_UINT32),
0,
MAKEUNIQUETAG(psCCBMemInfo));
if (psCCBKick->bTADependency)
{
psSyncInfo->psSyncData->ui32LastOpDumpVal++;
}
}
if (psCCBKick->hTASyncInfo != IMG_NULL)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->hTASyncInfo;
@ -578,7 +519,7 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
0,
MAKEUNIQUETAG(psCCBMemInfo));
PDUMPCOMMENT("Modify TA/TQ WOpPendingVal\r\n");
PDUMPCOMMENT("Modify TA/TQ OpPendingVal\r\n");
PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal,
psCCBMemInfo,
@ -603,7 +544,7 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
0,
MAKEUNIQUETAG(psCCBMemInfo));
PDUMPCOMMENT("Modify 3D/TQ WOpPendingVal\r\n");
PDUMPCOMMENT("Modify 3D/TQ OpPendingVal\r\n");
PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal,
psCCBMemInfo,

95
drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxtransfer.c
View file

@ -58,10 +58,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "sgxutils.h"
#include "ttrace.h"
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
#include "pvr_sync.h"
#endif
IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSFER_SGX_KICK *psKick)
{
PVRSRV_KERNEL_MEM_INFO *psCCBMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psKick->hCCBMemInfo;
@ -210,6 +206,9 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
}
}
psSharedTransferCmd->ui32NumSrcSyncs = ui32RealSrcSyncNum;
psSharedTransferCmd->ui32NumDstSyncs = ui32RealDstSyncNum;
if ((psKick->ui32Flags & SGXMKIF_TQFLAGS_KEEPPENDING) == 0UL)
{
IMG_UINT32 i = 0;
@ -279,87 +278,8 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
psSyncInfo->psSyncData->ui32WriteOpsPending++;
}
}
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
if (ui32RealDstSyncNum < SGX_MAX_TRANSFER_SYNC_OPS - 2 && psKick->iFenceFd > 0)
{
IMG_HANDLE ahSyncInfo[SGX_MAX_SRC_SYNCS_TA];
PVRSRV_DEVICE_SYNC_OBJECT *apsDevSyncs = &psSharedTransferCmd->asDstSyncs[ui32RealDstSyncNum];
IMG_UINT32 ui32NumSrcSyncs = 1;
IMG_UINT32 i;
ahSyncInfo[0] = (IMG_HANDLE)(psKick->iFenceFd - 1);
eError = PVRSyncPatchTransferSyncInfos(ahSyncInfo, apsDevSyncs, &ui32NumSrcSyncs);
if (eError != PVRSRV_OK)
{
/* We didn't kick yet, or perform PDUMP processing, so we should
* be able to trivially roll back any changes made to the sync
* data. If we don't do this, we'll wedge services cleanup.
*/
for (loop = 0; loop < psKick->ui32NumDstSync; loop++)
{
if (abDstSyncEnable[loop])
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop];
psSyncInfo->psSyncData->ui32WriteOpsPending--;
}
}
for (loop = 0; loop < psKick->ui32NumSrcSync; loop++)
{
if (abSrcSyncEnable[loop])
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop];
psSyncInfo->psSyncData->ui32ReadOpsPending--;
}
}
if (psKick->h3DSyncInfo != IMG_NULL)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo;
psSyncInfo->psSyncData->ui32WriteOpsPending++;
}
if (psKick->hTASyncInfo != IMG_NULL)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo;
psSyncInfo->psSyncData->ui32WriteOpsPending--;
}
PVR_DPF((PVR_DBG_ERROR, "SGXSubmitTransferKM: PVRSyncPatchCCBKickSyncInfos failed."));
PVR_TTRACE(PVRSRV_TRACE_GROUP_TRANSFER, PVRSRV_TRACE_CLASS_FUNCTION_EXIT,
TRANSFER_TOKEN_SUBMIT);
return eError;
}
/* Find a free dst sync to slot in our extra sync */
for (loop = 0; loop < psKick->ui32NumDstSync; loop++)
{
if (abDstSyncEnable[loop])
break;
}
/* We shouldn't be in this code path if ui32RealDstSyncNum
* didn't allow for at least two free synchronization slots.
*/
PVR_ASSERT(loop + ui32NumSrcSyncs <= SGX_MAX_TRANSFER_SYNC_OPS);
/* Slot in the extra dst syncs */
for (i = 0; i < ui32NumSrcSyncs; i++)
{
psKick->ahDstSyncInfo[loop + i] = ahSyncInfo[i];
abDstSyncEnable[loop + i] = IMG_TRUE;
psKick->ui32NumDstSync++;
ui32RealDstSyncNum++;
}
}
#endif /* defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC) */
}
psSharedTransferCmd->ui32NumSrcSyncs = ui32RealSrcSyncNum;
psSharedTransferCmd->ui32NumDstSyncs = ui32RealDstSyncNum;
#if defined(PDUMP)
if (PDumpIsCaptureFrameKM()
|| ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0))
@ -707,9 +627,6 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
ps2DCmd->sDstSyncData.sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr;
ps2DCmd->sDstSyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
ps2DCmd->sDstSyncData.sReadOps2CompleteDevVAddr = psSyncInfo->sReadOps2CompleteDevVAddr;
/* We can do this immediately as we only have one */
psSyncInfo->psSyncData->ui32WriteOpsPending++;
}
else
{
@ -725,6 +642,12 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
psSyncInfo->psSyncData->ui32ReadOpsPending++;
}
if (psKick->hDstSyncInfo != IMG_NULL)
{
psSyncInfo = psKick->hDstSyncInfo;
psSyncInfo->psSyncData->ui32WriteOpsPending++;
}
#if defined(PDUMP)
if ((PDumpIsCaptureFrameKM()
|| ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0)))

16
drivers/gpu/pvr/services4/srvkm/devices/sgx/sgxutils.c
View file

@ -67,7 +67,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#endif
IMG_UINT64 ui64KickCount;
int g_debug_CCB_Info_WCNT = 0;
int g_debug_CCB_Info_WCNT;
#if defined(SYS_CUSTOM_POWERDOWN)
PVRSRV_ERROR SysPowerDownMISR(PVRSRV_DEVICE_NODE * psDeviceNode, IMG_UINT32 ui32CallerID);
@ -550,7 +550,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode,
Increment the write offset
*/
*psKernelCCB->pui32WriteOffset = (*psKernelCCB->pui32WriteOffset + 1) & 255;
g_debug_CCB_Info_WCNT ++;
g_debug_CCB_Info_WCNT++;
#if defined(PDUMP)
if ((ui32CallerID != ISR_ID) && (bPDumpIsSuspended == IMG_FALSE) &&
@ -669,9 +669,9 @@ PVRSRV_ERROR SGXScheduleCCBCommandKM(PVRSRV_DEVICE_NODE *psDeviceNode,
eError = PVRSRVPowerLock(ui32CallerID, IMG_FALSE);
if (psDevInfo->psKernelCCBCtl->ui32ReadOffset > 0xff || psDevInfo->psKernelCCBCtl->ui32WriteOffset > 0xff)
PVR_DPF((PVR_DBG_ERROR,"SGX CCB check error: RO: %x, WO:%x ", psDevInfo->psKernelCCBCtl->ui32ReadOffset,
psDevInfo->psKernelCCBCtl->ui32WriteOffset));
PVR_ASSERT(psDevInfo->psKernelCCBCtl->ui32ReadOffset <= 0xff &&
PVR_DPF((PVR_DBG_ERROR, "SGX CCB check error: RO: %x, WO:%x ", psDevInfo->psKernelCCBCtl->ui32ReadOffset,
psDevInfo->psKernelCCBCtl->ui32WriteOffset));
PVR_ASSERT(psDevInfo->psKernelCCBCtl->ui32ReadOffset <= 0xff &&
psDevInfo->psKernelCCBCtl->ui32WriteOffset <= 0xff);
if (eError == PVRSRV_ERROR_RETRY)
@ -1249,7 +1249,7 @@ PVRSRV_ERROR SGXUnregisterHWRenderContextKM(IMG_HANDLE hHWRenderContext, IMG_BOO
eError = ResManFreeResByPtr(psCleanup->psResItem, bForceCleanup);
if(eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "SGXUnregisterHWRenderContextKM: ResManFreeResByPtr failed %d",eError));
PVR_DPF((PVR_DBG_ERROR, "SGXUnregisterHWRenderContextKM: ResManFreeResByPtr failed %d", eError));
PVR_DPF((PVR_DBG_ERROR, "ResManFreeResByPtr: hResItem 0x%x", (unsigned int)psCleanup->psResItem));
}
return eError;
@ -1443,7 +1443,7 @@ PVRSRV_ERROR SGXUnregisterHWTransferContextKM(IMG_HANDLE hHWTransferContext, IMG
eError = ResManFreeResByPtr(psCleanup->psResItem, bForceCleanup);
if(eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "SGXUnregisterHWTransferContextKM: ResManFreeResByPtr failed %d",eError));
PVR_DPF((PVR_DBG_ERROR, "SGXUnregisterHWTransferContextKM: ResManFreeResByPtr failed %d", eError));
PVR_DPF((PVR_DBG_ERROR, "ResManFreeResByPtr: hResItem 0x%x", (unsigned int)psCleanup->psResItem));
}
return eError;
@ -1783,7 +1783,7 @@ PVRSRV_ERROR SGXUnregisterHW2DContextKM(IMG_HANDLE hHW2DContext, IMG_BOOL bForce
eError = ResManFreeResByPtr(psCleanup->psResItem, bForceCleanup);
if(eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "SGXUnregisterHW2DContextKM: ResManFreeResByPtr failed %d",eError));
PVR_DPF((PVR_DBG_ERROR, "SGXUnregisterHW2DContextKM: ResManFreeResByPtr failed %d", eError));
PVR_DPF((PVR_DBG_ERROR, "ResManFreeResByPtr: hResItem 0x%x", (unsigned int)psCleanup->psResItem));
}
return eError;

4
drivers/gpu/pvr/services4/srvkm/env/linux/event.c vendored
View file

@ -204,7 +204,7 @@ PVRSRV_ERROR LinuxEventObjectDelete(IMG_HANDLE hOSEventObjectList, IMG_HANDLE hO
#endif
if(ResManFreeResByPtr(psLinuxEventObject->hResItem, CLEANUP_WITH_POLL) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "LinuxEventObjectDelete: ResManFreeResByPtr failed %d",PVRSRV_ERROR_UNABLE_TO_DESTROY_EVENT));
PVR_DPF((PVR_DBG_ERROR, "LinuxEventObjectDelete: ResManFreeResByPtr failed %d", PVRSRV_ERROR_UNABLE_TO_DESTROY_EVENT));
PVR_DPF((PVR_DBG_ERROR, "ResManFreeResByPtr: hResItem 0x%x", (unsigned int)psLinuxEventObject->hResItem));
return PVRSRV_ERROR_UNABLE_TO_DESTROY_EVENT;
}
@ -398,7 +398,7 @@ PVRSRV_ERROR LinuxEventObjectWait(IMG_HANDLE hOSEventObject, IMG_UINT32 ui32MSTi
ui32TimeOutJiffies = (IMG_UINT32)schedule_timeout((IMG_INT32)ui32TimeOutJiffies);
LinuxLockMutexNested(&gPVRSRVLock, PVRSRV_LOCK_CLASS_BRIDGE);
LinuxLockMutex(&gPVRSRVLock);
#if defined(DEBUG)
psLinuxEventObject->ui32Stats++;
#endif

253
drivers/gpu/pvr/services4/srvkm/env/linux/ion.c vendored
View file

@ -87,7 +87,7 @@ void PVRSRVExportFDToIONHandles(int fd, struct ion_client **client,
struct file *psFile;
/* Take the bridge mutex so the handle won't be freed underneath us */
LinuxLockMutexNested(&gPVRSRVLock, PVRSRV_LOCK_CLASS_BRIDGE);
LinuxLockMutex(&gPVRSRVLock);
psFile = fget(fd);
if(!psFile)
@ -263,196 +263,161 @@ IMG_VOID IonDeinit(IMG_VOID)
#endif /* defined(CONFIG_ION_OMAP) */
#define MAX_IMPORT_ION_FDS 3
typedef struct _ION_IMPORT_DATA_
{
/* ion client handles are imported into */
struct ion_client *psIonClient;
struct ion_handle *psIonHandle;
IMG_SYS_PHYADDR *pasSysPhysAddr;
IMG_PVOID pvKernAddr;
} ION_IMPORT_DATA;
/* Number of ion handles represented by this import */
IMG_UINT32 ui32NumIonHandles;
/* Array of ion handles in use by services */
struct ion_handle *apsIonHandle[MAX_IMPORT_ION_FDS];
/* Array of physical addresses represented by these buffers */
IMG_SYS_PHYADDR *psSysPhysAddr;
/* If ui32NumBuffers is 1 and ion_map_kernel() is implemented by the
* allocator, this may be non-NULL. Otherwise it will be NULL.
*/
IMG_PVOID pvKernAddr0;
}
ION_IMPORT_DATA;
PVRSRV_ERROR IonImportBufferAndAcquirePhysAddr(IMG_HANDLE hIonDev,
IMG_UINT32 ui32NumFDs,
IMG_INT32 *pai32BufferFDs,
IMG_UINT32 *pui32PageCount,
IMG_SYS_PHYADDR **ppsSysPhysAddr,
IMG_PVOID *ppvKernAddr0,
IMG_HANDLE *phPriv,
IMG_HANDLE *phUnique)
PVRSRV_ERROR IonImportBufferAndAquirePhysAddr(IMG_HANDLE hIonDev,
IMG_HANDLE hIonFD,
IMG_UINT32 *pui32PageCount,
IMG_SYS_PHYADDR **ppasSysPhysAddr,
IMG_PVOID *ppvKernAddr,
IMG_HANDLE *phPriv,
IMG_HANDLE *phUnique)
{
struct scatterlist *psTemp, *psScatterList[MAX_IMPORT_ION_FDS] = {};
PVRSRV_ERROR eError = PVRSRV_ERROR_OUT_OF_MEMORY;
struct ion_client *psIonClient = hIonDev;
IMG_UINT32 i, k, ui32PageCount = 0;
struct ion_handle *psIonHandle;
struct scatterlist *psScatterList;
struct scatterlist *psTemp;
IMG_SYS_PHYADDR *pasSysPhysAddr = NULL;
ION_IMPORT_DATA *psImportData;
PVRSRV_ERROR eError;
IMG_UINT32 ui32PageCount = 0;
IMG_UINT32 i;
IMG_PVOID pvKernAddr;
int fd = (int) hIonFD;
//S.LSI
#if defined (EXYNOS_ION_DMA_BUFFER_FD)
struct sg_table *pSgtable;
struct sg_table *pSgtable;
#endif
if(ui32NumFDs > MAX_IMPORT_ION_FDS)
{
printk(KERN_ERR "%s: More ion export fds passed in than supported "
"(%d provided, %d max)", __func__, ui32NumFDs,
MAX_IMPORT_ION_FDS);
return PVRSRV_ERROR_INVALID_PARAMS;
}
psImportData = kzalloc(sizeof(ION_IMPORT_DATA), GFP_KERNEL);
psImportData = kmalloc(sizeof(ION_IMPORT_DATA), GFP_KERNEL);
if (psImportData == NULL)
{
goto exitFailKMallocImportData;
return PVRSRV_ERROR_OUT_OF_MEMORY;
}
/* Set up import data for free call */
psImportData->psIonClient = psIonClient;
psImportData->ui32NumIonHandles = ui32NumFDs;
for(i = 0; i < ui32NumFDs; i++)
{
int fd = (int)pai32BufferFDs[i];
//S.LSI
#if defined (EXYNOS_ION_DMA_BUFFER_FD)
/* Get the buffer handle */
psImportData->apsIonHandle[i] = ion_import_dma_buf(psIonClient, fd);
if (IS_ERR_OR_NULL(psImportData->apsIonHandle[i]))
{
eError = PVRSRV_ERROR_INVALID_PARAMS;
goto exitFailImport;
}
/* Get the buffer handle */
psIonHandle = ion_import_dma_buf(psIonClient, fd);
#else
psImportData->apsIonHandle[i] = ion_import_fd(psIonClient, fd);
if (psImportData->apsIonHandle[i] == IMG_NULL)
{
eError = PVRSRV_ERROR_BAD_MAPPING;
goto exitFailImport;
}
/* Get the buffer handle */
psIonHandle = ion_import_fd(psIonClient, fd);
#endif
#if defined (EXYNOS_ION_DMA_BUFFER_FD)
pSgtable = ion_sg_table(psIonClient, psImportData->apsIonHandle[i]);
if (IS_ERR_OR_NULL(pSgtable))
{
eError = PVRSRV_ERROR_INVALID_PARAMS;
goto exitFailImport;
}
psScatterList[i] = pSgtable->sgl;
#else
psScatterList[i] = ion_map_dma(psIonClient, psImportData->apsIonHandle[i]);
#endif
if (psScatterList[i] == NULL)
{
eError = PVRSRV_ERROR_INVALID_PARAMS;
goto exitFailImport;
}
for(psTemp = psScatterList[i]; psTemp; psTemp = sg_next(psTemp))
{
IMG_UINT32 j;
for (j = 0; j < psTemp->length; j += PAGE_SIZE)
{
ui32PageCount++;
}
}
}
BUG_ON(ui32PageCount == 0);
psImportData->psSysPhysAddr = kmalloc(sizeof(IMG_SYS_PHYADDR) * ui32PageCount, GFP_KERNEL);
if (psImportData->psSysPhysAddr == NULL)
if (psIonHandle == IMG_NULL)
{
eError = PVRSRV_ERROR_BAD_MAPPING;
goto exitFailImport;
}
for(i = 0, k = 0; i < ui32NumFDs; i++)
/* Create data for free callback */
psImportData->psIonClient = psIonClient;
psImportData->psIonHandle = psIonHandle;
//S.LSI
#if defined (EXYNOS_ION_DMA_BUFFER_FD)
pSgtable = ion_sg_table(psIonClient, psIonHandle);
psScatterList = pSgtable->sgl;
#else
psScatterList = ion_map_dma(psIonClient, psIonHandle);
#endif
if (psScatterList == NULL)
{
for(psTemp = psScatterList[i]; psTemp; psTemp = sg_next(psTemp))
eError = PVRSRV_ERROR_INVALID_PARAMS;
goto exitFailMap;
}
/*
We do a two pass process, 1st workout how many pages there
are, 2nd fill in the data.
*/
for (i=0;i<2;i++)
{
psTemp = psScatterList;
if (i == 1)
{
pasSysPhysAddr = kmalloc(sizeof(IMG_SYS_PHYADDR) * ui32PageCount,
GFP_KERNEL);
if (pasSysPhysAddr == NULL)
{
eError = PVRSRV_ERROR_OUT_OF_MEMORY;
goto exitFailAlloc;
}
ui32PageCount = 0; /* Reset the page count a we use if for the index */
}
while(psTemp)
{
IMG_UINT32 j;
for (j = 0; j < psTemp->length; j += PAGE_SIZE)
for (j=0;j<psTemp->length;j+=PAGE_SIZE)
{
psImportData->psSysPhysAddr[k].uiAddr = sg_phys(psTemp) + j;
k++;
if (i == 1)
{
//S.LSI
/* Pass 2: Get the page data */
pasSysPhysAddr[ui32PageCount].uiAddr = sg_phys(psTemp) + j;
}
ui32PageCount++;
}
psTemp = sg_next(psTemp);
}
}
pvKernAddr = ion_map_kernel(psIonClient, psIonHandle);
if (IS_ERR(pvKernAddr))
{
pvKernAddr = IMG_NULL;
}
psImportData->pvKernAddr = pvKernAddr;
psImportData->pasSysPhysAddr = pasSysPhysAddr;
*ppvKernAddr = pvKernAddr;
*pui32PageCount = ui32PageCount;
*ppsSysPhysAddr = psImportData->psSysPhysAddr;
if(ui32NumFDs == 1)
{
IMG_PVOID pvKernAddr0;
pvKernAddr0 = ion_map_kernel(psIonClient, psImportData->apsIonHandle[0]);
if (IS_ERR(pvKernAddr0))
{
pvKernAddr0 = IMG_NULL;
}
psImportData->pvKernAddr0 = pvKernAddr0;
*ppvKernAddr0 = pvKernAddr0;
}
else
{
*ppvKernAddr0 = NULL;
}
*ppasSysPhysAddr = pasSysPhysAddr;
*phPriv = psImportData;
*phUnique = (IMG_HANDLE)psImportData->psSysPhysAddr[0].uiAddr;
/*
Note:
The only unique thing we can acquire from an ion_buffer
is it's address. The ion_handle we obtain in this function
is only unique to the ion_client.
*/
*phUnique = (IMG_HANDLE)pasSysPhysAddr[0].uiAddr;
return PVRSRV_OK;
exitFailImport:
for(i = 0; psImportData->apsIonHandle[i] != NULL; i++)
{
exitFailAlloc:
//S.LSI
#if defined (EXYNOS_ION_DMA_BUFFER_FD)
#else
if(psScatterList[i])
ion_unmap_dma(psIonClient, psImportData->apsIonHandle[i]);
ion_unmap_dma(psIonClient, psIonHandle);
#endif
ion_free(psIonClient, psImportData->apsIonHandle[i]);
}
exitFailMap:
ion_free(psIonClient, psIonHandle);
exitFailImport:
kfree(psImportData);
exitFailKMallocImportData:
return eError;
}
IMG_VOID IonUnimportBufferAndReleasePhysAddr(IMG_HANDLE hPriv)
{
ION_IMPORT_DATA *psImportData = hPriv;
IMG_UINT32 i;
if (psImportData->pvKernAddr0)
{
ion_unmap_kernel(psImportData->psIonClient, psImportData->apsIonHandle[0]);
}
for(i = 0; i < psImportData->ui32NumIonHandles; i++)
{
//S.LSI
#if defined (EXYNOS_ION_DMA_BUFFER_FD)
#else
ion_unmap_dma(psImportData->psIonClient, psImportData->apsIonHandle[i]);
ion_unmap_dma(psImportData->psIonClient, psImportData->psIonHandle);
#endif
ion_free(psImportData->psIonClient, psImportData->apsIonHandle[i]);
if (psImportData->pvKernAddr)
{
ion_unmap_kernel(psImportData->psIonClient, psImportData->psIonHandle);
}
kfree(psImportData->psSysPhysAddr);
kfree(psImportData->pasSysPhysAddr);
ion_free(psImportData->psIonClient, psImportData->psIonHandle);
kfree(psImportData);
}

15
drivers/gpu/pvr/services4/srvkm/env/linux/ion.h vendored
View file

@ -67,14 +67,13 @@ PVRSRV_ERROR IonInit(IMG_VOID);
IMG_VOID IonDeinit(IMG_VOID);
PVRSRV_ERROR IonImportBufferAndAcquirePhysAddr(IMG_HANDLE hIonDev,
IMG_UINT32 ui32NumFDs,
IMG_INT32 *pi32BufferFDs,
IMG_UINT32 *pui32PageCount,
IMG_SYS_PHYADDR **ppsSysPhysAddr,
IMG_PVOID *ppvKernAddr0,
IMG_HANDLE *phPriv,
IMG_HANDLE *phUnique);
PVRSRV_ERROR IonImportBufferAndAquirePhysAddr(IMG_HANDLE hIonDev,
IMG_HANDLE hIonFD,
IMG_UINT32 *pui32PageCount,
IMG_SYS_PHYADDR **ppasSysPhysAddr,
IMG_PVOID *ppvKernAddr,
IMG_HANDLE *phPriv,
IMG_HANDLE *phUnique);
IMG_VOID IonUnimportBufferAndReleasePhysAddr(IMG_HANDLE hPriv);

16
drivers/gpu/pvr/services4/srvkm/env/linux/mm.c vendored
View file

@ -328,7 +328,7 @@ DebugMemAllocRecordAdd(DEBUG_MEM_ALLOC_TYPE eAllocType,
LinuxLockMutex(&g_sDebugMutex);
psRecord = kmalloc(sizeof(DEBUG_MEM_ALLOC_REC), GFP_KERNEL);
if(!psRecord)
if (!psRecord)
return;
psRecord->eAllocType = eAllocType;
@ -2598,14 +2598,14 @@ static void ProcSeqShowMemArea(struct seq_file *sfile,void* el)
seq_printf(sfile,
#if !defined(DEBUG_LINUX_XML_PROC_FILES)
"%p %-24s %p " CPUPADDR_FMT " %" SIZE_T_FMT_LEN "u %-5u %08x=(%s)\n",
"%p %-24s %p " CPUPADDR_FMT " %u %-5u %08x=(%s)\n",
#else
"<linux_mem_area>\n"
"\t<pointer>%p</pointer>\n"
"\t<type>%s</type>\n"
"\t<cpu_virtual>%p</cpu_virtual>\n"
"\t<cpu_physical>" CPUPADDR_FMT "</cpu_physical>\n"
"\t<bytes>%" SIZE_T_FMT_LEN "d</bytes>\n"
"\t<bytes>%ld</bytes>\n"
"\t<pid>%u</pid>\n"
"\t<flags>%08x</flags>\n"
"\t<flags_string>%s</flags_string>\n"
@ -2846,13 +2846,13 @@ static void ProcSeqShowMemoryRecords(struct seq_file *sfile,void* el)
{
seq_printf(sfile,
#if !defined(DEBUG_LINUX_XML_PROC_FILES)
"%-16s %p " CPUPADDR_FMT " %" SIZE_T_FMT_LEN "u %-5d %-10s %s:%d\n",
"%-16s %p " CPUPADDR_FMT " %u %-5d %-10s %s:%d\n",
#else
"<allocation>\n"
"\t<type>%s</type>\n"
"\t<cpu_virtual>%p</cpu_virtual>\n"
"\t<cpu_physical>" CPUPADDR_FMT "</cpu_physical>\n"
"\t<bytes>%" SIZE_T_FMT_LEN "u</bytes>\n"
"\t<bytes>%u</bytes>\n"
"\t<pid>%d</pid>\n"
"\t<private>%s</private>\n"
"\t<filename>%s</filename>\n"
@ -2872,13 +2872,13 @@ static void ProcSeqShowMemoryRecords(struct seq_file *sfile,void* el)
{
seq_printf(sfile,
#if !defined(DEBUG_LINUX_XML_PROC_FILES)
"%-16s %p " CPUPADDR_FMT " %" SIZE_T_FMT_LEN "u %-5d %-10s %s:%d\n",
"%-16s %p " CPUPADDR_FMT " %u %-5d %-10s %s:%d\n",
#else
"<allocation>\n"
"\t<type>%s</type>\n"
"\t<cpu_virtual>%p</cpu_virtual>\n"
"\t<cpu_physical>" CPUPADDR_FMT "</cpu_physical>\n"
"\t<bytes>%" SIZE_T_FMT_LEN "u</bytes>\n"
"\t<bytes>%u</bytes>\n"
"\t<pid>%d</pid>\n"
"\t<private>%s</private>\n"
"\t<filename>%s</filename>\n"
@ -2978,7 +2978,7 @@ static IMG_VOID LinuxMMCleanup_MemAreas_ForEachCb(DEBUG_LINUX_MEM_AREA_REC *psCu
LinuxMemArea *psLinuxMemArea;
psLinuxMemArea = psCurrentRecord->psLinuxMemArea;
PVR_DPF((PVR_DBG_ERROR, "%s: BUG!: Cleaning up Linux memory area (%p), type=%s, size=%"SIZE_T_FMT_LEN"d bytes",
PVR_DPF((PVR_DBG_ERROR, "%s: BUG!: Cleaning up Linux memory area (%p), type=%s, size=%d bytes",
__FUNCTION__,
psCurrentRecord->psLinuxMemArea,
LinuxMemAreaTypeToString(psCurrentRecord->psLinuxMemArea->eAreaType),

28
drivers/gpu/pvr/services4/srvkm/env/linux/mmap.c vendored
View file

@ -409,7 +409,7 @@ PVRMMapOSMemHandleToMMapData(PVRSRV_PER_PROCESS_DATA *psPerProc,
IMG_HANDLE hOSMemHandle;
PVRSRV_ERROR eError;
LinuxLockMutexNested(&g_sMMapMutex, PVRSRV_LOCK_CLASS_MMAP);
LinuxLockMutex(&g_sMMapMutex);
PVR_ASSERT(PVRSRVGetMaxHandle(psPerProc->psHandleBase) <= MAX_MMAP_HANDLE);
@ -547,7 +547,7 @@ PVRMMapReleaseMMapData(PVRSRV_PER_PROCESS_DATA *psPerProc,
PVRSRV_ERROR eError;
IMG_UINT32 ui32PID = OSGetCurrentProcessIDKM();
LinuxLockMutexNested(&g_sMMapMutex, PVRSRV_LOCK_CLASS_MMAP);
LinuxLockMutex(&g_sMMapMutex);
PVR_ASSERT(PVRSRVGetMaxHandle(psPerProc->psHandleBase) <= MAX_MMAP_HANDLE);
@ -860,7 +860,7 @@ MMapVOpenNoLock(struct vm_area_struct* ps_vma)
static void
MMapVOpen(struct vm_area_struct* ps_vma)
{
LinuxLockMutexNested(&g_sMMapMutex, PVRSRV_LOCK_CLASS_MMAP);
LinuxLockMutex(&g_sMMapMutex);
MMapVOpenNoLock(ps_vma);
@ -947,7 +947,7 @@ static int MMapVAccess(struct vm_area_struct *ps_vma, unsigned long addr,
int iRetVal = -EINVAL;
IMG_VOID *pvKernelAddr;
LinuxLockMutexNested(&g_sMMapMutex, PVRSRV_LOCK_CLASS_MMAP);
LinuxLockMutex(&g_sMMapMutex);
psOffsetStruct = (PKV_OFFSET_STRUCT)ps_vma->vm_private_data;
psLinuxMemArea = psOffsetStruct->psLinuxMemArea;
@ -1033,12 +1033,12 @@ PVRMMap(struct file* pFile, struct vm_area_struct* ps_vma)
PVR_UNREFERENCED_PARAMETER(pFile);
LinuxLockMutexNested(&g_sMMapMutex, PVRSRV_LOCK_CLASS_MMAP);
LinuxLockMutex(&g_sMMapMutex);
uiByteSize = ps_vma->vm_end - ps_vma->vm_start;
PVR_DPF((PVR_DBG_MESSAGE, "%s: Received mmap(2) request with ui32MMapOffset 0x" UINTPTR_FMT ","
" and uiByteSize %" SIZE_T_FMT_LEN "u(0x%" SIZE_T_FMT_LEN "x)",
" and uiByteSize %u(0x%x)",
__FUNCTION__,
ps_vma->vm_pgoff,
uiByteSize,
@ -1223,7 +1223,7 @@ static void ProcSeqStartstopMMapRegistations(struct seq_file *sfile,IMG_BOOL sta
{
if(start)
{
LinuxLockMutexNested(&g_sMMapMutex, PVRSRV_LOCK_CLASS_MMAP);
LinuxLockMutex(&g_sMMapMutex);
}
else
{
@ -1301,7 +1301,7 @@ static void ProcSeqShowMMapRegistrations(struct seq_file *sfile, void *el)
seq_printf( sfile,
#if !defined(DEBUG_LINUX_XML_PROC_FILES)
"Allocations registered for mmap: %u\n"
"In total these areas correspond to %" SIZE_T_FMT_LEN "u bytes\n"
"In total these areas correspond to %u bytes\n"
"psLinuxMemArea "
"UserVAddr "
"KernelVAddr "
@ -1313,7 +1313,7 @@ static void ProcSeqShowMMapRegistrations(struct seq_file *sfile, void *el)
#else
"<mmap_header>\n"
"\t<count>%u</count>\n"
"\t<bytes>%" SIZE_T_FMT_LEN "u</bytes>\n"
"\t<bytes>%u</bytes>\n"
"</mmap_header>\n",
#endif
g_ui32RegisteredAreas,
@ -1330,7 +1330,7 @@ static void ProcSeqShowMMapRegistrations(struct seq_file *sfile, void *el)
seq_printf( sfile,
#if !defined(DEBUG_LINUX_XML_PROC_FILES)
"%p %p %p " CPUPADDR_FMT " " UINTPTR_FMT " %" SIZE_T_FMT_LEN "u %-24s %-5u %-8s %08x(%s)\n",
"%p %p %p " CPUPADDR_FMT " " UINTPTR_FMT " %u %-24s %-5u %-8s %08x(%s)\n",
#else
"<mmap_record>\n"
"\t<pointer>%p</pointer>\n"
@ -1338,7 +1338,7 @@ static void ProcSeqShowMMapRegistrations(struct seq_file *sfile, void *el)
"\t<kernel_virtual>%p</kernel_virtual>\n"
"\t<cpu_physical>" CPUPADDR_FMT "</cpu_physical>\n"
"\t<mmap_offset>" UINTPTR_FMT "</mmap_offset>\n"
"\t<bytes>%" SIZE_T_FMT_LEN "u</bytes>\n"
"\t<bytes>%u</bytes>\n"
"\t<linux_mem_area_type>%-24s</linux_mem_area_type>\n"
"\t<pid>%-5u</pid>\n"
"\t<name>%-8s</name>\n"
@ -1384,7 +1384,7 @@ PVRMMapRegisterArea(LinuxMemArea *psLinuxMemArea)
const IMG_CHAR *pszName = LinuxMemAreaTypeToString(LinuxMemAreaRootType(psLinuxMemArea));
#endif
LinuxLockMutexNested(&g_sMMapMutex, PVRSRV_LOCK_CLASS_MMAP);
LinuxLockMutex(&g_sMMapMutex);
#if defined(DEBUG) || defined(DEBUG_LINUX_MMAP_AREAS)
PVR_DPF((PVR_DBG_MESSAGE,
@ -1449,7 +1449,7 @@ PVRMMapRemoveRegisteredArea(LinuxMemArea *psLinuxMemArea)
PVRSRV_ERROR eError;
PKV_OFFSET_STRUCT psOffsetStruct, psTmpOffsetStruct;
LinuxLockMutexNested(&g_sMMapMutex, PVRSRV_LOCK_CLASS_MMAP);
LinuxLockMutex(&g_sMMapMutex);
PVR_ASSERT(psLinuxMemArea->bMMapRegistered);
@ -1549,7 +1549,7 @@ LinuxMMapPerProcessDisconnect(PVRSRV_ENV_PER_PROCESS_DATA *psEnvPerProc)
PVR_UNREFERENCED_PARAMETER(psEnvPerProc);
LinuxLockMutexNested(&g_sMMapMutex, PVRSRV_LOCK_CLASS_MMAP);
LinuxLockMutex(&g_sMMapMutex);
list_for_each_entry_safe(psOffsetStruct, psTmpOffsetStruct, &g_sMMapOffsetStructList, sMMapItem)
{

41
drivers/gpu/pvr/services4/srvkm/env/linux/module.c vendored
View file

@ -148,7 +148,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "linkage.h"
#include "buffer_manager.h"
#include "secutils.h"
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
#if defined(SUPPORT_ANDROID_SYNC)
#include "pvr_sync.h"
#endif
@ -204,6 +204,7 @@ IMG_UINT32 gPVRSuspendNotifier;
#include <linux/omap_ion.h>
extern struct ion_device *omap_ion_device;
struct ion_client *gpsIONClient;
EXPORT_SYMBOL(gpsIONClient);
#endif /* defined(CONFIG_ION_OMAP) */
/* PRQA S 3207 2 */ /* ignore 'not used' warning */
@ -431,11 +432,10 @@ extern IMG_BOOL bEnableMIFMornitering;
extern int exynos5_mif_register_notifier(struct notifier_block *n);
static int exynos_g3d_mif_notifier(struct notifier_block *notifier, unsigned long event, void *v)
{
if(event == MIF_DEVFREQ_EN_MONITORING) {
if (event == MIF_DEVFREQ_EN_MONITORING) {
PVR_LOG(("exynos_g3d_mif_notifier: MIF_DEVFREQ_EN_MONITORING"));
bEnableMIFMornitering = true;
}
else if(event == MIF_DEVFREQ_DIS_MONITORING) {
} else if (event == MIF_DEVFREQ_DIS_MONITORING) {
PVR_LOG(("exynos_g3d_mif_notifier: MIF_DEVFREQ_DIS_MONITORING"));
bEnableMIFMornitering = false;
}
@ -608,7 +608,7 @@ PVR_MOD_STATIC void PVRSRVDriverShutdown(LDM_DEV *pDevice)
* processes trying to use the driver after it has been
* shutdown.
*/
LinuxLockMutexNested(&gPVRSRVLock, PVRSRV_LOCK_CLASS_BRIDGE);
LinuxLockMutex(&gPVRSRVLock);
(void) PVRSRVSetPowerStateKM(PVRSRV_SYS_POWER_STATE_D1);
}
@ -669,7 +669,7 @@ PVR_MOD_STATIC int PVRSRVDriverSuspend(struct device *pDevice)
if (!bDriverIsSuspended && !bDriverIsShutdown)
{
LinuxLockMutexNested(&gPVRSRVLock, PVRSRV_LOCK_CLASS_BRIDGE);
LinuxLockMutex(&gPVRSRVLock);
if (PVRSRVSetPowerStateKM(PVRSRV_SYS_POWER_STATE_D3) == PVRSRV_OK)
{
@ -860,7 +860,7 @@ static int PVRSRVOpen(struct inode unref__ * pInode, struct file *pFile)
PVRSRV_ENV_PER_PROCESS_DATA *psEnvPerProc;
#endif
LinuxLockMutexNested(&gPVRSRVLock, PVRSRV_LOCK_CLASS_BRIDGE);
LinuxLockMutex(&gPVRSRVLock);
ui32PID = OSGetCurrentProcessIDKM();
@ -927,7 +927,7 @@ static int PVRSRVRelease(struct inode unref__ * pInode, struct file *pFile)
PVRSRV_FILE_PRIVATE_DATA *psPrivateData;
int err = 0;
LinuxLockMutexNested(&gPVRSRVLock, PVRSRV_LOCK_CLASS_BRIDGE);
LinuxLockMutex(&gPVRSRVLock);
#if defined(SUPPORT_DRI_DRM)
psPrivateData = (PVRSRV_FILE_PRIVATE_DATA *)pvPrivData;
@ -1047,7 +1047,9 @@ static int __init PVRCore_Init(void)
struct device *psDev;
#endif
#if defined(SUPPORT_ANDROID_SYNC)
PVRSyncDeviceInit();
#endif
#if !defined(SUPPORT_DRI_DRM)
/*
@ -1058,9 +1060,7 @@ static int __init PVRCore_Init(void)
#endif
PVR_TRACE(("PVRCore_Init"));
#if defined(PVR_LDM_MODULE) || defined(SUPPORT_DRI_DRM)
LinuxInitMutex(&gsPMMutex);
#endif
LinuxInitMutex(&gPVRSRVLock);
if (CreateProcEntries ())
@ -1110,16 +1110,6 @@ static int __init PVRCore_Init(void)
#if defined(CONFIG_ARM_EXYNOS5410_BUS_DEVFREQ)
exynos5_mif_register_notifier(&exynos_mif_nb);
#endif
#if defined(MODULE) && !defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV)
if ((error = platform_device_register(&powervr_device)) != 0)
{
platform_driver_unregister(&powervr_driver);
PVR_DPF((PVR_DBG_ERROR, "PVRCore_Init: unable to register platform device (%d)", error));
goto init_failed;
}
#endif
#endif /* PVR_LDM_PLATFORM_MODULE */
#if defined(PVR_LDM_PCI_MODULE)
@ -1197,9 +1187,6 @@ static int __init PVRCore_Init(void)
#endif /* defined(PVR_LDM_DEVICE_CLASS) */
#endif /* !defined(SUPPORT_DRI_DRM) */
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
PVRSyncDeviceInit();
#endif
return 0;
#if !defined(SUPPORT_DRI_DRM)
@ -1220,9 +1207,7 @@ sys_deinit:
/*S.LSI*/
#if defined (PVR_LDM_PLATFORM_MODULE)
#if defined(MODULE) && !defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV)
platform_device_unregister(&powervr_device);
#endif
platform_driver_unregister(&powervr_driver);
#endif
#ifdef CONFIG_PM_RUNTIME
@ -1294,7 +1279,7 @@ static void __exit PVRCore_Cleanup(void)
SysAcquireData(&psSysData);
#endif
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
#if defined(SUPPORT_ANDROID_SYNC)
PVRSyncDeviceDeInit();
#endif
@ -1327,9 +1312,7 @@ static void __exit PVRCore_Cleanup(void)
/*S.LSI*/
#if defined (PVR_LDM_PLATFORM_MODULE)
#if defined(MODULE) && !defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV)
platform_device_unregister(&powervr_device);
#endif
platform_driver_unregister(&powervr_driver);
#endif

10
drivers/gpu/pvr/services4/srvkm/env/linux/mutex.c vendored
View file

@ -66,11 +66,6 @@ IMG_VOID LinuxLockMutex(PVRSRV_LINUX_MUTEX *psPVRSRVMutex)
mutex_lock(psPVRSRVMutex);
}
IMG_VOID LinuxLockMutexNested(PVRSRV_LINUX_MUTEX *psPVRSRVMutex, unsigned int uiLockClass)
{
mutex_lock_nested(psPVRSRVMutex, uiLockClass);
}
PVRSRV_ERROR LinuxLockMutexInterruptible(PVRSRV_LINUX_MUTEX *psPVRSRVMutex)
{
if(mutex_lock_interruptible(psPVRSRVMutex) == -EINTR)
@ -114,11 +109,6 @@ IMG_VOID LinuxLockMutex(PVRSRV_LINUX_MUTEX *psPVRSRVMutex)
atomic_dec(&psPVRSRVMutex->Count);
}
IMG_VOID LinuxLockMutexNested(PVRSRV_LINUX_MUTEX *psPVRSRVMutex, unsigned int uiLockClass)
{
LinuxLockMutex(psPVRSRVMutex);
}
PVRSRV_ERROR LinuxLockMutexInterruptible(PVRSRV_LINUX_MUTEX *psPVRSRVMutex)
{
if(down_interruptible(&psPVRSRVMutex->sSemaphore) == -EINTR)

7
drivers/gpu/pvr/services4/srvkm/env/linux/mutex.h vendored
View file

@ -72,18 +72,11 @@ typedef struct {
#endif
enum PVRSRV_MUTEX_LOCK_CLASS
{
PVRSRV_LOCK_CLASS_BRIDGE,
PVRSRV_LOCK_CLASS_MMAP,
};
extern IMG_VOID LinuxInitMutex(PVRSRV_LINUX_MUTEX *psPVRSRVMutex);
extern IMG_VOID LinuxLockMutex(PVRSRV_LINUX_MUTEX *psPVRSRVMutex);
extern IMG_VOID LinuxLockMutexNested(PVRSRV_LINUX_MUTEX *psPVRSRVMutex, unsigned int uiLockClass);
extern PVRSRV_ERROR LinuxLockMutexInterruptible(PVRSRV_LINUX_MUTEX *psPVRSRVMutex);
extern IMG_INT32 LinuxTryLockMutex(PVRSRV_LINUX_MUTEX *psPVRSRVMutex);

20
drivers/gpu/pvr/services4/srvkm/env/linux/osfunc.c vendored
View file

@ -89,7 +89,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "linkage.h"
#include "pvr_uaccess.h"
#include "lock.h"
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
#if defined(SUPPORT_ANDROID_SYNC)
#include "pvr_sync.h"
#endif
@ -117,7 +117,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#if defined(EMULATOR)
#define EVENT_OBJECT_TIMEOUT_MS (2000)
#else
#define EVENT_OBJECT_TIMEOUT_MS (100)
#define EVENT_OBJECT_TIMEOUT_MS (300)
#endif /* EMULATOR */
#if !defined(DEBUG_LINUX_MEMORY_ALLOCATIONS)
@ -306,7 +306,6 @@ ExitSkipSwitch:
*phOSMemHandle = psLinuxMemArea;
LinuxMemAreaRegister(psLinuxMemArea);
/* S.LSI */
psLinuxMemArea->bDeferredFree = IMG_FALSE;
return PVRSRV_OK;
@ -1129,9 +1128,10 @@ static void MISRWrapper(
PVRSRVMISR(psSysData);
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
#if defined(SUPPORT_ANDROID_SYNC)
PVRSyncUpdateAllSyncs();
#endif
}
@ -1847,7 +1847,7 @@ OSUnRegisterMem (IMG_VOID *pvCpuVAddr,
eError = PVRMMapRemoveRegisteredArea(psLinuxMemArea);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "%s(%p, %" SIZE_T_FMT_LEN "u, 0x%08X, %p) FAILED!",
PVR_DPF((PVR_DBG_ERROR, "%s(%p, %u, 0x%08X, %p) FAILED!",
__FUNCTION__, pvCpuVAddr, uiBytes,
ui32MappingFlags, hOSMemHandle));
return eError;
@ -2005,7 +2005,7 @@ OSUnReservePhys(IMG_VOID *pvCpuVAddr,
eError = PVRMMapRemoveRegisteredArea(psLinuxMemArea);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "%s(%p, %" SIZE_T_FMT_LEN "u, 0x%08X, %p) FAILED!",
PVR_DPF((PVR_DBG_ERROR, "%s(%p, %u, 0x%08X, %p) FAILED!",
__FUNCTION__, pvCpuVAddr, uiBytes,
ui32MappingFlags, hOSMemHandle));
return eError;
@ -3559,8 +3559,8 @@ PVRSRV_ERROR OSAcquirePhysPageAddr(IMG_VOID *pvCPUVAddr,
if (uBeyondEndAddr <= uStartAddr)
{
PVR_DPF((PVR_DBG_ERROR,
"OSAcquirePhysPageAddr: Invalid address range (start " UINTPTR_FMT ", length %" SIZE_T_FMT_LEN "x)",
uStartAddrOrig, uAddrRangeOrig));
"OSAcquirePhysPageAddr: Invalid address range (start %x length %d)",
(unsigned int)uStartAddrOrig, uAddrRangeOrig));
goto error;
}
@ -3997,7 +3997,7 @@ IMG_BOOL CheckExecuteCacheOp(IMG_HANDLE hOSMemHandle,
PVR_ASSERT(psLinuxMemArea != IMG_NULL);
LinuxLockMutexNested(&g_sMMapMutex, PVRSRV_LOCK_CLASS_MMAP);
LinuxLockMutex(&g_sMMapMutex);
psMMapOffsetStructList = &psLinuxMemArea->sMMapOffsetStructList;
uiAreaLength = psLinuxMemArea->uiByteSize;
@ -4529,7 +4529,7 @@ IMG_VOID OSReleaseBridgeLock(IMG_VOID)
IMG_VOID OSReacquireBridgeLock(IMG_VOID)
{
LinuxLockMutexNested(&gPVRSRVLock, PVRSRV_LOCK_CLASS_BRIDGE);
LinuxLockMutex(&gPVRSRVLock);
}
typedef struct _OSTime

18
drivers/gpu/pvr/services4/srvkm/env/linux/osperproc.c vendored
View file

@ -87,21 +87,9 @@ PVRSRV_ERROR OSPerProcessPrivateDataInit(IMG_HANDLE *phOsPrivateData)
#if defined(SUPPORT_ION)
OSSNPrintf(psEnvPerProc->azIonClientName, ION_CLIENT_NAME_SIZE, "pvr_ion_client-%d", OSGetCurrentProcessIDKM());
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,4,39)
psEnvPerProc->psIONClient =
ion_client_create(gpsIonDev, psEnvPerProc->azIonClientName);
#else
psEnvPerProc->psIONClient =
ion_client_create(gpsIonDev,
#if defined(CONFIG_ION_OMAP)
/*1 << ION_HEAP_TYPE_SYSTEM_CONTIG |*/
1 << ION_HEAP_TYPE_SYSTEM
| 1 << OMAP_ION_HEAP_TYPE_TILER
#else /* defined(CONFIG_ION_OMAP) */
-1
#endif /* defined(CONFIG_ION_OMAP) */
, psEnvPerProc->azIonClientName);
#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3,4,39) */
psEnvPerProc->psIONClient =
ion_client_create(gpsIonDev, -1,
psEnvPerProc->azIonClientName);
if (IS_ERR_OR_NULL(psEnvPerProc->psIONClient))
{

4
drivers/gpu/pvr/services4/srvkm/env/linux/pvr_bridge_k.c vendored
View file

@ -141,7 +141,7 @@ static void ProcSeqStartstopBridgeStats(struct seq_file *sfile,IMG_BOOL start)
{
if(start)
{
LinuxLockMutexNested(&gPVRSRVLock, PVRSRV_LOCK_CLASS_BRIDGE);
LinuxLockMutex(&gPVRSRVLock);
}
else
{
@ -253,7 +253,7 @@ PVRSRV_BridgeDispatchKM(struct file *pFile, unsigned int unref__ ioctlCmd, unsig
PVRSRV_PER_PROCESS_DATA *psPerProc;
IMG_INT err = -EFAULT;
LinuxLockMutexNested(&gPVRSRVLock, PVRSRV_LOCK_CLASS_BRIDGE);
LinuxLockMutex(&gPVRSRVLock);
#if defined(SUPPORT_DRI_DRM)
psBridgePackageKM = (PVRSRV_BRIDGE_PACKAGE *)arg;

1775
drivers/gpu/pvr/services4/srvkm/env/linux/pvr_sync.c vendored
View file

File diff suppressed because it is too large Load diff

35
drivers/gpu/pvr/services4/srvkm/env/linux/pvr_sync.h vendored
View file

@ -45,28 +45,33 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef _PVR_SYNC_H
#define _PVR_SYNC_H
#include <linux/seq_file.h>
#include <linux/types.h>
#include <linux/sync.h>
#include "services_headers.h"
#include "pvr_sync_user.h"
#include "servicesint.h" // PVRSRV_DEVICE_SYNC_OBJECT
#include "handle.h"
/* services4 internal interface */
struct PVR_SYNC_TIMELINE
{
struct sync_timeline obj;
struct list_head sTimelineList; /* Used to keep a global list of all timelines for checking status */
};
struct PVR_SYNC
{
struct sync_pt pt;
/* S.LSI */
IMG_UINT32 magic;
PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
};
/* Prototypes */
int PVRSyncDeviceInit(void);
void PVRSyncDeviceDeInit(void);
void PVRSyncUpdateAllSyncs(void);
PVRSRV_ERROR
PVRSyncPatchCCBKickSyncInfos(IMG_HANDLE ahSyncs[SGX_MAX_SRC_SYNCS_TA],
PVRSRV_DEVICE_SYNC_OBJECT asDevSyncs[SGX_MAX_SRC_SYNCS_TA],
IMG_UINT32 *pui32NumSrcSyncs);
PVRSRV_ERROR
PVRSyncPatchTransferSyncInfos(IMG_HANDLE ahSyncs[SGX_MAX_SRC_SYNCS_TA],
PVRSRV_DEVICE_SYNC_OBJECT asDevSyncs[SGX_MAX_SRC_SYNCS_TA],
IMG_UINT32 *pui32NumSrcSyncs);
PVRSRV_ERROR
PVRSyncFencesToSyncInfos(PVRSRV_KERNEL_SYNC_INFO *apsSyncs[],
IMG_UINT32 *pui32NumSyncs,
struct sync_fence *apsFence[SGX_MAX_SRC_SYNCS_TA]);
struct PVR_SYNC_TIMELINE *PVRSyncCreateTimeline(const IMG_CHAR *name);
struct sync_pt *PVRSyncCreateSync(struct PVR_SYNC_TIMELINE *obj,
PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo);
#endif /* _PVR_SYNC_H */

0
drivers/gpu/pvr/services4/srvkm/env/linux/-pvr_sync_user.h → drivers/gpu/pvr/services4/srvkm/env/linux/pvr_sync_user.h vendored
View file

24
drivers/gpu/pvr/services4/srvkm/hwdefs/sgxerrata.h
View file

@ -216,6 +216,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */
#define FIX_HW_BRN_31278/* disabled prefetching in MMU */
#define FIX_HW_BRN_31542/* workaround in uKernel and Services */
#if defined(SGX_FEATURE_MP)
#define FIX_HW_BRN_31559/* workaround in services and uKernel */
#endif
#define FIX_HW_BRN_31620/* workaround in services */
#define FIX_HW_BRN_31780/* workaround in uKernel */
#define FIX_HW_BRN_32044 /* workaround in uKernel, services and client drivers */
@ -232,6 +235,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define FIX_HW_BRN_31195/* workaround in services */
#define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */
#define FIX_HW_BRN_31278/* disabled prefetching in MMU */
#if defined(SGX_FEATURE_MP)
#define FIX_HW_BRN_31559/* workaround in services and uKernel */
#endif
#define FIX_HW_BRN_31542/* workaround in uKernel and Services */
#define FIX_HW_BRN_31671/* workaround in uKernel */
#define FIX_HW_BRN_31780/* workaround in uKernel */
@ -246,6 +252,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#else
#if SGX_CORE_REV == 141
#define FIX_HW_BRN_29954/* turns off regbank split feature */
#if defined(SGX_FEATURE_MP)
#define FIX_HW_BRN_31559/* workaround in services and uKernel */
#endif
#define FIX_HW_BRN_31671 /* workaround in uKernel */
#define FIX_HW_BRN_31780/* workaround in uKernel */
#if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP)
@ -256,6 +265,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#else
#if SGX_CORE_REV == 142
#define FIX_HW_BRN_29954/* turns off regbank split feature */
#if defined(SGX_FEATURE_MP)
#define FIX_HW_BRN_31559/* workaround in services and uKernel */
#endif
#define FIX_HW_BRN_31671 /* workaround in uKernel */
#define FIX_HW_BRN_31780/* workaround in uKernel */
#if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP)
@ -271,6 +283,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */
#define FIX_HW_BRN_31278/* disabled prefetching in MMU */
#define FIX_HW_BRN_31542/* workaround in uKernel and Services */
#if defined(SGX_FEATURE_MP)
#define FIX_HW_BRN_31559/* workaround in services and uKernel */
#endif
#define FIX_HW_BRN_31620/* workaround in services */
#define FIX_HW_BRN_31780/* workaround in uKernel */
#define FIX_HW_BRN_32044 /* workaround in uKernel, services and client drivers */
@ -284,6 +299,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#else
#if SGX_CORE_REV == 213
#define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */
#if defined(SGX_FEATURE_MP)
#define FIX_HW_BRN_31559/* workaround in services and uKernel */
#endif
#define FIX_HW_BRN_31671 /* workaround in uKernel */
#define FIX_HW_BRN_31780/* workaround in uKernel */
#define FIX_HW_BRN_32085 /* workaround in services: prefetch fix applied, investigating PT based fix */
@ -346,6 +364,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define FIX_HW_BRN_31195/* workaround in services */
#define FIX_HW_BRN_31272/* workaround in services (srvclient) and uKernel */
#define FIX_HW_BRN_31278/* disabled prefetching in MMU */
#if defined(SGX_FEATURE_MP)
#define FIX_HW_BRN_31559/* workaround in services and uKernel */
#endif
#define FIX_HW_BRN_31542 /* workaround in uKernel and Services */
#define FIX_HW_BRN_31620/* workaround in services */
#define FIX_HW_BRN_31671 /* workaround in uKernel */
@ -359,6 +380,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define FIX_HW_BRN_36513 /* workaround in uKernel and Services */
#else
#if SGX_CORE_REV == 105
#if defined(SGX_FEATURE_MP)
#define FIX_HW_BRN_31559/* workaround in services and uKernel */
#endif
#define FIX_HW_BRN_31780/* workaround in uKernel */
#if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP)
#define FIX_HW_BRN_33657/* workaround in ukernel*/

6
drivers/gpu/pvr/services4/srvkm/include/osfunc.h
View file

@ -768,12 +768,6 @@ static INLINE IMG_VOID OSGetCurrentProcessNameKM(IMG_CHAR *pszName, IMG_UINT32 u
#endif
#if defined(__linux__) && defined(DEBUG)
#define OSDumpStack dump_stack
#else
#define OSDumpStack()
#endif
#if defined (__cplusplus)
}
#endif

8
drivers/gpu/pvr/services4/srvkm/include/queue.h
View file

@ -75,11 +75,6 @@ extern "C" {
IMG_UINT32 ui32AllocSize; /*!< allocated size*/
PFN_QUEUE_COMMAND_COMPLETE pfnCommandComplete; /*!< Command complete callback */
IMG_HANDLE hCallbackData; /*!< Command complete callback data */
#if defined(PVR_ANDROID_NATIVE_WINDOW_HAS_SYNC)
IMG_VOID *pvCleanupFence; /*!< Sync fence to 'put' after timeline inc() */
IMG_VOID *pvTimeline; /*!< Android sync timeline to inc() */
#endif
}COMMAND_COMPLETE_DATA, *PCOMMAND_COMPLETE_DATA;
#if !defined(USE_CODE)
@ -113,8 +108,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVInsertCommandKM(PVRSRV_QUEUE_INFO *psQueue,
PVRSRV_KERNEL_SYNC_INFO *apsSrcSync[],
IMG_SIZE_T ui32DataByteSize,
PFN_QUEUE_COMMAND_COMPLETE pfnCommandComplete,
IMG_HANDLE hCallbackData,
IMG_HANDLE *phFence);
IMG_HANDLE hCallbackData);
IMG_IMPORT
PVRSRV_ERROR IMG_CALLCONV PVRSRVGetQueueSpaceKM(PVRSRV_QUEUE_INFO *psQueue,

13
drivers/gpu/pvr/services4/system/exynos5410/sec_clock.c
View file

@ -5,13 +5,13 @@
*
* Samsung SoC SGX clock driver
*
* This software is proprietary of Samsung Electronics.
* This software is proprietary of Samsung Electronics.
* No part of this software, either material or conceptual may be copied or distributed, transmitted,
* transcribed, stored in a retrieval system or translated into any human or computer language in any form by any means,
* electronic, mechanical, manual or otherwise, or disclosed
* to third parties without the express written permission of Samsung Electronics.
*
* Alternatively, this program is free software in case of Linux Kernel;
* Alternatively, this program is free software in case of Linux Kernel;
* you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
@ -37,7 +37,7 @@ void __iomem *sgx_bts_base;
unsigned int sgx_clk_status;
#endif
#define DEBUG_BW
//#define DEBUG_BW
/* clock control */
static struct clk *sgx_core;
@ -266,8 +266,9 @@ void gpu_clock_disable()
/*this function using for DVFS*/
void gpu_clock_set(int sgx_clk)
{
#ifdef DEBUG_BW
int old_clk = clk_get_rate(g3d_clock_core)/MHZ;
#endif
if (clk_get_rate(fout_vpll_clock)/MHZ != sgx_clk)
sgx_gpu_src_clk = clk_set_rate(fout_vpll_clock, sgx_clk * MHZ);
@ -294,10 +295,10 @@ void gpu_clock_set(int sgx_clk)
else
bts = 0;
PVR_LOG(("SGX change clock [%d] Mhz -> [%d] MHz req [%d] MHz / M[%d] / B[%d]", old_clk, sgx_gpu_clk, sgx_clk, (800/mif_sdiv), bts));
PVR_LOG(("SGX change clock [%d] Mhz -> [%d] MHz req [%d] MHz / M[%d] / B[%d]", old_clk, sgx_gpu_clk, sgx_clk, (800 / mif_sdiv), bts));
}
#else
PVR_LOG(("SGX change clock [%d] Mhz -> [%d] MHz req [%d] MHz / M[%d]", old_clk, sgx_gpu_clk, sgx_clk, (800/mif_sdiv)));
PVR_LOG(("SGX change clock [%d] Mhz -> [%d] MHz req [%d] MHz / M[%d]", old_clk, sgx_gpu_clk, sgx_clk, (800 / mif_sdiv)));
#endif
}
#endif

50
drivers/gpu/pvr/services4/system/exynos5410/sec_control_pwr_clk.c
View file

@ -5,13 +5,13 @@
*
* Samsung SoC SGX power clock control driver
*
* This software is proprietary of Samsung Electronics.
* This software is proprietary of Samsung Electronics.
* No part of this software, either material or conceptual may be copied or distributed, transmitted,
* transcribed, stored in a retrieval system or translated into any human or computer language in any form by any means,
* electronic, mechanical, manual or otherwise, or disclosed
* to third parties without the express written permission of Samsung Electronics.
*
* Alternatively, this program is free software in case of Linux Kernel;
* Alternatively, this program is free software in case of Linux Kernel;
* you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
@ -43,7 +43,7 @@ struct pm_qos_request exynos5_g3d_int_qos;
static int sec_gpu_top_clock;
static int gpu_voltage_marin;
int sec_wakeup_lock_state = 1;
bool sec_gpu_power_on = false;
bool sec_gpu_power_on;
module_param(sec_wakeup_lock_state, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH);
MODULE_PARM_DESC(sec_wakeup_lock_state, "SGX wakeup lock setting");
@ -99,13 +99,12 @@ void sec_gpu_vol_clk_change(int sgx_clock, int sgx_voltage)
sgx_voltage += gpu_voltage_marin;
#if defined(CONFIG_ARM_EXYNOS5410_BUS_DEVFREQ)
if (sec_gpu_power_on) {
if (sgx_clock >= sec_gpu_top_clock) {
#ifdef CONFIG_ARM_EXYNOS_IKS_CPUFREQ
if (sgx_clock >= sec_gpu_top_clock) {
#ifdef CONFIG_ARM_EXYNOS_IKS_CPUFREQ
pm_qos_update_request(&exynos5_g3d_cpu_qos, 600000);
#else
#else
pm_qos_update_request(&exynos5_g3d_cpu_qos, 800000);
#endif
#endif
}
if (sgx_clock < MIF_THRESHHOLD_VALUE_CLK)
@ -117,23 +116,22 @@ void sec_gpu_vol_clk_change(int sgx_clock, int sgx_voltage)
pm_qos_update_request(&exynos5_g3d_int_qos, 0);
pm_qos_update_request(&exynos5_g3d_mif_qos, 0);
}
#endif
if (sec_gpu_power_on) {
if (cur_sgx_clock > sgx_clock) {
gpu_clock_set(sgx_clock);
gpu_voltage_set(sgx_voltage);
} else if (cur_sgx_clock < sgx_clock) {
gpu_voltage_set(sgx_voltage);
gpu_clock_set(sgx_clock);
}
sec_gpu_setting_clock = gpu_clock_get();
sec_gpu_setting_voltage = gpu_voltage_get();
if (cur_sgx_clock > sgx_clock) {
gpu_clock_set(sgx_clock);
gpu_voltage_set(sgx_voltage);
} else if (cur_sgx_clock < sgx_clock) {
gpu_voltage_set(sgx_voltage);
gpu_clock_set(sgx_clock);
}
sec_gpu_setting_clock = gpu_clock_get();
sec_gpu_setting_voltage = gpu_voltage_get();
}
else {
sec_gpu_setting_clock = sgx_clock;
sec_gpu_setting_voltage = sgx_voltage;
PVR_LOG(("SGX keep DVFS info sgx_clock:%d MHz, sgx_voltage:%d mV ", sgx_clock, sgx_voltage));
// PVR_LOG(("SGX keep DVFS info sgx_clock:%d MHz, sgx_voltage:%d mV ", sgx_clock, sgx_voltage));
}
mutex_unlock(&lock);
@ -148,18 +146,18 @@ static int sec_gpu_clock_disable(void)
static int sec_gpu_clock_enable(void)
{
int err = 0;
/*adonis must be set parent function after runtime pm resume*/
/* adonis must be set parent function after runtime pm resume */
err = gpu_clock_set_parent();
if (err) {
return err;
}
/* if setting wakeup lock clock, resume clock using that*/
/* if different with current clock and default cleck, need to set clock*/
if (gpu_clock_get() != sec_gpu_setting_clock)
gpu_clock_set(sec_gpu_setting_clock);
if (gpu_clock_get() != sec_gpu_setting_clock)
gpu_clock_set(sec_gpu_setting_clock);
if (gpu_voltage_get() != sec_gpu_setting_voltage)
gpu_voltage_set(sec_gpu_setting_voltage);
if (gpu_voltage_get() != sec_gpu_setting_voltage)
gpu_voltage_set(sec_gpu_setting_voltage);
if (sec_wakeup_lock_state) {
if (gpu_voltage_get() < WAKEUP_LOCK_VOLTAGE + gpu_voltage_marin)
@ -247,7 +245,7 @@ int sec_gpu_pwr_clk_margin_set(unsigned int margin_offset)
/* set or reset voltage margin - margin_offset */
if (margin_offset != gpu_voltage_marin) {
if (sec_gpu_power_on)
gpu_voltage_set(sec_gpu_setting_voltage - gpu_voltage_marin + margin_offset);
gpu_voltage_set(sec_gpu_setting_voltage - gpu_voltage_marin + margin_offset);
sec_gpu_setting_voltage = sec_gpu_setting_voltage - gpu_voltage_marin + margin_offset;
gpu_voltage_marin = margin_offset;
}
@ -256,7 +254,7 @@ int sec_gpu_pwr_clk_margin_set(unsigned int margin_offset)
/* this case restore voltage */
if (gpu_voltage_marin) {
if (sec_gpu_power_on)
gpu_voltage_set(sec_gpu_setting_voltage - gpu_voltage_marin);
gpu_voltage_set(sec_gpu_setting_voltage - gpu_voltage_marin);
sec_gpu_setting_voltage = sec_gpu_setting_voltage - gpu_voltage_marin;
gpu_voltage_marin = 0;
}

72
drivers/gpu/pvr/services4/system/exynos5410/sec_dvfs.c
View file

@ -5,13 +5,13 @@
*
* Samsung SoC SGX DVFS driver
*
* This software is proprietary of Samsung Electronics.
* This software is proprietary of Samsung Electronics.
* No part of this software, either material or conceptual may be copied or distributed, transmitted,
* transcribed, stored in a retrieval system or translated into any human or computer language in any form by any means,
* electronic, mechanical, manual or otherwise, or disclosed
* to third parties without the express written permission of Samsung Electronics.
*
* Alternatively, this program is free software in case of Linux Kernel;
* Alternatively, this program is free software in case of Linux Kernel;
* you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
@ -38,8 +38,8 @@
#define BASE_QUICK_DOWN_LEVEL 2
#define BASE_WAKE_UP_LEVEL 3
#define DOWN_REQUIREMENT_THRESHOLD 3
#ifdef USING_532MHZ
#define GPU_DVFS_MAX_LEVEL 5
#ifdef USING_640MHZ
#define GPU_DVFS_MAX_LEVEL 6
#else
#define GPU_DVFS_MAX_LEVEL 4
#endif
@ -55,12 +55,13 @@
/* start define DVFS info */
static GPU_DVFS_DATA default_dvfs_data[] = {
/* level, clock, voltage, src clk, min, max, min2, max2, stay, mask, etc */
#ifdef USING_532MHZ
{ 0, 532, 1150000, 532, 180, 256, 170, 256, 1, 0, 0 },
{ 1, 480, 1100000, 480, 170, 200, 160, 250, 2, 0, 0 },
{ 2, 350, 925000, 350, 160, 190, 150, 250, 3, 0, 0 },
{ 3, 266, 900000, 266, 150, 200, 140, 250, 3, 0, 0 },
{ 4, 177, 900000, 177, 0, 200, 0, 220, 3, 0, 0 },
#ifdef USING_640MHZ
{ 0, 640, 1200000, 640, 180, 256, 170, 256, 0, 0, 0 },
{ 1, 532, 1150000, 532, 170, 100, 160, 250, 0, 0, 0 },
{ 2, 480, 1100000, 480, 160, 190, 150, 250, 0, 0, 0 },
{ 3, 350, 925000, 350, 150, 200, 140, 250, 0, 0, 0 },
{ 4, 266, 900000, 266, 140, 200, 130, 220, 0, 0, 0 },
{ 5, 177, 900000, 177, 0, 200, 0, 220, 0, 0, 0 },
#else
{ 0, 480, 1100000, 480, 170, 256, 160, 256, 0, 0, 0 },
{ 1, 350, 925000, 350, 160, 190, 150, 210, 0, 0, 0 },
@ -85,8 +86,8 @@ int custom_threshold_change;
int custom_threshold[MAX_DVFS_LEVEL*4];
int sgx_dvfs_custom_threshold_size;
int custom_threshold_change;
char sgx_dvfs_table_string[256]={0};
char* sgx_dvfs_table;
char sgx_dvfs_table_string[256] = {0};
char *sgx_dvfs_table;
/* set sys parameters */
module_param(sgx_dvfs_level, int, S_IRUSR | S_IRGRP | S_IROTH);
MODULE_PARM_DESC(sgx_dvfs_level, "SGX DVFS status");
@ -100,10 +101,10 @@ module_param(sgx_dvfs_table, charp , S_IRUSR | S_IRGRP | S_IROTH);
MODULE_PARM_DESC(sgx_dvfs_table, "SGX DVFS frequency array (Mhz)");
#ifdef CONFIG_ASV_MARGIN_TEST
static int set_g3d_freq = 0;
static int set_g3d_freq;
static int __init get_g3d_freq(char *str)
{
get_option(&str, &set_g3d_freq);
get_option(&str, &set_g3d_freq);
return 0;
}
early_param("g3dfreq", get_g3d_freq);
@ -138,7 +139,7 @@ static int sec_gpu_lock_control_proc(int bmax, long value, size_t count)
custom_min_lock_level = lock_level;
}
if ((sgx_dvfs_max_lock) && (sgx_dvfs_min_lock) && (sgx_dvfs_max_lock < sgx_dvfs_min_lock)){ /* abnormal status */
if ((sgx_dvfs_max_lock) && (sgx_dvfs_min_lock) && (sgx_dvfs_max_lock < sgx_dvfs_min_lock)) { /* abnormal status */
if (sgx_dvfs_max_lock) /* max lock */
sec_gpu_vol_clk_change(g_gpu_dvfs_data[custom_max_lock_level].clock, g_gpu_dvfs_data[custom_max_lock_level].voltage);
} else { /* normal status */
@ -188,6 +189,15 @@ static ssize_t set_max_clock(struct device *d, struct device_attribute *a, const
}
static DEVICE_ATTR(sgx_dvfs_max_lock, S_IRUGO | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH, get_max_clock, set_max_clock);
static ssize_t get_cur_clock(struct device *d, struct device_attribute *a, char *buf)
{
PVR_DPF((PVR_DBG_MESSAGE,"get_cur_clock: %d MHz", g_gpu_dvfs_data[sgx_dvfs_level].clock));
return sprintf(buf, "%d\n", g_gpu_dvfs_data[sgx_dvfs_level].clock);
}
static DEVICE_ATTR(sgx_dvfs_cur_clk, S_IRUGO | S_IRGRP | S_IROTH, get_cur_clock, NULL);
void sec_gpu_dvfs_init(void)
{
struct platform_device *pdev;
@ -219,11 +229,13 @@ void sec_gpu_dvfs_init(void)
PVR_LOG(("device_create_file: dev_attr_sgx_dvfs_min_lock fail"));
if (device_create_file(&pdev->dev, &dev_attr_sgx_dvfs_max_lock) < 0)
PVR_LOG(("device_create_file: dev_attr_sgx_dvfs_max_lock fail"));
if (device_create_file(&pdev->dev, &dev_attr_sgx_dvfs_cur_clk) < 0)
PVR_LOG(("device_create_file: dev_attr_sgx_dvfs_max_lock fail"));
/* Generate DVFS table list*/
for( i = 0; i < sizeof(default_dvfs_data) / sizeof(GPU_DVFS_DATA) ; i++) {
offset = snprintf(sgx_dvfs_table_string+total, sizeof(sgx_dvfs_table_string), "%d ", default_dvfs_data[i].clock);
total += offset;
for (i = 0; i < sizeof(default_dvfs_data) / sizeof(GPU_DVFS_DATA); i++) {
offset = snprintf(sgx_dvfs_table_string+total, sizeof(sgx_dvfs_table_string), "%d ", default_dvfs_data[i].clock);
total += offset;
}
sgx_dvfs_table = sgx_dvfs_table_string;
if (device_create_file(&pdev->dev, &dev_attr_sgx_dvfs_table) < 0)
@ -258,8 +270,8 @@ void sec_gpu_dvfs_down_requirement_reset()
extern unsigned int *g_debug_CCB_Info_RO;
extern unsigned int *g_debug_CCB_Info_WO;
extern int g_debug_CCB_Info_WCNT;
static int g_debug_CCB_Info_Flag = 0;
static int g_debug_CCB_count = 1;
static int g_debug_CCB_Info_Flag;
//static int g_debug_CCB_count = 1;
int sec_clock_change_up(int level, int step)
{
level -= step;
@ -274,11 +286,12 @@ int sec_clock_change_up(int level, int step)
sgx_dvfs_down_requirement = g_gpu_dvfs_data[level].stay_total_count;
sec_gpu_vol_clk_change(g_gpu_dvfs_data[level].clock, g_gpu_dvfs_data[level].voltage);
if ((g_debug_CCB_Info_Flag % g_debug_CCB_count) == 0)
PVR_LOG(("SGX CCB RO : %d, WO : %d, Total : %d", *g_debug_CCB_Info_RO, *g_debug_CCB_Info_WO, g_debug_CCB_Info_WCNT));
// if ((g_debug_CCB_Info_Flag % g_debug_CCB_count) == 0)
// PVR_LOG(("SGX CCB RO : %d, WO : %d, Total : %d", *g_debug_CCB_Info_RO, *g_debug_CCB_Info_WO, g_debug_CCB_Info_WCNT));
g_debug_CCB_Info_WCNT = 0;
g_debug_CCB_Info_Flag ++;
g_debug_CCB_Info_Flag++;
return level;
}
@ -286,7 +299,7 @@ int sec_clock_change_up(int level, int step)
int sec_clock_change_down(int level, int step)
{
sgx_dvfs_down_requirement--;
if (sgx_dvfs_down_requirement > 0 )
if (sgx_dvfs_down_requirement > 0)
return level;
level += step;
@ -302,11 +315,11 @@ int sec_clock_change_down(int level, int step)
sgx_dvfs_down_requirement = g_gpu_dvfs_data[level].stay_total_count;
sec_gpu_vol_clk_change(g_gpu_dvfs_data[level].clock, g_gpu_dvfs_data[level].voltage);
if ((g_debug_CCB_Info_Flag % g_debug_CCB_count) == 0)
PVR_LOG(("SGX CCB RO : %d, WO : %d, Total : %d", *g_debug_CCB_Info_RO, *g_debug_CCB_Info_WO, g_debug_CCB_Info_WCNT));
// if ((g_debug_CCB_Info_Flag % g_debug_CCB_count) == 0)
// PVR_LOG(("SGX CCB RO : %d, WO : %d, Total : %d", *g_debug_CCB_Info_RO, *g_debug_CCB_Info_WO, g_debug_CCB_Info_WCNT));
g_debug_CCB_Info_WCNT = 0;
g_debug_CCB_Info_Flag ++;
g_debug_CCB_Info_Flag++;
return level;
}
@ -415,7 +428,8 @@ void sec_gpu_dvfs_handler(int utilization_value)
#endif
/* need to up current clock */
sgx_dvfs_level = sec_clock_change_up(sgx_dvfs_level, BASE_UP_STEP_LEVEL);
} else sgx_dvfs_down_requirement = g_gpu_dvfs_data[sgx_dvfs_level].stay_total_count;
}
} else
sgx_dvfs_down_requirement = g_gpu_dvfs_data[sgx_dvfs_level].stay_total_count;
}
g_g3dfreq = g_gpu_dvfs_data[sgx_dvfs_level].clock;
}

6
drivers/gpu/pvr/services4/system/exynos5410/sec_power.c
View file

@ -5,13 +5,13 @@
*
* Samsung SoC SGX power driver
*
* This software is proprietary of Samsung Electronics.
* This software is proprietary of Samsung Electronics.
* No part of this software, either material or conceptual may be copied or distributed, transmitted,
* transcribed, stored in a retrieval system or translated into any human or computer language in any form by any means,
* electronic, mechanical, manual or otherwise, or disclosed
* to third parties without the express written permission of Samsung Electronics.
*
* Alternatively, this program is free software in case of Linux Kernel;
* Alternatively, this program is free software in case of Linux Kernel;
* you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
@ -50,7 +50,7 @@ MODULE_PARM_DESC(sgx_gpu_power_state, "SGX power current status");
void gpu_voltage_set(int sgx_vol)
{
PVR_LOG(("SGX change voltage [%d] -> [%d] mV", sgx_gpu_vol, sgx_vol));
// PVR_LOG(("SGX change voltage [%d] -> [%d] mV", sgx_gpu_vol, sgx_vol));
regulator_set_voltage(g3d_pd_regulator, sgx_vol, sgx_vol);
sgx_gpu_vol = regulator_get_voltage(g3d_pd_regulator);
}

18
drivers/gpu/pvr/services4/system/exynos5410/secutils.c
View file

@ -5,13 +5,13 @@
*
* Samsung SoC SGX DVFS driver
*
* This software is proprietary of Samsung Electronics.
* This software is proprietary of Samsung Electronics.
* No part of this software, either material or conceptual may be copied or distributed, transmitted,
* transcribed, stored in a retrieval system or translated into any human or computer language in any form by any means,
* electronic, mechanical, manual or otherwise, or disclosed
* to third parties without the express written permission of Samsung Electronics.
*
* Alternatively, this program is free software in case of Linux Kernel;
* Alternatively, this program is free software in case of Linux Kernel;
* you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
@ -63,18 +63,15 @@ extern void sec_gpu_dvfs_handler(int utilization_value);
IMG_VOID SysSGXIdleTransition(IMG_BOOL bSGXIdle)
{
#if defined(CONFIG_ARM_EXYNOS5410_BUS_DEVFREQ)
if(bEnableMIFMornitering)
{
if (bEnableMIFMornitering) {
#endif
if (bSGXIdle)
sgx_hw_end(); /* wakeup state */
else
sgx_hw_start(); /* idle state */
#if defined(CONFIG_ARM_EXYNOS5410_BUS_DEVFREQ)
}
else
{
if (bSGXIdle){
} else {
if (bSGXIdle) {
sgx_hw_end(); /* wakeup state */
{
pm_qos_update_request(&exynos5_g3d_int_qos, 0);
@ -85,8 +82,7 @@ IMG_VOID SysSGXIdleTransition(IMG_BOOL bSGXIdle)
status = EXYNOS_CLKREG(0x2051c);
__raw_writel(0x3F, status);
}
}
else {
} else {
{
void __iomem *status;
status = EXYNOS_CLKREG(0x2051c);
@ -94,7 +90,7 @@ IMG_VOID SysSGXIdleTransition(IMG_BOOL bSGXIdle)
}
{
pm_qos_update_request(&exynos5_g3d_int_qos, 200000);
if(sgx_dvfs_level > 2)
if (sgx_dvfs_level > 2)
pm_qos_update_request(&exynos5_g3d_mif_qos, 267000);
else
pm_qos_update_request(&exynos5_g3d_mif_qos, 800000);

2
drivers/gpu/pvr/services4/system/exynos5410/sysconfig.h Normal file → Executable file
View file

@ -33,8 +33,6 @@ extern struct platform_device *gpsPVRLDMDev;
#define SYS_SGX_USSE_COUNT (1)
#define SYS_SGX_HWRECOVERY_TRACE_RESET_TIME_PERIOD 5000000
#define SYS_SGX_MAX_HWRECOVERY_OCCURANCE_COUNT 2
#if defined(SGX_FEATURE_HOST_PORT)

4
include/linux/videodev2_exynos_camera.h
View file

@ -1121,6 +1121,10 @@ enum set_3dnr_mode {
#define V4L2_CID_EMBEDDEDDATA_ENABLE (V4L2_CID_PRIVATE_BASE+130)
#define V4L2_CID_CAMERA_AUTO_FOCUS_RESULT_SECOND (V4L2_CID_PRIVATE_BASE + 131)
#define V4L2_CID_CAMERA_FINISH_AUTO_FOCUS (V4L2_CID_PRIVATE_BASE + 133)
#define V4L2_CID_CAMERA_RETURN_FOCUS (V4L2_CID_PRIVATE_BASE+134)
#define V4L2_CID_CAMERA_CHECK_SENSOR_STATUS (V4L2_CID_PRIVATE_BASE+150)
#define V4L2_CID_CAMERA_DEFAULT_FOCUS_POSITION (V4L2_CID_PRIVATE_BASE+151)
/* Pixel format FOURCC depth Description */