From 17b04333c58d5908ac1a691650efc1734b32a143 Mon Sep 17 00:00:00 2001 From: Matthew McGowan Date: Tue, 28 Feb 2023 14:26:50 -0800 Subject: [PATCH] fix: Increases the drive strength of 32kHz external crystal, in line with calculations specified in ST AN2867 sections 3.3, 3.4, and STM32L4 datasheet DS12023 Table 58. LSE oscillator characteristics. The drive strength RCC_LSEDRIVE_LOW is marginal for the 32kHz crystal oscillator stability, and RCC_LSEDRIVE_MEDIUMLOW meets the calculated drive strength with a small margin for parasitic capacitance. --- ports/stm32l4/boards/swan_r5/board.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/ports/stm32l4/boards/swan_r5/board.c b/ports/stm32l4/boards/swan_r5/board.c index cb9d785..ce130f6 100644 --- a/ports/stm32l4/boards/swan_r5/board.c +++ b/ports/stm32l4/boards/swan_r5/board.c @@ -28,8 +28,10 @@ void clock_init(void) /* Enable Power Control clock */ - __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - __HAL_RCC_PWR_CLK_ENABLE(); + // Sets the drive strength of 32kHz external crystal, in line with calculations specified in ST AN2867 sections 3.3, 3.4, and STM32L4 datasheet DS12023 Table 58. LSE oscillator characteristics. + // The drive strength RCC_LSEDRIVE_LOW is marginal for the 32kHz crystal oscillator stability, and RCC_LSEDRIVE_MEDIUMLOW meets the calculated drive strength with a small margin for parasitic capacitance. + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMLOW); + __HAL_RCC_PWR_CLK_ENABLE(); if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { Error_Handler();