<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright (c) 2017 Microchip Technology Inc.

SPDX-License-Identifier: Apache-2.0

Licensed under the Apache License, Version 2.0 (the "License"); you may
not use this file except in compliance with the License.
You may obtain a copy of the Licence at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
-->
<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
  <file timestamp="2017-08-03T21:21:39Z"/>
  <variants>
    <variant ordercode="SAMD51P19A-AU" package="TQFP128" pinout="SAMD51P" speedmax="150000000" tempmin="-40" tempmax="85" vccmin="1.71" vccmax="3.60"/>
    <variant ordercode="SAMD51P19A-AF" package="TQFP128" pinout="SAMD51P" speedmax="150000000" tempmin="-40" tempmax="125" vccmin="1.71" vccmax="3.60"/>
  </variants>
  <devices>
    <device name="ATSAMD51P19A" architecture="CORTEX-M4" family="SAMD" series="SAMD51">
      <address-spaces>
        <address-space id="base" name="base" start="0" size="0x100000000" endianness="little">
          <memory-segment name="CMCC" start="0x03000000" size="0x1000000" type="io" rw="RW"/>
          <memory-segment name="CMCC_DATARAM" start="0x3000000" size="0x1000" type="io" rw="RW"/>
          <memory-segment name="CMCC_TAGRAM" start="0x3001000" size="0x400" type="io" rw="RW"/>
          <memory-segment name="CMCC_VALIDRAM" start="0x3002000" size="0x40" type="io" rw="RW"/>
          <memory-segment name="HSRAM" start="0x20000000" size="0x30000" type="ram" rw="RW" exec="true"/>
          <memory-segment name="HSRAM_ETB" start="0x20000000" size="0x8000" type="ram" rw="RW" exec="true"/>
          <memory-segment name="HSRAM_RET1" start="0x20000000" size="0x8000" type="ram" rw="RW" exec="true"/>
          <memory-segment name="HPB0" start="0x40000000" size="0x4400" type="io" rw="RW"/>
          <memory-segment name="HPB1" start="0x41000000" size="0x22000" type="io" rw="RW"/>
          <memory-segment name="HPB2" start="0x42000000" size="0x3C00" type="io" rw="RW"/>
          <memory-segment name="HPB3" start="0x43000000" size="0x3000" type="io" rw="RW"/>
          <memory-segment name="FLASH" start="0x00000000" size="0x80000" type="flash" pagesize="512" rw="RW" exec="true"/>
          
          <memory-segment name="AUX0" start="0x00804000" size="0x200" type="user_page" pagesize="16" rw="RW"/>
          <memory-segment name="SEEPROM" start="0x44000000" size="0x20000" type="io" rw="RW"/>
          <memory-segment name="BKUPRAM" start="0x47000000" size="0x2000" type="ram" rw="RW" exec="true"/>
          <memory-segment name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW"/>
          <memory-segment name="QSPI" start="0x04000000" size="0x1000000" type="other" rw="RW" exec="true" external="true"/>
          <memory-segment name="SDHC0" start="0x45000000" size="0xC00" type="io" rw="RW"/>
          <memory-segment name="SDHC1" start="0x46000000" size="0xC00" type="io" rw="RW"/>
          <memory-segment name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW"/>
          
        </address-space>
        <address-space id="fuses" name="fuses" start="0x00000000" size="0x10000" endianness="little"/>
      </address-spaces>
      <parameters>
        <param name="GCLK_ID_TRACE" value="47"/>
        <param name="LITTLE_ENDIAN" value="1"/>
        <param name="NUM_IRQ" value="137"/>
        <param name="__CM4_REV" value="0x0001"/>
        <param name="__DEBUG_LVL" value="3"/>
        <param name="__FPU_PRESENT" value="1"/>
        <param name="__MPU_PRESENT" value="1"/>
        <param name="__NVIC_PRIO_BITS" value="3"/>
        <param name="__TRACE_LVL" value="2"/>
        <param name="__VTOR_PRESENT" value="1"/>
        <param name="__Vendor_SysTickConfig" value="0"/>
      </parameters>
      <peripherals>
        <module name="AC" id="U2501" version="1.0.0">
          <instance name="AC">
            <register-group name="AC" name-in-module="AC" address-space="base" offset="0x42002000"/>
            <signals>
              <signal group="AIN" index="0" function="B_AC" pad="PA04"/>
              <signal group="AIN" index="1" function="B_AC" pad="PA05"/>
              <signal group="AIN" index="2" function="B_AC" pad="PA06"/>
              <signal group="AIN" index="3" function="B_AC" pad="PA07"/>
              <signal group="CMP" index="0" function="M" pad="PA12"/>
              <signal group="CMP" index="0" function="M" pad="PA18"/>
              <signal group="CMP" index="0" function="M" pad="PB24"/>
              <signal group="CMP" index="1" function="M" pad="PA13"/>
              <signal group="CMP" index="1" function="M" pad="PA19"/>
              <signal group="CMP" index="1" function="M" pad="PB25"/>
            </signals>
            <parameters>
              <param name="COMPCTRL_MUXNEG_OPAMP" value="7"/>
              <param name="GCLK_ID" value="32"/>
              <param name="IMPLEMENTS_VDBLR" value="0"/>
              <param name="NUM_CMP" value="2"/>
              <param name="PAIRS" value="1"/>
              <param name="SPEED_LEVELS" value="2"/>
              <param name="INSTANCE_ID" value="72"/>
            </parameters>
          </instance>
        </module>
        <module name="ADC" id="U2500" version="1.0.0">
          <instance name="ADC0">
            <register-group name="ADC0" name-in-module="ADC" address-space="base" offset="0x43001C00"/>
            <signals>
              <signal group="AIN" index="0" function="B_ADC0" pad="PA02"/>
              <signal group="AIN" index="1" function="B_ADC0" pad="PA03"/>
              <signal group="AIN" index="2" function="B_ADC0" pad="PB08"/>
              <signal group="AIN" index="3" function="B_ADC0" pad="PB09"/>
              <signal group="AIN" index="4" function="B_ADC0" pad="PA04"/>
              <signal group="AIN" index="5" function="B_ADC0" pad="PA05"/>
              <signal group="AIN" index="6" function="B_ADC0" pad="PA06"/>
              <signal group="AIN" index="7" function="B_ADC0" pad="PA07"/>
              <signal group="AIN" index="8" function="B_ADC0" pad="PA08"/>
              <signal group="AIN" index="9" function="B_ADC0" pad="PA09"/>
              <signal group="AIN" index="10" function="B_ADC0" pad="PA10"/>
              <signal group="AIN" index="11" function="B_ADC0" pad="PA11"/>
              <signal group="AIN" index="12" function="B_ADC0" pad="PB00"/>
              <signal group="AIN" index="13" function="B_ADC0" pad="PB01"/>
              <signal group="AIN" index="14" function="B_ADC0" pad="PB02"/>
              <signal group="AIN" index="15" function="B_ADC0" pad="PB03"/>
              <signal group="DRV" index="0" function="O_PTC_DRV" pad="PA03"/>
              <signal group="DRV" index="1" function="O_PTC_DRV" pad="PB08"/>
              <signal group="DRV" index="2" function="O_PTC_DRV" pad="PB09"/>
              <signal group="DRV" index="3" function="O_PTC_DRV" pad="PA04"/>
              <signal group="DRV" index="4" function="O_PTC_DRV" pad="PA06"/>
              <signal group="DRV" index="5" function="O_PTC_DRV" pad="PA07"/>
              <signal group="DRV" index="6" function="O_PTC_DRV" pad="PA08"/>
              <signal group="DRV" index="7" function="O_PTC_DRV" pad="PA09"/>
              <signal group="DRV" index="8" function="O_PTC_DRV" pad="PA10"/>
              <signal group="DRV" index="9" function="O_PTC_DRV" pad="PA11"/>
              <signal group="DRV" index="10" function="O_PTC_DRV" pad="PA16"/>
              <signal group="DRV" index="11" function="O_PTC_DRV" pad="PA17"/>
              <signal group="DRV" index="12" function="O_PTC_DRV" pad="PA18"/>
              <signal group="DRV" index="13" function="O_PTC_DRV" pad="PA19"/>
              <signal group="DRV" index="14" function="O_PTC_DRV" pad="PA20"/>
              <signal group="DRV" index="15" function="O_PTC_DRV" pad="PA21"/>
              <signal group="DRV" index="16" function="O_PTC_DRV" pad="PA22"/>
              <signal group="DRV" index="17" function="O_PTC_DRV" pad="PA23"/>
              <signal group="DRV" index="18" function="O_PTC_DRV" pad="PA27"/>
              <signal group="DRV" index="19" function="O_PTC_DRV" pad="PA30"/>
              <signal group="DRV" index="20" function="O_PTC_DRV" pad="PB02"/>
              <signal group="DRV" index="21" function="O_PTC_DRV" pad="PB03"/>
              <signal group="DRV" index="22" function="O_PTC_DRV" pad="PB04"/>
              <signal group="DRV" index="23" function="O_PTC_DRV" pad="PB05"/>
              <signal group="DRV" index="24" function="O_PTC_DRV" pad="PB06"/>
              <signal group="DRV" index="25" function="O_PTC_DRV" pad="PB07"/>
              <signal group="DRV" index="26" function="O_PTC_DRV" pad="PB12"/>
              <signal group="DRV" index="27" function="O_PTC_DRV" pad="PB13"/>
              <signal group="DRV" index="28" function="O_PTC_DRV" pad="PB14"/>
              <signal group="DRV" index="29" function="O_PTC_DRV" pad="PB15"/>
              <signal group="DRV" index="30" function="O_PTC_DRV" pad="PB00"/>
              <signal group="DRV" index="31" function="O_PTC_DRV" pad="PB01"/>
              <signal group="X" index="0" function="B_PTC" pad="PA03"/>
              <signal group="Y" index="0" function="B_PTC" pad="PA03"/>
              <signal group="X" index="1" function="B_PTC" pad="PB08"/>
              <signal group="Y" index="1" function="B_PTC" pad="PB08"/>
              <signal group="X" index="2" function="B_PTC" pad="PB09"/>
              <signal group="Y" index="2" function="B_PTC" pad="PB09"/>
              <signal group="X" index="3" function="B_PTC" pad="PA04"/>
              <signal group="Y" index="3" function="B_PTC" pad="PA04"/>
              <signal group="X" index="4" function="B_PTC" pad="PA06"/>
              <signal group="Y" index="4" function="B_PTC" pad="PA06"/>
              <signal group="X" index="5" function="B_PTC" pad="PA07"/>
              <signal group="Y" index="5" function="B_PTC" pad="PA07"/>
              <signal group="X" index="6" function="B_PTC" pad="PA08"/>
              <signal group="Y" index="6" function="B_PTC" pad="PA08"/>
              <signal group="X" index="7" function="B_PTC" pad="PA09"/>
              <signal group="Y" index="7" function="B_PTC" pad="PA09"/>
              <signal group="X" index="8" function="B_PTC" pad="PA10"/>
              <signal group="Y" index="8" function="B_PTC" pad="PA10"/>
              <signal group="X" index="9" function="B_PTC" pad="PA11"/>
              <signal group="Y" index="9" function="B_PTC" pad="PA11"/>
              <signal group="X" index="10" function="B_PTC" pad="PA16"/>
              <signal group="Y" index="10" function="B_PTC" pad="PA16"/>
              <signal group="X" index="11" function="B_PTC" pad="PA17"/>
              <signal group="Y" index="11" function="B_PTC" pad="PA17"/>
              <signal group="X" index="13" function="B_PTC" pad="PA19"/>
              <signal group="Y" index="13" function="B_PTC" pad="PA19"/>
              <signal group="X" index="14" function="B_PTC" pad="PA20"/>
              <signal group="Y" index="14" function="B_PTC" pad="PA20"/>
              <signal group="X" index="15" function="B_PTC" pad="PA21"/>
              <signal group="Y" index="15" function="B_PTC" pad="PA21"/>
              <signal group="X" index="16" function="B_PTC" pad="PA22"/>
              <signal group="Y" index="16" function="B_PTC" pad="PA22"/>
              <signal group="X" index="17" function="B_PTC" pad="PA23"/>
              <signal group="Y" index="17" function="B_PTC" pad="PA23"/>
              <signal group="X" index="18" function="B_PTC" pad="PA27"/>
              <signal group="Y" index="18" function="B_PTC" pad="PA27"/>
              <signal group="X" index="19" function="B_PTC" pad="PA30"/>
              <signal group="Y" index="19" function="B_PTC" pad="PA30"/>
              <signal group="X" index="20" function="B_PTC" pad="PB02"/>
              <signal group="Y" index="20" function="B_PTC" pad="PB02"/>
              <signal group="X" index="21" function="B_PTC" pad="PB03"/>
              <signal group="Y" index="21" function="B_PTC" pad="PB03"/>
              <signal group="X" index="22" function="B_PTC" pad="PB04"/>
              <signal group="Y" index="22" function="B_PTC" pad="PB04"/>
              <signal group="X" index="23" function="B_PTC" pad="PB05"/>
              <signal group="Y" index="23" function="B_PTC" pad="PB05"/>
              <signal group="X" index="24" function="B_PTC" pad="PB06"/>
              <signal group="Y" index="24" function="B_PTC" pad="PB06"/>
              <signal group="X" index="25" function="B_PTC" pad="PB07"/>
              <signal group="Y" index="25" function="B_PTC" pad="PB07"/>
              <signal group="X" index="26" function="B_PTC" pad="PB12"/>
              <signal group="Y" index="26" function="B_PTC" pad="PB12"/>
              <signal group="X" index="27" function="B_PTC" pad="PB13"/>
              <signal group="Y" index="27" function="B_PTC" pad="PB13"/>
              <signal group="X" index="28" function="B_PTC" pad="PB14"/>
              <signal group="Y" index="28" function="B_PTC" pad="PB14"/>
              <signal group="X" index="29" function="B_PTC" pad="PB15"/>
              <signal group="Y" index="29" function="B_PTC" pad="PB15"/>
              <signal group="X" index="30" function="B_PTC" pad="PB00"/>
              <signal group="Y" index="30" function="B_PTC" pad="PB00"/>
              <signal group="X" index="31" function="B_PTC" pad="PB01"/>
              <signal group="Y" index="31" function="B_PTC" pad="PB01"/>
            </signals>
            <parameters>
              <param name="BANDGAP" value="27"/>
              <param name="CTAT" value="29"/>
              <param name="DMAC_ID_RESRDY" value="68"/>
              <param name="DMAC_ID_SEQ" value="69"/>
              <param name="EXTCHANNEL_MSB" value="15"/>
              <param name="GCLK_ID" value="40"/>
              <param name="MASTER_SLAVE_MODE" value="1"/>
              <param name="OPAMP2" value="0"/>
              <param name="OPAMP01" value="0"/>
              <param name="PTAT" value="28"/>
              <param name="TOUCH_IMPLEMENTED" value="1"/>
              <param name="TOUCH_LINES_NUM" value="32"/>
              <param name="INSTANCE_ID" value="103"/>
            </parameters>
          </instance>
          <instance name="ADC1">
            <register-group name="ADC1" name-in-module="ADC" address-space="base" offset="0x43002000"/>
            <signals>
              <signal group="AIN" index="0" function="B_ADC1" pad="PB08"/>
              <signal group="AIN" index="1" function="B_ADC1" pad="PB09"/>
              <signal group="AIN" index="2" function="B_ADC1" pad="PA08"/>
              <signal group="AIN" index="3" function="B_ADC1" pad="PA09"/>
              <signal group="AIN" index="4" function="B_ADC1" pad="PC02"/>
              <signal group="AIN" index="5" function="B_ADC1" pad="PC03"/>
              <signal group="AIN" index="6" function="B_ADC1" pad="PB04"/>
              <signal group="AIN" index="7" function="B_ADC1" pad="PB05"/>
              <signal group="AIN" index="8" function="B_ADC1" pad="PB06"/>
              <signal group="AIN" index="9" function="B_ADC1" pad="PB07"/>
              <signal group="AIN" index="10" function="B_ADC1" pad="PC00"/>
              <signal group="AIN" index="11" function="B_ADC1" pad="PC01"/>
              <signal group="AIN" index="12" function="B_ADC1" pad="PC30"/>
              <signal group="AIN" index="13" function="B_ADC1" pad="PC31"/>
              <signal group="AIN" index="14" function="B_ADC1" pad="PD00"/>
              <signal group="AIN" index="15" function="B_ADC1" pad="PD01"/>
            </signals>
            <parameters>
              <param name="BANDGAP" value="27"/>
              <param name="CTAT" value="29"/>
              <param name="DMAC_ID_RESRDY" value="70"/>
              <param name="DMAC_ID_SEQ" value="71"/>
              <param name="EXTCHANNEL_MSB" value="15"/>
              <param name="GCLK_ID" value="41"/>
              <param name="MASTER_SLAVE_MODE" value="2"/>
              <param name="OPAMP2" value="0"/>
              <param name="OPAMP01" value="0"/>
              <param name="PTAT" value="28"/>
              <param name="TOUCH_IMPLEMENTED" value="0"/>
              <param name="TOUCH_LINES_NUM" value="1"/>
              <param name="INSTANCE_ID" value="104"/>
            </parameters>
          </instance>
        </module>
        <module name="AES" id="U2238" version="2.2.0">
          <instance name="AES">
            <register-group name="AES" name-in-module="AES" address-space="base" offset="0x42002400"/>
            <parameters>
              <param name="DMAC_ID_RD" value="82"/>
              <param name="DMAC_ID_WR" value="81"/>
              <param name="FOUR_BYTE_OPERATION" value="1"/>
              <param name="GCM" value="1"/>
              <param name="KEYLEN" value="2"/>
              <param name="INSTANCE_ID" value="73"/>
            </parameters>
          </instance>
        </module>
        <module name="CCL" id="U2225" version="1.1.0">
          <instance name="CCL">
            <register-group name="CCL" name-in-module="CCL" address-space="base" offset="0x42003800"/>
            <signals>
              <signal group="IN" index="0" function="N" pad="PA04"/>
              <signal group="IN" index="0" function="N" pad="PA16"/>
              <signal group="IN" index="0" function="N" pad="PB22"/>
              <signal group="IN" index="1" function="N" pad="PA05"/>
              <signal group="IN" index="1" function="N" pad="PA17"/>
              <signal group="IN" index="1" function="N" pad="PB00"/>
              <signal group="IN" index="2" function="N" pad="PA06"/>
              <signal group="IN" index="2" function="N" pad="PA18"/>
              <signal group="IN" index="2" function="N" pad="PB01"/>
              <signal group="IN" index="3" function="N" pad="PA08"/>
              <signal group="IN" index="3" function="N" pad="PA30"/>
              <signal group="IN" index="4" function="N" pad="PA09"/>
              <signal group="IN" index="4" function="N" pad="PC27"/>
              <signal group="IN" index="5" function="N" pad="PA10"/>
              <signal group="IN" index="5" function="N" pad="PC28"/>
              <signal group="IN" index="6" function="N" pad="PA22"/>
              <signal group="IN" index="6" function="N" pad="PB06"/>
              <signal group="IN" index="7" function="N" pad="PA23"/>
              <signal group="IN" index="7" function="N" pad="PB07"/>
              <signal group="IN" index="8" function="N" pad="PA24"/>
              <signal group="IN" index="8" function="N" pad="PB08"/>
              <signal group="IN" index="9" function="N" pad="PB14"/>
              <signal group="IN" index="9" function="N" pad="PC20"/>
              <signal group="IN" index="10" function="N" pad="PB15"/>
              <signal group="IN" index="10" function="N" pad="PC21"/>
              <signal group="IN" index="11" function="N" pad="PB10"/>
              <signal group="IN" index="11" function="N" pad="PB16"/>
              <signal group="OUT" index="0" function="N" pad="PA07"/>
              <signal group="OUT" index="0" function="N" pad="PA19"/>
              <signal group="OUT" index="0" function="N" pad="PB02"/>
              <signal group="OUT" index="0" function="N" pad="PB23"/>
              <signal group="OUT" index="1" function="N" pad="PA11"/>
              <signal group="OUT" index="1" function="N" pad="PA31"/>
              <signal group="OUT" index="1" function="N" pad="PB11"/>
              <signal group="OUT" index="2" function="N" pad="PA25"/>
              <signal group="OUT" index="2" function="N" pad="PB09"/>
              <signal group="OUT" index="3" function="N" pad="PB17"/>
            </signals>
            <parameters>
              <param name="GCLK_ID" value="33"/>
              <param name="LUT_NUM" value="4"/>
              <param name="SEQ_NUM" value="2"/>
              <param name="INSTANCE_ID" value="78"/>
            </parameters>
          </instance>
        </module>
        <module name="CMCC" id="U2015" version="6.0.0">
          <instance name="CMCC">
            <register-group name="CMCC" name-in-module="CMCC" address-space="base" offset="0x41006000"/>
            <parameters>
              <param name="INSTANCE_ID" value="35"/>
            </parameters>
          </instance>
        </module>
        <module name="DAC" id="U2502" version="1.0.0">
          <instance name="DAC">
            <register-group name="DAC" name-in-module="DAC" address-space="base" offset="0x43002400"/>
            <signals>
              <signal group="VOUT" index="0" function="B_DAC" pad="PA02"/>
              <signal group="VOUT" index="1" function="B_DAC" pad="PA05"/>
            </signals>
            <parameters>
              <param name="CHANNEL_SIZE" value="2"/>
              <param name="DATA_SIZE" value="12"/>
              <param name="GCLK_ID" value="42"/>
              <param name="STEP" value="7"/>
              <param name="INSTANCE_ID" value="105"/>
            </parameters>
          </instance>
        </module>
        <module name="DMAC" id="U2503" version="1.0.0">
          <instance name="DMAC">
            <register-group name="DMAC" name-in-module="DMAC" address-space="base" offset="0x4100A000"/>
            <parameters>
              <param name="BURST" value="1"/>
              <param name="CH_BITS" value="5"/>
              <param name="CH_NUM" value="32"/>
              <param name="EVIN_NUM" value="8"/>
              <param name="EVOUT_NUM" value="4"/>
              <param name="FIFO_SIZE" value="16"/>
              <param name="LVL_BITS" value="2"/>
              <param name="LVL_NUM" value="4"/>
              <param name="QOSCTRL_D_RESETVALUE" value="2"/>
              <param name="QOSCTRL_F_RESETVALUE" value="2"/>
              <param name="QOSCTRL_WRB_RESETVALUE" value="2"/>
              <param name="TRIG_BITS" value="7"/>
              <param name="TRIG_NUM" value="85"/>
              <param name="INSTANCE_ID" value="37"/>
            </parameters>
          </instance>
        </module>
        <module name="DSU" id="U2410" version="1.0.0">
          <instance name="DSU">
            <register-group name="DSU" name-in-module="DSU" address-space="base" offset="0x41002000"/>
            <parameters>
              <param name="DMAC_ID_DCC0" value="2"/>
              <param name="DMAC_ID_DCC1" value="3"/>
              <param name="INSTANCE_ID" value="33"/>
            </parameters>
          </instance>
        </module>
        <module name="EIC" id="U2254" version="3.0.0">
          <instance name="EIC">
            <register-group name="EIC" name-in-module="EIC" address-space="base" offset="0x40002800"/>
            <signals>
              <signal group="EXTINT" index="0" function="A" pad="PA00"/>
              <signal group="EXTINT" index="0" function="A" pad="PA16"/>
              <signal group="EXTINT" index="0" function="A" pad="PB00"/>
              <signal group="EXTINT" index="0" function="A" pad="PB16"/>
              <signal group="EXTINT" index="0" function="A" pad="PC00"/>
              <signal group="EXTINT" index="0" function="A" pad="PC16"/>
              <signal group="EXTINT" index="0" function="A" pad="PD00"/>
              <signal group="EXTINT" index="1" function="A" pad="PA01"/>
              <signal group="EXTINT" index="1" function="A" pad="PA17"/>
              <signal group="EXTINT" index="1" function="A" pad="PB01"/>
              <signal group="EXTINT" index="1" function="A" pad="PB17"/>
              <signal group="EXTINT" index="1" function="A" pad="PC01"/>
              <signal group="EXTINT" index="1" function="A" pad="PC17"/>
              <signal group="EXTINT" index="1" function="A" pad="PD01"/>
              <signal group="EXTINT" index="2" function="A" pad="PA02"/>
              <signal group="EXTINT" index="2" function="A" pad="PA18"/>
              <signal group="EXTINT" index="2" function="A" pad="PB02"/>
              <signal group="EXTINT" index="2" function="A" pad="PB18"/>
              <signal group="EXTINT" index="2" function="A" pad="PC02"/>
              <signal group="EXTINT" index="2" function="A" pad="PC18"/>
              <signal group="EXTINT" index="3" function="A" pad="PA03"/>
              <signal group="EXTINT" index="3" function="A" pad="PA19"/>
              <signal group="EXTINT" index="3" function="A" pad="PB03"/>
              <signal group="EXTINT" index="3" function="A" pad="PB19"/>
              <signal group="EXTINT" index="3" function="A" pad="PC03"/>
              <signal group="EXTINT" index="3" function="A" pad="PC19"/>
              <signal group="EXTINT" index="3" function="A" pad="PD08"/>
              <signal group="EXTINT" index="4" function="A" pad="PA04"/>
              <signal group="EXTINT" index="4" function="A" pad="PA20"/>
              <signal group="EXTINT" index="4" function="A" pad="PB04"/>
              <signal group="EXTINT" index="4" function="A" pad="PB20"/>
              <signal group="EXTINT" index="4" function="A" pad="PC04"/>
              <signal group="EXTINT" index="4" function="A" pad="PC20"/>
              <signal group="EXTINT" index="4" function="A" pad="PD09"/>
              <signal group="EXTINT" index="5" function="A" pad="PA05"/>
              <signal group="EXTINT" index="5" function="A" pad="PA21"/>
              <signal group="EXTINT" index="5" function="A" pad="PB05"/>
              <signal group="EXTINT" index="5" function="A" pad="PB21"/>
              <signal group="EXTINT" index="5" function="A" pad="PC05"/>
              <signal group="EXTINT" index="5" function="A" pad="PC21"/>
              <signal group="EXTINT" index="5" function="A" pad="PD10"/>
              <signal group="EXTINT" index="6" function="A" pad="PA06"/>
              <signal group="EXTINT" index="6" function="A" pad="PA22"/>
              <signal group="EXTINT" index="6" function="A" pad="PB06"/>
              <signal group="EXTINT" index="6" function="A" pad="PB22"/>
              <signal group="EXTINT" index="6" function="A" pad="PC06"/>
              <signal group="EXTINT" index="6" function="A" pad="PC22"/>
              <signal group="EXTINT" index="6" function="A" pad="PD11"/>
              <signal group="EXTINT" index="7" function="A" pad="PA07"/>
              <signal group="EXTINT" index="7" function="A" pad="PA23"/>
              <signal group="EXTINT" index="7" function="A" pad="PB07"/>
              <signal group="EXTINT" index="7" function="A" pad="PB23"/>
              <signal group="EXTINT" index="7" function="A" pad="PC23"/>
              <signal group="EXTINT" index="7" function="A" pad="PD12"/>
              <signal group="EXTINT" index="8" function="A" pad="PA24"/>
              <signal group="EXTINT" index="8" function="A" pad="PB08"/>
              <signal group="EXTINT" index="8" function="A" pad="PB24"/>
              <signal group="EXTINT" index="8" function="A" pad="PC24"/>
              <signal group="EXTINT" index="9" function="A" pad="PA09"/>
              <signal group="EXTINT" index="9" function="A" pad="PA25"/>
              <signal group="EXTINT" index="9" function="A" pad="PB09"/>
              <signal group="EXTINT" index="9" function="A" pad="PB25"/>
              <signal group="EXTINT" index="9" function="A" pad="PC07"/>
              <signal group="EXTINT" index="9" function="A" pad="PC25"/>
              <signal group="EXTINT" index="10" function="A" pad="PA10"/>
              <signal group="EXTINT" index="10" function="A" pad="PB10"/>
              <signal group="EXTINT" index="10" function="A" pad="PC10"/>
              <signal group="EXTINT" index="10" function="A" pad="PC26"/>
              <signal group="EXTINT" index="10" function="A" pad="PD20"/>
              <signal group="EXTINT" index="11" function="A" pad="PA11"/>
              <signal group="EXTINT" index="11" function="A" pad="PA27"/>
              <signal group="EXTINT" index="11" function="A" pad="PB11"/>
              <signal group="EXTINT" index="11" function="A" pad="PC11"/>
              <signal group="EXTINT" index="11" function="A" pad="PC27"/>
              <signal group="EXTINT" index="11" function="A" pad="PD21"/>
              <signal group="EXTINT" index="12" function="A" pad="PA12"/>
              <signal group="EXTINT" index="12" function="A" pad="PB12"/>
              <signal group="EXTINT" index="12" function="A" pad="PB26"/>
              <signal group="EXTINT" index="12" function="A" pad="PC12"/>
              <signal group="EXTINT" index="12" function="A" pad="PC28"/>
              <signal group="EXTINT" index="13" function="A" pad="PA13"/>
              <signal group="EXTINT" index="13" function="A" pad="PB13"/>
              <signal group="EXTINT" index="13" function="A" pad="PB27"/>
              <signal group="EXTINT" index="13" function="A" pad="PC13"/>
              <signal group="EXTINT" index="14" function="A" pad="PA30"/>
              <signal group="EXTINT" index="14" function="A" pad="PB14"/>
              <signal group="EXTINT" index="14" function="A" pad="PB28"/>
              <signal group="EXTINT" index="14" function="A" pad="PB30"/>
              <signal group="EXTINT" index="14" function="A" pad="PC14"/>
              <signal group="EXTINT" index="14" function="A" pad="PC30"/>
              <signal group="EXTINT" index="14" function="A" pad="PA14"/>
              <signal group="EXTINT" index="15" function="A" pad="PA15"/>
              <signal group="EXTINT" index="15" function="A" pad="PA31"/>
              <signal group="EXTINT" index="15" function="A" pad="PB15"/>
              <signal group="EXTINT" index="15" function="A" pad="PB29"/>
              <signal group="EXTINT" index="15" function="A" pad="PB31"/>
              <signal group="EXTINT" index="15" function="A" pad="PC15"/>
              <signal group="EXTINT" index="15" function="A" pad="PC31"/>
              <signal group="NMI" function="A" pad="PA08"/>
            </signals>
            <parameters>
              <param name="EXTINT_NUM" value="16"/>
              <param name="GCLK_ID" value="4"/>
              <param name="NUMBER_OF_CONFIG_REGS" value="2"/>
              <param name="NUMBER_OF_DPRESCALER_REGS" value="2"/>
              <param name="NUMBER_OF_INTERRUPTS" value="16"/>
              <param name="INSTANCE_ID" value="10"/>
            </parameters>
          </instance>
        </module>
        <module name="EVSYS" id="U2504" version="1.0.0">
          <instance name="EVSYS">
            <register-group name="EVSYS" name-in-module="EVSYS" address-space="base" offset="0x4100E000"/>
            <parameters>
              <param name="ASYNCHRONOUS_CHANNELS" value="0xFFFFF000"/>
              <param name="CHANNELS" value="32"/>
              <param name="CHANNELS_BITS" value="5"/>
              <param name="EXTEVT_NUM" value="0"/>
              <param name="GENERATORS" value="119"/>
              <param name="GENERATORS_BITS" value="7"/>
              <param name="SYNCH_NUM" value="12"/>
              <param name="SYNCH_NUM_BITS" value="4"/>
              <param name="USERS" value="67"/>
              <param name="USERS_BITS" value="7"/>
              <param name="INSTANCE_ID" value="39"/>
            </parameters>
          </instance>
        </module>
        <module name="FREQM" id="U2257" version="1.1.0">
          <instance name="FREQM">
            <register-group name="FREQM" name-in-module="FREQM" address-space="base" offset="0x40002C00"/>
            <parameters>
              <param name="GCLK_ID_MSR" value="5"/>
              <param name="INSTANCE_ID" value="11"/>
            </parameters>
          </instance>
        </module>
        <module name="GCLK" id="U2122" version="1.2.0">
          <instance name="GCLK">
            <register-group name="GCLK" name-in-module="GCLK" address-space="base" offset="0x40001C00"/>
            <signals>
              <signal group="IO" index="0" function="M" pad="PA30"/>
              <signal group="IO" index="0" function="M" pad="PB14"/>
              <signal group="IO" index="0" function="M" pad="PA14"/>
              <signal group="IO" index="0" function="M" pad="PB22"/>
              <signal group="IO" index="1" function="M" pad="PB15"/>
              <signal group="IO" index="1" function="M" pad="PA15"/>
              <signal group="IO" index="1" function="M" pad="PB23"/>
              <signal group="IO" index="1" function="M" pad="PA27"/>
              <signal group="IO" index="2" function="M" pad="PA16"/>
              <signal group="IO" index="2" function="M" pad="PB16"/>
              <signal group="IO" index="3" function="M" pad="PA17"/>
              <signal group="IO" index="3" function="M" pad="PB17"/>
              <signal group="IO" index="4" function="M" pad="PA10"/>
              <signal group="IO" index="4" function="M" pad="PB10"/>
              <signal group="IO" index="4" function="M" pad="PB18"/>
              <signal group="IO" index="5" function="M" pad="PA11"/>
              <signal group="IO" index="5" function="M" pad="PB11"/>
              <signal group="IO" index="5" function="M" pad="PB19"/>
              <signal group="IO" index="6" function="M" pad="PB12"/>
              <signal group="IO" index="6" function="M" pad="PB20"/>
              <signal group="IO" index="7" function="M" pad="PB13"/>
              <signal group="IO" index="7" function="M" pad="PB21"/>
            </signals>
            <parameters>
              <param name="GENCTRL0_RESETVALUE" value="106"/>
              <param name="GENDIV_BITS" value="16"/>
              <param name="GEN_BITS" value="4"/>
              <param name="GEN_NUM" value="12"/>
              <param name="GEN_NUM_MSB" value="11"/>
              <param name="GEN_SOURCE_NUM_MSB" value="8"/>
              <param name="IO_NUM" value="8"/>
              <param name="NUM" value="48"/>
              <param name="SOURCE_BITS" value="4"/>
              <param name="SOURCE_NUM" value="9"/>
              <param name="INSTANCE_ID" value="7"/>
            </parameters>
          </instance>
        </module>
        <module name="HMATRIXB" id="I7638" version="2.1.4">
          <instance name="HMATRIX">
            <register-group name="HMATRIX" name-in-module="HMATRIXB" address-space="base" offset="0x4100C000"/>
            <parameters>
              <param name="MASTER_NUM" value="8"/>
              <param name="MASTER_CM4_S" value="0"/>
              <param name="MASTER_CMCC" value="1"/>
              <param name="MASTER_PICOP_MEM" value="2"/>
              <param name="MASTER_PICOP_IO" value="3"/>
              <param name="MASTER_DMAC_DTWR" value="4"/>
              <param name="MASTER_DMAC_DTRD" value="5"/>
              <param name="MASTER_ICM" value="6"/>
              <param name="MASTER_DSU" value="7"/>
              <param name="SLAVE_NUM" value="15"/>
              <param name="SLAVE_FLASH" value="0"/>
              <param name="SLAVE_FLASH_ALT" value="1"/>
              <param name="SLAVE_SEEPROM" value="2"/>
              <param name="SLAVE_RAMCM4S" value="3"/>
              <param name="SLAVE_RAMPPPDSU" value="4"/>
              <param name="SLAVE_RAMDMAWR" value="5"/>
              <param name="SLAVE_RAMDMACICM" value="6"/>
              <param name="SLAVE_HPB0" value="7"/>
              <param name="SLAVE_HPB1" value="8"/>
              <param name="SLAVE_HPB2" value="9"/>
              <param name="SLAVE_HPB3" value="10"/>
              <param name="SLAVE_SDHC0" value="12"/>
              <param name="SLAVE_SDHC1" value="13"/>
              <param name="SLAVE_QSPI" value="14"/>
              <param name="SLAVE_BKUPRAM" value="15"/>
              <param name="INSTANCE_ID" value="38"/>
            </parameters>
          </instance>
        </module>
        <module name="ICM" id="U2010" version="1.2.0">
          <instance name="ICM">
            <register-group name="ICM" name-in-module="ICM" address-space="base" offset="0x42002C00"/>
            <parameters>
              <param name="INSTANCE_ID" value="75"/>
            </parameters>
          </instance>
        </module>
        <module name="I2S" id="U2224" version="2.0.0">
          <instance name="I2S">
            <register-group name="I2S" name-in-module="I2S" address-space="base" offset="0x43002800"/>
            <signals>
              <signal group="FS" index="0" function="J" pad="PA09"/>
              <signal group="FS" index="0" function="J" pad="PA20"/>
              <signal group="FS" index="1" function="J" pad="PA23"/>
              <signal group="FS" index="1" function="J" pad="PB11"/>
              <signal group="MCK" index="0" function="J" pad="PA08"/>
              <signal group="MCK" index="0" function="J" pad="PB17"/>
              <signal group="MCK" index="1" function="J" pad="PB29"/>
              <signal group="MCK" index="1" function="J" pad="PB13"/>
              <signal group="SCK" index="0" function="J" pad="PA10"/>
              <signal group="SCK" index="0" function="J" pad="PB16"/>
              <signal group="SCK" index="1" function="J" pad="PB28"/>
              <signal group="SCK" index="1" function="J" pad="PB12"/>
              <signal group="SDI" function="J" pad="PA22"/>
              <signal group="SDI" function="J" pad="PB10"/>
              <signal group="SDO" function="J" pad="PA11"/>
              <signal group="SDO" function="J" pad="PA21"/>
            </signals>
            <parameters>
              <param name="CLK_NUM" value="2"/>
              <param name="MAX_SLOTS" value="8"/>
              <param name="MAX_WL_BITS" value="32"/>
              <param name="SER_NUM" value="2"/>
              <param name="INSTANCE_ID" value="106"/>
            </parameters>
          </instance>
        </module>
        <module name="MCLK" id="U2408" version="1.0.0">
          <instance name="MCLK">
            <register-group name="MCLK" name-in-module="MCLK" address-space="base" offset="0x40000800"/>
            <parameters>
              <param name="SYSTEM_CLOCK" value="48000000"/>
              <param name="INSTANCE_ID" value="2"/>
            </parameters>
            <clock-groups>
              <clock-group name="AHB" grouporder="0">
                <clock name="HPB0" bit="0"/>
                <clock name="HPB1" bit="1"/>
                <clock name="HPB2" bit="2"/>
                <clock name="HPB3" bit="3"/>
                <clock name="DSU" bit="4"/>
                <clock name="HMATRIX" bit="5"/>
                <clock name="NVMCTRL" bit="6"/>
                <clock name="HSRAM" bit="7"/>
                <clock name="CMCC" bit="8"/>
                <clock name="DMAC" bit="9"/>
                <clock name="USB" bit="10"/>
                <clock name="BKUPRAM" bit="11"/>
                <clock name="PAC" bit="12"/>
                <clock name="QSPI" bit="13"/>
                <clock name="SDHC0" bit="15"/>
                <clock name="SDHC1" bit="16"/>
                <clock name="ICM" bit="19"/>
                <clock name="PUKCC" bit="20"/>
                <clock name="QSPI_2X" bit="21"/>
                <clock name="NVMCTRL_SMEEPROM" bit="22"/>
                <clock name="NVMCTRL_CACHE" bit="23"/>
              </clock-group>
            </clock-groups>
          </instance>
        </module>
        <module name="NVMCTRL" id="U2409" version="1.0.0">
          <instance name="NVMCTRL">
            <register-group name="NVMCTRL" name-in-module="NVMCTRL" address-space="base" offset="0x41004000"/>
            <parameters>
              <param name="BLOCK_SIZE" value="8192"/>
              <param name="FLASH_SIZE" value="524288"/>
              <param name="PAGES" value="1024"/>
              <param name="PAGES_PR_REGION" value="64"/>
                  <!--  From Datasheet section "Electrical Characteristics","Flash Characteristics" table "Maximum operating Frequency" -->
                  <param name="PSM_0_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
                  <param name="PSM_0_FRMLP_FWS_0_MAX_FREQ" value="18000000"/>
                  <param name="PSM_0_FRMLP_FWS_1_MAX_FREQ" value="36000000"/>
                  <param name="PSM_0_FRMHS_FWS_0_MAX_FREQ" value="25000000"/>
                  <param name="PSM_0_FRMHS_FWS_1_MAX_FREQ" value="50000000"/>
                  <param name="PSM_1_FRMFW_FWS_1_MAX_FREQ" value="12000000"/>
                  <param name="PSM_1_FRMLP_FWS_0_MAX_FREQ" value="8000000"/>
                  <param name="PSM_1_FRMLP_FWS_1_MAX_FREQ" value="12000000"/>
              <param name="INSTANCE_ID" value="34"/>
            </parameters>
          </instance>
        </module>
        <module name="FUSES" id="U2409" version="1.0.0">
          <instance name="FUSES">
            <register-group name="SW0_FUSES" name-in-module="SW0_FUSES" address-space="fuses" offset="0x00800080"/>
            <register-group name="TEMP_LOG_FUSES" name-in-module="TEMP_LOG_FUSES" address-space="fuses" offset="0x00800100"/>
            <register-group name="USER_FUSES" name-in-module="USER_FUSES" address-space="fuses" offset="0x00804000"/>
          </instance>
        </module>
        <module name="OSCCTRL" id="U2401" version="1.0.0">
          <instance name="OSCCTRL">
            <register-group name="OSCCTRL" name-in-module="OSCCTRL" address-space="base" offset="0x40001000"/>
            <signals>
              <signal group="XIN" index="0" function="XIN0" pad="PA14"/>
              <signal group="XIN" index="1" function="XIN1" pad="PB22"/>
              <signal group="XOUT" index="0" function="XOUT0" pad="PA15"/>
              <signal group="XOUT" index="1" function="XOUT1" pad="PB23"/>
            </signals>
            <parameters>
              <param name="DFLLS_NUM" value="1"/>
              <param name="DFLL_IMPLEMENTED" value="1"/>
              <param name="DFLL48M_BIASTESTPT_IMPLEMENTED" value="0"/>
              <param name="DFLL48M_CDACSTEPSIZE_SIZE" value="2"/>
              <param name="DFLL48M_COARSE_RESET_VALUE" value="32"/>
              <param name="DFLL48M_COARSE_SIZE" value="6"/>
              <param name="DFLL48M_ENABLE_RESET_VALUE" value="1"/>
              <param name="DFLL48M_FDACSTEPSIZE_SIZE" value="2"/>
              <param name="DFLL48M_FINE_RESET_VALUE" value="128"/>
              <param name="DFLL48M_FINE_SIZE" value="8"/>
              <param name="DFLL48M_ONDEMAND_RESET_VALUE" value="1"/>
              <param name="DFLL48M_RUNSTDBY_RESET_VALUE" value="0"/>
              <param name="DFLL48M_TCAL_SIZE" value="4"/>
              <param name="DFLL48M_TCBIAS_SIZE" value="2"/>
              <param name="DFLL48M_TESTPTSEL_SIZE" value="3"/>
              <param name="DFLL48M_WAITLOCK_ACTIVE" value="1"/>
              <param name="DPLLS_NUM" value="2"/>
              <param name="DPLL0_IMPLEMENTED" value="1"/>
              <param name="DPLL0_I12ND_I12NDFRAC_PAD_CONTROL" value="0"/>
              <param name="DPLL0_OCC_IMPLEMENTED" value="1"/>
              <param name="DPLL1_IMPLEMENTED" value="1"/>
              <param name="DPLL1_I12ND_I12NDFRAC_PAD_CONTROL" value="0"/>
              <param name="DPLL1_OCC_IMPLEMENTED" value="0"/>
              <param name="GCLK_ID_DFLL48" value="0"/>
              <param name="GCLK_ID_FDPLL0" value="1"/>
              <param name="GCLK_ID_FDPLL1" value="2"/>
              <param name="GCLK_ID_FDPLL032K" value="3"/>
              <param name="GCLK_ID_FDPLL132K" value="3"/>
              <param name="OSC16M_IMPLEMENTED" value="0"/>
              <param name="OSC48M_IMPLEMENTED" value="0"/>
              <param name="OSC48M_NUM" value="1"/>
              <param name="RCOSCS_NUM" value="1"/>
              <param name="XOSCS_NUM" value="2"/>
              <param name="XOSC0_CFD_CLK_SELECT_SIZE" value="4"/>
              <param name="XOSC0_CFD_IMPLEMENTED" value="1"/>
              <param name="XOSC0_IMPLEMENTED" value="1"/>
              <param name="XOSC0_ONDEMAND_RESET_VALUE" value="1"/>
              <param name="XOSC0_RUNSTDBY_RESET_VALUE" value="0"/>
              <param name="XOSC1_CFD_CLK_SELECT_SIZE" value="4"/>
              <param name="XOSC1_CFD_IMPLEMENTED" value="1"/>
              <param name="XOSC1_IMPLEMENTED" value="1"/>
              <param name="XOSC1_ONDEMAND_RESET_VALUE" value="1"/>
              <param name="XOSC1_RUNSTDBY_RESET_VALUE" value="0"/>
              <param name="DFLL48M_VERSION" value="0x100"/>
              <param name="FDPLL_VERSION" value="0x100"/>
              <param name="XOSC_VERSION" value="0x100"/>
              <param name="INSTANCE_ID" value="4"/>
            </parameters>
          </instance>
        </module>
        <module name="OSC32KCTRL" id="U2400" version="1.0.0">
          <instance name="OSC32KCTRL">
            <register-group name="OSC32KCTRL" name-in-module="OSC32KCTRL" address-space="base" offset="0x40001400"/>
            <signals>
              <signal group="XIN32" function="XIN32" pad="PA00"/>
              <signal group="XOUT32" function="XOUT32" pad="PA01"/>
            </signals>
            <parameters>
              <param name="OSC32K_COARSE_CALIB_MSB" value="0"/>
              <param name="INSTANCE_ID" value="5"/>
            </parameters>
          </instance>
        </module>
        <module name="PAC" id="U2120" version="1.2.0">
          <instance name="PAC">
            <register-group name="PAC" name-in-module="PAC" address-space="base" offset="0x40000000"/>
            <parameters>
              <param name="HPB_NUM" value="4"/>
              <param name="INSTANCE_ID" value="0"/>
            </parameters>
          </instance>
        </module>
        <module name="PCC" id="U2017" version="1.1.0">
          <instance name="PCC">
            <register-group name="PCC" name-in-module="PCC" address-space="base" offset="0x43002C00"/>
            <signals>
              <signal group="CLK" function="K" pad="PA14"/>
              <signal group="DATA" index="0" function="K" pad="PA16"/>
              <signal group="DATA" index="1" function="K" pad="PA17"/>
              <signal group="DATA" index="2" function="K" pad="PA18"/>
              <signal group="DATA" index="3" function="K" pad="PA19"/>
              <signal group="DATA" index="4" function="K" pad="PA20"/>
              <signal group="DATA" index="5" function="K" pad="PA21"/>
              <signal group="DATA" index="6" function="K" pad="PA22"/>
              <signal group="DATA" index="7" function="K" pad="PA23"/>
              <signal group="DATA" index="8" function="K" pad="PB14"/>
              <signal group="DATA" index="9" function="K" pad="PB15"/>
              <signal group="DATA" index="10" function="K" pad="PC12"/>
              <signal group="DATA" index="11" function="K" pad="PC13"/>
              <signal group="DATA" index="12" function="K" pad="PC14"/>
              <signal group="DATA" index="13" function="K" pad="PC15"/>
              <signal group="DEN1" function="K" pad="PA12"/>
              <signal group="DEN2" function="K" pad="PA13"/>
            </signals>
            <parameters>
              <param name="DATA_SIZE" value="14"/>
              <param name="DMAC_ID_RX" value="80"/>
              <param name="INSTANCE_ID" value="107"/>
            </parameters>
          </instance>
        </module>
        <module name="PDEC" id="U2263" version="1.0.0">
          <instance name="PDEC">
            <register-group name="PDEC" name-in-module="PDEC" address-space="base" offset="0x42001C00"/>
            <signals>
              <signal group="QDI" index="0" function="G" pad="PB18"/>
              <signal group="QDI" index="0" function="G" pad="PB23"/>
              <signal group="QDI" index="0" function="G" pad="PC16"/>
              <signal group="QDI" index="0" function="G" pad="PA24"/>
              <signal group="QDI" index="1" function="G" pad="PB19"/>
              <signal group="QDI" index="1" function="G" pad="PB24"/>
              <signal group="QDI" index="1" function="G" pad="PC17"/>
              <signal group="QDI" index="1" function="G" pad="PA25"/>
              <signal group="QDI" index="2" function="G" pad="PB20"/>
              <signal group="QDI" index="2" function="G" pad="PB25"/>
              <signal group="QDI" index="2" function="G" pad="PC18"/>
              <signal group="QDI" index="2" function="G" pad="PB22"/>
            </signals>
            <parameters>
              <param name="CC_NUM" value="2"/>
              <param name="GCLK_ID" value="31"/>
              <param name="INSTANCE_ID" value="71"/>
            </parameters>
          </instance>
        </module>
        <module name="PM" id="U2406" version="1.0.0">
          <instance name="PM">
            <register-group name="PM" name-in-module="PM" address-space="base" offset="0x40000400"/>
            <signals>
              <signal group="RESET_N" function="default" pad="RESET_N"/>
            </signals>
            <parameters>
              <param name="PD_NUM" value="0"/>
              <param name="INSTANCE_ID" value="1"/>
            </parameters>
          </instance>
        </module>
        <module name="PORT" id="U2210" version="2.2.0">
          <instance name="PORT">
            <register-group name="PORT" name-in-module="PORT" address-space="base" offset="0x41008000"/>
            <signals>
              <signal group="P" index="0" function="default" pad="PA00"/>
              <signal group="P" index="1" function="default" pad="PA01"/>
              <signal group="P" index="2" function="default" pad="PA02"/>
              <signal group="P" index="3" function="default" pad="PA03"/>
              <signal group="P" index="4" function="default" pad="PA04"/>
              <signal group="P" index="5" function="default" pad="PA05"/>
              <signal group="P" index="6" function="default" pad="PA06"/>
              <signal group="P" index="7" function="default" pad="PA07"/>
              <signal group="P" index="8" function="default" pad="PA08"/>
              <signal group="P" index="9" function="default" pad="PA09"/>
              <signal group="P" index="10" function="default" pad="PA10"/>
              <signal group="P" index="11" function="default" pad="PA11"/>
              <signal group="P" index="12" function="default" pad="PA12"/>
              <signal group="P" index="13" function="default" pad="PA13"/>
              <signal group="P" index="14" function="default" pad="PA14"/>
              <signal group="P" index="15" function="default" pad="PA15"/>
              <signal group="P" index="16" function="default" pad="PA16"/>
              <signal group="P" index="17" function="default" pad="PA17"/>
              <signal group="P" index="18" function="default" pad="PA18"/>
              <signal group="P" index="19" function="default" pad="PA19"/>
              <signal group="P" index="20" function="default" pad="PA20"/>
              <signal group="P" index="21" function="default" pad="PA21"/>
              <signal group="P" index="22" function="default" pad="PA22"/>
              <signal group="P" index="23" function="default" pad="PA23"/>
              <signal group="P" index="24" function="default" pad="PA24"/>
              <signal group="P" index="25" function="default" pad="PA25"/>
              <signal group="P" index="27" function="default" pad="PA27"/>
              <signal group="P" index="30" function="default" pad="PA30"/>
              <signal group="P" index="31" function="default" pad="PA31"/>
              <signal group="P" index="32" function="default" pad="PB00"/>
              <signal group="P" index="33" function="default" pad="PB01"/>
              <signal group="P" index="34" function="default" pad="PB02"/>
              <signal group="P" index="35" function="default" pad="PB03"/>
              <signal group="P" index="36" function="default" pad="PB04"/>
              <signal group="P" index="37" function="default" pad="PB05"/>
              <signal group="P" index="38" function="default" pad="PB06"/>
              <signal group="P" index="39" function="default" pad="PB07"/>
              <signal group="P" index="40" function="default" pad="PB08"/>
              <signal group="P" index="41" function="default" pad="PB09"/>
              <signal group="P" index="42" function="default" pad="PB10"/>
              <signal group="P" index="43" function="default" pad="PB11"/>
              <signal group="P" index="44" function="default" pad="PB12"/>
              <signal group="P" index="45" function="default" pad="PB13"/>
              <signal group="P" index="46" function="default" pad="PB14"/>
              <signal group="P" index="47" function="default" pad="PB15"/>
              <signal group="P" index="48" function="default" pad="PB16"/>
              <signal group="P" index="49" function="default" pad="PB17"/>
              <signal group="P" index="50" function="default" pad="PB18"/>
              <signal group="P" index="51" function="default" pad="PB19"/>
              <signal group="P" index="52" function="default" pad="PB20"/>
              <signal group="P" index="53" function="default" pad="PB21"/>
              <signal group="P" index="54" function="default" pad="PB22"/>
              <signal group="P" index="55" function="default" pad="PB23"/>
              <signal group="P" index="56" function="default" pad="PB24"/>
              <signal group="P" index="57" function="default" pad="PB25"/>
              <signal group="P" index="58" function="default" pad="PB26"/>
              <signal group="P" index="59" function="default" pad="PB27"/>
              <signal group="P" index="60" function="default" pad="PB28"/>
              <signal group="P" index="61" function="default" pad="PB29"/>
              <signal group="P" index="62" function="default" pad="PB30"/>
              <signal group="P" index="63" function="default" pad="PB31"/>
              <signal group="P" index="64" function="default" pad="PC00"/>
              <signal group="P" index="65" function="default" pad="PC01"/>
              <signal group="P" index="66" function="default" pad="PC02"/>
              <signal group="P" index="67" function="default" pad="PC03"/>
              <signal group="P" index="68" function="default" pad="PC04"/>
              <signal group="P" index="69" function="default" pad="PC05"/>
              <signal group="P" index="70" function="default" pad="PC06"/>
              <signal group="P" index="71" function="default" pad="PC07"/>
              <signal group="P" index="74" function="default" pad="PC10"/>
              <signal group="P" index="75" function="default" pad="PC11"/>
              <signal group="P" index="76" function="default" pad="PC12"/>
              <signal group="P" index="77" function="default" pad="PC13"/>
              <signal group="P" index="78" function="default" pad="PC14"/>
              <signal group="P" index="79" function="default" pad="PC15"/>
              <signal group="P" index="80" function="default" pad="PC16"/>
              <signal group="P" index="81" function="default" pad="PC17"/>
              <signal group="P" index="82" function="default" pad="PC18"/>
              <signal group="P" index="83" function="default" pad="PC19"/>
              <signal group="P" index="84" function="default" pad="PC20"/>
              <signal group="P" index="85" function="default" pad="PC21"/>
              <signal group="P" index="86" function="default" pad="PC22"/>
              <signal group="P" index="87" function="default" pad="PC23"/>
              <signal group="P" index="88" function="default" pad="PC24"/>
              <signal group="P" index="89" function="default" pad="PC25"/>
              <signal group="P" index="90" function="default" pad="PC26"/>
              <signal group="P" index="91" function="default" pad="PC27"/>
              <signal group="P" index="92" function="default" pad="PC28"/>
              <signal group="P" index="94" function="default" pad="PC30"/>
              <signal group="P" index="95" function="default" pad="PC31"/>
              <signal group="P" index="96" function="default" pad="PD00"/>
              <signal group="P" index="97" function="default" pad="PD01"/>
              <signal group="P" index="104" function="default" pad="PD08"/>
              <signal group="P" index="105" function="default" pad="PD09"/>
              <signal group="P" index="106" function="default" pad="PD10"/>
              <signal group="P" index="107" function="default" pad="PD11"/>
              <signal group="P" index="108" function="default" pad="PD12"/>
              <signal group="P" index="116" function="default" pad="PD20"/>
              <signal group="P" index="117" function="default" pad="PD21"/>
            </signals>
            <parameters>
              <param name="BITS" value="118"/>
              <param name="DRVSTR" value="1"/>
              <param name="EV_NUM" value="4"/>
              <param name="GROUPS" value="4"/>
              <param name="ODRAIN" value="0"/>
              <param name="SLEWLIM" value="0"/>
              <param name="INSTANCE_ID" value="36"/>
            </parameters>
          </instance>
        </module>
        <module name="PUKCC" id="U2009" version="2.5.0">
          <instance name="PUKCC">
            <parameters>
              <param name="RAM_ADDR_SIZE" value="12"/>
              <param name="ROM_ADDR_SIZE" value="16"/>
              <param name="INSTANCE_ID" value="76"/>
            </parameters>
          </instance>
        </module>
        <module name="QSPI" id="U2008" version="1.6.3">
          <instance name="QSPI">
            <register-group name="QSPI" name-in-module="QSPI" address-space="base" offset="0x42003400"/>
            <signals>
              <signal group="CS" function="H" pad="PB11"/>
              <signal group="DATA" index="0" function="H" pad="PA08"/>
              <signal group="DATA" index="1" function="H" pad="PA09"/>
              <signal group="DATA" index="2" function="H" pad="PA10"/>
              <signal group="DATA" index="3" function="H" pad="PA11"/>
              <signal group="SCK" function="H" pad="PB10"/>
            </signals>
            <parameters>
              <param name="DMAC_ID_RX" value="83"/>
              <param name="DMAC_ID_TX" value="84"/>
              <param name="HADDR_MSB" value="23"/>
              <param name="OCMS" value="1"/>
              <param name="INSTANCE_ID" value="77"/>
            </parameters>
          </instance>
        </module>
        <module name="RAMECC" id="U2268" version="1.0.0">
          <instance name="RAMECC">
            <register-group name="RAMECC" name-in-module="RAMECC" address-space="base" offset="0x41020000"/>
            <parameters>
              <param name="RAMADDR_BITS" value="13"/>
              <param name="RAMBANK_NUM" value="4"/>
              <param name="INSTANCE_ID" value="48"/>
            </parameters>
          </instance>
        </module>
        <module name="RSTC" id="U2239" version="4.0.0">
          <instance name="RSTC">
            <register-group name="RSTC" name-in-module="RSTC" address-space="base" offset="0x40000C00"/>
            <parameters>
              <param name="BACKUP_IMPLEMENTED" value="1"/>
              <param name="HIB_IMPLEMENTED" value="1"/>
              <param name="NUMBER_OF_EXTWAKE" value="0"/>
              <param name="NVMRST_IMPLEMENTED" value="1"/>
              <param name="INSTANCE_ID" value="3"/>
            </parameters>
          </instance>
        </module>
        <module name="RTC" id="U2250" version="2.1.0">
          <instance name="RTC">
            <register-group name="RTC" name-in-module="RTC" address-space="base" offset="0x40002400"/>
            <signals>
              <signal group="IN" index="0" function="RTC" pad="PB00"/>
              <signal group="IN" index="1" function="RTC" pad="PB02"/>
              <signal group="IN" index="2" function="RTC_IN_2" pad="PA02"/>
              <signal group="IN" index="3" function="RTC" pad="PC00"/>
              <signal group="IN" index="4" function="RTC" pad="PC01"/>
              <signal group="OUT" function="RTC" pad="PB01"/>
            </signals>
            <parameters>
              <param name="DMAC_ID_TIMESTAMP" value="1"/>
              <param name="GPR_NUM" value="4"/>
              <param name="NUM_OF_ALARMS" value="2"/>
              <param name="NUM_OF_BKREGS" value="8"/>
              <param name="NUM_OF_COMP16" value="4"/>
              <param name="NUM_OF_COMP32" value="2"/>
              <param name="NUM_OF_TAMPERS" value="5"/>
              <param name="PER_NUM" value="8"/>
              <param name="INSTANCE_ID" value="9"/>
            </parameters>
          </instance>
        </module>
        <module name="SDHC" id="U2011" version="1.8.3">
          <instance name="SDHC0">
            <register-group name="SDHC0" name-in-module="SDHC" address-space="base" offset="0x45000000"/>
            <signals>
              <signal group="SDCD" function="I" pad="PA06"/>
              <signal group="SDCD" function="I" pad="PA12"/>
              <signal group="SDCD" function="I" pad="PB12"/>
              <signal group="SDCD" function="I" pad="PC06"/>
              <signal group="SDCK" function="I" pad="PB11"/>
              <signal group="SDCMD" function="I" pad="PA08"/>
              <signal group="SDDAT" index="0" function="I" pad="PA09"/>
              <signal group="SDDAT" index="1" function="I" pad="PA10"/>
              <signal group="SDDAT" index="2" function="I" pad="PA11"/>
              <signal group="SDDAT" index="3" function="I" pad="PB10"/>
              <signal group="SDWP" function="I" pad="PA07"/>
              <signal group="SDWP" function="I" pad="PA13"/>
              <signal group="SDWP" function="I" pad="PB13"/>
              <signal group="SDWP" function="I" pad="PC07"/>
            </signals>
            <parameters>
              <param name="CARD_DATA_SIZE" value="4"/>
              <param name="GCLK_ID" value="45"/>
              <param name="GCLK_ID_SLOW" value="3"/>
              <param name="NB_OF_DEVICES" value="1"/>
              <param name="NB_REG_PVR" value="8"/>
              <param name="NB_REG_RR" value="4"/>
            </parameters>
          </instance>
          <instance name="SDHC1">
            <register-group name="SDHC1" name-in-module="SDHC" address-space="base" offset="0x46000000"/>
            <signals>
              <signal group="SDCD" function="I" pad="PB16"/>
              <signal group="SDCD" function="I" pad="PC20"/>
              <signal group="SDCD" function="I" pad="PD20"/>
              <signal group="SDCK" function="I" pad="PA21"/>
              <signal group="SDCMD" function="I" pad="PA20"/>
              <signal group="SDDAT" index="0" function="I" pad="PB18"/>
              <signal group="SDDAT" index="1" function="I" pad="PB19"/>
              <signal group="SDDAT" index="2" function="I" pad="PB20"/>
              <signal group="SDDAT" index="3" function="I" pad="PB21"/>
              <signal group="SDWP" function="I" pad="PB17"/>
              <signal group="SDWP" function="I" pad="PC21"/>
              <signal group="SDWP" function="I" pad="PD21"/>
            </signals>
            <parameters>
              <param name="CARD_DATA_SIZE" value="4"/>
              <param name="GCLK_ID" value="46"/>
              <param name="GCLK_ID_SLOW" value="3"/>
              <param name="NB_OF_DEVICES" value="1"/>
              <param name="NB_REG_PVR" value="8"/>
              <param name="NB_REG_RR" value="4"/>
            </parameters>
          </instance>
        </module>
        <module name="SERCOM" id="U2201" version="5.0.0">
          <instance name="SERCOM0">
            <register-group name="SERCOM0" name-in-module="SERCOM" address-space="base" offset="0x40003000"/>
            <signals>
              <signal group="PAD" index="0" function="D" pad="PA04"/>
              <signal group="PAD" index="0" function="D" pad="PC17"/>
              <signal group="PAD" index="0" function="C" pad="PA08"/>
              <signal group="PAD" index="0" function="C" pad="PB24"/>
              <signal group="PAD" index="1" function="D" pad="PA05"/>
              <signal group="PAD" index="1" function="D" pad="PC16"/>
              <signal group="PAD" index="1" function="C" pad="PA09"/>
              <signal group="PAD" index="1" function="C" pad="PB25"/>
              <signal group="PAD" index="2" function="D" pad="PA06"/>
              <signal group="PAD" index="2" function="D" pad="PC18"/>
              <signal group="PAD" index="2" function="C" pad="PA10"/>
              <signal group="PAD" index="2" function="C" pad="PC24"/>
              <signal group="PAD" index="3" function="D" pad="PA07"/>
              <signal group="PAD" index="3" function="D" pad="PC19"/>
              <signal group="PAD" index="3" function="C" pad="PA11"/>
              <signal group="PAD" index="3" function="C" pad="PC25"/>
            </signals>
            <parameters>
              <param name="CLK_REDUCTION" value="1"/>
              <param name="DLY_COMPENSATION" value="1"/>
              <param name="DMA" value="1"/>
              <param name="DMAC_ID_RX" value="4"/>
              <param name="DMAC_ID_TX" value="5"/>
              <param name="FIFO_DEPTH_POWER" value="1"/>
              <param name="GCLK_ID_CORE" value="7"/>
              <param name="GCLK_ID_SLOW" value="3"/>
              <param name="INT_MSB" value="6"/>
              <param name="PMSB" value="3"/>
              <param name="RETENTION_SUPPORT" value="0"/>
              <param name="SE_CNT" value="1"/>
              <param name="SPI" value="1"/>
              <param name="SPI_HW_SS_CTRL" value="1"/>
              <param name="SPI_ICSPACE_EXT" value="1"/>
              <param name="SPI_OZMO" value="0"/>
              <param name="SPI_WAKE_ON_SSL" value="1"/>
              <param name="TTBIT_EXTENSION" value="1"/>
              <param name="TWIM" value="1"/>
              <param name="TWIS" value="1"/>
              <param name="TWIS_AUTO_ACK" value="1"/>
              <param name="TWIS_GROUP_CMD" value="1"/>
              <param name="TWIS_SDASETUP_CNT_SIZE" value="8"/>
              <param name="TWIS_SDASETUP_SIZE" value="4"/>
              <param name="TWIS_SUDAT" value="1"/>
              <param name="TWI_FASTMP" value="1"/>
              <param name="TWI_HSMODE" value="1"/>
              <param name="TWI_SCLSM_MODE" value="1"/>
              <param name="TWI_SMB_TIMEOUTS" value="1"/>
              <param name="TWI_TENBIT_ADR" value="1"/>
              <param name="USART" value="1"/>
              <param name="USART_AUTOBAUD" value="1"/>
              <param name="USART_COLDET" value="1"/>
              <param name="USART_FLOW_CTRL" value="1"/>
              <param name="USART_FRAC_BAUD" value="1"/>
              <param name="USART_IRDA" value="1"/>
              <param name="USART_ISO7816" value="1"/>
              <param name="USART_LIN_MASTER" value="1"/>
              <param name="USART_RS485" value="1"/>
              <param name="USART_SAMPA_EXT" value="1"/>
              <param name="USART_SAMPR_EXT" value="1"/>
              <param name="INSTANCE_ID" value="12"/>
            </parameters>
          </instance>
          <instance name="SERCOM1">
            <register-group name="SERCOM1" name-in-module="SERCOM" address-space="base" offset="0x40003400"/>
            <signals>
              <signal group="PAD" index="0" function="D" pad="PA00"/>
              <signal group="PAD" index="0" function="C" pad="PA16"/>
              <signal group="PAD" index="0" function="C" pad="PC22"/>
              <signal group="PAD" index="0" function="C" pad="PC27"/>
              <signal group="PAD" index="1" function="D" pad="PA01"/>
              <signal group="PAD" index="1" function="C" pad="PA17"/>
              <signal group="PAD" index="1" function="C" pad="PC23"/>
              <signal group="PAD" index="1" function="C" pad="PC28"/>
              <signal group="PAD" index="2" function="D" pad="PA30"/>
              <signal group="PAD" index="2" function="C" pad="PA18"/>
              <signal group="PAD" index="2" function="C" pad="PB22"/>
              <signal group="PAD" index="2" function="C" pad="PD20"/>
              <signal group="PAD" index="3" function="D" pad="PA31"/>
              <signal group="PAD" index="3" function="C" pad="PA19"/>
              <signal group="PAD" index="3" function="C" pad="PB23"/>
              <signal group="PAD" index="3" function="C" pad="PD21"/>
            </signals>
            <parameters>
              <param name="CLK_REDUCTION" value="1"/>
              <param name="DLY_COMPENSATION" value="1"/>
              <param name="DMA" value="1"/>
              <param name="DMAC_ID_RX" value="6"/>
              <param name="DMAC_ID_TX" value="7"/>
              <param name="FIFO_DEPTH_POWER" value="1"/>
              <param name="GCLK_ID_CORE" value="8"/>
              <param name="GCLK_ID_SLOW" value="3"/>
              <param name="INT_MSB" value="6"/>
              <param name="PMSB" value="3"/>
              <param name="RETENTION_SUPPORT" value="0"/>
              <param name="SE_CNT" value="1"/>
              <param name="SPI" value="1"/>
              <param name="SPI_HW_SS_CTRL" value="1"/>
              <param name="SPI_ICSPACE_EXT" value="1"/>
              <param name="SPI_OZMO" value="0"/>
              <param name="SPI_WAKE_ON_SSL" value="1"/>
              <param name="TTBIT_EXTENSION" value="1"/>
              <param name="TWIM" value="1"/>
              <param name="TWIS" value="1"/>
              <param name="TWIS_AUTO_ACK" value="1"/>
              <param name="TWIS_GROUP_CMD" value="1"/>
              <param name="TWIS_SDASETUP_CNT_SIZE" value="8"/>
              <param name="TWIS_SDASETUP_SIZE" value="4"/>
              <param name="TWIS_SUDAT" value="1"/>
              <param name="TWI_FASTMP" value="1"/>
              <param name="TWI_HSMODE" value="1"/>
              <param name="TWI_SCLSM_MODE" value="1"/>
              <param name="TWI_SMB_TIMEOUTS" value="1"/>
              <param name="TWI_TENBIT_ADR" value="1"/>
              <param name="USART" value="1"/>
              <param name="USART_AUTOBAUD" value="1"/>
              <param name="USART_COLDET" value="1"/>
              <param name="USART_FLOW_CTRL" value="1"/>
              <param name="USART_FRAC_BAUD" value="1"/>
              <param name="USART_IRDA" value="1"/>
              <param name="USART_ISO7816" value="1"/>
              <param name="USART_LIN_MASTER" value="1"/>
              <param name="USART_RS485" value="1"/>
              <param name="USART_SAMPA_EXT" value="1"/>
              <param name="USART_SAMPR_EXT" value="1"/>
              <param name="INSTANCE_ID" value="13"/>
            </parameters>
          </instance>
          <instance name="SERCOM2">
            <register-group name="SERCOM2" name-in-module="SERCOM" address-space="base" offset="0x41012000"/>
            <signals>
              <signal group="PAD" index="0" function="D" pad="PA09"/>
              <signal group="PAD" index="0" function="D" pad="PB25"/>
              <signal group="PAD" index="0" function="C" pad="PA12"/>
              <signal group="PAD" index="0" function="C" pad="PB26"/>
              <signal group="PAD" index="1" function="D" pad="PA08"/>
              <signal group="PAD" index="1" function="D" pad="PB24"/>
              <signal group="PAD" index="1" function="C" pad="PA13"/>
              <signal group="PAD" index="1" function="C" pad="PB27"/>
              <signal group="PAD" index="2" function="D" pad="PA10"/>
              <signal group="PAD" index="2" function="D" pad="PC24"/>
              <signal group="PAD" index="2" function="C" pad="PB28"/>
              <signal group="PAD" index="2" function="C" pad="PA14"/>
              <signal group="PAD" index="3" function="D" pad="PA11"/>
              <signal group="PAD" index="3" function="D" pad="PC25"/>
              <signal group="PAD" index="3" function="C" pad="PB29"/>
              <signal group="PAD" index="3" function="C" pad="PA15"/>
            </signals>
            <parameters>
              <param name="CLK_REDUCTION" value="1"/>
              <param name="DLY_COMPENSATION" value="1"/>
              <param name="DMA" value="1"/>
              <param name="DMAC_ID_RX" value="8"/>
              <param name="DMAC_ID_TX" value="9"/>
              <param name="FIFO_DEPTH_POWER" value="1"/>
              <param name="GCLK_ID_CORE" value="23"/>
              <param name="GCLK_ID_SLOW" value="3"/>
              <param name="INT_MSB" value="6"/>
              <param name="PMSB" value="3"/>
              <param name="RETENTION_SUPPORT" value="0"/>
              <param name="SE_CNT" value="1"/>
              <param name="SPI" value="1"/>
              <param name="SPI_HW_SS_CTRL" value="1"/>
              <param name="SPI_ICSPACE_EXT" value="1"/>
              <param name="SPI_OZMO" value="0"/>
              <param name="SPI_WAKE_ON_SSL" value="1"/>
              <param name="TTBIT_EXTENSION" value="1"/>
              <param name="TWIM" value="1"/>
              <param name="TWIS" value="1"/>
              <param name="TWIS_AUTO_ACK" value="1"/>
              <param name="TWIS_GROUP_CMD" value="1"/>
              <param name="TWIS_SDASETUP_CNT_SIZE" value="8"/>
              <param name="TWIS_SDASETUP_SIZE" value="4"/>
              <param name="TWIS_SUDAT" value="1"/>
              <param name="TWI_FASTMP" value="1"/>
              <param name="TWI_HSMODE" value="1"/>
              <param name="TWI_SCLSM_MODE" value="1"/>
              <param name="TWI_SMB_TIMEOUTS" value="1"/>
              <param name="TWI_TENBIT_ADR" value="1"/>
              <param name="USART" value="1"/>
              <param name="USART_AUTOBAUD" value="1"/>
              <param name="USART_COLDET" value="1"/>
              <param name="USART_FLOW_CTRL" value="1"/>
              <param name="USART_FRAC_BAUD" value="1"/>
              <param name="USART_IRDA" value="1"/>
              <param name="USART_ISO7816" value="1"/>
              <param name="USART_LIN_MASTER" value="1"/>
              <param name="USART_RS485" value="1"/>
              <param name="USART_SAMPA_EXT" value="1"/>
              <param name="USART_SAMPR_EXT" value="1"/>
              <param name="INSTANCE_ID" value="41"/>
            </parameters>
          </instance>
          <instance name="SERCOM3">
            <register-group name="SERCOM3" name-in-module="SERCOM" address-space="base" offset="0x41014000"/>
            <signals>
              <signal group="PAD" index="0" function="D" pad="PA17"/>
              <signal group="PAD" index="0" function="D" pad="PC23"/>
              <signal group="PAD" index="0" function="C" pad="PA22"/>
              <signal group="PAD" index="0" function="C" pad="PB20"/>
              <signal group="PAD" index="1" function="D" pad="PA16"/>
              <signal group="PAD" index="1" function="D" pad="PC22"/>
              <signal group="PAD" index="1" function="C" pad="PA23"/>
              <signal group="PAD" index="1" function="C" pad="PB21"/>
              <signal group="PAD" index="2" function="D" pad="PA18"/>
              <signal group="PAD" index="2" function="D" pad="PA20"/>
              <signal group="PAD" index="2" function="D" pad="PD20"/>
              <signal group="PAD" index="2" function="C" pad="PA24"/>
              <signal group="PAD" index="3" function="D" pad="PA19"/>
              <signal group="PAD" index="3" function="D" pad="PA21"/>
              <signal group="PAD" index="3" function="D" pad="PD21"/>
              <signal group="PAD" index="3" function="C" pad="PA25"/>
            </signals>
            <parameters>
              <param name="CLK_REDUCTION" value="1"/>
              <param name="DLY_COMPENSATION" value="1"/>
              <param name="DMA" value="1"/>
              <param name="DMAC_ID_RX" value="10"/>
              <param name="DMAC_ID_TX" value="11"/>
              <param name="FIFO_DEPTH_POWER" value="1"/>
              <param name="GCLK_ID_CORE" value="24"/>
              <param name="GCLK_ID_SLOW" value="3"/>
              <param name="INT_MSB" value="6"/>
              <param name="PMSB" value="3"/>
              <param name="RETENTION_SUPPORT" value="0"/>
              <param name="SE_CNT" value="1"/>
              <param name="SPI" value="1"/>
              <param name="SPI_HW_SS_CTRL" value="1"/>
              <param name="SPI_ICSPACE_EXT" value="1"/>
              <param name="SPI_OZMO" value="0"/>
              <param name="SPI_WAKE_ON_SSL" value="1"/>
              <param name="TTBIT_EXTENSION" value="1"/>
              <param name="TWIM" value="1"/>
              <param name="TWIS" value="1"/>
              <param name="TWIS_AUTO_ACK" value="1"/>
              <param name="TWIS_GROUP_CMD" value="1"/>
              <param name="TWIS_SDASETUP_CNT_SIZE" value="8"/>
              <param name="TWIS_SDASETUP_SIZE" value="4"/>
              <param name="TWIS_SUDAT" value="1"/>
              <param name="TWI_FASTMP" value="1"/>
              <param name="TWI_HSMODE" value="1"/>
              <param name="TWI_SCLSM_MODE" value="1"/>
              <param name="TWI_SMB_TIMEOUTS" value="1"/>
              <param name="TWI_TENBIT_ADR" value="1"/>
              <param name="USART" value="1"/>
              <param name="USART_AUTOBAUD" value="1"/>
              <param name="USART_COLDET" value="1"/>
              <param name="USART_FLOW_CTRL" value="1"/>
              <param name="USART_FRAC_BAUD" value="1"/>
              <param name="USART_IRDA" value="1"/>
              <param name="USART_ISO7816" value="1"/>
              <param name="USART_LIN_MASTER" value="1"/>
              <param name="USART_RS485" value="1"/>
              <param name="USART_SAMPA_EXT" value="1"/>
              <param name="USART_SAMPR_EXT" value="1"/>
              <param name="INSTANCE_ID" value="42"/>
            </parameters>
          </instance>
          <instance name="SERCOM4">
            <register-group name="SERCOM4" name-in-module="SERCOM" address-space="base" offset="0x43000000"/>
            <signals>
              <signal group="PAD" index="0" function="D" pad="PA13"/>
              <signal group="PAD" index="0" function="D" pad="PB08"/>
              <signal group="PAD" index="0" function="D" pad="PB27"/>
              <signal group="PAD" index="0" function="C" pad="PB12"/>
              <signal group="PAD" index="1" function="D" pad="PA12"/>
              <signal group="PAD" index="1" function="D" pad="PB09"/>
              <signal group="PAD" index="1" function="D" pad="PB26"/>
              <signal group="PAD" index="1" function="C" pad="PB13"/>
              <signal group="PAD" index="2" function="D" pad="PA14"/>
              <signal group="PAD" index="2" function="D" pad="PB10"/>
              <signal group="PAD" index="2" function="D" pad="PB28"/>
              <signal group="PAD" index="2" function="C" pad="PB14"/>
              <signal group="PAD" index="3" function="D" pad="PB11"/>
              <signal group="PAD" index="3" function="D" pad="PB29"/>
              <signal group="PAD" index="3" function="D" pad="PA15"/>
              <signal group="PAD" index="3" function="C" pad="PB15"/>
            </signals>
            <parameters>
              <param name="CLK_REDUCTION" value="1"/>
              <param name="DLY_COMPENSATION" value="1"/>
              <param name="DMA" value="1"/>
              <param name="DMAC_ID_RX" value="12"/>
              <param name="DMAC_ID_TX" value="13"/>
              <param name="FIFO_DEPTH_POWER" value="1"/>
              <param name="GCLK_ID_CORE" value="34"/>
              <param name="GCLK_ID_SLOW" value="3"/>
              <param name="INT_MSB" value="6"/>
              <param name="PMSB" value="3"/>
              <param name="RETENTION_SUPPORT" value="0"/>
              <param name="SE_CNT" value="1"/>
              <param name="SPI" value="1"/>
              <param name="SPI_HW_SS_CTRL" value="1"/>
              <param name="SPI_ICSPACE_EXT" value="1"/>
              <param name="SPI_OZMO" value="0"/>
              <param name="SPI_WAKE_ON_SSL" value="1"/>
              <param name="TTBIT_EXTENSION" value="1"/>
              <param name="TWIM" value="1"/>
              <param name="TWIS" value="1"/>
              <param name="TWIS_AUTO_ACK" value="1"/>
              <param name="TWIS_GROUP_CMD" value="1"/>
              <param name="TWIS_SDASETUP_CNT_SIZE" value="8"/>
              <param name="TWIS_SDASETUP_SIZE" value="4"/>
              <param name="TWIS_SUDAT" value="1"/>
              <param name="TWI_FASTMP" value="1"/>
              <param name="TWI_HSMODE" value="1"/>
              <param name="TWI_SCLSM_MODE" value="1"/>
              <param name="TWI_SMB_TIMEOUTS" value="1"/>
              <param name="TWI_TENBIT_ADR" value="1"/>
              <param name="USART" value="1"/>
              <param name="USART_AUTOBAUD" value="1"/>
              <param name="USART_COLDET" value="1"/>
              <param name="USART_FLOW_CTRL" value="1"/>
              <param name="USART_FRAC_BAUD" value="1"/>
              <param name="USART_IRDA" value="1"/>
              <param name="USART_ISO7816" value="1"/>
              <param name="USART_LIN_MASTER" value="1"/>
              <param name="USART_RS485" value="1"/>
              <param name="USART_SAMPA_EXT" value="1"/>
              <param name="USART_SAMPR_EXT" value="1"/>
              <param name="INSTANCE_ID" value="96"/>
            </parameters>
          </instance>
          <instance name="SERCOM5">
            <register-group name="SERCOM5" name-in-module="SERCOM" address-space="base" offset="0x43000400"/>
            <signals>
              <signal group="PAD" index="0" function="D" pad="PA23"/>
              <signal group="PAD" index="0" function="D" pad="PB02"/>
              <signal group="PAD" index="0" function="D" pad="PB31"/>
              <signal group="PAD" index="0" function="C" pad="PB16"/>
              <signal group="PAD" index="1" function="D" pad="PA22"/>
              <signal group="PAD" index="1" function="D" pad="PB03"/>
              <signal group="PAD" index="1" function="D" pad="PB30"/>
              <signal group="PAD" index="1" function="C" pad="PB17"/>
              <signal group="PAD" index="2" function="D" pad="PA24"/>
              <signal group="PAD" index="2" function="D" pad="PB00"/>
              <signal group="PAD" index="2" function="D" pad="PB22"/>
              <signal group="PAD" index="2" function="C" pad="PA20"/>
              <signal group="PAD" index="2" function="C" pad="PB18"/>
              <signal group="PAD" index="3" function="D" pad="PA25"/>
              <signal group="PAD" index="3" function="D" pad="PB01"/>
              <signal group="PAD" index="3" function="D" pad="PB23"/>
              <signal group="PAD" index="3" function="C" pad="PA21"/>
              <signal group="PAD" index="3" function="C" pad="PB19"/>
            </signals>
            <parameters>
              <param name="CLK_REDUCTION" value="1"/>
              <param name="DLY_COMPENSATION" value="1"/>
              <param name="DMA" value="1"/>
              <param name="DMAC_ID_RX" value="14"/>
              <param name="DMAC_ID_TX" value="15"/>
              <param name="FIFO_DEPTH_POWER" value="1"/>
              <param name="GCLK_ID_CORE" value="35"/>
              <param name="GCLK_ID_SLOW" value="3"/>
              <param name="INT_MSB" value="6"/>
              <param name="PMSB" value="3"/>
              <param name="RETENTION_SUPPORT" value="0"/>
              <param name="SE_CNT" value="1"/>
              <param name="SPI" value="1"/>
              <param name="SPI_HW_SS_CTRL" value="1"/>
              <param name="SPI_ICSPACE_EXT" value="1"/>
              <param name="SPI_OZMO" value="0"/>
              <param name="SPI_WAKE_ON_SSL" value="1"/>
              <param name="TTBIT_EXTENSION" value="1"/>
              <param name="TWIM" value="1"/>
              <param name="TWIS" value="1"/>
              <param name="TWIS_AUTO_ACK" value="1"/>
              <param name="TWIS_GROUP_CMD" value="1"/>
              <param name="TWIS_SDASETUP_CNT_SIZE" value="8"/>
              <param name="TWIS_SDASETUP_SIZE" value="4"/>
              <param name="TWIS_SUDAT" value="1"/>
              <param name="TWI_FASTMP" value="1"/>
              <param name="TWI_HSMODE" value="1"/>
              <param name="TWI_SCLSM_MODE" value="1"/>
              <param name="TWI_SMB_TIMEOUTS" value="1"/>
              <param name="TWI_TENBIT_ADR" value="1"/>
              <param name="USART" value="1"/>
              <param name="USART_AUTOBAUD" value="1"/>
              <param name="USART_COLDET" value="1"/>
              <param name="USART_FLOW_CTRL" value="1"/>
              <param name="USART_FRAC_BAUD" value="1"/>
              <param name="USART_IRDA" value="1"/>
              <param name="USART_ISO7816" value="1"/>
              <param name="USART_LIN_MASTER" value="1"/>
              <param name="USART_RS485" value="1"/>
              <param name="USART_SAMPA_EXT" value="1"/>
              <param name="USART_SAMPR_EXT" value="1"/>
              <param name="INSTANCE_ID" value="97"/>
            </parameters>
          </instance>
          <instance name="SERCOM6">
            <register-group name="SERCOM6" name-in-module="SERCOM" address-space="base" offset="0x43000800"/>
            <signals>
              <signal group="PAD" index="0" function="D" pad="PD09"/>
              <signal group="PAD" index="0" function="D" pad="PC13"/>
              <signal group="PAD" index="0" function="C" pad="PC04"/>
              <signal group="PAD" index="0" function="C" pad="PC16"/>
              <signal group="PAD" index="1" function="D" pad="PD08"/>
              <signal group="PAD" index="1" function="D" pad="PC12"/>
              <signal group="PAD" index="1" function="C" pad="PC05"/>
              <signal group="PAD" index="1" function="C" pad="PC17"/>
              <signal group="PAD" index="2" function="D" pad="PC14"/>
              <signal group="PAD" index="2" function="D" pad="PD10"/>
              <signal group="PAD" index="2" function="C" pad="PC06"/>
              <signal group="PAD" index="2" function="C" pad="PC10"/>
              <signal group="PAD" index="2" function="C" pad="PC18"/>
              <signal group="PAD" index="3" function="D" pad="PC15"/>
              <signal group="PAD" index="3" function="D" pad="PD11"/>
              <signal group="PAD" index="3" function="C" pad="PC07"/>
              <signal group="PAD" index="3" function="C" pad="PC11"/>
              <signal group="PAD" index="3" function="C" pad="PC19"/>
            </signals>
            <parameters>
              <param name="CLK_REDUCTION" value="1"/>
              <param name="DLY_COMPENSATION" value="1"/>
              <param name="DMA" value="1"/>
              <param name="DMAC_ID_RX" value="16"/>
              <param name="DMAC_ID_TX" value="17"/>
              <param name="FIFO_DEPTH_POWER" value="1"/>
              <param name="GCLK_ID_CORE" value="36"/>
              <param name="GCLK_ID_SLOW" value="3"/>
              <param name="INT_MSB" value="6"/>
              <param name="PMSB" value="3"/>
              <param name="RETENTION_SUPPORT" value="0"/>
              <param name="SE_CNT" value="1"/>
              <param name="SPI" value="1"/>
              <param name="SPI_HW_SS_CTRL" value="1"/>
              <param name="SPI_ICSPACE_EXT" value="1"/>
              <param name="SPI_OZMO" value="0"/>
              <param name="SPI_WAKE_ON_SSL" value="1"/>
              <param name="TTBIT_EXTENSION" value="1"/>
              <param name="TWIM" value="1"/>
              <param name="TWIS" value="1"/>
              <param name="TWIS_AUTO_ACK" value="1"/>
              <param name="TWIS_GROUP_CMD" value="1"/>
              <param name="TWIS_SDASETUP_CNT_SIZE" value="8"/>
              <param name="TWIS_SDASETUP_SIZE" value="4"/>
              <param name="TWIS_SUDAT" value="1"/>
              <param name="TWI_FASTMP" value="1"/>
              <param name="TWI_HSMODE" value="1"/>
              <param name="TWI_SCLSM_MODE" value="1"/>
              <param name="TWI_SMB_TIMEOUTS" value="1"/>
              <param name="TWI_TENBIT_ADR" value="1"/>
              <param name="USART" value="1"/>
              <param name="USART_AUTOBAUD" value="1"/>
              <param name="USART_COLDET" value="1"/>
              <param name="USART_FLOW_CTRL" value="1"/>
              <param name="USART_FRAC_BAUD" value="1"/>
              <param name="USART_IRDA" value="1"/>
              <param name="USART_ISO7816" value="1"/>
              <param name="USART_LIN_MASTER" value="1"/>
              <param name="USART_RS485" value="1"/>
              <param name="USART_SAMPA_EXT" value="1"/>
              <param name="USART_SAMPR_EXT" value="1"/>
              <param name="INSTANCE_ID" value="98"/>
            </parameters>
          </instance>
          <instance name="SERCOM7">
            <register-group name="SERCOM7" name-in-module="SERCOM" address-space="base" offset="0x43000C00"/>
            <signals>
              <signal group="PAD" index="0" function="D" pad="PB21"/>
              <signal group="PAD" index="0" function="C" pad="PD08"/>
              <signal group="PAD" index="0" function="C" pad="PB30"/>
              <signal group="PAD" index="0" function="C" pad="PC12"/>
              <signal group="PAD" index="1" function="D" pad="PB20"/>
              <signal group="PAD" index="1" function="C" pad="PD09"/>
              <signal group="PAD" index="1" function="C" pad="PB31"/>
              <signal group="PAD" index="1" function="C" pad="PC13"/>
              <signal group="PAD" index="2" function="D" pad="PB18"/>
              <signal group="PAD" index="2" function="D" pad="PC10"/>
              <signal group="PAD" index="2" function="C" pad="PC14"/>
              <signal group="PAD" index="2" function="C" pad="PD10"/>
              <signal group="PAD" index="2" function="C" pad="PA30"/>
              <signal group="PAD" index="3" function="D" pad="PB19"/>
              <signal group="PAD" index="3" function="D" pad="PC11"/>
              <signal group="PAD" index="3" function="C" pad="PC15"/>
              <signal group="PAD" index="3" function="C" pad="PD11"/>
              <signal group="PAD" index="3" function="C" pad="PA31"/>
            </signals>
            <parameters>
              <param name="CLK_REDUCTION" value="1"/>
              <param name="DLY_COMPENSATION" value="1"/>
              <param name="DMA" value="1"/>
              <param name="DMAC_ID_RX" value="18"/>
              <param name="DMAC_ID_TX" value="19"/>
              <param name="FIFO_DEPTH_POWER" value="1"/>
              <param name="GCLK_ID_CORE" value="37"/>
              <param name="GCLK_ID_SLOW" value="3"/>
              <param name="INT_MSB" value="6"/>
              <param name="PMSB" value="3"/>
              <param name="RETENTION_SUPPORT" value="0"/>
              <param name="SE_CNT" value="1"/>
              <param name="SPI" value="1"/>
              <param name="SPI_HW_SS_CTRL" value="1"/>
              <param name="SPI_ICSPACE_EXT" value="1"/>
              <param name="SPI_OZMO" value="0"/>
              <param name="SPI_WAKE_ON_SSL" value="1"/>
              <param name="TTBIT_EXTENSION" value="1"/>
              <param name="TWIM" value="1"/>
              <param name="TWIS" value="1"/>
              <param name="TWIS_AUTO_ACK" value="1"/>
              <param name="TWIS_GROUP_CMD" value="1"/>
              <param name="TWIS_SDASETUP_CNT_SIZE" value="8"/>
              <param name="TWIS_SDASETUP_SIZE" value="4"/>
              <param name="TWIS_SUDAT" value="1"/>
              <param name="TWI_FASTMP" value="1"/>
              <param name="TWI_HSMODE" value="1"/>
              <param name="TWI_SCLSM_MODE" value="1"/>
              <param name="TWI_SMB_TIMEOUTS" value="1"/>
              <param name="TWI_TENBIT_ADR" value="1"/>
              <param name="USART" value="1"/>
              <param name="USART_AUTOBAUD" value="1"/>
              <param name="USART_COLDET" value="1"/>
              <param name="USART_FLOW_CTRL" value="1"/>
              <param name="USART_FRAC_BAUD" value="1"/>
              <param name="USART_IRDA" value="1"/>
              <param name="USART_ISO7816" value="1"/>
              <param name="USART_LIN_MASTER" value="1"/>
              <param name="USART_RS485" value="1"/>
              <param name="USART_SAMPA_EXT" value="1"/>
              <param name="USART_SAMPR_EXT" value="1"/>
              <param name="INSTANCE_ID" value="99"/>
            </parameters>
          </instance>
        </module>
        <module name="SUPC" id="U2407" version="1.0.0">
          <instance name="SUPC">
            <register-group name="SUPC" name-in-module="SUPC" address-space="base" offset="0x40001800"/>
            <signals>
              <signal group="OUT" index="0" function="SUPC" pad="PB01"/>
              <signal group="OUT" index="1" function="SUPC" pad="PB02"/>
              <signal group="VBAT" function="SUPC" pad="PB03"/>
            </signals>
            <parameters>
              <param name="BOD12_CALIB_MSB" value="5"/>
              <param name="BOD33_CALIB_MSB" value="5"/>
              <param name="INSTANCE_ID" value="6"/>
            </parameters>
          </instance>
        </module>
        <module name="TAL" id="U2253" version="2.0.0">
          <instance name="TAL">
            <register-group name="TAL" name-in-module="TAL" address-space="base" offset="0x4101E000"/>
            <signals>
              <signal group="BRK" function="H" pad="PA27"/>
              <signal group="BRK" function="H" pad="PB31"/>
            </signals>
            <parameters>
              <param name="CPU_NUM" value="2"/>
              <param name="CTI_NUM" value="4"/>
              <param name="DMA_CH_NUM" value="32"/>
              <param name="EV_CH_NUM" value="12"/>
              <param name="EXTINT_NUM" value="16"/>
              <param name="ID_IN_INTCPUSEL" value="1"/>
              <param name="ID_NUM" value="130"/>
              <param name="INT_GRP_NUM" value="5"/>
              <param name="INT_NUM" value="137"/>
              <param name="INT_NUM_BITS" value="8"/>
              <param name="IPS_GRP_NUM" value="2"/>
              <param name="IPS_NUM" value="64"/>
              <param name="IRQMON_NUM" value="1"/>
              <param name="INSTANCE_ID" value="47"/>
            </parameters>
          </instance>
        </module>
        <module name="TC" id="U2249" version="3.0.0">
          <instance name="TC0">
            <register-group name="TC0" name-in-module="TC" address-space="base" offset="0x40003800"/>
            <signals>
              <signal group="WO" index="0" function="E" pad="PA04"/>
              <signal group="WO" index="0" function="E" pad="PA08"/>
              <signal group="WO" index="0" function="E" pad="PB30"/>
              <signal group="WO" index="1" function="E" pad="PA05"/>
              <signal group="WO" index="1" function="E" pad="PA09"/>
              <signal group="WO" index="1" function="E" pad="PB31"/>
            </signals>
            <parameters>
              <param name="CC_NUM" value="2"/>
              <param name="DMAC_ID_OVF" value="44"/>
              <param name="EXT" value="0"/>
              <param name="GCLK_ID" value="9"/>
              <param name="MASTER_SLAVE_MODE" value="1"/>
              <param name="OW_NUM" value="2"/>
              <param name="INSTANCE_ID" value="14"/>
            </parameters>
          </instance>
          <instance name="TC1">
            <register-group name="TC1" name-in-module="TC" address-space="base" offset="0x40003C00"/>
            <signals>
              <signal group="WO" index="0" function="E" pad="PA06"/>
              <signal group="WO" index="0" function="E" pad="PA10"/>
              <signal group="WO" index="1" function="E" pad="PA07"/>
              <signal group="WO" index="1" function="E" pad="PA11"/>
            </signals>
            <parameters>
              <param name="CC_NUM" value="2"/>
              <param name="DMAC_ID_OVF" value="47"/>
              <param name="EXT" value="0"/>
              <param name="GCLK_ID" value="9"/>
              <param name="MASTER_SLAVE_MODE" value="2"/>
              <param name="OW_NUM" value="2"/>
              <param name="INSTANCE_ID" value="15"/>
            </parameters>
          </instance>
          <instance name="TC2">
            <register-group name="TC2" name-in-module="TC" address-space="base" offset="0x4101A000"/>
            <signals>
              <signal group="WO" index="0" function="E" pad="PA12"/>
              <signal group="WO" index="0" function="E" pad="PA16"/>
              <signal group="WO" index="0" function="E" pad="PA00"/>
              <signal group="WO" index="1" function="E" pad="PA01"/>
              <signal group="WO" index="1" function="E" pad="PA13"/>
              <signal group="WO" index="1" function="E" pad="PA17"/>
            </signals>
            <parameters>
              <param name="CC_NUM" value="2"/>
              <param name="DMAC_ID_OVF" value="50"/>
              <param name="EXT" value="0"/>
              <param name="GCLK_ID" value="26"/>
              <param name="MASTER_SLAVE_MODE" value="1"/>
              <param name="OW_NUM" value="2"/>
              <param name="INSTANCE_ID" value="45"/>
            </parameters>
          </instance>
          <instance name="TC3">
            <register-group name="TC3" name-in-module="TC" address-space="base" offset="0x4101C000"/>
            <signals>
              <signal group="WO" index="0" function="E" pad="PA18"/>
              <signal group="WO" index="0" function="E" pad="PA14"/>
              <signal group="WO" index="1" function="E" pad="PA15"/>
              <signal group="WO" index="1" function="E" pad="PA19"/>
            </signals>
            <parameters>
              <param name="CC_NUM" value="2"/>
              <param name="DMAC_ID_OVF" value="53"/>
              <param name="EXT" value="0"/>
              <param name="GCLK_ID" value="26"/>
              <param name="MASTER_SLAVE_MODE" value="2"/>
              <param name="OW_NUM" value="2"/>
              <param name="INSTANCE_ID" value="46"/>
            </parameters>
          </instance>
          <instance name="TC4">
            <register-group name="TC4" name-in-module="TC" address-space="base" offset="0x42001400"/>
            <signals>
              <signal group="WO" index="0" function="E" pad="PA22"/>
              <signal group="WO" index="0" function="E" pad="PB08"/>
              <signal group="WO" index="0" function="E" pad="PB12"/>
              <signal group="WO" index="1" function="E" pad="PA23"/>
              <signal group="WO" index="1" function="E" pad="PB09"/>
              <signal group="WO" index="1" function="E" pad="PB13"/>
            </signals>
            <parameters>
              <param name="CC_NUM" value="2"/>
              <param name="DMAC_ID_OVF" value="56"/>
              <param name="EXT" value="0"/>
              <param name="GCLK_ID" value="30"/>
              <param name="MASTER_SLAVE_MODE" value="1"/>
              <param name="OW_NUM" value="2"/>
              <param name="INSTANCE_ID" value="69"/>
            </parameters>
          </instance>
          <instance name="TC5">
            <register-group name="TC5" name-in-module="TC" address-space="base" offset="0x42001800"/>
            <signals>
              <signal group="WO" index="0" function="E" pad="PA24"/>
              <signal group="WO" index="0" function="E" pad="PB10"/>
              <signal group="WO" index="0" function="E" pad="PB14"/>
              <signal group="WO" index="1" function="E" pad="PA25"/>
              <signal group="WO" index="1" function="E" pad="PB11"/>
              <signal group="WO" index="1" function="E" pad="PB15"/>
            </signals>
            <parameters>
              <param name="CC_NUM" value="2"/>
              <param name="DMAC_ID_OVF" value="59"/>
              <param name="EXT" value="0"/>
              <param name="GCLK_ID" value="30"/>
              <param name="MASTER_SLAVE_MODE" value="2"/>
              <param name="OW_NUM" value="2"/>
              <param name="INSTANCE_ID" value="70"/>
            </parameters>
          </instance>
          <instance name="TC6">
            <register-group name="TC6" name-in-module="TC" address-space="base" offset="0x43001400"/>
            <signals>
              <signal group="WO" index="0" function="E" pad="PA30"/>
              <signal group="WO" index="0" function="E" pad="PB02"/>
              <signal group="WO" index="0" function="E" pad="PB16"/>
              <signal group="WO" index="1" function="E" pad="PA31"/>
              <signal group="WO" index="1" function="E" pad="PB03"/>
              <signal group="WO" index="1" function="E" pad="PB17"/>
            </signals>
            <parameters>
              <param name="CC_NUM" value="2"/>
              <param name="DMAC_ID_OVF" value="62"/>
              <param name="EXT" value="0"/>
              <param name="GCLK_ID" value="39"/>
              <param name="MASTER_SLAVE_MODE" value="1"/>
              <param name="OW_NUM" value="2"/>
              <param name="INSTANCE_ID" value="101"/>
            </parameters>
          </instance>
          <instance name="TC7">
            <register-group name="TC7" name-in-module="TC" address-space="base" offset="0x43001800"/>
            <signals>
              <signal group="WO" index="0" function="E" pad="PA20"/>
              <signal group="WO" index="0" function="E" pad="PB00"/>
              <signal group="WO" index="0" function="E" pad="PB22"/>
              <signal group="WO" index="1" function="E" pad="PA21"/>
              <signal group="WO" index="1" function="E" pad="PB01"/>
              <signal group="WO" index="1" function="E" pad="PB23"/>
            </signals>
            <parameters>
              <param name="CC_NUM" value="2"/>
              <param name="DMAC_ID_OVF" value="65"/>
              <param name="EXT" value="0"/>
              <param name="GCLK_ID" value="39"/>
              <param name="MASTER_SLAVE_MODE" value="2"/>
              <param name="OW_NUM" value="2"/>
              <param name="INSTANCE_ID" value="102"/>
            </parameters>
          </instance>
        </module>
        <module name="TCC" id="U2213" version="3.1.0">
          <instance name="TCC0">
            <register-group name="TCC0" name-in-module="TCC" address-space="base" offset="0x41016000"/>
            <signals>
              <signal group="WO" index="0" function="G" pad="PA20"/>
              <signal group="WO" index="0" function="G" pad="PB12"/>
              <signal group="WO" index="0" function="F" pad="PA08"/>
              <signal group="WO" index="0" function="F" pad="PC04"/>
              <signal group="WO" index="0" function="F" pad="PC10"/>
              <signal group="WO" index="0" function="F" pad="PC16"/>
              <signal group="WO" index="1" function="G" pad="PA21"/>
              <signal group="WO" index="1" function="G" pad="PB13"/>
              <signal group="WO" index="1" function="F" pad="PA09"/>
              <signal group="WO" index="1" function="F" pad="PC11"/>
              <signal group="WO" index="1" function="F" pad="PC17"/>
              <signal group="WO" index="1" function="F" pad="PD08"/>
              <signal group="WO" index="2" function="G" pad="PA22"/>
              <signal group="WO" index="2" function="G" pad="PB14"/>
              <signal group="WO" index="2" function="F" pad="PA10"/>
              <signal group="WO" index="2" function="F" pad="PC12"/>
              <signal group="WO" index="2" function="F" pad="PC18"/>
              <signal group="WO" index="2" function="F" pad="PD09"/>
              <signal group="WO" index="3" function="G" pad="PA23"/>
              <signal group="WO" index="3" function="G" pad="PB15"/>
              <signal group="WO" index="3" function="F" pad="PA11"/>
              <signal group="WO" index="3" function="F" pad="PC13"/>
              <signal group="WO" index="3" function="F" pad="PC19"/>
              <signal group="WO" index="3" function="F" pad="PD10"/>
              <signal group="WO" index="4" function="G" pad="PA16"/>
              <signal group="WO" index="4" function="G" pad="PB16"/>
              <signal group="WO" index="4" function="F" pad="PB10"/>
              <signal group="WO" index="4" function="F" pad="PC14"/>
              <signal group="WO" index="4" function="F" pad="PC20"/>
              <signal group="WO" index="4" function="F" pad="PD11"/>
              <signal group="WO" index="5" function="G" pad="PA17"/>
              <signal group="WO" index="5" function="G" pad="PB17"/>
              <signal group="WO" index="5" function="F" pad="PB11"/>
              <signal group="WO" index="5" function="F" pad="PC15"/>
              <signal group="WO" index="5" function="F" pad="PC21"/>
              <signal group="WO" index="5" function="F" pad="PD12"/>
              <signal group="WO" index="6" function="G" pad="PA18"/>
              <signal group="WO" index="6" function="G" pad="PB30"/>
              <signal group="WO" index="6" function="F" pad="PA12"/>
              <signal group="WO" index="6" function="F" pad="PC22"/>
              <signal group="WO" index="7" function="G" pad="PA19"/>
              <signal group="WO" index="7" function="G" pad="PB31"/>
              <signal group="WO" index="7" function="F" pad="PA13"/>
              <signal group="WO" index="7" function="F" pad="PC23"/>
            </signals>
            <parameters>
              <param name="CC_NUM" value="6"/>
              <param name="DITHERING" value="1"/>
              <param name="DMAC_ID_OVF" value="22"/>
              <param name="DTI" value="1"/>
              <param name="EXT" value="31"/>
              <param name="GCLK_ID" value="25"/>
              <param name="MASTER_SLAVE_MODE" value="1"/>
              <param name="OTMX" value="1"/>
              <param name="OW_NUM" value="8"/>
              <param name="PG" value="1"/>
              <param name="SIZE" value="24"/>
              <param name="SWAP" value="1"/>
              <param name="INSTANCE_ID" value="43"/>
            </parameters>
          </instance>
          <instance name="TCC1">
            <register-group name="TCC1" name-in-module="TCC" address-space="base" offset="0x41018000"/>
            <signals>
              <signal group="WO" index="0" function="G" pad="PB10"/>
              <signal group="WO" index="0" function="G" pad="PC14"/>
              <signal group="WO" index="0" function="F" pad="PA16"/>
              <signal group="WO" index="0" function="F" pad="PB18"/>
              <signal group="WO" index="0" function="F" pad="PD20"/>
              <signal group="WO" index="1" function="G" pad="PB11"/>
              <signal group="WO" index="1" function="G" pad="PC15"/>
              <signal group="WO" index="1" function="F" pad="PA17"/>
              <signal group="WO" index="1" function="F" pad="PB19"/>
              <signal group="WO" index="1" function="F" pad="PD21"/>
              <signal group="WO" index="2" function="G" pad="PA12"/>
              <signal group="WO" index="2" function="G" pad="PA14"/>
              <signal group="WO" index="2" function="F" pad="PA18"/>
              <signal group="WO" index="2" function="F" pad="PB20"/>
              <signal group="WO" index="2" function="F" pad="PB26"/>
              <signal group="WO" index="3" function="G" pad="PA13"/>
              <signal group="WO" index="3" function="G" pad="PA15"/>
              <signal group="WO" index="3" function="F" pad="PA19"/>
              <signal group="WO" index="3" function="F" pad="PB21"/>
              <signal group="WO" index="3" function="F" pad="PB27"/>
              <signal group="WO" index="4" function="G" pad="PA08"/>
              <signal group="WO" index="4" function="G" pad="PC10"/>
              <signal group="WO" index="4" function="F" pad="PA20"/>
              <signal group="WO" index="4" function="F" pad="PB28"/>
              <signal group="WO" index="5" function="G" pad="PA09"/>
              <signal group="WO" index="5" function="G" pad="PC11"/>
              <signal group="WO" index="5" function="F" pad="PA21"/>
              <signal group="WO" index="5" function="F" pad="PB29"/>
              <signal group="WO" index="6" function="G" pad="PA10"/>
              <signal group="WO" index="6" function="G" pad="PC12"/>
              <signal group="WO" index="6" function="F" pad="PA22"/>
              <signal group="WO" index="7" function="G" pad="PA11"/>
              <signal group="WO" index="7" function="G" pad="PC13"/>
              <signal group="WO" index="7" function="F" pad="PA23"/>
            </signals>
            <parameters>
              <param name="CC_NUM" value="4"/>
              <param name="DITHERING" value="1"/>
              <param name="DMAC_ID_OVF" value="29"/>
              <param name="DTI" value="1"/>
              <param name="EXT" value="31"/>
              <param name="GCLK_ID" value="25"/>
              <param name="MASTER_SLAVE_MODE" value="2"/>
              <param name="OTMX" value="1"/>
              <param name="OW_NUM" value="8"/>
              <param name="PG" value="1"/>
              <param name="SIZE" value="24"/>
              <param name="SWAP" value="1"/>
              <param name="INSTANCE_ID" value="44"/>
            </parameters>
          </instance>
          <instance name="TCC2">
            <register-group name="TCC2" name-in-module="TCC" address-space="base" offset="0x42000C00"/>
            <signals>
              <signal group="WO" index="0" function="F" pad="PA14"/>
              <signal group="WO" index="0" function="F" pad="PA30"/>
              <signal group="WO" index="1" function="F" pad="PA15"/>
              <signal group="WO" index="1" function="F" pad="PA31"/>
              <signal group="WO" index="2" function="F" pad="PA24"/>
              <signal group="WO" index="2" function="F" pad="PB02"/>
            </signals>
            <parameters>
              <param name="CC_NUM" value="3"/>
              <param name="DITHERING" value="0"/>
              <param name="DMAC_ID_OVF" value="34"/>
              <param name="DTI" value="0"/>
              <param name="EXT" value="1"/>
              <param name="GCLK_ID" value="29"/>
              <param name="MASTER_SLAVE_MODE" value="0"/>
              <param name="OTMX" value="1"/>
              <param name="OW_NUM" value="3"/>
              <param name="PG" value="0"/>
              <param name="SIZE" value="16"/>
              <param name="SWAP" value="0"/>
              <param name="INSTANCE_ID" value="67"/>
            </parameters>
          </instance>
          <instance name="TCC3">
            <register-group name="TCC3" name-in-module="TCC" address-space="base" offset="0x42001000"/>
            <signals>
              <signal group="WO" index="0" function="F" pad="PB12"/>
              <signal group="WO" index="0" function="F" pad="PB16"/>
              <signal group="WO" index="1" function="F" pad="PB13"/>
              <signal group="WO" index="1" function="F" pad="PB17"/>
            </signals>
            <parameters>
              <param name="CC_NUM" value="2"/>
              <param name="DITHERING" value="0"/>
              <param name="DMAC_ID_OVF" value="38"/>
              <param name="DTI" value="0"/>
              <param name="EXT" value="0"/>
              <param name="GCLK_ID" value="29"/>
              <param name="MASTER_SLAVE_MODE" value="0"/>
              <param name="OTMX" value="0"/>
              <param name="OW_NUM" value="2"/>
              <param name="PG" value="0"/>
              <param name="SIZE" value="16"/>
              <param name="SWAP" value="0"/>
              <param name="INSTANCE_ID" value="68"/>
            </parameters>
          </instance>
          <instance name="TCC4">
            <register-group name="TCC4" name-in-module="TCC" address-space="base" offset="0x43001000"/>
            <signals>
              <signal group="WO" index="0" function="F" pad="PB14"/>
              <signal group="WO" index="0" function="F" pad="PB30"/>
              <signal group="WO" index="1" function="F" pad="PB15"/>
              <signal group="WO" index="1" function="F" pad="PB31"/>
            </signals>
            <parameters>
              <param name="CC_NUM" value="2"/>
              <param name="DITHERING" value="0"/>
              <param name="DMAC_ID_OVF" value="41"/>
              <param name="DTI" value="0"/>
              <param name="EXT" value="0"/>
              <param name="GCLK_ID" value="38"/>
              <param name="MASTER_SLAVE_MODE" value="0"/>
              <param name="OTMX" value="0"/>
              <param name="OW_NUM" value="2"/>
              <param name="PG" value="0"/>
              <param name="SIZE" value="16"/>
              <param name="SWAP" value="0"/>
              <param name="INSTANCE_ID" value="100"/>
            </parameters>
          </instance>
        </module>
        <module name="TRNG" id="U2242" version="1.1.0">
          <instance name="TRNG">
            <register-group name="TRNG" name-in-module="TRNG" address-space="base" offset="0x42002800"/>
            <parameters>
              <param name="INSTANCE_ID" value="74"/>
            </parameters>
          </instance>
        </module>
        <module name="USB" id="U2222" version="1.2.0">
          <instance name="USB">
            <register-group name="USB" name-in-module="USB" address-space="base" offset="0x41000000"/>
            <signals>
              <signal group="DM" function="H" pad="PA24"/>
              <signal group="DP" function="H" pad="PA25"/>
              <signal group="SOF_1KHZ" function="H" pad="PA23"/>
              <signal group="SOF_1KHZ" function="H" pad="PB22"/>
            </signals>
            <parameters>
              <param name="AHB_2_USB_FIFO_DEPTH" value="4"/>
              <param name="AHB_2_USB_RD_DATA_BITS" value="8"/>
              <param name="AHB_2_USB_WR_DATA_BITS" value="32"/>
              <param name="AHB_2_USB_WR_THRESHOLD" value="2"/>
              <param name="DATA_BUS_16_8" value="0"/>
              <param name="EPNUM" value="8"/>
              <param name="EPT_NUM" value="8"/>
              <param name="GCLK_ID" value="10"/>
              <param name="INITIAL_CONTROL_QOS" value="3"/>
              <param name="INITIAL_DATA_QOS" value="3"/>
              <param name="MISSING_SOF_DET_IMPLEMENTED" value="1"/>
              <param name="PIPE_NUM" value="8"/>
              <param name="SYSTEM_CLOCK_IS_CKUSB" value="0"/>
              <param name="USB_2_AHB_FIFO_DEPTH" value="4"/>
              <param name="USB_2_AHB_RD_DATA_BITS" value="16"/>
              <param name="USB_2_AHB_RD_THRESHOLD" value="2"/>
              <param name="USB_2_AHB_WR_DATA_BITS" value="8"/>
              <param name="INSTANCE_ID" value="32"/>
            </parameters>
          </instance>
        </module>
        <module name="WDT" id="U2251" version="1.1.0">
          <instance name="WDT">
            <register-group name="WDT" name-in-module="WDT" address-space="base" offset="0x40002000"/>
            <parameters>
              <param name="INSTANCE_ID" value="8"/>
            </parameters>
          </instance>
        </module>
      <module name="SystemControl">
            <instance name="SystemControl">
                <register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
            </instance>
        </module><module name="SysTick">
            <instance name="SysTick">
                <register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
            </instance>
        </module><module name="NVIC">
            <instance name="NVIC">
                <register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
            </instance>
        </module><module name="MPU">
            <instance name="MPU">
                <register-group address-space="base" offset="0xE000ED90" name-in-module="MPU" name="MPU"/>
            </instance>
        </module></peripherals>
      <interrupts>
        <interrupt name="NonMaskableInt" index="-14" caption="Non Maskable Interrupt"/>
        <interrupt name="HardFault" index="-13" caption="Cortex-M4 Hard Fault Interrupt"/>
        <interrupt name="MemoryManagement" index="-12" caption="Cortex-M4 Memory Management Interrupt"/>
        <interrupt name="BusFault" index="-11" caption="Cortex-M4 Bus Fault Interrupt"/>
        <interrupt name="UsageFault" index="-10" caption="Cortex-M4 Usage Fault Interrupt"/>
        <interrupt name="SVCall" index="-5" caption="Cortex-M4 SV Call Interrupt"/>
        <interrupt name="DebugMonitor" index="-4" caption="Cortex-M4 Debug Monitor Interrupt"/>
        <interrupt name="PendSV" index="-2" caption="Cortex-M4 Pend SV Interrupt"/>
        <interrupt name="SysTick" index="-1" caption="Cortex-M4 System Tick Interrupt"/>
        <interrupt name="PM" index="0" module-instance="PM"/>
        <interrupt name="MCLK" index="1" module-instance="MCLK"/>
        <interrupt name="OSCCTRL_XOSC0" index="2" module-instance="OSCCTRL"/>
        <interrupt name="OSCCTRL_XOSC1" index="3" module-instance="OSCCTRL"/>
        <interrupt name="OSCCTRL_DFLL" index="4" module-instance="OSCCTRL"/>
        <interrupt name="OSCCTRL_DPLL0" index="5" module-instance="OSCCTRL"/>
        <interrupt name="OSCCTRL_DPLL1" index="6" module-instance="OSCCTRL"/>
        <interrupt name="OSC32KCTRL" index="7" module-instance="OSC32KCTRL"/>
        <interrupt name="SUPC_OTHER" index="8" module-instance="SUPC"/>
        <interrupt name="SUPC_BODDET" index="9" module-instance="SUPC"/>
        <interrupt name="WDT" index="10" module-instance="WDT"/>
        <interrupt name="RTC" index="11" module-instance="RTC"/>
        <interrupt name="EIC_EXTINT_0" index="12" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_1" index="13" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_2" index="14" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_3" index="15" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_4" index="16" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_5" index="17" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_6" index="18" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_7" index="19" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_8" index="20" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_9" index="21" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_10" index="22" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_11" index="23" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_12" index="24" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_13" index="25" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_14" index="26" module-instance="EIC"/>
        <interrupt name="EIC_EXTINT_15" index="27" module-instance="EIC"/>
        <interrupt name="FREQM" index="28" module-instance="FREQM"/>
        <interrupt name="NVMCTRL_0" index="29" module-instance="NVMCTRL"/>
        <interrupt name="NVMCTRL_1" index="30" module-instance="NVMCTRL"/>
        <interrupt name="DMAC_0" index="31" module-instance="DMAC"/>
        <interrupt name="DMAC_1" index="32" module-instance="DMAC"/>
        <interrupt name="DMAC_2" index="33" module-instance="DMAC"/>
        <interrupt name="DMAC_3" index="34" module-instance="DMAC"/>
        <interrupt name="DMAC_OTHER" index="35" module-instance="DMAC"/>
        <interrupt name="EVSYS_0" index="36" module-instance="EVSYS"/>
        <interrupt name="EVSYS_1" index="37" module-instance="EVSYS"/>
        <interrupt name="EVSYS_2" index="38" module-instance="EVSYS"/>
        <interrupt name="EVSYS_3" index="39" module-instance="EVSYS"/>
        <interrupt name="EVSYS_OTHER" index="40" module-instance="EVSYS"/>
        <interrupt name="PAC" index="41" module-instance="PAC"/>
        <interrupt name="TAL_BRK" index="42" module-instance="TAL"/>
        <interrupt name="TAL_IPS" index="43" module-instance="TAL"/>
        <interrupt name="RAMECC" index="45" module-instance="RAMECC"/>
        <interrupt name="SERCOM0_0" index="46" module-instance="SERCOM0"/>
        <interrupt name="SERCOM0_1" index="47" module-instance="SERCOM0"/>
        <interrupt name="SERCOM0_2" index="48" module-instance="SERCOM0"/>
        <interrupt name="SERCOM0_OTHER" index="49" module-instance="SERCOM0"/>
        <interrupt name="SERCOM1_0" index="50" module-instance="SERCOM1"/>
        <interrupt name="SERCOM1_1" index="51" module-instance="SERCOM1"/>
        <interrupt name="SERCOM1_2" index="52" module-instance="SERCOM1"/>
        <interrupt name="SERCOM1_OTHER" index="53" module-instance="SERCOM1"/>
        <interrupt name="SERCOM2_0" index="54" module-instance="SERCOM2"/>
        <interrupt name="SERCOM2_1" index="55" module-instance="SERCOM2"/>
        <interrupt name="SERCOM2_2" index="56" module-instance="SERCOM2"/>
        <interrupt name="SERCOM2_OTHER" index="57" module-instance="SERCOM2"/>
        <interrupt name="SERCOM3_0" index="58" module-instance="SERCOM3"/>
        <interrupt name="SERCOM3_1" index="59" module-instance="SERCOM3"/>
        <interrupt name="SERCOM3_2" index="60" module-instance="SERCOM3"/>
        <interrupt name="SERCOM3_OTHER" index="61" module-instance="SERCOM3"/>
        <interrupt name="SERCOM4_0" index="62" module-instance="SERCOM4"/>
        <interrupt name="SERCOM4_1" index="63" module-instance="SERCOM4"/>
        <interrupt name="SERCOM4_2" index="64" module-instance="SERCOM4"/>
        <interrupt name="SERCOM4_OTHER" index="65" module-instance="SERCOM4"/>
        <interrupt name="SERCOM5_0" index="66" module-instance="SERCOM5"/>
        <interrupt name="SERCOM5_1" index="67" module-instance="SERCOM5"/>
        <interrupt name="SERCOM5_2" index="68" module-instance="SERCOM5"/>
        <interrupt name="SERCOM5_OTHER" index="69" module-instance="SERCOM5"/>
        <interrupt name="SERCOM6_0" index="70" module-instance="SERCOM6"/>
        <interrupt name="SERCOM6_1" index="71" module-instance="SERCOM6"/>
        <interrupt name="SERCOM6_2" index="72" module-instance="SERCOM6"/>
        <interrupt name="SERCOM6_OTHER" index="73" module-instance="SERCOM6"/>
        <interrupt name="SERCOM7_0" index="74" module-instance="SERCOM7"/>
        <interrupt name="SERCOM7_1" index="75" module-instance="SERCOM7"/>
        <interrupt name="SERCOM7_2" index="76" module-instance="SERCOM7"/>
        <interrupt name="SERCOM7_OTHER" index="77" module-instance="SERCOM7"/>
        <interrupt name="USB_OTHER" index="80" module-instance="USB"/>
        <interrupt name="USB_SOF_HSOF" index="81" module-instance="USB"/>
        <interrupt name="USB_TRCPT0" index="82" module-instance="USB"/>
        <interrupt name="USB_TRCPT1" index="83" module-instance="USB"/>
        <interrupt name="TCC0_OTHER" index="85" module-instance="TCC0"/>
        <interrupt name="TCC0_MC0" index="86" module-instance="TCC0"/>
        <interrupt name="TCC0_MC1" index="87" module-instance="TCC0"/>
        <interrupt name="TCC0_MC2" index="88" module-instance="TCC0"/>
        <interrupt name="TCC0_MC3" index="89" module-instance="TCC0"/>
        <interrupt name="TCC0_MC4" index="90" module-instance="TCC0"/>
        <interrupt name="TCC0_MC5" index="91" module-instance="TCC0"/>
        <interrupt name="TCC1_OTHER" index="92" module-instance="TCC1"/>
        <interrupt name="TCC1_MC0" index="93" module-instance="TCC1"/>
        <interrupt name="TCC1_MC1" index="94" module-instance="TCC1"/>
        <interrupt name="TCC1_MC2" index="95" module-instance="TCC1"/>
        <interrupt name="TCC1_MC3" index="96" module-instance="TCC1"/>
        <interrupt name="TCC2_OTHER" index="97" module-instance="TCC2"/>
        <interrupt name="TCC2_MC0" index="98" module-instance="TCC2"/>
        <interrupt name="TCC2_MC1" index="99" module-instance="TCC2"/>
        <interrupt name="TCC2_MC2" index="100" module-instance="TCC2"/>
        <interrupt name="TCC3_OTHER" index="101" module-instance="TCC3"/>
        <interrupt name="TCC3_MC0" index="102" module-instance="TCC3"/>
        <interrupt name="TCC3_MC1" index="103" module-instance="TCC3"/>
        <interrupt name="TCC4_OTHER" index="104" module-instance="TCC4"/>
        <interrupt name="TCC4_MC0" index="105" module-instance="TCC4"/>
        <interrupt name="TCC4_MC1" index="106" module-instance="TCC4"/>
        <interrupt name="TC0" index="107" module-instance="TC0"/>
        <interrupt name="TC1" index="108" module-instance="TC1"/>
        <interrupt name="TC2" index="109" module-instance="TC2"/>
        <interrupt name="TC3" index="110" module-instance="TC3"/>
        <interrupt name="TC4" index="111" module-instance="TC4"/>
        <interrupt name="TC5" index="112" module-instance="TC5"/>
        <interrupt name="TC6" index="113" module-instance="TC6"/>
        <interrupt name="TC7" index="114" module-instance="TC7"/>
        <interrupt name="PDEC_OTHER" index="115" module-instance="PDEC"/>
        <interrupt name="PDEC_MC0" index="116" module-instance="PDEC"/>
        <interrupt name="PDEC_MC1" index="117" module-instance="PDEC"/>
        <interrupt name="ADC0_OTHER" index="118" module-instance="ADC0"/>
        <interrupt name="ADC0_RESRDY" index="119" module-instance="ADC0"/>
        <interrupt name="ADC1_OTHER" index="120" module-instance="ADC1"/>
        <interrupt name="ADC1_RESRDY" index="121" module-instance="ADC1"/>
        <interrupt name="AC" index="122" module-instance="AC"/>
        <interrupt name="DAC_OTHER" index="123" module-instance="DAC"/>
        <interrupt name="DAC_EMPTY_0" index="124" module-instance="DAC"/>
        <interrupt name="DAC_EMPTY_1" index="125" module-instance="DAC"/>
        <interrupt name="DAC_RESRDY_0" index="126" module-instance="DAC"/>
        <interrupt name="DAC_RESRDY_1" index="127" module-instance="DAC"/>
        <interrupt name="I2S" index="128" module-instance="I2S"/>
        <interrupt name="PCC" index="129" module-instance="PCC"/>
        <interrupt name="AES" index="130" module-instance="AES"/>
        <interrupt name="TRNG" index="131" module-instance="TRNG"/>
        <interrupt name="ICM" index="132" module-instance="ICM"/>
        <interrupt name="PUKCC" index="133" module-instance="PUKCC"/>
        <interrupt name="QSPI" index="134" module-instance="QSPI"/>
        <interrupt name="SDHC0" index="135" module-instance="SDHC0"/>
        <interrupt name="SDHC1" index="136" module-instance="SDHC1"/>
      </interrupts>
      <interfaces>
        <interface name="SWD" type="swd"/>
      </interfaces>
      <property-groups>
        <property-group name="SIGNATURES">
          <property name="DSU_DID" value="0x60060001"/>
        </property-group>
      </property-groups>
    </device>
  </devices>
  <modules>
    <module name="AC" id="U2501" version="1.0.0" caption="Analog Comparators">
      <register-group name="AC" caption="Analog Comparators">
        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
        </register>
        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B">
          <bitfield name="START0" caption="Comparator 0 Start Comparison" mask="0x1"/>
          <bitfield name="START1" caption="Comparator 1 Start Comparison" mask="0x2"/>
        </register>
        <register name="EVCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Event Control">
          <bitfield name="COMPEO0" caption="Comparator 0 Event Output Enable" mask="0x1"/>
          <bitfield name="COMPEO1" caption="Comparator 1 Event Output Enable" mask="0x2"/>
          <bitfield name="WINEO0" caption="Window 0 Event Output Enable" mask="0x10"/>
          <bitfield name="COMPEI0" caption="Comparator 0 Event Input Enable" mask="0x100"/>
          <bitfield name="COMPEI1" caption="Comparator 1 Event Input Enable" mask="0x200"/>
          <bitfield name="INVEI0" caption="Comparator 0 Input Event Invert Enable" mask="0x1000"/>
          <bitfield name="INVEI1" caption="Comparator 1 Input Event Invert Enable" mask="0x2000"/>
        </register>
        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
        </register>
        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
          <bitfield name="COMP0" caption="Comparator 0 Interrupt Enable" mask="0x1"/>
          <bitfield name="COMP1" caption="Comparator 1 Interrupt Enable" mask="0x2"/>
          <bitfield name="WIN0" caption="Window 0 Interrupt Enable" mask="0x10"/>
        </register>
        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
          <bitfield name="COMP0" caption="Comparator 0" mask="0x1"/>
          <bitfield name="COMP1" caption="Comparator 1" mask="0x2"/>
          <bitfield name="WIN0" caption="Window 0" mask="0x10"/>
        </register>
        <register name="STATUSA" offset="0x7" rw="R" size="1" initval="0x00" caption="Status A">
          <bitfield name="STATE0" caption="Comparator 0 Current State" mask="0x1"/>
          <bitfield name="STATE1" caption="Comparator 1 Current State" mask="0x2"/>
          <bitfield name="WSTATE0" caption="Window 0 Current State" mask="0x30" values="AC_STATUSA__WSTATE0"/>
        </register>
        <register name="STATUSB" offset="0x8" rw="R" size="1" initval="0x00" caption="Status B">
          <bitfield name="READY0" caption="Comparator 0 Ready" mask="0x1"/>
          <bitfield name="READY1" caption="Comparator 1 Ready" mask="0x2"/>
        </register>
        <register name="DBGCTRL" offset="0x9" rw="RW" size="1" initval="0x00" caption="Debug Control">
          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
        </register>
        <register name="WINCTRL" offset="0xA" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Window Control">
          <bitfield name="WEN0" caption="Window 0 Mode Enable" mask="0x1"/>
          <bitfield name="WINTSEL0" caption="Window 0 Interrupt Selection" mask="0x6" values="AC_WINCTRL__WINTSEL0"/>
        </register>
        <register name="SCALER" offset="0xC" rw="RW" size="1" count="2" initval="0x00" caption="Scaler n">
          <bitfield name="VALUE" caption="Scaler Value" mask="0x3F"/>
        </register>
        <register name="COMPCTRL" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Comparator Control n">
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="SINGLE" caption="Single-Shot Mode" mask="0x4"/>
          <bitfield name="INTSEL" caption="Interrupt Selection" mask="0x18" values="AC_COMPCTRL__INTSEL"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
          <bitfield name="MUXNEG" caption="Negative Input Mux Selection" mask="0x700" values="AC_COMPCTRL__MUXNEG"/>
          <bitfield name="MUXPOS" caption="Positive Input Mux Selection" mask="0x7000" values="AC_COMPCTRL__MUXPOS"/>
          <bitfield name="SWAP" caption="Swap Inputs and Invert" mask="0x8000"/>
          <bitfield name="SPEED" caption="Speed Selection" mask="0x30000" values="AC_COMPCTRL__SPEED"/>
          <bitfield name="HYSTEN" caption="Hysteresis Enable" mask="0x80000"/>
          <bitfield name="HYST" caption="Hysteresis Level" mask="0x300000" values="AC_COMPCTRL__HYST"/>
          <bitfield name="FLEN" caption="Filter Length" mask="0x7000000" values="AC_COMPCTRL__FLEN"/>
          <bitfield name="OUT" caption="Output" mask="0x30000000" values="AC_COMPCTRL__OUT"/>
        </register>
        <register name="SYNCBUSY" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
          <bitfield name="WINCTRL" caption="WINCTRL Synchronization Busy" mask="0x4"/>
          <bitfield name="COMPCTRL0" caption="COMPCTRL 0 Synchronization Busy" mask="0x8"/>
          <bitfield name="COMPCTRL1" caption="COMPCTRL 1 Synchronization Busy" mask="0x10"/>
        </register>
        <register name="CALIB" offset="0x24" rw="RW" size="2" initval="0x0101" caption="Calibration">
          <bitfield name="BIAS0" caption="COMP0/1 Bias Scaling" mask="0x3"/>
        </register>
      </register-group>
      <value-group name="AC_STATUSA__WSTATE0">
        <value name="ABOVE" caption="Signal is above window" value="0"/>
        <value name="INSIDE" caption="Signal is inside window" value="1"/>
        <value name="BELOW" caption="Signal is below window" value="2"/>
      </value-group>
      <value-group name="AC_STATUSA__WSTATE1">
        <value name="ABOVE" caption="Signal is above window" value="0"/>
        <value name="INSIDE" caption="Signal is inside window" value="1"/>
        <value name="BELOW" caption="Signal is below window" value="2"/>
      </value-group>
      <value-group name="AC_WINCTRL__WINTSEL0">
        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
      </value-group>
      <value-group name="AC_WINCTRL__WINTSEL1">
        <value name="ABOVE" caption="Interrupt on signal above window" value="0"/>
        <value name="INSIDE" caption="Interrupt on signal inside window" value="1"/>
        <value name="BELOW" caption="Interrupt on signal below window" value="2"/>
        <value name="OUTSIDE" caption="Interrupt on signal outside window" value="3"/>
      </value-group>
      <value-group name="AC_COMPCTRL__FLEN">
        <value name="OFF" caption="No filtering" value="0"/>
        <value name="MAJ3" caption="3-bit majority function (2 of 3)" value="1"/>
        <value name="MAJ5" caption="5-bit majority function (3 of 5)" value="2"/>
      </value-group>
      <value-group name="AC_COMPCTRL__HYST">
        <value name="HYST50" caption="50mV" value="0"/>
        <value name="HYST100" caption="100mV" value="1"/>
        <value name="HYST150" caption="150mV" value="2"/>
      </value-group>
      <value-group name="AC_COMPCTRL__INTSEL">
        <value name="TOGGLE" caption="Interrupt on comparator output toggle" value="0"/>
        <value name="RISING" caption="Interrupt on comparator output rising" value="1"/>
        <value name="FALLING" caption="Interrupt on comparator output falling" value="2"/>
        <value name="EOC" caption="Interrupt on end of comparison (single-shot mode only)" value="3"/>
      </value-group>
      <value-group name="AC_COMPCTRL__MUXNEG">
        <value name="PIN0" caption="I/O pin 0" value="0"/>
        <value name="PIN1" caption="I/O pin 1" value="1"/>
        <value name="PIN2" caption="I/O pin 2" value="2"/>
        <value name="PIN3" caption="I/O pin 3" value="3"/>
        <value name="GND" caption="Ground" value="4"/>
        <value name="VSCALE" caption="VDD scaler" value="5"/>
        <value name="BANDGAP" caption="Internal bandgap voltage" value="6"/>
        <value name="DAC" caption="DAC output" value="7"/>
      </value-group>
      <value-group name="AC_COMPCTRL__MUXPOS">
        <value name="PIN0" caption="I/O pin 0" value="0"/>
        <value name="PIN1" caption="I/O pin 1" value="1"/>
        <value name="PIN2" caption="I/O pin 2" value="2"/>
        <value name="PIN3" caption="I/O pin 3" value="3"/>
        <value name="VSCALE" caption="VDD Scaler" value="4"/>
      </value-group>
      <value-group name="AC_COMPCTRL__OUT">
        <value name="OFF" caption="The output of COMPn is not routed to the COMPn I/O port" value="0"/>
        <value name="ASYNC" caption="The asynchronous output of COMPn is routed to the COMPn I/O port" value="1"/>
        <value name="SYNC" caption="The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" value="2"/>
      </value-group>
      <value-group name="AC_COMPCTRL__SPEED">
        <value name="HIGH" caption="High speed" value="3"/>
      </value-group>
    </module>
    <module name="ADC" id="U2500" version="1.0.0" caption="Analog Digital Converter">
      <register-group name="ADC" caption="Analog Digital Converter">
        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="DUALSEL" caption="Dual Mode Trigger Selection" mask="0x18" values="ADC_CTRLA__DUALSEL"/>
          <bitfield name="SLAVEEN" caption="Slave Enable" mask="0x20"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
          <bitfield name="PRESCALER" caption="Prescaler Configuration" mask="0x700" values="ADC_CTRLA__PRESCALER"/>
          <bitfield name="R2R" caption="Rail to Rail Operation Enable" mask="0x8000"/>
        </register>
        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
          <bitfield name="FLUSHEI" caption="Flush Event Input Enable" mask="0x1"/>
          <bitfield name="STARTEI" caption="Start Conversion Event Input Enable" mask="0x2"/>
          <bitfield name="FLUSHINV" caption="Flush Event Invert Enable" mask="0x4"/>
          <bitfield name="STARTINV" caption="Start Conversion Event Invert Enable" mask="0x8"/>
          <bitfield name="RESRDYEO" caption="Result Ready Event Out" mask="0x10"/>
          <bitfield name="WINMONEO" caption="Window Monitor Event Out" mask="0x20"/>
        </register>
        <register name="DBGCTRL" offset="0x3" rw="RW" size="1" initval="0x00" caption="Debug Control">
          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
        </register>
        <register name="INPUTCTRL" offset="0x4" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Input Control">
          <bitfield name="MUXPOS" caption="Positive Mux Input Selection" mask="0x1F" values="ADC_INPUTCTRL__MUXPOS"/>
          <bitfield name="DIFFMODE" caption="Differential Mode" mask="0x80"/>
          <bitfield name="MUXNEG" caption="Negative Mux Input Selection" mask="0x1F00" values="ADC_INPUTCTRL__MUXNEG"/>
          <bitfield name="DSEQSTOP" caption="Stop DMA Sequencing" mask="0x8000"/>
        </register>
        <register name="CTRLB" offset="0x6" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Control B">
          <bitfield name="LEFTADJ" caption="Left-Adjusted Result" mask="0x1"/>
          <bitfield name="FREERUN" caption="Free Running Mode" mask="0x2"/>
          <bitfield name="CORREN" caption="Digital Correction Logic Enable" mask="0x4"/>
          <bitfield name="RESSEL" caption="Conversion Result Resolution" mask="0x18" values="ADC_CTRLB__RESSEL"/>
          <bitfield name="WINMODE" caption="Window Monitor Mode" mask="0x700" values="ADC_CTRLB__WINMODE"/>
          <bitfield name="WINSS" caption="Window Single Sample" mask="0x800"/>
        </register>
        <register name="REFCTRL" offset="0x8" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Reference Control">
          <bitfield name="REFSEL" caption="Reference Selection" mask="0xF" values="ADC_REFCTRL__REFSEL"/>
          <bitfield name="REFCOMP" caption="Reference Buffer Offset Compensation Enable" mask="0x80"/>
        </register>
        <register name="AVGCTRL" offset="0xA" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Average Control">
          <bitfield name="SAMPLENUM" caption="Number of Samples to be Collected" mask="0xF" values="ADC_AVGCTRL__SAMPLENUM"/>
          <bitfield name="ADJRES" caption="Adjusting Result / Division Coefficient" mask="0x70"/>
        </register>
        <register name="SAMPCTRL" offset="0xB" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Sample Time Control">
          <bitfield name="SAMPLEN" caption="Sampling Time Length" mask="0x3F"/>
          <bitfield name="OFFCOMP" caption="Comparator Offset Compensation Enable" mask="0x80"/>
        </register>
        <register name="WINLT" offset="0xC" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Lower Threshold">
          <bitfield name="WINLT" caption="Window Lower Threshold" mask="0xFFFF"/>
        </register>
        <register name="WINUT" offset="0xE" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Window Monitor Upper Threshold">
          <bitfield name="WINUT" caption="Window Upper Threshold" mask="0xFFFF"/>
        </register>
        <register name="GAINCORR" offset="0x10" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Gain Correction">
          <bitfield name="GAINCORR" caption="Gain Correction Value" mask="0xFFF"/>
        </register>
        <register name="OFFSETCORR" offset="0x12" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Offset Correction">
          <bitfield name="OFFSETCORR" caption="Offset Correction Value" mask="0xFFF"/>
        </register>
        <register name="SWTRIG" offset="0x14" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Software Trigger">
          <bitfield name="FLUSH" caption="ADC Conversion Flush" mask="0x1"/>
          <bitfield name="START" caption="Start ADC Conversion" mask="0x2"/>
        </register>
        <register name="INTENCLR" offset="0x2C" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
          <bitfield name="RESRDY" caption="Result Ready Interrupt Disable" mask="0x1"/>
          <bitfield name="OVERRUN" caption="Overrun Interrupt Disable" mask="0x2"/>
          <bitfield name="WINMON" caption="Window Monitor Interrupt Disable" mask="0x4"/>
        </register>
        <register name="INTENSET" offset="0x2D" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
          <bitfield name="RESRDY" caption="Result Ready Interrupt Enable" mask="0x1"/>
          <bitfield name="OVERRUN" caption="Overrun Interrupt Enable" mask="0x2"/>
          <bitfield name="WINMON" caption="Window Monitor Interrupt Enable" mask="0x4"/>
        </register>
        <register name="INTFLAG" offset="0x2E" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
          <bitfield name="RESRDY" caption="Result Ready Interrupt Flag" mask="0x1"/>
          <bitfield name="OVERRUN" caption="Overrun Interrupt Flag" mask="0x2"/>
          <bitfield name="WINMON" caption="Window Monitor Interrupt Flag" mask="0x4"/>
        </register>
        <register name="STATUS" offset="0x2F" rw="R" size="1" initval="0x00" caption="Status">
          <bitfield name="ADCBUSY" caption="ADC Busy Status" mask="0x1"/>
          <bitfield name="WCC" caption="Window Comparator Counter" mask="0xFC"/>
        </register>
        <register name="SYNCBUSY" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
          <bitfield name="SWRST" caption="SWRST Synchronization Busy" mask="0x1"/>
          <bitfield name="ENABLE" caption="ENABLE Synchronization Busy" mask="0x2"/>
          <bitfield name="INPUTCTRL" caption="Input Control Synchronization Busy" mask="0x4"/>
          <bitfield name="CTRLB" caption="Control B Synchronization Busy" mask="0x8"/>
          <bitfield name="REFCTRL" caption="Reference Control Synchronization Busy" mask="0x10"/>
          <bitfield name="AVGCTRL" caption="Average Control Synchronization Busy" mask="0x20"/>
          <bitfield name="SAMPCTRL" caption="Sampling Time Control Synchronization Busy" mask="0x40"/>
          <bitfield name="WINLT" caption="Window Monitor Lower Threshold Synchronization Busy" mask="0x80"/>
          <bitfield name="WINUT" caption="Window Monitor Upper Threshold Synchronization Busy" mask="0x100"/>
          <bitfield name="GAINCORR" caption="Gain Correction Synchronization Busy" mask="0x200"/>
          <bitfield name="OFFSETCORR" caption="Offset Correction Synchronization Busy" mask="0x400"/>
          <bitfield name="SWTRIG" caption="Software Trigger Synchronization Busy" mask="0x800"/>
        </register>
        <register name="DSEQDATA" offset="0x34" rw="W" size="4" initval="0x00000000" caption="DMA Sequencial Data">
          <bitfield name="DATA" caption="DMA Sequential Data" mask="0xFFFFFFFF"/>
        </register>
        <register name="DSEQCTRL" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="DMA Sequential Control">
          <bitfield name="INPUTCTRL" caption="Input Control" mask="0x1"/>
          <bitfield name="CTRLB" caption="Control B" mask="0x2"/>
          <bitfield name="REFCTRL" caption="Reference Control" mask="0x4"/>
          <bitfield name="AVGCTRL" caption="Average Control" mask="0x8"/>
          <bitfield name="SAMPCTRL" caption="Sampling Time Control" mask="0x10"/>
          <bitfield name="WINLT" caption="Window Monitor Lower Threshold" mask="0x20"/>
          <bitfield name="WINUT" caption="Window Monitor Upper Threshold" mask="0x40"/>
          <bitfield name="GAINCORR" caption="Gain Correction" mask="0x80"/>
          <bitfield name="OFFSETCORR" caption="Offset Correction" mask="0x100"/>
          <bitfield name="AUTOSTART" caption="ADC Auto-Start Conversion" mask="0x80000000"/>
        </register>
        <register name="DSEQSTAT" offset="0x3C" rw="R" size="4" initval="0x00000000" caption="DMA Sequencial Status">
          <bitfield name="INPUTCTRL" caption="Input Control" mask="0x1"/>
          <bitfield name="CTRLB" caption="Control B" mask="0x2"/>
          <bitfield name="REFCTRL" caption="Reference Control" mask="0x4"/>
          <bitfield name="AVGCTRL" caption="Average Control" mask="0x8"/>
          <bitfield name="SAMPCTRL" caption="Sampling Time Control" mask="0x10"/>
          <bitfield name="WINLT" caption="Window Monitor Lower Threshold" mask="0x20"/>
          <bitfield name="WINUT" caption="Window Monitor Upper Threshold" mask="0x40"/>
          <bitfield name="GAINCORR" caption="Gain Correction" mask="0x80"/>
          <bitfield name="OFFSETCORR" caption="Offset Correction" mask="0x100"/>
          <bitfield name="BUSY" caption="DMA Sequencing Busy" mask="0x80000000"/>
        </register>
        <register name="RESULT" offset="0x40" rw="R" size="2" initval="0x0000" caption="Result Conversion Value">
          <bitfield name="RESULT" caption="Result Conversion Value" mask="0xFFFF"/>
        </register>
        <register name="RESS" offset="0x44" rw="R" size="2" initval="0x0000" caption="Last Sample Result">
          <bitfield name="RESS" caption="Last ADC conversion result" mask="0xFFFF"/>
        </register>
        <register name="CALIB" offset="0x48" rw="RW" size="2" initval="0x0000" caption="Calibration">
          <bitfield name="BIASCOMP" caption="Bias Comparator Scaling" mask="0x7"/>
          <bitfield name="BIASR2R" caption="Bias R2R Ampli scaling" mask="0x70"/>
          <bitfield name="BIASREFBUF" caption="Bias  Reference Buffer Scaling" mask="0x700"/>
        </register>
      </register-group>
      <value-group name="ADC_CTRLA__DUALSEL">
        <value name="BOTH" caption="Start event or software trigger will start a conversion on both ADCs" value="0"/>
        <value name="INTERLEAVE" caption="START event or software trigger will alternatingly start a conversion on ADC0 and ADC1" value="1"/>
      </value-group>
      <value-group name="ADC_CTRLA__PRESCALER">
        <value name="DIV2" caption="Peripheral clock divided by 2" value="0"/>
        <value name="DIV4" caption="Peripheral clock divided by 4" value="1"/>
        <value name="DIV8" caption="Peripheral clock divided by 8" value="2"/>
        <value name="DIV16" caption="Peripheral clock divided by 16" value="3"/>
        <value name="DIV32" caption="Peripheral clock divided by 32" value="4"/>
        <value name="DIV64" caption="Peripheral clock divided by 64" value="5"/>
        <value name="DIV128" caption="Peripheral clock divided by 128" value="6"/>
        <value name="DIV256" caption="Peripheral clock divided by 256" value="7"/>
      </value-group>
      <value-group name="ADC_INPUTCTRL__MUXNEG">
        <value name="AIN0" caption="ADC AIN0 Pin" value="0x0"/>
        <value name="AIN1" caption="ADC AIN1 Pin" value="0x1"/>
        <value name="AIN2" caption="ADC AIN2 Pin" value="0x2"/>
        <value name="AIN3" caption="ADC AIN3 Pin" value="0x3"/>
        <value name="AIN4" caption="ADC AIN4 Pin" value="0x4"/>
        <value name="AIN5" caption="ADC AIN5 Pin" value="0x5"/>
        <value name="AIN6" caption="ADC AIN6 Pin" value="0x6"/>
        <value name="AIN7" caption="ADC AIN7 Pin" value="0x7"/>
        <value name="GND" caption="Internal Ground" value="0x18"/>
      </value-group>
      <value-group name="ADC_INPUTCTRL__MUXPOS">
        <value name="AIN0" caption="ADC AIN0 Pin" value="0x0"/>
        <value name="AIN1" caption="ADC AIN1 Pin" value="0x1"/>
        <value name="AIN2" caption="ADC AIN2 Pin" value="0x2"/>
        <value name="AIN3" caption="ADC AIN3 Pin" value="0x3"/>
        <value name="AIN4" caption="ADC AIN4 Pin" value="0x4"/>
        <value name="AIN5" caption="ADC AIN5 Pin" value="0x5"/>
        <value name="AIN6" caption="ADC AIN6 Pin" value="0x6"/>
        <value name="AIN7" caption="ADC AIN7 Pin" value="0x7"/>
        <value name="AIN8" caption="ADC AIN8 Pin" value="0x8"/>
        <value name="AIN9" caption="ADC AIN9 Pin" value="0x9"/>
        <value name="AIN10" caption="ADC AIN10 Pin" value="0xA"/>
        <value name="AIN11" caption="ADC AIN11 Pin" value="0xB"/>
        <value name="AIN12" caption="ADC AIN12 Pin" value="0xC"/>
        <value name="AIN13" caption="ADC AIN13 Pin" value="0xD"/>
        <value name="AIN14" caption="ADC AIN14 Pin" value="0xE"/>
        <value name="AIN15" caption="ADC AIN15 Pin" value="0xF"/>
        <value name="AIN16" caption="ADC AIN16 Pin" value="0x10"/>
        <value name="AIN17" caption="ADC AIN17 Pin" value="0x11"/>
        <value name="AIN18" caption="ADC AIN18 Pin" value="0x12"/>
        <value name="AIN19" caption="ADC AIN19 Pin" value="0x13"/>
        <value name="AIN20" caption="ADC AIN20 Pin" value="0x14"/>
        <value name="AIN21" caption="ADC AIN21 Pin" value="0x15"/>
        <value name="AIN22" caption="ADC AIN22 Pin" value="0x16"/>
        <value name="AIN23" caption="ADC AIN23 Pin" value="0x17"/>
        <value name="SCALEDCOREVCC" caption="1/4 Scaled Core Supply" value="0x18"/>
        <value name="SCALEDVBAT" caption="1/4 Scaled VBAT Supply" value="0x19"/>
        <value name="SCALEDIOVCC" caption="1/4 Scaled I/O Supply" value="0x1A"/>
        <value name="BANDGAP" caption="Bandgap Voltage" value="0x1B"/>
        <value name="PTAT" caption="Temperature Sensor" value="0x1C"/>
        <value name="CTAT" caption="Temperature Sensor" value="0x1D"/>
        <value name="DAC" caption="DAC Output" value="0x1E"/>
        <value name="PTC" caption="PTC output (only on ADC0)" value="0x1F"/>
      </value-group>
      <value-group name="ADC_CTRLB__RESSEL">
        <value name="12BIT" caption="12-bit result" value="0x0"/>
        <value name="16BIT" caption="For averaging mode output" value="0x1"/>
        <value name="10BIT" caption="10-bit result" value="0x2"/>
        <value name="8BIT" caption="8-bit result" value="0x3"/>
      </value-group>
      <value-group name="ADC_CTRLB__WINMODE">
        <value name="DISABLE" caption="No window mode (default)" value="0"/>
        <value name="MODE1" caption="RESULT &gt; WINLT" value="1"/>
        <value name="MODE2" caption="RESULT &lt; WINUT" value="2"/>
        <value name="MODE3" caption="WINLT &lt; RESULT &lt; WINUT" value="3"/>
        <value name="MODE4" caption="!(WINLT &lt; RESULT &lt; WINUT)" value="4"/>
      </value-group>
      <value-group name="ADC_REFCTRL__REFSEL">
        <value name="INTREF" caption="Internal Bandgap Reference" value="0x0"/>
        <value name="INTVCC0" caption="1/2 VDDANA" value="0x2"/>
        <value name="INTVCC1" caption="VDDANA" value="0x3"/>
        <value name="AREFA" caption="External Reference" value="0x4"/>
        <value name="AREFB" caption="External Reference" value="0x5"/>
        <value name="AREFC" caption="External Reference (only on ADC1)" value="0x6"/>
      </value-group>
      <value-group name="ADC_AVGCTRL__SAMPLENUM">
        <value name="1" caption="1 sample" value="0x0"/>
        <value name="2" caption="2 samples" value="0x1"/>
        <value name="4" caption="4 samples" value="0x2"/>
        <value name="8" caption="8 samples" value="0x3"/>
        <value name="16" caption="16 samples" value="0x4"/>
        <value name="32" caption="32 samples" value="0x5"/>
        <value name="64" caption="64 samples" value="0x6"/>
        <value name="128" caption="128 samples" value="0x7"/>
        <value name="256" caption="256 samples" value="0x8"/>
        <value name="512" caption="512 samples" value="0x9"/>
        <value name="1024" caption="1024 samples" value="0xA"/>
      </value-group>
    </module>
    <module name="AES" id="U2238" version="2.2.0" caption="Advanced Encryption Standard">
      <register-group name="AES" caption="Advanced Encryption Standard">
        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="AESMODE" caption="AES Modes of operation" mask="0x1C" values="AES_CTRLA__AESMODE"/>
          <bitfield name="CFBS" caption="Cipher Feedback Block Size" mask="0xE0" values="AES_CTRLA__CFBS"/>
          <bitfield name="KEYSIZE" caption="Encryption Key Size" mask="0x300" values="AES_CTRLA__KEYSIZE"/>
          <bitfield name="CIPHER" caption="Cipher Mode" mask="0x400" values="AES_CTRLA__CIPHER"/>
          <bitfield name="STARTMODE" caption="Start Mode Select" mask="0x800" values="AES_CTRLA__STARTMODE"/>
          <bitfield name="LOD" caption="Last Output Data Mode" mask="0x1000" values="AES_CTRLA__LOD"/>
          <bitfield name="KEYGEN" caption="Last Key Generation" mask="0x2000" values="AES_CTRLA__KEYGEN"/>
          <bitfield name="XORKEY" caption="XOR Key Operation" mask="0x4000" values="AES_CTRLA__XORKEY"/>
          <bitfield name="CTYPE" caption="Counter Measure Type" mask="0xF0000"/>
        </register>
        <register name="CTRLB" offset="0x4" rw="RW" size="1" initval="0x00" caption="Control B">
          <bitfield name="START" caption="Start Encryption/Decryption" mask="0x1"/>
          <bitfield name="NEWMSG" caption="New message" mask="0x2"/>
          <bitfield name="EOM" caption="End of message" mask="0x4"/>
          <bitfield name="GFMUL" caption="GF Multiplication" mask="0x8"/>
        </register>
        <register name="INTENCLR" offset="0x5" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
          <bitfield name="ENCCMP" caption="Encryption Complete Interrupt Enable" mask="0x1"/>
          <bitfield name="GFMCMP" caption="GF Multiplication Complete Interrupt Enable" mask="0x2"/>
        </register>
        <register name="INTENSET" offset="0x6" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
          <bitfield name="ENCCMP" caption="Encryption Complete Interrupt Enable" mask="0x1"/>
          <bitfield name="GFMCMP" caption="GF Multiplication Complete Interrupt Enable" mask="0x2"/>
        </register>
        <register name="INTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status">
          <bitfield name="ENCCMP" caption="Encryption Complete" mask="0x1"/>
          <bitfield name="GFMCMP" caption="GF Multiplication Complete" mask="0x2"/>
        </register>
        <register name="DATABUFPTR" offset="0x8" rw="RW" size="1" initval="0x00" caption="Data buffer pointer">
          <bitfield name="INDATAPTR" caption="Input Data Pointer" mask="0x3"/>
        </register>
        <register name="DBGCTRL" offset="0x9" rw="RW" size="1" initval="0x00" caption="Debug control">
          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
        </register>
        <register name="KEYWORD" offset="0xC" rw="W" size="4" count="8" initval="0x00000000" caption="Keyword n">
        </register>
        <register name="INDATA" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Indata">
        </register>
        <register name="INTVECTV" offset="0x3C" rw="W" size="4" count="4" initval="0x00000000" caption="Initialisation Vector n">
        </register>
        <register name="HASHKEY" offset="0x5C" rw="RW" size="4" count="4" initval="0x00000000" caption="Hash key n">
        </register>
        <register name="GHASH" offset="0x6C" rw="RW" size="4" count="4" initval="0x00000000" caption="Galois Hash n">
        </register>
        <register name="CIPLEN" offset="0x80" rw="RW" size="4" initval="0x00000000" caption="Cipher Length">
        </register>
        <register name="RANDSEED" offset="0x84" rw="RW" size="4" initval="0x00000000" caption="Random Seed">
        </register>
      </register-group>
      <value-group name="AES_CTRLA__AESMODE">
        <value name="ECB" caption="Electronic code book mode" value="0x0"/>
        <value name="CBC" caption="Cipher block chaining mode" value="0x1"/>
        <value name="OFB" caption="Output feedback mode" value="0x2"/>
        <value name="CFB" caption="Cipher feedback mode" value="0x3"/>
        <value name="COUNTER" caption="Counter mode" value="0x4"/>
        <value name="CCM" caption="CCM mode" value="0x5"/>
        <value name="GCM" caption="Galois counter mode" value="0x6"/>
      </value-group>
      <value-group name="AES_CTRLA__CFBS">
        <value name="128BIT" caption="128-bit Input data block for Encryption/Decryption in Cipher Feedback mode" value="0x0"/>
        <value name="64BIT" caption="64-bit Input data block for Encryption/Decryption in Cipher Feedback mode" value="0x1"/>
        <value name="32BIT" caption="32-bit Input data block for Encryption/Decryption in Cipher Feedback mode" value="0x2"/>
        <value name="16BIT" caption="16-bit Input data block for Encryption/Decryption in Cipher Feedback mode" value="0x3"/>
        <value name="8BIT" caption="8-bit Input data block for Encryption/Decryption in Cipher Feedback mode" value="0x4"/>
      </value-group>
      <value-group name="AES_CTRLA__CIPHER">
        <value name="DEC" caption="Decryption" value="0x0"/>
        <value name="ENC" caption="Encryption" value="0x1"/>
      </value-group>
      <value-group name="AES_CTRLA__KEYGEN">
        <value name="NONE" caption="No effect" value="0x0"/>
        <value name="LAST" caption="Start Computation of the last NK words of the expanded key" value="0x1"/>
      </value-group>
      <value-group name="AES_CTRLA__KEYSIZE">
        <value name="128BIT" caption="128-bit Key for Encryption / Decryption" value="0x0"/>
        <value name="192BIT" caption="192-bit Key for Encryption / Decryption" value="0x1"/>
        <value name="256BIT" caption="256-bit Key for Encryption / Decryption" value="0x2"/>
      </value-group>
      <value-group name="AES_CTRLA__LOD">
        <value name="NONE" caption="No effect" value="0x0"/>
        <value name="LAST" caption="Start encryption in Last Output Data mode" value="0x1"/>
      </value-group>
      <value-group name="AES_CTRLA__STARTMODE">
        <value name="MANUAL" caption="Start Encryption / Decryption in Manual mode" value="0x0"/>
        <value name="AUTO" caption="Start Encryption / Decryption in Auto mode" value="0x1"/>
      </value-group>
      <value-group name="AES_CTRLA__XORKEY">
        <value name="NONE" caption="No effect" value="0x0"/>
        <value name="XOR" caption="The user keyword gets XORed with the previous keyword register content." value="0x1"/>
      </value-group>
    </module>
    <module name="CCL" id="U2225" version="1.1.0" caption="Configurable Custom Logic">
      <register-group name="CCL" caption="Configurable Custom Logic">
        <register name="CTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
        </register>
        <register name="SEQCTRL" offset="0x4" rw="RW" size="1" count="2" initval="0x00" caption="SEQ Control x">
          <bitfield name="SEQSEL" caption="Sequential Selection" mask="0xF" values="CCL_SEQCTRL__SEQSEL"/>
        </register>
        <register name="LUTCTRL" offset="0x8" rw="RW" size="4" count="4" initval="0x00000000" caption="LUT Control x">
          <bitfield name="ENABLE" caption="LUT Enable" mask="0x2"/>
          <bitfield name="FILTSEL" caption="Filter Selection" mask="0x30" values="CCL_LUTCTRL__FILTSEL"/>
          <bitfield name="EDGESEL" caption="Edge Selection" mask="0x80"/>
          <bitfield name="INSEL0" caption="Input Selection 0" mask="0xF00" values="CCL_LUTCTRL__INSEL0"/>
          <bitfield name="INSEL1" caption="Input Selection 1" mask="0xF000" values="CCL_LUTCTRL__INSEL1"/>
          <bitfield name="INSEL2" caption="Input Selection 2" mask="0xF0000" values="CCL_LUTCTRL__INSEL2"/>
          <bitfield name="INVEI" caption="Inverted Event Input Enable" mask="0x100000"/>
          <bitfield name="LUTEI" caption="LUT Event Input Enable" mask="0x200000"/>
          <bitfield name="LUTEO" caption="LUT Event Output Enable" mask="0x400000"/>
          <bitfield name="TRUTH" caption="Truth Value" mask="0xFF000000"/>
        </register>
      </register-group>
      <value-group name="CCL_SEQCTRL__SEQSEL">
        <value name="DISABLE" caption="Sequential logic is disabled" value="0"/>
        <value name="DFF" caption="D flip flop" value="1"/>
        <value name="JK" caption="JK flip flop" value="2"/>
        <value name="LATCH" caption="D latch" value="3"/>
        <value name="RS" caption="RS latch" value="4"/>
      </value-group>
      <value-group name="CCL_LUTCTRL__FILTSEL">
        <value name="DISABLE" caption="Filter disabled" value="0"/>
        <value name="SYNCH" caption="Synchronizer enabled" value="1"/>
        <value name="FILTER" caption="Filter enabled" value="2"/>
      </value-group>
      <value-group name="CCL_LUTCTRL__INSEL0">
        <value name="MASK" caption="Masked input" value="0"/>
        <value name="FEEDBACK" caption="Feedback input source" value="1"/>
        <value name="LINK" caption="Linked LUT input source" value="2"/>
        <value name="EVENT" caption="Event input source" value="3"/>
        <value name="IO" caption="I/O pin input source" value="4"/>
        <value name="AC" caption="AC input source" value="5"/>
        <value name="TC" caption="TC input source" value="6"/>
        <value name="ALTTC" caption="Alternate TC input source" value="7"/>
        <value name="TCC" caption="TCC input source" value="8"/>
        <value name="SERCOM" caption="SERCOM input source" value="9"/>
      </value-group>
      <value-group name="CCL_LUTCTRL__INSEL1">
        <value name="MASK" caption="Masked input" value="0x0"/>
        <value name="FEEDBACK" caption="Feedback input source" value="0x1"/>
        <value name="LINK" caption="Linked LUT input source" value="0x2"/>
        <value name="EVENT" caption="Event input source" value="0x3"/>
        <value name="IO" caption="I/O pin input source" value="0x4"/>
        <value name="AC" caption="AC input source" value="0x5"/>
        <value name="TC" caption="TC input source" value="0x6"/>
        <value name="ALTTC" caption="Alternate TC input source" value="0x7"/>
        <value name="TCC" caption="TCC input source" value="0x8"/>
        <value name="SERCOM" caption="SERCOM input source" value="0x9"/>
      </value-group>
      <value-group name="CCL_LUTCTRL__INSEL2">
        <value name="MASK" caption="Masked input" value="0x0"/>
        <value name="FEEDBACK" caption="Feedback input source" value="0x1"/>
        <value name="LINK" caption="Linked LUT input source" value="0x2"/>
        <value name="EVENT" caption="Event input source" value="0x3"/>
        <value name="IO" caption="I/O pin input source" value="0x4"/>
        <value name="AC" caption="AC input source" value="0x5"/>
        <value name="TC" caption="TC input source" value="0x6"/>
        <value name="ALTTC" caption="Alternate TC input source" value="0x7"/>
        <value name="TCC" caption="TCC input source" value="0x8"/>
        <value name="SERCOM" caption="SERCOM input source" value="0x9"/>
      </value-group>
    </module>
    <module name="CMCC" id="U2015" version="6.0.0" caption="Cortex M Cache Controller">
      <register-group name="CMCC" caption="Cortex M Cache Controller">
        <register name="TYPE" offset="0x0" rw="R" size="4" access-size="4" initval="0x000012D2" caption="Cache Type Register">
          <bitfield name="GCLK" caption="dynamic Clock Gating supported" mask="0x2"/>
          <bitfield name="RRP" caption="Round Robin Policy supported" mask="0x10"/>
          <bitfield name="WAYNUM" caption="Number of Way" mask="0x60" values="CMCC_TYPE__WAYNUM"/>
          <bitfield name="LCKDOWN" caption="Lock Down supported" mask="0x80"/>
          <bitfield name="CSIZE" caption="Cache Size" mask="0x700" values="CMCC_TYPE__CSIZE"/>
          <bitfield name="CLSIZE" caption="Cache Line Size" mask="0x3800" values="CMCC_TYPE__CLSIZE"/>
        </register>
        <register name="CFG" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000020" caption="Cache Configuration Register">
          <bitfield name="ICDIS" caption="Instruction Cache Disable" mask="0x2"/>
          <bitfield name="DCDIS" caption="Data Cache Disable" mask="0x4"/>
          <bitfield name="CSIZESW" caption="Cache size configured by software" mask="0x70" values="CMCC_CFG__CSIZESW"/>
        </register>
        <register name="CTRL" offset="0x8" rw="W" size="4" access-size="4" initval="0x00000000" caption="Cache Control Register">
          <bitfield name="CEN" caption="Cache Controller Enable" mask="0x1"/>
        </register>
        <register name="SR" offset="0xC" rw="R" size="4" access-size="4" initval="0x00000000" caption="Cache Status Register">
          <bitfield name="CSTS" caption="Cache Controller Status" mask="0x1"/>
        </register>
        <register name="LCKWAY" offset="0x10" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Cache Lock per Way Register">
          <bitfield name="LCKWAY" caption="Lockdown way Register" mask="0xF"/>
        </register>
        <register name="MAINT0" offset="0x20" rw="W" size="4" access-size="4" initval="0x00000000" caption="Cache Maintenance Register 0">
          <bitfield name="INVALL" caption="Cache Controller invalidate All" mask="0x1"/>
        </register>
        <register name="MAINT1" offset="0x24" rw="W" size="4" access-size="4" initval="0x00000000" caption="Cache Maintenance Register 1">
          <bitfield name="INDEX" caption="Invalidate Index" mask="0xFF0"/>
          <bitfield name="WAY" caption="Invalidate Way" mask="0xF0000000" values="CMCC_MAINT1__WAY"/>
        </register>
        <register name="MCFG" offset="0x28" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Cache Monitor Configuration Register">
          <bitfield name="MODE" caption="Cache Controller Monitor Counter Mode" mask="0x3" values="CMCC_MCFG__MODE"/>
        </register>
        <register name="MEN" offset="0x2C" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Cache Monitor Enable Register">
          <bitfield name="MENABLE" caption="Cache Controller Monitor Enable" mask="0x1"/>
        </register>
        <register name="MCTRL" offset="0x30" rw="W" size="4" access-size="4" initval="0x00000000" caption="Cache Monitor Control Register">
          <bitfield name="SWRST" caption="Cache Controller Software Reset" mask="0x1"/>
        </register>
        <register name="MSR" offset="0x34" rw="R" size="4" access-size="4" initval="0x00000000" caption="Cache Monitor Status Register">
          <bitfield name="EVENT_CNT" caption="Monitor Event Counter" mask="0xFFFFFFFF"/>
        </register>
      </register-group>
      <value-group name="CMCC_TYPE__CLSIZE">
        <value name="CLSIZE_4B" caption="Cache Line Size is 4 bytes" value="0"/>
        <value name="CLSIZE_8B" caption="Cache Line Size is 8 bytes" value="1"/>
        <value name="CLSIZE_16B" caption="Cache Line Size is 16 bytes" value="2"/>
        <value name="CLSIZE_32B" caption="Cache Line Size is 32 bytes" value="3"/>
        <value name="CLSIZE_64B" caption="Cache Line Size is 64 bytes" value="4"/>
        <value name="CLSIZE_128B" caption="Cache Line Size is 128 bytes" value="5"/>
      </value-group>
      <value-group name="CMCC_TYPE__CSIZE">
        <value name="CSIZE_1KB" caption="Cache Size is 1 KB" value="0"/>
        <value name="CSIZE_2KB" caption="Cache Size is 2 KB" value="1"/>
        <value name="CSIZE_4KB" caption="Cache Size is 4 KB" value="2"/>
        <value name="CSIZE_8KB" caption="Cache Size is 8 KB" value="3"/>
        <value name="CSIZE_16KB" caption="Cache Size is 16 KB" value="4"/>
        <value name="CSIZE_32KB" caption="Cache Size is 32 KB" value="5"/>
        <value name="CSIZE_64KB" caption="Cache Size is 64 KB" value="6"/>
      </value-group>
      <value-group name="CMCC_TYPE__WAYNUM">
        <value name="DMAPPED" caption="Direct Mapped Cache" value="0"/>
        <value name="ARCH2WAY" caption="2-WAY set associative" value="1"/>
        <value name="ARCH4WAY" caption="4-WAY set associative" value="2"/>
      </value-group>
      <value-group name="CMCC_CFG__CSIZESW">
        <value name="CONF_CSIZE_1KB" caption="The Cache Size is configured to 1KB" value="0"/>
        <value name="CONF_CSIZE_2KB" caption="The Cache Size is configured to 2KB" value="1"/>
        <value name="CONF_CSIZE_4KB" caption="The Cache Size is configured to 4KB" value="2"/>
        <value name="CONF_CSIZE_8KB" caption="The Cache Size is configured to 8KB" value="3"/>
        <value name="CONF_CSIZE_16KB" caption="The Cache Size is configured to 16KB" value="4"/>
        <value name="CONF_CSIZE_32KB" caption="The Cache Size is configured to 32KB" value="5"/>
        <value name="CONF_CSIZE_64KB" caption="The Cache Size is configured to 64KB" value="6"/>
      </value-group>
      <value-group name="CMCC_MAINT1__WAY">
        <value name="WAY0" caption="Way 0 is selection for index invalidation" value="0"/>
        <value name="WAY1" caption="Way 1 is selection for index invalidation" value="1"/>
        <value name="WAY2" caption="Way 2 is selection for index invalidation" value="2"/>
        <value name="WAY3" caption="Way 3 is selection for index invalidation" value="3"/>
      </value-group>
      <value-group name="CMCC_MCFG__MODE">
        <value name="CYCLE_COUNT" caption="Cycle counter" value="0"/>
        <value name="IHIT_COUNT" caption="Instruction hit counter" value="1"/>
        <value name="DHIT_COUNT" caption="Data hit counter" value="2"/>
      </value-group>
    </module>
    <module name="DAC" id="U2502" version="1.0.0" caption="Digital-to-Analog Converter">
      <register-group name="DAC" caption="Digital-to-Analog Converter">
        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable DAC Controller" mask="0x2"/>
        </register>
        <register name="CTRLB" offset="0x1" rw="RW" size="1" initval="0x02" caption="Control B">
          <bitfield name="DIFF" caption="Differential mode enable" mask="0x1"/>
          <bitfield name="REFSEL" caption="Reference Selection for DAC0/1" mask="0x6" values="DAC_CTRLB__REFSEL"/>
        </register>
        <register name="EVCTRL" offset="0x2" rw="RW" size="1" initval="0x00" caption="Event Control">
          <bitfield name="STARTEI0" caption="Start Conversion Event Input DAC 0" mask="0x1"/>
          <bitfield name="STARTEI1" caption="Start Conversion Event Input DAC 1" mask="0x2"/>
          <bitfield name="EMPTYEO0" caption="Data Buffer Empty Event Output DAC 0" mask="0x4"/>
          <bitfield name="EMPTYEO1" caption="Data Buffer Empty Event Output DAC 1" mask="0x8"/>
          <bitfield name="INVEI0" caption="Enable Invertion of DAC 0 input event" mask="0x10"/>
          <bitfield name="INVEI1" caption="Enable Invertion of DAC 1 input event" mask="0x20"/>
          <bitfield name="RESRDYEO0" caption="Result Ready Event Output 0" mask="0x40"/>
          <bitfield name="RESRDYEO1" caption="Result Ready Event Output 1" mask="0x80"/>
        </register>
        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
          <bitfield name="UNDERRUN0" caption="Underrun 0 Interrupt Enable" mask="0x1"/>
          <bitfield name="UNDERRUN1" caption="Underrun 1 Interrupt Enable" mask="0x2"/>
          <bitfield name="EMPTY0" caption="Data Buffer 0 Empty Interrupt Enable" mask="0x4"/>
          <bitfield name="EMPTY1" caption="Data Buffer 1 Empty Interrupt Enable" mask="0x8"/>
          <bitfield name="RESRDY0" caption="Result 0 Ready Interrupt Enable" mask="0x10"/>
          <bitfield name="RESRDY1" caption="Result 1 Ready Interrupt Enable" mask="0x20"/>
          <bitfield name="OVERRUN0" caption="Overrun 0 Interrupt Enable" mask="0x40"/>
          <bitfield name="OVERRUN1" caption="Overrun 1 Interrupt Enable" mask="0x80"/>
        </register>
        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
          <bitfield name="UNDERRUN0" caption="Underrun 0 Interrupt Enable" mask="0x1"/>
          <bitfield name="UNDERRUN1" caption="Underrun 1 Interrupt Enable" mask="0x2"/>
          <bitfield name="EMPTY0" caption="Data Buffer 0 Empty Interrupt Enable" mask="0x4"/>
          <bitfield name="EMPTY1" caption="Data Buffer 1 Empty Interrupt Enable" mask="0x8"/>
          <bitfield name="RESRDY0" caption="Result 0 Ready Interrupt Enable" mask="0x10"/>
          <bitfield name="RESRDY1" caption="Result 1 Ready Interrupt Enable" mask="0x20"/>
          <bitfield name="OVERRUN0" caption="Overrun 0 Interrupt Enable" mask="0x40"/>
          <bitfield name="OVERRUN1" caption="Overrun 1 Interrupt Enable" mask="0x80"/>
        </register>
        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
          <bitfield name="UNDERRUN0" caption="Result 0 Underrun" mask="0x1"/>
          <bitfield name="UNDERRUN1" caption="Result 1 Underrun" mask="0x2"/>
          <bitfield name="EMPTY0" caption="Data Buffer 0 Empty" mask="0x4"/>
          <bitfield name="EMPTY1" caption="Data Buffer 1 Empty" mask="0x8"/>
          <bitfield name="RESRDY0" caption="Result 0 Ready" mask="0x10"/>
          <bitfield name="RESRDY1" caption="Result 1 Ready" mask="0x20"/>
          <bitfield name="OVERRUN0" caption="Result 0 Overrun" mask="0x40"/>
          <bitfield name="OVERRUN1" caption="Result 1 Overrun" mask="0x80"/>
        </register>
        <register name="STATUS" offset="0x7" rw="R" size="1" initval="0x00" caption="Status">
          <bitfield name="READY0" caption="DAC 0 Startup Ready" mask="0x1"/>
          <bitfield name="READY1" caption="DAC 1 Startup Ready" mask="0x2"/>
          <bitfield name="EOC0" caption="DAC 0 End of Conversion" mask="0x4"/>
          <bitfield name="EOC1" caption="DAC 1 End of Conversion" mask="0x8"/>
        </register>
        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="DAC Enable Status" mask="0x2"/>
          <bitfield name="DATA0" caption="Data DAC 0" mask="0x4"/>
          <bitfield name="DATA1" caption="Data DAC 1" mask="0x8"/>
          <bitfield name="DATABUF0" caption="Data Buffer DAC 0" mask="0x10"/>
          <bitfield name="DATABUF1" caption="Data Buffer DAC 1" mask="0x20"/>
        </register>
        <register name="DACCTRL" offset="0xC" rw="RW" size="2" count="2" initval="0x0000" caption="DAC n Control">
          <bitfield name="LEFTADJ" caption="Left Adjusted Data" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable DAC0" mask="0x2"/>
          <bitfield name="CCTRL" caption="Current Control" mask="0xC" values="DAC_DACCTRL__CCTRL"/>
          <bitfield name="FEXT" caption="Standalone Filter" mask="0x20"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
          <bitfield name="DITHER" caption="Dithering Mode" mask="0x80"/>
          <bitfield name="REFRESH" caption="Refresh period" mask="0xF00"/>
          <bitfield name="OSR" caption="Sampling Rate" mask="0xE000"/>
        </register>
        <register name="DATA" offset="0x10" rw="W" access="WSYNC" size="2" count="2" initval="0x0000" caption="DAC n Data">
          <bitfield name="DATA" caption="DAC0 Data" mask="0xFFFF"/>
        </register>
        <register name="DATABUF" offset="0x14" rw="W" access="WSYNC" size="2" count="2" initval="0x0000" caption="DAC n Data Buffer">
          <bitfield name="DATABUF" caption="DAC0 Data Buffer" mask="0xFFFF"/>
        </register>
        <register name="DBGCTRL" offset="0x18" rw="RW" size="1" initval="0x00" caption="Debug Control">
          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
        </register>
        <register name="RESULT" offset="0x1C" rw="R" size="2" count="2" initval="0x0000" caption="Filter Result">
          <bitfield name="RESULT" caption="Filter Result" mask="0xFFFF"/>
        </register>
      </register-group>
      <value-group name="DAC_CTRLB__REFSEL">
        <value name="VREFPU" caption="External reference unbuffered" value="0"/>
        <value name="VDDANA" caption="Analog supply" value="1"/>
        <value name="VREFPB" caption="External reference buffered" value="2"/>
        <value name="INTREF" caption="Internal bandgap reference" value="3"/>
      </value-group>
      <value-group name="DAC_DACCTRL__CCTRL">
        <value name="CC100K" caption="GCLK_DAC &lt;= 1.2MHz (100kSPS)" value="0x0"/>
        <value name="CC1M" caption="1.2MHz &lt; GCLK_DAC  &lt;= 6MHz (500kSPS)" value="0x1"/>
        <value name="CC12M" caption="6MHz &lt; GCLK_DAC &lt;= 12MHz (1MSPS)" value="0x2"/>
      </value-group>
    </module>
    <module name="DMAC" id="U2503" version="1.0.0" caption="Direct Memory Access Controller">
      <register-group name="CHANNEL" size="0x10">
        <register name="CHCTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Channel n Control A">
          <bitfield name="SWRST" caption="Channel Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Channel Enable" mask="0x2"/>
          <bitfield name="RUNSTDBY" caption="Channel Run in Standby" mask="0x40"/>
          <bitfield name="TRIGSRC" caption="Trigger Source" mask="0x7F00" values="DMAC_CHCTRLA__TRIGSRC"/>
          <bitfield name="TRIGACT" caption="Trigger Action" mask="0x300000" values="DMAC_CHCTRLA__TRIGACT"/>
          <bitfield name="BURSTLEN" caption="Burst Length" mask="0xF000000" values="DMAC_CHCTRLA__BURSTLEN"/>
          <bitfield name="THRESHOLD" caption="FIFO Threshold" mask="0x30000000" values="DMAC_CHCTRLA__THRESHOLD"/>
        </register>
        <register name="CHCTRLB" offset="0x4" rw="RW" size="1" initval="0x00" caption="Channel n Control B">
          <bitfield name="CMD" caption="Software Command" mask="0x3" values="DMAC_CHCTRLB__CMD"/>
        </register>
        <register name="CHPRILVL" offset="0x5" rw="RW" size="1" initval="0x00" caption="Channel n Priority Level">
          <bitfield name="PRILVL" caption="Channel Priority Level" mask="0x3" values="DMAC_CHPRILVL__PRILVL"/>
        </register>
        <register name="CHEVCTRL" offset="0x6" rw="RW" size="1" initval="0x00" caption="Channel n Event Control">
          <bitfield name="EVACT" caption="Channel Event Input Action" mask="0x7" values="DMAC_CHEVCTRL__EVACT"/>
          <bitfield name="EVOMODE" caption="Channel Event Output Mode" mask="0x30" values="DMAC_CHEVCTRL__EVOMODE"/>
          <bitfield name="EVIE" caption="Channel Event Input Enable" mask="0x40"/>
          <bitfield name="EVOE" caption="Channel Event Output Enable" mask="0x80"/>
        </register>
        <register name="CHINTENCLR" offset="0xC" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel n Interrupt Enable Clear">
          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
        </register>
        <register name="CHINTENSET" offset="0xD" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel n Interrupt Enable Set">
          <bitfield name="TERR" caption="Channel Transfer Error Interrupt Enable" mask="0x1"/>
          <bitfield name="TCMPL" caption="Channel Transfer Complete Interrupt Enable" mask="0x2"/>
          <bitfield name="SUSP" caption="Channel Suspend Interrupt Enable" mask="0x4"/>
        </register>
        <register name="CHINTFLAG" offset="0xE" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel n Interrupt Flag Status and Clear">
          <bitfield name="TERR" caption="Channel Transfer Error" mask="0x1"/>
          <bitfield name="TCMPL" caption="Channel Transfer Complete" mask="0x2"/>
          <bitfield name="SUSP" caption="Channel Suspend" mask="0x4"/>
        </register>
        <register name="CHSTATUS" offset="0xF" rw="RW" size="1" initval="0x00" caption="Channel n Status">
          <bitfield name="PEND" caption="Channel Pending" mask="0x1"/>
          <bitfield name="BUSY" caption="Channel Busy" mask="0x2"/>
          <bitfield name="FERR" caption="Channel Fetch Error" mask="0x4"/>
          <bitfield name="CRCERR" caption="Channel CRC Error" mask="0x8"/>
        </register>
      </register-group>
      <register-group name="DMAC" caption="Direct Memory Access Controller">
        <register name="CTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Control">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="DMAENABLE" caption="DMA Enable" mask="0x2"/>
          <bitfield name="LVLEN0" caption="Priority Level 0 Enable" mask="0x100"/>
          <bitfield name="LVLEN1" caption="Priority Level 1 Enable" mask="0x200"/>
          <bitfield name="LVLEN2" caption="Priority Level 2 Enable" mask="0x400"/>
          <bitfield name="LVLEN3" caption="Priority Level 3 Enable" mask="0x800"/>
        </register>
        <register name="CRCCTRL" offset="0x2" rw="RW" size="2" initval="0x0000" caption="CRC Control">
          <bitfield name="CRCBEATSIZE" caption="CRC Beat Size" mask="0x3" values="DMAC_CRCCTRL__CRCBEATSIZE"/>
          <bitfield name="CRCPOLY" caption="CRC Polynomial Type" mask="0xC" values="DMAC_CRCCTRL__CRCPOLY"/>
          <bitfield name="CRCSRC" caption="CRC Input Source" mask="0x3F00" values="DMAC_CRCCTRL__CRCSRC"/>
          <bitfield name="CRCMODE" caption="CRC Operating Mode" mask="0xC000" values="DMAC_CRCCTRL__CRCMODE"/>
        </register>
        <register name="CRCDATAIN" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="CRC Data Input">
          <bitfield name="CRCDATAIN" caption="CRC Data Input" mask="0xFFFFFFFF"/>
        </register>
        <register name="CRCCHKSUM" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="CRC Checksum">
          <bitfield name="CRCCHKSUM" caption="CRC Checksum" mask="0xFFFFFFFF"/>
        </register>
        <register name="CRCSTATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="CRC Status">
          <bitfield name="CRCBUSY" caption="CRC Module Busy" mask="0x1"/>
          <bitfield name="CRCZERO" caption="CRC Zero" mask="0x2"/>
          <bitfield name="CRCERR" caption="CRC Error" mask="0x4"/>
        </register>
        <register name="DBGCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Debug Control">
          <bitfield name="DBGRUN" caption="Debug Run" mask="0x1"/>
        </register>
        <register name="SWTRIGCTRL" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Software Trigger Control">
          <bitfield name="SWTRIG0" caption="Channel 0 Software Trigger" mask="0x1"/>
          <bitfield name="SWTRIG1" caption="Channel 1 Software Trigger" mask="0x2"/>
          <bitfield name="SWTRIG2" caption="Channel 2 Software Trigger" mask="0x4"/>
          <bitfield name="SWTRIG3" caption="Channel 3 Software Trigger" mask="0x8"/>
          <bitfield name="SWTRIG4" caption="Channel 4 Software Trigger" mask="0x10"/>
          <bitfield name="SWTRIG5" caption="Channel 5 Software Trigger" mask="0x20"/>
          <bitfield name="SWTRIG6" caption="Channel 6 Software Trigger" mask="0x40"/>
          <bitfield name="SWTRIG7" caption="Channel 7 Software Trigger" mask="0x80"/>
          <bitfield name="SWTRIG8" caption="Channel 8 Software Trigger" mask="0x100"/>
          <bitfield name="SWTRIG9" caption="Channel 9 Software Trigger" mask="0x200"/>
          <bitfield name="SWTRIG10" caption="Channel 10 Software Trigger" mask="0x400"/>
          <bitfield name="SWTRIG11" caption="Channel 11 Software Trigger" mask="0x800"/>
          <bitfield name="SWTRIG12" caption="Channel 12 Software Trigger" mask="0x1000"/>
          <bitfield name="SWTRIG13" caption="Channel 13 Software Trigger" mask="0x2000"/>
          <bitfield name="SWTRIG14" caption="Channel 14 Software Trigger" mask="0x4000"/>
          <bitfield name="SWTRIG15" caption="Channel 15 Software Trigger" mask="0x8000"/>
          <bitfield name="SWTRIG16" caption="Channel 16 Software Trigger" mask="0x10000"/>
          <bitfield name="SWTRIG17" caption="Channel 17 Software Trigger" mask="0x20000"/>
          <bitfield name="SWTRIG18" caption="Channel 18 Software Trigger" mask="0x40000"/>
          <bitfield name="SWTRIG19" caption="Channel 19 Software Trigger" mask="0x80000"/>
          <bitfield name="SWTRIG20" caption="Channel 20 Software Trigger" mask="0x100000"/>
          <bitfield name="SWTRIG21" caption="Channel 21 Software Trigger" mask="0x200000"/>
          <bitfield name="SWTRIG22" caption="Channel 22 Software Trigger" mask="0x400000"/>
          <bitfield name="SWTRIG23" caption="Channel 23 Software Trigger" mask="0x800000"/>
          <bitfield name="SWTRIG24" caption="Channel 24 Software Trigger" mask="0x1000000"/>
          <bitfield name="SWTRIG25" caption="Channel 25 Software Trigger" mask="0x2000000"/>
          <bitfield name="SWTRIG26" caption="Channel 26 Software Trigger" mask="0x4000000"/>
          <bitfield name="SWTRIG27" caption="Channel 27 Software Trigger" mask="0x8000000"/>
          <bitfield name="SWTRIG28" caption="Channel 28 Software Trigger" mask="0x10000000"/>
          <bitfield name="SWTRIG29" caption="Channel 29 Software Trigger" mask="0x20000000"/>
          <bitfield name="SWTRIG30" caption="Channel 30 Software Trigger" mask="0x40000000"/>
          <bitfield name="SWTRIG31" caption="Channel 31 Software Trigger" mask="0x80000000"/>
        </register>
        <register name="PRICTRL0" offset="0x14" rw="RW" size="4" initval="0x40404040" caption="Priority Control 0">
          <bitfield name="LVLPRI0" caption="Level 0 Channel Priority Number" mask="0x1F"/>
          <bitfield name="QOS0" caption="Level 0 Quality of Service" mask="0x60" values="DMAC_PRICTRL0__QOS0"/>
          <bitfield name="RRLVLEN0" caption="Level 0 Round-Robin Scheduling Enable" mask="0x80"/>
          <bitfield name="LVLPRI1" caption="Level 1 Channel Priority Number" mask="0x1F00"/>
          <bitfield name="QOS1" caption="Level 1 Quality of Service" mask="0x6000" values="DMAC_PRICTRL0__QOS1"/>
          <bitfield name="RRLVLEN1" caption="Level 1 Round-Robin Scheduling Enable" mask="0x8000"/>
          <bitfield name="LVLPRI2" caption="Level 2 Channel Priority Number" mask="0x1F0000"/>
          <bitfield name="QOS2" caption="Level 2 Quality of Service" mask="0x600000" values="DMAC_PRICTRL0__QOS2"/>
          <bitfield name="RRLVLEN2" caption="Level 2 Round-Robin Scheduling Enable" mask="0x800000"/>
          <bitfield name="LVLPRI3" caption="Level 3 Channel Priority Number" mask="0x1F000000"/>
          <bitfield name="QOS3" caption="Level 3 Quality of Service" mask="0x60000000" values="DMAC_PRICTRL0__QOS3"/>
          <bitfield name="RRLVLEN3" caption="Level 3 Round-Robin Scheduling Enable" mask="0x80000000"/>
        </register>
        <register name="INTPEND" offset="0x20" rw="RW" size="2" initval="0x0000" caption="Interrupt Pending">
          <bitfield name="ID" caption="Channel ID" mask="0x1F"/>
          <bitfield name="TERR" caption="Transfer Error" mask="0x100"/>
          <bitfield name="TCMPL" caption="Transfer Complete" mask="0x200"/>
          <bitfield name="SUSP" caption="Channel Suspend" mask="0x400"/>
          <bitfield name="CRCERR" caption="CRC Error" mask="0x1000"/>
          <bitfield name="FERR" caption="Fetch Error" mask="0x2000"/>
          <bitfield name="BUSY" caption="Busy" mask="0x4000"/>
          <bitfield name="PEND" caption="Pending" mask="0x8000"/>
        </register>
        <register name="INTSTATUS" offset="0x24" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
          <bitfield name="CHINT12" caption="Channel 12 Pending Interrupt" mask="0x1000"/>
          <bitfield name="CHINT13" caption="Channel 13 Pending Interrupt" mask="0x2000"/>
          <bitfield name="CHINT14" caption="Channel 14 Pending Interrupt" mask="0x4000"/>
          <bitfield name="CHINT15" caption="Channel 15 Pending Interrupt" mask="0x8000"/>
          <bitfield name="CHINT16" caption="Channel 16 Pending Interrupt" mask="0x10000"/>
          <bitfield name="CHINT17" caption="Channel 17 Pending Interrupt" mask="0x20000"/>
          <bitfield name="CHINT18" caption="Channel 18 Pending Interrupt" mask="0x40000"/>
          <bitfield name="CHINT19" caption="Channel 19 Pending Interrupt" mask="0x80000"/>
          <bitfield name="CHINT20" caption="Channel 20 Pending Interrupt" mask="0x100000"/>
          <bitfield name="CHINT21" caption="Channel 21 Pending Interrupt" mask="0x200000"/>
          <bitfield name="CHINT22" caption="Channel 22 Pending Interrupt" mask="0x400000"/>
          <bitfield name="CHINT23" caption="Channel 23 Pending Interrupt" mask="0x800000"/>
          <bitfield name="CHINT24" caption="Channel 24 Pending Interrupt" mask="0x1000000"/>
          <bitfield name="CHINT25" caption="Channel 25 Pending Interrupt" mask="0x2000000"/>
          <bitfield name="CHINT26" caption="Channel 26 Pending Interrupt" mask="0x4000000"/>
          <bitfield name="CHINT27" caption="Channel 27 Pending Interrupt" mask="0x8000000"/>
          <bitfield name="CHINT28" caption="Channel 28 Pending Interrupt" mask="0x10000000"/>
          <bitfield name="CHINT29" caption="Channel 29 Pending Interrupt" mask="0x20000000"/>
          <bitfield name="CHINT30" caption="Channel 30 Pending Interrupt" mask="0x40000000"/>
          <bitfield name="CHINT31" caption="Channel 31 Pending Interrupt" mask="0x80000000"/>
        </register>
        <register name="BUSYCH" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
          <bitfield name="BUSYCH12" caption="Busy Channel 12" mask="0x1000"/>
          <bitfield name="BUSYCH13" caption="Busy Channel 13" mask="0x2000"/>
          <bitfield name="BUSYCH14" caption="Busy Channel 14" mask="0x4000"/>
          <bitfield name="BUSYCH15" caption="Busy Channel 15" mask="0x8000"/>
          <bitfield name="BUSYCH16" caption="Busy Channel 16" mask="0x10000"/>
          <bitfield name="BUSYCH17" caption="Busy Channel 17" mask="0x20000"/>
          <bitfield name="BUSYCH18" caption="Busy Channel 18" mask="0x40000"/>
          <bitfield name="BUSYCH19" caption="Busy Channel 19" mask="0x80000"/>
          <bitfield name="BUSYCH20" caption="Busy Channel 20" mask="0x100000"/>
          <bitfield name="BUSYCH21" caption="Busy Channel 21" mask="0x200000"/>
          <bitfield name="BUSYCH22" caption="Busy Channel 22" mask="0x400000"/>
          <bitfield name="BUSYCH23" caption="Busy Channel 23" mask="0x800000"/>
          <bitfield name="BUSYCH24" caption="Busy Channel 24" mask="0x1000000"/>
          <bitfield name="BUSYCH25" caption="Busy Channel 25" mask="0x2000000"/>
          <bitfield name="BUSYCH26" caption="Busy Channel 26" mask="0x4000000"/>
          <bitfield name="BUSYCH27" caption="Busy Channel 27" mask="0x8000000"/>
          <bitfield name="BUSYCH28" caption="Busy Channel 28" mask="0x10000000"/>
          <bitfield name="BUSYCH29" caption="Busy Channel 29" mask="0x20000000"/>
          <bitfield name="BUSYCH30" caption="Busy Channel 30" mask="0x40000000"/>
          <bitfield name="BUSYCH31" caption="Busy Channel 31" mask="0x80000000"/>
        </register>
        <register name="PENDCH" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="Pending Channels">
          <bitfield name="PENDCH0" caption="Pending Channel 0" mask="0x1"/>
          <bitfield name="PENDCH1" caption="Pending Channel 1" mask="0x2"/>
          <bitfield name="PENDCH2" caption="Pending Channel 2" mask="0x4"/>
          <bitfield name="PENDCH3" caption="Pending Channel 3" mask="0x8"/>
          <bitfield name="PENDCH4" caption="Pending Channel 4" mask="0x10"/>
          <bitfield name="PENDCH5" caption="Pending Channel 5" mask="0x20"/>
          <bitfield name="PENDCH6" caption="Pending Channel 6" mask="0x40"/>
          <bitfield name="PENDCH7" caption="Pending Channel 7" mask="0x80"/>
          <bitfield name="PENDCH8" caption="Pending Channel 8" mask="0x100"/>
          <bitfield name="PENDCH9" caption="Pending Channel 9" mask="0x200"/>
          <bitfield name="PENDCH10" caption="Pending Channel 10" mask="0x400"/>
          <bitfield name="PENDCH11" caption="Pending Channel 11" mask="0x800"/>
          <bitfield name="PENDCH12" caption="Pending Channel 12" mask="0x1000"/>
          <bitfield name="PENDCH13" caption="Pending Channel 13" mask="0x2000"/>
          <bitfield name="PENDCH14" caption="Pending Channel 14" mask="0x4000"/>
          <bitfield name="PENDCH15" caption="Pending Channel 15" mask="0x8000"/>
          <bitfield name="PENDCH16" caption="Pending Channel 16" mask="0x10000"/>
          <bitfield name="PENDCH17" caption="Pending Channel 17" mask="0x20000"/>
          <bitfield name="PENDCH18" caption="Pending Channel 18" mask="0x40000"/>
          <bitfield name="PENDCH19" caption="Pending Channel 19" mask="0x80000"/>
          <bitfield name="PENDCH20" caption="Pending Channel 20" mask="0x100000"/>
          <bitfield name="PENDCH21" caption="Pending Channel 21" mask="0x200000"/>
          <bitfield name="PENDCH22" caption="Pending Channel 22" mask="0x400000"/>
          <bitfield name="PENDCH23" caption="Pending Channel 23" mask="0x800000"/>
          <bitfield name="PENDCH24" caption="Pending Channel 24" mask="0x1000000"/>
          <bitfield name="PENDCH25" caption="Pending Channel 25" mask="0x2000000"/>
          <bitfield name="PENDCH26" caption="Pending Channel 26" mask="0x4000000"/>
          <bitfield name="PENDCH27" caption="Pending Channel 27" mask="0x8000000"/>
          <bitfield name="PENDCH28" caption="Pending Channel 28" mask="0x10000000"/>
          <bitfield name="PENDCH29" caption="Pending Channel 29" mask="0x20000000"/>
          <bitfield name="PENDCH30" caption="Pending Channel 30" mask="0x40000000"/>
          <bitfield name="PENDCH31" caption="Pending Channel 31" mask="0x80000000"/>
        </register>
        <register name="ACTIVE" offset="0x30" rw="R" size="4" initval="0x00000000" caption="Active Channel and Levels">
          <bitfield name="LVLEX0" caption="Level 0 Channel Trigger Request Executing" mask="0x1"/>
          <bitfield name="LVLEX1" caption="Level 1 Channel Trigger Request Executing" mask="0x2"/>
          <bitfield name="LVLEX2" caption="Level 2 Channel Trigger Request Executing" mask="0x4"/>
          <bitfield name="LVLEX3" caption="Level 3 Channel Trigger Request Executing" mask="0x8"/>
          <bitfield name="ID" caption="Active Channel ID" mask="0x1F00"/>
          <bitfield name="ABUSY" caption="Active Channel Busy" mask="0x8000"/>
          <bitfield name="BTCNT" caption="Active Channel Block Transfer Count" mask="0xFFFF0000"/>
        </register>
        <register name="BASEADDR" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Descriptor Memory Section Base Address">
          <bitfield name="BASEADDR" caption="Descriptor Memory Base Address" mask="0xFFFFFFFF"/>
        </register>
        <register name="WRBADDR" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Write-Back Memory Section Base Address">
          <bitfield name="WRBADDR" caption="Write-Back Memory Base Address" mask="0xFFFFFFFF"/>
        </register>
        <register-group name="CHANNEL" name-in-module="CHANNEL" offset="0x40" count="32"/>
      </register-group>
      <register-group name="DMAC_DESCRIPTOR" caption="Direct Memory Access Controller" section="hsram" aligned="8">
        <register name="BTCTRL" offset="0x0" rw="RW" size="2" initval="0x0000" caption="Block Transfer Control">
          <bitfield name="VALID" caption="Descriptor Valid" mask="0x1"/>
          <bitfield name="EVOSEL" caption="Block Event Output Selection" mask="0x6" values="DMAC_BTCTRL__EVOSEL"/>
          <bitfield name="BLOCKACT" caption="Block Action" mask="0x18" values="DMAC_BTCTRL__BLOCKACT"/>
          <bitfield name="BEATSIZE" caption="Beat Size" mask="0x300" values="DMAC_BTCTRL__BEATSIZE"/>
          <bitfield name="SRCINC" caption="Source Address Increment Enable" mask="0x400"/>
          <bitfield name="DSTINC" caption="Destination Address Increment Enable" mask="0x800"/>
          <bitfield name="STEPSEL" caption="Step Selection" mask="0x1000" values="DMAC_BTCTRL__STEPSEL"/>
          <bitfield name="STEPSIZE" caption="Address Increment Step Size" mask="0xE000" values="DMAC_BTCTRL__STEPSIZE"/>
        </register>
        <register name="BTCNT" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Block Transfer Count">
          <bitfield name="BTCNT" caption="Block Transfer Count" mask="0xFFFF"/>
        </register>
        <register name="SRCADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Block Transfer Source Address">
          <bitfield name="SRCADDR" caption="Transfer Source Address" mask="0xFFFFFFFF"/>
        </register>
        <register name="DSTADDR" offset="0x8" rw="RW" size="4" caption="Block Transfer Destination Address">
          <mode name="CRC">
            <bitfield name="CHKINIT" caption="CRC Checksum Initial Value" mask="0xFFFFFFFF"/>
          </mode>
          <mode name="DEFAULT_MODE">
            <bitfield name="DSTADDR" caption="Transfer Destination Address" mask="0xFFFFFFFF"/>
          </mode>
        </register>
        <register name="DESCADDR" offset="0xC" rw="RW" size="4" caption="Next Descriptor Address">
          <bitfield name="DESCADDR" caption="Next Descriptor Address" mask="0xFFFFFFFF"/>
        </register>
      </register-group>
      <value-group name="DMAC_BTCTRL__BEATSIZE">
        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
      </value-group>
      <value-group name="DMAC_BTCTRL__BLOCKACT">
        <value name="NOACT" caption="Channel will be disabled if it is the last block transfer in the transaction" value="0x0"/>
        <value name="INT" caption="Channel will be disabled if it is the last block transfer in the transaction and block interrupt" value="0x1"/>
        <value name="SUSPEND" caption="Channel suspend operation is completed" value="0x2"/>
        <value name="BOTH" caption="Both channel suspend operation and block interrupt" value="0x3"/>
      </value-group>
      <value-group name="DMAC_BTCTRL__EVOSEL">
        <value name="DISABLE" caption="Event generation disabled" value="0x0"/>
        <value name="BLOCK" caption="Block event strobe" value="0x1"/>
        <value name="BURST" caption="Burst event strobe" value="0x3"/>
      </value-group>
      <value-group name="DMAC_BTCTRL__STEPSEL">
        <value name="DST" caption="Step size settings apply to the destination address" value="0x0"/>
        <value name="SRC" caption="Step size settings apply to the source address" value="0x1"/>
      </value-group>
      <value-group name="DMAC_BTCTRL__STEPSIZE">
        <value name="X1" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 1" value="0x0"/>
        <value name="X2" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 2" value="0x1"/>
        <value name="X4" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 4" value="0x2"/>
        <value name="X8" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 8" value="0x3"/>
        <value name="X16" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 16" value="0x4"/>
        <value name="X32" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 32" value="0x5"/>
        <value name="X64" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 64" value="0x6"/>
        <value name="X128" caption="Next ADDR = ADDR + (1&lt;&lt;BEATSIZE) * 128" value="0x7"/>
      </value-group>
      <value-group name="DMAC_CRCCTRL__CRCBEATSIZE">
        <value name="BYTE" caption="8-bit bus transfer" value="0x0"/>
        <value name="HWORD" caption="16-bit bus transfer" value="0x1"/>
        <value name="WORD" caption="32-bit bus transfer" value="0x2"/>
      </value-group>
      <value-group name="DMAC_CRCCTRL__CRCMODE">
        <value name="DEFAULT" caption="Default operating mode" value="0"/>
        <value name="CRCMON" caption="Memory CRC monitor operating mode" value="2"/>
        <value name="CRCGEN" caption="Memory CRC generation operating mode" value="3"/>
      </value-group>
      <value-group name="DMAC_CRCCTRL__CRCPOLY">
        <value name="CRC16" caption="CRC-16 (CRC-CCITT)" value="0x0"/>
        <value name="CRC32" caption="CRC32 (IEEE 802.3)" value="0x1"/>
      </value-group>
      <value-group name="DMAC_CRCCTRL__CRCSRC">
        <value name="DISABLE" caption="CRC Disabled" value="0x00"/>
        <value name="IO" caption="I/O interface" value="0x01"/>
      </value-group>
      <value-group name="DMAC_PRICTRL0__QOS0">
        <value name="REGULAR" caption="Regular delivery" value="0"/>
        <value name="SHORTAGE" caption="Bandwidth shortage" value="1"/>
        <value name="SENSITIVE" caption="Latency sensitive" value="2"/>
        <value name="CRITICAL" caption="Latency critical" value="3"/>
      </value-group>
      <value-group name="DMAC_PRICTRL0__QOS1">
        <value name="REGULAR" caption="Regular delivery" value="0"/>
        <value name="SHORTAGE" caption="Bandwidth shortage" value="1"/>
        <value name="SENSITIVE" caption="Latency sensitive" value="2"/>
        <value name="CRITICAL" caption="Latency critical" value="3"/>
      </value-group>
      <value-group name="DMAC_PRICTRL0__QOS2">
        <value name="REGULAR" caption="Regular delivery" value="0"/>
        <value name="SHORTAGE" caption="Bandwidth shortage" value="1"/>
        <value name="SENSITIVE" caption="Latency sensitive" value="2"/>
        <value name="CRITICAL" caption="Latency critical" value="3"/>
      </value-group>
      <value-group name="DMAC_PRICTRL0__QOS3">
        <value name="REGULAR" caption="Regular delivery" value="0"/>
        <value name="SHORTAGE" caption="Bandwidth shortage" value="1"/>
        <value name="SENSITIVE" caption="Latency sensitive" value="2"/>
        <value name="CRITICAL" caption="Latency critical" value="3"/>
      </value-group>
      <value-group name="DMAC_CHCTRLA__BURSTLEN">
        <value name="SINGLE" caption="Single-beat burst length" value="0"/>
        <value name="2BEAT" caption="2-beats burst length" value="1"/>
        <value name="3BEAT" caption="3-beats burst length" value="2"/>
        <value name="4BEAT" caption="4-beats burst length" value="3"/>
        <value name="5BEAT" caption="5-beats burst length" value="4"/>
        <value name="6BEAT" caption="6-beats burst length" value="5"/>
        <value name="7BEAT" caption="7-beats burst length" value="6"/>
        <value name="8BEAT" caption="8-beats burst length" value="7"/>
        <value name="9BEAT" caption="9-beats burst length" value="8"/>
        <value name="10BEAT" caption="10-beats burst length" value="9"/>
        <value name="11BEAT" caption="11-beats burst length" value="10"/>
        <value name="12BEAT" caption="12-beats burst length" value="11"/>
        <value name="13BEAT" caption="13-beats burst length" value="12"/>
        <value name="14BEAT" caption="14-beats burst length" value="13"/>
        <value name="15BEAT" caption="15-beats burst length" value="14"/>
        <value name="16BEAT" caption="16-beats burst length" value="15"/>
      </value-group>
      <value-group name="DMAC_CHCTRLA__THRESHOLD">
        <value name="1BEAT" caption="Destination write starts after each beat source address read" value="0"/>
        <value name="2BEATS" caption="Destination write starts after 2-beats source address read" value="1"/>
        <value name="4BEATS" caption="Destination write starts after 4-beats source address read" value="2"/>
        <value name="8BEATS" caption="Destination write starts after 8-beats source address read" value="3"/>
      </value-group>
      <value-group name="DMAC_CHCTRLA__TRIGACT">
        <value name="BLOCK" caption="One trigger required for each block transfer" value="0"/>
        <value name="BURST" caption="One trigger required for each burst transfer" value="2"/>
        <value name="TRANSACTION" caption="One trigger required for each transaction" value="3"/>
      </value-group>
      <value-group name="DMAC_CHCTRLA__TRIGSRC">
        <value name="DISABLE" caption="Only software/event triggers" value="0"/>
      </value-group>
      <value-group name="DMAC_CHCTRLB__CMD">
        <value name="NOACT" caption="No action" value="0x0"/>
        <value name="SUSPEND" caption="Channel suspend operation" value="0x1"/>
        <value name="RESUME" caption="Channel resume operation" value="0x2"/>
      </value-group>
      <value-group name="DMAC_CHPRILVL__PRILVL">
        <value name="LVL0" caption="Channel Priority Level 0 (Lowest Level)" value="0"/>
        <value name="LVL1" caption="Channel Priority Level 1" value="1"/>
        <value name="LVL2" caption="Channel Priority Level 2" value="2"/>
        <value name="LVL3" caption="Channel Priority Level 3" value="3"/>
        <value name="LVL4" caption="Channel Priority Level 4" value="4"/>
        <value name="LVL5" caption="Channel Priority Level 5" value="5"/>
        <value name="LVL6" caption="Channel Priority Level 6" value="6"/>
        <value name="LVL7" caption="Channel Priority Level 7 (Highest Level)" value="7"/>
      </value-group>
      <value-group name="DMAC_CHEVCTRL__EVACT">
        <value name="NOACT" caption="No action" value="0"/>
        <value name="TRIG" caption="Transfer and periodic transfer trigger" value="1"/>
        <value name="CTRIG" caption="Conditional transfer trigger" value="2"/>
        <value name="CBLOCK" caption="Conditional block transfer" value="3"/>
        <value name="SUSPEND" caption="Channel suspend operation" value="4"/>
        <value name="RESUME" caption="Channel resume operation" value="5"/>
        <value name="SSKIP" caption="Skip next block suspend action" value="6"/>
        <value name="INCPRI" caption="Increase priority" value="7"/>
      </value-group>
      <value-group name="DMAC_CHEVCTRL__EVOMODE">
        <value name="DEFAULT" caption="Block event output selection. Refer to BTCTRL.EVOSEL for available selections." value="0"/>
        <value name="TRIGACT" caption="Ongoing trigger action" value="1"/>
      </value-group>
    </module>
    <module name="DSU" id="U2410" version="1.0.0" caption="Device Service Unit">
      <register-group name="DSU" caption="Device Service Unit">
        <register name="CTRL" offset="0x0" rw="W" size="1" initval="0x00" caption="Control">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="CRC" caption="32-bit Cyclic Redundancy Code" mask="0x4"/>
          <bitfield name="MBIST" caption="Memory built-in self-test" mask="0x8"/>
          <bitfield name="CE" caption="Chip-Erase" mask="0x10"/>
          <bitfield name="ARR" caption="Auxiliary Row Read" mask="0x40"/>
          <bitfield name="SMSA" caption="Start Memory Stream Access" mask="0x80"/>
        </register>
        <register name="STATUSA" offset="0x1" rw="RW" size="1" initval="0x00" caption="Status A">
          <bitfield name="DONE" caption="Done" mask="0x1"/>
          <bitfield name="CRSTEXT" caption="CPU Reset Phase Extension" mask="0x2"/>
          <bitfield name="BERR" caption="Bus Error" mask="0x4"/>
          <bitfield name="FAIL" caption="Failure" mask="0x8"/>
          <bitfield name="PERR" caption="Protection Error" mask="0x10"/>
        </register>
        <register name="STATUSB" offset="0x2" rw="R" size="1" initval="0x00" caption="Status B">
          <bitfield name="PROT" caption="Protected" mask="0x1"/>
          <bitfield name="DBGPRES" caption="Debugger Present" mask="0x2"/>
          <bitfield name="DCCD0" caption="Debug Communication Channel 0 Dirty" mask="0x4"/>
          <bitfield name="DCCD1" caption="Debug Communication Channel 1 Dirty" mask="0x8"/>
          <bitfield name="HPE" caption="Hot-Plugging Enable" mask="0x10"/>
          <bitfield name="CELCK" caption="Chip Erase Locked" mask="0x20"/>
          <bitfield name="TDCCD0" caption="Test Debug Communication Channel 0 Dirty" mask="0x40"/>
          <bitfield name="TDCCD1" caption="Test Debug Communication Channel 1 Dirty" mask="0x80"/>
        </register>
        <register name="ADDR" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Address">
          <bitfield name="AMOD" caption="Access Mode" mask="0x3"/>
          <bitfield name="ADDR" caption="Address" mask="0xFFFFFFFC"/>
        </register>
        <register name="LENGTH" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Length">
          <bitfield name="LENGTH" caption="Length" mask="0xFFFFFFFC"/>
        </register>
        <register name="DATA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Data">
          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
        </register>
        <register name="DCC" offset="0x10" rw="RW" size="4" count="2" initval="0x00000000" caption="Debug Communication Channel n">
          <bitfield name="DATA" caption="Data" mask="0xFFFFFFFF"/>
        </register>
        <register name="DID" offset="0x18" rw="R" size="4" initval="0x60060001" caption="Device Identification">
          <bitfield name="DEVSEL" caption="Device Select" mask="0xFF"/>
          <bitfield name="REVISION" caption="Revision Number" mask="0xF00"/>
          <bitfield name="DIE" caption="Die Number" mask="0xF000"/>
          <bitfield name="SERIES" caption="Series" mask="0x3F0000" values="DSU_DID__SERIES"/>
          <bitfield name="FAMILY" caption="Family" mask="0xF800000" values="DSU_DID__FAMILY"/>
          <bitfield name="PROCESSOR" caption="Processor" mask="0xF0000000" values="DSU_DID__PROCESSOR"/>
        </register>
        <register name="CFG" offset="0x1C" rw="RW" size="4" initval="0x00000002" caption="Configuration">
          <bitfield name="LQOS" caption="Latency Quality Of Service" mask="0x3"/>
          <bitfield name="DCCDMALEVEL" caption="DMA Trigger Level" mask="0xC" values="DSU_CFG__DCCDMALEVEL"/>
          <bitfield name="ETBRAMEN" caption="Trace Control" mask="0x10"/>
        </register>
        <register name="MBCTRL" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="MBIST Control">
          <bitfield name="SWRST" caption="MBIST Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="MBIST Enable" mask="0x2"/>
        </register>
        <register name="MBCONFIG" offset="0x44" rw="RW" size="4" initval="0x00000000" caption="MBIST Configuration">
          <bitfield name="ALGO" caption="MBIST Algorithm" mask="0x1F" values="DSU_MBCONFIG__ALGO"/>
          <bitfield name="DEFRDMARGIN" caption="Force Default Read Margin" mask="0x40"/>
          <bitfield name="DBG" caption="Enable Debug Mode" mask="0x80"/>
        </register>
        <register name="MBWORD" offset="0x48" rw="RW" size="4" initval="0x00000000" caption="MBIST Background Word">
          <bitfield name="DATA" caption="MBIST Background Word" mask="0xFFFFFFFF"/>
        </register>
        <register name="MBGSTAT" offset="0x4C" rw="RW" size="4" initval="0x00000000" caption="MBIST Global Status">
          <bitfield name="ALLDONE" caption="MBIST Completed" mask="0x1"/>
          <bitfield name="FAILED" caption="MBIST Failed" mask="0x2"/>
          <bitfield name="ERRINFO" caption="MBIST Error Info Present" mask="0x4"/>
          <bitfield name="CONFIGURED" caption="MBIST Configuration Sent" mask="0x8"/>
        </register>
        <register name="MBDFAIL" offset="0x50" rw="R" size="4" initval="0x00000000" caption="MBIST Fail Data">
          <bitfield name="DATA" caption="Error Data Read" mask="0xFFFFFFFF"/>
        </register>
        <register name="MBDEXP" offset="0x54" rw="R" size="4" initval="0x00000000" caption="MBIST Expected Data">
          <bitfield name="DATA" caption="Expected Data" mask="0xFFFFFFFF"/>
        </register>
        <register name="MBAFAIL" offset="0x58" rw="R" size="4" initval="0x00000000" caption="MBIST Fail Address">
          <bitfield name="ADDR" caption="Error Address" mask="0x3FFF"/>
        </register>
        <register name="MBCONTEXT" offset="0x5C" rw="R" size="4" initval="0x00000000" caption="MBIST Fail Context">
          <bitfield name="SUBSTEP" caption="Algorithm Sub-step" mask="0x1F" values="DSU_MBCONTEXT__SUBSTEP"/>
          <bitfield name="STEP" caption="Algorithm Step" mask="0x3E0" values="DSU_MBCONTEXT__STEP"/>
          <bitfield name="PORT" caption="DPRAM Port Index" mask="0x400"/>
        </register>
        <register name="MBENABLE0" offset="0x60" rw="RW" size="4" initval="0x00000000" caption="MBIST Memory Enable 0">
          <bitfield name="ENABLE0" caption="Memory 0 MBIST Enable" mask="0x1"/>
          <bitfield name="ENABLE1" caption="Memory 1 MBIST Enable" mask="0x2"/>
          <bitfield name="ENABLE2" caption="Memory 2 MBIST Enable" mask="0x4"/>
          <bitfield name="ENABLE3" caption="Memory 3 MBIST Enable" mask="0x8"/>
          <bitfield name="ENABLE4" caption="Memory 4 MBIST Enable" mask="0x10"/>
          <bitfield name="ENABLE5" caption="Memory 5 MBIST Enable" mask="0x20"/>
          <bitfield name="ENABLE6" caption="Memory 6 MBIST Enable" mask="0x40"/>
          <bitfield name="ENABLE7" caption="Memory 7 MBIST Enable" mask="0x80"/>
          <bitfield name="ENABLE8" caption="Memory 8 MBIST Enable" mask="0x100"/>
          <bitfield name="ENABLE9" caption="Memory 9 MBIST Enable" mask="0x200"/>
          <bitfield name="ENABLE10" caption="Memory 10 MBIST Enable" mask="0x400"/>
          <bitfield name="ENABLE11" caption="Memory 11 MBIST Enable" mask="0x800"/>
          <bitfield name="ENABLE12" caption="Memory 12 MBIST Enable" mask="0x1000"/>
          <bitfield name="ENABLE13" caption="Memory 13 MBIST Enable" mask="0x2000"/>
          <bitfield name="ENABLE14" caption="Memory 14 MBIST Enable" mask="0x4000"/>
          <bitfield name="ENABLE15" caption="Memory 15 MBIST Enable" mask="0x8000"/>
          <bitfield name="ENABLE16" caption="Memory 16 MBIST Enable" mask="0x10000"/>
          <bitfield name="ENABLE17" caption="Memory 17 MBIST Enable" mask="0x20000"/>
          <bitfield name="ENABLE18" caption="Memory 18 MBIST Enable" mask="0x40000"/>
          <bitfield name="ENABLE19" caption="Memory 19 MBIST Enable" mask="0x80000"/>
          <bitfield name="ENABLE20" caption="Memory 20 MBIST Enable" mask="0x100000"/>
          <bitfield name="ENABLE21" caption="Memory 21 MBIST Enable" mask="0x200000"/>
          <bitfield name="ENABLE22" caption="Memory 22 MBIST Enable" mask="0x400000"/>
          <bitfield name="ENABLE23" caption="Memory 23 MBIST Enable" mask="0x800000"/>
          <bitfield name="ENABLE24" caption="Memory 24 MBIST Enable" mask="0x1000000"/>
          <bitfield name="ENABLE25" caption="Memory 25 MBIST Enable" mask="0x2000000"/>
          <bitfield name="ENABLE26" caption="Memory 26 MBIST Enable" mask="0x4000000"/>
          <bitfield name="ENABLE27" caption="Memory 27 MBIST Enable" mask="0x8000000"/>
          <bitfield name="ENABLE28" caption="Memory 28 MBIST Enable" mask="0x10000000"/>
        </register>
        <register name="MBBUSY0" offset="0x68" rw="R" size="4" initval="0x00000000" caption="MBIST Memory Busy 0">
          <bitfield name="BUSY0" caption="Memory 0 BIST Busy" mask="0x1"/>
          <bitfield name="BUSY1" caption="Memory 1 BIST Busy" mask="0x2"/>
          <bitfield name="BUSY2" caption="Memory 2 BIST Busy" mask="0x4"/>
          <bitfield name="BUSY3" caption="Memory 3 BIST Busy" mask="0x8"/>
          <bitfield name="BUSY4" caption="Memory 4 BIST Busy" mask="0x10"/>
          <bitfield name="BUSY5" caption="Memory 5 BIST Busy" mask="0x20"/>
          <bitfield name="BUSY6" caption="Memory 6 BIST Busy" mask="0x40"/>
          <bitfield name="BUSY7" caption="Memory 7 BIST Busy" mask="0x80"/>
          <bitfield name="BUSY8" caption="Memory 8 BIST Busy" mask="0x100"/>
          <bitfield name="BUSY9" caption="Memory 9 BIST Busy" mask="0x200"/>
          <bitfield name="BUSY10" caption="Memory 10 BIST Busy" mask="0x400"/>
          <bitfield name="BUSY11" caption="Memory 11 BIST Busy" mask="0x800"/>
          <bitfield name="BUSY12" caption="Memory 12 BIST Busy" mask="0x1000"/>
          <bitfield name="BUSY13" caption="Memory 13 BIST Busy" mask="0x2000"/>
          <bitfield name="BUSY14" caption="Memory 14 BIST Busy" mask="0x4000"/>
          <bitfield name="BUSY15" caption="Memory 15 BIST Busy" mask="0x8000"/>
          <bitfield name="BUSY16" caption="Memory 16 BIST Busy" mask="0x10000"/>
          <bitfield name="BUSY17" caption="Memory 17 BIST Busy" mask="0x20000"/>
          <bitfield name="BUSY18" caption="Memory 18 BIST Busy" mask="0x40000"/>
          <bitfield name="BUSY19" caption="Memory 19 BIST Busy" mask="0x80000"/>
          <bitfield name="BUSY20" caption="Memory 20 BIST Busy" mask="0x100000"/>
          <bitfield name="BUSY21" caption="Memory 21 BIST Busy" mask="0x200000"/>
          <bitfield name="BUSY22" caption="Memory 22 BIST Busy" mask="0x400000"/>
          <bitfield name="BUSY23" caption="Memory 23 BIST Busy" mask="0x800000"/>
          <bitfield name="BUSY24" caption="Memory 24 BIST Busy" mask="0x1000000"/>
          <bitfield name="BUSY25" caption="Memory 25 BIST Busy" mask="0x2000000"/>
          <bitfield name="BUSY26" caption="Memory 26 BIST Busy" mask="0x4000000"/>
          <bitfield name="BUSY27" caption="Memory 27 BIST Busy" mask="0x8000000"/>
          <bitfield name="BUSY28" caption="Memory 28 BIST Busy" mask="0x10000000"/>
        </register>
        <register name="MBSTATUS0" offset="0x70" rw="RW" size="4" initval="0x00000000" caption="MBIST Memory Status 0">
          <bitfield name="STATUS0" caption="Memory 0 MBIST Status" mask="0x1"/>
          <bitfield name="STATUS1" caption="Memory 1 MBIST Status" mask="0x2"/>
          <bitfield name="STATUS2" caption="Memory 2 MBIST Status" mask="0x4"/>
          <bitfield name="STATUS3" caption="Memory 3 MBIST Status" mask="0x8"/>
          <bitfield name="STATUS4" caption="Memory 4 MBIST Status" mask="0x10"/>
          <bitfield name="STATUS5" caption="Memory 5 MBIST Status" mask="0x20"/>
          <bitfield name="STATUS6" caption="Memory 6 MBIST Status" mask="0x40"/>
          <bitfield name="STATUS7" caption="Memory 7 MBIST Status" mask="0x80"/>
          <bitfield name="STATUS8" caption="Memory 8 MBIST Status" mask="0x100"/>
          <bitfield name="STATUS9" caption="Memory 9 MBIST Status" mask="0x200"/>
          <bitfield name="STATUS10" caption="Memory 10 MBIST Status" mask="0x400"/>
          <bitfield name="STATUS11" caption="Memory 11 MBIST Status" mask="0x800"/>
          <bitfield name="STATUS12" caption="Memory 12 MBIST Status" mask="0x1000"/>
          <bitfield name="STATUS13" caption="Memory 13 MBIST Status" mask="0x2000"/>
          <bitfield name="STATUS14" caption="Memory 14 MBIST Status" mask="0x4000"/>
          <bitfield name="STATUS15" caption="Memory 15 MBIST Status" mask="0x8000"/>
          <bitfield name="STATUS16" caption="Memory 16 MBIST Status" mask="0x10000"/>
          <bitfield name="STATUS17" caption="Memory 17 MBIST Status" mask="0x20000"/>
          <bitfield name="STATUS18" caption="Memory 18 MBIST Status" mask="0x40000"/>
          <bitfield name="STATUS19" caption="Memory 19 MBIST Status" mask="0x80000"/>
          <bitfield name="STATUS20" caption="Memory 20 MBIST Status" mask="0x100000"/>
          <bitfield name="STATUS21" caption="Memory 21 MBIST Status" mask="0x200000"/>
          <bitfield name="STATUS22" caption="Memory 22 MBIST Status" mask="0x400000"/>
          <bitfield name="STATUS23" caption="Memory 23 MBIST Status" mask="0x800000"/>
          <bitfield name="STATUS24" caption="Memory 24 MBIST Status" mask="0x1000000"/>
          <bitfield name="STATUS25" caption="Memory 25 MBIST Status" mask="0x2000000"/>
          <bitfield name="STATUS26" caption="Memory 26 MBIST Status" mask="0x4000000"/>
          <bitfield name="STATUS27" caption="Memory 27 MBIST Status" mask="0x8000000"/>
          <bitfield name="STATUS28" caption="Memory 28 MBIST Status" mask="0x10000000"/>
        </register>
        <register name="DCFG" offset="0xF0" rw="RW" size="4" count="2" initval="0x00000000" caption="Device Configuration">
          <bitfield name="DCFG" caption="Device Configuration" mask="0xFFFFFFFF"/>
        </register>
        <register name="ENTRY0" offset="0x1000" rw="R" size="4" initval="0x9F0FC002" caption="CoreSight ROM Table Entry 0">
          <bitfield name="EPRES" caption="Entry Present" mask="0x1"/>
          <bitfield name="FMT" caption="Format" mask="0x2"/>
          <bitfield name="ADDOFF" caption="Address Offset" mask="0xFFFFF000"/>
        </register>
        <register name="ENTRY1" offset="0x1004" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Entry 1">
        </register>
        <register name="END" offset="0x1008" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table End">
          <bitfield name="END" caption="End Marker" mask="0xFFFFFFFF"/>
        </register>
        <register name="MEMTYPE" offset="0x1FCC" rw="R" size="4" initval="0x00000000" caption="CoreSight ROM Table Memory Type">
          <bitfield name="SMEMP" caption="System Memory Present" mask="0x1"/>
        </register>
        <register name="PID4" offset="0x1FD0" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 4">
          <bitfield name="JEPCC" caption="JEP-106 Continuation Code" mask="0xF"/>
          <bitfield name="FKBC" caption="4KB count" mask="0xF0"/>
        </register>
        <register name="PID5" offset="0x1FD4" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 5">
        </register>
        <register name="PID6" offset="0x1FD8" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 6">
        </register>
        <register name="PID7" offset="0x1FDC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 7">
        </register>
        <register name="PID0" offset="0x1FE0" rw="R" size="4" initval="0x000000D0" caption="Peripheral Identification 0">
          <bitfield name="PARTNBL" caption="Part Number Low" mask="0xFF"/>
        </register>
        <register name="PID1" offset="0x1FE4" rw="R" size="4" initval="0x000000FC" caption="Peripheral Identification 1">
          <bitfield name="PARTNBH" caption="Part Number High" mask="0xF"/>
          <bitfield name="JEPIDCL" caption="Low part of the JEP-106 Identity Code" mask="0xF0"/>
        </register>
        <register name="PID2" offset="0x1FE8" rw="R" size="4" initval="0x00000009" caption="Peripheral Identification 2">
          <bitfield name="JEPIDCH" caption="JEP-106 Identity Code High" mask="0x7"/>
          <bitfield name="JEPU" caption="JEP-106 Identity Code is used" mask="0x8"/>
          <bitfield name="REVISION" caption="Revision Number" mask="0xF0"/>
        </register>
        <register name="PID3" offset="0x1FEC" rw="R" size="4" initval="0x00000000" caption="Peripheral Identification 3">
          <bitfield name="CUSMOD" caption="ARM CUSMOD" mask="0xF"/>
          <bitfield name="REVAND" caption="Revision Number" mask="0xF0"/>
        </register>
        <register name="CID0" offset="0x1FF0" rw="R" size="4" initval="0x0000000D" caption="Component Identification 0">
          <bitfield name="PREAMBLEB0" caption="Preamble Byte 0" mask="0xFF"/>
        </register>
        <register name="CID1" offset="0x1FF4" rw="R" size="4" initval="0x00000010" caption="Component Identification 1">
          <bitfield name="PREAMBLE" caption="Preamble" mask="0xF"/>
          <bitfield name="CCLASS" caption="Component Class" mask="0xF0"/>
        </register>
        <register name="CID2" offset="0x1FF8" rw="R" size="4" initval="0x00000005" caption="Component Identification 2">
          <bitfield name="PREAMBLEB2" caption="Preamble Byte 2" mask="0xFF"/>
        </register>
        <register name="CID3" offset="0x1FFC" rw="R" size="4" initval="0x000000B1" caption="Component Identification 3">
          <bitfield name="PREAMBLEB3" caption="Preamble Byte 3" mask="0xFF"/>
        </register>
      </register-group>
      <value-group name="DSU_DID__FAMILY">
        <value name="0" caption="General purpose microcontroller" value="0"/>
        <value name="1" caption="PicoPower" value="1"/>
      </value-group>
      <value-group name="DSU_DID__PROCESSOR">
        <value name="CM0P" caption="Cortex-M0+" value="0x1"/>
        <value name="CM23" caption="Cortex-M23" value="0x2"/>
        <value name="CM3" caption="Cortex-M3" value="0x3"/>
        <value name="CM4" caption="Cortex-M4" value="0x5"/>
        <value name="CM4F" caption="Cortex-M4 with FPU" value="0x6"/>
        <value name="CM33" caption="Cortex-M33" value="0x7"/>
      </value-group>
      <value-group name="DSU_DID__SERIES">
        <value name="0" caption="Cortex-M0+ processor, basic feature set" value="0"/>
        <value name="1" caption="Cortex-M0+ processor, USB" value="1"/>
      </value-group>
      <value-group name="DSU_CFG__DCCDMALEVEL">
        <value name="EMPTY" caption="Trigger rises when DCC is empty" value="0"/>
        <value name="FULL" caption="Trigger rises when DCC is full" value="1"/>
      </value-group>
      <value-group name="DSU_MBCONFIG__ALGO">
        <value name="MEMCLEAR" caption="Memory Clear (1n)" value="0x00"/>
        <value name="VERIFY" caption="Memory Verify (1n)" value="0x01"/>
        <value name="CLEARVER" caption="Memory Clear and Verify (2n)" value="0x02"/>
        <value name="ADDR_DEC" caption="Address Decoder (2n)" value="0x03"/>
        <value name="MARCH_LR" caption="March LR (14n)" value="0x04"/>
        <value name="MARCH_SR" caption="March SR (14n)" value="0x05"/>
        <value name="MARCH_SS" caption="March SS (22n)" value="0x06"/>
        <value name="CRC_UP" caption="CRC increasing address (1n)" value="0x08"/>
        <value name="CRC_DOWN" caption="CRC decreasing address (1n)" value="0x09"/>
      </value-group>
      <value-group name="DSU_MBCONTEXT__STEP">
        <value name="DOWN_R0W1" value="0x2"/>
        <value name="UP_R1W0R0W1" value="0x3"/>
        <value name="UP_R1W0" value="0x4"/>
        <value name="UP_R0W1R1W0" value="0x5"/>
        <value name="UP_R0" value="0x6"/>
        <value name="UP_R0R0W0R0W1" value="0x7"/>
        <value name="UP_R1R1W1R1W0" value="0x8"/>
        <value name="DOWN_R0R0W0R0W1" value="0x9"/>
        <value name="DOWN_R1R1W1R1W0" value="0xA"/>
        <value name="UP_R0R0" value="0xC"/>
        <value name="DOWN_R1W0R0W1" value="0xE"/>
        <value name="DOWN_R1R1" value="0xF"/>
      </value-group>
      <value-group name="DSU_MBCONTEXT__SUBSTEP">
        <value name="R0_1" value="0x1"/>
        <value name="R1_1" value="0x3"/>
        <value name="R0_2" value="0x5"/>
        <value name="R1_2" value="0x7"/>
        <value name="R0_3" value="0x9"/>
        <value name="R1_3" value="0xB"/>
      </value-group>
    </module>
    <module name="EIC" id="U2254" version="3.0.0" caption="External Interrupt Controller">
      <register-group name="EIC" caption="External Interrupt Controller">
        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="CKSEL" caption="Clock Selection" mask="0x10"/>
        </register>
        <register name="NMICTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="Non-Maskable Interrupt Control">
          <bitfield name="NMISENSE" caption="Non-Maskable Interrupt Sense Configuration" mask="0x7" values="EIC_NMICTRL__NMISENSE"/>
          <bitfield name="NMIFILTEN" caption="Non-Maskable Interrupt Filter Enable" mask="0x8"/>
          <bitfield name="NMIASYNCH" caption="Asynchronous Edge Detection Mode" mask="0x10"/>
        </register>
        <register name="NMIFLAG" offset="0x2" rw="RW" size="2" atomic-op="clear:NMIFLAG" initval="0x0000" caption="Non-Maskable Interrupt Flag Status and Clear">
          <bitfield name="NMI" caption="Non-Maskable Interrupt" mask="0x1"/>
        </register>
        <register name="SYNCBUSY" offset="0x4" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
          <bitfield name="SWRST" caption="Software Reset Synchronization Busy Status" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable Synchronization Busy Status" mask="0x2"/>
        </register>
        <register name="EVCTRL" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Event Control">
          <bitfield name="EXTINTEO" caption="External Interrupt Event Output Enable" mask="0xFFFF"/>
        </register>
        <register name="INTENCLR" offset="0xC" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
          <bitfield name="EXTINT" caption="External Interrupt Enable" mask="0xFFFF"/>
        </register>
        <register name="INTENSET" offset="0x10" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
          <bitfield name="EXTINT" caption="External Interrupt Enable" mask="0xFFFF"/>
        </register>
        <register name="INTFLAG" offset="0x14" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
          <bitfield name="EXTINT" caption="External Interrupt" mask="0xFFFF"/>
        </register>
        <register name="ASYNCH" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="External Interrupt Asynchronous Mode">
          <bitfield name="ASYNCH" caption="Asynchronous Edge Detection Mode" mask="0xFFFF"/>
        </register>
        <register name="CONFIG" offset="0x1C" rw="RW" size="4" count="2" initval="0x00000000" caption="External Interrupt Sense Configuration">
          <bitfield name="SENSE0" caption="Input Sense Configuration 0" mask="0x7" values="EIC_CONFIG__SENSE0"/>
          <bitfield name="FILTEN0" caption="Filter Enable 0" mask="0x8"/>
          <bitfield name="SENSE1" caption="Input Sense Configuration 1" mask="0x70" values="EIC_CONFIG__SENSE1"/>
          <bitfield name="FILTEN1" caption="Filter Enable 1" mask="0x80"/>
          <bitfield name="SENSE2" caption="Input Sense Configuration 2" mask="0x700" values="EIC_CONFIG__SENSE2"/>
          <bitfield name="FILTEN2" caption="Filter Enable 2" mask="0x800"/>
          <bitfield name="SENSE3" caption="Input Sense Configuration 3" mask="0x7000" values="EIC_CONFIG__SENSE3"/>
          <bitfield name="FILTEN3" caption="Filter Enable 3" mask="0x8000"/>
          <bitfield name="SENSE4" caption="Input Sense Configuration 4" mask="0x70000" values="EIC_CONFIG__SENSE4"/>
          <bitfield name="FILTEN4" caption="Filter Enable 4" mask="0x80000"/>
          <bitfield name="SENSE5" caption="Input Sense Configuration 5" mask="0x700000" values="EIC_CONFIG__SENSE5"/>
          <bitfield name="FILTEN5" caption="Filter Enable 5" mask="0x800000"/>
          <bitfield name="SENSE6" caption="Input Sense Configuration 6" mask="0x7000000" values="EIC_CONFIG__SENSE6"/>
          <bitfield name="FILTEN6" caption="Filter Enable 6" mask="0x8000000"/>
          <bitfield name="SENSE7" caption="Input Sense Configuration 7" mask="0x70000000" values="EIC_CONFIG__SENSE7"/>
          <bitfield name="FILTEN7" caption="Filter Enable 7" mask="0x80000000"/>
        </register>
        <register name="DEBOUNCEN" offset="0x30" rw="RW" size="4" initval="0x00000000" caption="Debouncer Enable">
          <bitfield name="DEBOUNCEN" caption="Debouncer Enable" mask="0xFFFF"/>
        </register>
        <register name="DPRESCALER" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Debouncer Prescaler">
          <bitfield name="PRESCALER0" caption="Debouncer Prescaler" mask="0x7"/>
          <bitfield name="PRESCALER1" caption="Debouncer Prescaler" mask="0x70"/>
          <bitfield name="STATES0" caption="Debouncer number of states" mask="0x8"/>
          <bitfield name="STATES1" caption="Debouncer number of states" mask="0x80"/>
          <bitfield name="TICKON" caption="Pin Sampler frequency selection" mask="0x10000"/>
        </register>
        <register name="PINSTATE" offset="0x38" rw="R" size="4" initval="0x00000000" caption="Pin State">
          <bitfield name="PINSTATE" caption="Pin State" mask="0xFFFF"/>
        </register>
      </register-group>
      <value-group name="EIC_NMICTRL__NMISENSE">
        <value name="NONE" caption="No detection" value="0"/>
        <value name="RISE" caption="Rising-edge detection" value="1"/>
        <value name="FALL" caption="Falling-edge detection" value="2"/>
        <value name="BOTH" caption="Both-edges detection" value="3"/>
        <value name="HIGH" caption="High-level detection" value="4"/>
        <value name="LOW" caption="Low-level detection" value="5"/>
      </value-group>
      <value-group name="EIC_CONFIG__SENSE0">
        <value name="NONE" caption="No detection" value="0"/>
        <value name="RISE" caption="Rising edge detection" value="1"/>
        <value name="FALL" caption="Falling edge detection" value="2"/>
        <value name="BOTH" caption="Both edges detection" value="3"/>
        <value name="HIGH" caption="High level detection" value="4"/>
        <value name="LOW" caption="Low level detection" value="5"/>
      </value-group>
      <value-group name="EIC_CONFIG__SENSE1">
        <value name="NONE" caption="No detection" value="0"/>
        <value name="RISE" caption="Rising edge detection" value="1"/>
        <value name="FALL" caption="Falling edge detection" value="2"/>
        <value name="BOTH" caption="Both edges detection" value="3"/>
        <value name="HIGH" caption="High level detection" value="4"/>
        <value name="LOW" caption="Low level detection" value="5"/>
      </value-group>
      <value-group name="EIC_CONFIG__SENSE2">
        <value name="NONE" caption="No detection" value="0"/>
        <value name="RISE" caption="Rising edge detection" value="1"/>
        <value name="FALL" caption="Falling edge detection" value="2"/>
        <value name="BOTH" caption="Both edges detection" value="3"/>
        <value name="HIGH" caption="High level detection" value="4"/>
        <value name="LOW" caption="Low level detection" value="5"/>
      </value-group>
      <value-group name="EIC_CONFIG__SENSE3">
        <value name="NONE" caption="No detection" value="0"/>
        <value name="RISE" caption="Rising edge detection" value="1"/>
        <value name="FALL" caption="Falling edge detection" value="2"/>
        <value name="BOTH" caption="Both edges detection" value="3"/>
        <value name="HIGH" caption="High level detection" value="4"/>
        <value name="LOW" caption="Low level detection" value="5"/>
      </value-group>
      <value-group name="EIC_CONFIG__SENSE4">
        <value name="NONE" caption="No detection" value="0"/>
        <value name="RISE" caption="Rising edge detection" value="1"/>
        <value name="FALL" caption="Falling edge detection" value="2"/>
        <value name="BOTH" caption="Both edges detection" value="3"/>
        <value name="HIGH" caption="High level detection" value="4"/>
        <value name="LOW" caption="Low level detection" value="5"/>
      </value-group>
      <value-group name="EIC_CONFIG__SENSE5">
        <value name="NONE" caption="No detection" value="0"/>
        <value name="RISE" caption="Rising edge detection" value="1"/>
        <value name="FALL" caption="Falling edge detection" value="2"/>
        <value name="BOTH" caption="Both edges detection" value="3"/>
        <value name="HIGH" caption="High level detection" value="4"/>
        <value name="LOW" caption="Low level detection" value="5"/>
      </value-group>
      <value-group name="EIC_CONFIG__SENSE6">
        <value name="NONE" caption="No detection" value="0"/>
        <value name="RISE" caption="Rising edge detection" value="1"/>
        <value name="FALL" caption="Falling edge detection" value="2"/>
        <value name="BOTH" caption="Both edges detection" value="3"/>
        <value name="HIGH" caption="High level detection" value="4"/>
        <value name="LOW" caption="Low level detection" value="5"/>
      </value-group>
      <value-group name="EIC_CONFIG__SENSE7">
        <value name="NONE" caption="No detection" value="0"/>
        <value name="RISE" caption="Rising edge detection" value="1"/>
        <value name="FALL" caption="Falling edge detection" value="2"/>
        <value name="BOTH" caption="Both edges detection" value="3"/>
        <value name="HIGH" caption="High level detection" value="4"/>
        <value name="LOW" caption="Low level detection" value="5"/>
      </value-group>
    </module>
    <module name="EVSYS" id="U2504" version="1.0.0" caption="Event System Interface">
      <register-group name="CHANNEL" size="0x8">
        <register name="CHANNEL" offset="0x0" rw="RW" size="4" initval="0x00008000" caption="Channel n Control">
          <bitfield name="EVGEN" caption="Event Generator Selection" mask="0x7F"/>
          <bitfield name="PATH" caption="Path Selection" mask="0x300" values="EVSYS_CHANNEL__PATH"/>
          <bitfield name="EDGSEL" caption="Edge Detection Selection" mask="0xC00" values="EVSYS_CHANNEL__EDGSEL"/>
          <bitfield name="RUNSTDBY" caption="Run in standby" mask="0x4000"/>
          <bitfield name="ONDEMAND" caption="Generic Clock On Demand" mask="0x8000"/>
        </register>
        <register name="CHINTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:CHINTENCLR" initval="0x00" caption="Channel n Interrupt Enable Clear">
          <bitfield name="OVR" caption="Channel Overrun Interrupt Disable" mask="0x1"/>
          <bitfield name="EVD" caption="Channel Event Detected Interrupt Disable" mask="0x2"/>
        </register>
        <register name="CHINTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:CHINTENSET" initval="0x00" caption="Channel n Interrupt Enable Set">
          <bitfield name="OVR" caption="Channel Overrun Interrupt Enable" mask="0x1"/>
          <bitfield name="EVD" caption="Channel Event Detected Interrupt Enable" mask="0x2"/>
        </register>
        <register name="CHINTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:CHINTFLAG" initval="0x00" caption="Channel n Interrupt Flag Status and Clear">
          <bitfield name="OVR" caption="Channel Overrun" mask="0x1"/>
          <bitfield name="EVD" caption="Channel Event Detected" mask="0x2"/>
        </register>
        <register name="CHSTATUS" offset="0x7" rw="R" size="1" initval="0x01" caption="Channel n Status">
          <bitfield name="RDYUSR" caption="Ready User" mask="0x1"/>
          <bitfield name="BUSYCH" caption="Busy Channel" mask="0x2"/>
        </register>
      </register-group>
      <register-group name="EVSYS" caption="Event System Interface">
        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
        </register>
        <register name="SWEVT" offset="0x4" rw="W" size="4" initval="0x00000000" caption="Software Event">
          <bitfield name="CHANNEL0" caption="Channel 0 Software Selection" mask="0x1"/>
          <bitfield name="CHANNEL1" caption="Channel 1 Software Selection" mask="0x2"/>
          <bitfield name="CHANNEL2" caption="Channel 2 Software Selection" mask="0x4"/>
          <bitfield name="CHANNEL3" caption="Channel 3 Software Selection" mask="0x8"/>
          <bitfield name="CHANNEL4" caption="Channel 4 Software Selection" mask="0x10"/>
          <bitfield name="CHANNEL5" caption="Channel 5 Software Selection" mask="0x20"/>
          <bitfield name="CHANNEL6" caption="Channel 6 Software Selection" mask="0x40"/>
          <bitfield name="CHANNEL7" caption="Channel 7 Software Selection" mask="0x80"/>
          <bitfield name="CHANNEL8" caption="Channel 8 Software Selection" mask="0x100"/>
          <bitfield name="CHANNEL9" caption="Channel 9 Software Selection" mask="0x200"/>
          <bitfield name="CHANNEL10" caption="Channel 10 Software Selection" mask="0x400"/>
          <bitfield name="CHANNEL11" caption="Channel 11 Software Selection" mask="0x800"/>
          <bitfield name="CHANNEL12" caption="Channel 12 Software Selection" mask="0x1000"/>
          <bitfield name="CHANNEL13" caption="Channel 13 Software Selection" mask="0x2000"/>
          <bitfield name="CHANNEL14" caption="Channel 14 Software Selection" mask="0x4000"/>
          <bitfield name="CHANNEL15" caption="Channel 15 Software Selection" mask="0x8000"/>
          <bitfield name="CHANNEL16" caption="Channel 16 Software Selection" mask="0x10000"/>
          <bitfield name="CHANNEL17" caption="Channel 17 Software Selection" mask="0x20000"/>
          <bitfield name="CHANNEL18" caption="Channel 18 Software Selection" mask="0x40000"/>
          <bitfield name="CHANNEL19" caption="Channel 19 Software Selection" mask="0x80000"/>
          <bitfield name="CHANNEL20" caption="Channel 20 Software Selection" mask="0x100000"/>
          <bitfield name="CHANNEL21" caption="Channel 21 Software Selection" mask="0x200000"/>
          <bitfield name="CHANNEL22" caption="Channel 22 Software Selection" mask="0x400000"/>
          <bitfield name="CHANNEL23" caption="Channel 23 Software Selection" mask="0x800000"/>
          <bitfield name="CHANNEL24" caption="Channel 24 Software Selection" mask="0x1000000"/>
          <bitfield name="CHANNEL25" caption="Channel 25 Software Selection" mask="0x2000000"/>
          <bitfield name="CHANNEL26" caption="Channel 26 Software Selection" mask="0x4000000"/>
          <bitfield name="CHANNEL27" caption="Channel 27 Software Selection" mask="0x8000000"/>
          <bitfield name="CHANNEL28" caption="Channel 28 Software Selection" mask="0x10000000"/>
          <bitfield name="CHANNEL29" caption="Channel 29 Software Selection" mask="0x20000000"/>
          <bitfield name="CHANNEL30" caption="Channel 30 Software Selection" mask="0x40000000"/>
          <bitfield name="CHANNEL31" caption="Channel 31 Software Selection" mask="0x80000000"/>
        </register>
        <register name="PRICTRL" offset="0x8" rw="RW" size="1" initval="0x00" caption="Priority Control">
          <bitfield name="PRI" caption="Channel Priority Number" mask="0xF"/>
          <bitfield name="RREN" caption="Round-Robin Scheduling Enable" mask="0x80"/>
        </register>
        <register name="INTPEND" offset="0x10" rw="RW" size="2" initval="0x4000" caption="Channel Pending Interrupt">
          <bitfield name="ID" caption="Channel ID" mask="0xF"/>
          <bitfield name="OVR" caption="Channel Overrun" mask="0x100"/>
          <bitfield name="EVD" caption="Channel Event Detected" mask="0x200"/>
          <bitfield name="READY" caption="Ready" mask="0x4000"/>
          <bitfield name="BUSY" caption="Busy" mask="0x8000"/>
        </register>
        <register name="INTSTATUS" offset="0x14" rw="R" size="4" initval="0x00000000" caption="Interrupt Status">
          <bitfield name="CHINT0" caption="Channel 0 Pending Interrupt" mask="0x1"/>
          <bitfield name="CHINT1" caption="Channel 1 Pending Interrupt" mask="0x2"/>
          <bitfield name="CHINT2" caption="Channel 2 Pending Interrupt" mask="0x4"/>
          <bitfield name="CHINT3" caption="Channel 3 Pending Interrupt" mask="0x8"/>
          <bitfield name="CHINT4" caption="Channel 4 Pending Interrupt" mask="0x10"/>
          <bitfield name="CHINT5" caption="Channel 5 Pending Interrupt" mask="0x20"/>
          <bitfield name="CHINT6" caption="Channel 6 Pending Interrupt" mask="0x40"/>
          <bitfield name="CHINT7" caption="Channel 7 Pending Interrupt" mask="0x80"/>
          <bitfield name="CHINT8" caption="Channel 8 Pending Interrupt" mask="0x100"/>
          <bitfield name="CHINT9" caption="Channel 9 Pending Interrupt" mask="0x200"/>
          <bitfield name="CHINT10" caption="Channel 10 Pending Interrupt" mask="0x400"/>
          <bitfield name="CHINT11" caption="Channel 11 Pending Interrupt" mask="0x800"/>
        </register>
        <register name="BUSYCH" offset="0x18" rw="R" size="4" initval="0x00000000" caption="Busy Channels">
          <bitfield name="BUSYCH0" caption="Busy Channel 0" mask="0x1"/>
          <bitfield name="BUSYCH1" caption="Busy Channel 1" mask="0x2"/>
          <bitfield name="BUSYCH2" caption="Busy Channel 2" mask="0x4"/>
          <bitfield name="BUSYCH3" caption="Busy Channel 3" mask="0x8"/>
          <bitfield name="BUSYCH4" caption="Busy Channel 4" mask="0x10"/>
          <bitfield name="BUSYCH5" caption="Busy Channel 5" mask="0x20"/>
          <bitfield name="BUSYCH6" caption="Busy Channel 6" mask="0x40"/>
          <bitfield name="BUSYCH7" caption="Busy Channel 7" mask="0x80"/>
          <bitfield name="BUSYCH8" caption="Busy Channel 8" mask="0x100"/>
          <bitfield name="BUSYCH9" caption="Busy Channel 9" mask="0x200"/>
          <bitfield name="BUSYCH10" caption="Busy Channel 10" mask="0x400"/>
          <bitfield name="BUSYCH11" caption="Busy Channel 11" mask="0x800"/>
        </register>
        <register name="READYUSR" offset="0x1C" rw="R" size="4" initval="0xFFFFFFFF" caption="Ready Users">
          <bitfield name="READYUSR0" caption="Ready User for Channel 0" mask="0x1"/>
          <bitfield name="READYUSR1" caption="Ready User for Channel 1" mask="0x2"/>
          <bitfield name="READYUSR2" caption="Ready User for Channel 2" mask="0x4"/>
          <bitfield name="READYUSR3" caption="Ready User for Channel 3" mask="0x8"/>
          <bitfield name="READYUSR4" caption="Ready User for Channel 4" mask="0x10"/>
          <bitfield name="READYUSR5" caption="Ready User for Channel 5" mask="0x20"/>
          <bitfield name="READYUSR6" caption="Ready User for Channel 6" mask="0x40"/>
          <bitfield name="READYUSR7" caption="Ready User for Channel 7" mask="0x80"/>
          <bitfield name="READYUSR8" caption="Ready User for Channel 8" mask="0x100"/>
          <bitfield name="READYUSR9" caption="Ready User for Channel 9" mask="0x200"/>
          <bitfield name="READYUSR10" caption="Ready User for Channel 10" mask="0x400"/>
          <bitfield name="READYUSR11" caption="Ready User for Channel 11" mask="0x800"/>
        </register>
        <register-group name="CHANNEL" name-in-module="CHANNEL" offset="0x020" count="32"/>
        <register name="USER" offset="0x120" rw="RW" size="4" count="67" initval="0x00000000" caption="User Multiplexer n">
          <bitfield name="CHANNEL" caption="Channel Event Selection" mask="0x3F"/>
        </register>
      </register-group>
      <value-group name="EVSYS_CHANNEL__EDGSEL">
        <value name="NO_EVT_OUTPUT" caption="No event output when using the resynchronized or synchronous path" value="0"/>
        <value name="RISING_EDGE" caption="Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" value="1"/>
        <value name="FALLING_EDGE" caption="Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" value="2"/>
        <value name="BOTH_EDGES" caption="Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" value="3"/>
      </value-group>
      <value-group name="EVSYS_CHANNEL__PATH">
        <value name="SYNCHRONOUS" caption="Synchronous path" value="0"/>
        <value name="RESYNCHRONIZED" caption="Resynchronized path" value="1"/>
        <value name="ASYNCHRONOUS" caption="Asynchronous path" value="2"/>
      </value-group>
    </module>
    <module name="FREQM" id="U2257" version="1.1.0" caption="Frequency Meter">
      <register-group name="FREQM" caption="Frequency Meter">
        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A Register">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
        </register>
        <register name="CTRLB" offset="0x1" rw="W" size="1" initval="0x00" caption="Control B Register">
          <bitfield name="START" caption="Start Measurement" mask="0x1"/>
        </register>
        <register name="CFGA" offset="0x2" rw="RW" size="2" initval="0x0000" caption="Config A register">
          <bitfield name="REFNUM" caption="Number of Reference Clock Cycles" mask="0xFF"/>
        </register>
        <register name="INTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear Register">
          <bitfield name="DONE" caption="Measurement Done Interrupt Enable" mask="0x1"/>
        </register>
        <register name="INTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set Register">
          <bitfield name="DONE" caption="Measurement Done Interrupt Enable" mask="0x1"/>
        </register>
        <register name="INTFLAG" offset="0xA" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Register">
          <bitfield name="DONE" caption="Measurement Done" mask="0x1"/>
        </register>
        <register name="STATUS" offset="0xB" rw="RW" size="1" initval="0x00" caption="Status Register">
          <bitfield name="BUSY" caption="FREQM Status" mask="0x1"/>
          <bitfield name="OVF" caption="Sticky Count Value Overflow" mask="0x2"/>
        </register>
        <register name="SYNCBUSY" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy Register">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
        </register>
        <register name="VALUE" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Count Value Register">
          <bitfield name="VALUE" caption="Measurement Value" mask="0xFFFFFF"/>
        </register>
      </register-group>
    </module>
    <module name="GCLK" id="U2122" version="1.2.0" caption="Generic Clock Generator">
      <register-group name="GCLK" caption="Generic Clock Generator">
        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
        </register>
        <register name="SYNCBUSY" offset="0x4" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
          <bitfield name="SWRST" caption="Software Reset Synchroniation Busy bit" mask="0x1"/>
          <bitfield name="GENCTRL0" caption="Generic Clock Generator Control 0 Synchronization Busy bits" mask="0x4" values="GCLK_SYNCBUSY__GENCTRL"/>
          <bitfield name="GENCTRL1" caption="Generic Clock Generator Control 1 Synchronization Busy bits" mask="0x8" values="GCLK_SYNCBUSY__GENCTRL"/>
          <bitfield name="GENCTRL2" caption="Generic Clock Generator Control 2 Synchronization Busy bits" mask="0x10" values="GCLK_SYNCBUSY__GENCTRL"/>
          <bitfield name="GENCTRL3" caption="Generic Clock Generator Control 3 Synchronization Busy bits" mask="0x20" values="GCLK_SYNCBUSY__GENCTRL"/>
          <bitfield name="GENCTRL4" caption="Generic Clock Generator Control 4 Synchronization Busy bits" mask="0x40" values="GCLK_SYNCBUSY__GENCTRL"/>
          <bitfield name="GENCTRL5" caption="Generic Clock Generator Control 5 Synchronization Busy bits" mask="0x80" values="GCLK_SYNCBUSY__GENCTRL"/>
          <bitfield name="GENCTRL6" caption="Generic Clock Generator Control 6 Synchronization Busy bits" mask="0x100" values="GCLK_SYNCBUSY__GENCTRL"/>
          <bitfield name="GENCTRL7" caption="Generic Clock Generator Control 7 Synchronization Busy bits" mask="0x200" values="GCLK_SYNCBUSY__GENCTRL"/>
          <bitfield name="GENCTRL8" caption="Generic Clock Generator Control 8 Synchronization Busy bits" mask="0x400" values="GCLK_SYNCBUSY__GENCTRL"/>
          <bitfield name="GENCTRL9" caption="Generic Clock Generator Control 9 Synchronization Busy bits" mask="0x800" values="GCLK_SYNCBUSY__GENCTRL"/>
          <bitfield name="GENCTRL10" caption="Generic Clock Generator Control 10 Synchronization Busy bits" mask="0x1000" values="GCLK_SYNCBUSY__GENCTRL"/>
          <bitfield name="GENCTRL11" caption="Generic Clock Generator Control 11 Synchronization Busy bits" mask="0x2000" values="GCLK_SYNCBUSY__GENCTRL"/>
        </register>
        <register name="GENCTRL" offset="0x20" rw="RW" size="4" count="12" initval="0x00000000" caption="Generic Clock Generator Control">
          <bitfield name="SRC" caption="Source Select" mask="0xF" values="GCLK_GENCTRL__SRC"/>
          <bitfield name="GENEN" caption="Generic Clock Generator Enable" mask="0x100"/>
          <bitfield name="IDC" caption="Improve Duty Cycle" mask="0x200"/>
          <bitfield name="OOV" caption="Output Off Value" mask="0x400"/>
          <bitfield name="OE" caption="Output Enable" mask="0x800"/>
          <bitfield name="DIVSEL" caption="Divide Selection" mask="0x1000"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x2000"/>
          <bitfield name="DIV" caption="Division Factor" mask="0xFFFF0000"/>
        </register>
        <register name="PCHCTRL" offset="0x80" rw="RW" size="4" count="48" initval="0x00000000" caption="Peripheral Clock Control">
          <bitfield name="GEN" caption="Generic Clock Generator" mask="0xF" values="GCLK_PCHCTRL__GEN"/>
          <bitfield name="CHEN" caption="Channel Enable" mask="0x40"/>
          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x80"/>
        </register>
      </register-group>
      <value-group name="GCLK_SYNCBUSY__GENCTRL">
        <value name="GCLK0" caption="Generic clock generator 0" value="0x0001"/>
        <value name="GCLK1" caption="Generic clock generator 1" value="0x0002"/>
        <value name="GCLK2" caption="Generic clock generator 2" value="0x0004"/>
        <value name="GCLK3" caption="Generic clock generator 3" value="0x0008"/>
        <value name="GCLK4" caption="Generic clock generator 4" value="0x0010"/>
        <value name="GCLK5" caption="Generic clock generator 5" value="0x0020"/>
        <value name="GCLK6" caption="Generic clock generator 6" value="0x0040"/>
        <value name="GCLK7" caption="Generic clock generator 7" value="0x0080"/>
        <value name="GCLK8" caption="Generic clock generator 8" value="0x0100"/>
        <value name="GCLK9" caption="Generic clock generator 9" value="0x0200"/>
        <value name="GCLK10" caption="Generic clock generator 10" value="0x0400"/>
        <value name="GCLK11" caption="Generic clock generator 11" value="0x0800"/>
      </value-group>
      <value-group name="GCLK_GENCTRL__SRC">
        <value name="XOSC0" caption="XOSC0 oscillator output" value="0"/>
        <value name="XOSC1" caption="XOSC1 oscillator output" value="1"/>
        <value name="GCLKIN" caption="Generator input pad" value="2"/>
        <value name="GCLKGEN1" caption="Generic clock generator 1 output" value="3"/>
        <value name="OSCULP32K" caption="OSCULP32K oscillator output" value="4"/>
        <value name="XOSC32K" caption="XOSC32K oscillator output" value="5"/>
        <value name="DFLL" caption="DFLL output" value="6"/>
        <value name="DPLL0" caption="DPLL0 output" value="7"/>
        <value name="DPLL1" caption="DPLL1 output" value="8"/>
      </value-group>
      <value-group name="GCLK_PCHCTRL__GEN">
        <value name="GCLK0" caption="Generic clock generator 0" value="0x0"/>
        <value name="GCLK1" caption="Generic clock generator 1" value="0x1"/>
        <value name="GCLK2" caption="Generic clock generator 2" value="0x2"/>
        <value name="GCLK3" caption="Generic clock generator 3" value="0x3"/>
        <value name="GCLK4" caption="Generic clock generator 4" value="0x4"/>
        <value name="GCLK5" caption="Generic clock generator 5" value="0x5"/>
        <value name="GCLK6" caption="Generic clock generator 6" value="0x6"/>
        <value name="GCLK7" caption="Generic clock generator 7" value="0x7"/>
        <value name="GCLK8" caption="Generic clock generator 8" value="0x8"/>
        <value name="GCLK9" caption="Generic clock generator 9" value="0x9"/>
        <value name="GCLK10" caption="Generic clock generator 10" value="0xA"/>
        <value name="GCLK11" caption="Generic clock generator 11" value="0xB"/>
      </value-group>
    </module>
    <module name="HMATRIXB" id="I7638" version="2.1.4" caption="HSB Matrix">
      <register-group name="PRS" size="0x8">
        <register name="PRAS" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority A for Slave">
        </register>
        <register name="PRBS" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Priority B for Slave">
        </register>
      </register-group>
      <register-group name="HMATRIXB" caption="HSB Matrix">
        <register-group name="PRS" name-in-module="PRS" offset="0x080" count="16"/>
      </register-group>
    </module>
    <module name="ICM" id="U2010" version="1.2.0" caption="Integrity Check Monitor">
      <register-group name="ICM" caption="Integrity Check Monitor">
        <register name="CFG" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Configuration">
          <bitfield name="WBDIS" caption="Write Back Disable" mask="0x1"/>
          <bitfield name="EOMDIS" caption="End of Monitoring Disable" mask="0x2"/>
          <bitfield name="SLBDIS" caption="Secondary List Branching Disable" mask="0x4"/>
          <bitfield name="BBC" caption="Bus Burden Control" mask="0xF0"/>
          <bitfield name="ASCD" caption="Automatic Switch To Compare Digest" mask="0x100"/>
          <bitfield name="DUALBUFF" caption="Dual Input Buffer" mask="0x200"/>
          <bitfield name="UIHASH" caption="User Initial Hash Value" mask="0x1000"/>
          <bitfield name="UALGO" caption="User SHA Algorithm" mask="0xE000" values="ICM_CFG__UALGO"/>
          <bitfield name="HAPROT" caption="Region Hash Area Protection" mask="0x3F0000"/>
          <bitfield name="DAPROT" caption="Region Descriptor Area Protection" mask="0x3F000000"/>
        </register>
        <register name="CTRL" offset="0x4" rw="W" size="4" access-size="4" caption="Control">
          <bitfield name="ENABLE" caption="ICM Enable" mask="0x1"/>
          <bitfield name="DISABLE" caption="ICM Disable Register" mask="0x2"/>
          <bitfield name="SWRST" caption="Software Reset" mask="0x4"/>
          <bitfield name="REHASH" caption="Recompute Internal Hash" mask="0xF0"/>
          <bitfield name="RMDIS" caption="Region Monitoring Disable" mask="0xF00"/>
          <bitfield name="RMEN" caption="Region Monitoring Enable" mask="0xF000"/>
        </register>
        <register name="SR" offset="0x8" rw="R" size="4" access-size="4" initval="0x00000000" caption="Status">
          <bitfield name="ENABLE" caption="ICM Controller Enable Register" mask="0x1"/>
          <bitfield name="RAWRMDIS" caption="RAW Region Monitoring Disabled Status" mask="0xF00"/>
          <bitfield name="RMDIS" caption="Region Monitoring Disabled Status" mask="0xF000"/>
        </register>
        <register name="IER" offset="0x10" rw="W" size="4" access-size="4" atomic-op="set:IMR" caption="Interrupt Enable">
          <bitfield name="RHC" caption="Region Hash Completed Interrupt Enable" mask="0xF"/>
          <bitfield name="RDM" caption="Region Digest Mismatch Interrupt Enable" mask="0xF0"/>
          <bitfield name="RBE" caption="Region Bus Error Interrupt Enable" mask="0xF00"/>
          <bitfield name="RWC" caption="Region Wrap Condition detected Interrupt Enable" mask="0xF000"/>
          <bitfield name="REC" caption="Region End bit Condition Detected Interrupt Enable" mask="0xF0000"/>
          <bitfield name="RSU" caption="Region Status Updated Interrupt Disable" mask="0xF00000"/>
          <bitfield name="URAD" caption="Undefined Register Access Detection Interrupt Enable" mask="0x1000000"/>
        </register>
        <register name="IDR" offset="0x14" rw="W" size="4" access-size="4" atomic-op="clear:IMR" initval="0x00000000" caption="Interrupt Disable">
          <bitfield name="RHC" caption="Region Hash Completed Interrupt Disable" mask="0xF"/>
          <bitfield name="RDM" caption="Region Digest Mismatch Interrupt Disable" mask="0xF0"/>
          <bitfield name="RBE" caption="Region Bus Error Interrupt Disable" mask="0xF00"/>
          <bitfield name="RWC" caption="Region Wrap Condition Detected Interrupt Disable" mask="0xF000"/>
          <bitfield name="REC" caption="Region End bit Condition detected Interrupt Disable" mask="0xF0000"/>
          <bitfield name="RSU" caption="Region Status Updated Interrupt Disable" mask="0xF00000"/>
          <bitfield name="URAD" caption="Undefined Register Access Detection Interrupt Disable" mask="0x1000000"/>
        </register>
        <register name="IMR" offset="0x18" rw="R" size="4" access-size="4" initval="0x00000000" caption="Interrupt Mask">
          <bitfield name="RHC" caption="Region Hash Completed Interrupt Mask" mask="0xF"/>
          <bitfield name="RDM" caption="Region Digest Mismatch Interrupt Mask" mask="0xF0"/>
          <bitfield name="RBE" caption="Region Bus Error Interrupt Mask" mask="0xF00"/>
          <bitfield name="RWC" caption="Region Wrap Condition Detected Interrupt Mask" mask="0xF000"/>
          <bitfield name="REC" caption="Region End bit Condition Detected Interrupt Mask" mask="0xF0000"/>
          <bitfield name="RSU" caption="Region Status Updated Interrupt Mask" mask="0xF00000"/>
          <bitfield name="URAD" caption="Undefined Register Access Detection Interrupt Mask" mask="0x1000000"/>
        </register>
        <register name="ISR" offset="0x1C" rw="R" size="4" access-size="4" initval="0x00000000" caption="Interrupt Status">
          <bitfield name="RHC" caption="Region Hash Completed" mask="0xF"/>
          <bitfield name="RDM" caption="Region Digest Mismatch" mask="0xF0"/>
          <bitfield name="RBE" caption="Region Bus Error" mask="0xF00"/>
          <bitfield name="RWC" caption="Region Wrap Condition Detected" mask="0xF000"/>
          <bitfield name="REC" caption="Region End bit Condition Detected" mask="0xF0000"/>
          <bitfield name="RSU" caption="Region Status Updated Detected" mask="0xF00000"/>
          <bitfield name="URAD" caption="Undefined Register Access Detection Status" mask="0x1000000"/>
        </register>
        <register name="UASR" offset="0x20" rw="R" size="4" access-size="4" initval="0x00000000" caption="Undefined Access Status">
          <bitfield name="URAT" caption="Undefined Register Access Trace" mask="0x7" values="ICM_UASR__URAT"/>
        </register>
        <register name="DSCR" offset="0x30" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Region Descriptor Area Start Address">
          <bitfield name="DASA" caption="Descriptor Area Start Address" mask="0xFFFFFFC0"/>
        </register>
        <register name="HASH" offset="0x34" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Region Hash Area Start Address">
          <bitfield name="HASA" caption="Hash Area Start Address" mask="0xFFFFFF80"/>
        </register>
        <register name="UIHVAL" offset="0x38" rw="W" size="4" access-size="4" count="8" initval="0x00000000" caption="User Initial Hash Value n">
          <bitfield name="VAL" caption="Initial Hash Value" mask="0xFFFFFFFF"/>
        </register>
      </register-group>
      <register-group name="ICM_DESCRIPTOR" caption="Integrity Check Monitor">
        <register name="RADDR" offset="0x0" rw="RW" size="4" access-size="4" caption="Region Start Address">
        </register>
        <register name="RCFG" offset="0x4" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Region Configuration">
          <bitfield name="CDWBN" caption="Compare Digest Write Back" mask="0x1" values="ICM_RCFG__CDWBN"/>
          <bitfield name="WRAP" caption="Region Wrap" mask="0x2" values="ICM_RCFG__WRAP"/>
          <bitfield name="EOM" caption="End of Monitoring" mask="0x4" values="ICM_RCFG__EOM"/>
          <bitfield name="RHIEN" caption="Region Hash Interrupt Enable" mask="0x10" values="ICM_RCFG__RHIEN"/>
          <bitfield name="DMIEN" caption="Region Digest Mismatch Interrupt Enable" mask="0x20" values="ICM_RCFG__DMIEN"/>
          <bitfield name="BEIEN" caption="Region Bus Error Interrupt Enable" mask="0x40" values="ICM_RCFG__BEIEN"/>
          <bitfield name="WCIEN" caption="Region Wrap Condition Detected Interrupt Enable" mask="0x80" values="ICM_RCFG__WCIEN"/>
          <bitfield name="ECIEN" caption="Region End bit Condition detected Interrupt Enable" mask="0x100" values="ICM_RCFG__ECIEN"/>
          <bitfield name="SUIEN" caption="Region Status Updated Interrupt Enable" mask="0x200" values="ICM_RCFG__SUIEN"/>
          <bitfield name="PROCDLY" caption="SHA Processing Delay" mask="0x400" values="ICM_RCFG__PROCDLY"/>
          <bitfield name="ALGO" caption="SHA Algorithm" mask="0x7000"/>
          <bitfield name="MRPROT" caption="Memory Region AHB Protection" mask="0x3F000000"/>
        </register>
        <register name="RCTRL" offset="0x8" rw="RW" size="4" access-size="4" caption="Region Control">
          <bitfield name="TRSIZE" caption="Transfer Size" mask="0xFFFF"/>
        </register>
        <register name="RNEXT" offset="0xC" rw="RW" size="4" access-size="4" caption="Region Next Address">
        </register>
      </register-group>
      <value-group name="ICM_CFG__UALGO">
        <value name="SHA1" caption="SHA1 Algorithm" value="0x0"/>
        <value name="SHA256" caption="SHA256 Algorithm" value="0x1"/>
        <value name="SHA224" caption="SHA224 Algorithm" value="0x4"/>
      </value-group>
      <value-group name="ICM_RCFG__BEIEN">
        <value name="EN" value="0"/>
        <value name="DIS" value="1"/>
      </value-group>
      <value-group name="ICM_RCFG__CDWBN">
        <value name="WRBA" value="0"/>
        <value name="COMP" value="1"/>
      </value-group>
      <value-group name="ICM_RCFG__DMIEN">
        <value name="EN" value="0"/>
        <value name="DIS" value="1"/>
      </value-group>
      <value-group name="ICM_RCFG__ECIEN">
        <value name="EN" value="0"/>
        <value name="DIS" value="1"/>
      </value-group>
      <value-group name="ICM_RCFG__EOM">
        <value name="NO" value="0"/>
        <value name="YES" value="1"/>
      </value-group>
      <value-group name="ICM_RCFG__PROCDLY">
        <value name="SHORT" value="0"/>
        <value name="LONG" value="1"/>
      </value-group>
      <value-group name="ICM_RCFG__RHIEN">
        <value name="EN" value="0"/>
        <value name="DIS" value="1"/>
      </value-group>
      <value-group name="ICM_RCFG__SUIEN">
        <value name="EN" value="0"/>
        <value name="DIS" value="1"/>
      </value-group>
      <value-group name="ICM_RCFG__WCIEN">
        <value name="EN" value="0"/>
        <value name="DIS" value="1"/>
      </value-group>
      <value-group name="ICM_RCFG__WRAP">
        <value name="NO" value="0"/>
        <value name="YES" value="1"/>
      </value-group>
      <value-group name="ICM_UASR__URAT">
        <value name="UNSPEC_STRUCT_MEMBER" caption="Unspecified structure member set to one detected when the descriptor is loaded" value="0x0"/>
        <value name="CFG_MODIFIED" caption="CFG modified during active monitoring" value="0x1"/>
        <value name="DSCR_MODIFIED" caption="DSCR modified during active monitoring" value="0x2"/>
        <value name="HASH_MODIFIED" caption="HASH modified during active monitoring" value="0x3"/>
        <value name="READ_ACCESS" caption="Write-only register read access" value="0x4"/>
      </value-group>
    </module>
    <module name="I2S" id="U2224" version="2.0.0" caption="Inter-IC Sound Interface">
      <register-group name="I2S" caption="Inter-IC Sound Interface">
        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="CKEN0" caption="Clock Unit 0 Enable" mask="0x4"/>
          <bitfield name="CKEN1" caption="Clock Unit 1 Enable" mask="0x8"/>
          <bitfield name="TXEN" caption="Tx Serializer Enable" mask="0x10"/>
          <bitfield name="RXEN" caption="Rx Serializer Enable" mask="0x20"/>
        </register>
        <register name="CLKCTRL" offset="0x4" rw="RW" size="4" count="2" initval="0x00000000" caption="Clock Unit n Control">
          <bitfield name="SLOTSIZE" caption="Slot Size" mask="0x3" values="I2S_CLKCTRL__SLOTSIZE"/>
          <bitfield name="NBSLOTS" caption="Number of Slots in Frame" mask="0x1C"/>
          <bitfield name="FSWIDTH" caption="Frame Sync Width" mask="0x60" values="I2S_CLKCTRL__FSWIDTH"/>
          <bitfield name="BITDELAY" caption="Data Delay from Frame Sync" mask="0x80" values="I2S_CLKCTRL__BITDELAY"/>
          <bitfield name="FSSEL" caption="Frame Sync Select" mask="0x100" values="I2S_CLKCTRL__FSSEL"/>
          <bitfield name="FSINV" caption="Frame Sync Invert" mask="0x200"/>
          <bitfield name="FSOUTINV" caption="Frame Sync Output Invert" mask="0x400"/>
          <bitfield name="SCKSEL" caption="Serial Clock Select" mask="0x800" values="I2S_CLKCTRL__SCKSEL"/>
          <bitfield name="SCKOUTINV" caption="Serial Clock Output Invert" mask="0x1000"/>
          <bitfield name="MCKSEL" caption="Master Clock Select" mask="0x2000" values="I2S_CLKCTRL__MCKSEL"/>
          <bitfield name="MCKEN" caption="Master Clock Enable" mask="0x4000"/>
          <bitfield name="MCKOUTINV" caption="Master Clock Output Invert" mask="0x8000"/>
          <bitfield name="MCKDIV" caption="Master Clock Division Factor" mask="0x3F0000"/>
          <bitfield name="MCKOUTDIV" caption="Master Clock Output Division Factor" mask="0x3F000000"/>
        </register>
        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
        </register>
        <register name="INTENSET" offset="0x10" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
          <bitfield name="RXRDY0" caption="Receive Ready 0 Interrupt Enable" mask="0x1"/>
          <bitfield name="RXRDY1" caption="Receive Ready 1 Interrupt Enable" mask="0x2"/>
          <bitfield name="RXOR0" caption="Receive Overrun 0 Interrupt Enable" mask="0x10"/>
          <bitfield name="RXOR1" caption="Receive Overrun 1 Interrupt Enable" mask="0x20"/>
          <bitfield name="TXRDY0" caption="Transmit Ready 0 Interrupt Enable" mask="0x100"/>
          <bitfield name="TXRDY1" caption="Transmit Ready 1 Interrupt Enable" mask="0x200"/>
          <bitfield name="TXUR0" caption="Transmit Underrun 0 Interrupt Enable" mask="0x1000"/>
          <bitfield name="TXUR1" caption="Transmit Underrun 1 Interrupt Enable" mask="0x2000"/>
        </register>
        <register name="INTFLAG" offset="0x14" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
          <bitfield name="RXRDY0" caption="Receive Ready 0" mask="0x1"/>
          <bitfield name="RXRDY1" caption="Receive Ready 1" mask="0x2"/>
          <bitfield name="RXOR0" caption="Receive Overrun 0" mask="0x10"/>
          <bitfield name="RXOR1" caption="Receive Overrun 1" mask="0x20"/>
          <bitfield name="TXRDY0" caption="Transmit Ready 0" mask="0x100"/>
          <bitfield name="TXRDY1" caption="Transmit Ready 1" mask="0x200"/>
          <bitfield name="TXUR0" caption="Transmit Underrun 0" mask="0x1000"/>
          <bitfield name="TXUR1" caption="Transmit Underrun 1" mask="0x2000"/>
        </register>
        <register name="SYNCBUSY" offset="0x18" rw="R" size="2" initval="0x0000" caption="Synchronization Status">
          <bitfield name="SWRST" caption="Software Reset Synchronization Status" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable Synchronization Status" mask="0x2"/>
          <bitfield name="CKEN0" caption="Clock Unit 0 Enable Synchronization Status" mask="0x4"/>
          <bitfield name="CKEN1" caption="Clock Unit 1 Enable Synchronization Status" mask="0x8"/>
          <bitfield name="TXEN" caption="Tx Serializer Enable Synchronization Status" mask="0x10"/>
          <bitfield name="RXEN" caption="Rx Serializer Enable Synchronization Status" mask="0x20"/>
          <bitfield name="TXDATA" caption="Tx Data Synchronization Status" mask="0x100"/>
          <bitfield name="RXDATA" caption="Rx Data Synchronization Status" mask="0x200"/>
        </register>
        <register name="TXCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Tx Serializer Control">
          <bitfield name="TXDEFAULT" caption="Line Default Line when Slot Disabled" mask="0xC" values="I2S_TXCTRL__TXDEFAULT"/>
          <bitfield name="TXSAME" caption="Transmit Data when Underrun" mask="0x10" values="I2S_TXCTRL__TXSAME"/>
          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_TXCTRL__SLOTADJ"/>
          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_TXCTRL__DATASIZE"/>
          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_TXCTRL__WORDADJ"/>
          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_TXCTRL__EXTEND"/>
          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_TXCTRL__BITREV"/>
          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_TXCTRL__MONO"/>
          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_TXCTRL__DMA"/>
        </register>
        <register name="RXCTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Rx Serializer Control">
          <bitfield name="SERMODE" caption="Serializer Mode" mask="0x3" values="I2S_RXCTRL__SERMODE"/>
          <bitfield name="CLKSEL" caption="Clock Unit Selection" mask="0x20" values="I2S_RXCTRL__CLKSEL"/>
          <bitfield name="SLOTADJ" caption="Data Slot Formatting Adjust" mask="0x80" values="I2S_RXCTRL__SLOTADJ"/>
          <bitfield name="DATASIZE" caption="Data Word Size" mask="0x700" values="I2S_RXCTRL__DATASIZE"/>
          <bitfield name="WORDADJ" caption="Data Word Formatting Adjust" mask="0x1000" values="I2S_RXCTRL__WORDADJ"/>
          <bitfield name="EXTEND" caption="Data Formatting Bit Extension" mask="0x6000" values="I2S_RXCTRL__EXTEND"/>
          <bitfield name="BITREV" caption="Data Formatting Bit Reverse" mask="0x8000" values="I2S_RXCTRL__BITREV"/>
          <bitfield name="SLOTDIS0" caption="Slot 0 Disabled for this Serializer" mask="0x10000"/>
          <bitfield name="SLOTDIS1" caption="Slot 1 Disabled for this Serializer" mask="0x20000"/>
          <bitfield name="SLOTDIS2" caption="Slot 2 Disabled for this Serializer" mask="0x40000"/>
          <bitfield name="SLOTDIS3" caption="Slot 3 Disabled for this Serializer" mask="0x80000"/>
          <bitfield name="SLOTDIS4" caption="Slot 4 Disabled for this Serializer" mask="0x100000"/>
          <bitfield name="SLOTDIS5" caption="Slot 5 Disabled for this Serializer" mask="0x200000"/>
          <bitfield name="SLOTDIS6" caption="Slot 6 Disabled for this Serializer" mask="0x400000"/>
          <bitfield name="SLOTDIS7" caption="Slot 7 Disabled for this Serializer" mask="0x800000"/>
          <bitfield name="MONO" caption="Mono Mode" mask="0x1000000" values="I2S_RXCTRL__MONO"/>
          <bitfield name="DMA" caption="Single or Multiple DMA Channels" mask="0x2000000" values="I2S_RXCTRL__DMA"/>
          <bitfield name="RXLOOP" caption="Loop-back Test Mode" mask="0x4000000"/>
        </register>
        <register name="TXDATA" offset="0x30" rw="W" access="WSYNC" size="4" initval="0x00000000" caption="Tx Data">
          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
        </register>
        <register name="RXDATA" offset="0x34" rw="R" access="RSYNC" size="4" initval="0x00000000" caption="Rx Data">
          <bitfield name="DATA" caption="Sample Data" mask="0xFFFFFFFF"/>
        </register>
      </register-group>
      <value-group name="I2S_CLKCTRL__BITDELAY">
        <value name="LJ" caption="Left Justified (0 Bit Delay)" value="0x0"/>
        <value name="I2S" caption="I2S (1 Bit Delay)" value="0x1"/>
      </value-group>
      <value-group name="I2S_CLKCTRL__FSSEL">
        <value name="SCKDIV" caption="Divided Serial Clock n is used as Frame Sync n source" value="0x0"/>
        <value name="FSPIN" caption="FSn input pin is used as Frame Sync n source" value="0x1"/>
      </value-group>
      <value-group name="I2S_CLKCTRL__FSWIDTH">
        <value name="SLOT" caption="Frame Sync Pulse is 1 Slot wide (default for I2S protocol)" value="0x0"/>
        <value name="HALF" caption="Frame Sync Pulse is half a Frame wide" value="0x1"/>
        <value name="BIT" caption="Frame Sync Pulse is 1 Bit wide" value="0x2"/>
        <value name="BURST" caption="Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested" value="0x3"/>
      </value-group>
      <value-group name="I2S_CLKCTRL__MCKSEL">
        <value name="GCLK" caption="GCLK_I2S_n is used as Master Clock n source" value="0x0"/>
        <value name="MCKPIN" caption="MCKn input pin is used as Master Clock n source" value="0x1"/>
      </value-group>
      <value-group name="I2S_CLKCTRL__SCKSEL">
        <value name="MCKDIV" caption="Divided Master Clock n is used as Serial Clock n source" value="0x0"/>
        <value name="SCKPIN" caption="SCKn input pin is used as Serial Clock n source" value="0x1"/>
      </value-group>
      <value-group name="I2S_CLKCTRL__SLOTSIZE">
        <value name="8" caption="8-bit Slot for Clock Unit n" value="0x0"/>
        <value name="16" caption="16-bit Slot for Clock Unit n" value="0x1"/>
        <value name="24" caption="24-bit Slot for Clock Unit n" value="0x2"/>
        <value name="32" caption="32-bit Slot for Clock Unit n" value="0x3"/>
      </value-group>
      <value-group name="I2S_TXCTRL__BITREV">
        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
      </value-group>
      <value-group name="I2S_TXCTRL__DATASIZE">
        <value name="32" caption="32 bits" value="0x0"/>
        <value name="24" caption="24 bits" value="0x1"/>
        <value name="20" caption="20 bits" value="0x2"/>
        <value name="18" caption="18 bits" value="0x3"/>
        <value name="16" caption="16 bits" value="0x4"/>
        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
        <value name="8" caption="8 bits" value="0x6"/>
        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
      </value-group>
      <value-group name="I2S_TXCTRL__DMA">
        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
      </value-group>
      <value-group name="I2S_TXCTRL__EXTEND">
        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
        <value name="ONE" caption="Extend with ones" value="0x1"/>
        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
      </value-group>
      <value-group name="I2S_TXCTRL__MONO">
        <value name="STEREO" caption="Normal mode" value="0x0"/>
        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
      </value-group>
      <value-group name="I2S_TXCTRL__SLOTADJ">
        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
      </value-group>
      <value-group name="I2S_TXCTRL__TXDEFAULT">
        <value name="ZERO" caption="Output Default Value is 0" value="0x0"/>
        <value name="ONE" caption="Output Default Value is 1" value="0x1"/>
        <value name="HIZ" caption="Output Default Value is high impedance" value="0x3"/>
      </value-group>
      <value-group name="I2S_TXCTRL__TXSAME">
        <value name="ZERO" caption="Zero data transmitted in case of underrun" value="0x0"/>
        <value name="SAME" caption="Last data transmitted in case of underrun" value="0x1"/>
      </value-group>
      <value-group name="I2S_TXCTRL__WORDADJ">
        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
      </value-group>
      <value-group name="I2S_RXCTRL__BITREV">
        <value name="MSBIT" caption="Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)" value="0x0"/>
        <value name="LSBIT" caption="Transfer Data Least Significant Bit (LSB) first" value="0x1"/>
      </value-group>
      <value-group name="I2S_RXCTRL__CLKSEL">
        <value name="CLK0" caption="Use Clock Unit 0" value="0x0"/>
        <value name="CLK1" caption="Use Clock Unit 1" value="0x1"/>
      </value-group>
      <value-group name="I2S_RXCTRL__DATASIZE">
        <value name="32" caption="32 bits" value="0x0"/>
        <value name="24" caption="24 bits" value="0x1"/>
        <value name="20" caption="20 bits" value="0x2"/>
        <value name="18" caption="18 bits" value="0x3"/>
        <value name="16" caption="16 bits" value="0x4"/>
        <value name="16C" caption="16 bits compact stereo" value="0x5"/>
        <value name="8" caption="8 bits" value="0x6"/>
        <value name="8C" caption="8 bits compact stereo" value="0x7"/>
      </value-group>
      <value-group name="I2S_RXCTRL__DMA">
        <value name="SINGLE" caption="Single DMA channel" value="0x0"/>
        <value name="MULTIPLE" caption="One DMA channel per data channel" value="0x1"/>
      </value-group>
      <value-group name="I2S_RXCTRL__EXTEND">
        <value name="ZERO" caption="Extend with zeroes" value="0x0"/>
        <value name="ONE" caption="Extend with ones" value="0x1"/>
        <value name="MSBIT" caption="Extend with Most Significant Bit" value="0x2"/>
        <value name="LSBIT" caption="Extend with Least Significant Bit" value="0x3"/>
      </value-group>
      <value-group name="I2S_RXCTRL__MONO">
        <value name="STEREO" caption="Normal mode" value="0x0"/>
        <value name="MONO" caption="Left channel data is duplicated to right channel" value="0x1"/>
      </value-group>
      <value-group name="I2S_RXCTRL__SERMODE">
        <value name="RX" caption="Receive" value="0x0"/>
        <value name="PDM2" caption="Receive one PDM data on each serial clock edge" value="0x2"/>
      </value-group>
      <value-group name="I2S_RXCTRL__SLOTADJ">
        <value name="RIGHT" caption="Data is right adjusted in slot" value="0x0"/>
        <value name="LEFT" caption="Data is left adjusted in slot" value="0x1"/>
      </value-group>
      <value-group name="I2S_RXCTRL__WORDADJ">
        <value name="RIGHT" caption="Data is right adjusted in word" value="0x0"/>
        <value name="LEFT" caption="Data is left adjusted in word" value="0x1"/>
      </value-group>
    </module>
    <module name="MCLK" id="U2408" version="1.0.0" caption="Main Clock">
      <register-group name="MCLK" caption="Main Clock">
        <register name="INTENCLR" offset="0x1" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
        </register>
        <register name="INTENSET" offset="0x2" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
          <bitfield name="CKRDY" caption="Clock Ready Interrupt Enable" mask="0x1"/>
        </register>
        <register name="INTFLAG" offset="0x3" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x01" caption="Interrupt Flag Status and Clear">
          <bitfield name="CKRDY" caption="Clock Ready" mask="0x1"/>
        </register>
        <register name="HSDIV" offset="0x4" rw="R" size="1" initval="0x01" caption="HS Clock Division">
          <bitfield name="DIV" caption="CPU Clock Division Factor" mask="0xFF" values="MCLK_HSDIV__DIV"/>
        </register>
        <register name="CPUDIV" offset="0x5" rw="RW" size="1" initval="0x01" caption="CPU Clock Division">
          <bitfield name="DIV" caption="Low-Power Clock Division Factor" mask="0xFF" values="MCLK_CPUDIV__DIV"/>
        </register>
        <register name="AHBMASK" offset="0x10" rw="RW" size="4" initval="0x00FFFFFF" caption="AHB Mask">
          <bitfield name="HPB0_" caption="HPB0 AHB Clock Mask" mask="0x1"/>
          <bitfield name="HPB1_" caption="HPB1 AHB Clock Mask" mask="0x2"/>
          <bitfield name="HPB2_" caption="HPB2 AHB Clock Mask" mask="0x4"/>
          <bitfield name="HPB3_" caption="HPB3 AHB Clock Mask" mask="0x8"/>
          <bitfield name="DSU_" caption="DSU AHB Clock Mask" mask="0x10"/>
          <bitfield name="HMATRIX_" caption="HMATRIX AHB Clock Mask" mask="0x20"/>
          <bitfield name="NVMCTRL_" caption="NVMCTRL AHB Clock Mask" mask="0x40"/>
          <bitfield name="HSRAM_" caption="HSRAM AHB Clock Mask" mask="0x80"/>
          <bitfield name="CMCC_" caption="CMCC AHB Clock Mask" mask="0x100"/>
          <bitfield name="DMAC_" caption="DMAC AHB Clock Mask" mask="0x200"/>
          <bitfield name="USB_" caption="USB AHB Clock Mask" mask="0x400"/>
          <bitfield name="BKUPRAM_" caption="BKUPRAM AHB Clock Mask" mask="0x800"/>
          <bitfield name="PAC_" caption="PAC AHB Clock Mask" mask="0x1000"/>
          <bitfield name="QSPI_" caption="QSPI AHB Clock Mask" mask="0x2000"/>
          <bitfield name="SDHC0_" caption="SDHC0 AHB Clock Mask" mask="0x8000"/>
          <bitfield name="SDHC1_" caption="SDHC1 AHB Clock Mask" mask="0x10000"/>
          <bitfield name="ICM_" caption="ICM AHB Clock Mask" mask="0x80000"/>
          <bitfield name="PUKCC_" caption="PUKCC AHB Clock Mask" mask="0x100000"/>
          <bitfield name="QSPI_2X_" caption="QSPI_2X AHB Clock Mask" mask="0x200000"/>
          <bitfield name="NVMCTRL_SMEEPROM_" caption="NVMCTRL_SMEEPROM AHB Clock Mask" mask="0x400000"/>
          <bitfield name="NVMCTRL_CACHE_" caption="NVMCTRL_CACHE AHB Clock Mask" mask="0x800000"/>
        </register>
        <register name="APBAMASK" offset="0x14" rw="RW" size="4" initval="0x000007FF" caption="APBA Mask">
          <bitfield name="PAC_" caption="PAC APB Clock Enable" mask="0x1"/>
          <bitfield name="PM_" caption="PM APB Clock Enable" mask="0x2"/>
          <bitfield name="MCLK_" caption="MCLK APB Clock Enable" mask="0x4"/>
          <bitfield name="RSTC_" caption="RSTC APB Clock Enable" mask="0x8"/>
          <bitfield name="OSCCTRL_" caption="OSCCTRL APB Clock Enable" mask="0x10"/>
          <bitfield name="OSC32KCTRL_" caption="OSC32KCTRL APB Clock Enable" mask="0x20"/>
          <bitfield name="SUPC_" caption="SUPC APB Clock Enable" mask="0x40"/>
          <bitfield name="GCLK_" caption="GCLK APB Clock Enable" mask="0x80"/>
          <bitfield name="WDT_" caption="WDT APB Clock Enable" mask="0x100"/>
          <bitfield name="RTC_" caption="RTC APB Clock Enable" mask="0x200"/>
          <bitfield name="EIC_" caption="EIC APB Clock Enable" mask="0x400"/>
          <bitfield name="FREQM_" caption="FREQM APB Clock Enable" mask="0x800"/>
          <bitfield name="SERCOM0_" caption="SERCOM0 APB Clock Enable" mask="0x1000"/>
          <bitfield name="SERCOM1_" caption="SERCOM1 APB Clock Enable" mask="0x2000"/>
          <bitfield name="TC0_" caption="TC0 APB Clock Enable" mask="0x4000"/>
          <bitfield name="TC1_" caption="TC1 APB Clock Enable" mask="0x8000"/>
        </register>
        <register name="APBBMASK" offset="0x18" rw="RW" size="4" initval="0x00018056" caption="APBB Mask">
          <bitfield name="USB_" caption="USB APB Clock Enable" mask="0x1"/>
          <bitfield name="DSU_" caption="DSU APB Clock Enable" mask="0x2"/>
          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Clock Enable" mask="0x4"/>
          <bitfield name="PORT_" caption="PORT APB Clock Enable" mask="0x10"/>
          <bitfield name="HMATRIX_" caption="HMATRIX APB Clock Enable" mask="0x40"/>
          <bitfield name="EVSYS_" caption="EVSYS APB Clock Enable" mask="0x80"/>
          <bitfield name="SERCOM2_" caption="SERCOM2 APB Clock Enable" mask="0x200"/>
          <bitfield name="SERCOM3_" caption="SERCOM3 APB Clock Enable" mask="0x400"/>
          <bitfield name="TCC0_" caption="TCC0 APB Clock Enable" mask="0x800"/>
          <bitfield name="TCC1_" caption="TCC1 APB Clock Enable" mask="0x1000"/>
          <bitfield name="TC2_" caption="TC2 APB Clock Enable" mask="0x2000"/>
          <bitfield name="TC3_" caption="TC3 APB Clock Enable" mask="0x4000"/>
          <bitfield name="TAL_" caption="TAL APB Clock Enable" mask="0x8000"/>
          <bitfield name="RAMECC_" caption="RAMECC APB Clock Enable" mask="0x10000"/>
        </register>
        <register name="APBCMASK" offset="0x1C" rw="RW" size="4" initval="0x00002000" caption="APBC Mask">
          <bitfield name="TCC2_" caption="TCC2 APB Clock Enable" mask="0x8"/>
          <bitfield name="TCC3_" caption="TCC3 APB Clock Enable" mask="0x10"/>
          <bitfield name="TC4_" caption="TC4 APB Clock Enable" mask="0x20"/>
          <bitfield name="TC5_" caption="TC5 APB Clock Enable" mask="0x40"/>
          <bitfield name="PDEC_" caption="PDEC APB Clock Enable" mask="0x80"/>
          <bitfield name="AC_" caption="AC APB Clock Enable" mask="0x100"/>
          <bitfield name="AES_" caption="AES APB Clock Enable" mask="0x200"/>
          <bitfield name="TRNG_" caption="TRNG APB Clock Enable" mask="0x400"/>
          <bitfield name="ICM_" caption="ICM APB Clock Enable" mask="0x800"/>
          <bitfield name="QSPI_" caption="QSPI APB Clock Enable" mask="0x2000"/>
          <bitfield name="CCL_" caption="CCL APB Clock Enable" mask="0x4000"/>
        </register>
        <register name="APBDMASK" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="APBD Mask">
          <bitfield name="SERCOM4_" caption="SERCOM4 APB Clock Enable" mask="0x1"/>
          <bitfield name="SERCOM5_" caption="SERCOM5 APB Clock Enable" mask="0x2"/>
          <bitfield name="SERCOM6_" caption="SERCOM6 APB Clock Enable" mask="0x4"/>
          <bitfield name="SERCOM7_" caption="SERCOM7 APB Clock Enable" mask="0x8"/>
          <bitfield name="TCC4_" caption="TCC4 APB Clock Enable" mask="0x10"/>
          <bitfield name="TC6_" caption="TC6 APB Clock Enable" mask="0x20"/>
          <bitfield name="TC7_" caption="TC7 APB Clock Enable" mask="0x40"/>
          <bitfield name="ADC0_" caption="ADC0 APB Clock Enable" mask="0x80"/>
          <bitfield name="ADC1_" caption="ADC1 APB Clock Enable" mask="0x100"/>
          <bitfield name="DAC_" caption="DAC APB Clock Enable" mask="0x200"/>
          <bitfield name="I2S_" caption="I2S APB Clock Enable" mask="0x400"/>
          <bitfield name="PCC_" caption="PCC APB Clock Enable" mask="0x800"/>
        </register>
      </register-group>
      <value-group name="MCLK_HSDIV__DIV">
        <value name="DIV1" caption="Divide by 1" value="0x01"/>
      </value-group>
      <value-group name="MCLK_CPUDIV__DIV">
        <value name="DIV1" caption="Divide by 1" value="0x01"/>
        <value name="DIV2" caption="Divide by 2" value="0x02"/>
        <value name="DIV4" caption="Divide by 4" value="0x04"/>
        <value name="DIV8" caption="Divide by 8" value="0x08"/>
        <value name="DIV16" caption="Divide by 16" value="0x10"/>
        <value name="DIV32" caption="Divide by 32" value="0x20"/>
        <value name="DIV64" caption="Divide by 64" value="0x40"/>
        <value name="DIV128" caption="Divide by 128" value="0x80"/>
      </value-group>
    </module>
    <module name="NVMCTRL" id="U2409" version="1.0.0" caption="Non-Volatile Memory Controller">
      <register-group name="NVMCTRL" caption="Non-Volatile Memory Controller">
        <register name="CTRLA" offset="0x0" rw="RW" size="2" initval="0x0004" caption="Control A">
          <bitfield name="AUTOWS" caption="Auto Wait State Enable" mask="0x4"/>
          <bitfield name="SUSPEN" caption="Suspend Enable" mask="0x8"/>
          <bitfield name="WMODE" caption="Write Mode" mask="0x30" values="NVMCTRL_CTRLA__WMODE"/>
          <bitfield name="PRM" caption="Power Reduction Mode during Sleep" mask="0xC0" values="NVMCTRL_CTRLA__PRM"/>
          <bitfield name="RWS" caption="NVM Read Wait States" mask="0xF00"/>
          <bitfield name="AHBNS0" caption="Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated" mask="0x1000"/>
          <bitfield name="AHBNS1" caption="Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated" mask="0x2000"/>
          <bitfield name="CACHEDIS0" caption="AHB0 Cache Disable" mask="0x4000"/>
          <bitfield name="CACHEDIS1" caption="AHB1 Cache Disable" mask="0x8000"/>
        </register>
        <register name="CTRLB" offset="0x4" rw="W" size="2" initval="0x0000" caption="Control B">
          <bitfield name="CMD" caption="Command" mask="0x7F" values="NVMCTRL_CTRLB__CMD"/>
          <bitfield name="CMDEX" caption="Command Execution" mask="0xFF00" values="NVMCTRL_CTRLB__CMDEX"/>
        </register>
        <register name="PARAM" offset="0x8" rw="R" size="4" initval="0x00060000" caption="NVM Parameter">
          <bitfield name="NVMP" caption="NVM Pages" mask="0xFFFF"/>
          <bitfield name="PSZ" caption="Page Size" mask="0x70000" values="NVMCTRL_PARAM__PSZ"/>
          <bitfield name="SEE" caption="SmartEEPROM Supported" mask="0x80000000"/>
        </register>
        <register name="INTENCLR" offset="0xC" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="Interrupt Enable Clear">
          <bitfield name="DONE" caption="Command Done Interrupt Clear" mask="0x1"/>
          <bitfield name="ADDRE" caption="Address Error" mask="0x2"/>
          <bitfield name="PROGE" caption="Programming Error Interrupt Clear" mask="0x4"/>
          <bitfield name="LOCKE" caption="Lock Error Interrupt Clear" mask="0x8"/>
          <bitfield name="ECCSE" caption="ECC Single Error Interrupt Clear" mask="0x10"/>
          <bitfield name="ECCDE" caption="ECC Dual Error Interrupt Clear" mask="0x20"/>
          <bitfield name="NVME" caption="NVM Error Interrupt Clear" mask="0x40"/>
          <bitfield name="SUSP" caption="Suspended Write Or Erase Interrupt Clear" mask="0x80"/>
          <bitfield name="SEESFULL" caption="Active SEES Full Interrupt Clear" mask="0x100"/>
          <bitfield name="SEESOVF" caption="Active SEES Overflow Interrupt Clear" mask="0x200"/>
          <bitfield name="SEEWRC" caption="SEE Write Completed Interrupt Clear" mask="0x400"/>
        </register>
        <register name="INTENSET" offset="0xE" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="Interrupt Enable Set">
          <bitfield name="DONE" caption="Command Done Interrupt Enable" mask="0x1"/>
          <bitfield name="ADDRE" caption="Address Error Interrupt Enable" mask="0x2"/>
          <bitfield name="PROGE" caption="Programming Error Interrupt Enable" mask="0x4"/>
          <bitfield name="LOCKE" caption="Lock Error Interrupt Enable" mask="0x8"/>
          <bitfield name="ECCSE" caption="ECC Single Error Interrupt Enable" mask="0x10"/>
          <bitfield name="ECCDE" caption="ECC Dual Error Interrupt Enable" mask="0x20"/>
          <bitfield name="NVME" caption="NVM Error Interrupt Enable" mask="0x40"/>
          <bitfield name="SUSP" caption="Suspended Write Or Erase  Interrupt Enable" mask="0x80"/>
          <bitfield name="SEESFULL" caption="Active SEES Full Interrupt Enable" mask="0x100"/>
          <bitfield name="SEESOVF" caption="Active SEES Overflow Interrupt Enable" mask="0x200"/>
          <bitfield name="SEEWRC" caption="SEE Write Completed Interrupt Enable" mask="0x400"/>
        </register>
        <register name="INTFLAG" offset="0x10" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="Interrupt Flag Status and Clear">
          <bitfield name="DONE" caption="Command Done" mask="0x1"/>
          <bitfield name="ADDRE" caption="Address Error" mask="0x2"/>
          <bitfield name="PROGE" caption="Programming Error" mask="0x4"/>
          <bitfield name="LOCKE" caption="Lock Error" mask="0x8"/>
          <bitfield name="ECCSE" caption="ECC Single Error" mask="0x10"/>
          <bitfield name="ECCDE" caption="ECC Dual Error" mask="0x20"/>
          <bitfield name="NVME" caption="NVM Error" mask="0x40"/>
          <bitfield name="SUSP" caption="Suspended Write Or Erase Operation" mask="0x80"/>
          <bitfield name="SEESFULL" caption="Active SEES Full" mask="0x100"/>
          <bitfield name="SEESOVF" caption="Active SEES Overflow" mask="0x200"/>
          <bitfield name="SEEWRC" caption="SEE Write Completed" mask="0x400"/>
        </register>
        <register name="STATUS" offset="0x12" rw="R" size="2" initval="0x0000" caption="Status">
          <bitfield name="READY" caption="Ready to accept a command" mask="0x1"/>
          <bitfield name="PRM" caption="Power Reduction Mode" mask="0x2"/>
          <bitfield name="LOAD" caption="NVM Page Buffer Active Loading" mask="0x4"/>
          <bitfield name="SUSP" caption="NVM Write Or Erase Operation Is Suspended" mask="0x8"/>
          <bitfield name="AFIRST" caption="BANKA First" mask="0x10"/>
          <bitfield name="BPDIS" caption="Boot Loader Protection Disable" mask="0x20"/>
          <bitfield name="BOOTPROT" caption="Boot Loader Protection Size" mask="0xF00"/>
        </register>
        <register name="ADDR" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Address">
          <bitfield name="ADDR" caption="NVM Address" mask="0xFFFFFF"/>
        </register>
        <register name="RUNLOCK" offset="0x18" rw="R" size="4" initval="0x00000000" caption="Lock Section">
          <bitfield name="RUNLOCK" caption="Region Un-Lock Bits" mask="0xFFFFFFFF"/>
        </register>
        <register name="PBLDATA" offset="0x1C" rw="R" size="4" count="2" initval="0xFFFFFFFF" caption="Page Buffer Load Data x">
          <bitfield name="DATA" caption="Page Buffer Data" mask="0xFFFFFFFF"/>
        </register>
        <register name="ECCERR" offset="0x24" rw="R" size="4" initval="0x00000000" caption="ECC Error Status Register">
          <bitfield name="ADDR" caption="Error Address" mask="0xFFFFFF"/>
          <bitfield name="TYPEL" caption="Low Double-Word Error Type" mask="0x30000000" values="NVMCTRL_ECCERR__TYPEL"/>
          <bitfield name="TYPEH" caption="High Double-Word Error Type" mask="0xC0000000" values="NVMCTRL_ECCERR__TYPEH"/>
        </register>
        <register name="DBGCTRL" offset="0x28" rw="RW" size="1" initval="0x00" caption="Debug Control">
          <bitfield name="ECCDIS" caption="Debugger ECC Read Disable" mask="0x1"/>
          <bitfield name="ECCELOG" caption="Debugger ECC Error Tracking Mode" mask="0x2"/>
        </register>
        <register name="SEECFG" offset="0x2A" rw="RW" size="1" initval="0x00" caption="SmartEEPROM Configuration Register">
          <bitfield name="WMODE" caption="Write Mode" mask="0x1" values="NVMCTRL_SEECFG__WMODE"/>
          <bitfield name="APRDIS" caption="Automatic Page Reallocation Disable" mask="0x2"/>
        </register>
        <register name="SEESTAT" offset="0x2C" rw="R" size="4" initval="0x00000000" caption="SmartEEPROM Status Register">
          <bitfield name="ASEES" caption="Active SmartEEPROM Sector" mask="0x1"/>
          <bitfield name="LOAD" caption="Page Buffer Loaded" mask="0x2"/>
          <bitfield name="BUSY" caption="Busy" mask="0x4"/>
          <bitfield name="LOCK" caption="SmartEEPROM Write Access Is Locked" mask="0x8"/>
          <bitfield name="RLOCK" caption="SmartEEPROM Write Access To Register Address Space Is Locked" mask="0x10"/>
          <bitfield name="SBLK" caption="Blocks Number In a Sector" mask="0xF00"/>
          <bitfield name="PSZ" caption="SmartEEPROM Page Size" mask="0x70000"/>
        </register>
      </register-group>
      <value-group name="NVMCTRL_CTRLA__PRM">
        <value name="SEMIAUTO" caption="NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access." value="0"/>
        <value name="FULLAUTO" caption="NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode." value="1"/>
        <value name="MANUAL" caption="NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access." value="3"/>
      </value-group>
      <value-group name="NVMCTRL_CTRLA__WMODE">
        <value name="MAN" caption="Manual Write" value="0"/>
        <value name="ADW" caption="Automatic Double Word Write" value="1"/>
        <value name="AQW" caption="Automatic Quad Word" value="2"/>
        <value name="AP" caption="Automatic Page Write" value="3"/>
      </value-group>
      <value-group name="NVMCTRL_CTRLB__CMD">
        <value name="EP" caption="Erase Page - Only supported in the USER and AUX pages." value="0x0"/>
        <value name="EB" caption="Erase Block - Erases the block addressed by the ADDR register, not supported in the user page" value="0x1"/>
        <value name="WP" caption="Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page" value="0x3"/>
        <value name="WQW" caption="Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register." value="0x4"/>
        <value name="SWRST" caption="Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers" value="0x10"/>
        <value name="LR" caption="Lock Region - Locks the region containing the address location in the ADDR register." value="0x11"/>
        <value name="UR" caption="Unlock Region - Unlocks the region containing the address location in the ADDR register." value="0x12"/>
        <value name="SPRM" caption="Sets the power reduction mode." value="0x13"/>
        <value name="CPRM" caption="Clears the power reduction mode." value="0x14"/>
        <value name="PBC" caption="Page Buffer Clear - Clears the page buffer." value="0x15"/>
        <value name="SSB" caption="Set Security Bit" value="0x16"/>
        <value name="BKSWRST" caption="Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK" value="0x17"/>
        <value name="CELCK" caption="Chip Erase Lock - DSU.CE command is not available" value="0x18"/>
        <value name="CEULCK" caption="Chip Erase Unlock - DSU.CE command is available" value="0x19"/>
        <value name="SBPDIS" caption="Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence" value="0x1A"/>
        <value name="CBPDIS" caption="Clears STATUS.BPDIS, Boot loader protection is not discarded" value="0x1B"/>
        <value name="ASEES0" caption="Activate SmartEEPROM Sector 0, deactivate Sector 1" value="0x30"/>
        <value name="ASEES1" caption="Activate SmartEEPROM Sector 1, deactivate Sector 0" value="0x31"/>
        <value name="SEERALOC" caption="Starts SmartEEPROM sector reallocation algorithm" value="0x32"/>
        <value name="SEEFLUSH" caption="Flush SMEE data when in buffered mode" value="0x33"/>
        <value name="LSEE" caption="Lock access to SmartEEPROM data from any mean" value="0x34"/>
        <value name="USEE" caption="Unlock access to SmartEEPROM data" value="0x35"/>
        <value name="LSEER" caption="Lock access to the SmartEEPROM Register Address Space (above 64KB)" value="0x36"/>
        <value name="USEER" caption="Unlock access to the SmartEEPROM Register Address Space (above 64KB)" value="0x37"/>
      </value-group>
      <value-group name="NVMCTRL_CTRLB__CMDEX">
        <value name="KEY" caption="Execution Key" value="0xA5"/>
      </value-group>
      <value-group name="NVMCTRL_PARAM__PSZ">
        <value name="8" caption="8 bytes" value="0x0"/>
        <value name="16" caption="16 bytes" value="0x1"/>
        <value name="32" caption="32 bytes" value="0x2"/>
        <value name="64" caption="64 bytes" value="0x3"/>
        <value name="128" caption="128 bytes" value="0x4"/>
        <value name="256" caption="256 bytes" value="0x5"/>
        <value name="512" caption="512 bytes" value="0x6"/>
        <value name="1024" caption="1024 bytes" value="0x7"/>
      </value-group>
      <value-group name="NVMCTRL_ECCERR__TYPEH">
        <value name="None" caption="No Error Detected Since Last Read" value="0"/>
        <value name="Single" caption="At Least One Single Error Detected Since last Read" value="1"/>
        <value name="Dual" caption="At Least One Dual Error Detected Since Last Read" value="2"/>
      </value-group>
      <value-group name="NVMCTRL_ECCERR__TYPEL">
        <value name="None" caption="No Error Detected Since Last Read" value="0"/>
        <value name="Single" caption="At Least One Single Error Detected Since last Read" value="1"/>
        <value name="Dual" caption="At Least One Dual Error Detected Since Last Read" value="2"/>
      </value-group>
      <value-group name="NVMCTRL_SEECFG__WMODE">
        <value name="UNBUFFERED" caption="A NVM write command is issued after each write in the pagebuffer" value="0"/>
        <value name="BUFFERED" caption="A NVM write command is issued when a write to a new page is requested" value="1"/>
      </value-group>
    </module>
    <module name="FUSES" id="U2409" version="1.0.0" caption="Non-Volatile Fuses">
      <register-group name="SW0_FUSES">
        <register name="SW0_WORD_0" offset="0x0" size="4" rw="R" caption="SW0 Page Word 0">
          <bitfield name="AC_BIAS0" caption="PAIR0 Bias Calibration" mask="0x3"/>
          <bitfield name="ADC0_BIASCOMP" caption="ADC Comparator Scaling" mask="0x1C"/>
          <bitfield name="ADC0_BIASREFBUF" caption="ADC Bias Reference Buffer Scaling" mask="0xE0"/>
          <bitfield name="ADC0_BIASR2R" caption="ADC Bias R2R ampli scaling" mask="0x700"/>
          <bitfield name="ADC1_BIASCOMP" caption="ADC Comparator Scaling" mask="0x70000"/>
          <bitfield name="ADC1_BIASREFBUF" caption="ADC Bias Reference Buffer Scaling" mask="0x380000"/>
          <bitfield name="ADC1_BIASR2R" caption="ADC Bias R2R ampli scaling" mask="0x1C00000"/>
        </register>
        <register name="SW0_WORD_1" offset="0x4" size="4" rw="R" caption="SW0 Page Word 1">
          <bitfield name="USB_TRANSN" caption="USB pad Transn calibration" mask="0x1F"/>
          <bitfield name="USB_TRANSP" caption="USB pad Transp calibration" mask="0x3E0"/>
          <bitfield name="USB_TRIM" caption="USB pad Trim calibration" mask="0x1C00"/>
        </register>
      </register-group>
      <register-group name="TEMP_LOG_FUSES">
        <register name="TEMP_LOG_WORD_0" offset="0x0" size="4" rw="R" caption="TEMP_LOG Page Word 0">
          <bitfield name="ROOM_TEMP_VAL_INT" caption="Integer part of room temperature in oC" mask="0xFF"/>
          <bitfield name="ROOM_TEMP_VAL_DEC" caption="Decimal part of room temperature" mask="0xF00"/>
          <bitfield name="HOT_TEMP_VAL_INT" caption="Integer part of hot temperature in oC" mask="0xFF000"/>
          <bitfield name="HOT_TEMP_VAL_DEC" caption="Decimal part of hot temperature" mask="0xF00000"/>
          <bitfield name="ROOM_INT1V_VAL" caption="2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)" mask="0xFF000000"/>
        </register>
        <register name="TEMP_LOG_WORD_1" offset="0x4" size="4" rw="R" caption="TEMP_LOG Page Word 1">
          <bitfield name="HOT_INT1V_VAL" caption="2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)" mask="0xFF"/>
          <bitfield name="ROOM_ADC_VAL_PTAT" caption="12-bit ADC conversion at room temperature PTAT" mask="0xFFF00"/>
          <bitfield name="HOT_ADC_VAL_PTAT" caption="12-bit ADC conversion at hot temperature PTAT" mask="0xFFF00000"/>
        </register>
        <register name="TEMP_LOG_WORD_2" offset="0x8" size="4" rw="R" caption="TEMP_LOG Page Word 2">
          <bitfield name="ROOM_ADC_VAL_CTAT" caption="12-bit ADC conversion at room temperature CTAT" mask="0xFFF"/>
          <bitfield name="HOT_ADC_VAL_CTAT" caption="12-bit ADC conversion at hot temperature CTAT" mask="0xFFF000"/>
        </register>
      </register-group>
      <register-group name="USER_FUSES">
        <register name="USER_WORD_0" offset="0x0" size="4" rw="RW" caption="USER Page Word 0">
          <bitfield name="BOD33_DIS" caption="BOD33 Disable" mask="0x1"/>
          <bitfield name="BOD33USERLEVEL" caption="BOD33 User Level" mask="0x1FE"/>
          <bitfield name="BOD33_ACTION" caption="BOD33 Action" mask="0x600"/>
          <bitfield name="BOD33_HYST" caption="BOD33 Hysteresis" mask="0x7800"/>
          <bitfield name="BOD12_DIS" caption="BOD12 Disable" mask="0x10000"/>
          <bitfield name="BOD12USERLEVEL" caption="BOD12 User Level" mask="0x7E0000"/>
          <bitfield name="BOD12_ACTION" caption="BOD12 Action" mask="0x1800000"/>
          <bitfield name="BOD12_HYST" caption="BOD12 Hysteresis" mask="0x2000000"/>
          <bitfield name="NVMCTRL_BOOTPROT" caption="Bootloader Size" mask="0x3C000000"/>
        </register>
        <register name="USER_WORD_1" offset="0x4" size="4" rw="RW" caption="USER Page Word 1">
          <bitfield name="NVMCTRL_SEESBLK" caption="Number Of Physical NVM Blocks Composing a SmartEEPROM Sector" mask="0xF"/>
          <bitfield name="NVMCTRL_SEEPSZ" caption="Size Of SmartEEPROM Page" mask="0x70"/>
          <bitfield name="RAMECC_ECCDIS" caption="RAM ECC Disable fuse" mask="0x80"/>
          <bitfield name="WDT_ENABLE" caption="WDT Enable" mask="0x10000"/>
          <bitfield name="WDT_ALWAYSON" caption="WDT Always On" mask="0x20000"/>
          <bitfield name="WDT_PER" caption="WDT Period" mask="0x3C0000"/>
          <bitfield name="WDT_WINDOW" caption="WDT Window" mask="0x3C00000"/>
          <bitfield name="WDT_EWOFFSET" caption="WDT Early Warning Offset" mask="0x3C000000"/>
          <bitfield name="WDT_WEN" caption="WDT Window Mode Enable" mask="0x40000000"/>
        </register>
        <register name="USER_WORD_2" offset="0x8" size="4" rw="RW" caption="USER Page Word 2">
          <bitfield name="NVMCTRL_REGION_LOCKS" caption="NVM Region Locks" mask="0xFFFFFFFF"/>
        </register>
      </register-group>
    </module>
    <module name="OSCCTRL" id="U2401" version="1.0.0" caption="Oscillators Control">
      <register-group name="DPLL" size="0x14">
        <register name="DPLLCTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x80" caption="DPLL Control A">
          <bitfield name="ENABLE" caption="DPLL Enable" mask="0x2"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
        </register>
        <register name="DPLLRATIO" offset="0x4" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="DPLL Ratio Control">
          <bitfield name="LDR" caption="Loop Divider Ratio" mask="0x1FFF"/>
          <bitfield name="LDRFRAC" caption="Loop Divider Ratio Fractional Part" mask="0x1F0000"/>
        </register>
        <register name="DPLLCTRLB" offset="0x8" rw="RW" size="4" initval="0x00000020" caption="DPLL Control B">
          <bitfield name="FILTER" caption="Proportional Integral Filter Selection" mask="0xF"/>
          <bitfield name="WUF" caption="Wake Up Fast" mask="0x10"/>
          <bitfield name="REFCLK" caption="Reference Clock Selection" mask="0xE0" values="OSCCTRL_DPLLCTRLB__REFCLK"/>
          <bitfield name="LTIME" caption="Lock Time" mask="0x700" values="OSCCTRL_DPLLCTRLB__LTIME"/>
          <bitfield name="LBYPASS" caption="Lock Bypass" mask="0x800"/>
          <bitfield name="DCOFILTER" caption="Sigma-Delta DCO Filter Selection" mask="0x7000"/>
          <bitfield name="DCOEN" caption="DCO Filter Enable" mask="0x8000"/>
          <bitfield name="DIV" caption="Clock Divider" mask="0x7FF0000"/>
        </register>
        <register name="DPLLSYNCBUSY" offset="0xC" rw="R" size="4" initval="0x00000000" caption="DPLL Synchronization Busy">
          <bitfield name="ENABLE" caption="DPLL Enable Synchronization Status" mask="0x2"/>
          <bitfield name="DPLLRATIO" caption="DPLL Loop Divider Ratio Synchronization Status" mask="0x4"/>
        </register>
        <register name="DPLLSTATUS" offset="0x10" rw="R" size="4" initval="0x00000000" caption="DPLL Status">
          <bitfield name="LOCK" caption="DPLL Lock Status" mask="0x1"/>
          <bitfield name="CLKRDY" caption="DPLL Clock Ready" mask="0x2"/>
        </register>
      </register-group>
      <register-group name="OSCCTRL" caption="Oscillators Control">
        <register name="EVCTRL" offset="0x0" rw="RW" size="1" initval="0x00" caption="Event Control">
          <bitfield name="CFDEO0" caption="Clock 0 Failure Detector Event Output Enable" mask="0x1"/>
          <bitfield name="CFDEO1" caption="Clock 1 Failure Detector Event Output Enable" mask="0x2"/>
        </register>
        <register name="INTENCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
          <bitfield name="XOSCRDY0" caption="XOSC 0 Ready Interrupt Enable" mask="0x1"/>
          <bitfield name="XOSCRDY1" caption="XOSC 1 Ready Interrupt Enable" mask="0x2"/>
          <bitfield name="XOSCFAIL0" caption="XOSC 0 Clock Failure Detector Interrupt Enable" mask="0x4"/>
          <bitfield name="XOSCFAIL1" caption="XOSC 1 Clock Failure Detector Interrupt Enable" mask="0x8"/>
          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x100"/>
          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x200"/>
          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x400"/>
          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x800"/>
          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x1000"/>
          <bitfield name="DPLL0LCKR" caption="DPLL0 Lock Rise Interrupt Enable" mask="0x10000"/>
          <bitfield name="DPLL0LCKF" caption="DPLL0 Lock Fall Interrupt Enable" mask="0x20000"/>
          <bitfield name="DPLL0LTO" caption="DPLL0 Lock Timeout Interrupt Enable" mask="0x40000"/>
          <bitfield name="DPLL0LDRTO" caption="DPLL0 Loop Divider Ratio Update Complete Interrupt Enable" mask="0x80000"/>
          <bitfield name="DPLL1LCKR" caption="DPLL1 Lock Rise Interrupt Enable" mask="0x1000000"/>
          <bitfield name="DPLL1LCKF" caption="DPLL1 Lock Fall Interrupt Enable" mask="0x2000000"/>
          <bitfield name="DPLL1LTO" caption="DPLL1 Lock Timeout Interrupt Enable" mask="0x4000000"/>
          <bitfield name="DPLL1LDRTO" caption="DPLL1 Loop Divider Ratio Update Complete Interrupt Enable" mask="0x8000000"/>
        </register>
        <register name="INTENSET" offset="0x8" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
          <bitfield name="XOSCRDY0" caption="XOSC 0 Ready Interrupt Enable" mask="0x1"/>
          <bitfield name="XOSCRDY1" caption="XOSC 1 Ready Interrupt Enable" mask="0x2"/>
          <bitfield name="XOSCFAIL0" caption="XOSC 0 Clock Failure Detector Interrupt Enable" mask="0x4"/>
          <bitfield name="XOSCFAIL1" caption="XOSC 1 Clock Failure Detector Interrupt Enable" mask="0x8"/>
          <bitfield name="DFLLRDY" caption="DFLL Ready Interrupt Enable" mask="0x100"/>
          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds Interrupt Enable" mask="0x200"/>
          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine Interrupt Enable" mask="0x400"/>
          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse Interrupt Enable" mask="0x800"/>
          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped Interrupt Enable" mask="0x1000"/>
          <bitfield name="DPLL0LCKR" caption="DPLL0 Lock Rise Interrupt Enable" mask="0x10000"/>
          <bitfield name="DPLL0LCKF" caption="DPLL0 Lock Fall Interrupt Enable" mask="0x20000"/>
          <bitfield name="DPLL0LTO" caption="DPLL0 Lock Timeout Interrupt Enable" mask="0x40000"/>
          <bitfield name="DPLL0LDRTO" caption="DPLL0 Loop Divider Ratio Update Complete Interrupt Enable" mask="0x80000"/>
          <bitfield name="DPLL1LCKR" caption="DPLL1 Lock Rise Interrupt Enable" mask="0x1000000"/>
          <bitfield name="DPLL1LCKF" caption="DPLL1 Lock Fall Interrupt Enable" mask="0x2000000"/>
          <bitfield name="DPLL1LTO" caption="DPLL1 Lock Timeout Interrupt Enable" mask="0x4000000"/>
          <bitfield name="DPLL1LDRTO" caption="DPLL1 Loop Divider Ratio Update Complete Interrupt Enable" mask="0x8000000"/>
        </register>
        <register name="INTFLAG" offset="0xC" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
          <bitfield name="XOSCRDY0" caption="XOSC 0 Ready" mask="0x1"/>
          <bitfield name="XOSCRDY1" caption="XOSC 1 Ready" mask="0x2"/>
          <bitfield name="XOSCFAIL0" caption="XOSC 0 Clock Failure Detector" mask="0x4"/>
          <bitfield name="XOSCFAIL1" caption="XOSC 1 Clock Failure Detector" mask="0x8"/>
          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x100"/>
          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x200"/>
          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x400"/>
          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x800"/>
          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x1000"/>
          <bitfield name="DPLL0LCKR" caption="DPLL0 Lock Rise" mask="0x10000"/>
          <bitfield name="DPLL0LCKF" caption="DPLL0 Lock Fall" mask="0x20000"/>
          <bitfield name="DPLL0LTO" caption="DPLL0 Lock Timeout" mask="0x40000"/>
          <bitfield name="DPLL0LDRTO" caption="DPLL0 Loop Divider Ratio Update Complete" mask="0x80000"/>
          <bitfield name="DPLL1LCKR" caption="DPLL1 Lock Rise" mask="0x1000000"/>
          <bitfield name="DPLL1LCKF" caption="DPLL1 Lock Fall" mask="0x2000000"/>
          <bitfield name="DPLL1LTO" caption="DPLL1 Lock Timeout" mask="0x4000000"/>
          <bitfield name="DPLL1LDRTO" caption="DPLL1 Loop Divider Ratio Update Complete" mask="0x8000000"/>
        </register>
        <register name="STATUS" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Status">
          <bitfield name="XOSCRDY0" caption="XOSC 0 Ready" mask="0x1"/>
          <bitfield name="XOSCRDY1" caption="XOSC 1 Ready" mask="0x2"/>
          <bitfield name="XOSCFAIL0" caption="XOSC 0 Clock Failure Detector" mask="0x4"/>
          <bitfield name="XOSCFAIL1" caption="XOSC 1 Clock Failure Detector" mask="0x8"/>
          <bitfield name="XOSCCKSW0" caption="XOSC 0 Clock Switch" mask="0x10"/>
          <bitfield name="XOSCCKSW1" caption="XOSC 1 Clock Switch" mask="0x20"/>
          <bitfield name="DFLLRDY" caption="DFLL Ready" mask="0x100"/>
          <bitfield name="DFLLOOB" caption="DFLL Out Of Bounds" mask="0x200"/>
          <bitfield name="DFLLLCKF" caption="DFLL Lock Fine" mask="0x400"/>
          <bitfield name="DFLLLCKC" caption="DFLL Lock Coarse" mask="0x800"/>
          <bitfield name="DFLLRCS" caption="DFLL Reference Clock Stopped" mask="0x1000"/>
          <bitfield name="DPLL0LCKR" caption="DPLL0 Lock Rise" mask="0x10000"/>
          <bitfield name="DPLL0LCKF" caption="DPLL0 Lock Fall" mask="0x20000"/>
          <bitfield name="DPLL0TO" caption="DPLL0 Timeout" mask="0x40000"/>
          <bitfield name="DPLL0LDRTO" caption="DPLL0 Loop Divider Ratio Update Complete" mask="0x80000"/>
          <bitfield name="DPLL1LCKR" caption="DPLL1 Lock Rise" mask="0x1000000"/>
          <bitfield name="DPLL1LCKF" caption="DPLL1 Lock Fall" mask="0x2000000"/>
          <bitfield name="DPLL1TO" caption="DPLL1 Timeout" mask="0x4000000"/>
          <bitfield name="DPLL1LDRTO" caption="DPLL1 Loop Divider Ratio Update Complete" mask="0x8000000"/>
        </register>
        <register name="XOSCCTRL" offset="0x14" rw="RW" size="4" count="2" initval="0x00000080" caption="External Multipurpose Crystal Oscillator Control">
          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
          <bitfield name="LOWBUFGAIN" caption="Low Buffer Gain Enable" mask="0x100"/>
          <bitfield name="IPTAT" caption="Oscillator Current Reference" mask="0x600"/>
          <bitfield name="IMULT" caption="Oscillator Current Multiplier" mask="0x7800"/>
          <bitfield name="ENALC" caption="Automatic Loop Control Enable" mask="0x8000"/>
          <bitfield name="CFDEN" caption="Clock Failure Detector Enable" mask="0x10000"/>
          <bitfield name="SWBEN" caption="Xosc Clock Switch Enable" mask="0x20000"/>
          <bitfield name="STARTUP" caption="Start-Up Time" mask="0xF00000"/>
          <bitfield name="CFDPRESC" caption="Clock Failure Detector Prescaler" mask="0xF000000"/>
        </register>
        <register name="DFLLCTRLA" offset="0x1C" rw="RW" size="1" initval="0x82" caption="DFLL48M Control A">
          <bitfield name="ENABLE" caption="DFLL Enable" mask="0x2"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
        </register>
        <register name="DFLLCTRLB" offset="0x20" rw="RW" access="RSYNC" size="1" initval="0x00" caption="DFLL48M Control B">
          <bitfield name="MODE" caption="Operating Mode Selection" mask="0x1"/>
          <bitfield name="STABLE" caption="Stable DFLL Frequency" mask="0x2"/>
          <bitfield name="LLAW" caption="Lose Lock After Wake" mask="0x4"/>
          <bitfield name="USBCRM" caption="USB Clock Recovery Mode" mask="0x8"/>
          <bitfield name="CCDIS" caption="Chill Cycle Disable" mask="0x10"/>
          <bitfield name="QLDIS" caption="Quick Lock Disable" mask="0x20"/>
          <bitfield name="BPLCKC" caption="Bypass Coarse Lock" mask="0x40"/>
          <bitfield name="WAITLOCK" caption="Wait Lock" mask="0x80"/>
        </register>
        <register name="DFLLVAL" offset="0x24" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="DFLL48M Value">
          <bitfield name="FINE" caption="Fine Value" mask="0xFF"/>
          <bitfield name="COARSE" caption="Coarse Value" mask="0xFC00"/>
          <bitfield name="DIFF" caption="Multiplication Ratio Difference" mask="0xFFFF0000"/>
        </register>
        <register name="DFLLMUL" offset="0x28" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="DFLL48M Multiplier">
          <bitfield name="MUL" caption="DFLL Multiply Factor" mask="0xFFFF"/>
          <bitfield name="FSTEP" caption="Fine Maximum Step" mask="0xFF0000"/>
          <bitfield name="CSTEP" caption="Coarse Maximum Step" mask="0xFC000000"/>
        </register>
        <register name="DFLLSYNC" offset="0x2C" rw="RW" size="1" initval="0x00" caption="DFLL48M Synchronization">
          <bitfield name="ENABLE" caption="ENABLE Synchronization Busy" mask="0x2"/>
          <bitfield name="DFLLCTRLB" caption="DFLLCTRLB Synchronization Busy" mask="0x4"/>
          <bitfield name="DFLLVAL" caption="DFLLVAL Synchronization Busy" mask="0x8"/>
          <bitfield name="DFLLMUL" caption="DFLLMUL Synchronization Busy" mask="0x10"/>
        </register>
        <register-group name="DPLL" name-in-module="DPLL" offset="0x30" count="2"/>
      </register-group>
      <value-group name="OSCCTRL_DPLLCTRLB__LTIME">
        <value name="DEFAULT" caption="No time-out. Automatic lock" value="0x0"/>
        <value name="800US" caption="Time-out if no lock within 800us" value="0x4"/>
        <value name="900US" caption="Time-out if no lock within 900us" value="0x5"/>
        <value name="1MS" caption="Time-out if no lock within 1ms" value="0x6"/>
        <value name="1P1MS" caption="Time-out if no lock within 1.1ms" value="0x7"/>
      </value-group>
      <value-group name="OSCCTRL_DPLLCTRLB__REFCLK">
        <value name="GCLK" caption="Dedicated GCLK clock reference" value="0x0"/>
        <value name="XOSC32" caption="XOSC32K clock reference" value="0x1"/>
        <value name="XOSC0" caption="XOSC0 clock reference" value="0x2"/>
        <value name="XOSC1" caption="XOSC1 clock reference" value="0x3"/>
      </value-group>
    </module>
    <module name="OSC32KCTRL" id="U2400" version="1.0.0" caption="32kHz Oscillators Control">
      <register-group name="OSC32KCTRL" caption="32kHz Oscillators Control">
        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x1"/>
          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector Interrupt Enable" mask="0x4"/>
        </register>
        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready Interrupt Enable" mask="0x1"/>
          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector Interrupt Enable" mask="0x4"/>
        </register>
        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x1"/>
          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector" mask="0x4"/>
        </register>
        <register name="STATUS" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
          <bitfield name="XOSC32KRDY" caption="XOSC32K Ready" mask="0x1"/>
          <bitfield name="XOSC32KFAIL" caption="XOSC32K Clock Failure Detector" mask="0x4"/>
          <bitfield name="XOSC32KSW" caption="XOSC32K Clock switch" mask="0x8"/>
        </register>
        <register name="RTCCTRL" offset="0x10" rw="RW" size="1" initval="0x00" caption="RTC Clock Selection">
          <bitfield name="RTCSEL" caption="RTC Clock Selection" mask="0x7" values="OSC32KCTRL_RTCCTRL__RTCSEL"/>
        </register>
        <register name="XOSC32K" offset="0x14" rw="RW" size="2" initval="0x2080" caption="32kHz External Crystal Oscillator (XOSC32K) Control">
          <bitfield name="ENABLE" caption="Oscillator Enable" mask="0x2"/>
          <bitfield name="XTALEN" caption="Crystal Oscillator Enable" mask="0x4"/>
          <bitfield name="EN32K" caption="32kHz Output Enable" mask="0x8"/>
          <bitfield name="EN1K" caption="1kHz Output Enable" mask="0x10"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
          <bitfield name="ONDEMAND" caption="On Demand Control" mask="0x80"/>
          <bitfield name="STARTUP" caption="Oscillator Start-Up Time" mask="0x700"/>
          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x1000"/>
          <bitfield name="CGM" caption="Control Gain Mode" mask="0x6000" values="OSC32KCTRL_XOSC32K__CGM"/>
        </register>
        <register name="CFDCTRL" offset="0x16" rw="RW" size="1" initval="0x00" caption="Clock Failure Detector Control">
          <bitfield name="CFDEN" caption="Clock Failure Detector Enable" mask="0x1"/>
          <bitfield name="SWBACK" caption="Clock Switch Back" mask="0x2"/>
          <bitfield name="CFDPRESC" caption="Clock Failure Detector Prescaler" mask="0x4"/>
        </register>
        <register name="EVCTRL" offset="0x17" rw="RW" size="1" initval="0x00" caption="Event Control">
          <bitfield name="CFDEO" caption="Clock Failure Detector Event Output Enable" mask="0x1"/>
        </register>
        <register name="OSCULP32K" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control">
          <bitfield name="EN32K" caption="Enable Out 32k" mask="0x2"/>
          <bitfield name="EN1K" caption="Enable Out 1k" mask="0x4"/>
          <bitfield name="CALIB" caption="Oscillator Calibration" mask="0x3F00"/>
          <bitfield name="WRTLOCK" caption="Write Lock" mask="0x8000"/>
        </register>
      </register-group>
      <value-group name="OSC32KCTRL_RTCCTRL__RTCSEL">
        <value name="ULP1K" caption="1.024kHz from 32kHz internal ULP oscillator" value="0"/>
        <value name="ULP32K" caption="32.768kHz from 32kHz internal ULP oscillator" value="1"/>
        <value name="XOSC1K" caption="1.024kHz from 32.768kHz internal oscillator" value="4"/>
        <value name="XOSC32K" caption="32.768kHz from 32.768kHz external crystal oscillator" value="5"/>
      </value-group>
      <value-group name="OSC32KCTRL_XOSC32K__CGM">
        <value name="XT" caption="Standard mode" value="1"/>
        <value name="HS" caption="High Speed mode" value="2"/>
      </value-group>
    </module>
    <module name="PAC" id="U2120" version="1.2.0" caption="Peripheral Access Controller">
      <register-group name="PAC" caption="Peripheral Access Controller">
        <register name="WRCTRL" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Write control">
          <bitfield name="PERID" caption="Peripheral identifier" mask="0xFFFF"/>
          <bitfield name="KEY" caption="Peripheral access control key" mask="0xFF0000" values="PAC_WRCTRL__KEY"/>
        </register>
        <register name="EVCTRL" offset="0x4" rw="RW" size="1" initval="0x00" caption="Event control">
          <bitfield name="ERREO" caption="Peripheral acess error event output" mask="0x1"/>
        </register>
        <register name="INTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt enable clear">
          <bitfield name="ERR" caption="Peripheral access error interrupt disable" mask="0x1"/>
        </register>
        <register name="INTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt enable set">
          <bitfield name="ERR" caption="Peripheral access error interrupt enable" mask="0x1"/>
        </register>
        <register name="INTFLAGAHB" offset="0x10" rw="RW" size="4" atomic-op="clear:INTFLAGAHB" initval="0x00000000" caption="Bridge interrupt flag status">
          <bitfield name="FLASH_" caption="FLASH" mask="0x1"/>
          <bitfield name="FLASH_ALT_" caption="FLASH_ALT" mask="0x2"/>
          <bitfield name="SEEPROM_" caption="SEEPROM" mask="0x4"/>
          <bitfield name="RAMCM4S_" caption="RAMCM4S" mask="0x8"/>
          <bitfield name="RAMPPPDSU_" caption="RAMPPPDSU" mask="0x10"/>
          <bitfield name="RAMDMAWR_" caption="RAMDMAWR" mask="0x20"/>
          <bitfield name="RAMDMACICM_" caption="RAMDMACICM" mask="0x40"/>
          <bitfield name="HPB0_" caption="HPB0" mask="0x80"/>
          <bitfield name="HPB1_" caption="HPB1" mask="0x100"/>
          <bitfield name="HPB2_" caption="HPB2" mask="0x200"/>
          <bitfield name="HPB3_" caption="HPB3" mask="0x400"/>
          <bitfield name="PUKCC_" caption="PUKCC" mask="0x800"/>
          <bitfield name="SDHC0_" caption="SDHC0" mask="0x1000"/>
          <bitfield name="SDHC1_" caption="SDHC1" mask="0x2000"/>
          <bitfield name="QSPI_" caption="QSPI" mask="0x4000"/>
          <bitfield name="BKUPRAM_" caption="BKUPRAM" mask="0x8000"/>
        </register>
        <register name="INTFLAGA" offset="0x14" rw="RW" size="4" atomic-op="clear:INTFLAGA" initval="0x00000000" caption="Peripheral interrupt flag status - Bridge A">
          <bitfield name="PAC_" caption="PAC" mask="0x1"/>
          <bitfield name="PM_" caption="PM" mask="0x2"/>
          <bitfield name="MCLK_" caption="MCLK" mask="0x4"/>
          <bitfield name="RSTC_" caption="RSTC" mask="0x8"/>
          <bitfield name="OSCCTRL_" caption="OSCCTRL" mask="0x10"/>
          <bitfield name="OSC32KCTRL_" caption="OSC32KCTRL" mask="0x20"/>
          <bitfield name="SUPC_" caption="SUPC" mask="0x40"/>
          <bitfield name="GCLK_" caption="GCLK" mask="0x80"/>
          <bitfield name="WDT_" caption="WDT" mask="0x100"/>
          <bitfield name="RTC_" caption="RTC" mask="0x200"/>
          <bitfield name="EIC_" caption="EIC" mask="0x400"/>
          <bitfield name="FREQM_" caption="FREQM" mask="0x800"/>
          <bitfield name="SERCOM0_" caption="SERCOM0" mask="0x1000"/>
          <bitfield name="SERCOM1_" caption="SERCOM1" mask="0x2000"/>
          <bitfield name="TC0_" caption="TC0" mask="0x4000"/>
          <bitfield name="TC1_" caption="TC1" mask="0x8000"/>
        </register>
        <register name="INTFLAGB" offset="0x18" rw="RW" size="4" atomic-op="clear:INTFLAGB" initval="0x00000000" caption="Peripheral interrupt flag status - Bridge B">
          <bitfield name="USB_" caption="USB" mask="0x1"/>
          <bitfield name="DSU_" caption="DSU" mask="0x2"/>
          <bitfield name="NVMCTRL_" caption="NVMCTRL" mask="0x4"/>
          <bitfield name="CMCC_" caption="CMCC" mask="0x8"/>
          <bitfield name="PORT_" caption="PORT" mask="0x10"/>
          <bitfield name="DMAC_" caption="DMAC" mask="0x20"/>
          <bitfield name="HMATRIX_" caption="HMATRIX" mask="0x40"/>
          <bitfield name="EVSYS_" caption="EVSYS" mask="0x80"/>
          <bitfield name="SERCOM2_" caption="SERCOM2" mask="0x200"/>
          <bitfield name="SERCOM3_" caption="SERCOM3" mask="0x400"/>
          <bitfield name="TCC0_" caption="TCC0" mask="0x800"/>
          <bitfield name="TCC1_" caption="TCC1" mask="0x1000"/>
          <bitfield name="TC2_" caption="TC2" mask="0x2000"/>
          <bitfield name="TC3_" caption="TC3" mask="0x4000"/>
          <bitfield name="TAL_" caption="TAL" mask="0x8000"/>
          <bitfield name="RAMECC_" caption="RAMECC" mask="0x10000"/>
        </register>
        <register name="INTFLAGC" offset="0x1C" rw="RW" size="4" atomic-op="clear:INTFLAGC" initval="0x00000000" caption="Peripheral interrupt flag status - Bridge C">
          <bitfield name="TCC2_" caption="TCC2" mask="0x8"/>
          <bitfield name="TCC3_" caption="TCC3" mask="0x10"/>
          <bitfield name="TC4_" caption="TC4" mask="0x20"/>
          <bitfield name="TC5_" caption="TC5" mask="0x40"/>
          <bitfield name="PDEC_" caption="PDEC" mask="0x80"/>
          <bitfield name="AC_" caption="AC" mask="0x100"/>
          <bitfield name="AES_" caption="AES" mask="0x200"/>
          <bitfield name="TRNG_" caption="TRNG" mask="0x400"/>
          <bitfield name="ICM_" caption="ICM" mask="0x800"/>
          <bitfield name="PUKCC_" caption="PUKCC" mask="0x1000"/>
          <bitfield name="QSPI_" caption="QSPI" mask="0x2000"/>
          <bitfield name="CCL_" caption="CCL" mask="0x4000"/>
        </register>
        <register name="INTFLAGD" offset="0x20" rw="RW" size="4" atomic-op="clear:INTFLAGD" initval="0x00000000" caption="Peripheral interrupt flag status - Bridge D">
          <bitfield name="SERCOM4_" caption="SERCOM4" mask="0x1"/>
          <bitfield name="SERCOM5_" caption="SERCOM5" mask="0x2"/>
          <bitfield name="SERCOM6_" caption="SERCOM6" mask="0x4"/>
          <bitfield name="SERCOM7_" caption="SERCOM7" mask="0x8"/>
          <bitfield name="TCC4_" caption="TCC4" mask="0x10"/>
          <bitfield name="TC6_" caption="TC6" mask="0x20"/>
          <bitfield name="TC7_" caption="TC7" mask="0x40"/>
          <bitfield name="ADC0_" caption="ADC0" mask="0x80"/>
          <bitfield name="ADC1_" caption="ADC1" mask="0x100"/>
          <bitfield name="DAC_" caption="DAC" mask="0x200"/>
          <bitfield name="I2S_" caption="I2S" mask="0x400"/>
          <bitfield name="PCC_" caption="PCC" mask="0x800"/>
        </register>
        <register name="STATUSA" offset="0x34" rw="R" size="4" initval="0x00010000" caption="Peripheral write protection status - Bridge A">
          <bitfield name="PAC_" caption="PAC APB Protect Enable" mask="0x1"/>
          <bitfield name="PM_" caption="PM APB Protect Enable" mask="0x2"/>
          <bitfield name="MCLK_" caption="MCLK APB Protect Enable" mask="0x4"/>
          <bitfield name="RSTC_" caption="RSTC APB Protect Enable" mask="0x8"/>
          <bitfield name="OSCCTRL_" caption="OSCCTRL APB Protect Enable" mask="0x10"/>
          <bitfield name="OSC32KCTRL_" caption="OSC32KCTRL APB Protect Enable" mask="0x20"/>
          <bitfield name="SUPC_" caption="SUPC APB Protect Enable" mask="0x40"/>
          <bitfield name="GCLK_" caption="GCLK APB Protect Enable" mask="0x80"/>
          <bitfield name="WDT_" caption="WDT APB Protect Enable" mask="0x100"/>
          <bitfield name="RTC_" caption="RTC APB Protect Enable" mask="0x200"/>
          <bitfield name="EIC_" caption="EIC APB Protect Enable" mask="0x400"/>
          <bitfield name="FREQM_" caption="FREQM APB Protect Enable" mask="0x800"/>
          <bitfield name="SERCOM0_" caption="SERCOM0 APB Protect Enable" mask="0x1000"/>
          <bitfield name="SERCOM1_" caption="SERCOM1 APB Protect Enable" mask="0x2000"/>
          <bitfield name="TC0_" caption="TC0 APB Protect Enable" mask="0x4000"/>
          <bitfield name="TC1_" caption="TC1 APB Protect Enable" mask="0x8000"/>
        </register>
        <register name="STATUSB" offset="0x38" rw="R" size="4" initval="0x00000002" caption="Peripheral write protection status - Bridge B">
          <bitfield name="USB_" caption="USB APB Protect Enable" mask="0x1"/>
          <bitfield name="DSU_" caption="DSU APB Protect Enable" mask="0x2"/>
          <bitfield name="NVMCTRL_" caption="NVMCTRL APB Protect Enable" mask="0x4"/>
          <bitfield name="CMCC_" caption="CMCC APB Protect Enable" mask="0x8"/>
          <bitfield name="PORT_" caption="PORT APB Protect Enable" mask="0x10"/>
          <bitfield name="DMAC_" caption="DMAC APB Protect Enable" mask="0x20"/>
          <bitfield name="HMATRIX_" caption="HMATRIX APB Protect Enable" mask="0x40"/>
          <bitfield name="EVSYS_" caption="EVSYS APB Protect Enable" mask="0x80"/>
          <bitfield name="SERCOM2_" caption="SERCOM2 APB Protect Enable" mask="0x200"/>
          <bitfield name="SERCOM3_" caption="SERCOM3 APB Protect Enable" mask="0x400"/>
          <bitfield name="TCC0_" caption="TCC0 APB Protect Enable" mask="0x800"/>
          <bitfield name="TCC1_" caption="TCC1 APB Protect Enable" mask="0x1000"/>
          <bitfield name="TC2_" caption="TC2 APB Protect Enable" mask="0x2000"/>
          <bitfield name="TC3_" caption="TC3 APB Protect Enable" mask="0x4000"/>
          <bitfield name="TAL_" caption="TAL APB Protect Enable" mask="0x8000"/>
          <bitfield name="RAMECC_" caption="RAMECC APB Protect Enable" mask="0x10000"/>
        </register>
        <register name="STATUSC" offset="0x3C" rw="R" size="4" initval="0x00000000" caption="Peripheral write protection status - Bridge C">
          <bitfield name="TCC2_" caption="TCC2 APB Protect Enable" mask="0x8"/>
          <bitfield name="TCC3_" caption="TCC3 APB Protect Enable" mask="0x10"/>
          <bitfield name="TC4_" caption="TC4 APB Protect Enable" mask="0x20"/>
          <bitfield name="TC5_" caption="TC5 APB Protect Enable" mask="0x40"/>
          <bitfield name="PDEC_" caption="PDEC APB Protect Enable" mask="0x80"/>
          <bitfield name="AC_" caption="AC APB Protect Enable" mask="0x100"/>
          <bitfield name="AES_" caption="AES APB Protect Enable" mask="0x200"/>
          <bitfield name="TRNG_" caption="TRNG APB Protect Enable" mask="0x400"/>
          <bitfield name="ICM_" caption="ICM APB Protect Enable" mask="0x800"/>
          <bitfield name="PUKCC_" caption="PUKCC APB Protect Enable" mask="0x1000"/>
          <bitfield name="QSPI_" caption="QSPI APB Protect Enable" mask="0x2000"/>
          <bitfield name="CCL_" caption="CCL APB Protect Enable" mask="0x4000"/>
        </register>
        <register name="STATUSD" offset="0x40" rw="R" size="4" initval="0x00000000" caption="Peripheral write protection status - Bridge D">
          <bitfield name="SERCOM4_" caption="SERCOM4 APB Protect Enable" mask="0x1"/>
          <bitfield name="SERCOM5_" caption="SERCOM5 APB Protect Enable" mask="0x2"/>
          <bitfield name="SERCOM6_" caption="SERCOM6 APB Protect Enable" mask="0x4"/>
          <bitfield name="SERCOM7_" caption="SERCOM7 APB Protect Enable" mask="0x8"/>
          <bitfield name="TCC4_" caption="TCC4 APB Protect Enable" mask="0x10"/>
          <bitfield name="TC6_" caption="TC6 APB Protect Enable" mask="0x20"/>
          <bitfield name="TC7_" caption="TC7 APB Protect Enable" mask="0x40"/>
          <bitfield name="ADC0_" caption="ADC0 APB Protect Enable" mask="0x80"/>
          <bitfield name="ADC1_" caption="ADC1 APB Protect Enable" mask="0x100"/>
          <bitfield name="DAC_" caption="DAC APB Protect Enable" mask="0x200"/>
          <bitfield name="I2S_" caption="I2S APB Protect Enable" mask="0x400"/>
          <bitfield name="PCC_" caption="PCC APB Protect Enable" mask="0x800"/>
        </register>
      </register-group>
      <value-group name="PAC_WRCTRL__KEY">
        <value name="OFF" caption="No action" value="0"/>
        <value name="CLR" caption="Clear protection" value="1"/>
        <value name="SET" caption="Set protection" value="2"/>
        <value name="SETLCK" caption="Set and lock protection" value="3"/>
      </value-group>
    </module>
    <module name="PCC" id="U2017" version="1.1.0" caption="Parallel Capture Controller">
      <register-group name="PCC" caption="Parallel Capture Controller">
        <register name="MR" offset="0x0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Mode Register">
          <bitfield name="PCEN" caption="Parallel Capture Enable" mask="0x1"/>
          <bitfield name="DSIZE" caption="Data size" mask="0x30"/>
          <bitfield name="SCALE" caption="Scale data" mask="0x100"/>
          <bitfield name="ALWYS" caption="Always Sampling" mask="0x200"/>
          <bitfield name="HALFS" caption="Half Sampling" mask="0x400"/>
          <bitfield name="FRSTS" caption="First sample" mask="0x800"/>
          <bitfield name="ISIZE" caption="Input Data Size" mask="0x70000"/>
          <bitfield name="CID" caption="Clear If Disabled" mask="0xC0000000"/>
        </register>
        <register name="IER" offset="0x4" rw="W" size="4" access-size="4" atomic-op="set:IMR" initval="0x00000000" caption="Interrupt Enable Register">
          <bitfield name="DRDY" caption="Data Ready Interrupt Enable" mask="0x1"/>
          <bitfield name="OVRE" caption="Overrun Error Interrupt Enable" mask="0x2"/>
        </register>
        <register name="IDR" offset="0x8" rw="W" size="4" access-size="4" atomic-op="clear:IMR" initval="0x00000000" caption="Interrupt Disable Register">
          <bitfield name="DRDY" caption="Data Ready Interrupt Disable" mask="0x1"/>
          <bitfield name="OVRE" caption="Overrun Error Interrupt Disable" mask="0x2"/>
        </register>
        <register name="IMR" offset="0xC" rw="R" size="4" access-size="4" initval="0x00000000" caption="Interrupt Mask Register">
          <bitfield name="DRDY" caption="Data Ready Interrupt Mask" mask="0x1"/>
          <bitfield name="OVRE" caption="Overrun Error Interrupt Mask" mask="0x2"/>
        </register>
        <register name="ISR" offset="0x10" rw="R" size="4" access-size="4" initval="0x00000000" caption="Interrupt Status Register">
          <bitfield name="DRDY" caption="Data Ready Interrupt Status" mask="0x1"/>
          <bitfield name="OVRE" caption="Overrun Error Interrupt Status" mask="0x2"/>
        </register>
        <register name="RHR" offset="0x14" rw="R" size="4" access-size="4" initval="0x00000000" caption="Reception Holding Register">
          <bitfield name="RDATA" caption="Reception Data" mask="0xFFFFFFFF"/>
        </register>
        <register name="WPMR" offset="0xE0" rw="RW" size="4" access-size="4" initval="0x00000000" caption="Write Protection Mode Register">
          <bitfield name="WPEN" caption="Write Protection Enable" mask="0x1"/>
          <bitfield name="WPKEY" caption="Write Protection Key" mask="0xFFFFFF00"/>
        </register>
        <register name="WPSR" offset="0xE4" rw="R" size="4" access-size="4" initval="0x00000000" caption="Write Protection Status Register">
          <bitfield name="WPVS" caption="Write Protection Violation Source" mask="0x1"/>
          <bitfield name="WPVSRC" caption="Write Protection Violation Status" mask="0xFFFF00"/>
        </register>
      </register-group>
    </module>
    <module name="PDEC" id="U2263" version="1.0.0" caption="Quadrature Decodeur">
      <register-group name="PDEC" caption="Quadrature Decodeur">
        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="MODE" caption="Operation Mode" mask="0xC" values="PDEC_CTRLA__MODE"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
          <bitfield name="CONF" caption="PDEC Configuration" mask="0x700" values="PDEC_CTRLA__CONF"/>
          <bitfield name="ALOCK" caption="Auto Lock" mask="0x800"/>
          <bitfield name="SWAP" caption="PDEC Phase A and B Swap" mask="0x4000"/>
          <bitfield name="PEREN" caption="Period Enable" mask="0x8000"/>
          <bitfield name="PINEN0" caption="PDEC Input From Pin 0 Enable" mask="0x10000"/>
          <bitfield name="PINEN1" caption="PDEC Input From Pin 1 Enable" mask="0x20000"/>
          <bitfield name="PINEN2" caption="PDEC Input From Pin 2 Enable" mask="0x40000"/>
          <bitfield name="PINVEN0" caption="IO Pin 0 Invert Enable" mask="0x100000"/>
          <bitfield name="PINVEN1" caption="IO Pin 1 Invert Enable" mask="0x200000"/>
          <bitfield name="PINVEN2" caption="IO Pin 2 Invert Enable" mask="0x400000"/>
          <bitfield name="ANGULAR" caption="Angular Counter Length" mask="0x7000000"/>
          <bitfield name="MAXCMP" caption="Maximum Consecutive Missing Pulses" mask="0xF0000000"/>
        </register>
        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
          <bitfield name="CMD" caption="Command" mask="0xE0" values="PDEC_CTRLBCLR__CMD"/>
        </register>
        <register name="CTRLBSET" offset="0x5" rw="RW" access="RWSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
          <bitfield name="CMD" caption="Command" mask="0xE0" values="PDEC_CTRLBSET__CMD"/>
        </register>
        <register name="EVCTRL" offset="0x6" rw="RW" size="2" initval="0x0000" caption="Event Control">
          <bitfield name="EVACT" caption="Event Action" mask="0x3" values="PDEC_EVCTRL__EVACT"/>
          <bitfield name="EVINV" caption="Inverted Event Input Enable" mask="0x1C"/>
          <bitfield name="EVEI" caption="Event Input Enable" mask="0xE0"/>
          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
          <bitfield name="ERREO" caption="Error  Output Event Enable" mask="0x200"/>
          <bitfield name="DIREO" caption="Direction Output Event Enable" mask="0x400"/>
          <bitfield name="VLCEO" caption="Velocity Output Event Enable" mask="0x800"/>
          <bitfield name="MCEO0" caption="Match Channel 0 Event Output Enable" mask="0x1000"/>
          <bitfield name="MCEO1" caption="Match Channel 1 Event Output Enable" mask="0x2000"/>
        </register>
        <register name="INTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
          <bitfield name="OVF" caption="Overflow/Underflow Interrupt Disable" mask="0x1"/>
          <bitfield name="ERR" caption="Error Interrupt Disable" mask="0x2"/>
          <bitfield name="DIR" caption="Direction Interrupt Disable" mask="0x4"/>
          <bitfield name="VLC" caption="Velocity Interrupt Disable" mask="0x8"/>
          <bitfield name="MC0" caption="Channel 0 Compare Match Disable" mask="0x10"/>
          <bitfield name="MC1" caption="Channel 1 Compare Match Disable" mask="0x20"/>
        </register>
        <register name="INTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
          <bitfield name="OVF" caption="Overflow/Underflow Interrupt Enable" mask="0x1"/>
          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x2"/>
          <bitfield name="DIR" caption="Direction Interrupt Enable" mask="0x4"/>
          <bitfield name="VLC" caption="Velocity Interrupt Enable" mask="0x8"/>
          <bitfield name="MC0" caption="Channel 0 Compare Match Enable" mask="0x10"/>
          <bitfield name="MC1" caption="Channel 1 Compare Match Enable" mask="0x20"/>
        </register>
        <register name="INTFLAG" offset="0xA" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
          <bitfield name="OVF" caption="Overflow/Underflow" mask="0x1"/>
          <bitfield name="ERR" caption="Error" mask="0x2"/>
          <bitfield name="DIR" caption="Direction Change" mask="0x4"/>
          <bitfield name="VLC" caption="Velocity" mask="0x8"/>
          <bitfield name="MC0" caption="Channel 0 Compare Match" mask="0x10"/>
          <bitfield name="MC1" caption="Channel 1 Compare Match" mask="0x20"/>
        </register>
        <register name="STATUS" offset="0xC" rw="RW" access="RWSYNC" size="2" initval="0x0040" caption="Status">
          <bitfield name="QERR" caption="Quadrature Error Flag" mask="0x1"/>
          <bitfield name="IDXERR" caption="Index Error Flag" mask="0x2"/>
          <bitfield name="MPERR" caption="Missing Pulse Error flag" mask="0x4"/>
          <bitfield name="WINERR" caption="Window Error Flag" mask="0x10"/>
          <bitfield name="HERR" caption="Hall Error Flag" mask="0x20"/>
          <bitfield name="STOP" caption="Stop" mask="0x40"/>
          <bitfield name="DIR" caption="Direction Status Flag" mask="0x80"/>
          <bitfield name="PRESCBUFV" caption="Prescaler Buffer Valid" mask="0x100"/>
          <bitfield name="FILTERBUFV" caption="Filter Buffer Valid" mask="0x200"/>
          <bitfield name="CCBUFV0" caption="Compare Channel 0 Buffer Valid" mask="0x1000"/>
          <bitfield name="CCBUFV1" caption="Compare Channel 1 Buffer Valid" mask="0x2000"/>
        </register>
        <register name="DBGCTRL" offset="0xF" rw="RW" size="1" initval="0x00" caption="Debug Control">
          <bitfield name="DBGRUN" caption="Debug Run Mode" mask="0x1"/>
        </register>
        <register name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Synchronization Status">
          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
          <bitfield name="CTRLB" caption="Control B Synchronization Busy" mask="0x4"/>
          <bitfield name="STATUS" caption="Status Synchronization Busy" mask="0x8"/>
          <bitfield name="PRESC" caption="Prescaler Synchronization Busy" mask="0x10"/>
          <bitfield name="FILTER" caption="Filter Synchronization Busy" mask="0x20"/>
          <bitfield name="COUNT" caption="Count Synchronization Busy" mask="0x40"/>
          <bitfield name="CC0" caption="Compare Channel 0 Synchronization Busy" mask="0x80"/>
          <bitfield name="CC1" caption="Compare Channel 1 Synchronization Busy" mask="0x100"/>
        </register>
        <register name="PRESC" offset="0x14" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Prescaler Value">
          <bitfield name="PRESC" caption="Prescaler Value" mask="0xF" values="PDEC_PRESC__PRESC"/>
        </register>
        <register name="FILTER" offset="0x15" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Filter Value">
          <bitfield name="FILTER" caption="Filter Value" mask="0xFF"/>
        </register>
        <register name="PRESCBUF" offset="0x18" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Prescaler Buffer Value">
          <bitfield name="PRESCBUF" caption="Prescaler Buffer Value" mask="0xF" values="PDEC_PRESCBUF__PRESCBUF"/>
        </register>
        <register name="FILTERBUF" offset="0x19" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Filter Buffer Value">
          <bitfield name="FILTERBUF" caption="Filter Buffer Value" mask="0xFF"/>
        </register>
        <register name="COUNT" offset="0x1C" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Counter Value">
          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
        </register>
        <register name="CC" offset="0x20" rw="RW" access="RWSYNC" size="4" count="2" initval="0x00000000" caption="Channel n Compare Value">
          <bitfield name="CC" caption="Channel Compare Value" mask="0xFFFF"/>
        </register>
        <register name="CCBUF" offset="0x30" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="Channel Compare Buffer Value">
          <bitfield name="CCBUF" caption="Channel Compare Buffer Value" mask="0xFFFF"/>
        </register>
      </register-group>
      <value-group name="PDEC_CTRLA__CONF">
        <value name="X4" caption="Quadrature decoder direction" value="0"/>
        <value name="X4S" caption="Secure Quadrature decoder direction" value="1"/>
        <value name="X2" caption="Decoder direction" value="2"/>
        <value name="X2S" caption="Secure decoder direction" value="3"/>
        <value name="AUTOC" caption="Auto correction mode" value="4"/>
      </value-group>
      <value-group name="PDEC_CTRLA__MODE">
        <value name="QDEC" caption="QDEC operating mode" value="0"/>
        <value name="HALL" caption="HALL operating mode" value="1"/>
        <value name="COUNTER" caption="COUNTER operating mode" value="2"/>
      </value-group>
      <value-group name="PDEC_CTRLBCLR__CMD">
        <value name="NONE" caption="No action" value="0"/>
        <value name="RETRIGGER" caption="Force a counter restart or retrigger" value="1"/>
        <value name="UPDATE" caption="Force update of double buffered registers" value="2"/>
        <value name="READSYNC" caption="Force a read synchronization of COUNT" value="3"/>
        <value name="START" caption="Start QDEC/HALL" value="4"/>
        <value name="STOP" caption="Stop QDEC/HALL" value="5"/>
      </value-group>
      <value-group name="PDEC_CTRLBSET__CMD">
        <value name="NONE" caption="No action" value="0"/>
        <value name="RETRIGGER" caption="Force a counter restart or retrigger" value="1"/>
        <value name="UPDATE" caption="Force update of double buffered registers" value="2"/>
        <value name="READSYNC" caption="Force a read synchronization of COUNT" value="3"/>
        <value name="Start" caption="Start QDEC/HALL" value="4"/>
        <value name="Stop" caption="Stop QDEC/HALL" value="5"/>
      </value-group>
      <value-group name="PDEC_EVCTRL__EVACT">
        <value name="OFF" caption="Event action disabled" value="0"/>
        <value name="RETRIGGER" caption="Start, restart or retrigger on event" value="1"/>
        <value name="COUNT" caption="Count on event" value="2"/>
      </value-group>
      <value-group name="PDEC_PRESC__PRESC">
        <value name="DIV1" caption="No division" value="0"/>
        <value name="DIV2" caption="Divide by 2" value="1"/>
        <value name="DIV4" caption="Divide by 4" value="2"/>
        <value name="DIV8" caption="Divide by 8" value="3"/>
        <value name="DIV16" caption="Divide by 16" value="4"/>
        <value name="DIV32" caption="Divide by 32" value="5"/>
        <value name="DIV64" caption="Divide by 64" value="6"/>
        <value name="DIV128" caption="Divide by 128" value="7"/>
        <value name="DIV256" caption="Divide by 256" value="8"/>
        <value name="DIV512" caption="Divide by 512" value="9"/>
        <value name="DIV1024" caption="Divide by 1024" value="10"/>
      </value-group>
      <value-group name="PDEC_PRESCBUF__PRESCBUF">
        <value name="DIV1" caption="No division" value="0"/>
        <value name="DIV2" caption="Divide by 2" value="1"/>
        <value name="DIV4" caption="Divide by 4" value="2"/>
        <value name="DIV8" caption="Divide by 8" value="3"/>
        <value name="DIV16" caption="Divide by 16" value="4"/>
        <value name="DIV32" caption="Divide by 32" value="5"/>
        <value name="DIV64" caption="Divide by 64" value="6"/>
        <value name="DIV128" caption="Divide by 128" value="7"/>
        <value name="DIV256" caption="Divide by 256" value="8"/>
        <value name="DIV512" caption="Divide by 512" value="9"/>
        <value name="DIV1024" caption="Divide by 1024" value="10"/>
      </value-group>
    </module>
    <module name="PM" id="U2406" version="1.0.0" caption="Power Manager">
      <register-group name="PM" caption="Power Manager">
        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
          <bitfield name="IORET" caption="I/O Retention" mask="0x4"/>
        </register>
        <register name="SLEEPCFG" offset="0x1" rw="RW" size="1" initval="0x02" caption="Sleep Configuration">
          <bitfield name="SLEEPMODE" caption="Sleep Mode" mask="0x7" values="PM_SLEEPCFG__SLEEPMODE"/>
        </register>
        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
          <bitfield name="SLEEPRDY" caption="Sleep Mode Entry Ready Enable" mask="0x1"/>
        </register>
        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
          <bitfield name="SLEEPRDY" caption="Sleep Mode Entry Ready Enable" mask="0x1"/>
        </register>
        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
          <bitfield name="SLEEPRDY" caption="Sleep Mode Entry Ready" mask="0x1"/>
        </register>
        <register name="STDBYCFG" offset="0x8" rw="RW" size="1" initval="0x00" caption="Standby Configuration">
          <bitfield name="RAMCFG" caption="Ram Configuration" mask="0x3" values="PM_STDBYCFG__RAMCFG"/>
          <bitfield name="FASTWKUP" caption="Fast Wakeup" mask="0x30"/>
        </register>
        <register name="HIBCFG" offset="0x9" rw="RW" size="1" initval="0x00" caption="Hibernate Configuration">
          <bitfield name="RAMCFG" caption="Ram Configuration" mask="0x3"/>
          <bitfield name="BRAMCFG" caption="Backup Ram Configuration" mask="0xC"/>
        </register>
        <register name="BKUPCFG" offset="0xA" rw="RW" size="1" initval="0x00" caption="Backup Configuration">
          <bitfield name="BRAMCFG" caption="Ram Configuration" mask="0x3"/>
        </register>
        <register name="PWSAKDLY" offset="0x12" rw="RW" size="1" initval="0x00" caption="Power Switch Acknowledge Delay">
          <bitfield name="DLYVAL" caption="Delay Value" mask="0x7F"/>
          <bitfield name="IGNACK" caption="Ignore Acknowledge" mask="0x80"/>
        </register>
      </register-group>
      <value-group name="PM_SLEEPCFG__SLEEPMODE">
        <value name="IDLE0" caption="CPU clock is OFF" value="0"/>
        <value name="IDLE1" caption="AHB clock is OFF" value="1"/>
        <value name="IDLE2" caption="APB clock are OFF" value="2"/>
        <value name="STANDBY" caption="All Clocks are OFF" value="4"/>
        <value name="HIBERNATE" caption="Backup domain is ON as well as some PDRAMs" value="5"/>
        <value name="BACKUP" caption="Only Backup domain is powered ON" value="6"/>
        <value name="OFF" caption="All power domains are powered OFF" value="7"/>
      </value-group>
      <value-group name="PM_STDBYCFG__RAMCFG">
        <value name="RET" caption="All the RAMs are retained" value="0"/>
        <value name="PARTIAL" caption="Only the first 32K bytes are retained" value="1"/>
        <value name="OFF" caption="All the RAMs are OFF" value="2"/>
      </value-group>
    </module>
    <module name="PORT" id="U2210" version="2.2.0" caption="Port Module">
      <register-group name="GROUP" size="0x80">
        <register name="DIR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Data Direction">
          <bitfield name="DIR" caption="Port Data Direction" mask="0xFFFFFFFF"/>
        </register>
        <register name="DIRCLR" offset="0x4" rw="RW" size="4" atomic-op="clear:DIR" initval="0x00000000" caption="Data Direction Clear">
          <bitfield name="DIRCLR" caption="Port Data Direction Clear" mask="0xFFFFFFFF"/>
        </register>
        <register name="DIRSET" offset="0x8" rw="RW" size="4" atomic-op="set:DIR" initval="0x00000000" caption="Data Direction Set">
          <bitfield name="DIRSET" caption="Port Data Direction Set" mask="0xFFFFFFFF"/>
        </register>
        <register name="DIRTGL" offset="0xC" rw="RW" size="4" atomic-op="toggle:DIR" initval="0x00000000" caption="Data Direction Toggle">
          <bitfield name="DIRTGL" caption="Port Data Direction Toggle" mask="0xFFFFFFFF"/>
        </register>
        <register name="OUT" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Data Output Value">
          <bitfield name="OUT" caption="PORT Data Output Value" mask="0xFFFFFFFF"/>
        </register>
        <register name="OUTCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:OUT" initval="0x00000000" caption="Data Output Value Clear">
          <bitfield name="OUTCLR" caption="PORT Data Output Value Clear" mask="0xFFFFFFFF"/>
        </register>
        <register name="OUTSET" offset="0x18" rw="RW" size="4" atomic-op="set:OUT" initval="0x00000000" caption="Data Output Value Set">
          <bitfield name="OUTSET" caption="PORT Data Output Value Set" mask="0xFFFFFFFF"/>
        </register>
        <register name="OUTTGL" offset="0x1C" rw="RW" size="4" atomic-op="toggle:OUT" initval="0x00000000" caption="Data Output Value Toggle">
          <bitfield name="OUTTGL" caption="PORT Data Output Value Toggle" mask="0xFFFFFFFF"/>
        </register>
        <register name="IN" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Data Input Value">
          <bitfield name="IN" caption="PORT Data Input Value" mask="0xFFFFFFFF"/>
        </register>
        <register name="CTRL" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Control">
          <bitfield name="SAMPLING" caption="Input Sampling Mode" mask="0xFFFFFFFF"/>
        </register>
        <register name="WRCONFIG" offset="0x28" rw="W" size="4" access-size="4" initval="0x00000000" caption="Write Configuration">
          <bitfield name="PINMASK" caption="Pin Mask for Multiple Pin Configuration" mask="0xFFFF"/>
          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x10000"/>
          <bitfield name="INEN" caption="Input Enable" mask="0x20000"/>
          <bitfield name="PULLEN" caption="Pull Enable" mask="0x40000"/>
          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x400000"/>
          <bitfield name="PMUX" caption="Peripheral Multiplexing" mask="0xF000000"/>
          <bitfield name="WRPMUX" caption="Write PMUX" mask="0x10000000"/>
          <bitfield name="WRPINCFG" caption="Write PINCFG" mask="0x40000000"/>
          <bitfield name="HWSEL" caption="Half-Word Select" mask="0x80000000"/>
        </register>
        <register name="EVCTRL" offset="0x2C" rw="RW" size="4" initval="0x00000000" caption="Event Input Control">
          <bitfield name="PID0" caption="PORT Event Pin Identifier 0" mask="0x1F"/>
          <bitfield name="EVACT0" caption="PORT Event Action 0" mask="0x60" values="PORT_EVCTRL__EVACT0"/>
          <bitfield name="PORTEI0" caption="PORT Event Input Enable 0" mask="0x80"/>
          <bitfield name="PID1" caption="PORT Event Pin Identifier 1" mask="0x1F00"/>
          <bitfield name="EVACT1" caption="PORT Event Action 1" mask="0x6000"/>
          <bitfield name="PORTEI1" caption="PORT Event Input Enable 1" mask="0x8000"/>
          <bitfield name="PID2" caption="PORT Event Pin Identifier 2" mask="0x1F0000"/>
          <bitfield name="EVACT2" caption="PORT Event Action 2" mask="0x600000"/>
          <bitfield name="PORTEI2" caption="PORT Event Input Enable 2" mask="0x800000"/>
          <bitfield name="PID3" caption="PORT Event Pin Identifier 3" mask="0x1F000000"/>
          <bitfield name="EVACT3" caption="PORT Event Action 3" mask="0x60000000"/>
          <bitfield name="PORTEI3" caption="PORT Event Input Enable 3" mask="0x80000000"/>
        </register>
        <register name="PMUX" offset="0x30" rw="RW" size="1" count="16" initval="0x00" caption="Peripheral Multiplexing">
          <bitfield name="PMUXE" caption="Peripheral Multiplexing for Even-Numbered Pin" mask="0xF"/>
          <bitfield name="PMUXO" caption="Peripheral Multiplexing for Odd-Numbered Pin" mask="0xF0"/>
        </register>
        <register name="PINCFG" offset="0x40" rw="RW" size="1" count="32" initval="0x00" caption="Pin Configuration">
          <bitfield name="PMUXEN" caption="Peripheral Multiplexer Enable" mask="0x1"/>
          <bitfield name="INEN" caption="Input Enable" mask="0x2"/>
          <bitfield name="PULLEN" caption="Pull Enable" mask="0x4"/>
          <bitfield name="DRVSTR" caption="Output Driver Strength Selection" mask="0x40"/>
        </register>
      </register-group>
      <register-group name="PORT" caption="Port Module">
        <register-group name="GROUP" name-in-module="GROUP" offset="0x00" count="4"/>
      </register-group>
      <value-group name="PORT_EVCTRL__EVACT0">
        <value name="OUT" caption="Event output to pin" value="0x0"/>
        <value name="SET" caption="Set output register of pin on event" value="0x1"/>
        <value name="CLR" caption="Clear output register of pin on event" value="0x2"/>
        <value name="TGL" caption="Toggle output register of pin on event" value="0x3"/>
      </value-group>
    </module>
    <module name="PUKCC" id="U2009" version="2.5.0" caption="PUblic-Key Cryptography Controller">
      <register-group name="PUKCC" caption="PUblic-Key Cryptography Controller"/>
    </module>
    <module name="QSPI" id="U2008" version="1.6.3" caption="Quad SPI interface">
      <register-group name="QSPI" caption="Quad SPI interface">
        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="LASTXFER" caption="Last Transfer" mask="0x1000000"/>
        </register>
        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="Control B">
          <bitfield name="MODE" caption="Serial Memory Mode" mask="0x1" values="QSPI_CTRLB__MODE"/>
          <bitfield name="LOOPEN" caption="Local Loopback Enable" mask="0x2"/>
          <bitfield name="WDRBT" caption="Wait Data Read Before Transfer" mask="0x4"/>
          <bitfield name="SMEMREG" caption="Serial Memory reg" mask="0x8"/>
          <bitfield name="CSMODE" caption="Chip Select Mode" mask="0x30" values="QSPI_CTRLB__CSMODE"/>
          <bitfield name="DATALEN" caption="Data Length" mask="0xF00" values="QSPI_CTRLB__DATALEN"/>
          <bitfield name="DLYBCT" caption="Delay Between Consecutive Transfers" mask="0xFF0000"/>
          <bitfield name="DLYCS" caption="Minimum Inactive CS Delay" mask="0xFF000000"/>
        </register>
        <register name="BAUD" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Baud Rate">
          <bitfield name="CPOL" caption="Clock Polarity" mask="0x1"/>
          <bitfield name="CPHA" caption="Clock Phase" mask="0x2"/>
          <bitfield name="BAUD" caption="Serial Clock Baud Rate" mask="0xFF00"/>
          <bitfield name="DLYBS" caption="Delay Before SCK" mask="0xFF0000"/>
        </register>
        <register name="RXDATA" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Receive Data">
          <bitfield name="DATA" caption="Receive Data" mask="0xFFFF"/>
        </register>
        <register name="TXDATA" offset="0x10" rw="W" size="4" initval="0x00000000" caption="Transmit Data">
          <bitfield name="DATA" caption="Transmit Data" mask="0xFFFF"/>
        </register>
        <register name="INTENCLR" offset="0x14" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
          <bitfield name="RXC" caption="Receive Data Register Full Interrupt Disable" mask="0x1"/>
          <bitfield name="DRE" caption="Transmit Data Register Empty Interrupt Disable" mask="0x2"/>
          <bitfield name="TXC" caption="Transmission Complete Interrupt Disable" mask="0x4"/>
          <bitfield name="ERROR" caption="Overrun Error Interrupt Disable" mask="0x8"/>
          <bitfield name="CSRISE" caption="Chip Select Rise Interrupt Disable" mask="0x100"/>
          <bitfield name="INSTREND" caption="Instruction End Interrupt Disable" mask="0x400"/>
        </register>
        <register name="INTENSET" offset="0x18" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
          <bitfield name="RXC" caption="Receive Data Register Full Interrupt Enable" mask="0x1"/>
          <bitfield name="DRE" caption="Transmit Data Register Empty Interrupt Enable" mask="0x2"/>
          <bitfield name="TXC" caption="Transmission Complete Interrupt Enable" mask="0x4"/>
          <bitfield name="ERROR" caption="Overrun Error Interrupt Enable" mask="0x8"/>
          <bitfield name="CSRISE" caption="Chip Select Rise Interrupt Enable" mask="0x100"/>
          <bitfield name="INSTREND" caption="Instruction End Interrupt Enable" mask="0x400"/>
        </register>
        <register name="INTFLAG" offset="0x1C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
          <bitfield name="RXC" caption="Receive Data Register Full" mask="0x1"/>
          <bitfield name="DRE" caption="Transmit Data Register Empty" mask="0x2"/>
          <bitfield name="TXC" caption="Transmission Complete" mask="0x4"/>
          <bitfield name="ERROR" caption="Overrun Error" mask="0x8"/>
          <bitfield name="CSRISE" caption="Chip Select Rise" mask="0x100"/>
          <bitfield name="INSTREND" caption="Instruction End" mask="0x400"/>
        </register>
        <register name="STATUS" offset="0x20" rw="R" size="4" initval="0x00000200" caption="Status Register">
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="CSSTATUS" caption="Chip Select" mask="0x200"/>
        </register>
        <register name="INSTRADDR" offset="0x30" rw="RW" size="4" initval="0x00000000" caption="Instruction Address">
          <bitfield name="ADDR" caption="Instruction Address" mask="0xFFFFFFFF"/>
        </register>
        <register name="INSTRCTRL" offset="0x34" rw="RW" size="4" initval="0x00000000" caption="Instruction Code">
          <bitfield name="INSTR" caption="Instruction Code" mask="0xFF"/>
          <bitfield name="OPTCODE" caption="Option Code" mask="0xFF0000"/>
        </register>
        <register name="INSTRFRAME" offset="0x38" rw="RW" size="4" initval="0x00000000" caption="Instruction Frame">
          <bitfield name="WIDTH" caption="Instruction Code, Address, Option Code and Data Width" mask="0x7" values="QSPI_INSTRFRAME__WIDTH"/>
          <bitfield name="INSTREN" caption="Instruction Enable" mask="0x10"/>
          <bitfield name="ADDREN" caption="Address Enable" mask="0x20"/>
          <bitfield name="OPTCODEEN" caption="Option Enable" mask="0x40"/>
          <bitfield name="DATAEN" caption="Data Enable" mask="0x80"/>
          <bitfield name="OPTCODELEN" caption="Option Code Length" mask="0x300" values="QSPI_INSTRFRAME__OPTCODELEN"/>
          <bitfield name="ADDRLEN" caption="Address Length" mask="0x400" values="QSPI_INSTRFRAME__ADDRLEN"/>
          <bitfield name="TFRTYPE" caption="Data Transfer Type" mask="0x3000" values="QSPI_INSTRFRAME__TFRTYPE"/>
          <bitfield name="CRMODE" caption="Continuous Read Mode" mask="0x4000"/>
          <bitfield name="DDREN" caption="Double Data Rate Enable" mask="0x8000"/>
          <bitfield name="DUMMYLEN" caption="Dummy Cycles Length" mask="0x1F0000"/>
        </register>
        <register name="SCRAMBCTRL" offset="0x40" rw="RW" size="4" initval="0x00000000" caption="Scrambling Mode">
          <bitfield name="ENABLE" caption="Scrambling/Unscrambling Enable" mask="0x1"/>
          <bitfield name="RANDOMDIS" caption="Scrambling/Unscrambling Random Value Disable" mask="0x2"/>
        </register>
        <register name="SCRAMBKEY" offset="0x44" rw="W" size="4" initval="0x00000000" caption="Scrambling Key">
          <bitfield name="KEY" caption="Scrambling User Key" mask="0xFFFFFFFF"/>
        </register>
      </register-group>
      <value-group name="QSPI_CTRLB__CSMODE">
        <value name="NORELOAD" caption="The chip select is deasserted if TD has not been reloaded before the end of the current transfer." value="0x0"/>
        <value name="LASTXFER" caption="The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred." value="0x1"/>
        <value name="SYSTEMATICALLY" caption="The chip select is deasserted systematically after each transfer." value="0x2"/>
      </value-group>
      <value-group name="QSPI_CTRLB__DATALEN">
        <value name="8BITS" caption="8-bits transfer" value="0x0"/>
        <value name="9BITS" caption="9 bits transfer" value="0x1"/>
        <value name="10BITS" caption="10-bits transfer" value="0x2"/>
        <value name="11BITS" caption="11-bits transfer" value="0x3"/>
        <value name="12BITS" caption="12-bits transfer" value="0x4"/>
        <value name="13BITS" caption="13-bits transfer" value="0x5"/>
        <value name="14BITS" caption="14-bits transfer" value="0x6"/>
        <value name="15BITS" caption="15-bits transfer" value="0x7"/>
        <value name="16BITS" caption="16-bits transfer" value="0x8"/>
      </value-group>
      <value-group name="QSPI_CTRLB__MODE">
        <value name="SPI" caption="SPI operating mode" value="0"/>
        <value name="MEMORY" caption="Serial Memory operating mode" value="1"/>
      </value-group>
      <value-group name="QSPI_INSTRFRAME__ADDRLEN">
        <value name="24BITS" caption="24-bits address length" value="0"/>
        <value name="32BITS" caption="32-bits address length" value="1"/>
      </value-group>
      <value-group name="QSPI_INSTRFRAME__OPTCODELEN">
        <value name="1BIT" caption="1-bit length option code" value="0x0"/>
        <value name="2BITS" caption="2-bits length option code" value="0x1"/>
        <value name="4BITS" caption="4-bits length option code" value="0x2"/>
        <value name="8BITS" caption="8-bits length option code" value="0x3"/>
      </value-group>
      <value-group name="QSPI_INSTRFRAME__TFRTYPE">
        <value name="READ" caption="Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible." value="0x0"/>
        <value name="READMEMORY" caption="Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible." value="0x1"/>
        <value name="WRITE" caption="Write transfer into the serial memory.Scrambling is not performed." value="0x2"/>
        <value name="WRITEMEMORY" caption="Write data transfer into the serial memory.If enabled, scrambling is performed." value="0x3"/>
      </value-group>
      <value-group name="QSPI_INSTRFRAME__WIDTH">
        <value name="SINGLE_BIT_SPI" caption="Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI" value="0x0"/>
        <value name="DUAL_OUTPUT" caption="Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI" value="0x1"/>
        <value name="QUAD_OUTPUT" caption="Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI" value="0x2"/>
        <value name="DUAL_IO" caption="Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI" value="0x3"/>
        <value name="QUAD_IO" caption="Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI" value="0x4"/>
        <value name="DUAL_CMD" caption="Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI" value="0x5"/>
        <value name="QUAD_CMD" caption="Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI" value="0x6"/>
      </value-group>
    </module>
    <module name="RAMECC" id="U2268" version="1.0.0" caption="RAM ECC">
      <register-group name="RAMECC" caption="RAM ECC">
        <register name="INTENCLR" offset="0x0" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
          <bitfield name="SINGLEE" caption="Single Bit ECC Error Interrupt Enable Clear" mask="0x1"/>
          <bitfield name="DUALE" caption="Dual Bit ECC Error Interrupt Enable Clear" mask="0x2"/>
        </register>
        <register name="INTENSET" offset="0x1" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
          <bitfield name="SINGLEE" caption="Single Bit ECC Error Interrupt Enable Set" mask="0x1"/>
          <bitfield name="DUALE" caption="Dual Bit ECC Error Interrupt Enable Set" mask="0x2"/>
        </register>
        <register name="INTFLAG" offset="0x2" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag">
          <bitfield name="SINGLEE" caption="Single Bit ECC Error Interrupt" mask="0x1"/>
          <bitfield name="DUALE" caption="Dual Bit ECC Error Interrupt" mask="0x2"/>
        </register>
        <register name="STATUS" offset="0x3" rw="R" size="1" initval="0x00" caption="Status">
          <bitfield name="ECCDIS" caption="ECC Disable" mask="0x1"/>
        </register>
        <register name="ERRADDR" offset="0x4" rw="R" size="4" initval="0x00000000" caption="Error Address">
          <bitfield name="ERRADDR" caption="Error Address" mask="0x1FFFF"/>
        </register>
        <register name="DBGCTRL" offset="0xF" rw="RW" size="1" initval="0x00" caption="Debug Control">
          <bitfield name="ECCDIS" caption="ECC Disable" mask="0x1"/>
          <bitfield name="ECCELOG" caption="ECC Error Log" mask="0x2"/>
        </register>
      </register-group>
    </module>
    <module name="RSTC" id="U2239" version="4.0.0" caption="Reset Controller">
      <register-group name="RSTC" caption="Reset Controller">
        <register name="RCAUSE" offset="0x0" rw="R" size="1" caption="Reset Cause">
          <bitfield name="POR" caption="Power On Reset" mask="0x1"/>
          <bitfield name="BODCORE" caption="Brown Out CORE Detector Reset" mask="0x2"/>
          <bitfield name="BODVDD" caption="Brown Out VDD Detector Reset" mask="0x4"/>
          <bitfield name="NVM" caption="NVM Reset" mask="0x8"/>
          <bitfield name="EXT" caption="External Reset" mask="0x10"/>
          <bitfield name="WDT" caption="Watchdog Reset" mask="0x20"/>
          <bitfield name="SYST" caption="System Reset Request" mask="0x40"/>
          <bitfield name="BACKUP" caption="Backup Reset" mask="0x80"/>
        </register>
        <register name="BKUPEXIT" offset="0x2" rw="R" size="1" initval="0x00" caption="Backup Exit Source">
          <bitfield name="RTC" caption="Real Timer Counter Interrupt" mask="0x2"/>
          <bitfield name="BBPS" caption="Battery Backup Power Switch" mask="0x4"/>
          <bitfield name="HIB" caption="Hibernate" mask="0x80"/>
        </register>
      </register-group>
    </module>
    <module name="RTC" id="U2250" version="2.1.0" caption="Real-Time Counter">
      <register-group name="MODE2_ALARM" size="0x8">
        <register name="ALARM" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="MODE2_ALARM Alarm n Value">
          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_ALARM_ALARM__HOUR"/>
          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
        </register>
        <register name="MASK" offset="0x4" rw="RW" access="WSYNC" size="1" initval="0x00" caption="MODE2_ALARM Alarm n Mask">
          <bitfield name="SEL" caption="Alarm Mask Selection" mask="0x7" values="RTC_MODE2_ALARM_MASK__SEL"/>
        </register>
      </register-group>
      <register-group class="union" union-tag="RTC.MODE0.CTRLA.MODE" name="RTC" caption="Real-Time Counter">
        <register-group name="MODE0" name-in-module="RTC_MODE0" union-tag-value="0" offset="0"/>
        <register-group name="MODE1" name-in-module="RTC_MODE1" union-tag-value="1" offset="0"/>
        <register-group name="MODE2" name-in-module="RTC_MODE2" union-tag-value="2" offset="0"/>
      </register-group>
      <register-group name="RTC_MODE0" caption="Real-Time Counter - 32-bit Counter with Single 32-bit Compare">
        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE0 Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE0_CTRLA__MODE"/>
          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE0_CTRLA__PRESCALER"/>
          <bitfield name="BKTRST" caption="BKUP Registers Reset On Tamper Enable" mask="0x2000"/>
          <bitfield name="GPTRST" caption="GP Registers Reset On Tamper Enable" mask="0x4000"/>
          <bitfield name="COUNTSYNC" caption="Count Read Synchronization Enable" mask="0x8000"/>
        </register>
        <register name="CTRLB" offset="0x2" rw="RW" size="2" initval="0x0000" caption="MODE0 Control B">
          <bitfield name="GP0EN" caption="General Purpose 0 Enable" mask="0x1"/>
          <bitfield name="GP2EN" caption="General Purpose 2 Enable" mask="0x2"/>
          <bitfield name="DEBMAJ" caption="Debouncer Majority Enable" mask="0x10"/>
          <bitfield name="DEBASYNC" caption="Debouncer Asynchronous Enable" mask="0x20"/>
          <bitfield name="RTCOUT" caption="RTC Output Enable" mask="0x40"/>
          <bitfield name="DMAEN" caption="DMA Enable" mask="0x80"/>
          <bitfield name="DEBF" caption="Debounce Freqnuency" mask="0x700" values="RTC_MODE0_CTRLB__DEBF"/>
          <bitfield name="ACTF" caption="Active Layer Freqnuency" mask="0x7000" values="RTC_MODE0_CTRLB__ACTF"/>
        </register>
        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="MODE0 Event Control">
          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
          <bitfield name="TAMPEREO" caption="Tamper Event Output Enable" mask="0x4000"/>
          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
          <bitfield name="TAMPEVEI" caption="Tamper Event Input Enable" mask="0x10000"/>
        </register>
        <register name="INTENCLR" offset="0x8" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="MODE0 Interrupt Enable Clear">
          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
        </register>
        <register name="INTENSET" offset="0xA" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="MODE0 Interrupt Enable Set">
          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
        </register>
        <register name="INTFLAG" offset="0xC" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="MODE0 Interrupt Flag Status and Clear">
          <bitfield name="PER0" caption="Periodic Interval 0" mask="0x1"/>
          <bitfield name="PER1" caption="Periodic Interval 1" mask="0x2"/>
          <bitfield name="PER2" caption="Periodic Interval 2" mask="0x4"/>
          <bitfield name="PER3" caption="Periodic Interval 3" mask="0x8"/>
          <bitfield name="PER4" caption="Periodic Interval 4" mask="0x10"/>
          <bitfield name="PER5" caption="Periodic Interval 5" mask="0x20"/>
          <bitfield name="PER6" caption="Periodic Interval 6" mask="0x40"/>
          <bitfield name="PER7" caption="Periodic Interval 7" mask="0x80"/>
          <bitfield name="CMP0" caption="Compare 0" mask="0x100"/>
          <bitfield name="CMP1" caption="Compare 1" mask="0x200"/>
          <bitfield name="TAMPER" caption="Tamper" mask="0x4000"/>
          <bitfield name="OVF" caption="Overflow" mask="0x8000"/>
        </register>
        <register name="DBGCTRL" offset="0xE" rw="RW" size="1" initval="0x00" caption="Debug Control">
          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
        </register>
        <register name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="MODE0 Synchronization Busy Status">
          <bitfield name="SWRST" caption="Software Reset Busy" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable Bit Busy" mask="0x2"/>
          <bitfield name="FREQCORR" caption="FREQCORR Register Busy" mask="0x4"/>
          <bitfield name="COUNT" caption="COUNT Register Busy" mask="0x8"/>
          <bitfield name="COMP0" caption="COMP 0 Register Busy" mask="0x20"/>
          <bitfield name="COMP1" caption="COMP 1 Register Busy" mask="0x40"/>
          <bitfield name="COUNTSYNC" caption="Count Synchronization Enable Bit Busy" mask="0x8000"/>
          <bitfield name="GP0" caption="General Purpose 0 Register Busy" mask="0x10000"/>
          <bitfield name="GP1" caption="General Purpose 1 Register Busy" mask="0x20000"/>
          <bitfield name="GP2" caption="General Purpose 2 Register Busy" mask="0x40000"/>
          <bitfield name="GP3" caption="General Purpose 3 Register Busy" mask="0x80000"/>
        </register>
        <register name="FREQCORR" offset="0x14" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
        </register>
        <register name="COUNT" offset="0x18" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="MODE0 Counter Value">
          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
        </register>
        <register name="COMP" offset="0x20" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="MODE0 Compare n Value">
          <bitfield name="COMP" caption="Compare Value" mask="0xFFFFFFFF"/>
        </register>
        <register name="GP" offset="0x40" rw="RW" size="4" count="4" initval="0x00000000" caption="General Purpose">
          <bitfield name="GP" caption="General Purpose" mask="0xFFFFFFFF"/>
        </register>
        <register name="TAMPCTRL" offset="0x60" rw="RW" size="4" initval="0x00000000" caption="Tamper Control">
          <bitfield name="IN0ACT" caption="Tamper Input 0 Action" mask="0x3" values="RTC_TAMPCTRL__IN0ACT"/>
          <bitfield name="IN1ACT" caption="Tamper Input 1 Action" mask="0xC" values="RTC_TAMPCTRL__IN1ACT"/>
          <bitfield name="IN2ACT" caption="Tamper Input 2 Action" mask="0x30" values="RTC_TAMPCTRL__IN2ACT"/>
          <bitfield name="IN3ACT" caption="Tamper Input 3 Action" mask="0xC0" values="RTC_TAMPCTRL__IN3ACT"/>
          <bitfield name="IN4ACT" caption="Tamper Input 4 Action" mask="0x300" values="RTC_TAMPCTRL__IN4ACT"/>
          <bitfield name="TAMLVL0" caption="Tamper Level Select 0" mask="0x10000"/>
          <bitfield name="TAMLVL1" caption="Tamper Level Select 1" mask="0x20000"/>
          <bitfield name="TAMLVL2" caption="Tamper Level Select 2" mask="0x40000"/>
          <bitfield name="TAMLVL3" caption="Tamper Level Select 3" mask="0x80000"/>
          <bitfield name="TAMLVL4" caption="Tamper Level Select 4" mask="0x100000"/>
          <bitfield name="DEBNC0" caption="Debouncer Enable 0" mask="0x1000000"/>
          <bitfield name="DEBNC1" caption="Debouncer Enable 1" mask="0x2000000"/>
          <bitfield name="DEBNC2" caption="Debouncer Enable 2" mask="0x4000000"/>
          <bitfield name="DEBNC3" caption="Debouncer Enable 3" mask="0x8000000"/>
          <bitfield name="DEBNC4" caption="Debouncer Enable 4" mask="0x10000000"/>
        </register>
        <register name="TIMESTAMP" offset="0x64" rw="R" access="RSYNC" size="4" initval="0x00000000" caption="MODE0 Timestamp">
          <bitfield name="COUNT" caption="Count Timestamp Value" mask="0xFFFFFFFF"/>
        </register>
        <register name="TAMPID" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Tamper ID">
          <bitfield name="TAMPID0" caption="Tamper Input 0 Detected" mask="0x1"/>
          <bitfield name="TAMPID1" caption="Tamper Input 1 Detected" mask="0x2"/>
          <bitfield name="TAMPID2" caption="Tamper Input 2 Detected" mask="0x4"/>
          <bitfield name="TAMPID3" caption="Tamper Input 3 Detected" mask="0x8"/>
          <bitfield name="TAMPID4" caption="Tamper Input 4 Detected" mask="0x10"/>
          <bitfield name="TAMPEVT" caption="Tamper Event Detected" mask="0x80000000"/>
        </register>
        <register name="BKUP" offset="0x80" rw="RW" size="4" count="8" initval="0x00000000" caption="Backup">
          <bitfield name="BKUP" caption="Backup" mask="0xFFFFFFFF"/>
        </register>
      </register-group>
      <register-group name="RTC_MODE1" caption="Real-Time Counter - 16-bit Counter with Two 16-bit Compares">
        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE1_CTRLA__MODE"/>
          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE1_CTRLA__PRESCALER"/>
          <bitfield name="BKTRST" caption="BKUP Registers Reset On Tamper Enable" mask="0x2000"/>
          <bitfield name="GPTRST" caption="GP Registers Reset On Tamper Enable" mask="0x4000"/>
          <bitfield name="COUNTSYNC" caption="Count Read Synchronization Enable" mask="0x8000"/>
        </register>
        <register name="CTRLB" offset="0x2" rw="RW" size="2" initval="0x0000" caption="MODE1 Control B">
          <bitfield name="GP0EN" caption="General Purpose 0 Enable" mask="0x1"/>
          <bitfield name="GP2EN" caption="General Purpose 2 Enable" mask="0x2"/>
          <bitfield name="DEBMAJ" caption="Debouncer Majority Enable" mask="0x10"/>
          <bitfield name="DEBASYNC" caption="Debouncer Asynchronous Enable" mask="0x20"/>
          <bitfield name="RTCOUT" caption="RTC Output Enable" mask="0x40"/>
          <bitfield name="DMAEN" caption="DMA Enable" mask="0x80"/>
          <bitfield name="DEBF" caption="Debounce Freqnuency" mask="0x700" values="RTC_MODE1_CTRLB__DEBF"/>
          <bitfield name="ACTF" caption="Active Layer Freqnuency" mask="0x7000" values="RTC_MODE1_CTRLB__ACTF"/>
        </register>
        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="MODE1 Event Control">
          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
          <bitfield name="CMPEO0" caption="Compare 0 Event Output Enable" mask="0x100"/>
          <bitfield name="CMPEO1" caption="Compare 1 Event Output Enable" mask="0x200"/>
          <bitfield name="CMPEO2" caption="Compare 2 Event Output Enable" mask="0x400"/>
          <bitfield name="CMPEO3" caption="Compare 3 Event Output Enable" mask="0x800"/>
          <bitfield name="TAMPEREO" caption="Tamper Event Output Enable" mask="0x4000"/>
          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
          <bitfield name="TAMPEVEI" caption="Tamper Event Input Enable" mask="0x10000"/>
        </register>
        <register name="INTENCLR" offset="0x8" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="MODE1 Interrupt Enable Clear">
          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
          <bitfield name="CMP2" caption="Compare 2 Interrupt Enable" mask="0x400"/>
          <bitfield name="CMP3" caption="Compare 3 Interrupt Enable" mask="0x800"/>
          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
        </register>
        <register name="INTENSET" offset="0xA" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="MODE1 Interrupt Enable Set">
          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
          <bitfield name="CMP0" caption="Compare 0 Interrupt Enable" mask="0x100"/>
          <bitfield name="CMP1" caption="Compare 1 Interrupt Enable" mask="0x200"/>
          <bitfield name="CMP2" caption="Compare 2 Interrupt Enable" mask="0x400"/>
          <bitfield name="CMP3" caption="Compare 3 Interrupt Enable" mask="0x800"/>
          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
        </register>
        <register name="INTFLAG" offset="0xC" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="MODE1 Interrupt Flag Status and Clear">
          <bitfield name="PER0" caption="Periodic Interval 0" mask="0x1"/>
          <bitfield name="PER1" caption="Periodic Interval 1" mask="0x2"/>
          <bitfield name="PER2" caption="Periodic Interval 2" mask="0x4"/>
          <bitfield name="PER3" caption="Periodic Interval 3" mask="0x8"/>
          <bitfield name="PER4" caption="Periodic Interval 4" mask="0x10"/>
          <bitfield name="PER5" caption="Periodic Interval 5" mask="0x20"/>
          <bitfield name="PER6" caption="Periodic Interval 6" mask="0x40"/>
          <bitfield name="PER7" caption="Periodic Interval 7" mask="0x80"/>
          <bitfield name="CMP0" caption="Compare 0" mask="0x100"/>
          <bitfield name="CMP1" caption="Compare 1" mask="0x200"/>
          <bitfield name="CMP2" caption="Compare 2" mask="0x400"/>
          <bitfield name="CMP3" caption="Compare 3" mask="0x800"/>
          <bitfield name="TAMPER" caption="Tamper" mask="0x4000"/>
          <bitfield name="OVF" caption="Overflow" mask="0x8000"/>
        </register>
        <register name="DBGCTRL" offset="0xE" rw="RW" size="1" initval="0x00" caption="Debug Control">
          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
        </register>
        <register name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="MODE1 Synchronization Busy Status">
          <bitfield name="SWRST" caption="Software Reset Bit Busy" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable Bit Busy" mask="0x2"/>
          <bitfield name="FREQCORR" caption="FREQCORR Register Busy" mask="0x4"/>
          <bitfield name="COUNT" caption="COUNT Register Busy" mask="0x8"/>
          <bitfield name="PER" caption="PER Register Busy" mask="0x10"/>
          <bitfield name="COMP0" caption="COMP 0 Register Busy" mask="0x20"/>
          <bitfield name="COMP1" caption="COMP 1 Register Busy" mask="0x40"/>
          <bitfield name="COMP2" caption="COMP 2 Register Busy" mask="0x80"/>
          <bitfield name="COMP3" caption="COMP 3 Register Busy" mask="0x100"/>
          <bitfield name="COUNTSYNC" caption="Count Synchronization Enable Bit Busy" mask="0x8000"/>
          <bitfield name="GP0" caption="General Purpose 0 Register Busy" mask="0x10000"/>
          <bitfield name="GP1" caption="General Purpose 1 Register Busy" mask="0x20000"/>
          <bitfield name="GP2" caption="General Purpose 2 Register Busy" mask="0x40000"/>
          <bitfield name="GP3" caption="General Purpose 3 Register Busy" mask="0x80000"/>
        </register>
        <register name="FREQCORR" offset="0x14" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
        </register>
        <register name="COUNT" offset="0x18" rw="RW" access="RSYNC" size="2" initval="0x0000" caption="MODE1 Counter Value">
          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
        </register>
        <register name="PER" offset="0x1C" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE1 Counter Period">
          <bitfield name="PER" caption="Counter Period" mask="0xFFFF"/>
        </register>
        <register name="COMP" offset="0x20" rw="RW" access="WSYNC" size="2" count="4" initval="0x0000" caption="MODE1 Compare n Value">
          <bitfield name="COMP" caption="Compare Value" mask="0xFFFF"/>
        </register>
        <register name="GP" offset="0x40" rw="RW" size="4" count="4" initval="0x00000000" caption="General Purpose">
          <bitfield name="GP" caption="General Purpose" mask="0xFFFFFFFF"/>
        </register>
        <register name="TAMPCTRL" offset="0x60" rw="RW" size="4" initval="0x00000000" caption="Tamper Control">
          <bitfield name="IN0ACT" caption="Tamper Input 0 Action" mask="0x3" values="RTC_TAMPCTRL__IN0ACT"/>
          <bitfield name="IN1ACT" caption="Tamper Input 1 Action" mask="0xC" values="RTC_TAMPCTRL__IN1ACT"/>
          <bitfield name="IN2ACT" caption="Tamper Input 2 Action" mask="0x30" values="RTC_TAMPCTRL__IN2ACT"/>
          <bitfield name="IN3ACT" caption="Tamper Input 3 Action" mask="0xC0" values="RTC_TAMPCTRL__IN3ACT"/>
          <bitfield name="IN4ACT" caption="Tamper Input 4 Action" mask="0x300" values="RTC_TAMPCTRL__IN4ACT"/>
          <bitfield name="TAMLVL0" caption="Tamper Level Select 0" mask="0x10000"/>
          <bitfield name="TAMLVL1" caption="Tamper Level Select 1" mask="0x20000"/>
          <bitfield name="TAMLVL2" caption="Tamper Level Select 2" mask="0x40000"/>
          <bitfield name="TAMLVL3" caption="Tamper Level Select 3" mask="0x80000"/>
          <bitfield name="TAMLVL4" caption="Tamper Level Select 4" mask="0x100000"/>
          <bitfield name="DEBNC0" caption="Debouncer Enable 0" mask="0x1000000"/>
          <bitfield name="DEBNC1" caption="Debouncer Enable 1" mask="0x2000000"/>
          <bitfield name="DEBNC2" caption="Debouncer Enable 2" mask="0x4000000"/>
          <bitfield name="DEBNC3" caption="Debouncer Enable 3" mask="0x8000000"/>
          <bitfield name="DEBNC4" caption="Debouncer Enable 4" mask="0x10000000"/>
        </register>
        <register name="TIMESTAMP" offset="0x64" rw="R" access="RSYNC" size="4" initval="0x00000000" caption="MODE1 Timestamp">
          <bitfield name="COUNT" caption="Count Timestamp Value" mask="0xFFFF"/>
        </register>
        <register name="TAMPID" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Tamper ID">
          <bitfield name="TAMPID0" caption="Tamper Input 0 Detected" mask="0x1"/>
          <bitfield name="TAMPID1" caption="Tamper Input 1 Detected" mask="0x2"/>
          <bitfield name="TAMPID2" caption="Tamper Input 2 Detected" mask="0x4"/>
          <bitfield name="TAMPID3" caption="Tamper Input 3 Detected" mask="0x8"/>
          <bitfield name="TAMPID4" caption="Tamper Input 4 Detected" mask="0x10"/>
          <bitfield name="TAMPEVT" caption="Tamper Event Detected" mask="0x80000000"/>
        </register>
        <register name="BKUP" offset="0x80" rw="RW" size="4" count="8" initval="0x00000000" caption="Backup">
          <bitfield name="BKUP" caption="Backup" mask="0xFFFFFFFF"/>
        </register>
      </register-group>
      <register-group name="RTC_MODE2" caption="Real-Time Counter - Clock/Calendar with Alarm">
        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="MODE2 Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="MODE" caption="Operating Mode" mask="0xC" values="RTC_MODE2_CTRLA__MODE"/>
          <bitfield name="CLKREP" caption="Clock Representation" mask="0x40"/>
          <bitfield name="MATCHCLR" caption="Clear on Match" mask="0x80"/>
          <bitfield name="PRESCALER" caption="Prescaler" mask="0xF00" values="RTC_MODE2_CTRLA__PRESCALER"/>
          <bitfield name="BKTRST" caption="BKUP Registers Reset On Tamper Enable" mask="0x2000"/>
          <bitfield name="GPTRST" caption="GP Registers Reset On Tamper Enable" mask="0x4000"/>
          <bitfield name="CLOCKSYNC" caption="Clock Read Synchronization Enable" mask="0x8000"/>
        </register>
        <register name="CTRLB" offset="0x2" rw="RW" size="2" initval="0x0000" caption="MODE2 Control B">
          <bitfield name="GP0EN" caption="General Purpose 0 Enable" mask="0x1"/>
          <bitfield name="GP2EN" caption="General Purpose 2 Enable" mask="0x2"/>
          <bitfield name="DEBMAJ" caption="Debouncer Majority Enable" mask="0x10"/>
          <bitfield name="DEBASYNC" caption="Debouncer Asynchronous Enable" mask="0x20"/>
          <bitfield name="RTCOUT" caption="RTC Output Enable" mask="0x40"/>
          <bitfield name="DMAEN" caption="DMA Enable" mask="0x80"/>
          <bitfield name="DEBF" caption="Debounce Freqnuency" mask="0x700" values="RTC_MODE2_CTRLB__DEBF"/>
          <bitfield name="ACTF" caption="Active Layer Freqnuency" mask="0x7000" values="RTC_MODE2_CTRLB__ACTF"/>
        </register>
        <register name="EVCTRL" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="MODE2 Event Control">
          <bitfield name="PEREO0" caption="Periodic Interval 0 Event Output Enable" mask="0x1"/>
          <bitfield name="PEREO1" caption="Periodic Interval 1 Event Output Enable" mask="0x2"/>
          <bitfield name="PEREO2" caption="Periodic Interval 2 Event Output Enable" mask="0x4"/>
          <bitfield name="PEREO3" caption="Periodic Interval 3 Event Output Enable" mask="0x8"/>
          <bitfield name="PEREO4" caption="Periodic Interval 4 Event Output Enable" mask="0x10"/>
          <bitfield name="PEREO5" caption="Periodic Interval 5 Event Output Enable" mask="0x20"/>
          <bitfield name="PEREO6" caption="Periodic Interval 6 Event Output Enable" mask="0x40"/>
          <bitfield name="PEREO7" caption="Periodic Interval 7 Event Output Enable" mask="0x80"/>
          <bitfield name="ALARMEO0" caption="Alarm 0 Event Output Enable" mask="0x100"/>
          <bitfield name="ALARMEO1" caption="Alarm 1 Event Output Enable" mask="0x200"/>
          <bitfield name="TAMPEREO" caption="Tamper Event Output Enable" mask="0x4000"/>
          <bitfield name="OVFEO" caption="Overflow Event Output Enable" mask="0x8000"/>
          <bitfield name="TAMPEVEI" caption="Tamper Event Input Enable" mask="0x10000"/>
        </register>
        <register name="INTENCLR" offset="0x8" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="MODE2 Interrupt Enable Clear">
          <bitfield name="PER0" caption="Periodic Interval 0 Interrupt Enable" mask="0x1"/>
          <bitfield name="PER1" caption="Periodic Interval 1 Interrupt Enable" mask="0x2"/>
          <bitfield name="PER2" caption="Periodic Interval 2 Interrupt Enable" mask="0x4"/>
          <bitfield name="PER3" caption="Periodic Interval 3 Interrupt Enable" mask="0x8"/>
          <bitfield name="PER4" caption="Periodic Interval 4 Interrupt Enable" mask="0x10"/>
          <bitfield name="PER5" caption="Periodic Interval 5 Interrupt Enable" mask="0x20"/>
          <bitfield name="PER6" caption="Periodic Interval 6 Interrupt Enable" mask="0x40"/>
          <bitfield name="PER7" caption="Periodic Interval 7 Interrupt Enable" mask="0x80"/>
          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x100"/>
          <bitfield name="ALARM1" caption="Alarm 1 Interrupt Enable" mask="0x200"/>
          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
        </register>
        <register name="INTENSET" offset="0xA" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="MODE2 Interrupt Enable Set">
          <bitfield name="PER0" caption="Periodic Interval 0 Enable" mask="0x1"/>
          <bitfield name="PER1" caption="Periodic Interval 1 Enable" mask="0x2"/>
          <bitfield name="PER2" caption="Periodic Interval 2 Enable" mask="0x4"/>
          <bitfield name="PER3" caption="Periodic Interval 3 Enable" mask="0x8"/>
          <bitfield name="PER4" caption="Periodic Interval 4 Enable" mask="0x10"/>
          <bitfield name="PER5" caption="Periodic Interval 5 Enable" mask="0x20"/>
          <bitfield name="PER6" caption="Periodic Interval 6 Enable" mask="0x40"/>
          <bitfield name="PER7" caption="Periodic Interval 7 Enable" mask="0x80"/>
          <bitfield name="ALARM0" caption="Alarm 0 Interrupt Enable" mask="0x100"/>
          <bitfield name="ALARM1" caption="Alarm 1 Interrupt Enable" mask="0x200"/>
          <bitfield name="TAMPER" caption="Tamper Enable" mask="0x4000"/>
          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x8000"/>
        </register>
        <register name="INTFLAG" offset="0xC" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="MODE2 Interrupt Flag Status and Clear">
          <bitfield name="PER0" caption="Periodic Interval 0" mask="0x1"/>
          <bitfield name="PER1" caption="Periodic Interval 1" mask="0x2"/>
          <bitfield name="PER2" caption="Periodic Interval 2" mask="0x4"/>
          <bitfield name="PER3" caption="Periodic Interval 3" mask="0x8"/>
          <bitfield name="PER4" caption="Periodic Interval 4" mask="0x10"/>
          <bitfield name="PER5" caption="Periodic Interval 5" mask="0x20"/>
          <bitfield name="PER6" caption="Periodic Interval 6" mask="0x40"/>
          <bitfield name="PER7" caption="Periodic Interval 7" mask="0x80"/>
          <bitfield name="ALARM0" caption="Alarm 0" mask="0x100"/>
          <bitfield name="ALARM1" caption="Alarm 1" mask="0x200"/>
          <bitfield name="TAMPER" caption="Tamper" mask="0x4000"/>
          <bitfield name="OVF" caption="Overflow" mask="0x8000"/>
        </register>
        <register name="DBGCTRL" offset="0xE" rw="RW" size="1" initval="0x00" caption="Debug Control">
          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
        </register>
        <register name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="MODE2 Synchronization Busy Status">
          <bitfield name="SWRST" caption="Software Reset Bit Busy" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable Bit Busy" mask="0x2"/>
          <bitfield name="FREQCORR" caption="FREQCORR Register Busy" mask="0x4"/>
          <bitfield name="CLOCK" caption="CLOCK Register Busy" mask="0x8"/>
          <bitfield name="ALARM0" caption="ALARM 0 Register Busy" mask="0x20"/>
          <bitfield name="ALARM1" caption="ALARM 1 Register Busy" mask="0x40"/>
          <bitfield name="MASK0" caption="MASK 0 Register Busy" mask="0x800"/>
          <bitfield name="MASK1" caption="MASK 1 Register Busy" mask="0x1000"/>
          <bitfield name="CLOCKSYNC" caption="Clock Synchronization Enable Bit Busy" mask="0x8000"/>
          <bitfield name="GP0" caption="General Purpose 0 Register Busy" mask="0x10000"/>
          <bitfield name="GP1" caption="General Purpose 1 Register Busy" mask="0x20000"/>
          <bitfield name="GP2" caption="General Purpose 2 Register Busy" mask="0x40000"/>
          <bitfield name="GP3" caption="General Purpose 3 Register Busy" mask="0x80000"/>
        </register>
        <register name="FREQCORR" offset="0x14" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Frequency Correction">
          <bitfield name="VALUE" caption="Correction Value" mask="0x7F"/>
          <bitfield name="SIGN" caption="Correction Sign" mask="0x80"/>
        </register>
        <register name="CLOCK" offset="0x18" rw="RW" access="RSYNC" size="4" initval="0x00000000" caption="MODE2 Clock Value">
          <bitfield name="SECOND" caption="Second" mask="0x3F"/>
          <bitfield name="MINUTE" caption="Minute" mask="0xFC0"/>
          <bitfield name="HOUR" caption="Hour" mask="0x1F000" values="RTC_MODE2_CLOCK__HOUR"/>
          <bitfield name="DAY" caption="Day" mask="0x3E0000"/>
          <bitfield name="MONTH" caption="Month" mask="0x3C00000"/>
          <bitfield name="YEAR" caption="Year" mask="0xFC000000"/>
        </register>
        <register-group name="MODE2_ALARM" name-in-module="MODE2_ALARM" offset="0x20" count="2"/>
        <register name="GP" offset="0x40" rw="RW" size="4" count="4" initval="0x00000000" caption="General Purpose">
          <bitfield name="GP" caption="General Purpose" mask="0xFFFFFFFF"/>
        </register>
        <register name="TAMPCTRL" offset="0x60" rw="RW" size="4" initval="0x00000000" caption="Tamper Control">
          <bitfield name="IN0ACT" caption="Tamper Input 0 Action" mask="0x3" values="RTC_TAMPCTRL__IN0ACT"/>
          <bitfield name="IN1ACT" caption="Tamper Input 1 Action" mask="0xC" values="RTC_TAMPCTRL__IN1ACT"/>
          <bitfield name="IN2ACT" caption="Tamper Input 2 Action" mask="0x30" values="RTC_TAMPCTRL__IN2ACT"/>
          <bitfield name="IN3ACT" caption="Tamper Input 3 Action" mask="0xC0" values="RTC_TAMPCTRL__IN3ACT"/>
          <bitfield name="IN4ACT" caption="Tamper Input 4 Action" mask="0x300" values="RTC_TAMPCTRL__IN4ACT"/>
          <bitfield name="TAMLVL0" caption="Tamper Level Select 0" mask="0x10000"/>
          <bitfield name="TAMLVL1" caption="Tamper Level Select 1" mask="0x20000"/>
          <bitfield name="TAMLVL2" caption="Tamper Level Select 2" mask="0x40000"/>
          <bitfield name="TAMLVL3" caption="Tamper Level Select 3" mask="0x80000"/>
          <bitfield name="TAMLVL4" caption="Tamper Level Select 4" mask="0x100000"/>
          <bitfield name="DEBNC0" caption="Debouncer Enable 0" mask="0x1000000"/>
          <bitfield name="DEBNC1" caption="Debouncer Enable 1" mask="0x2000000"/>
          <bitfield name="DEBNC2" caption="Debouncer Enable 2" mask="0x4000000"/>
          <bitfield name="DEBNC3" caption="Debouncer Enable 3" mask="0x8000000"/>
          <bitfield name="DEBNC4" caption="Debouncer Enable 4" mask="0x10000000"/>
        </register>
        <register name="TIMESTAMP" offset="0x64" rw="R" access="RSYNC" size="4" initval="0x00000000" caption="MODE2 Timestamp">
          <bitfield name="SECOND" caption="Second Timestamp Value" mask="0x3F"/>
          <bitfield name="MINUTE" caption="Minute Timestamp Value" mask="0xFC0"/>
          <bitfield name="HOUR" caption="Hour Timestamp Value" mask="0x1F000" values="RTC_MODE2_TIMESTAMP__HOUR"/>
          <bitfield name="DAY" caption="Day Timestamp Value" mask="0x3E0000"/>
          <bitfield name="MONTH" caption="Month Timestamp Value" mask="0x3C00000"/>
          <bitfield name="YEAR" caption="Year Timestamp Value" mask="0xFC000000"/>
        </register>
        <register name="TAMPID" offset="0x68" rw="RW" size="4" initval="0x00000000" caption="Tamper ID">
          <bitfield name="TAMPID0" caption="Tamper Input 0 Detected" mask="0x1"/>
          <bitfield name="TAMPID1" caption="Tamper Input 1 Detected" mask="0x2"/>
          <bitfield name="TAMPID2" caption="Tamper Input 2 Detected" mask="0x4"/>
          <bitfield name="TAMPID3" caption="Tamper Input 3 Detected" mask="0x8"/>
          <bitfield name="TAMPID4" caption="Tamper Input 4 Detected" mask="0x10"/>
          <bitfield name="TAMPEVT" caption="Tamper Event Detected" mask="0x80000000"/>
        </register>
        <register name="BKUP" offset="0x80" rw="RW" size="4" count="8" initval="0x00000000" caption="Backup">
          <bitfield name="BKUP" caption="Backup" mask="0xFFFFFFFF"/>
        </register>
      </register-group>
      <value-group name="RTC_MODE0_CTRLA__MODE">
        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0x0"/>
        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="0x1"/>
        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="0x2"/>
      </value-group>
      <value-group name="RTC_MODE0_CTRLA__PRESCALER">
        <value name="OFF" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x1"/>
        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x2"/>
        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x3"/>
        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x4"/>
        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x5"/>
        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x6"/>
        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x7"/>
        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x8"/>
        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x9"/>
        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0xA"/>
        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xB"/>
      </value-group>
      <value-group name="RTC_MODE1_CTRLA__MODE">
        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0"/>
        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="1"/>
        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="2"/>
      </value-group>
      <value-group name="RTC_MODE1_CTRLA__PRESCALER">
        <value name="OFF" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0"/>
        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="1"/>
        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="2"/>
        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="3"/>
        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="4"/>
        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="5"/>
        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="6"/>
        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="7"/>
        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="8"/>
        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="9"/>
        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0xA"/>
        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xB"/>
      </value-group>
      <value-group name="RTC_MODE2_CTRLA__MODE">
        <value name="COUNT32" caption="Mode 0: 32-bit Counter" value="0"/>
        <value name="COUNT16" caption="Mode 1: 16-bit Counter" value="1"/>
        <value name="CLOCK" caption="Mode 2: Clock/Calendar" value="2"/>
      </value-group>
      <value-group name="RTC_MODE2_CTRLA__PRESCALER">
        <value name="OFF" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x0"/>
        <value name="DIV1" caption="CLK_RTC_CNT = GCLK_RTC/1" value="0x1"/>
        <value name="DIV2" caption="CLK_RTC_CNT = GCLK_RTC/2" value="0x2"/>
        <value name="DIV4" caption="CLK_RTC_CNT = GCLK_RTC/4" value="0x3"/>
        <value name="DIV8" caption="CLK_RTC_CNT = GCLK_RTC/8" value="0x4"/>
        <value name="DIV16" caption="CLK_RTC_CNT = GCLK_RTC/16" value="0x5"/>
        <value name="DIV32" caption="CLK_RTC_CNT = GCLK_RTC/32" value="0x6"/>
        <value name="DIV64" caption="CLK_RTC_CNT = GCLK_RTC/64" value="0x7"/>
        <value name="DIV128" caption="CLK_RTC_CNT = GCLK_RTC/128" value="0x8"/>
        <value name="DIV256" caption="CLK_RTC_CNT = GCLK_RTC/256" value="0x9"/>
        <value name="DIV512" caption="CLK_RTC_CNT = GCLK_RTC/512" value="0xA"/>
        <value name="DIV1024" caption="CLK_RTC_CNT = GCLK_RTC/1024" value="0xB"/>
      </value-group>
      <value-group name="RTC_MODE0_CTRLB__ACTF">
        <value name="DIV2" caption="CLK_RTC_OUT = CLK_RTC/2" value="0x0"/>
        <value name="DIV4" caption="CLK_RTC_OUT = CLK_RTC/4" value="0x1"/>
        <value name="DIV8" caption="CLK_RTC_OUT = CLK_RTC/8" value="0x2"/>
        <value name="DIV16" caption="CLK_RTC_OUT = CLK_RTC/16" value="0x3"/>
        <value name="DIV32" caption="CLK_RTC_OUT = CLK_RTC/32" value="0x4"/>
        <value name="DIV64" caption="CLK_RTC_OUT = CLK_RTC/64" value="0x5"/>
        <value name="DIV128" caption="CLK_RTC_OUT = CLK_RTC/128" value="0x6"/>
        <value name="DIV256" caption="CLK_RTC_OUT = CLK_RTC/256" value="0x7"/>
      </value-group>
      <value-group name="RTC_MODE0_CTRLB__DEBF">
        <value name="DIV2" caption="CLK_RTC_DEB = CLK_RTC/2" value="0x0"/>
        <value name="DIV4" caption="CLK_RTC_DEB = CLK_RTC/4" value="0x1"/>
        <value name="DIV8" caption="CLK_RTC_DEB = CLK_RTC/8" value="0x2"/>
        <value name="DIV16" caption="CLK_RTC_DEB = CLK_RTC/16" value="0x3"/>
        <value name="DIV32" caption="CLK_RTC_DEB = CLK_RTC/32" value="0x4"/>
        <value name="DIV64" caption="CLK_RTC_DEB = CLK_RTC/64" value="0x5"/>
        <value name="DIV128" caption="CLK_RTC_DEB = CLK_RTC/128" value="0x6"/>
        <value name="DIV256" caption="CLK_RTC_DEB = CLK_RTC/256" value="0x7"/>
      </value-group>
      <value-group name="RTC_MODE1_CTRLB__ACTF">
        <value name="DIV2" caption="CLK_RTC_OUT = CLK_RTC/2" value="0x0"/>
        <value name="DIV4" caption="CLK_RTC_OUT = CLK_RTC/4" value="0x1"/>
        <value name="DIV8" caption="CLK_RTC_OUT = CLK_RTC/8" value="0x2"/>
        <value name="DIV16" caption="CLK_RTC_OUT = CLK_RTC/16" value="0x3"/>
        <value name="DIV32" caption="CLK_RTC_OUT = CLK_RTC/32" value="0x4"/>
        <value name="DIV64" caption="CLK_RTC_OUT = CLK_RTC/64" value="0x5"/>
        <value name="DIV128" caption="CLK_RTC_OUT = CLK_RTC/128" value="0x6"/>
        <value name="DIV256" caption="CLK_RTC_OUT = CLK_RTC/256" value="0x7"/>
      </value-group>
      <value-group name="RTC_MODE1_CTRLB__DEBF">
        <value name="DIV2" caption="CLK_RTC_DEB = CLK_RTC/2" value="0x0"/>
        <value name="DIV4" caption="CLK_RTC_DEB = CLK_RTC/4" value="0x1"/>
        <value name="DIV8" caption="CLK_RTC_DEB = CLK_RTC/8" value="0x2"/>
        <value name="DIV16" caption="CLK_RTC_DEB = CLK_RTC/16" value="0x3"/>
        <value name="DIV32" caption="CLK_RTC_DEB = CLK_RTC/32" value="0x4"/>
        <value name="DIV64" caption="CLK_RTC_DEB = CLK_RTC/64" value="0x5"/>
        <value name="DIV128" caption="CLK_RTC_DEB = CLK_RTC/128" value="0x6"/>
        <value name="DIV256" caption="CLK_RTC_DEB = CLK_RTC/256" value="0x7"/>
      </value-group>
      <value-group name="RTC_MODE2_CTRLB__ACTF">
        <value name="DIV2" caption="CLK_RTC_OUT = CLK_RTC/2" value="0x0"/>
        <value name="DIV4" caption="CLK_RTC_OUT = CLK_RTC/4" value="0x1"/>
        <value name="DIV8" caption="CLK_RTC_OUT = CLK_RTC/8" value="0x2"/>
        <value name="DIV16" caption="CLK_RTC_OUT = CLK_RTC/16" value="0x3"/>
        <value name="DIV32" caption="CLK_RTC_OUT = CLK_RTC/32" value="0x4"/>
        <value name="DIV64" caption="CLK_RTC_OUT = CLK_RTC/64" value="0x5"/>
        <value name="DIV128" caption="CLK_RTC_OUT = CLK_RTC/128" value="0x6"/>
        <value name="DIV256" caption="CLK_RTC_OUT = CLK_RTC/256" value="0x7"/>
      </value-group>
      <value-group name="RTC_MODE2_CTRLB__DEBF">
        <value name="DIV2" caption="CLK_RTC_DEB = CLK_RTC/2" value="0x0"/>
        <value name="DIV4" caption="CLK_RTC_DEB = CLK_RTC/4" value="0x1"/>
        <value name="DIV8" caption="CLK_RTC_DEB = CLK_RTC/8" value="0x2"/>
        <value name="DIV16" caption="CLK_RTC_DEB = CLK_RTC/16" value="0x3"/>
        <value name="DIV32" caption="CLK_RTC_DEB = CLK_RTC/32" value="0x4"/>
        <value name="DIV64" caption="CLK_RTC_DEB = CLK_RTC/64" value="0x5"/>
        <value name="DIV128" caption="CLK_RTC_DEB = CLK_RTC/128" value="0x6"/>
        <value name="DIV256" caption="CLK_RTC_DEB = CLK_RTC/256" value="0x7"/>
      </value-group>
      <value-group name="RTC_MODE2_CLOCK__HOUR">
        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
      </value-group>
      <value-group name="RTC_MODE2_ALARM_ALARM__HOUR">
        <value name="AM" caption="Morning hour" value="0x00"/>
        <value name="PM" caption="Afternoon hour" value="0x10"/>
      </value-group>
      <value-group name="RTC_MODE2_ALARM_MASK__SEL">
        <value name="OFF" caption="Alarm Disabled" value="0x0"/>
        <value name="SS" caption="Match seconds only" value="0x1"/>
        <value name="MMSS" caption="Match seconds and minutes only" value="0x2"/>
        <value name="HHMMSS" caption="Match seconds, minutes, and hours only" value="0x3"/>
        <value name="DDHHMMSS" caption="Match seconds, minutes, hours, and days only" value="0x4"/>
        <value name="MMDDHHMMSS" caption="Match seconds, minutes, hours, days, and months only" value="0x5"/>
        <value name="YYMMDDHHMMSS" caption="Match seconds, minutes, hours, days, months, and years" value="0x6"/>
      </value-group>
      <value-group name="RTC_TAMPCTRL__IN0ACT">
        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
        <value name="WAKE" caption="Wake without timestamp" value="0x1"/>
        <value name="CAPTURE" caption="Capture timestamp" value="0x2"/>
        <value name="ACTL" caption="Compare IN0 to OUT" value="0x3"/>
      </value-group>
      <value-group name="RTC_TAMPCTRL__IN1ACT">
        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
        <value name="WAKE" caption="Wake without timestamp" value="0x1"/>
        <value name="CAPTURE" caption="Capture timestamp" value="0x2"/>
        <value name="ACTL" caption="Compare IN1 to OUT" value="0x3"/>
      </value-group>
      <value-group name="RTC_TAMPCTRL__IN2ACT">
        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
        <value name="WAKE" caption="Wake without timestamp" value="0x1"/>
        <value name="CAPTURE" caption="Capture timestamp" value="0x2"/>
        <value name="ACTL" caption="Compare IN2 to OUT" value="0x3"/>
      </value-group>
      <value-group name="RTC_TAMPCTRL__IN3ACT">
        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
        <value name="WAKE" caption="Wake without timestamp" value="0x1"/>
        <value name="CAPTURE" caption="Capture timestamp" value="0x2"/>
        <value name="ACTL" caption="Compare IN3 to OUT" value="0x3"/>
      </value-group>
      <value-group name="RTC_TAMPCTRL__IN4ACT">
        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
        <value name="WAKE" caption="Wake without timestamp" value="0x1"/>
        <value name="CAPTURE" caption="Capture timestamp" value="0x2"/>
        <value name="ACTL" caption="Compare IN4 to OUT" value="0x3"/>
      </value-group>
      <value-group name="RTC_TAMPCTRL__IN5ACT">
        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
        <value name="WAKE" caption="Wake without timestamp" value="0x1"/>
        <value name="CAPTURE" caption="Capture timestamp" value="0x2"/>
        <value name="ACTL" caption="Compare IN5 to OUT" value="0x3"/>
      </value-group>
      <value-group name="RTC_TAMPCTRL__IN6ACT">
        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
        <value name="WAKE" caption="Wake without timestamp" value="0x1"/>
        <value name="CAPTURE" caption="Capture timestamp" value="0x2"/>
        <value name="ACTL" caption="Compare IN6 to OUT" value="0x3"/>
      </value-group>
      <value-group name="RTC_TAMPCTRL__IN7ACT">
        <value name="OFF" caption="Off (Disabled)" value="0x0"/>
        <value name="WAKE" caption="Wake without timestamp" value="0x1"/>
        <value name="CAPTURE" caption="Capture timestamp" value="0x2"/>
        <value name="ACTL" caption="Compare IN7 to OUT" value="0x3"/>
      </value-group>
      <value-group name="RTC_MODE2_TIMESTAMP__HOUR">
        <value name="AM" caption="AM when CLKREP in 12-hour" value="0x00"/>
        <value name="PM" caption="PM when CLKREP in 12-hour" value="0x10"/>
      </value-group>
    </module>
    <module name="SDHC" id="U2011" version="1.8.3" caption="SD/MMC Host Controller">
      <register-group name="SDHC" caption="SD/MMC Host Controller">
        <register name="SSAR" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SDMA System Address / Argument 2">
          <mode name="CMD23">
            <bitfield name="ARG2" caption="Argument 2" mask="0xFFFFFFFF"/>
          </mode>
          <mode name="DEFAULT_MODE">
            <bitfield name="ADDR" caption="SDMA System Address" mask="0xFFFFFFFF"/>
          </mode>
        </register>
        <register name="BSR" offset="0x4" rw="RW" size="2" initval="0x0000" caption="Block Size">
          <bitfield name="BLOCKSIZE" caption="Transfer Block Size" mask="0x3FF"/>
          <bitfield name="BOUNDARY" caption="SDMA Buffer Boundary" mask="0x7000" values="SDHC_BSR__BOUNDARY"/>
        </register>
        <register name="BCR" offset="0x6" rw="RW" size="2" initval="0x0000" caption="Block Count">
          <bitfield name="BCNT" caption="Blocks Count for Current Transfer" mask="0xFFFF"/>
        </register>
        <register name="ARG1R" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="Argument 1">
          <bitfield name="ARG" caption="Argument 1" mask="0xFFFFFFFF"/>
        </register>
        <register name="TMR" offset="0xC" rw="RW" size="2" initval="0x0000" caption="Transfer Mode">
          <bitfield name="DMAEN" caption="DMA Enable" mask="0x1" values="SDHC_TMR__DMAEN"/>
          <bitfield name="BCEN" caption="Block Count Enable" mask="0x2" values="SDHC_TMR__BCEN"/>
          <bitfield name="ACMDEN" caption="Auto Command Enable" mask="0xC" values="SDHC_TMR__ACMDEN"/>
          <bitfield name="DTDSEL" caption="Data Transfer Direction Selection" mask="0x10" values="SDHC_TMR__DTDSEL"/>
          <bitfield name="MSBSEL" caption="Multi/Single Block Selection" mask="0x20" values="SDHC_TMR__MSBSEL"/>
        </register>
        <register name="CR" offset="0xE" rw="RW" size="2" initval="0x0000" caption="Command">
          <bitfield name="RESPTYP" caption="Response Type" mask="0x3" values="SDHC_CR__RESPTYP"/>
          <bitfield name="CMDCCEN" caption="Command CRC Check Enable" mask="0x8" values="SDHC_CR__CMDCCEN"/>
          <bitfield name="CMDICEN" caption="Command Index Check Enable" mask="0x10" values="SDHC_CR__CMDICEN"/>
          <bitfield name="DPSEL" caption="Data Present Select" mask="0x20" values="SDHC_CR__DPSEL"/>
          <bitfield name="CMDTYP" caption="Command Type" mask="0xC0" values="SDHC_CR__CMDTYP"/>
          <bitfield name="CMDIDX" caption="Command Index" mask="0x3F00"/>
        </register>
        <register name="RR" offset="0x10" rw="R" size="4" count="4" initval="0x00000000" caption="Response">
          <bitfield name="CMDRESP" caption="Command Response" mask="0xFFFFFFFF"/>
        </register>
        <register name="BDPR" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Buffer Data Port">
          <bitfield name="BUFDATA" caption="Buffer Data" mask="0xFFFFFFFF"/>
        </register>
        <register name="PSR" offset="0x24" rw="R" size="4" initval="0x00F80000" caption="Present State">
          <bitfield name="CMDINHC" caption="Command Inhibit (CMD)" mask="0x1" values="SDHC_PSR__CMDINHC"/>
          <bitfield name="CMDINHD" caption="Command Inhibit (DAT)" mask="0x2" values="SDHC_PSR__CMDINHD"/>
          <bitfield name="DLACT" caption="DAT Line Active" mask="0x4" values="SDHC_PSR__DLACT"/>
          <bitfield name="RTREQ" caption="Re-Tuning Request" mask="0x8" values="SDHC_PSR__RTREQ"/>
          <bitfield name="WTACT" caption="Write Transfer Active" mask="0x100" values="SDHC_PSR__WTACT"/>
          <bitfield name="RTACT" caption="Read Transfer Active" mask="0x200" values="SDHC_PSR__RTACT"/>
          <bitfield name="BUFWREN" caption="Buffer Write Enable" mask="0x400" values="SDHC_PSR__BUFWREN"/>
          <bitfield name="BUFRDEN" caption="Buffer Read Enable" mask="0x800" values="SDHC_PSR__BUFRDEN"/>
          <bitfield name="CARDINS" caption="Card Inserted" mask="0x10000" values="SDHC_PSR__CARDINS"/>
          <bitfield name="CARDSS" caption="Card State Stable" mask="0x20000" values="SDHC_PSR__CARDSS"/>
          <bitfield name="CARDDPL" caption="Card Detect Pin Level" mask="0x40000" values="SDHC_PSR__CARDDPL"/>
          <bitfield name="WRPPL" caption="Write Protect Pin Level" mask="0x80000" values="SDHC_PSR__WRPPL"/>
          <bitfield name="DATLL" caption="DAT[3:0] Line Level" mask="0xF00000"/>
          <bitfield name="CMDLL" caption="CMD Line Level" mask="0x1000000"/>
        </register>
        <register name="HC1R" offset="0x28" rw="RW" size="1" initval="0xE00" caption="Host Control 1">
          <mode name="DEFAULT_MODE">
            <bitfield name="LEDCTRL" caption="LED Control" mask="0x1" values="SDHC_HC1R__LEDCTRL"/>
            <bitfield name="DW" caption="Data Width" mask="0x2" values="SDHC_HC1R__DW"/>
            <bitfield name="HSEN" caption="High Speed Enable" mask="0x4" values="SDHC_HC1R__HSEN"/>
            <bitfield name="DMASEL" caption="DMA Select" mask="0x18" values="SDHC_HC1R__DMASEL"/>
            <bitfield name="CARDDTL" caption="Card Detect Test Level" mask="0x40" values="SDHC_HC1R__CARDDTL"/>
            <bitfield name="CARDDSEL" caption="Card Detect Signal Selection" mask="0x80" values="SDHC_HC1R__CARDDSEL"/>
          </mode>
          <mode name="EMMC">
            <bitfield name="DW" caption="Data Width" mask="0x2" values="SDHC_HC1R__DW"/>
            <bitfield name="HSEN" caption="High Speed Enable" mask="0x4" values="SDHC_HC1R__HSEN"/>
            <bitfield name="DMASEL" caption="DMA Select" mask="0x18" values="SDHC_HC1R__DMASEL"/>
          </mode>
        </register>
        <register name="PCR" offset="0x29" rw="RW" size="1" initval="0x0E" caption="Power Control">
          <bitfield name="SDBPWR" caption="SD Bus Power" mask="0x1" values="SDHC_PCR__SDBPWR"/>
          <bitfield name="SDBVSEL" caption="SD Bus Voltage Select" mask="0xE" values="SDHC_PCR__SDBVSEL"/>
        </register>
        <register name="BGCR" offset="0x2A" rw="RW" size="1" initval="0x00" caption="Block Gap Control">
          <mode name="DEFAULT_MODE">
            <bitfield name="STPBGR" caption="Stop at Block Gap Request" mask="0x1" values="SDHC_BGCR__STPBGR"/>
            <bitfield name="CONTR" caption="Continue Request" mask="0x2" values="SDHC_BGCR__CONTR"/>
            <bitfield name="RWCTRL" caption="Read Wait Control" mask="0x4" values="SDHC_BGCR__RWCTRL"/>
            <bitfield name="INTBG" caption="Interrupt at Block Gap" mask="0x8" values="SDHC_BGCR__INTBG"/>
          </mode>
          <mode name="EMMC">
            <bitfield name="STPBGR" caption="Stop at Block Gap Request" mask="0x1" values="SDHC_BGCR__STPBGR"/>
            <bitfield name="CONTR" caption="Continue Request" mask="0x2" values="SDHC_BGCR__CONTR"/>
          </mode>
        </register>
        <register name="WCR" offset="0x2B" rw="RW" size="1" initval="0x00" caption="Wakeup Control">
          <bitfield name="WKENCINT" caption="Wakeup Event Enable on Card Interrupt" mask="0x1" values="SDHC_WCR__WKENCINT"/>
          <bitfield name="WKENCINS" caption="Wakeup Event Enable on Card Insertion" mask="0x2" values="SDHC_WCR__WKENCINS"/>
          <bitfield name="WKENCREM" caption="Wakeup Event Enable on Card Removal" mask="0x4" values="SDHC_WCR__WKENCREM"/>
        </register>
        <register name="CCR" offset="0x2C" rw="RW" size="2" initval="0x0000" caption="Clock Control">
          <bitfield name="INTCLKEN" caption="Internal Clock Enable" mask="0x1" values="SDHC_CCR__INTCLKEN"/>
          <bitfield name="INTCLKS" caption="Internal Clock Stable" mask="0x2" values="SDHC_CCR__INTCLKS"/>
          <bitfield name="SDCLKEN" caption="SD Clock Enable" mask="0x4" values="SDHC_CCR__SDCLKEN"/>
          <bitfield name="CLKGSEL" caption="Clock Generator Select" mask="0x20" values="SDHC_CCR__CLKGSEL"/>
          <bitfield name="USDCLKFSEL" caption="Upper Bits of SDCLK Frequency Select" mask="0xC0"/>
          <bitfield name="SDCLKFSEL" caption="SDCLK Frequency Select" mask="0xFF00"/>
        </register>
        <register name="TCR" offset="0x2E" rw="RW" size="1" initval="0x00" caption="Timeout Control">
          <bitfield name="DTCVAL" caption="Data Timeout Counter Value" mask="0xF"/>
        </register>
        <register name="SRR" offset="0x2F" rw="RW" size="1" initval="0x00" caption="Software Reset">
          <bitfield name="SWRSTALL" caption="Software Reset For All" mask="0x1" values="SDHC_SRR__SWRSTALL"/>
          <bitfield name="SWRSTCMD" caption="Software Reset For CMD Line" mask="0x2" values="SDHC_SRR__SWRSTCMD"/>
          <bitfield name="SWRSTDAT" caption="Software Reset For DAT Line" mask="0x4" values="SDHC_SRR__SWRSTDAT"/>
        </register>
        <register name="NISTR" offset="0x30" rw="RW" size="2" initval="0x0000" caption="Normal Interrupt Status">
          <mode name="DEFAULT_MODE">
            <bitfield name="CMDC" caption="Command Complete" mask="0x1" values="SDHC_NISTR__CMDC"/>
            <bitfield name="TRFC" caption="Transfer Complete" mask="0x2" values="SDHC_NISTR__TRFC"/>
            <bitfield name="BLKGE" caption="Block Gap Event" mask="0x4" values="SDHC_NISTR__BLKGE"/>
            <bitfield name="DMAINT" caption="DMA Interrupt" mask="0x8" values="SDHC_NISTR__DMAINT"/>
            <bitfield name="BWRRDY" caption="Buffer Write Ready" mask="0x10" values="SDHC_NISTR__BWRRDY"/>
            <bitfield name="BRDRDY" caption="Buffer Read Ready" mask="0x20" values="SDHC_NISTR__BRDRDY"/>
            <bitfield name="CINS" caption="Card Insertion" mask="0x40" values="SDHC_NISTR__CINS"/>
            <bitfield name="CREM" caption="Card Removal" mask="0x80" values="SDHC_NISTR__CREM"/>
            <bitfield name="CINT" caption="Card Interrupt" mask="0x100" values="SDHC_NISTR__CINT"/>
            <bitfield name="ERRINT" caption="Error Interrupt" mask="0x8000" values="SDHC_NISTR__ERRINT"/>
          </mode>
          <mode name="EMMC">
            <bitfield name="CMDC" caption="Command Complete" mask="0x1" values="SDHC_NISTR__CMDC"/>
            <bitfield name="TRFC" caption="Transfer Complete" mask="0x2" values="SDHC_NISTR__TRFC"/>
            <bitfield name="BLKGE" caption="Block Gap Event" mask="0x4" values="SDHC_NISTR__BLKGE"/>
            <bitfield name="DMAINT" caption="DMA Interrupt" mask="0x8" values="SDHC_NISTR__DMAINT"/>
            <bitfield name="BWRRDY" caption="Buffer Write Ready" mask="0x10" values="SDHC_NISTR__BWRRDY"/>
            <bitfield name="BRDRDY" caption="Buffer Read Ready" mask="0x20" values="SDHC_NISTR__BRDRDY"/>
            <bitfield name="BOOTAR" caption="Boot Acknowledge Received" mask="0x4000"/>
            <bitfield name="ERRINT" caption="Error Interrupt" mask="0x8000" values="SDHC_NISTR__ERRINT"/>
          </mode>
        </register>
        <register name="EISTR" offset="0x32" rw="RW" size="2" initval="0x0000" caption="Error Interrupt Status">
          <mode name="DEFAULT_MODE">
            <bitfield name="CMDTEO" caption="Command Timeout Error" mask="0x1" values="SDHC_EISTR__CMDTEO"/>
            <bitfield name="CMDCRC" caption="Command CRC Error" mask="0x2" values="SDHC_EISTR__CMDCRC"/>
            <bitfield name="CMDEND" caption="Command End Bit Error" mask="0x4" values="SDHC_EISTR__CMDEND"/>
            <bitfield name="CMDIDX" caption="Command Index Error" mask="0x8" values="SDHC_EISTR__CMDIDX"/>
            <bitfield name="DATTEO" caption="Data Timeout Error" mask="0x10" values="SDHC_EISTR__DATTEO"/>
            <bitfield name="DATCRC" caption="Data CRC Error" mask="0x20" values="SDHC_EISTR__DATCRC"/>
            <bitfield name="DATEND" caption="Data End Bit Error" mask="0x40" values="SDHC_EISTR__DATEND"/>
            <bitfield name="CURLIM" caption="Current Limit Error" mask="0x80" values="SDHC_EISTR__CURLIM"/>
            <bitfield name="ACMD" caption="Auto CMD Error" mask="0x100" values="SDHC_EISTR__ACMD"/>
            <bitfield name="ADMA" caption="ADMA Error" mask="0x200" values="SDHC_EISTR__ADMA"/>
          </mode>
          <mode name="EMMC">
            <bitfield name="CMDTEO" caption="Command Timeout Error" mask="0x1" values="SDHC_EISTR__CMDTEO"/>
            <bitfield name="CMDCRC" caption="Command CRC Error" mask="0x2" values="SDHC_EISTR__CMDCRC"/>
            <bitfield name="CMDEND" caption="Command End Bit Error" mask="0x4" values="SDHC_EISTR__CMDEND"/>
            <bitfield name="CMDIDX" caption="Command Index Error" mask="0x8" values="SDHC_EISTR__CMDIDX"/>
            <bitfield name="DATTEO" caption="Data Timeout Error" mask="0x10" values="SDHC_EISTR__DATTEO"/>
            <bitfield name="DATCRC" caption="Data CRC Error" mask="0x20" values="SDHC_EISTR__DATCRC"/>
            <bitfield name="DATEND" caption="Data End Bit Error" mask="0x40" values="SDHC_EISTR__DATEND"/>
            <bitfield name="CURLIM" caption="Current Limit Error" mask="0x80" values="SDHC_EISTR__CURLIM"/>
            <bitfield name="ACMD" caption="Auto CMD Error" mask="0x100" values="SDHC_EISTR__ACMD"/>
            <bitfield name="ADMA" caption="ADMA Error" mask="0x200" values="SDHC_EISTR__ADMA"/>
            <bitfield name="BOOTAE" caption="Boot Acknowledge Error" mask="0x1000" values="SDHC_EISTR__BOOTAE"/>
          </mode>
        </register>
        <register name="NISTER" offset="0x34" rw="RW" size="2" initval="0x0000" caption="Normal Interrupt Status Enable">
          <mode name="DEFAULT_MODE">
            <bitfield name="CMDC" caption="Command Complete Status Enable" mask="0x1" values="SDHC_NISTER__CMDC"/>
            <bitfield name="TRFC" caption="Transfer Complete Status Enable" mask="0x2" values="SDHC_NISTER__TRFC"/>
            <bitfield name="BLKGE" caption="Block Gap Event Status Enable" mask="0x4" values="SDHC_NISTER__BLKGE"/>
            <bitfield name="DMAINT" caption="DMA Interrupt Status Enable" mask="0x8" values="SDHC_NISTER__DMAINT"/>
            <bitfield name="BWRRDY" caption="Buffer Write Ready Status Enable" mask="0x10" values="SDHC_NISTER__BWRRDY"/>
            <bitfield name="BRDRDY" caption="Buffer Read Ready Status Enable" mask="0x20" values="SDHC_NISTER__BRDRDY"/>
            <bitfield name="CINS" caption="Card Insertion Status Enable" mask="0x40" values="SDHC_NISTER__CINS"/>
            <bitfield name="CREM" caption="Card Removal Status Enable" mask="0x80" values="SDHC_NISTER__CREM"/>
            <bitfield name="CINT" caption="Card Interrupt Status Enable" mask="0x100" values="SDHC_NISTER__CINT"/>
          </mode>
          <mode name="EMMC">
            <bitfield name="CMDC" caption="Command Complete Status Enable" mask="0x1" values="SDHC_NISTER__CMDC"/>
            <bitfield name="TRFC" caption="Transfer Complete Status Enable" mask="0x2" values="SDHC_NISTER__TRFC"/>
            <bitfield name="BLKGE" caption="Block Gap Event Status Enable" mask="0x4" values="SDHC_NISTER__BLKGE"/>
            <bitfield name="DMAINT" caption="DMA Interrupt Status Enable" mask="0x8" values="SDHC_NISTER__DMAINT"/>
            <bitfield name="BWRRDY" caption="Buffer Write Ready Status Enable" mask="0x10" values="SDHC_NISTER__BWRRDY"/>
            <bitfield name="BRDRDY" caption="Buffer Read Ready Status Enable" mask="0x20" values="SDHC_NISTER__BRDRDY"/>
            <bitfield name="BOOTAR" caption="Boot Acknowledge Received Status Enable" mask="0x4000"/>
          </mode>
        </register>
        <register name="EISTER" offset="0x36" rw="RW" size="2" initval="0x0000" caption="Error Interrupt Status Enable">
          <mode name="DEFAULT_MODE">
            <bitfield name="CMDTEO" caption="Command Timeout Error Status Enable" mask="0x1" values="SDHC_EISTER__CMDTEO"/>
            <bitfield name="CMDCRC" caption="Command CRC Error Status Enable" mask="0x2" values="SDHC_EISTER__CMDCRC"/>
            <bitfield name="CMDEND" caption="Command End Bit Error Status Enable" mask="0x4" values="SDHC_EISTER__CMDEND"/>
            <bitfield name="CMDIDX" caption="Command Index Error Status Enable" mask="0x8" values="SDHC_EISTER__CMDIDX"/>
            <bitfield name="DATTEO" caption="Data Timeout Error Status Enable" mask="0x10" values="SDHC_EISTER__DATTEO"/>
            <bitfield name="DATCRC" caption="Data CRC Error Status Enable" mask="0x20" values="SDHC_EISTER__DATCRC"/>
            <bitfield name="DATEND" caption="Data End Bit Error Status Enable" mask="0x40" values="SDHC_EISTER__DATEND"/>
            <bitfield name="CURLIM" caption="Current Limit Error Status Enable" mask="0x80" values="SDHC_EISTER__CURLIM"/>
            <bitfield name="ACMD" caption="Auto CMD Error Status Enable" mask="0x100" values="SDHC_EISTER__ACMD"/>
            <bitfield name="ADMA" caption="ADMA Error Status Enable" mask="0x200" values="SDHC_EISTER__ADMA"/>
          </mode>
          <mode name="EMMC">
            <bitfield name="CMDTEO" caption="Command Timeout Error Status Enable" mask="0x1" values="SDHC_EISTER__CMDTEO"/>
            <bitfield name="CMDCRC" caption="Command CRC Error Status Enable" mask="0x2" values="SDHC_EISTER__CMDCRC"/>
            <bitfield name="CMDEND" caption="Command End Bit Error Status Enable" mask="0x4" values="SDHC_EISTER__CMDEND"/>
            <bitfield name="CMDIDX" caption="Command Index Error Status Enable" mask="0x8" values="SDHC_EISTER__CMDIDX"/>
            <bitfield name="DATTEO" caption="Data Timeout Error Status Enable" mask="0x10" values="SDHC_EISTER__DATTEO"/>
            <bitfield name="DATCRC" caption="Data CRC Error Status Enable" mask="0x20" values="SDHC_EISTER__DATCRC"/>
            <bitfield name="DATEND" caption="Data End Bit Error Status Enable" mask="0x40" values="SDHC_EISTER__DATEND"/>
            <bitfield name="CURLIM" caption="Current Limit Error Status Enable" mask="0x80" values="SDHC_EISTER__CURLIM"/>
            <bitfield name="ACMD" caption="Auto CMD Error Status Enable" mask="0x100" values="SDHC_EISTER__ACMD"/>
            <bitfield name="ADMA" caption="ADMA Error Status Enable" mask="0x200" values="SDHC_EISTER__ADMA"/>
            <bitfield name="BOOTAE" caption="Boot Acknowledge Error Status Enable" mask="0x1000"/>
          </mode>
        </register>
        <register name="NISIER" offset="0x38" rw="RW" size="2" initval="0x0000" caption="Normal Interrupt Signal Enable">
          <mode name="DEFAULT_MODE">
            <bitfield name="CMDC" caption="Command Complete Signal Enable" mask="0x1" values="SDHC_NISIER__CMDC"/>
            <bitfield name="TRFC" caption="Transfer Complete Signal Enable" mask="0x2" values="SDHC_NISIER__TRFC"/>
            <bitfield name="BLKGE" caption="Block Gap Event Signal Enable" mask="0x4" values="SDHC_NISIER__BLKGE"/>
            <bitfield name="DMAINT" caption="DMA Interrupt Signal Enable" mask="0x8" values="SDHC_NISIER__DMAINT"/>
            <bitfield name="BWRRDY" caption="Buffer Write Ready Signal Enable" mask="0x10" values="SDHC_NISIER__BWRRDY"/>
            <bitfield name="BRDRDY" caption="Buffer Read Ready Signal Enable" mask="0x20" values="SDHC_NISIER__BRDRDY"/>
            <bitfield name="CINS" caption="Card Insertion Signal Enable" mask="0x40" values="SDHC_NISIER__CINS"/>
            <bitfield name="CREM" caption="Card Removal Signal Enable" mask="0x80" values="SDHC_NISIER__CREM"/>
            <bitfield name="CINT" caption="Card Interrupt Signal Enable" mask="0x100" values="SDHC_NISIER__CINT"/>
          </mode>
          <mode name="EMMC">
            <bitfield name="CMDC" caption="Command Complete Signal Enable" mask="0x1" values="SDHC_NISIER__CMDC"/>
            <bitfield name="TRFC" caption="Transfer Complete Signal Enable" mask="0x2" values="SDHC_NISIER__TRFC"/>
            <bitfield name="BLKGE" caption="Block Gap Event Signal Enable" mask="0x4" values="SDHC_NISIER__BLKGE"/>
            <bitfield name="DMAINT" caption="DMA Interrupt Signal Enable" mask="0x8" values="SDHC_NISIER__DMAINT"/>
            <bitfield name="BWRRDY" caption="Buffer Write Ready Signal Enable" mask="0x10" values="SDHC_NISIER__BWRRDY"/>
            <bitfield name="BRDRDY" caption="Buffer Read Ready Signal Enable" mask="0x20" values="SDHC_NISIER__BRDRDY"/>
            <bitfield name="BOOTAR" caption="Boot Acknowledge Received Signal Enable" mask="0x4000"/>
          </mode>
        </register>
        <register name="EISIER" offset="0x3A" rw="RW" size="2" initval="0x0000" caption="Error Interrupt Signal Enable">
          <mode name="DEFAULT_MODE">
            <bitfield name="CMDTEO" caption="Command Timeout Error Signal Enable" mask="0x1" values="SDHC_EISIER__CMDTEO"/>
            <bitfield name="CMDCRC" caption="Command CRC Error Signal Enable" mask="0x2" values="SDHC_EISIER__CMDCRC"/>
            <bitfield name="CMDEND" caption="Command End Bit Error Signal Enable" mask="0x4" values="SDHC_EISIER__CMDEND"/>
            <bitfield name="CMDIDX" caption="Command Index Error Signal Enable" mask="0x8" values="SDHC_EISIER__CMDIDX"/>
            <bitfield name="DATTEO" caption="Data Timeout Error Signal Enable" mask="0x10" values="SDHC_EISIER__DATTEO"/>
            <bitfield name="DATCRC" caption="Data CRC Error Signal Enable" mask="0x20" values="SDHC_EISIER__DATCRC"/>
            <bitfield name="DATEND" caption="Data End Bit Error Signal Enable" mask="0x40" values="SDHC_EISIER__DATEND"/>
            <bitfield name="CURLIM" caption="Current Limit Error Signal Enable" mask="0x80" values="SDHC_EISIER__CURLIM"/>
            <bitfield name="ACMD" caption="Auto CMD Error Signal Enable" mask="0x100" values="SDHC_EISIER__ACMD"/>
            <bitfield name="ADMA" caption="ADMA Error Signal Enable" mask="0x200" values="SDHC_EISIER__ADMA"/>
          </mode>
          <mode name="EMMC">
            <bitfield name="CMDTEO" caption="Command Timeout Error Signal Enable" mask="0x1" values="SDHC_EISIER__CMDTEO"/>
            <bitfield name="CMDCRC" caption="Command CRC Error Signal Enable" mask="0x2" values="SDHC_EISIER__CMDCRC"/>
            <bitfield name="CMDEND" caption="Command End Bit Error Signal Enable" mask="0x4" values="SDHC_EISIER__CMDEND"/>
            <bitfield name="CMDIDX" caption="Command Index Error Signal Enable" mask="0x8" values="SDHC_EISIER__CMDIDX"/>
            <bitfield name="DATTEO" caption="Data Timeout Error Signal Enable" mask="0x10" values="SDHC_EISIER__DATTEO"/>
            <bitfield name="DATCRC" caption="Data CRC Error Signal Enable" mask="0x20" values="SDHC_EISIER__DATCRC"/>
            <bitfield name="DATEND" caption="Data End Bit Error Signal Enable" mask="0x40" values="SDHC_EISIER__DATEND"/>
            <bitfield name="CURLIM" caption="Current Limit Error Signal Enable" mask="0x80" values="SDHC_EISIER__CURLIM"/>
            <bitfield name="ACMD" caption="Auto CMD Error Signal Enable" mask="0x100" values="SDHC_EISIER__ACMD"/>
            <bitfield name="ADMA" caption="ADMA Error Signal Enable" mask="0x200" values="SDHC_EISIER__ADMA"/>
            <bitfield name="BOOTAE" caption="Boot Acknowledge Error Signal Enable" mask="0x1000"/>
          </mode>
        </register>
        <register name="ACESR" offset="0x3C" rw="R" size="2" initval="0x0000" caption="Auto CMD Error Status">
          <bitfield name="ACMD12NE" caption="Auto CMD12 Not Executed" mask="0x1" values="SDHC_ACESR__ACMD12NE"/>
          <bitfield name="ACMDTEO" caption="Auto CMD Timeout Error" mask="0x2" values="SDHC_ACESR__ACMDTEO"/>
          <bitfield name="ACMDCRC" caption="Auto CMD CRC Error" mask="0x4" values="SDHC_ACESR__ACMDCRC"/>
          <bitfield name="ACMDEND" caption="Auto CMD End Bit Error" mask="0x8" values="SDHC_ACESR__ACMDEND"/>
          <bitfield name="ACMDIDX" caption="Auto CMD Index Error" mask="0x10" values="SDHC_ACESR__ACMDIDX"/>
          <bitfield name="CMDNI" caption="Command not Issued By Auto CMD12 Error" mask="0x80" values="SDHC_ACESR__CMDNI"/>
        </register>
        <register name="HC2R" offset="0x3E" rw="RW" size="2" initval="0x0000" caption="Host Control 2">
          <mode name="DEFAULT_MODE">
            <bitfield name="UHSMS" caption="UHS Mode Select" mask="0x7" values="SDHC_HC2R__UHSMS"/>
            <bitfield name="VS18EN" caption="1.8V Signaling Enable" mask="0x8" values="SDHC_HC2R__VS18EN"/>
            <bitfield name="DRVSEL" caption="Driver Strength Select" mask="0x30" values="SDHC_HC2R__DRVSEL"/>
            <bitfield name="EXTUN" caption="Execute Tuning" mask="0x40" values="SDHC_HC2R__EXTUN"/>
            <bitfield name="SLCKSEL" caption="Sampling Clock Select" mask="0x80" values="SDHC_HC2R__SLCKSEL"/>
            <bitfield name="ASINTEN" caption="Asynchronous Interrupt Enable" mask="0x4000" values="SDHC_HC2R__ASINTEN"/>
            <bitfield name="PVALEN" caption="Preset Value Enable" mask="0x8000" values="SDHC_HC2R__PVALEN"/>
          </mode>
          <mode name="EMMC">
            <bitfield name="HS200EN" caption="HS200 Mode Enable" mask="0xF" values="SDHC_HC2R__HS200EN"/>
            <bitfield name="DRVSEL" caption="Driver Strength Select" mask="0x30" values="SDHC_HC2R__DRVSEL"/>
            <bitfield name="EXTUN" caption="Execute Tuning" mask="0x40" values="SDHC_HC2R__EXTUN"/>
            <bitfield name="SLCKSEL" caption="Sampling Clock Select" mask="0x80" values="SDHC_HC2R__SLCKSEL"/>
            <bitfield name="PVALEN" caption="Preset Value Enable" mask="0x8000" values="SDHC_HC2R__PVALEN"/>
          </mode>
        </register>
        <register name="CA0R" offset="0x40" rw="R" size="4" initval="0x27E80080" caption="Capabilities 0">
          <bitfield name="TEOCLKF" caption="Timeout Clock Frequency" mask="0x3F" values="SDHC_CA0R__TEOCLKF"/>
          <bitfield name="TEOCLKU" caption="Timeout Clock Unit" mask="0x80" values="SDHC_CA0R__TEOCLKU"/>
          <bitfield name="BASECLKF" caption="Base Clock Frequency" mask="0xFF00" values="SDHC_CA0R__BASECLKF"/>
          <bitfield name="MAXBLKL" caption="Max Block Length" mask="0x30000" values="SDHC_CA0R__MAXBLKL"/>
          <bitfield name="ED8SUP" caption="8-bit Support for Embedded Device" mask="0x40000" values="SDHC_CA0R__ED8SUP"/>
          <bitfield name="ADMA2SUP" caption="ADMA2 Support" mask="0x80000" values="SDHC_CA0R__ADMA2SUP"/>
          <bitfield name="HSSUP" caption="High Speed Support" mask="0x200000" values="SDHC_CA0R__HSSUP"/>
          <bitfield name="SDMASUP" caption="SDMA Support" mask="0x400000" values="SDHC_CA0R__SDMASUP"/>
          <bitfield name="SRSUP" caption="Suspend/Resume Support" mask="0x800000" values="SDHC_CA0R__SRSUP"/>
          <bitfield name="V33VSUP" caption="Voltage Support 3.3V" mask="0x1000000" values="SDHC_CA0R__V33VSUP"/>
          <bitfield name="V30VSUP" caption="Voltage Support 3.0V" mask="0x2000000" values="SDHC_CA0R__V30VSUP"/>
          <bitfield name="V18VSUP" caption="Voltage Support 1.8V" mask="0x4000000" values="SDHC_CA0R__V18VSUP"/>
          <bitfield name="SB64SUP" caption="64-Bit System Bus Support" mask="0x10000000" values="SDHC_CA0R__SB64SUP"/>
          <bitfield name="ASINTSUP" caption="Asynchronous Interrupt Support" mask="0x20000000" values="SDHC_CA0R__ASINTSUP"/>
          <bitfield name="SLTYPE" caption="Slot Type" mask="0xC0000000" values="SDHC_CA0R__SLTYPE"/>
        </register>
        <register name="CA1R" offset="0x44" rw="R" size="4" initval="0x00000070" caption="Capabilities 1">
          <bitfield name="SDR50SUP" caption="SDR50 Support" mask="0x1" values="SDHC_CA1R__SDR50SUP"/>
          <bitfield name="SDR104SUP" caption="SDR104 Support" mask="0x2" values="SDHC_CA1R__SDR104SUP"/>
          <bitfield name="DDR50SUP" caption="DDR50 Support" mask="0x4" values="SDHC_CA1R__DDR50SUP"/>
          <bitfield name="DRVASUP" caption="Driver Type A Support" mask="0x10" values="SDHC_CA1R__DRVASUP"/>
          <bitfield name="DRVCSUP" caption="Driver Type C Support" mask="0x20" values="SDHC_CA1R__DRVCSUP"/>
          <bitfield name="DRVDSUP" caption="Driver Type D Support" mask="0x40" values="SDHC_CA1R__DRVDSUP"/>
          <bitfield name="TCNTRT" caption="Timer Count for Re-Tuning" mask="0xF00" values="SDHC_CA1R__TCNTRT"/>
          <bitfield name="TSDR50" caption="Use Tuning for SDR50" mask="0x2000" values="SDHC_CA1R__TSDR50"/>
          <bitfield name="CLKMULT" caption="Clock Multiplier" mask="0xFF0000" values="SDHC_CA1R__CLKMULT"/>
        </register>
        <register name="MCCAR" offset="0x48" rw="R" size="4" initval="0x00000000" caption="Maximum Current Capabilities">
          <bitfield name="MAXCUR33V" caption="Maximum Current for 3.3V" mask="0xFF" values="SDHC_MCCAR__MAXCUR33V"/>
          <bitfield name="MAXCUR30V" caption="Maximum Current for 3.0V" mask="0xFF00" values="SDHC_MCCAR__MAXCUR30V"/>
          <bitfield name="MAXCUR18V" caption="Maximum Current for 1.8V" mask="0xFF0000" values="SDHC_MCCAR__MAXCUR18V"/>
        </register>
        <register name="FERACES" offset="0x50" rw="W" size="2" initval="0x0000" caption="Force Event for Auto CMD Error Status">
          <bitfield name="ACMD12NE" caption="Force Event for Auto CMD12 Not Executed" mask="0x1" values="SDHC_FERACES__ACMD12NE"/>
          <bitfield name="ACMDTEO" caption="Force Event for Auto CMD Timeout Error" mask="0x2" values="SDHC_FERACES__ACMDTEO"/>
          <bitfield name="ACMDCRC" caption="Force Event for Auto CMD CRC Error" mask="0x4" values="SDHC_FERACES__ACMDCRC"/>
          <bitfield name="ACMDEND" caption="Force Event for Auto CMD End Bit Error" mask="0x8" values="SDHC_FERACES__ACMDEND"/>
          <bitfield name="ACMDIDX" caption="Force Event for Auto CMD Index Error" mask="0x10" values="SDHC_FERACES__ACMDIDX"/>
          <bitfield name="CMDNI" caption="Force Event for Command Not Issued By Auto CMD12 Error" mask="0x80" values="SDHC_FERACES__CMDNI"/>
        </register>
        <register name="FEREIS" offset="0x52" rw="W" size="2" initval="0x0000" caption="Force Event for Error Interrupt Status">
          <bitfield name="CMDTEO" caption="Force Event for Command Timeout Error" mask="0x1" values="SDHC_FEREIS__CMDTEO"/>
          <bitfield name="CMDCRC" caption="Force Event for Command CRC Error" mask="0x2" values="SDHC_FEREIS__CMDCRC"/>
          <bitfield name="CMDEND" caption="Force Event for Command End Bit Error" mask="0x4" values="SDHC_FEREIS__CMDEND"/>
          <bitfield name="CMDIDX" caption="Force Event for Command Index Error" mask="0x8" values="SDHC_FEREIS__CMDIDX"/>
          <bitfield name="DATTEO" caption="Force Event for Data Timeout Error" mask="0x10" values="SDHC_FEREIS__DATTEO"/>
          <bitfield name="DATCRC" caption="Force Event for Data CRC Error" mask="0x20" values="SDHC_FEREIS__DATCRC"/>
          <bitfield name="DATEND" caption="Force Event for Data End Bit Error" mask="0x40" values="SDHC_FEREIS__DATEND"/>
          <bitfield name="CURLIM" caption="Force Event for Current Limit Error" mask="0x80" values="SDHC_FEREIS__CURLIM"/>
          <bitfield name="ACMD" caption="Force Event for Auto CMD Error" mask="0x100" values="SDHC_FEREIS__ACMD"/>
          <bitfield name="ADMA" caption="Force Event for ADMA Error" mask="0x200" values="SDHC_FEREIS__ADMA"/>
          <bitfield name="BOOTAE" caption="Force Event for Boot Acknowledge Error" mask="0x1000" values="SDHC_FEREIS__BOOTAE"/>
        </register>
        <register name="AESR" offset="0x54" rw="R" size="1" initval="0x00" caption="ADMA Error Status">
          <bitfield name="ERRST" caption="ADMA Error State" mask="0x3" values="SDHC_AESR__ERRST"/>
          <bitfield name="LMIS" caption="ADMA Length Mismatch Error" mask="0x4" values="SDHC_AESR__LMIS"/>
        </register>
        <register name="ASAR" offset="0x58" rw="RW" size="4" count="1" initval="0x00000000" caption="ADMA System Address n">
          <bitfield name="ADMASA" caption="ADMA System Address" mask="0xFFFFFFFF"/>
        </register>
        <register name="PVR" offset="0x60" rw="RW" size="2" count="8" initval="0x0000" caption="Preset Value n">
          <bitfield name="SDCLKFSEL" caption="SDCLK Frequency Select Value for Initialization" mask="0x3FF"/>
          <bitfield name="CLKGSEL" caption="Clock Generator Select Value for Initialization" mask="0x400" values="SDHC_PVR__CLKGSEL"/>
          <bitfield name="DRVSEL" caption="Driver Strength Select Value for Initialization" mask="0xC000" values="SDHC_PVR__DRVSEL"/>
        </register>
        <register name="SISR" offset="0xFC" rw="R" size="2" initval="0x20000" caption="Slot Interrupt Status">
          <bitfield name="INTSSL" caption="Interrupt Signal for Each Slot" mask="0x1"/>
        </register>
        <register name="HCVR" offset="0xFE" rw="R" size="2" initval="0x1802" caption="Host Controller Version">
          <bitfield name="SVER" caption="Spec Version" mask="0xFF"/>
          <bitfield name="VVER" caption="Vendor Version" mask="0xFF00"/>
        </register>
        <register name="MC1R" offset="0x204" rw="RW" size="1" initval="0x00" caption="MMC Control 1">
          <bitfield name="CMDTYP" caption="e.MMC Command Type" mask="0x3" values="SDHC_MC1R__CMDTYP"/>
          <bitfield name="DDR" caption="e.MMC HSDDR Mode" mask="0x8"/>
          <bitfield name="OPD" caption="e.MMC Open Drain Mode" mask="0x10"/>
          <bitfield name="BOOTA" caption="e.MMC Boot Acknowledge Enable" mask="0x20"/>
          <bitfield name="RSTN" caption="e.MMC Reset Signal" mask="0x40"/>
          <bitfield name="FCD" caption="e.MMC Force Card Detect" mask="0x80"/>
        </register>
        <register name="MC2R" offset="0x205" rw="W" size="1" initval="0x00" caption="MMC Control 2">
          <bitfield name="SRESP" caption="e.MMC Abort Wait IRQ" mask="0x1"/>
          <bitfield name="ABOOT" caption="e.MMC Abort Boot" mask="0x2"/>
        </register>
        <register name="ACR" offset="0x208" rw="RW" size="4" initval="0x00000000" caption="AHB Control">
          <bitfield name="BMAX" caption="AHB Maximum Burst" mask="0x3" values="SDHC_ACR__BMAX"/>
        </register>
        <register name="CC2R" offset="0x20C" rw="RW" size="4" initval="0x00000000" caption="Clock Control 2">
          <bitfield name="FSDCLKD" caption="Force SDCK Disabled" mask="0x1" values="SDHC_CC2R__FSDCLKD"/>
        </register>
        <register name="CACR" offset="0x230" rw="RW" size="4" initval="0x00000000" caption="Capabilities Control">
          <bitfield name="CAPWREN" caption="Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers)" mask="0x1"/>
          <bitfield name="KEY" caption="Key (0x46)" mask="0xFF00"/>
        </register>
        <register name="DBGR" offset="0x234" rw="RW" size="1" initval="0x00" caption="Debug">
          <bitfield name="NIDBG" caption="Non-intrusive debug enable" mask="0x1" values="SDHC_DBGR__NIDBG"/>
        </register>
      </register-group>
      <value-group name="SDHC_BSR__BOUNDARY">
        <value name="4K" caption="4k bytes" value="0"/>
        <value name="8K" caption="8k bytes" value="1"/>
        <value name="16K" caption="16k bytes" value="2"/>
        <value name="32K" caption="32k bytes" value="3"/>
        <value name="64K" caption="64k bytes" value="4"/>
        <value name="128K" caption="128k bytes" value="5"/>
        <value name="256K" caption="256k bytes" value="6"/>
        <value name="512K" caption="512k bytes" value="7"/>
      </value-group>
      <value-group name="SDHC_TMR__ACMDEN">
        <value name="DISABLED" caption="Auto Command Disabled" value="0"/>
        <value name="CMD12" caption="Auto CMD12 Enable" value="1"/>
        <value name="CMD23" caption="Auto CMD23 Enable" value="2"/>
      </value-group>
      <value-group name="SDHC_TMR__BCEN">
        <value name="DISABLE" caption="Disable" value="0"/>
        <value name="ENABLE" caption="Enable" value="1"/>
      </value-group>
      <value-group name="SDHC_TMR__DMAEN">
        <value name="DISABLE" caption="No data transfer or Non DMA data transfer" value="0"/>
        <value name="ENABLE" caption="DMA data transfer" value="1"/>
      </value-group>
      <value-group name="SDHC_TMR__DTDSEL">
        <value name="WRITE" caption="Write (Host to Card)" value="0"/>
        <value name="READ" caption="Read (Card to Host)" value="1"/>
      </value-group>
      <value-group name="SDHC_TMR__MSBSEL">
        <value name="SINGLE" caption="Single Block" value="0"/>
        <value name="MULTIPLE" caption="Multiple Block" value="1"/>
      </value-group>
      <value-group name="SDHC_CR__CMDCCEN">
        <value name="DISABLE" caption="Disable" value="0"/>
        <value name="ENABLE" caption="Enable" value="1"/>
      </value-group>
      <value-group name="SDHC_CR__CMDICEN">
        <value name="DISABLE" caption="Disable" value="0"/>
        <value name="ENABLE" caption="Enable" value="1"/>
      </value-group>
      <value-group name="SDHC_CR__CMDTYP">
        <value name="NORMAL" caption="Other commands" value="0"/>
        <value name="SUSPEND" caption="CMD52 for writing Bus Suspend in CCCR" value="1"/>
        <value name="RESUME" caption="CMD52 for writing Function Select in CCCR" value="2"/>
        <value name="ABORT" caption="CMD12, CMD52 for writing I/O Abort in CCCR" value="3"/>
      </value-group>
      <value-group name="SDHC_CR__DPSEL">
        <value name="NO_DATA" caption="No Data Present" value="0"/>
        <value name="DATA" caption="Data Present" value="1"/>
      </value-group>
      <value-group name="SDHC_CR__RESPTYP">
        <value name="NONE" caption="No response" value="0"/>
        <value name="136_BIT" caption="136-bit response" value="1"/>
        <value name="48_BIT" caption="48-bit response" value="2"/>
        <value name="48_BIT_BUSY" caption="48-bit response check busy after response" value="3"/>
      </value-group>
      <value-group name="SDHC_PSR__BUFRDEN">
        <value name="DISABLE" caption="Read disable" value="0"/>
        <value name="ENABLE" caption="Read enable" value="1"/>
      </value-group>
      <value-group name="SDHC_PSR__BUFWREN">
        <value name="DISABLE" caption="Write disable" value="0"/>
        <value name="ENABLE" caption="Write enable" value="1"/>
      </value-group>
      <value-group name="SDHC_PSR__CARDDPL">
        <value name="NO" caption="No card present (SDCD#=1)" value="0"/>
        <value name="YES" caption="Card present (SDCD#=0)" value="1"/>
      </value-group>
      <value-group name="SDHC_PSR__CARDINS">
        <value name="NO" caption="Reset or Debouncing or No Card" value="0"/>
        <value name="YES" caption="Card inserted" value="1"/>
      </value-group>
      <value-group name="SDHC_PSR__CARDSS">
        <value name="NO" caption="Reset or Debouncing" value="0"/>
        <value name="YES" caption="No Card or Insered" value="1"/>
      </value-group>
      <value-group name="SDHC_PSR__CMDINHC">
        <value name="CAN" caption="Can issue command using only CMD line" value="0"/>
        <value name="CANNOT" caption="Cannot issue command" value="1"/>
      </value-group>
      <value-group name="SDHC_PSR__CMDINHD">
        <value name="CAN" caption="Can issue command which uses the DAT line" value="0"/>
        <value name="CANNOT" caption="Cannot issue command which uses the DAT line" value="1"/>
      </value-group>
      <value-group name="SDHC_PSR__DLACT">
        <value name="INACTIVE" caption="DAT Line Inactive" value="0"/>
        <value name="ACTIVE" caption="DAT Line Active" value="1"/>
      </value-group>
      <value-group name="SDHC_PSR__RTACT">
        <value name="NO" caption="No valid data" value="0"/>
        <value name="YES" caption="Transferring data" value="1"/>
      </value-group>
      <value-group name="SDHC_PSR__RTREQ">
        <value name="OK" caption="Fixed or well-tuned sampling clock" value="0"/>
        <value name="REQUIRED" caption="Sampling clock needs re-tuning" value="1"/>
      </value-group>
      <value-group name="SDHC_PSR__WRPPL">
        <value name="PROTECTED" caption="Write protected (SDWP#=0)" value="0"/>
        <value name="ENABLED" caption="Write enabled (SDWP#=1)" value="1"/>
      </value-group>
      <value-group name="SDHC_PSR__WTACT">
        <value name="NO" caption="No valid data" value="0"/>
        <value name="YES" caption="Transferring data" value="1"/>
      </value-group>
      <value-group name="SDHC_HC1R__CARDDSEL">
        <value name="NORMAL" caption="SDCD# is selected (for normal use)" value="0"/>
        <value name="TEST" caption="The Card Select Test Level is selected (for test purpose)" value="1"/>
      </value-group>
      <value-group name="SDHC_HC1R__CARDDTL">
        <value name="NO" caption="No Card" value="0"/>
        <value name="YES" caption="Card Inserted" value="1"/>
      </value-group>
      <value-group name="SDHC_HC1R__DMASEL">
        <value name="SDMA" caption="SDMA is selected" value="0"/>
        <value name="32BIT" caption="32-bit Address ADMA2 is selected" value="2"/>
      </value-group>
      <value-group name="SDHC_HC1R__DW">
        <value name="1BIT" caption="1-bit mode" value="0"/>
        <value name="4BIT" caption="4-bit mode" value="1"/>
      </value-group>
      <value-group name="SDHC_HC1R__HSEN">
        <value name="NORMAL" caption="Normal Speed mode" value="0"/>
        <value name="HIGH" caption="High Speed mode" value="1"/>
      </value-group>
      <value-group name="SDHC_HC1R__LEDCTRL">
        <value name="OFF" caption="LED off" value="0"/>
        <value name="ON" caption="LED on" value="1"/>
      </value-group>
      <value-group name="SDHC_HC1R__EXTDW">
        <value name="NO" caption="No Card" value="0"/>
        <value name="YES" caption="Card Inserted" value="1"/>
      </value-group>
      <value-group name="SDHC_PCR__SDBPWR">
        <value name="OFF" caption="Power off" value="0"/>
        <value name="ON" caption="Power on" value="1"/>
      </value-group>
      <value-group name="SDHC_PCR__SDBVSEL">
        <value name="1V8" caption="1.8V (Typ.)" value="5"/>
        <value name="3V0" caption="3.0V (Typ.)" value="6"/>
        <value name="3V3" caption="3.3V (Typ.)" value="7"/>
      </value-group>
      <value-group name="SDHC_BGCR__CONTR">
        <value name="GO_ON" caption="Not affected" value="0"/>
        <value name="RESTART" caption="Restart" value="1"/>
      </value-group>
      <value-group name="SDHC_BGCR__INTBG">
        <value name="DISABLED" caption="Disabled" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_BGCR__RWCTRL">
        <value name="DISABLE" caption="Disable Read Wait Control" value="0"/>
        <value name="ENABLE" caption="Enable Read Wait Control" value="1"/>
      </value-group>
      <value-group name="SDHC_BGCR__STPBGR">
        <value name="TRANSFER" caption="Transfer" value="0"/>
        <value name="STOP" caption="Stop" value="1"/>
      </value-group>
      <value-group name="SDHC_WCR__WKENCINS">
        <value name="DISABLE" caption="Disable" value="0"/>
        <value name="ENABLE" caption="Enable" value="1"/>
      </value-group>
      <value-group name="SDHC_WCR__WKENCINT">
        <value name="DISABLE" caption="Disable" value="0"/>
        <value name="ENABLE" caption="Enable" value="1"/>
      </value-group>
      <value-group name="SDHC_WCR__WKENCREM">
        <value name="DISABLE" caption="Disable" value="0"/>
        <value name="ENABLE" caption="Enable" value="1"/>
      </value-group>
      <value-group name="SDHC_CCR__CLKGSEL">
        <value name="DIV" caption="Divided Clock Mode" value="0"/>
        <value name="PROG" caption="Programmable Clock Mode" value="1"/>
      </value-group>
      <value-group name="SDHC_CCR__INTCLKEN">
        <value name="OFF" caption="Stop" value="0"/>
        <value name="ON" caption="Oscillate" value="1"/>
      </value-group>
      <value-group name="SDHC_CCR__INTCLKS">
        <value name="NOT_READY" caption="Not Ready" value="0"/>
        <value name="READY" caption="Ready" value="1"/>
      </value-group>
      <value-group name="SDHC_CCR__SDCLKEN">
        <value name="DISABLE" caption="Disable" value="0"/>
        <value name="ENABLE" caption="Enable" value="1"/>
      </value-group>
      <value-group name="SDHC_SRR__SWRSTALL">
        <value name="WORK" caption="Work" value="0"/>
        <value name="RESET" caption="Reset" value="1"/>
      </value-group>
      <value-group name="SDHC_SRR__SWRSTCMD">
        <value name="WORK" caption="Work" value="0"/>
        <value name="RESET" caption="Reset" value="1"/>
      </value-group>
      <value-group name="SDHC_SRR__SWRSTDAT">
        <value name="WORK" caption="Work" value="0"/>
        <value name="RESET" caption="Reset" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTR__BLKGE">
        <value name="NO" caption="No Block Gap Event" value="0"/>
        <value name="STOP" caption="Transaction stopped at block gap" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTR__BRDRDY">
        <value name="NO" caption="Not ready to read buffer" value="0"/>
        <value name="YES" caption="Ready to read buffer" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTR__BWRRDY">
        <value name="NO" caption="Not ready to write buffer" value="0"/>
        <value name="YES" caption="Ready to write buffer" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTR__CINS">
        <value name="NO" caption="Card state stable or Debouncing" value="0"/>
        <value name="YES" caption="Card inserted" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTR__CINT">
        <value name="NO" caption="No Card Interrupt" value="0"/>
        <value name="YES" caption="Generate Card Interrupt" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTR__CMDC">
        <value name="NO" caption="No command complete" value="0"/>
        <value name="YES" caption="Command complete" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTR__CREM">
        <value name="NO" caption="Card state stable or Debouncing" value="0"/>
        <value name="YES" caption="Card Removed" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTR__DMAINT">
        <value name="NO" caption="No DMA Interrupt" value="0"/>
        <value name="YES" caption="DMA Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTR__ERRINT">
        <value name="NO" caption="No Error" value="0"/>
        <value name="YES" caption="Error" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTR__INTA">
        <value name="NO" caption="No interrupt is detected" value="0"/>
        <value name="YES" caption="INT_A is detected" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTR__INTB">
        <value name="NO" caption="No interrupt is detected" value="0"/>
        <value name="YES" caption="INT_B is detected" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTR__INTC">
        <value name="NO" caption="No interrupt is detected" value="0"/>
        <value name="YES" caption="INT_C is detected" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTR__RTEVT">
        <value name="OK" caption="Re-Tuning is not required" value="0"/>
        <value name="REQUIRED" caption="Re-Tuning should be performed" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTR__TRFC">
        <value name="NO" caption="Not complete" value="0"/>
        <value name="YES" caption="Command execution is completed" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTR__ACMD">
        <value name="NO" caption="No Error" value="0"/>
        <value name="YES" caption="Error" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTR__ADMA">
        <value name="NO" caption="No Error" value="0"/>
        <value name="YES" caption="Error" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTR__CMDCRC">
        <value name="NO" caption="No Error" value="0"/>
        <value name="YES" caption="CRC Error Generated" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTR__CMDEND">
        <value name="NO" caption="No error" value="0"/>
        <value name="YES" caption="End Bit Error Generated" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTR__CMDIDX">
        <value name="NO" caption="No Error" value="0"/>
        <value name="YES" caption="Error" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTR__CMDTEO">
        <value name="NO" caption="No Error" value="0"/>
        <value name="YES" caption="Timeout" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTR__CURLIM">
        <value name="NO" caption="No Error" value="0"/>
        <value name="YES" caption="Power Fail" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTR__DATCRC">
        <value name="NO" caption="No Error" value="0"/>
        <value name="YES" caption="Error" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTR__DATEND">
        <value name="NO" caption="No Error" value="0"/>
        <value name="YES" caption="Error" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTR__DATTEO">
        <value name="NO" caption="No Error" value="0"/>
        <value name="YES" caption="Timeout" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTR__TUNING">
        <value name="NO" caption="No Error" value="0"/>
        <value name="YES" caption="Error" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTR__BOOTAE">
        <value name="0" caption="FIFO contains at least one byte" value="0"/>
        <value name="1" caption="FIFO is empty" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTER__BLKGE">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTER__BRDRDY">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTER__BWRRDY">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTER__CINS">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTER__CINT">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTER__CMDC">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTER__CREM">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTER__DMAINT">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTER__INTA">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTER__INTB">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTER__INTC">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTER__RTEVT">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISTER__TRFC">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTER__ACMD">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTER__ADMA">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTER__CMDCRC">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTER__CMDEND">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTER__CMDIDX">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTER__CMDTEO">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTER__CURLIM">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTER__DATCRC">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTER__DATEND">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTER__DATTEO">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISTER__TUNING">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISIER__BLKGE">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISIER__BRDRDY">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISIER__BWRRDY">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISIER__CINS">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISIER__CINT">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISIER__CMDC">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISIER__CREM">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISIER__DMAINT">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISIER__INTA">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISIER__INTB">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISIER__INTC">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISIER__RTEVT">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_NISIER__TRFC">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISIER__ACMD">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISIER__ADMA">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISIER__CMDCRC">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISIER__CMDEND">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISIER__CMDIDX">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISIER__CMDTEO">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISIER__CURLIM">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISIER__DATCRC">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISIER__DATEND">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISIER__DATTEO">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_EISIER__TUNING">
        <value name="MASKED" caption="Masked" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_ACESR__ACMDCRC">
        <value name="NO" caption="No error" value="0"/>
        <value name="YES" caption="CRC Error Generated" value="1"/>
      </value-group>
      <value-group name="SDHC_ACESR__ACMDEND">
        <value name="NO" caption="No error" value="0"/>
        <value name="YES" caption="End Bit Error Generated" value="1"/>
      </value-group>
      <value-group name="SDHC_ACESR__ACMDIDX">
        <value name="NO" caption="No error" value="0"/>
        <value name="YES" caption="Error" value="1"/>
      </value-group>
      <value-group name="SDHC_ACESR__ACMDTEO">
        <value name="NO" caption="No error" value="0"/>
        <value name="YES" caption="Timeout" value="1"/>
      </value-group>
      <value-group name="SDHC_ACESR__ACMD12NE">
        <value name="EXEC" caption="Executed" value="0"/>
        <value name="NOT_EXEC" caption="Not executed" value="1"/>
      </value-group>
      <value-group name="SDHC_ACESR__CMDNI">
        <value name="OK" caption="No error" value="0"/>
        <value name="NOT_ISSUED" caption="Not Issued" value="1"/>
      </value-group>
      <value-group name="SDHC_HC2R__ASINTEN">
        <value name="DISABLED" caption="Disabled" value="0"/>
        <value name="ENABLED" caption="Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_HC2R__DRVSEL">
        <value name="B" caption="Driver Type B is Selected (Default)" value="0"/>
        <value name="A" caption="Driver Type A is Selected" value="1"/>
        <value name="C" caption="Driver Type C is Selected" value="2"/>
        <value name="D" caption="Driver Type D is Selected" value="3"/>
      </value-group>
      <value-group name="SDHC_HC2R__EXTUN">
        <value name="NO" caption="Not Tuned or Tuning Completed" value="0"/>
        <value name="REQUESTED" caption="Execute Tuning" value="1"/>
      </value-group>
      <value-group name="SDHC_HC2R__PVALEN">
        <value name="HOST" caption="SDCLK and Driver Strength are controlled by Host Controller" value="0"/>
        <value name="AUTO" caption="Automatic Selection by Preset Value is Enabled" value="1"/>
      </value-group>
      <value-group name="SDHC_HC2R__SLCKSEL">
        <value name="FIXED" caption="Fixed clock is used to sample data" value="0"/>
        <value name="TUNED" caption="Tuned clock is used to sample data" value="1"/>
      </value-group>
      <value-group name="SDHC_HC2R__UHSMS">
        <value name="SDR12" caption="SDR12" value="0"/>
        <value name="SDR25" caption="SDR25" value="1"/>
        <value name="SDR50" caption="SDR50" value="2"/>
        <value name="SDR104" caption="SDR104" value="3"/>
        <value name="DDR50" caption="DDR50" value="4"/>
      </value-group>
      <value-group name="SDHC_HC2R__VS18EN">
        <value name="S33V" caption="3.3V Signaling" value="0"/>
        <value name="S18V" caption="1.8V Signaling" value="1"/>
      </value-group>
      <value-group name="SDHC_HC2R__HS200EN">
        <value name="SDR12" caption="SDR12" value="0"/>
        <value name="SDR25" caption="SDR25" value="1"/>
        <value name="SDR50" caption="SDR50" value="2"/>
        <value name="SDR104" caption="SDR104" value="3"/>
        <value name="DDR50" caption="DDR50" value="4"/>
      </value-group>
      <value-group name="SDHC_CA0R__ADMA2SUP">
        <value name="NO" caption="ADMA2 not Supported" value="0"/>
        <value name="YES" caption="ADMA2 Supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA0R__ASINTSUP">
        <value name="NO" caption="Asynchronous Interrupt not Supported" value="0"/>
        <value name="YES" caption="Asynchronous Interrupt supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA0R__BASECLKF">
        <value name="OTHER" caption="Get information via another method" value="0"/>
      </value-group>
      <value-group name="SDHC_CA0R__ED8SUP">
        <value name="NO" caption="8-bit Bus Width not Supported" value="0"/>
        <value name="YES" caption="8-bit Bus Width Supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA0R__HSSUP">
        <value name="NO" caption="High Speed not Supported" value="0"/>
        <value name="YES" caption="High Speed Supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA0R__MAXBLKL">
        <value name="512" caption="512 bytes" value="0"/>
        <value name="1024" caption="1024 bytes" value="1"/>
        <value name="2048" caption="2048 bytes" value="2"/>
      </value-group>
      <value-group name="SDHC_CA0R__SB64SUP">
        <value name="NO" caption="32-bit Address Descriptors and System Bus" value="0"/>
        <value name="YES" caption="64-bit Address Descriptors and System Bus" value="1"/>
      </value-group>
      <value-group name="SDHC_CA0R__SDMASUP">
        <value name="NO" caption="SDMA not Supported" value="0"/>
        <value name="YES" caption="SDMA Supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA0R__SLTYPE">
        <value name="REMOVABLE" caption="Removable Card Slot" value="0"/>
        <value name="EMBEDDED" caption="Embedded Slot for One Device" value="1"/>
      </value-group>
      <value-group name="SDHC_CA0R__SRSUP">
        <value name="NO" caption="Suspend/Resume not Supported" value="0"/>
        <value name="YES" caption="Suspend/Resume Supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA0R__TEOCLKF">
        <value name="OTHER" caption="Get information via another method" value="0"/>
      </value-group>
      <value-group name="SDHC_CA0R__TEOCLKU">
        <value name="KHZ" caption="KHz" value="0"/>
        <value name="MHZ" caption="MHz" value="1"/>
      </value-group>
      <value-group name="SDHC_CA0R__V18VSUP">
        <value name="NO" caption="1.8V Not Supported" value="0"/>
        <value name="YES" caption="1.8V Supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA0R__V30VSUP">
        <value name="NO" caption="3.0V Not Supported" value="0"/>
        <value name="YES" caption="3.0V Supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA0R__V33VSUP">
        <value name="NO" caption="3.3V Not Supported" value="0"/>
        <value name="YES" caption="3.3V Supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA1R__CLKMULT">
        <value name="NO" caption="Clock Multiplier is Not Supported" value="0"/>
      </value-group>
      <value-group name="SDHC_CA1R__DDR50SUP">
        <value name="NO" caption="DDR50 is Not Supported" value="0"/>
        <value name="YES" caption="DDR50 is Supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA1R__DRVASUP">
        <value name="NO" caption="Driver Type A is Not Supported" value="0"/>
        <value name="YES" caption="Driver Type A is Supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA1R__DRVCSUP">
        <value name="NO" caption="Driver Type C is Not Supported" value="0"/>
        <value name="YES" caption="Driver Type C is Supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA1R__DRVDSUP">
        <value name="NO" caption="Driver Type D is Not Supported" value="0"/>
        <value name="YES" caption="Driver Type D is Supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA1R__RTMOD">
        <value name="MODE1" caption="Mode 1: Timer 4MB max" value="0"/>
        <value name="MODE2" caption="Mode 2: Timer and Re-Tuning Request 4MB max" value="1"/>
        <value name="MODE3" caption="Mode 3: Auto Re-Tuning (for transfer) Timer and Re-Tuning Request" value="2"/>
      </value-group>
      <value-group name="SDHC_CA1R__SDR50SUP">
        <value name="NO" caption="SDR50 is Not Supported" value="0"/>
        <value name="YES" caption="SDR50 is Supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA1R__SDR104SUP">
        <value name="NO" caption="SDR104 is Not Supported" value="0"/>
        <value name="YES" caption="SDR104 is Supported" value="1"/>
      </value-group>
      <value-group name="SDHC_CA1R__TCNTRT">
        <value name="DISABLED" caption="Re-Tuning Timer disabled" value="0"/>
        <value name="1S" caption="1 second" value="1"/>
        <value name="2S" caption="2 seconds" value="2"/>
        <value name="4S" caption="4 seconds" value="3"/>
        <value name="8S" caption="8 seconds" value="4"/>
        <value name="16S" caption="16 seconds" value="5"/>
        <value name="32S" caption="32 seconds" value="6"/>
        <value name="64S" caption="64 seconds" value="7"/>
        <value name="128S" caption="128 seconds" value="8"/>
        <value name="256S" caption="256 seconds" value="9"/>
        <value name="512S" caption="512 seconds" value="10"/>
        <value name="1024S" caption="1024 seconds" value="11"/>
        <value name="OTHER" caption="Get information from other source" value="15"/>
      </value-group>
      <value-group name="SDHC_CA1R__TSDR50">
        <value name="NO" caption="SDR50 does not require tuning" value="0"/>
        <value name="YES" caption="SDR50 requires tuning" value="1"/>
      </value-group>
      <value-group name="SDHC_MCCAR__MAXCUR18V">
        <value name="OTHER" caption="Get information via another method" value="0"/>
        <value name="4MA" caption="4mA" value="1"/>
        <value name="8MA" caption="8mA" value="2"/>
        <value name="12MA" caption="12mA" value="3"/>
      </value-group>
      <value-group name="SDHC_MCCAR__MAXCUR30V">
        <value name="OTHER" caption="Get information via another method" value="0"/>
        <value name="4MA" caption="4mA" value="1"/>
        <value name="8MA" caption="8mA" value="2"/>
        <value name="12MA" caption="12mA" value="3"/>
      </value-group>
      <value-group name="SDHC_MCCAR__MAXCUR33V">
        <value name="OTHER" caption="Get information via another method" value="0"/>
        <value name="4MA" caption="4mA" value="1"/>
        <value name="8MA" caption="8mA" value="2"/>
        <value name="12MA" caption="12mA" value="3"/>
      </value-group>
      <value-group name="SDHC_FERACES__ACMDCRC">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FERACES__ACMDEND">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FERACES__ACMDIDX">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FERACES__ACMDTEO">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FERACES__ACMD12NE">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FERACES__CMDNI">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FEREIS__ACMD">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FEREIS__ADMA">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FEREIS__BOOTAE">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FEREIS__CMDCRC">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FEREIS__CMDEND">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FEREIS__CMDIDX">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FEREIS__CMDTEO">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FEREIS__CURLIM">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FEREIS__DATCRC">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FEREIS__DATEND">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_FEREIS__DATTEO">
        <value name="NO" caption="No Interrupt" value="0"/>
        <value name="YES" caption="Interrupt is generated" value="1"/>
      </value-group>
      <value-group name="SDHC_AESR__ERRST">
        <value name="STOP" caption="ST_STOP (Stop DMA)" value="0"/>
        <value name="FDS" caption="ST_FDS (Fetch Descriptor)" value="1"/>
        <value name="TFR" caption="ST_TFR (Transfer Data)" value="3"/>
      </value-group>
      <value-group name="SDHC_AESR__LMIS">
        <value name="NO" caption="No Error" value="0"/>
        <value name="YES" caption="Error" value="1"/>
      </value-group>
      <value-group name="SDHC_PVR__CLKGSEL">
        <value name="DIV" caption="Host Controller Ver2.00 Compatible Clock Generator (Divider)" value="0"/>
        <value name="PROG" caption="Programmable Clock Generator" value="1"/>
      </value-group>
      <value-group name="SDHC_PVR__DRVSEL">
        <value name="B" caption="Driver Type B is Selected" value="0"/>
        <value name="A" caption="Driver Type A is Selected" value="1"/>
        <value name="C" caption="Driver Type C is Selected" value="2"/>
        <value name="D" caption="Driver Type D is Selected" value="3"/>
      </value-group>
      <value-group name="SDHC_MC1R__CMDTYP">
        <value name="NORMAL" caption="Not a MMC specific command" value="0"/>
        <value name="WAITIRQ" caption="Wait IRQ Command" value="1"/>
        <value name="STREAM" caption="Stream Command" value="2"/>
        <value name="BOOT" caption="Boot Command" value="3"/>
      </value-group>
      <value-group name="SDHC_ACR__BMAX">
        <value name="INCR16" value="0"/>
        <value name="INCR8" value="1"/>
        <value name="INCR4" value="2"/>
        <value name="SINGLE" value="3"/>
      </value-group>
      <value-group name="SDHC_CC2R__FSDCLKD">
        <value name="NOEFFECT" caption="No effect" value="0"/>
        <value name="DISABLE" caption="SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled" value="1"/>
      </value-group>
      <value-group name="SDHC_DBGR__NIDBG">
        <value name="IDBG" caption="Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer)" value="0"/>
        <value name="NIDBG" caption="Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer)" value="1"/>
      </value-group>
    </module>
    <module name="SERCOM" id="U2201" version="5.0.0" caption="Serial Communication Interface">
      <register-group class="union" union-tag="SERCOM.I2CM_CTRLA.MODE" name="SERCOM" caption="Serial Communication Interface">
        <register-group name="I2CM" name-in-module="SERCOM_I2CM" union-tag-value="5" offset="0"/>
        <register-group name="I2CS" name-in-module="SERCOM_I2CS" union-tag-value="4" offset="0"/>
        <register-group name="SPI" name-in-module="SERCOM_SPI" union-tag-mask="6" union-tag-value="2" offset="0"/>
        <register-group name="USART" name-in-module="SERCOM_USART" union-tag-mask="6" union-tag-value="0" offset="0"/>
      </register-group>
      <register-group name="SERCOM_I2CM" caption="Serial Communication Interface - I2C Master Mode">
        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CM Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="MODE" caption="Operating Mode" mask="0x1C"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x80"/>
          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
          <bitfield name="MEXTTOEN" caption="Master SCL Low Extend Timeout" mask="0x400000"/>
          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
          <bitfield name="INACTOUT" caption="Inactive Time-Out" mask="0x30000000"/>
          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
        </register>
        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CM Control B">
          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
          <bitfield name="QCEN" caption="Quick Command Enable" mask="0x200"/>
          <bitfield name="CMD" caption="Command" mask="0x30000"/>
          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
        </register>
        <register name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="I2CM Control C">
          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x1000000"/>
        </register>
        <register name="BAUD" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="I2CM Baud Rate">
          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
          <bitfield name="BAUDLOW" caption="Baud Rate Value Low" mask="0xFF00"/>
          <bitfield name="HSBAUD" caption="High Speed Baud Rate Value" mask="0xFF0000"/>
          <bitfield name="HSBAUDLOW" caption="High Speed Baud Rate Value Low" mask="0xFF000000"/>
        </register>
        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CM Interrupt Enable Clear">
          <bitfield name="MB" caption="Master On Bus Interrupt Disable" mask="0x1"/>
          <bitfield name="SB" caption="Slave On Bus Interrupt Disable" mask="0x2"/>
          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
        </register>
        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CM Interrupt Enable Set">
          <bitfield name="MB" caption="Master On Bus Interrupt Enable" mask="0x1"/>
          <bitfield name="SB" caption="Slave On Bus Interrupt Enable" mask="0x2"/>
          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
        </register>
        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CM Interrupt Flag Status and Clear">
          <bitfield name="MB" caption="Master On Bus Interrupt" mask="0x1"/>
          <bitfield name="SB" caption="Slave On Bus Interrupt" mask="0x2"/>
          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
        </register>
        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CM Status">
          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
          <bitfield name="ARBLOST" caption="Arbitration Lost" mask="0x2"/>
          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
          <bitfield name="BUSSTATE" caption="Bus State" mask="0x30"/>
          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
          <bitfield name="MEXTTOUT" caption="Master SCL Low Extend Timeout" mask="0x100"/>
          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
          <bitfield name="LENERR" caption="Length Error" mask="0x400"/>
        </register>
        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CM Synchronization Busy">
          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
          <bitfield name="SYSOP" caption="System Operation Synchronization Busy" mask="0x4"/>
          <bitfield name="LENGTH" caption="Length Synchronization Busy" mask="0x10"/>
        </register>
        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CM Address">
          <bitfield name="ADDR" caption="Address Value" mask="0x7FF"/>
          <bitfield name="LENEN" caption="Length Enable" mask="0x2000"/>
          <bitfield name="HS" caption="High Speed Mode" mask="0x4000"/>
          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
          <bitfield name="LEN" caption="Length" mask="0xFF0000"/>
        </register>
        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="I2CM Data">
          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
        </register>
        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="I2CM Debug Control">
          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
        </register>
      </register-group>
      <register-group name="SERCOM_I2CS" caption="Serial Communication Interface - I2C Slave Mode">
        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="I2CS Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="MODE" caption="Operating Mode" mask="0x1C"/>
          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
          <bitfield name="PINOUT" caption="Pin Usage" mask="0x10000"/>
          <bitfield name="SDAHOLD" caption="SDA Hold Time" mask="0x300000"/>
          <bitfield name="SEXTTOEN" caption="Slave SCL Low Extend Timeout" mask="0x800000"/>
          <bitfield name="SPEED" caption="Transfer Speed" mask="0x3000000"/>
          <bitfield name="SCLSM" caption="SCL Clock Stretch Mode" mask="0x8000000"/>
          <bitfield name="LOWTOUTEN" caption="SCL Low Timeout Enable" mask="0x40000000"/>
        </register>
        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="I2CS Control B">
          <bitfield name="SMEN" caption="Smart Mode Enable" mask="0x100"/>
          <bitfield name="GCMD" caption="PMBus Group Command" mask="0x200"/>
          <bitfield name="AACKEN" caption="Automatic Address Acknowledge" mask="0x400"/>
          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
          <bitfield name="CMD" caption="Command" mask="0x30000"/>
          <bitfield name="ACKACT" caption="Acknowledge Action" mask="0x40000"/>
        </register>
        <register name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="I2CS Control C">
          <bitfield name="SDASETUP" caption="SDA Setup Time" mask="0xF"/>
          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x1000000"/>
        </register>
        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="I2CS Interrupt Enable Clear">
          <bitfield name="PREC" caption="Stop Received Interrupt Disable" mask="0x1"/>
          <bitfield name="AMATCH" caption="Address Match Interrupt Disable" mask="0x2"/>
          <bitfield name="DRDY" caption="Data Interrupt Disable" mask="0x4"/>
          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
        </register>
        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="I2CS Interrupt Enable Set">
          <bitfield name="PREC" caption="Stop Received Interrupt Enable" mask="0x1"/>
          <bitfield name="AMATCH" caption="Address Match Interrupt Enable" mask="0x2"/>
          <bitfield name="DRDY" caption="Data Interrupt Enable" mask="0x4"/>
          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
        </register>
        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="I2CS Interrupt Flag Status and Clear">
          <bitfield name="PREC" caption="Stop Received Interrupt" mask="0x1"/>
          <bitfield name="AMATCH" caption="Address Match Interrupt" mask="0x2"/>
          <bitfield name="DRDY" caption="Data Interrupt" mask="0x4"/>
          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
        </register>
        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="I2CS Status">
          <bitfield name="BUSERR" caption="Bus Error" mask="0x1"/>
          <bitfield name="COLL" caption="Transmit Collision" mask="0x2"/>
          <bitfield name="RXNACK" caption="Received Not Acknowledge" mask="0x4"/>
          <bitfield name="DIR" caption="Read/Write Direction" mask="0x8"/>
          <bitfield name="SR" caption="Repeated Start" mask="0x10"/>
          <bitfield name="LOWTOUT" caption="SCL Low Timeout" mask="0x40"/>
          <bitfield name="CLKHOLD" caption="Clock Hold" mask="0x80"/>
          <bitfield name="SEXTTOUT" caption="Slave SCL Low Extend Timeout" mask="0x200"/>
          <bitfield name="HS" caption="High Speed" mask="0x400"/>
          <bitfield name="LENERR" caption="Transaction Length Error" mask="0x800"/>
        </register>
        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="I2CS Synchronization Busy">
          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
          <bitfield name="LENGTH" caption="Length Synchronization Busy" mask="0x10"/>
        </register>
        <register name="LENGTH" offset="0x22" rw="RW" size="2" initval="0x0000" caption="I2CS Length">
          <bitfield name="LEN" caption="Data Length" mask="0xFF"/>
          <bitfield name="LENEN" caption="Data Length Enable" mask="0x100"/>
        </register>
        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="I2CS Address">
          <bitfield name="GENCEN" caption="General Call Address Enable" mask="0x1"/>
          <bitfield name="ADDR" caption="Address Value" mask="0x7FE"/>
          <bitfield name="TENBITEN" caption="Ten Bit Addressing Enable" mask="0x8000"/>
          <bitfield name="ADDRMASK" caption="Address Mask" mask="0x7FE0000"/>
        </register>
        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="I2CS Data">
          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
        </register>
      </register-group>
      <register-group name="SERCOM_SPI" caption="Serial Communication Interface - SPI Mode">
        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="SPI Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="MODE" caption="Operating Mode" mask="0x1C"/>
          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
          <bitfield name="DOPO" caption="Data Out Pinout" mask="0x30000"/>
          <bitfield name="DIPO" caption="Data In Pinout" mask="0x300000"/>
          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
          <bitfield name="CPHA" caption="Clock Phase" mask="0x10000000"/>
          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
        </register>
        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="SPI Control B">
          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
          <bitfield name="PLOADEN" caption="Data Preload Enable" mask="0x40"/>
          <bitfield name="SSDE" caption="Slave Select Low Detect Enable" mask="0x200"/>
          <bitfield name="MSSEN" caption="Master Slave Select Enable" mask="0x2000"/>
          <bitfield name="AMODE" caption="Address Mode" mask="0xC000"/>
          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
        </register>
        <register name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="SPI Control C">
          <bitfield name="ICSPACE" caption="Inter-Character Spacing" mask="0x3F"/>
          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x1000000"/>
        </register>
        <register name="BAUD" offset="0xC" rw="RW" size="1" initval="0x00" caption="SPI Baud Rate">
          <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFF"/>
        </register>
        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="SPI Interrupt Enable Clear">
          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
          <bitfield name="SSL" caption="Slave Select Low Interrupt Disable" mask="0x8"/>
          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
        </register>
        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="SPI Interrupt Enable Set">
          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
          <bitfield name="SSL" caption="Slave Select Low Interrupt Enable" mask="0x8"/>
          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
        </register>
        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="SPI Interrupt Flag Status and Clear">
          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
          <bitfield name="SSL" caption="Slave Select Low Interrupt Flag" mask="0x8"/>
          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
        </register>
        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="SPI Status">
          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
          <bitfield name="LENERR" caption="Transaction Length Error" mask="0x800"/>
        </register>
        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="SPI Synchronization Busy">
          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
          <bitfield name="LENGTH" caption="LENGTH Synchronization Busy" mask="0x10"/>
        </register>
        <register name="LENGTH" offset="0x22" rw="RW" size="2" initval="0x0000" caption="SPI Length">
          <bitfield name="LEN" caption="Data Length" mask="0xFF"/>
          <bitfield name="LENEN" caption="Data Length Enable" mask="0x100"/>
        </register>
        <register name="ADDR" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="SPI Address">
          <bitfield name="ADDR" caption="Address Value" mask="0xFF"/>
          <bitfield name="ADDRMASK" caption="Address Mask" mask="0xFF0000"/>
        </register>
        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="SPI Data">
          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
        </register>
        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="SPI Debug Control">
          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
        </register>
      </register-group>
      <register-group name="SERCOM_USART" caption="Serial Communication Interface - USART Mode">
        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="USART Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="MODE" caption="Operating Mode" mask="0x1C"/>
          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x80"/>
          <bitfield name="IBON" caption="Immediate Buffer Overflow Notification" mask="0x100"/>
          <bitfield name="TXINV" caption="Transmit Data Invert" mask="0x200"/>
          <bitfield name="RXINV" caption="Receive Data Invert" mask="0x400"/>
          <bitfield name="SAMPR" caption="Sample" mask="0xE000"/>
          <bitfield name="TXPO" caption="Transmit Data Pinout" mask="0x30000"/>
          <bitfield name="RXPO" caption="Receive Data Pinout" mask="0x300000"/>
          <bitfield name="SAMPA" caption="Sample Adjustment" mask="0xC00000"/>
          <bitfield name="FORM" caption="Frame Format" mask="0xF000000"/>
          <bitfield name="CMODE" caption="Communication Mode" mask="0x10000000"/>
          <bitfield name="CPOL" caption="Clock Polarity" mask="0x20000000"/>
          <bitfield name="DORD" caption="Data Order" mask="0x40000000"/>
        </register>
        <register name="CTRLB" offset="0x4" rw="RW" size="4" initval="0x00000000" caption="USART Control B">
          <bitfield name="CHSIZE" caption="Character Size" mask="0x7"/>
          <bitfield name="SBMODE" caption="Stop Bit Mode" mask="0x40"/>
          <bitfield name="COLDEN" caption="Collision Detection Enable" mask="0x100"/>
          <bitfield name="SFDE" caption="Start of Frame Detection Enable" mask="0x200"/>
          <bitfield name="ENC" caption="Encoding Format" mask="0x400"/>
          <bitfield name="PMODE" caption="Parity Mode" mask="0x2000"/>
          <bitfield name="TXEN" caption="Transmitter Enable" mask="0x10000"/>
          <bitfield name="RXEN" caption="Receiver Enable" mask="0x20000"/>
          <bitfield name="LINCMD" caption="LIN Command" mask="0x3000000"/>
        </register>
        <register name="CTRLC" offset="0x8" rw="RW" size="4" initval="0x00000000" caption="USART Control C">
          <bitfield name="GTIME" caption="Guard Time" mask="0x7"/>
          <bitfield name="BRKLEN" caption="LIN Master Break Length" mask="0x300"/>
          <bitfield name="HDRDLY" caption="LIN Master Header Delay" mask="0xC00"/>
          <bitfield name="INACK" caption="Inhibit Not Acknowledge" mask="0x10000"/>
          <bitfield name="DSNACK" caption="Disable Successive NACK" mask="0x20000"/>
          <bitfield name="MAXITER" caption="Maximum Iterations" mask="0x700000"/>
          <bitfield name="DATA32B" caption="Data 32 Bit" mask="0x3000000"/>
        </register>
        <register name="BAUD" offset="0xC" rw="RW" size="2" initval="0x0000" caption="USART Baud Rate">
          <mode name="DEFAULT_MODE">
            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
          </mode>
          <mode name="FRAC_MODE">
            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
          </mode>
          <mode name="FRACFP_MODE">
            <bitfield name="BAUD" caption="Baud Rate Value" mask="0x1FFF"/>
            <bitfield name="FP" caption="Fractional Part" mask="0xE000"/>
          </mode>
          <mode name="USARTFP_MODE">
            <bitfield name="BAUD" caption="Baud Rate Value" mask="0xFFFF"/>
          </mode>
        </register>
        <register name="RXPL" offset="0xE" rw="RW" size="1" initval="0x00" caption="USART Receive Pulse Length">
          <bitfield name="RXPL" caption="Receive Pulse Length" mask="0xFF"/>
        </register>
        <register name="INTENCLR" offset="0x14" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="USART Interrupt Enable Clear">
          <bitfield name="DRE" caption="Data Register Empty Interrupt Disable" mask="0x1"/>
          <bitfield name="TXC" caption="Transmit Complete Interrupt Disable" mask="0x2"/>
          <bitfield name="RXC" caption="Receive Complete Interrupt Disable" mask="0x4"/>
          <bitfield name="RXS" caption="Receive Start Interrupt Disable" mask="0x8"/>
          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Disable" mask="0x10"/>
          <bitfield name="RXBRK" caption="Break Received Interrupt Disable" mask="0x20"/>
          <bitfield name="ERROR" caption="Combined Error Interrupt Disable" mask="0x80"/>
        </register>
        <register name="INTENSET" offset="0x16" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="USART Interrupt Enable Set">
          <bitfield name="DRE" caption="Data Register Empty Interrupt Enable" mask="0x1"/>
          <bitfield name="TXC" caption="Transmit Complete Interrupt Enable" mask="0x2"/>
          <bitfield name="RXC" caption="Receive Complete Interrupt Enable" mask="0x4"/>
          <bitfield name="RXS" caption="Receive Start Interrupt Enable" mask="0x8"/>
          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt Enable" mask="0x10"/>
          <bitfield name="RXBRK" caption="Break Received Interrupt Enable" mask="0x20"/>
          <bitfield name="ERROR" caption="Combined Error Interrupt Enable" mask="0x80"/>
        </register>
        <register name="INTFLAG" offset="0x18" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="USART Interrupt Flag Status and Clear">
          <bitfield name="DRE" caption="Data Register Empty Interrupt" mask="0x1"/>
          <bitfield name="TXC" caption="Transmit Complete Interrupt" mask="0x2"/>
          <bitfield name="RXC" caption="Receive Complete Interrupt" mask="0x4"/>
          <bitfield name="RXS" caption="Receive Start Interrupt" mask="0x8"/>
          <bitfield name="CTSIC" caption="Clear To Send Input Change Interrupt" mask="0x10"/>
          <bitfield name="RXBRK" caption="Break Received Interrupt" mask="0x20"/>
          <bitfield name="ERROR" caption="Combined Error Interrupt" mask="0x80"/>
        </register>
        <register name="STATUS" offset="0x1A" rw="RW" size="2" initval="0x0000" caption="USART Status">
          <bitfield name="PERR" caption="Parity Error" mask="0x1"/>
          <bitfield name="FERR" caption="Frame Error" mask="0x2"/>
          <bitfield name="BUFOVF" caption="Buffer Overflow" mask="0x4"/>
          <bitfield name="CTS" caption="Clear To Send" mask="0x8"/>
          <bitfield name="ISF" caption="Inconsistent Sync Field" mask="0x10"/>
          <bitfield name="COLL" caption="Collision Detected" mask="0x20"/>
          <bitfield name="TXE" caption="Transmitter Empty" mask="0x40"/>
          <bitfield name="ITER" caption="Maximum Number of Repetitions Reached" mask="0x80"/>
        </register>
        <register name="SYNCBUSY" offset="0x1C" rw="R" size="4" initval="0x00000000" caption="USART Synchronization Busy">
          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
          <bitfield name="ENABLE" caption="SERCOM Enable Synchronization Busy" mask="0x2"/>
          <bitfield name="CTRLB" caption="CTRLB Synchronization Busy" mask="0x4"/>
          <bitfield name="RXERRCNT" caption="RXERRCNT Synchronization Busy" mask="0x8"/>
          <bitfield name="LENGTH" caption="LENGTH Synchronization Busy" mask="0x10"/>
        </register>
        <register name="RXERRCNT" offset="0x20" rw="R" size="1" initval="0x00" caption="USART Receive Error Count">
        </register>
        <register name="LENGTH" offset="0x22" rw="RW" size="2" initval="0x0000" caption="USART Length">
          <bitfield name="LEN" caption="Data Length" mask="0xFF"/>
          <bitfield name="LENEN" caption="Data Length Enable" mask="0x300"/>
        </register>
        <register name="DATA" offset="0x28" rw="RW" size="4" initval="0x00000000" caption="USART Data">
          <bitfield name="DATA" caption="Data Value" mask="0xFFFFFFFF"/>
        </register>
        <register name="DBGCTRL" offset="0x30" rw="RW" size="1" initval="0x00" caption="USART Debug Control">
          <bitfield name="DBGSTOP" caption="Debug Mode" mask="0x1"/>
        </register>
      </register-group>
    </module>
    <module name="SUPC" id="U2407" version="1.0.0" caption="Supply Controller">
      <register-group name="SUPC" caption="Supply Controller">
        <register name="INTENCLR" offset="0x0" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x1"/>
          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x2"/>
          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x4"/>
          <bitfield name="BOD12RDY" caption="BOD12 Ready" mask="0x8"/>
          <bitfield name="BOD12DET" caption="BOD12 Detection" mask="0x10"/>
          <bitfield name="B12SRDY" caption="BOD12 Synchronization Ready" mask="0x20"/>
          <bitfield name="VREGRDY" caption="Voltage Regulator Ready" mask="0x100"/>
          <bitfield name="VCORERDY" caption="VDDCORE Ready" mask="0x400"/>
        </register>
        <register name="INTENSET" offset="0x4" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x1"/>
          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x2"/>
          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x4"/>
          <bitfield name="BOD12RDY" caption="BOD12 Ready" mask="0x8"/>
          <bitfield name="BOD12DET" caption="BOD12 Detection" mask="0x10"/>
          <bitfield name="B12SRDY" caption="BOD12 Synchronization Ready" mask="0x20"/>
          <bitfield name="VREGRDY" caption="Voltage Regulator Ready" mask="0x100"/>
          <bitfield name="VCORERDY" caption="VDDCORE Ready" mask="0x400"/>
        </register>
        <register name="INTFLAG" offset="0x8" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x1"/>
          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x2"/>
          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x4"/>
          <bitfield name="BOD12RDY" caption="BOD12 Ready" mask="0x8"/>
          <bitfield name="BOD12DET" caption="BOD12 Detection" mask="0x10"/>
          <bitfield name="B12SRDY" caption="BOD12 Synchronization Ready" mask="0x20"/>
          <bitfield name="VREGRDY" caption="Voltage Regulator Ready" mask="0x100"/>
          <bitfield name="VCORERDY" caption="VDDCORE Ready" mask="0x400"/>
        </register>
        <register name="STATUS" offset="0xC" rw="R" size="4" initval="0x00000000" caption="Power and Clocks Status">
          <bitfield name="BOD33RDY" caption="BOD33 Ready" mask="0x1"/>
          <bitfield name="BOD33DET" caption="BOD33 Detection" mask="0x2"/>
          <bitfield name="B33SRDY" caption="BOD33 Synchronization Ready" mask="0x4"/>
          <bitfield name="BOD12RDY" caption="BOD12 Ready" mask="0x8"/>
          <bitfield name="BOD12DET" caption="BOD12 Detection" mask="0x10"/>
          <bitfield name="B12SRDY" caption="BOD12 Synchronization Ready" mask="0x20"/>
          <bitfield name="VREGRDY" caption="Voltage Regulator Ready" mask="0x100"/>
          <bitfield name="VCORERDY" caption="VDDCORE Ready" mask="0x400"/>
        </register>
        <register name="BOD33" offset="0x10" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="BOD33 Control">
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="ACTION" caption="Action when Threshold Crossed" mask="0xC" values="SUPC_BOD33__ACTION"/>
          <bitfield name="STDBYCFG" caption="Configuration in Standby mode" mask="0x10"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby mode" mask="0x20"/>
          <bitfield name="RUNHIB" caption="Run in Hibernate mode" mask="0x40"/>
          <bitfield name="RUNBKUP" caption="Run in Backup mode" mask="0x80"/>
          <bitfield name="HYST" caption="Hysteresis value" mask="0xF00"/>
          <bitfield name="PSEL" caption="Prescaler Select" mask="0x7000" values="SUPC_BOD33__PSEL"/>
          <bitfield name="LEVEL" caption="Threshold Level for VDD" mask="0xFF0000"/>
          <bitfield name="VBATLEVEL" caption="Threshold Level in battery backup sleep mode for VBAT" mask="0xFF000000"/>
        </register>
        <register name="BOD12" offset="0x14" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="BOD12 Control">
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="HYST" caption="Hysteresis Enable" mask="0x4"/>
          <bitfield name="ACTION" caption="Action when Threshold Crossed" mask="0x18" values="SUPC_BOD12__ACTION"/>
          <bitfield name="STDBYCFG" caption="Configuration in Standby mode" mask="0x20"/>
          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x40"/>
          <bitfield name="ACTCFG" caption="Configuration in Active mode" mask="0x100"/>
          <bitfield name="PSEL" caption="Prescaler Select" mask="0xF000" values="SUPC_BOD12__PSEL"/>
          <bitfield name="LEVEL" caption="Threshold Level" mask="0x3F0000"/>
        </register>
        <register name="VREG" offset="0x18" rw="RW" size="4" initval="0x00000002" caption="VREG Control">
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="SEL" caption="Voltage Regulator Selection" mask="0x4" values="SUPC_VREG__SEL"/>
          <bitfield name="RUNBKUP" caption="Run in Backup mode" mask="0x80"/>
          <bitfield name="VSEN" caption="Voltage Scaling Enable" mask="0x10000"/>
          <bitfield name="VSPER" caption="Voltage Scaling Period" mask="0x7000000"/>
        </register>
        <register name="VREF" offset="0x1C" rw="RW" size="4" initval="0x00000000" caption="VREF Control">
          <bitfield name="TSEN" caption="Temperature Sensor Output Enable" mask="0x2"/>
          <bitfield name="VREFOE" caption="Voltage Reference Output Enable" mask="0x4"/>
          <bitfield name="TSSEL" caption="Temperature Sensor Selection" mask="0x8"/>
          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x40"/>
          <bitfield name="ONDEMAND" caption="On Demand Contrl" mask="0x80"/>
          <bitfield name="SEL" caption="Voltage Reference Selection" mask="0xF0000" values="SUPC_VREF__SEL"/>
        </register>
        <register name="BBPS" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Battery Backup Power Switch">
          <bitfield name="CONF" caption="Battery Backup Configuration" mask="0x1" values="SUPC_BBPS__CONF"/>
          <bitfield name="WAKEEN" caption="Wake Enable" mask="0x4"/>
        </register>
        <register name="BKOUT" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Backup Output Control">
          <bitfield name="EN" caption="Enable Output" mask="0x3"/>
          <bitfield name="CLR" caption="Clear Output" mask="0x300"/>
          <bitfield name="SET" caption="Set Output" mask="0x30000"/>
          <bitfield name="RTCTGL" caption="RTC Toggle Output" mask="0x3000000"/>
        </register>
        <register name="BKIN" offset="0x28" rw="R" size="4" initval="0x00000000" caption="Backup Input Control">
          <bitfield name="BKIN" caption="Backup Input Value" mask="0xFF"/>
        </register>
      </register-group>
      <value-group name="SUPC_BOD33__ACTION">
        <value name="NONE" caption="No action" value="0x0"/>
        <value name="RESET" caption="The BOD33 generates a reset" value="0x1"/>
        <value name="INT" caption="The BOD33 generates an interrupt" value="0x2"/>
        <value name="BKUP" caption="The BOD33 puts the device in backup sleep mode" value="0x3"/>
      </value-group>
      <value-group name="SUPC_BOD33__PSEL">
        <value name="NODIV" caption="Not divided" value="0x0"/>
        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
      </value-group>
      <value-group name="SUPC_BOD12__ACTION">
        <value name="NONE" caption="No action" value="0x0"/>
        <value name="RESET" caption="The BOD12 generates a reset" value="0x1"/>
        <value name="INT" caption="The BOD12 generates an interrupt" value="0x2"/>
      </value-group>
      <value-group name="SUPC_BOD12__PSEL">
        <value name="DIV2" caption="Divide clock by 2" value="0x0"/>
        <value name="DIV4" caption="Divide clock by 4" value="0x1"/>
        <value name="DIV8" caption="Divide clock by 8" value="0x2"/>
        <value name="DIV16" caption="Divide clock by 16" value="0x3"/>
        <value name="DIV32" caption="Divide clock by 32" value="0x4"/>
        <value name="DIV64" caption="Divide clock by 64" value="0x5"/>
        <value name="DIV128" caption="Divide clock by 128" value="0x6"/>
        <value name="DIV256" caption="Divide clock by 256" value="0x7"/>
        <value name="DIV512" caption="Divide clock by 512" value="0x8"/>
        <value name="DIV1024" caption="Divide clock by 1024" value="0x9"/>
        <value name="DIV2048" caption="Divide clock by 2048" value="0xA"/>
        <value name="DIV4096" caption="Divide clock by 4096" value="0xB"/>
        <value name="DIV8192" caption="Divide clock by 8192" value="0xC"/>
        <value name="DIV16384" caption="Divide clock by 16384" value="0xD"/>
        <value name="DIV32768" caption="Divide clock by 32768" value="0xE"/>
        <value name="DIV65536" caption="Divide clock by 65536" value="0xF"/>
      </value-group>
      <value-group name="SUPC_VREG__SEL">
        <value name="LDO" caption="LDO selection" value="0x0"/>
        <value name="BUCK" caption="Buck selection" value="0x1"/>
      </value-group>
      <value-group name="SUPC_VREF__SEL">
        <value name="1V0" caption="1.0V voltage reference typical value" value="0x0"/>
        <value name="1V1" caption="1.1V voltage reference typical value" value="0x1"/>
        <value name="1V2" caption="1.2V voltage reference typical value" value="0x2"/>
        <value name="1V25" caption="1.25V voltage reference typical value" value="0x3"/>
        <value name="2V0" caption="2.0V voltage reference typical value" value="0x4"/>
        <value name="2V2" caption="2.2V voltage reference typical value" value="0x5"/>
        <value name="2V4" caption="2.4V voltage reference typical value" value="0x6"/>
        <value name="2V5" caption="2.5V voltage reference typical value" value="0x7"/>
      </value-group>
      <value-group name="SUPC_BBPS__CONF">
        <value name="BOD33" caption="The power switch is handled by the BOD33" value="0x0"/>
        <value name="FORCED" caption="In Backup Domain, the backup domain is always supplied by battery backup power" value="0x1"/>
      </value-group>
    </module>
    <module name="TAL" id="U2253" version="2.0.0" caption="Trigger Allocator">
      <register-group name="CPUIRQS" size="0x20">
        <register name="CPUIRQS" offset="0x0" rw="R" size="4" count="5" initval="0x00000000" caption="Interrupt Status m for CPU n">
          <bitfield name="CPUIRQS" caption="Interrupt Requests for CPU n" mask="0xFFFFFFFF"/>
        </register>
      </register-group>
      <register-group name="CTIS" size="0x2">
        <register name="CTICTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Cross-Trigger Interface n Control A">
          <bitfield name="BRK" caption="Action when global break issued" mask="0x3" values="TAL_CTICTRLA__BRK"/>
          <bitfield name="RESTART" caption="Action when global restart issued" mask="0x4" values="TAL_CTICTRLA__RESTART"/>
          <bitfield name="IPS" caption="Action when inter-process resource freed" mask="0x8" values="TAL_CTICTRLA__IPS"/>
        </register>
        <register name="CTIMASK" offset="0x1" rw="RW" size="1" initval="0x00" caption="Cross-Trigger Interface n Mask">
          <bitfield name="CPU0" caption="CPU 0 Break Master" mask="0x1"/>
          <bitfield name="CPU1" caption="CPU 1 Break Master" mask="0x2"/>
          <bitfield name="EVBRK" caption="Event Break Master" mask="0x40"/>
          <bitfield name="EXTBRK" caption="External Break Master" mask="0x80"/>
        </register>
      </register-group>
      <register-group name="SMASKS" size="0x8">
        <register name="SMASK" offset="0x0" rw="RW" size="4" count="2" initval="0x00000000" caption="Inter-Process Signal Mask m for CPU n">
          <bitfield name="IPS0" caption="Inter-Process Signal 0" mask="0x1"/>
          <bitfield name="IPS1" caption="Inter-Process Signal 1" mask="0x2"/>
          <bitfield name="IPS2" caption="Inter-Process Signal 2" mask="0x4"/>
          <bitfield name="IPS3" caption="Inter-Process Signal 3" mask="0x8"/>
          <bitfield name="IPS4" caption="Inter-Process Signal 4" mask="0x10"/>
          <bitfield name="IPS5" caption="Inter-Process Signal 5" mask="0x20"/>
          <bitfield name="IPS6" caption="Inter-Process Signal 6" mask="0x40"/>
          <bitfield name="IPS7" caption="Inter-Process Signal 7" mask="0x80"/>
          <bitfield name="IPS8" caption="Inter-Process Signal 8" mask="0x100"/>
          <bitfield name="IPS9" caption="Inter-Process Signal 9" mask="0x200"/>
          <bitfield name="IPS10" caption="Inter-Process Signal 10" mask="0x400"/>
          <bitfield name="IPS11" caption="Inter-Process Signal 11" mask="0x800"/>
          <bitfield name="IPS12" caption="Inter-Process Signal 12" mask="0x1000"/>
          <bitfield name="IPS13" caption="Inter-Process Signal 13" mask="0x2000"/>
          <bitfield name="IPS14" caption="Inter-Process Signal 14" mask="0x4000"/>
          <bitfield name="IPS15" caption="Inter-Process Signal 15" mask="0x8000"/>
          <bitfield name="IPS16" caption="Inter-Process Signal 16" mask="0x10000"/>
          <bitfield name="IPS17" caption="Inter-Process Signal 17" mask="0x20000"/>
          <bitfield name="IPS18" caption="Inter-Process Signal 18" mask="0x40000"/>
          <bitfield name="IPS19" caption="Inter-Process Signal 19" mask="0x80000"/>
          <bitfield name="IPS20" caption="Inter-Process Signal 20" mask="0x100000"/>
          <bitfield name="IPS21" caption="Inter-Process Signal 21" mask="0x200000"/>
          <bitfield name="IPS22" caption="Inter-Process Signal 22" mask="0x400000"/>
          <bitfield name="IPS23" caption="Inter-Process Signal 23" mask="0x800000"/>
          <bitfield name="IPS24" caption="Inter-Process Signal 24" mask="0x1000000"/>
          <bitfield name="IPS25" caption="Inter-Process Signal 25" mask="0x2000000"/>
          <bitfield name="IPS26" caption="Inter-Process Signal 26" mask="0x4000000"/>
          <bitfield name="IPS27" caption="Inter-Process Signal 27" mask="0x8000000"/>
          <bitfield name="IPS28" caption="Inter-Process Signal 28" mask="0x10000000"/>
          <bitfield name="IPS29" caption="Inter-Process Signal 29" mask="0x20000000"/>
          <bitfield name="IPS30" caption="Inter-Process Signal 30" mask="0x40000000"/>
          <bitfield name="IPS31" caption="Inter-Process Signal 31" mask="0x80000000"/>
        </register>
      </register-group>
      <register-group name="TAL" caption="Trigger Allocator">
        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
        </register>
        <register name="EXTCTRL" offset="0x1" rw="RW" size="1" initval="0x00" caption="External Break Control">
          <bitfield name="ENABLE" caption="Enable BRK Pin" mask="0x1"/>
          <bitfield name="INV" caption="Invert BRK Pin" mask="0x2"/>
        </register>
        <register name="EVCTRL" offset="0x4" rw="RW" size="2" initval="0x0000" caption="Event Control">
          <bitfield name="BRKEI" caption="Break Input Event Enable" mask="0x1"/>
          <bitfield name="BRKEO" caption="Break Output Event Enable" mask="0x2"/>
          <bitfield name="IRQMONEO0" caption="Interrupt Request Monitor 0 Output Event Enable" mask="0x4"/>
        </register>
        <register name="INTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
          <bitfield name="BRK" caption="Break Interrupt Enable" mask="0x1"/>
          <bitfield name="IPS0" caption="Inter-Processor Signal Interrupt Enable for CPU 0" mask="0x2"/>
          <bitfield name="IPS1" caption="Inter-Processor Signal Interrupt Enable for CPU 1" mask="0x4"/>
        </register>
        <register name="INTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
          <bitfield name="BRK" caption="Break Interrupt Enable" mask="0x1"/>
          <bitfield name="IPS0" caption="Inter-Processor Signal Interrupt Enable for CPU 0" mask="0x2"/>
          <bitfield name="IPS1" caption="Inter-Processor Signal Interrupt Enable for CPU 1" mask="0x4"/>
        </register>
        <register name="INTFLAG" offset="0xA" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
          <bitfield name="BRK" caption="Break" mask="0x1"/>
          <bitfield name="IPS0" caption="Inter-Processor Signal for CPU 0" mask="0x2"/>
          <bitfield name="IPS1" caption="Inter-Processor Signal for CPU 1" mask="0x4"/>
        </register>
        <register name="GLOBMASK" offset="0xB" rw="RW" size="1" initval="0x00" caption="Global Break Requests Mask">
          <bitfield name="CPU0" caption="CPU 0 Break Master" mask="0x1"/>
          <bitfield name="CPU1" caption="CPU 1 Break Master" mask="0x2"/>
          <bitfield name="EVBRK" caption="Event Break Master" mask="0x40"/>
          <bitfield name="EXTBRK" caption="External Break Master" mask="0x80"/>
        </register>
        <register name="HALT" offset="0xC" rw="W" size="1" initval="0x00" caption="Debug Halt Request">
          <bitfield name="CPU0" caption="CPU 0 Break Master" mask="0x1"/>
          <bitfield name="CPU1" caption="CPU 1 Break Master" mask="0x2"/>
          <bitfield name="EVBRK" caption="Event Break Master" mask="0x40"/>
          <bitfield name="EXTBRK" caption="External Break Master" mask="0x80"/>
        </register>
        <register name="RESTART" offset="0xD" rw="W" size="1" initval="0x00" caption="Debug Restart Request">
          <bitfield name="CPU0" caption="CPU 0 Break Master" mask="0x1"/>
          <bitfield name="CPU1" caption="CPU 1 Break Master" mask="0x2"/>
          <bitfield name="EXTBRK" caption="External Break Master" mask="0x80"/>
        </register>
        <register name="BRKSTATUS" offset="0xE" rw="R" size="2" initval="0x0000" caption="Break Request Status">
          <bitfield name="CPU0" caption="CPU 0 Break Request" mask="0x3"/>
          <bitfield name="CPU1" caption="CPU 1 Break Request" mask="0xC"/>
          <bitfield name="EVBRK" caption="Event Break Request" mask="0x3000"/>
          <bitfield name="EXTBRK" caption="External Break Request" mask="0xC000"/>
        </register>
        <register-group name="CTIS" name-in-module="CTIS" offset="0x010" count="4"/>
        <register name="INTSTATUS" offset="0x20" rw="R" size="1" count="137" initval="0x00" caption="Interrupt n Status">
          <bitfield name="IRQ0" caption="Interrupt Status for Interrupt Request 0 within Interrupt n" mask="0x1"/>
          <bitfield name="IRQ1" caption="Interrupt Status for Interrupt Request 1 within Interrupt n" mask="0x2"/>
          <bitfield name="IRQ2" caption="Interrupt Status for Interrupt Request 2 within Interrupt n" mask="0x4"/>
          <bitfield name="IRQ3" caption="Interrupt Status for Interrupt Request 3 within Interrupt n" mask="0x8"/>
          <bitfield name="IRQ4" caption="Interrupt Status for Interrupt Request 4 within Interrupt n" mask="0x10"/>
          <bitfield name="IRQ5" caption="Interrupt Status for Interrupt Request 5 within Interrupt n" mask="0x20"/>
          <bitfield name="IRQ6" caption="Interrupt Status for Interrupt Request 6 within Interrupt n" mask="0x40"/>
          <bitfield name="IRQ7" caption="Interrupt Status for Interrupt Request 7 within Interrupt n" mask="0x80"/>
        </register>
        <register name="DMACPUSEL0" offset="0x110" rw="RW" size="4" initval="0x00000000" caption="DMA Channel Interrupts CPU Select 0">
          <bitfield name="CH0" caption="DMA Channel 0 Interrupt CPU Select" mask="0x1"/>
          <bitfield name="CH1" caption="DMA Channel 1 Interrupt CPU Select" mask="0x4"/>
          <bitfield name="CH2" caption="DMA Channel 2 Interrupt CPU Select" mask="0x10"/>
          <bitfield name="CH3" caption="DMA Channel 3 Interrupt CPU Select" mask="0x40"/>
          <bitfield name="CH4" caption="DMA Channel 4 Interrupt CPU Select" mask="0x100"/>
          <bitfield name="CH5" caption="DMA Channel 5 Interrupt CPU Select" mask="0x400"/>
          <bitfield name="CH6" caption="DMA Channel 6 Interrupt CPU Select" mask="0x1000"/>
          <bitfield name="CH7" caption="DMA Channel 7 Interrupt CPU Select" mask="0x4000"/>
          <bitfield name="CH8" caption="DMA Channel 8 Interrupt CPU Select" mask="0x10000"/>
          <bitfield name="CH9" caption="DMA Channel 9 Interrupt CPU Select" mask="0x40000"/>
          <bitfield name="CH10" caption="DMA Channel 10 Interrupt CPU Select" mask="0x100000"/>
          <bitfield name="CH11" caption="DMA Channel 11 Interrupt CPU Select" mask="0x400000"/>
          <bitfield name="CH12" caption="DMA Channel 12 Interrupt CPU Select" mask="0x1000000"/>
          <bitfield name="CH13" caption="DMA Channel 13 Interrupt CPU Select" mask="0x4000000"/>
          <bitfield name="CH14" caption="DMA Channel 14 Interrupt CPU Select" mask="0x10000000"/>
          <bitfield name="CH15" caption="DMA Channel 15 Interrupt CPU Select" mask="0x40000000"/>
        </register>
        <register name="DMACPUSEL1" offset="0x114" rw="RW" size="4" initval="0x00000000" caption="DMA Channel Interrupts CPU Select 1">
          <bitfield name="CH16" caption="DMA Channel 16 Interrupt CPU Select" mask="0x1"/>
          <bitfield name="CH17" caption="DMA Channel 17 Interrupt CPU Select" mask="0x4"/>
          <bitfield name="CH18" caption="DMA Channel 18 Interrupt CPU Select" mask="0x10"/>
          <bitfield name="CH19" caption="DMA Channel 19 Interrupt CPU Select" mask="0x40"/>
          <bitfield name="CH20" caption="DMA Channel 20 Interrupt CPU Select" mask="0x100"/>
          <bitfield name="CH21" caption="DMA Channel 21 Interrupt CPU Select" mask="0x400"/>
          <bitfield name="CH22" caption="DMA Channel 22 Interrupt CPU Select" mask="0x1000"/>
          <bitfield name="CH23" caption="DMA Channel 23 Interrupt CPU Select" mask="0x4000"/>
          <bitfield name="CH24" caption="DMA Channel 24 Interrupt CPU Select" mask="0x10000"/>
          <bitfield name="CH25" caption="DMA Channel 25 Interrupt CPU Select" mask="0x40000"/>
          <bitfield name="CH26" caption="DMA Channel 26 Interrupt CPU Select" mask="0x100000"/>
          <bitfield name="CH27" caption="DMA Channel 27 Interrupt CPU Select" mask="0x400000"/>
          <bitfield name="CH28" caption="DMA Channel 28 Interrupt CPU Select" mask="0x1000000"/>
          <bitfield name="CH29" caption="DMA Channel 29 Interrupt CPU Select" mask="0x4000000"/>
          <bitfield name="CH30" caption="DMA Channel 30 Interrupt CPU Select" mask="0x10000000"/>
          <bitfield name="CH31" caption="DMA Channel 31 Interrupt CPU Select" mask="0x40000000"/>
        </register>
        <register name="EVCPUSEL0" offset="0x118" rw="RW" size="4" initval="0x00000000" caption="EVSYS Channel Interrupts CPU Select 0">
          <bitfield name="CH0" caption="Event Channel 0 Interrupt CPU Select" mask="0x1"/>
          <bitfield name="CH1" caption="Event Channel 1 Interrupt CPU Select" mask="0x4"/>
          <bitfield name="CH2" caption="Event Channel 2 Interrupt CPU Select" mask="0x10"/>
          <bitfield name="CH3" caption="Event Channel 3 Interrupt CPU Select" mask="0x40"/>
          <bitfield name="CH4" caption="Event Channel 4 Interrupt CPU Select" mask="0x100"/>
          <bitfield name="CH5" caption="Event Channel 5 Interrupt CPU Select" mask="0x400"/>
          <bitfield name="CH6" caption="Event Channel 6 Interrupt CPU Select" mask="0x1000"/>
          <bitfield name="CH7" caption="Event Channel 7 Interrupt CPU Select" mask="0x4000"/>
          <bitfield name="CH8" caption="Event Channel 8 Interrupt CPU Select" mask="0x10000"/>
          <bitfield name="CH9" caption="Event Channel 9 Interrupt CPU Select" mask="0x40000"/>
          <bitfield name="CH10" caption="Event Channel 10 Interrupt CPU Select" mask="0x100000"/>
          <bitfield name="CH11" caption="Event Channel 11 Interrupt CPU Select" mask="0x400000"/>
        </register>
        <register name="EICCPUSEL0" offset="0x120" rw="RW" size="4" initval="0x00000000" caption="EIC External Interrupts CPU Select 0">
          <bitfield name="EXTINT0" caption="External Interrupt 0 CPU Select" mask="0x1"/>
          <bitfield name="EXTINT1" caption="External Interrupt 1 CPU Select" mask="0x4"/>
          <bitfield name="EXTINT2" caption="External Interrupt 2 CPU Select" mask="0x10"/>
          <bitfield name="EXTINT3" caption="External Interrupt 3 CPU Select" mask="0x40"/>
          <bitfield name="EXTINT4" caption="External Interrupt 4 CPU Select" mask="0x100"/>
          <bitfield name="EXTINT5" caption="External Interrupt 5 CPU Select" mask="0x400"/>
          <bitfield name="EXTINT6" caption="External Interrupt 6 CPU Select" mask="0x1000"/>
          <bitfield name="EXTINT7" caption="External Interrupt 7 CPU Select" mask="0x4000"/>
          <bitfield name="EXTINT8" caption="External Interrupt 8 CPU Select" mask="0x10000"/>
          <bitfield name="EXTINT9" caption="External Interrupt 9 CPU Select" mask="0x40000"/>
          <bitfield name="EXTINT10" caption="External Interrupt 10 CPU Select" mask="0x100000"/>
          <bitfield name="EXTINT11" caption="External Interrupt 11 CPU Select" mask="0x400000"/>
          <bitfield name="EXTINT12" caption="External Interrupt 12 CPU Select" mask="0x1000000"/>
          <bitfield name="EXTINT13" caption="External Interrupt 13 CPU Select" mask="0x4000000"/>
          <bitfield name="EXTINT14" caption="External Interrupt 14 CPU Select" mask="0x10000000"/>
          <bitfield name="EXTINT15" caption="External Interrupt 15 CPU Select" mask="0x40000000"/>
        </register>
        <register name="INTCPUSEL0" offset="0x128" rw="RW" size="4" initval="0x00000000" caption="Interrupts CPU Select 0">
          <bitfield name="PAC" caption="PAC Interrupt CPU Select" mask="0x1"/>
          <bitfield name="PM" caption="PM Interrupt CPU Select" mask="0x4"/>
          <bitfield name="MCLK" caption="MCLK Interrupt CPU Select" mask="0x10"/>
          <bitfield name="OSCCTRL" caption="OSCCTRL Interrupt CPU Select" mask="0x100"/>
          <bitfield name="OSC32KCTRL" caption="OSC32KCTRL Interrupt CPU Select" mask="0x400"/>
          <bitfield name="SUPC" caption="SUPC Interrupt CPU Select" mask="0x1000"/>
          <bitfield name="WDT" caption="WDT Interrupt CPU Select" mask="0x10000"/>
          <bitfield name="RTC" caption="RTC Interrupt CPU Select" mask="0x40000"/>
          <bitfield name="EIC" caption="EIC Interrupt CPU Select" mask="0x100000"/>
          <bitfield name="FREQM" caption="FREQM Interrupt CPU Select" mask="0x400000"/>
          <bitfield name="SERCOM0" caption="SERCOM0 Interrupt CPU Select" mask="0x1000000"/>
          <bitfield name="SERCOM1" caption="SERCOM1 Interrupt CPU Select" mask="0x4000000"/>
          <bitfield name="TC0" caption="TC0 Interrupt CPU Select" mask="0x10000000"/>
          <bitfield name="TC1" caption="TC1 Interrupt CPU Select" mask="0x40000000"/>
        </register>
        <register name="INTCPUSEL1" offset="0x12C" rw="RW" size="4" initval="0x00000000" caption="Interrupts CPU Select 1">
        </register>
        <register name="INTCPUSEL2" offset="0x130" rw="RW" size="4" initval="0x00000000" caption="Interrupts CPU Select 2">
          <bitfield name="USB" caption="USB Interrupt CPU Select" mask="0x1"/>
          <bitfield name="NVMCTRL" caption="NVMCTRL Interrupt CPU Select" mask="0x10"/>
          <bitfield name="DMAC" caption="DMAC Interrupt CPU Select" mask="0x400"/>
          <bitfield name="EVSYS" caption="EVSYS Interrupt CPU Select" mask="0x4000"/>
          <bitfield name="PICOP" caption="PICOP Interrupt CPU Select" mask="0x10000"/>
          <bitfield name="SERCOM2" caption="SERCOM2 Interrupt CPU Select" mask="0x40000"/>
          <bitfield name="SERCOM3" caption="SERCOM3 Interrupt CPU Select" mask="0x100000"/>
          <bitfield name="TCC0" caption="TCC0 Interrupt CPU Select" mask="0x400000"/>
          <bitfield name="TCC1" caption="TCC1 Interrupt CPU Select" mask="0x1000000"/>
          <bitfield name="TC2" caption="TC2 Interrupt CPU Select" mask="0x4000000"/>
          <bitfield name="TC3" caption="TC3 Interrupt CPU Select" mask="0x10000000"/>
          <bitfield name="TAL" caption="TAL Interrupt CPU Select" mask="0x40000000"/>
        </register>
        <register name="INTCPUSEL3" offset="0x134" rw="RW" size="4" initval="0x00000000" caption="Interrupts CPU Select 3">
          <bitfield name="RAMECC" caption="RAMECC Interrupt CPU Select" mask="0x1"/>
        </register>
        <register name="INTCPUSEL4" offset="0x138" rw="RW" size="4" initval="0x00000000" caption="Interrupts CPU Select 4">
          <bitfield name="CAN0" caption="CAN0 Interrupt CPU Select" mask="0x1"/>
          <bitfield name="CAN1" caption="CAN1 Interrupt CPU Select" mask="0x4"/>
          <bitfield name="GMAC" caption="GMAC Interrupt CPU Select" mask="0x10"/>
          <bitfield name="TCC2" caption="TCC2 Interrupt CPU Select" mask="0x40"/>
          <bitfield name="TCC3" caption="TCC3 Interrupt CPU Select" mask="0x100"/>
          <bitfield name="TC4" caption="TC4 Interrupt CPU Select" mask="0x400"/>
          <bitfield name="TC5" caption="TC5 Interrupt CPU Select" mask="0x1000"/>
          <bitfield name="PDEC" caption="PDEC Interrupt CPU Select" mask="0x4000"/>
          <bitfield name="AC" caption="AC Interrupt CPU Select" mask="0x10000"/>
          <bitfield name="AES" caption="AES Interrupt CPU Select" mask="0x40000"/>
          <bitfield name="TRNG" caption="TRNG Interrupt CPU Select" mask="0x100000"/>
          <bitfield name="ICM" caption="ICM Interrupt CPU Select" mask="0x400000"/>
          <bitfield name="PUKCC" caption="PUKCC Interrupt CPU Select" mask="0x1000000"/>
          <bitfield name="QSPI" caption="QSPI Interrupt CPU Select" mask="0x4000000"/>
        </register>
        <register name="INTCPUSEL5" offset="0x13C" rw="RW" size="4" initval="0x00000000" caption="Interrupts CPU Select 5">
        </register>
        <register name="INTCPUSEL6" offset="0x140" rw="RW" size="4" initval="0x00000000" caption="Interrupts CPU Select 6">
          <bitfield name="SERCOM4" caption="SERCOM4 Interrupt CPU Select" mask="0x1"/>
          <bitfield name="SERCOM5" caption="SERCOM5 Interrupt CPU Select" mask="0x4"/>
          <bitfield name="SERCOM6" caption="SERCOM6 Interrupt CPU Select" mask="0x10"/>
          <bitfield name="SERCOM7" caption="SERCOM7 Interrupt CPU Select" mask="0x40"/>
          <bitfield name="TCC4" caption="TCC4 Interrupt CPU Select" mask="0x100"/>
          <bitfield name="TC6" caption="TC6 Interrupt CPU Select" mask="0x400"/>
          <bitfield name="TC7" caption="TC7 Interrupt CPU Select" mask="0x1000"/>
          <bitfield name="ADC0" caption="ADC0 Interrupt CPU Select" mask="0x4000"/>
          <bitfield name="ADC1" caption="ADC1 Interrupt CPU Select" mask="0x10000"/>
          <bitfield name="DAC" caption="DAC Interrupt CPU Select" mask="0x40000"/>
          <bitfield name="I2S" caption="I2S Interrupt CPU Select" mask="0x100000"/>
          <bitfield name="PCC" caption="PCC Interrupt CPU Select" mask="0x400000"/>
        </register>
        <register name="INTCPUSEL7" offset="0x144" rw="RW" size="4" initval="0x00000000" caption="Interrupts CPU Select 7">
        </register>
        <register name="INTCPUSEL8" offset="0x148" rw="RW" size="4" initval="0x00000000" caption="Interrupts CPU Select 8">
          <bitfield name="SDHC0" caption="SDHC0 Interrupt CPU Select" mask="0x1"/>
          <bitfield name="SDHC1" caption="SDHC1 Interrupt CPU Select" mask="0x4"/>
        </register>
        <register name="IRQTRIG" offset="0x164" rw="RW" size="4" initval="0x00000000" caption="Interrupt Trigger">
          <bitfield name="ENABLE" caption="Trigger Enable" mask="0x1"/>
          <bitfield name="IRQNUM" caption="Interrupt Request Number" mask="0xFF00"/>
          <bitfield name="OVERRIDE" caption="Interrupt Request Override Value" mask="0xFF0000"/>
        </register>
        <register name="IRQMON" offset="0x168" rw="RW" size="2" count="1" initval="0x0000" caption="Interrupt Monitor Select">
          <bitfield name="EXTEND" caption="Extended Interrupt Request" mask="0x1" values="TAL_IRQMON__EXTEND"/>
          <bitfield name="DROP" caption="Drop Shortened Events" mask="0x2"/>
          <bitfield name="CPUID" caption="ID of CPU currently servicing this IRQ" mask="0x4"/>
          <bitfield name="IRQNUM" caption="Interrupt Request Number" mask="0xFF00"/>
        </register>
        <register-group name="CPUIRQS" name-in-module="CPUIRQS" offset="0x180" count="2"/>
        <register-group name="SMASKS" name-in-module="SMASKS" offset="0x200" count="2"/>
        <register name="SFLAGCLR" offset="0x220" rw="W" size="4" atomic-op="clear:SFLAG" count="2" initval="0x00000000" caption="Inter-Process Signal Flag Clear">
          <bitfield name="IPS0" caption="Inter-Process Signal 0" mask="0x1"/>
          <bitfield name="IPS1" caption="Inter-Process Signal 1" mask="0x2"/>
          <bitfield name="IPS2" caption="Inter-Process Signal 2" mask="0x4"/>
          <bitfield name="IPS3" caption="Inter-Process Signal 3" mask="0x8"/>
          <bitfield name="IPS4" caption="Inter-Process Signal 4" mask="0x10"/>
          <bitfield name="IPS5" caption="Inter-Process Signal 5" mask="0x20"/>
          <bitfield name="IPS6" caption="Inter-Process Signal 6" mask="0x40"/>
          <bitfield name="IPS7" caption="Inter-Process Signal 7" mask="0x80"/>
          <bitfield name="IPS8" caption="Inter-Process Signal 8" mask="0x100"/>
          <bitfield name="IPS9" caption="Inter-Process Signal 9" mask="0x200"/>
          <bitfield name="IPS10" caption="Inter-Process Signal 10" mask="0x400"/>
          <bitfield name="IPS11" caption="Inter-Process Signal 11" mask="0x800"/>
          <bitfield name="IPS12" caption="Inter-Process Signal 12" mask="0x1000"/>
          <bitfield name="IPS13" caption="Inter-Process Signal 13" mask="0x2000"/>
          <bitfield name="IPS14" caption="Inter-Process Signal 14" mask="0x4000"/>
          <bitfield name="IPS15" caption="Inter-Process Signal 15" mask="0x8000"/>
          <bitfield name="IPS16" caption="Inter-Process Signal 16" mask="0x10000"/>
          <bitfield name="IPS17" caption="Inter-Process Signal 17" mask="0x20000"/>
          <bitfield name="IPS18" caption="Inter-Process Signal 18" mask="0x40000"/>
          <bitfield name="IPS19" caption="Inter-Process Signal 19" mask="0x80000"/>
          <bitfield name="IPS20" caption="Inter-Process Signal 20" mask="0x100000"/>
          <bitfield name="IPS21" caption="Inter-Process Signal 21" mask="0x200000"/>
          <bitfield name="IPS22" caption="Inter-Process Signal 22" mask="0x400000"/>
          <bitfield name="IPS23" caption="Inter-Process Signal 23" mask="0x800000"/>
          <bitfield name="IPS24" caption="Inter-Process Signal 24" mask="0x1000000"/>
          <bitfield name="IPS25" caption="Inter-Process Signal 25" mask="0x2000000"/>
          <bitfield name="IPS26" caption="Inter-Process Signal 26" mask="0x4000000"/>
          <bitfield name="IPS27" caption="Inter-Process Signal 27" mask="0x8000000"/>
          <bitfield name="IPS28" caption="Inter-Process Signal 28" mask="0x10000000"/>
          <bitfield name="IPS29" caption="Inter-Process Signal 29" mask="0x20000000"/>
          <bitfield name="IPS30" caption="Inter-Process Signal 30" mask="0x40000000"/>
          <bitfield name="IPS31" caption="Inter-Process Signal 31" mask="0x80000000"/>
        </register>
        <register name="SFLAGSET" offset="0x228" rw="W" size="4" atomic-op="set:SFLAG" count="2" initval="0x00000000" caption="Inter-Process Signal Flag Set">
          <bitfield name="IPS0" caption="Inter-Process Signal 0" mask="0x1"/>
          <bitfield name="IPS1" caption="Inter-Process Signal 1" mask="0x2"/>
          <bitfield name="IPS2" caption="Inter-Process Signal 2" mask="0x4"/>
          <bitfield name="IPS3" caption="Inter-Process Signal 3" mask="0x8"/>
          <bitfield name="IPS4" caption="Inter-Process Signal 4" mask="0x10"/>
          <bitfield name="IPS5" caption="Inter-Process Signal 5" mask="0x20"/>
          <bitfield name="IPS6" caption="Inter-Process Signal 6" mask="0x40"/>
          <bitfield name="IPS7" caption="Inter-Process Signal 7" mask="0x80"/>
          <bitfield name="IPS8" caption="Inter-Process Signal 8" mask="0x100"/>
          <bitfield name="IPS9" caption="Inter-Process Signal 9" mask="0x200"/>
          <bitfield name="IPS10" caption="Inter-Process Signal 10" mask="0x400"/>
          <bitfield name="IPS11" caption="Inter-Process Signal 11" mask="0x800"/>
          <bitfield name="IPS12" caption="Inter-Process Signal 12" mask="0x1000"/>
          <bitfield name="IPS13" caption="Inter-Process Signal 13" mask="0x2000"/>
          <bitfield name="IPS14" caption="Inter-Process Signal 14" mask="0x4000"/>
          <bitfield name="IPS15" caption="Inter-Process Signal 15" mask="0x8000"/>
          <bitfield name="IPS16" caption="Inter-Process Signal 16" mask="0x10000"/>
          <bitfield name="IPS17" caption="Inter-Process Signal 17" mask="0x20000"/>
          <bitfield name="IPS18" caption="Inter-Process Signal 18" mask="0x40000"/>
          <bitfield name="IPS19" caption="Inter-Process Signal 19" mask="0x80000"/>
          <bitfield name="IPS20" caption="Inter-Process Signal 20" mask="0x100000"/>
          <bitfield name="IPS21" caption="Inter-Process Signal 21" mask="0x200000"/>
          <bitfield name="IPS22" caption="Inter-Process Signal 22" mask="0x400000"/>
          <bitfield name="IPS23" caption="Inter-Process Signal 23" mask="0x800000"/>
          <bitfield name="IPS24" caption="Inter-Process Signal 24" mask="0x1000000"/>
          <bitfield name="IPS25" caption="Inter-Process Signal 25" mask="0x2000000"/>
          <bitfield name="IPS26" caption="Inter-Process Signal 26" mask="0x4000000"/>
          <bitfield name="IPS27" caption="Inter-Process Signal 27" mask="0x8000000"/>
          <bitfield name="IPS28" caption="Inter-Process Signal 28" mask="0x10000000"/>
          <bitfield name="IPS29" caption="Inter-Process Signal 29" mask="0x20000000"/>
          <bitfield name="IPS30" caption="Inter-Process Signal 30" mask="0x40000000"/>
          <bitfield name="IPS31" caption="Inter-Process Signal 31" mask="0x80000000"/>
        </register>
        <register name="SFLAG" offset="0x230" rw="R" size="4" count="2" initval="0x00000000" caption="Inter-Process Signal Flag">
          <bitfield name="IPS0" caption="Inter-Process Signal 0" mask="0x1"/>
          <bitfield name="IPS1" caption="Inter-Process Signal 1" mask="0x2"/>
          <bitfield name="IPS2" caption="Inter-Process Signal 2" mask="0x4"/>
          <bitfield name="IPS3" caption="Inter-Process Signal 3" mask="0x8"/>
          <bitfield name="IPS4" caption="Inter-Process Signal 4" mask="0x10"/>
          <bitfield name="IPS5" caption="Inter-Process Signal 5" mask="0x20"/>
          <bitfield name="IPS6" caption="Inter-Process Signal 6" mask="0x40"/>
          <bitfield name="IPS7" caption="Inter-Process Signal 7" mask="0x80"/>
          <bitfield name="IPS8" caption="Inter-Process Signal 8" mask="0x100"/>
          <bitfield name="IPS9" caption="Inter-Process Signal 9" mask="0x200"/>
          <bitfield name="IPS10" caption="Inter-Process Signal 10" mask="0x400"/>
          <bitfield name="IPS11" caption="Inter-Process Signal 11" mask="0x800"/>
          <bitfield name="IPS12" caption="Inter-Process Signal 12" mask="0x1000"/>
          <bitfield name="IPS13" caption="Inter-Process Signal 13" mask="0x2000"/>
          <bitfield name="IPS14" caption="Inter-Process Signal 14" mask="0x4000"/>
          <bitfield name="IPS15" caption="Inter-Process Signal 15" mask="0x8000"/>
          <bitfield name="IPS16" caption="Inter-Process Signal 16" mask="0x10000"/>
          <bitfield name="IPS17" caption="Inter-Process Signal 17" mask="0x20000"/>
          <bitfield name="IPS18" caption="Inter-Process Signal 18" mask="0x40000"/>
          <bitfield name="IPS19" caption="Inter-Process Signal 19" mask="0x80000"/>
          <bitfield name="IPS20" caption="Inter-Process Signal 20" mask="0x100000"/>
          <bitfield name="IPS21" caption="Inter-Process Signal 21" mask="0x200000"/>
          <bitfield name="IPS22" caption="Inter-Process Signal 22" mask="0x400000"/>
          <bitfield name="IPS23" caption="Inter-Process Signal 23" mask="0x800000"/>
          <bitfield name="IPS24" caption="Inter-Process Signal 24" mask="0x1000000"/>
          <bitfield name="IPS25" caption="Inter-Process Signal 25" mask="0x2000000"/>
          <bitfield name="IPS26" caption="Inter-Process Signal 26" mask="0x4000000"/>
          <bitfield name="IPS27" caption="Inter-Process Signal 27" mask="0x8000000"/>
          <bitfield name="IPS28" caption="Inter-Process Signal 28" mask="0x10000000"/>
          <bitfield name="IPS29" caption="Inter-Process Signal 29" mask="0x20000000"/>
          <bitfield name="IPS30" caption="Inter-Process Signal 30" mask="0x40000000"/>
          <bitfield name="IPS31" caption="Inter-Process Signal 31" mask="0x80000000"/>
        </register>
        <register name="SFLAGCLRR" offset="0x300" rw="RW" size="1" count="64" initval="0x00" caption="Inter-Process Signal Flag Bit n">
          <bitfield name="IPS" caption="Inter-Process Signal n" mask="0x1"/>
        </register>
      </register-group>
      <value-group name="TAL_CTICTRLA__BRK">
        <value name="BREAK" caption="Break when requested" value="0"/>
        <value name="INTERRUPT" caption="Trigger DBG interrupt instead of break" value="1"/>
        <value name="IGNORE" caption="Ignore break request" value="2"/>
      </value-group>
      <value-group name="TAL_CTICTRLA__IPS">
        <value name="EVENT" caption="Generate CPU Event when awaited resource is freed." value="0"/>
        <value name="INTERRUPT" caption="Generate Interrupt when awaited resource is freed." value="1"/>
      </value-group>
      <value-group name="TAL_CTICTRLA__RESTART">
        <value name="RESTART" caption="Restart when requested" value="0"/>
        <value name="IGNORE" caption="Ignore restart request" value="1"/>
      </value-group>
      <value-group name="TAL_IRQMON__EXTEND">
        <value name="NO" caption="Event is Interrupt Request signal" value="0"/>
        <value name="YES" caption="Event is Interrupt Request signal extended until end of Interrupt Handler" value="1"/>
      </value-group>
    </module>
    <module name="TC" id="U2249" version="3.0.0" caption="Basic Timer Counter">
      <register-group class="union" union-tag="TC.CTRLA.MODE" name="TC" caption="Basic Timer Counter">
        <register-group name="COUNT8" name-in-module="TC_COUNT8" union-tag-value="1" offset="0"/>
        <register-group name="COUNT16" name-in-module="TC_COUNT16" union-tag-value="0" offset="0"/>
        <register-group name="COUNT32" name-in-module="TC_COUNT32" union-tag-value="2" offset="0"/>
      </register-group>
      <register-group name="TC_COUNT8" caption="Basic Timer Counter - 8-bit Counter Mode">
        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="MODE" caption="Timer Counter Mode" mask="0xC" values="TC_CTRLA__MODE"/>
          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x30" values="TC_CTRLA__PRESCSYNC"/>
          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x40"/>
          <bitfield name="ONDEMAND" caption="Clock On Demand" mask="0x80"/>
          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
          <bitfield name="ALOCK" caption="Auto Lock" mask="0x800"/>
          <bitfield name="CAPTEN0" caption="Capture Channel 0 Enable" mask="0x10000"/>
          <bitfield name="CAPTEN1" caption="Capture Channel 1 Enable" mask="0x20000"/>
          <bitfield name="COPEN0" caption="Capture On Pin 0 Enable" mask="0x100000"/>
          <bitfield name="COPEN1" caption="Capture On Pin 1 Enable" mask="0x200000"/>
          <bitfield name="CAPTMODE0" caption="Capture Mode Channel 0" mask="0x3000000" values="TC_CTRLA__CAPTMODE0"/>
          <bitfield name="CAPTMODE1" caption="Capture mode Channel 1" mask="0x18000000" values="TC_CTRLA__CAPTMODE1"/>
        </register>
        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
          <bitfield name="ONESHOT" caption="One-Shot on Counter" mask="0x4"/>
          <bitfield name="CMD" caption="Command" mask="0xE0" values="TC_CTRLBCLR__CMD"/>
        </register>
        <register name="CTRLBSET" offset="0x5" rw="RW" access="RWSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
          <bitfield name="ONESHOT" caption="One-Shot on Counter" mask="0x4"/>
          <bitfield name="CMD" caption="Command" mask="0xE0" values="TC_CTRLBSET__CMD"/>
        </register>
        <register name="EVCTRL" offset="0x6" rw="RW" size="2" initval="0x0000" caption="Event Control">
          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
          <bitfield name="TCINV" caption="TC Event Input Polarity" mask="0x10"/>
          <bitfield name="TCEI" caption="TC Event Enable" mask="0x20"/>
          <bitfield name="OVFEO" caption="Event Output Enable" mask="0x100"/>
          <bitfield name="MCEO0" caption="MC Event Output Enable 0" mask="0x1000"/>
          <bitfield name="MCEO1" caption="MC Event Output Enable 1" mask="0x2000"/>
        </register>
        <register name="INTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
          <bitfield name="OVF" caption="OVF Interrupt Disable" mask="0x1"/>
          <bitfield name="ERR" caption="ERR Interrupt Disable" mask="0x2"/>
          <bitfield name="MC0" caption="MC Interrupt Disable 0" mask="0x10"/>
          <bitfield name="MC1" caption="MC Interrupt Disable 1" mask="0x20"/>
        </register>
        <register name="INTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
          <bitfield name="OVF" caption="OVF Interrupt Enable" mask="0x1"/>
          <bitfield name="ERR" caption="ERR Interrupt Enable" mask="0x2"/>
          <bitfield name="MC0" caption="MC Interrupt Enable 0" mask="0x10"/>
          <bitfield name="MC1" caption="MC Interrupt Enable 1" mask="0x20"/>
        </register>
        <register name="INTFLAG" offset="0xA" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
          <bitfield name="OVF" caption="OVF Interrupt Flag" mask="0x1"/>
          <bitfield name="ERR" caption="ERR Interrupt Flag" mask="0x2"/>
          <bitfield name="MC0" caption="MC Interrupt Flag 0" mask="0x10"/>
          <bitfield name="MC1" caption="MC Interrupt Flag 1" mask="0x20"/>
        </register>
        <register name="STATUS" offset="0xB" rw="RW" access="RSYNC" size="1" initval="0x01" caption="Status">
          <bitfield name="STOP" caption="Stop Status Flag" mask="0x1"/>
          <bitfield name="SLAVE" caption="Slave Status Flag" mask="0x2"/>
          <bitfield name="PERBUFV" caption="Synchronization Busy Status" mask="0x8"/>
          <bitfield name="CCBUFV0" caption="Compare channel buffer 0 valid" mask="0x10"/>
          <bitfield name="CCBUFV1" caption="Compare channel buffer 1 valid" mask="0x20"/>
        </register>
        <register name="WAVE" offset="0xC" rw="RW" size="1" initval="0x00" caption="Waveform Generation Control">
          <bitfield name="WAVEGEN" caption="Waveform Generation Mode" mask="0x3" values="TC_WAVE__WAVEGEN"/>
        </register>
        <register name="DRVCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Control C">
          <bitfield name="INVEN0" caption="Output Waveform Invert Enable 0" mask="0x1"/>
          <bitfield name="INVEN1" caption="Output Waveform Invert Enable 1" mask="0x2"/>
        </register>
        <register name="DBGCTRL" offset="0xF" rw="RW" size="1" initval="0x00" caption="Debug Control">
          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
        </register>
        <register name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Synchronization Status">
          <bitfield name="SWRST" caption="swrst" mask="0x1"/>
          <bitfield name="ENABLE" caption="enable" mask="0x2"/>
          <bitfield name="CTRLB" caption="CTRLB" mask="0x4"/>
          <bitfield name="STATUS" caption="STATUS" mask="0x8"/>
          <bitfield name="COUNT" caption="Counter" mask="0x10"/>
          <bitfield name="PER" caption="Period" mask="0x20"/>
          <bitfield name="CC0" caption="Compare Channel 0" mask="0x40"/>
          <bitfield name="CC1" caption="Compare Channel 1" mask="0x80"/>
        </register>
        <register name="COUNT" offset="0x14" rw="RW" access="RWSYNC" size="1" initval="0x00" caption="COUNT8 Count">
          <bitfield name="COUNT" caption="Counter Value" mask="0xFF"/>
        </register>
        <register name="PER" offset="0x1B" rw="RW" access="WSYNC" size="1" initval="0xFF" caption="COUNT8 Period">
          <bitfield name="PER" caption="Period Value" mask="0xFF"/>
        </register>
        <register name="CC" offset="0x1C" rw="RW" access="RWSYNC" size="1" count="2" initval="0x00" caption="COUNT8 Compare and Capture">
          <bitfield name="CC" caption="Counter/Compare Value" mask="0xFF"/>
        </register>
        <register name="PERBUF" offset="0x2F" rw="RW" access="WSYNC" size="1" initval="0xFF" caption="COUNT8 Period Buffer">
          <bitfield name="PERBUF" caption="Period Buffer Value" mask="0xFF"/>
        </register>
        <register name="CCBUF" offset="0x30" rw="RW" access="WSYNC" size="1" count="2" initval="0x00" caption="COUNT8 Compare and Capture Buffer">
          <bitfield name="CCBUF" caption="Counter/Compare Buffer Value" mask="0xFF"/>
        </register>
      </register-group>
      <register-group name="TC_COUNT16" caption="Basic Timer Counter - 16-bit Counter Mode">
        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="MODE" caption="Timer Counter Mode" mask="0xC" values="TC_CTRLA__MODE"/>
          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x30" values="TC_CTRLA__PRESCSYNC"/>
          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x40"/>
          <bitfield name="ONDEMAND" caption="Clock On Demand" mask="0x80"/>
          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
          <bitfield name="ALOCK" caption="Auto Lock" mask="0x800"/>
          <bitfield name="CAPTEN0" caption="Capture Channel 0 Enable" mask="0x10000"/>
          <bitfield name="CAPTEN1" caption="Capture Channel 1 Enable" mask="0x20000"/>
          <bitfield name="COPEN0" caption="Capture On Pin 0 Enable" mask="0x100000"/>
          <bitfield name="COPEN1" caption="Capture On Pin 1 Enable" mask="0x200000"/>
          <bitfield name="CAPTMODE0" caption="Capture Mode Channel 0" mask="0x3000000" values="TC_CTRLA__CAPTMODE0"/>
          <bitfield name="CAPTMODE1" caption="Capture mode Channel 1" mask="0x18000000" values="TC_CTRLA__CAPTMODE1"/>
        </register>
        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
          <bitfield name="ONESHOT" caption="One-Shot on Counter" mask="0x4"/>
          <bitfield name="CMD" caption="Command" mask="0xE0" values="TC_CTRLBCLR__CMD"/>
        </register>
        <register name="CTRLBSET" offset="0x5" rw="RW" access="RWSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
          <bitfield name="ONESHOT" caption="One-Shot on Counter" mask="0x4"/>
          <bitfield name="CMD" caption="Command" mask="0xE0" values="TC_CTRLBSET__CMD"/>
        </register>
        <register name="EVCTRL" offset="0x6" rw="RW" size="2" initval="0x0000" caption="Event Control">
          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
          <bitfield name="TCINV" caption="TC Event Input Polarity" mask="0x10"/>
          <bitfield name="TCEI" caption="TC Event Enable" mask="0x20"/>
          <bitfield name="OVFEO" caption="Event Output Enable" mask="0x100"/>
          <bitfield name="MCEO0" caption="MC Event Output Enable 0" mask="0x1000"/>
          <bitfield name="MCEO1" caption="MC Event Output Enable 1" mask="0x2000"/>
        </register>
        <register name="INTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
          <bitfield name="OVF" caption="OVF Interrupt Disable" mask="0x1"/>
          <bitfield name="ERR" caption="ERR Interrupt Disable" mask="0x2"/>
          <bitfield name="MC0" caption="MC Interrupt Disable 0" mask="0x10"/>
          <bitfield name="MC1" caption="MC Interrupt Disable 1" mask="0x20"/>
        </register>
        <register name="INTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
          <bitfield name="OVF" caption="OVF Interrupt Enable" mask="0x1"/>
          <bitfield name="ERR" caption="ERR Interrupt Enable" mask="0x2"/>
          <bitfield name="MC0" caption="MC Interrupt Enable 0" mask="0x10"/>
          <bitfield name="MC1" caption="MC Interrupt Enable 1" mask="0x20"/>
        </register>
        <register name="INTFLAG" offset="0xA" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
          <bitfield name="OVF" caption="OVF Interrupt Flag" mask="0x1"/>
          <bitfield name="ERR" caption="ERR Interrupt Flag" mask="0x2"/>
          <bitfield name="MC0" caption="MC Interrupt Flag 0" mask="0x10"/>
          <bitfield name="MC1" caption="MC Interrupt Flag 1" mask="0x20"/>
        </register>
        <register name="STATUS" offset="0xB" rw="RW" access="RSYNC" size="1" initval="0x01" caption="Status">
          <bitfield name="STOP" caption="Stop Status Flag" mask="0x1"/>
          <bitfield name="SLAVE" caption="Slave Status Flag" mask="0x2"/>
          <bitfield name="PERBUFV" caption="Synchronization Busy Status" mask="0x8"/>
          <bitfield name="CCBUFV0" caption="Compare channel buffer 0 valid" mask="0x10"/>
          <bitfield name="CCBUFV1" caption="Compare channel buffer 1 valid" mask="0x20"/>
        </register>
        <register name="WAVE" offset="0xC" rw="RW" size="1" initval="0x00" caption="Waveform Generation Control">
          <bitfield name="WAVEGEN" caption="Waveform Generation Mode" mask="0x3" values="TC_WAVE__WAVEGEN"/>
        </register>
        <register name="DRVCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Control C">
          <bitfield name="INVEN0" caption="Output Waveform Invert Enable 0" mask="0x1"/>
          <bitfield name="INVEN1" caption="Output Waveform Invert Enable 1" mask="0x2"/>
        </register>
        <register name="DBGCTRL" offset="0xF" rw="RW" size="1" initval="0x00" caption="Debug Control">
          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
        </register>
        <register name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Synchronization Status">
          <bitfield name="SWRST" caption="swrst" mask="0x1"/>
          <bitfield name="ENABLE" caption="enable" mask="0x2"/>
          <bitfield name="CTRLB" caption="CTRLB" mask="0x4"/>
          <bitfield name="STATUS" caption="STATUS" mask="0x8"/>
          <bitfield name="COUNT" caption="Counter" mask="0x10"/>
          <bitfield name="PER" caption="Period" mask="0x20"/>
          <bitfield name="CC0" caption="Compare Channel 0" mask="0x40"/>
          <bitfield name="CC1" caption="Compare Channel 1" mask="0x80"/>
        </register>
        <register name="COUNT" offset="0x14" rw="RW" access="RWSYNC" size="2" initval="0x0000" caption="COUNT16 Count">
          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFF"/>
        </register>
        <register name="CC" offset="0x1C" rw="RW" access="RWSYNC" size="2" count="2" initval="0x0000" caption="COUNT16 Compare and Capture">
          <bitfield name="CC" caption="Counter/Compare Value" mask="0xFFFF"/>
        </register>
        <register name="CCBUF" offset="0x30" rw="RW" access="WSYNC" size="2" count="2" initval="0x0000" caption="COUNT16 Compare and Capture Buffer">
          <bitfield name="CCBUF" caption="Counter/Compare Buffer Value" mask="0xFFFF"/>
        </register>
      </register-group>
      <register-group name="TC_COUNT32" caption="Basic Timer Counter - 32-bit Counter Mode">
        <register name="CTRLA" offset="0x0" rw="RW" size="4" initval="0x00000000" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="MODE" caption="Timer Counter Mode" mask="0xC" values="TC_CTRLA__MODE"/>
          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization" mask="0x30" values="TC_CTRLA__PRESCSYNC"/>
          <bitfield name="RUNSTDBY" caption="Run during Standby" mask="0x40"/>
          <bitfield name="ONDEMAND" caption="Clock On Demand" mask="0x80"/>
          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TC_CTRLA__PRESCALER"/>
          <bitfield name="ALOCK" caption="Auto Lock" mask="0x800"/>
          <bitfield name="CAPTEN0" caption="Capture Channel 0 Enable" mask="0x10000"/>
          <bitfield name="CAPTEN1" caption="Capture Channel 1 Enable" mask="0x20000"/>
          <bitfield name="COPEN0" caption="Capture On Pin 0 Enable" mask="0x100000"/>
          <bitfield name="COPEN1" caption="Capture On Pin 1 Enable" mask="0x200000"/>
          <bitfield name="CAPTMODE0" caption="Capture Mode Channel 0" mask="0x3000000" values="TC_CTRLA__CAPTMODE0"/>
          <bitfield name="CAPTMODE1" caption="Capture mode Channel 1" mask="0x18000000" values="TC_CTRLA__CAPTMODE1"/>
        </register>
        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
          <bitfield name="ONESHOT" caption="One-Shot on Counter" mask="0x4"/>
          <bitfield name="CMD" caption="Command" mask="0xE0" values="TC_CTRLBCLR__CMD"/>
        </register>
        <register name="CTRLBSET" offset="0x5" rw="RW" access="RWSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
          <bitfield name="ONESHOT" caption="One-Shot on Counter" mask="0x4"/>
          <bitfield name="CMD" caption="Command" mask="0xE0" values="TC_CTRLBSET__CMD"/>
        </register>
        <register name="EVCTRL" offset="0x6" rw="RW" size="2" initval="0x0000" caption="Event Control">
          <bitfield name="EVACT" caption="Event Action" mask="0x7" values="TC_EVCTRL__EVACT"/>
          <bitfield name="TCINV" caption="TC Event Input Polarity" mask="0x10"/>
          <bitfield name="TCEI" caption="TC Event Enable" mask="0x20"/>
          <bitfield name="OVFEO" caption="Event Output Enable" mask="0x100"/>
          <bitfield name="MCEO0" caption="MC Event Output Enable 0" mask="0x1000"/>
          <bitfield name="MCEO1" caption="MC Event Output Enable 1" mask="0x2000"/>
        </register>
        <register name="INTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
          <bitfield name="OVF" caption="OVF Interrupt Disable" mask="0x1"/>
          <bitfield name="ERR" caption="ERR Interrupt Disable" mask="0x2"/>
          <bitfield name="MC0" caption="MC Interrupt Disable 0" mask="0x10"/>
          <bitfield name="MC1" caption="MC Interrupt Disable 1" mask="0x20"/>
        </register>
        <register name="INTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
          <bitfield name="OVF" caption="OVF Interrupt Enable" mask="0x1"/>
          <bitfield name="ERR" caption="ERR Interrupt Enable" mask="0x2"/>
          <bitfield name="MC0" caption="MC Interrupt Enable 0" mask="0x10"/>
          <bitfield name="MC1" caption="MC Interrupt Enable 1" mask="0x20"/>
        </register>
        <register name="INTFLAG" offset="0xA" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
          <bitfield name="OVF" caption="OVF Interrupt Flag" mask="0x1"/>
          <bitfield name="ERR" caption="ERR Interrupt Flag" mask="0x2"/>
          <bitfield name="MC0" caption="MC Interrupt Flag 0" mask="0x10"/>
          <bitfield name="MC1" caption="MC Interrupt Flag 1" mask="0x20"/>
        </register>
        <register name="STATUS" offset="0xB" rw="RW" access="RSYNC" size="1" initval="0x01" caption="Status">
          <bitfield name="STOP" caption="Stop Status Flag" mask="0x1"/>
          <bitfield name="SLAVE" caption="Slave Status Flag" mask="0x2"/>
          <bitfield name="PERBUFV" caption="Synchronization Busy Status" mask="0x8"/>
          <bitfield name="CCBUFV0" caption="Compare channel buffer 0 valid" mask="0x10"/>
          <bitfield name="CCBUFV1" caption="Compare channel buffer 1 valid" mask="0x20"/>
        </register>
        <register name="WAVE" offset="0xC" rw="RW" size="1" initval="0x00" caption="Waveform Generation Control">
          <bitfield name="WAVEGEN" caption="Waveform Generation Mode" mask="0x3" values="TC_WAVE__WAVEGEN"/>
        </register>
        <register name="DRVCTRL" offset="0xD" rw="RW" size="1" initval="0x00" caption="Control C">
          <bitfield name="INVEN0" caption="Output Waveform Invert Enable 0" mask="0x1"/>
          <bitfield name="INVEN1" caption="Output Waveform Invert Enable 1" mask="0x2"/>
        </register>
        <register name="DBGCTRL" offset="0xF" rw="RW" size="1" initval="0x00" caption="Debug Control">
          <bitfield name="DBGRUN" caption="Run During Debug" mask="0x1"/>
        </register>
        <register name="SYNCBUSY" offset="0x10" rw="R" size="4" initval="0x00000000" caption="Synchronization Status">
          <bitfield name="SWRST" caption="swrst" mask="0x1"/>
          <bitfield name="ENABLE" caption="enable" mask="0x2"/>
          <bitfield name="CTRLB" caption="CTRLB" mask="0x4"/>
          <bitfield name="STATUS" caption="STATUS" mask="0x8"/>
          <bitfield name="COUNT" caption="Counter" mask="0x10"/>
          <bitfield name="PER" caption="Period" mask="0x20"/>
          <bitfield name="CC0" caption="Compare Channel 0" mask="0x40"/>
          <bitfield name="CC1" caption="Compare Channel 1" mask="0x80"/>
        </register>
        <register name="COUNT" offset="0x14" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="COUNT32 Count">
          <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFFFF"/>
        </register>
        <register name="CC" offset="0x1C" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare and Capture">
          <bitfield name="CC" caption="Counter/Compare Value" mask="0xFFFFFFFF"/>
        </register>
        <register name="CCBUF" offset="0x30" rw="RW" access="WSYNC" size="4" count="2" initval="0x00000000" caption="COUNT32 Compare and Capture Buffer">
          <bitfield name="CCBUF" caption="Counter/Compare Buffer Value" mask="0xFFFFFFFF"/>
        </register>
      </register-group>
      <value-group name="TC_CTRLA__CAPTMODE0">
        <value name="DEFAULT" caption="Default capture" value="0"/>
        <value name="CAPTMIN" caption="Minimum capture" value="1"/>
        <value name="CAPTMAX" caption="Maximum capture" value="2"/>
      </value-group>
      <value-group name="TC_CTRLA__CAPTMODE1">
        <value name="DEFAULT" caption="Default capture" value="0"/>
        <value name="CAPTMIN" caption="Minimum capture" value="1"/>
        <value name="CAPTMAX" caption="Maximum capture" value="2"/>
      </value-group>
      <value-group name="TC_CTRLA__MODE">
        <value name="COUNT16" caption="Counter in 16-bit mode" value="0"/>
        <value name="COUNT8" caption="Counter in 8-bit mode" value="1"/>
        <value name="COUNT32" caption="Counter in 32-bit mode" value="2"/>
      </value-group>
      <value-group name="TC_CTRLA__PRESCALER">
        <value name="DIV1" caption="Prescaler: GCLK_TC" value="0"/>
        <value name="DIV2" caption="Prescaler: GCLK_TC/2" value="1"/>
        <value name="DIV4" caption="Prescaler: GCLK_TC/4" value="2"/>
        <value name="DIV8" caption="Prescaler: GCLK_TC/8" value="3"/>
        <value name="DIV16" caption="Prescaler: GCLK_TC/16" value="4"/>
        <value name="DIV64" caption="Prescaler: GCLK_TC/64" value="5"/>
        <value name="DIV256" caption="Prescaler: GCLK_TC/256" value="6"/>
        <value name="DIV1024" caption="Prescaler: GCLK_TC/1024" value="7"/>
      </value-group>
      <value-group name="TC_CTRLA__PRESCSYNC">
        <value name="GCLK" caption="Reload or reset the counter on next generic clock" value="0"/>
        <value name="PRESC" caption="Reload or reset the counter on next prescaler clock" value="1"/>
        <value name="RESYNC" caption="Reload or reset the counter on next generic clock and reset the prescaler counter" value="2"/>
      </value-group>
      <value-group name="TC_CTRLBCLR__CMD">
        <value name="NONE" caption="No action" value="0"/>
        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
        <value name="STOP" caption="Force a stop" value="2"/>
        <value name="UPDATE" caption="Force update of double-buffered register" value="3"/>
        <value name="READSYNC" caption="Force a read synchronization of COUNT" value="4"/>
        <value name="DMAOS" caption="One-shot DMA trigger" value="5"/>
      </value-group>
      <value-group name="TC_CTRLBSET__CMD">
        <value name="NONE" caption="No action" value="0"/>
        <value name="RETRIGGER" caption="Force a start, restart or retrigger" value="1"/>
        <value name="STOP" caption="Force a stop" value="2"/>
        <value name="UPDATE" caption="Force update of double-buffered register" value="3"/>
        <value name="READSYNC" caption="Force a read synchronization of COUNT" value="4"/>
        <value name="DMAOS" caption="One-shot DMA trigger" value="5"/>
      </value-group>
      <value-group name="TC_EVCTRL__EVACT">
        <value name="OFF" caption="Event action disabled" value="0"/>
        <value name="RETRIGGER" caption="Start, restart or retrigger TC on event" value="1"/>
        <value name="COUNT" caption="Count on event" value="2"/>
        <value name="START" caption="Start TC on event" value="3"/>
        <value name="STAMP" caption="Time stamp capture" value="4"/>
        <value name="PPW" caption="Period catured in CC0, pulse width in CC1" value="5"/>
        <value name="PWP" caption="Period catured in CC1, pulse width in CC0" value="6"/>
        <value name="PW" caption="Pulse width capture" value="7"/>
      </value-group>
      <value-group name="TC_WAVE__WAVEGEN">
        <value name="NFRQ" caption="Normal frequency" value="0"/>
        <value name="MFRQ" caption="Match frequency" value="1"/>
        <value name="NPWM" caption="Normal PWM" value="2"/>
        <value name="MPWM" caption="Match PWM" value="3"/>
      </value-group>
    </module>
    <module name="TCC" id="U2213" version="3.1.0" caption="Timer Counter Control">
      <register-group name="TCC" caption="Timer Counter Control">
        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="RESOLUTION" caption="Enhanced Resolution" mask="0x60" values="TCC_CTRLA__RESOLUTION"/>
          <bitfield name="PRESCALER" caption="Prescaler" mask="0x700" values="TCC_CTRLA__PRESCALER"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x800"/>
          <bitfield name="PRESCSYNC" caption="Prescaler and Counter Synchronization Selection" mask="0x3000" values="TCC_CTRLA__PRESCSYNC"/>
          <bitfield name="ALOCK" caption="Auto Lock" mask="0x4000"/>
          <bitfield name="MSYNC" caption="Master Synchronization (only for TCC Slave Instance)" mask="0x8000"/>
          <bitfield name="DMAOS" caption="DMA One-shot Trigger Mode" mask="0x800000"/>
          <bitfield name="CPTEN0" caption="Capture Channel 0 Enable" mask="0x1000000"/>
          <bitfield name="CPTEN1" caption="Capture Channel 1 Enable" mask="0x2000000"/>
          <bitfield name="CPTEN2" caption="Capture Channel 2 Enable" mask="0x4000000"/>
          <bitfield name="CPTEN3" caption="Capture Channel 3 Enable" mask="0x8000000"/>
          <bitfield name="CPTEN4" caption="Capture Channel 4 Enable" mask="0x10000000"/>
          <bitfield name="CPTEN5" caption="Capture Channel 5 Enable" mask="0x20000000"/>
        </register>
        <register name="CTRLBCLR" offset="0x4" rw="RW" access="RWSYNC" size="1" atomic-op="clear:CTRLBCLR" initval="0x00" caption="Control B Clear">
          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBCLR__IDXCMD"/>
          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBCLR__CMD"/>
        </register>
        <register name="CTRLBSET" offset="0x5" rw="RW" access="RWSYNC" size="1" atomic-op="set:CTRLBSET" initval="0x00" caption="Control B Set">
          <bitfield name="DIR" caption="Counter Direction" mask="0x1"/>
          <bitfield name="LUPD" caption="Lock Update" mask="0x2"/>
          <bitfield name="ONESHOT" caption="One-Shot" mask="0x4"/>
          <bitfield name="IDXCMD" caption="Ramp Index Command" mask="0x18" values="TCC_CTRLBSET__IDXCMD"/>
          <bitfield name="CMD" caption="TCC Command" mask="0xE0" values="TCC_CTRLBSET__CMD"/>
        </register>
        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
          <bitfield name="SWRST" caption="Swrst Busy" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable Busy" mask="0x2"/>
          <bitfield name="CTRLB" caption="Ctrlb Busy" mask="0x4"/>
          <bitfield name="STATUS" caption="Status Busy" mask="0x8"/>
          <bitfield name="COUNT" caption="Count Busy" mask="0x10"/>
          <bitfield name="PATT" caption="Pattern Busy" mask="0x20"/>
          <bitfield name="WAVE" caption="Wave Busy" mask="0x40"/>
          <bitfield name="PER" caption="Period Busy" mask="0x80"/>
          <bitfield name="CC0" caption="Compare Channel 0 Busy" mask="0x100"/>
          <bitfield name="CC1" caption="Compare Channel 1 Busy" mask="0x200"/>
          <bitfield name="CC2" caption="Compare Channel 2 Busy" mask="0x400"/>
          <bitfield name="CC3" caption="Compare Channel 3 Busy" mask="0x800"/>
          <bitfield name="CC4" caption="Compare Channel 4 Busy" mask="0x1000"/>
          <bitfield name="CC5" caption="Compare Channel 5 Busy" mask="0x2000"/>
        </register>
        <register name="FCTRLA" offset="0xC" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault A Configuration">
          <bitfield name="SRC" caption="Fault A Source" mask="0x3" values="TCC_FCTRLA__SRC"/>
          <bitfield name="KEEP" caption="Fault A Keeper" mask="0x8"/>
          <bitfield name="QUAL" caption="Fault A Qualification" mask="0x10"/>
          <bitfield name="BLANK" caption="Fault A Blanking Mode" mask="0x60" values="TCC_FCTRLA__BLANK"/>
          <bitfield name="RESTART" caption="Fault A Restart" mask="0x80"/>
          <bitfield name="HALT" caption="Fault A Halt Mode" mask="0x300" values="TCC_FCTRLA__HALT"/>
          <bitfield name="CHSEL" caption="Fault A Capture Channel" mask="0xC00" values="TCC_FCTRLA__CHSEL"/>
          <bitfield name="CAPTURE" caption="Fault A Capture Action" mask="0x7000" values="TCC_FCTRLA__CAPTURE"/>
          <bitfield name="BLANKPRESC" caption="Fault A Blanking Prescaler" mask="0x8000"/>
          <bitfield name="BLANKVAL" caption="Fault A Blanking Time" mask="0xFF0000"/>
          <bitfield name="FILTERVAL" caption="Fault A Filter Value" mask="0xF000000"/>
        </register>
        <register name="FCTRLB" offset="0x10" rw="RW" size="4" initval="0x00000000" caption="Recoverable Fault B Configuration">
          <bitfield name="SRC" caption="Fault B Source" mask="0x3" values="TCC_FCTRLB__SRC"/>
          <bitfield name="KEEP" caption="Fault B Keeper" mask="0x8"/>
          <bitfield name="QUAL" caption="Fault B Qualification" mask="0x10"/>
          <bitfield name="BLANK" caption="Fault B Blanking Mode" mask="0x60" values="TCC_FCTRLB__BLANK"/>
          <bitfield name="RESTART" caption="Fault B Restart" mask="0x80"/>
          <bitfield name="HALT" caption="Fault B Halt Mode" mask="0x300" values="TCC_FCTRLB__HALT"/>
          <bitfield name="CHSEL" caption="Fault B Capture Channel" mask="0xC00" values="TCC_FCTRLB__CHSEL"/>
          <bitfield name="CAPTURE" caption="Fault B Capture Action" mask="0x7000" values="TCC_FCTRLB__CAPTURE"/>
          <bitfield name="BLANKPRESC" caption="Fault B Blanking Prescaler" mask="0x8000"/>
          <bitfield name="BLANKVAL" caption="Fault B Blanking Time" mask="0xFF0000"/>
          <bitfield name="FILTERVAL" caption="Fault B Filter Value" mask="0xF000000"/>
        </register>
        <register name="WEXCTRL" offset="0x14" rw="RW" size="4" initval="0x00000000" caption="Waveform Extension Configuration">
          <bitfield name="OTMX" caption="Output Matrix" mask="0x3"/>
          <bitfield name="DTIEN0" caption="Dead-time Insertion Generator 0 Enable" mask="0x100"/>
          <bitfield name="DTIEN1" caption="Dead-time Insertion Generator 1 Enable" mask="0x200"/>
          <bitfield name="DTIEN2" caption="Dead-time Insertion Generator 2 Enable" mask="0x400"/>
          <bitfield name="DTIEN3" caption="Dead-time Insertion Generator 3 Enable" mask="0x800"/>
          <bitfield name="DTLS" caption="Dead-time Low Side Outputs Value" mask="0xFF0000"/>
          <bitfield name="DTHS" caption="Dead-time High Side Outputs Value" mask="0xFF000000"/>
        </register>
        <register name="DRVCTRL" offset="0x18" rw="RW" size="4" initval="0x00000000" caption="Driver Control">
          <bitfield name="NRE0" caption="Non-Recoverable State 0 Output Enable" mask="0x1"/>
          <bitfield name="NRE1" caption="Non-Recoverable State 1 Output Enable" mask="0x2"/>
          <bitfield name="NRE2" caption="Non-Recoverable State 2 Output Enable" mask="0x4"/>
          <bitfield name="NRE3" caption="Non-Recoverable State 3 Output Enable" mask="0x8"/>
          <bitfield name="NRE4" caption="Non-Recoverable State 4 Output Enable" mask="0x10"/>
          <bitfield name="NRE5" caption="Non-Recoverable State 5 Output Enable" mask="0x20"/>
          <bitfield name="NRE6" caption="Non-Recoverable State 6 Output Enable" mask="0x40"/>
          <bitfield name="NRE7" caption="Non-Recoverable State 7 Output Enable" mask="0x80"/>
          <bitfield name="NRV0" caption="Non-Recoverable State 0 Output Value" mask="0x100"/>
          <bitfield name="NRV1" caption="Non-Recoverable State 1 Output Value" mask="0x200"/>
          <bitfield name="NRV2" caption="Non-Recoverable State 2 Output Value" mask="0x400"/>
          <bitfield name="NRV3" caption="Non-Recoverable State 3 Output Value" mask="0x800"/>
          <bitfield name="NRV4" caption="Non-Recoverable State 4 Output Value" mask="0x1000"/>
          <bitfield name="NRV5" caption="Non-Recoverable State 5 Output Value" mask="0x2000"/>
          <bitfield name="NRV6" caption="Non-Recoverable State 6 Output Value" mask="0x4000"/>
          <bitfield name="NRV7" caption="Non-Recoverable State 7 Output Value" mask="0x8000"/>
          <bitfield name="INVEN0" caption="Output Waveform 0 Inversion" mask="0x10000"/>
          <bitfield name="INVEN1" caption="Output Waveform 1 Inversion" mask="0x20000"/>
          <bitfield name="INVEN2" caption="Output Waveform 2 Inversion" mask="0x40000"/>
          <bitfield name="INVEN3" caption="Output Waveform 3 Inversion" mask="0x80000"/>
          <bitfield name="INVEN4" caption="Output Waveform 4 Inversion" mask="0x100000"/>
          <bitfield name="INVEN5" caption="Output Waveform 5 Inversion" mask="0x200000"/>
          <bitfield name="INVEN6" caption="Output Waveform 6 Inversion" mask="0x400000"/>
          <bitfield name="INVEN7" caption="Output Waveform 7 Inversion" mask="0x800000"/>
          <bitfield name="FILTERVAL0" caption="Non-Recoverable Fault Input 0 Filter Value" mask="0xF000000"/>
          <bitfield name="FILTERVAL1" caption="Non-Recoverable Fault Input 1 Filter Value" mask="0xF0000000"/>
        </register>
        <register name="DBGCTRL" offset="0x1E" rw="RW" size="1" initval="0x00" caption="Debug Control">
          <bitfield name="DBGRUN" caption="Debug Running Mode" mask="0x1"/>
          <bitfield name="FDDBD" caption="Fault Detection on Debug Break Detection" mask="0x4"/>
        </register>
        <register name="EVCTRL" offset="0x20" rw="RW" size="4" initval="0x00000000" caption="Event Control">
          <bitfield name="EVACT0" caption="Timer/counter Input Event0 Action" mask="0x7" values="TCC_EVCTRL__EVACT0"/>
          <bitfield name="EVACT1" caption="Timer/counter Input Event1 Action" mask="0x38" values="TCC_EVCTRL__EVACT1"/>
          <bitfield name="CNTSEL" caption="Timer/counter Output Event Mode" mask="0xC0" values="TCC_EVCTRL__CNTSEL"/>
          <bitfield name="OVFEO" caption="Overflow/Underflow Output Event Enable" mask="0x100"/>
          <bitfield name="TRGEO" caption="Retrigger Output Event Enable" mask="0x200"/>
          <bitfield name="CNTEO" caption="Timer/counter Output Event Enable" mask="0x400"/>
          <bitfield name="TCINV0" caption="Inverted Event 0 Input Enable" mask="0x1000"/>
          <bitfield name="TCINV1" caption="Inverted Event 1 Input Enable" mask="0x2000"/>
          <bitfield name="TCEI0" caption="Timer/counter Event 0 Input Enable" mask="0x4000"/>
          <bitfield name="TCEI1" caption="Timer/counter Event 1 Input Enable" mask="0x8000"/>
          <bitfield name="MCEI0" caption="Match or Capture Channel 0 Event Input Enable" mask="0x10000"/>
          <bitfield name="MCEI1" caption="Match or Capture Channel 1 Event Input Enable" mask="0x20000"/>
          <bitfield name="MCEI2" caption="Match or Capture Channel 2 Event Input Enable" mask="0x40000"/>
          <bitfield name="MCEI3" caption="Match or Capture Channel 3 Event Input Enable" mask="0x80000"/>
          <bitfield name="MCEI4" caption="Match or Capture Channel 4 Event Input Enable" mask="0x100000"/>
          <bitfield name="MCEI5" caption="Match or Capture Channel 5 Event Input Enable" mask="0x200000"/>
          <bitfield name="MCEO0" caption="Match or Capture Channel 0 Event Output Enable" mask="0x1000000"/>
          <bitfield name="MCEO1" caption="Match or Capture Channel 1 Event Output Enable" mask="0x2000000"/>
          <bitfield name="MCEO2" caption="Match or Capture Channel 2 Event Output Enable" mask="0x4000000"/>
          <bitfield name="MCEO3" caption="Match or Capture Channel 3 Event Output Enable" mask="0x8000000"/>
          <bitfield name="MCEO4" caption="Match or Capture Channel 4 Event Output Enable" mask="0x10000000"/>
          <bitfield name="MCEO5" caption="Match or Capture Channel 5 Event Output Enable" mask="0x20000000"/>
        </register>
        <register name="INTENCLR" offset="0x24" rw="RW" size="4" atomic-op="clear:INTENCLR" initval="0x00000000" caption="Interrupt Enable Clear">
          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
          <bitfield name="UFS" caption="Non-Recoverable Update Fault Interrupt Enable" mask="0x400"/>
          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
          <bitfield name="MC4" caption="Match or Capture Channel 4 Interrupt Enable" mask="0x100000"/>
          <bitfield name="MC5" caption="Match or Capture Channel 5 Interrupt Enable" mask="0x200000"/>
        </register>
        <register name="INTENSET" offset="0x28" rw="RW" size="4" atomic-op="set:INTENSET" initval="0x00000000" caption="Interrupt Enable Set">
          <bitfield name="OVF" caption="Overflow Interrupt Enable" mask="0x1"/>
          <bitfield name="TRG" caption="Retrigger Interrupt Enable" mask="0x2"/>
          <bitfield name="CNT" caption="Counter Interrupt Enable" mask="0x4"/>
          <bitfield name="ERR" caption="Error Interrupt Enable" mask="0x8"/>
          <bitfield name="UFS" caption="Non-Recoverable Update Fault Interrupt Enable" mask="0x400"/>
          <bitfield name="DFS" caption="Non-Recoverable Debug Fault Interrupt Enable" mask="0x800"/>
          <bitfield name="FAULTA" caption="Recoverable Fault A Interrupt Enable" mask="0x1000"/>
          <bitfield name="FAULTB" caption="Recoverable Fault B Interrupt Enable" mask="0x2000"/>
          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 Interrupt Enable" mask="0x4000"/>
          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 Interrupt Enable" mask="0x8000"/>
          <bitfield name="MC0" caption="Match or Capture Channel 0 Interrupt Enable" mask="0x10000"/>
          <bitfield name="MC1" caption="Match or Capture Channel 1 Interrupt Enable" mask="0x20000"/>
          <bitfield name="MC2" caption="Match or Capture Channel 2 Interrupt Enable" mask="0x40000"/>
          <bitfield name="MC3" caption="Match or Capture Channel 3 Interrupt Enable" mask="0x80000"/>
          <bitfield name="MC4" caption="Match or Capture Channel 4 Interrupt Enable" mask="0x100000"/>
          <bitfield name="MC5" caption="Match or Capture Channel 5 Interrupt Enable" mask="0x200000"/>
        </register>
        <register name="INTFLAG" offset="0x2C" rw="RW" size="4" atomic-op="clear:INTFLAG" initval="0x00000000" caption="Interrupt Flag Status and Clear">
          <bitfield name="OVF" caption="Overflow" mask="0x1"/>
          <bitfield name="TRG" caption="Retrigger" mask="0x2"/>
          <bitfield name="CNT" caption="Counter" mask="0x4"/>
          <bitfield name="ERR" caption="Error" mask="0x8"/>
          <bitfield name="UFS" caption="Non-Recoverable Update Fault" mask="0x400"/>
          <bitfield name="DFS" caption="Non-Recoverable Debug Fault" mask="0x800"/>
          <bitfield name="FAULTA" caption="Recoverable Fault A" mask="0x1000"/>
          <bitfield name="FAULTB" caption="Recoverable Fault B" mask="0x2000"/>
          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0" mask="0x4000"/>
          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1" mask="0x8000"/>
          <bitfield name="MC0" caption="Match or Capture 0" mask="0x10000"/>
          <bitfield name="MC1" caption="Match or Capture 1" mask="0x20000"/>
          <bitfield name="MC2" caption="Match or Capture 2" mask="0x40000"/>
          <bitfield name="MC3" caption="Match or Capture 3" mask="0x80000"/>
          <bitfield name="MC4" caption="Match or Capture 4" mask="0x100000"/>
          <bitfield name="MC5" caption="Match or Capture 5" mask="0x200000"/>
        </register>
        <register name="STATUS" offset="0x30" rw="RW" size="4" initval="0x00000001" caption="Status">
          <bitfield name="STOP" caption="Stop" mask="0x1"/>
          <bitfield name="IDX" caption="Ramp" mask="0x2"/>
          <bitfield name="UFS" caption="Non-recoverable Update Fault State" mask="0x4"/>
          <bitfield name="DFS" caption="Non-Recoverable Debug Fault State" mask="0x8"/>
          <bitfield name="SLAVE" caption="Slave" mask="0x10"/>
          <bitfield name="PATTBUFV" caption="Pattern Buffer Valid" mask="0x20"/>
          <bitfield name="PERBUFV" caption="Period Buffer Valid" mask="0x80"/>
          <bitfield name="FAULTAIN" caption="Recoverable Fault A Input" mask="0x100"/>
          <bitfield name="FAULTBIN" caption="Recoverable Fault B Input" mask="0x200"/>
          <bitfield name="FAULT0IN" caption="Non-Recoverable Fault0 Input" mask="0x400"/>
          <bitfield name="FAULT1IN" caption="Non-Recoverable Fault1 Input" mask="0x800"/>
          <bitfield name="FAULTA" caption="Recoverable Fault A State" mask="0x1000"/>
          <bitfield name="FAULTB" caption="Recoverable Fault B State" mask="0x2000"/>
          <bitfield name="FAULT0" caption="Non-Recoverable Fault 0 State" mask="0x4000"/>
          <bitfield name="FAULT1" caption="Non-Recoverable Fault 1 State" mask="0x8000"/>
          <bitfield name="CCBUFV0" caption="Compare Channel 0 Buffer Valid" mask="0x10000"/>
          <bitfield name="CCBUFV1" caption="Compare Channel 1 Buffer Valid" mask="0x20000"/>
          <bitfield name="CCBUFV2" caption="Compare Channel 2 Buffer Valid" mask="0x40000"/>
          <bitfield name="CCBUFV3" caption="Compare Channel 3 Buffer Valid" mask="0x80000"/>
          <bitfield name="CCBUFV4" caption="Compare Channel 4 Buffer Valid" mask="0x100000"/>
          <bitfield name="CCBUFV5" caption="Compare Channel 5 Buffer Valid" mask="0x200000"/>
          <bitfield name="CMP0" caption="Compare Channel 0 Value" mask="0x1000000"/>
          <bitfield name="CMP1" caption="Compare Channel 1 Value" mask="0x2000000"/>
          <bitfield name="CMP2" caption="Compare Channel 2 Value" mask="0x4000000"/>
          <bitfield name="CMP3" caption="Compare Channel 3 Value" mask="0x8000000"/>
          <bitfield name="CMP4" caption="Compare Channel 4 Value" mask="0x10000000"/>
          <bitfield name="CMP5" caption="Compare Channel 5 Value" mask="0x20000000"/>
        </register>
        <register name="COUNT" offset="0x34" rw="RW" access="RWSYNC" size="4" initval="0x00000000" caption="Count">
          <mode name="DITH4">
            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFF0"/>
          </mode>
          <mode name="DITH5">
            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFE0"/>
          </mode>
          <mode name="DITH6">
            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFC0"/>
          </mode>
          <mode name="DEFAULT_MODE">
            <bitfield name="COUNT" caption="Counter Value" mask="0xFFFFFF"/>
          </mode>
        </register>
        <register name="PATT" offset="0x38" rw="RW" access="WSYNC" size="2" initval="0x0000" caption="Pattern">
          <bitfield name="PGE0" caption="Pattern Generator 0 Output Enable" mask="0x1"/>
          <bitfield name="PGE1" caption="Pattern Generator 1 Output Enable" mask="0x2"/>
          <bitfield name="PGE2" caption="Pattern Generator 2 Output Enable" mask="0x4"/>
          <bitfield name="PGE3" caption="Pattern Generator 3 Output Enable" mask="0x8"/>
          <bitfield name="PGE4" caption="Pattern Generator 4 Output Enable" mask="0x10"/>
          <bitfield name="PGE5" caption="Pattern Generator 5 Output Enable" mask="0x20"/>
          <bitfield name="PGE6" caption="Pattern Generator 6 Output Enable" mask="0x40"/>
          <bitfield name="PGE7" caption="Pattern Generator 7 Output Enable" mask="0x80"/>
          <bitfield name="PGV0" caption="Pattern Generator 0 Output Value" mask="0x100"/>
          <bitfield name="PGV1" caption="Pattern Generator 1 Output Value" mask="0x200"/>
          <bitfield name="PGV2" caption="Pattern Generator 2 Output Value" mask="0x400"/>
          <bitfield name="PGV3" caption="Pattern Generator 3 Output Value" mask="0x800"/>
          <bitfield name="PGV4" caption="Pattern Generator 4 Output Value" mask="0x1000"/>
          <bitfield name="PGV5" caption="Pattern Generator 5 Output Value" mask="0x2000"/>
          <bitfield name="PGV6" caption="Pattern Generator 6 Output Value" mask="0x4000"/>
          <bitfield name="PGV7" caption="Pattern Generator 7 Output Value" mask="0x8000"/>
        </register>
        <register name="WAVE" offset="0x3C" rw="RW" access="WSYNC" size="4" initval="0x00000000" caption="Waveform Control">
          <bitfield name="WAVEGEN" caption="Waveform Generation" mask="0x7" values="TCC_WAVE__WAVEGEN"/>
          <bitfield name="RAMP" caption="Ramp Mode" mask="0x30" values="TCC_WAVE__RAMP"/>
          <bitfield name="CIPEREN" caption="Circular period Enable" mask="0x80"/>
          <bitfield name="CICCEN0" caption="Circular Channel 0 Enable" mask="0x100"/>
          <bitfield name="CICCEN1" caption="Circular Channel 1 Enable" mask="0x200"/>
          <bitfield name="CICCEN2" caption="Circular Channel 2 Enable" mask="0x400"/>
          <bitfield name="CICCEN3" caption="Circular Channel 3 Enable" mask="0x800"/>
          <bitfield name="POL0" caption="Channel 0 Polarity" mask="0x10000"/>
          <bitfield name="POL1" caption="Channel 1 Polarity" mask="0x20000"/>
          <bitfield name="POL2" caption="Channel 2 Polarity" mask="0x40000"/>
          <bitfield name="POL3" caption="Channel 3 Polarity" mask="0x80000"/>
          <bitfield name="POL4" caption="Channel 4 Polarity" mask="0x100000"/>
          <bitfield name="POL5" caption="Channel 5 Polarity" mask="0x200000"/>
          <bitfield name="SWAP0" caption="Swap DTI Output Pair 0" mask="0x1000000"/>
          <bitfield name="SWAP1" caption="Swap DTI Output Pair 1" mask="0x2000000"/>
          <bitfield name="SWAP2" caption="Swap DTI Output Pair 2" mask="0x4000000"/>
          <bitfield name="SWAP3" caption="Swap DTI Output Pair 3" mask="0x8000000"/>
        </register>
        <register name="PER" offset="0x40" rw="RW" access="WSYNC" size="4" initval="0xFFFFFFFF" caption="Period">
          <mode name="DITH4">
            <bitfield name="DITHER" caption="Dithering Cycle Number" mask="0xF"/>
            <bitfield name="PER" caption="Period Value" mask="0xFFFFF0"/>
          </mode>
          <mode name="DITH5">
            <bitfield name="DITHER" caption="Dithering Cycle Number" mask="0x1F"/>
            <bitfield name="PER" caption="Period Value" mask="0xFFFFE0"/>
          </mode>
          <mode name="DITH6">
            <bitfield name="DITHER" caption="Dithering Cycle Number" mask="0x3F"/>
            <bitfield name="PER" caption="Period Value" mask="0xFFFFC0"/>
          </mode>
          <mode name="DEFAULT_MODE">
            <bitfield name="PER" caption="Period Value" mask="0xFFFFFF"/>
          </mode>
        </register>
        <register name="CC" offset="0x44" rw="RW" size="4" count="6" initval="0x00000000" caption="Compare and Capture">
          <mode name="DITH4">
            <bitfield name="DITHER" caption="Dithering Cycle Number" mask="0xF"/>
            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFF0"/>
          </mode>
          <mode name="DITH5">
            <bitfield name="DITHER" caption="Dithering Cycle Number" mask="0x1F"/>
            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFE0"/>
          </mode>
          <mode name="DITH6">
            <bitfield name="DITHER" caption="Dithering Cycle Number" mask="0x3F"/>
            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFC0"/>
          </mode>
          <mode name="DEFAULT_MODE">
            <bitfield name="CC" caption="Channel Compare/Capture Value" mask="0xFFFFFF"/>
          </mode>
        </register>
        <register name="PATTBUF" offset="0x64" rw="RW" size="2" initval="0x0000" caption="Pattern Buffer">
          <bitfield name="PGEB0" caption="Pattern Generator 0 Output Enable Buffer" mask="0x1"/>
          <bitfield name="PGEB1" caption="Pattern Generator 1 Output Enable Buffer" mask="0x2"/>
          <bitfield name="PGEB2" caption="Pattern Generator 2 Output Enable Buffer" mask="0x4"/>
          <bitfield name="PGEB3" caption="Pattern Generator 3 Output Enable Buffer" mask="0x8"/>
          <bitfield name="PGEB4" caption="Pattern Generator 4 Output Enable Buffer" mask="0x10"/>
          <bitfield name="PGEB5" caption="Pattern Generator 5 Output Enable Buffer" mask="0x20"/>
          <bitfield name="PGEB6" caption="Pattern Generator 6 Output Enable Buffer" mask="0x40"/>
          <bitfield name="PGEB7" caption="Pattern Generator 7 Output Enable Buffer" mask="0x80"/>
          <bitfield name="PGVB0" caption="Pattern Generator 0 Output Enable" mask="0x100"/>
          <bitfield name="PGVB1" caption="Pattern Generator 1 Output Enable" mask="0x200"/>
          <bitfield name="PGVB2" caption="Pattern Generator 2 Output Enable" mask="0x400"/>
          <bitfield name="PGVB3" caption="Pattern Generator 3 Output Enable" mask="0x800"/>
          <bitfield name="PGVB4" caption="Pattern Generator 4 Output Enable" mask="0x1000"/>
          <bitfield name="PGVB5" caption="Pattern Generator 5 Output Enable" mask="0x2000"/>
          <bitfield name="PGVB6" caption="Pattern Generator 6 Output Enable" mask="0x4000"/>
          <bitfield name="PGVB7" caption="Pattern Generator 7 Output Enable" mask="0x8000"/>
        </register>
        <register name="PERBUF" offset="0x6C" rw="RW" size="4" initval="0xFFFFFFFF" caption="Period Buffer">
          <mode name="DITH4">
            <bitfield name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0xF"/>
            <bitfield name="PERBUF" caption="Period Buffer Value" mask="0xFFFFF0"/>
          </mode>
          <mode name="DITH5">
            <bitfield name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
            <bitfield name="PERBUF" caption="Period Buffer Value" mask="0xFFFFE0"/>
          </mode>
          <mode name="DITH6">
            <bitfield name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
            <bitfield name="PERBUF" caption="Period Buffer Value" mask="0xFFFFC0"/>
          </mode>
          <mode name="DEFAULT_MODE">
            <bitfield name="PERBUF" caption="Period Buffer Value" mask="0xFFFFFF"/>
          </mode>
        </register>
        <register name="CCBUF" offset="0x70" rw="RW" size="4" count="6" initval="0x00000000" caption="Compare and Capture Buffer">
          <mode name="DITH4">
            <bitfield name="CCBUF" caption="Channel Compare/Capture Buffer Value" mask="0xF"/>
            <bitfield name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0xFFFFF0"/>
          </mode>
          <mode name="DITH5">
            <bitfield name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x1F"/>
            <bitfield name="CCBUF" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFE0"/>
          </mode>
          <mode name="DITH6">
            <bitfield name="DITHERBUF" caption="Dithering Buffer Cycle Number" mask="0x3F"/>
            <bitfield name="CCBUF" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFC0"/>
          </mode>
          <mode name="DEFAULT_MODE">
            <bitfield name="CCBUF" caption="Channel Compare/Capture Buffer Value" mask="0xFFFFFF"/>
          </mode>
        </register>
      </register-group>
      <value-group name="TCC_CTRLA__PRESCALER">
        <value name="DIV1" caption="No division" value="0"/>
        <value name="DIV2" caption="Divide by 2" value="1"/>
        <value name="DIV4" caption="Divide by 4" value="2"/>
        <value name="DIV8" caption="Divide by 8" value="3"/>
        <value name="DIV16" caption="Divide by 16" value="4"/>
        <value name="DIV64" caption="Divide by 64" value="5"/>
        <value name="DIV256" caption="Divide by 256" value="6"/>
        <value name="DIV1024" caption="Divide by 1024" value="7"/>
      </value-group>
      <value-group name="TCC_CTRLA__PRESCSYNC">
        <value name="GCLK" caption="Reload or reset counter on next GCLK" value="0"/>
        <value name="PRESC" caption="Reload or reset counter on next prescaler clock" value="1"/>
        <value name="RESYNC" caption="Reload or reset counter on next GCLK and reset prescaler counter" value="2"/>
      </value-group>
      <value-group name="TCC_CTRLA__RESOLUTION">
        <value name="NONE" caption="Dithering is disabled" value="0"/>
        <value name="DITH4" caption="Dithering is done every 16 PWM frames" value="1"/>
        <value name="DITH5" caption="Dithering is done every 32 PWM frames" value="2"/>
        <value name="DITH6" caption="Dithering is done every 64 PWM frames" value="3"/>
      </value-group>
      <value-group name="TCC_CTRLBCLR__CMD">
        <value name="NONE" caption="No action" value="0"/>
        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
        <value name="STOP" caption="Force stop" value="2"/>
        <value name="UPDATE" caption="Force update or double buffered registers" value="3"/>
        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
        <value name="DMAOS" caption="One-shot DMA trigger" value="5"/>
      </value-group>
      <value-group name="TCC_CTRLBCLR__IDXCMD">
        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
      </value-group>
      <value-group name="TCC_CTRLBSET__CMD">
        <value name="NONE" caption="No action" value="0"/>
        <value name="RETRIGGER" caption="Clear start, restart or retrigger" value="1"/>
        <value name="STOP" caption="Force stop" value="2"/>
        <value name="UPDATE" caption="Force update or double buffered registers" value="3"/>
        <value name="READSYNC" caption="Force COUNT read synchronization" value="4"/>
        <value name="DMAOS" caption="One-shot DMA trigger" value="5"/>
      </value-group>
      <value-group name="TCC_CTRLBSET__IDXCMD">
        <value name="DISABLE" caption="Command disabled: Index toggles between cycles A and B" value="0"/>
        <value name="SET" caption="Set index: cycle B will be forced in the next cycle" value="1"/>
        <value name="CLEAR" caption="Clear index: cycle A will be forced in the next cycle" value="2"/>
        <value name="HOLD" caption="Hold index: the next cycle will be the same as the current cycle" value="3"/>
      </value-group>
      <value-group name="TCC_FCTRLA__BLANK">
        <value name="START" caption="Blanking applied from start of the ramp" value="0"/>
        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
      </value-group>
      <value-group name="TCC_FCTRLA__CAPTURE">
        <value name="DISABLE" caption="No capture" value="0"/>
        <value name="CAPT" caption="Capture on fault" value="1"/>
        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
        <value name="CAPTMARK" caption="Capture with ramp index as MSB value" value="7"/>
      </value-group>
      <value-group name="TCC_FCTRLA__CHSEL">
        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
      </value-group>
      <value-group name="TCC_FCTRLA__HALT">
        <value name="DISABLE" caption="Halt action disabled" value="0"/>
        <value name="HW" caption="Hardware halt action" value="1"/>
        <value name="SW" caption="Software halt action" value="2"/>
        <value name="NR" caption="Non-recoverable fault" value="3"/>
      </value-group>
      <value-group name="TCC_FCTRLA__SRC">
        <value name="DISABLE" caption="Fault input disabled" value="0"/>
        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
      </value-group>
      <value-group name="TCC_FCTRLB__BLANK">
        <value name="START" caption="Blanking applied from start of the ramp" value="0"/>
        <value name="RISE" caption="Blanking applied from rising edge of the output waveform" value="1"/>
        <value name="FALL" caption="Blanking applied from falling edge of the output waveform" value="2"/>
        <value name="BOTH" caption="Blanking applied from each toggle of the output waveform" value="3"/>
      </value-group>
      <value-group name="TCC_FCTRLB__CAPTURE">
        <value name="DISABLE" caption="No capture" value="0"/>
        <value name="CAPT" caption="Capture on fault" value="1"/>
        <value name="CAPTMIN" caption="Minimum capture" value="2"/>
        <value name="CAPTMAX" caption="Maximum capture" value="3"/>
        <value name="LOCMIN" caption="Minimum local detection" value="4"/>
        <value name="LOCMAX" caption="Maximum local detection" value="5"/>
        <value name="DERIV0" caption="Minimum and maximum local detection" value="6"/>
        <value name="CAPTMARK" caption="Capture with ramp index as MSB value" value="7"/>
      </value-group>
      <value-group name="TCC_FCTRLB__CHSEL">
        <value name="CC0" caption="Capture value stored in channel 0" value="0"/>
        <value name="CC1" caption="Capture value stored in channel 1" value="1"/>
        <value name="CC2" caption="Capture value stored in channel 2" value="2"/>
        <value name="CC3" caption="Capture value stored in channel 3" value="3"/>
      </value-group>
      <value-group name="TCC_FCTRLB__HALT">
        <value name="DISABLE" caption="Halt action disabled" value="0"/>
        <value name="HW" caption="Hardware halt action" value="1"/>
        <value name="SW" caption="Software halt action" value="2"/>
        <value name="NR" caption="Non-recoverable fault" value="3"/>
      </value-group>
      <value-group name="TCC_FCTRLB__SRC">
        <value name="DISABLE" caption="Fault input disabled" value="0"/>
        <value name="ENABLE" caption="MCEx (x=0,1) event input" value="1"/>
        <value name="INVERT" caption="Inverted MCEx (x=0,1) event input" value="2"/>
        <value name="ALTFAULT" caption="Alternate fault (A or B) state at the end of the previous period" value="3"/>
      </value-group>
      <value-group name="TCC_EVCTRL__CNTSEL">
        <value name="START" caption="An interrupt/event is generated when a new counter cycle starts" value="0"/>
        <value name="END" caption="An interrupt/event is generated when a counter cycle ends" value="1"/>
        <value name="BETWEEN" caption="An interrupt/event is generated when a counter cycle ends, except for the first and last cycles" value="2"/>
        <value name="BOUNDARY" caption="An interrupt/event is generated when a new counter cycle starts or a counter cycle ends" value="3"/>
      </value-group>
      <value-group name="TCC_EVCTRL__EVACT0">
        <value name="OFF" caption="Event action disabled" value="0"/>
        <value name="RETRIGGER" caption="Start, restart or re-trigger counter on event" value="1"/>
        <value name="COUNTEV" caption="Count on event" value="2"/>
        <value name="START" caption="Start counter on event" value="3"/>
        <value name="INC" caption="Increment counter on event" value="4"/>
        <value name="COUNT" caption="Count on active state of asynchronous event" value="5"/>
        <value name="STAMP" caption="Stamp capture" value="6"/>
        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
      </value-group>
      <value-group name="TCC_EVCTRL__EVACT1">
        <value name="OFF" caption="Event action disabled" value="0"/>
        <value name="RETRIGGER" caption="Re-trigger counter on event" value="1"/>
        <value name="DIR" caption="Direction control" value="2"/>
        <value name="STOP" caption="Stop counter on event" value="3"/>
        <value name="DEC" caption="Decrement counter on event" value="4"/>
        <value name="PPW" caption="Period capture value in CC0 register, pulse width capture value in CC1 register" value="5"/>
        <value name="PWP" caption="Period capture value in CC1 register, pulse width capture value in CC0 register" value="6"/>
        <value name="FAULT" caption="Non-recoverable fault" value="7"/>
      </value-group>
      <value-group name="TCC_WAVE__RAMP">
        <value name="RAMP1" caption="RAMP1 operation" value="0"/>
        <value name="RAMP2A" caption="Alternative RAMP2 operation" value="1"/>
        <value name="RAMP2" caption="RAMP2 operation" value="2"/>
        <value name="RAMP2C" caption="Critical RAMP2 operation" value="3"/>
      </value-group>
      <value-group name="TCC_WAVE__WAVEGEN">
        <value name="NFRQ" caption="Normal frequency" value="0"/>
        <value name="MFRQ" caption="Match frequency" value="1"/>
        <value name="NPWM" caption="Normal PWM" value="2"/>
        <value name="DSCRITICAL" caption="Dual-slope critical" value="4"/>
        <value name="DSBOTTOM" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO" value="5"/>
        <value name="DSBOTH" caption="Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP" value="6"/>
        <value name="DSTOP" caption="Dual-slope with interrupt/event condition when COUNT reaches TOP" value="7"/>
      </value-group>
    </module>
    <module name="TRNG" id="U2242" version="1.1.0" caption="True Random Generator">
      <register-group name="TRNG" caption="True Random Generator">
        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby" mask="0x40"/>
        </register>
        <register name="EVCTRL" offset="0x4" rw="RW" size="1" initval="0x00" caption="Event Control">
          <bitfield name="DATARDYEO" caption="Data Ready Event Output" mask="0x1"/>
        </register>
        <register name="INTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
          <bitfield name="DATARDY" caption="Data Ready Interrupt Enable" mask="0x1"/>
        </register>
        <register name="INTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
          <bitfield name="DATARDY" caption="Data Ready Interrupt Enable" mask="0x1"/>
        </register>
        <register name="INTFLAG" offset="0xA" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
          <bitfield name="DATARDY" caption="Data Ready Interrupt Flag" mask="0x1"/>
        </register>
        <register name="DATA" offset="0x20" rw="R" size="4" initval="0x00000000" caption="Output Data">
          <bitfield name="DATA" caption="Output Data" mask="0xFFFFFFFF"/>
        </register>
      </register-group>
    </module>
    <module name="USB" id="U2222" version="1.2.0" caption="Universal Serial Bus">
      <register-group name="DEVICE_DESC_BANK" size="0x10">
        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer">
          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
        </register>
        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="DEVICE_DESC_BANK Endpoint Bank, Packet Size">
          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
          <bitfield name="SIZE" caption="Enpoint size" mask="0x70000000"/>
          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
        </register>
        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="DEVICE_DESC_BANK Endpoint Bank, Extended">
          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
        </register>
        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="DEVICE_DESC_BANK Enpoint Bank, Status of Bank">
          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
        </register>
      </register-group>
      <register-group name="HOST_DESC_BANK" size="0x10">
        <register name="ADDR" offset="0x0" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Adress of Data Buffer">
          <bitfield name="ADDR" caption="Adress of data buffer" mask="0xFFFFFFFF"/>
        </register>
        <register name="PCKSIZE" offset="0x4" rw="RW" size="4" caption="HOST_DESC_BANK Host Bank, Packet Size">
          <bitfield name="BYTE_COUNT" caption="Byte Count" mask="0x3FFF"/>
          <bitfield name="MULTI_PACKET_SIZE" caption="Multi Packet In or Out size" mask="0xFFFC000"/>
          <bitfield name="SIZE" caption="Pipe size" mask="0x70000000"/>
          <bitfield name="AUTO_ZLP" caption="Automatic Zero Length Packet" mask="0x80000000"/>
        </register>
        <register name="EXTREG" offset="0x8" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Extended">
          <bitfield name="SUBPID" caption="SUBPID field send with extended token" mask="0xF"/>
          <bitfield name="VARIABLE" caption="Variable field send with extended token" mask="0x7FF0"/>
        </register>
        <register name="STATUS_BK" offset="0xA" rw="RW" size="1" caption="HOST_DESC_BANK Host Bank, Status of Bank">
          <bitfield name="CRCERR" caption="CRC Error Status" mask="0x1"/>
          <bitfield name="ERRORFLOW" caption="Error Flow Status" mask="0x2"/>
        </register>
        <register name="CTRL_PIPE" offset="0xC" rw="RW" size="2" initval="0x0000" caption="HOST_DESC_BANK Host Bank, Host Control Pipe">
          <bitfield name="PDADDR" caption="Pipe Device Adress" mask="0x7F"/>
          <bitfield name="PEPNUM" caption="Pipe Endpoint Number" mask="0xF00"/>
          <bitfield name="PERMAX" caption="Pipe Error Max Number" mask="0xF000"/>
        </register>
        <register name="STATUS_PIPE" offset="0xE" rw="RW" size="2" caption="HOST_DESC_BANK Host Bank, Host Status Pipe">
          <bitfield name="DTGLER" caption="Data Toggle Error" mask="0x1"/>
          <bitfield name="DAPIDER" caption="Data PID Error" mask="0x2"/>
          <bitfield name="PIDER" caption="PID Error" mask="0x4"/>
          <bitfield name="TOUTER" caption="Time Out Error" mask="0x8"/>
          <bitfield name="CRC16ER" caption="CRC16 Error" mask="0x10"/>
          <bitfield name="ERCNT" caption="Pipe Error Count" mask="0xE0"/>
        </register>
      </register-group>
      <register-group name="DEVICE_ENDPOINT" size="0x20">
        <register name="EPCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Configuration">
          <bitfield name="EPTYPE0" caption="End Point Type0" mask="0x7"/>
          <bitfield name="EPTYPE1" caption="End Point Type1" mask="0x70"/>
          <bitfield name="NYETDIS" caption="NYET Token Disable" mask="0x80"/>
        </register>
        <register name="EPSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Clear">
          <bitfield name="DTGLOUT" caption="Data Toggle OUT Clear" mask="0x1"/>
          <bitfield name="DTGLIN" caption="Data Toggle IN Clear" mask="0x2"/>
          <bitfield name="CURBK" caption="Current Bank Clear" mask="0x4"/>
          <bitfield name="STALLRQ0" caption="Stall 0 Request Clear" mask="0x10"/>
          <bitfield name="STALLRQ1" caption="Stall 1 Request Clear" mask="0x20"/>
          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
        </register>
        <register name="EPSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:EPSTATUS" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status Set">
          <bitfield name="DTGLOUT" caption="Data Toggle OUT Set" mask="0x1"/>
          <bitfield name="DTGLIN" caption="Data Toggle IN Set" mask="0x2"/>
          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
          <bitfield name="STALLRQ0" caption="Stall 0 Request Set" mask="0x10"/>
          <bitfield name="STALLRQ1" caption="Stall 1 Request Set" mask="0x20"/>
          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
        </register>
        <register name="EPSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="DEVICE_ENDPOINT End Point Pipe Status">
          <bitfield name="DTGLOUT" caption="Data Toggle Out" mask="0x1"/>
          <bitfield name="DTGLIN" caption="Data Toggle In" mask="0x2"/>
          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
          <bitfield name="STALLRQ0" caption="Stall 0 Request" mask="0x10"/>
          <bitfield name="STALLRQ1" caption="Stall 1 Request" mask="0x20"/>
          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
        </register>
        <register name="EPINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:EPINTFLAG" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Flag">
          <bitfield name="TRCPT0" caption="Transfer Complete 0" mask="0x1"/>
          <bitfield name="TRCPT1" caption="Transfer Complete 1" mask="0x2"/>
          <bitfield name="TRFAIL0" caption="Error Flow 0" mask="0x4"/>
          <bitfield name="TRFAIL1" caption="Error Flow 1" mask="0x8"/>
          <bitfield name="RXSTP" caption="Received Setup" mask="0x10"/>
          <bitfield name="STALL0" caption="Stall 0 In/out" mask="0x20"/>
          <bitfield name="STALL1" caption="Stall 1 In/out" mask="0x40"/>
        </register>
        <register name="EPINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:EPINTENCLR" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Clear Flag">
          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Disable" mask="0x1"/>
          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Disable" mask="0x2"/>
          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Disable" mask="0x4"/>
          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Disable" mask="0x8"/>
          <bitfield name="RXSTP" caption="Received Setup Interrupt Disable" mask="0x10"/>
          <bitfield name="STALL0" caption="Stall 0 In/Out Interrupt Disable" mask="0x20"/>
          <bitfield name="STALL1" caption="Stall 1 In/Out Interrupt Disable" mask="0x40"/>
        </register>
        <register name="EPINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:EPINTENSET" initval="0x00" caption="DEVICE_ENDPOINT End Point Interrupt Set Flag">
          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
          <bitfield name="TRFAIL0" caption="Error Flow 0 Interrupt Enable" mask="0x4"/>
          <bitfield name="TRFAIL1" caption="Error Flow 1 Interrupt Enable" mask="0x8"/>
          <bitfield name="RXSTP" caption="Received Setup Interrupt Enable" mask="0x10"/>
          <bitfield name="STALL0" caption="Stall 0 In/out Interrupt enable" mask="0x20"/>
          <bitfield name="STALL1" caption="Stall 1 In/out Interrupt enable" mask="0x40"/>
        </register>
      </register-group>
      <register-group name="HOST_PIPE" size="0x20">
        <register name="PCFG" offset="0x0" rw="RW" size="1" initval="0x00" caption="HOST_PIPE End Point Configuration">
          <bitfield name="PTOKEN" caption="Pipe Token" mask="0x3"/>
          <bitfield name="BK" caption="Pipe Bank" mask="0x4"/>
          <bitfield name="PTYPE" caption="Pipe Type" mask="0x38"/>
        </register>
        <register name="BINTERVAL" offset="0x3" rw="RW" size="1" initval="0x00" caption="HOST_PIPE Bus Access Period of Pipe">
          <bitfield name="BITINTERVAL" caption="Bit Interval" mask="0xFF"/>
        </register>
        <register name="PSTATUSCLR" offset="0x4" rw="W" size="1" atomic-op="clear:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Clear">
          <bitfield name="DTGL" caption="Data Toggle clear" mask="0x1"/>
          <bitfield name="CURBK" caption="Curren Bank clear" mask="0x4"/>
          <bitfield name="PFREEZE" caption="Pipe Freeze Clear" mask="0x10"/>
          <bitfield name="BK0RDY" caption="Bank 0 Ready Clear" mask="0x40"/>
          <bitfield name="BK1RDY" caption="Bank 1 Ready Clear" mask="0x80"/>
        </register>
        <register name="PSTATUSSET" offset="0x5" rw="W" size="1" atomic-op="set:PSTATUS" initval="0x00" caption="HOST_PIPE End Point Pipe Status Set">
          <bitfield name="DTGL" caption="Data Toggle Set" mask="0x1"/>
          <bitfield name="CURBK" caption="Current Bank Set" mask="0x4"/>
          <bitfield name="PFREEZE" caption="Pipe Freeze Set" mask="0x10"/>
          <bitfield name="BK0RDY" caption="Bank 0 Ready Set" mask="0x40"/>
          <bitfield name="BK1RDY" caption="Bank 1 Ready Set" mask="0x80"/>
        </register>
        <register name="PSTATUS" offset="0x6" rw="R" size="1" initval="0x00" caption="HOST_PIPE End Point Pipe Status">
          <bitfield name="DTGL" caption="Data Toggle" mask="0x1"/>
          <bitfield name="CURBK" caption="Current Bank" mask="0x4"/>
          <bitfield name="PFREEZE" caption="Pipe Freeze" mask="0x10"/>
          <bitfield name="BK0RDY" caption="Bank 0 ready" mask="0x40"/>
          <bitfield name="BK1RDY" caption="Bank 1 ready" mask="0x80"/>
        </register>
        <register name="PINTFLAG" offset="0x7" rw="RW" size="1" atomic-op="clear:PINTFLAG" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag">
          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Flag" mask="0x1"/>
          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Flag" mask="0x2"/>
          <bitfield name="TRFAIL" caption="Error Flow Interrupt Flag" mask="0x4"/>
          <bitfield name="PERR" caption="Pipe Error Interrupt Flag" mask="0x8"/>
          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Flag" mask="0x10"/>
          <bitfield name="STALL" caption="Stall Interrupt Flag" mask="0x20"/>
        </register>
        <register name="PINTENCLR" offset="0x8" rw="RW" size="1" atomic-op="clear:PINTENCLR" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Clear">
          <bitfield name="TRCPT0" caption="Transfer Complete 0 Disable" mask="0x1"/>
          <bitfield name="TRCPT1" caption="Transfer Complete 1 Disable" mask="0x2"/>
          <bitfield name="TRFAIL" caption="Error Flow Interrupt Disable" mask="0x4"/>
          <bitfield name="PERR" caption="Pipe Error Interrupt Disable" mask="0x8"/>
          <bitfield name="TXSTP" caption="Transmit Setup Interrupt Disable" mask="0x10"/>
          <bitfield name="STALL" caption="Stall Inetrrupt Disable" mask="0x20"/>
        </register>
        <register name="PINTENSET" offset="0x9" rw="RW" size="1" atomic-op="set:PINTENSET" initval="0x00" caption="HOST_PIPE Pipe Interrupt Flag Set">
          <bitfield name="TRCPT0" caption="Transfer Complete 0 Interrupt Enable" mask="0x1"/>
          <bitfield name="TRCPT1" caption="Transfer Complete 1 Interrupt Enable" mask="0x2"/>
          <bitfield name="TRFAIL" caption="Error Flow Interrupt Enable" mask="0x4"/>
          <bitfield name="PERR" caption="Pipe Error Interrupt Enable" mask="0x8"/>
          <bitfield name="TXSTP" caption="Transmit  Setup Interrupt Enable" mask="0x10"/>
          <bitfield name="STALL" caption="Stall Interrupt Enable" mask="0x20"/>
        </register>
      </register-group>
      <register-group class="union" union-tag="USB.CTRLA.MODE" name="USB" caption="Universal Serial Bus">
        <register-group name="DEVICE" name-in-module="USB_DEVICE" union-tag-value="0" offset="0"/>
        <register-group name="HOST" name-in-module="USB_HOST" union-tag-value="1" offset="0"/>
      </register-group>
      <register-group name="USB_DEVICE" caption="Universal Serial Bus - USB is Device">
        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
        </register>
        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
        </register>
        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x0F" caption="USB Quality Of Service">
          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3"/>
          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC"/>
        </register>
        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0001" caption="DEVICE Control B">
          <bitfield name="DETACH" caption="Detach" mask="0x1"/>
          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x2"/>
          <bitfield name="SPDCONF" caption="Speed Configuration" mask="0xC" values="USB_DEVICE_CTRLB__SPDCONF"/>
          <bitfield name="NREPLY" caption="No Reply" mask="0x10"/>
          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
          <bitfield name="TSTPCKT" caption="Test packet mode" mask="0x80"/>
          <bitfield name="OPMODE2" caption="Specific Operational Mode" mask="0x100"/>
          <bitfield name="GNAK" caption="Global NAK" mask="0x200"/>
          <bitfield name="LPMHDSK" caption="Link Power Management Handshake" mask="0xC00" values="USB_DEVICE_CTRLB__LPMHDSK"/>
        </register>
        <register name="DADD" offset="0xA" rw="RW" size="1" initval="0x00" caption="DEVICE Device Address">
          <bitfield name="DADD" caption="Device Address" mask="0x7F"/>
          <bitfield name="ADDEN" caption="Device Address Enable" mask="0x80"/>
        </register>
        <register name="STATUS" offset="0xC" rw="R" size="1" initval="0x40" caption="DEVICE Status">
          <bitfield name="SPEED" caption="Speed Status" mask="0xC" values="USB_DEVICE_STATUS__SPEED"/>
          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0" values="USB_DEVICE_STATUS__LINESTATE"/>
        </register>
        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
        </register>
        <register name="FNUM" offset="0x10" rw="R" size="2" initval="0x0000" caption="DEVICE Device Frame Number">
          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
          <bitfield name="FNCERR" caption="Frame Number CRC Error" mask="0x8000"/>
        </register>
        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="DEVICE Device Interrupt Enable Clear">
          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
        </register>
        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="DEVICE Device Interrupt Enable Set">
          <bitfield name="SUSPEND" caption="Suspend Interrupt Enable" mask="0x1"/>
          <bitfield name="MSOF" caption="Micro Start of Frame Interrupt Enable in High Speed Mode" mask="0x2"/>
          <bitfield name="SOF" caption="Start Of Frame Interrupt Enable" mask="0x4"/>
          <bitfield name="EORST" caption="End of Reset Interrupt Enable" mask="0x8"/>
          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
          <bitfield name="EORSM" caption="End Of Resume Interrupt Enable" mask="0x20"/>
          <bitfield name="UPRSM" caption="Upstream Resume Interrupt Enable" mask="0x40"/>
          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
          <bitfield name="LPMNYET" caption="Link Power Management Not Yet Interrupt Enable" mask="0x100"/>
          <bitfield name="LPMSUSP" caption="Link Power Management Suspend Interrupt Enable" mask="0x200"/>
        </register>
        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="DEVICE Device Interrupt Flag">
          <bitfield name="SUSPEND" caption="Suspend" mask="0x1"/>
          <bitfield name="MSOF" caption="Micro Start of Frame in High Speed Mode" mask="0x2"/>
          <bitfield name="SOF" caption="Start Of Frame" mask="0x4"/>
          <bitfield name="EORST" caption="End of Reset" mask="0x8"/>
          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
          <bitfield name="EORSM" caption="End Of Resume" mask="0x20"/>
          <bitfield name="UPRSM" caption="Upstream Resume" mask="0x40"/>
          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
          <bitfield name="LPMNYET" caption="Link Power Management Not Yet" mask="0x100"/>
          <bitfield name="LPMSUSP" caption="Link Power Management Suspend" mask="0x200"/>
        </register>
        <register name="EPINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="DEVICE End Point Interrupt Summary">
          <bitfield name="EPINT0" caption="End Point 0 Interrupt" mask="0x1"/>
          <bitfield name="EPINT1" caption="End Point 1 Interrupt" mask="0x2"/>
          <bitfield name="EPINT2" caption="End Point 2 Interrupt" mask="0x4"/>
          <bitfield name="EPINT3" caption="End Point 3 Interrupt" mask="0x8"/>
          <bitfield name="EPINT4" caption="End Point 4 Interrupt" mask="0x10"/>
          <bitfield name="EPINT5" caption="End Point 5 Interrupt" mask="0x20"/>
          <bitfield name="EPINT6" caption="End Point 6 Interrupt" mask="0x40"/>
          <bitfield name="EPINT7" caption="End Point 7 Interrupt" mask="0x80"/>
        </register>
        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
        </register>
        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
        </register>
        <register-group name="DEVICE_ENDPOINT" name-in-module="DEVICE_ENDPOINT" offset="0x100" count="8"/>
      </register-group>
      <register-group name="USB_DEVICE_DESCRIPTOR" caption="Universal Serial Bus - USB is Device">
        <register-group name="DEVICE_DESC_BANK" name-in-module="DEVICE_DESC_BANK" offset="0x000" count="2"/>
      </register-group>
      <register-group name="USB_HOST" caption="Universal Serial Bus - USB is Host">
        <register name="CTRLA" offset="0x0" rw="RW" size="1" initval="0x00" caption="Control A">
          <bitfield name="SWRST" caption="Software Reset" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="RUNSTDBY" caption="Run in Standby Mode" mask="0x4"/>
          <bitfield name="MODE" caption="Operating Mode" mask="0x80" values="USB_CTRLA__MODE"/>
        </register>
        <register name="SYNCBUSY" offset="0x2" rw="R" size="1" initval="0x00" caption="Synchronization Busy">
          <bitfield name="SWRST" caption="Software Reset Synchronization Busy" mask="0x1"/>
          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
        </register>
        <register name="QOSCTRL" offset="0x3" rw="RW" size="1" initval="0x0F" caption="USB Quality Of Service">
          <bitfield name="CQOS" caption="Configuration Quality of Service" mask="0x3"/>
          <bitfield name="DQOS" caption="Data Quality of Service" mask="0xC"/>
        </register>
        <register name="CTRLB" offset="0x8" rw="RW" size="2" initval="0x0000" caption="HOST Control B">
          <bitfield name="RESUME" caption="Send USB Resume" mask="0x2"/>
          <bitfield name="SPDCONF" caption="Speed Configuration for Host" mask="0xC" values="USB_HOST_CTRLB__SPDCONF"/>
          <bitfield name="AUTORESUME" caption="Auto Resume Enable" mask="0x10"/>
          <bitfield name="TSTJ" caption="Test mode J" mask="0x20"/>
          <bitfield name="TSTK" caption="Test mode K" mask="0x40"/>
          <bitfield name="SOFE" caption="Start of Frame Generation Enable" mask="0x100"/>
          <bitfield name="BUSRESET" caption="Send USB Reset" mask="0x200"/>
          <bitfield name="VBUSOK" caption="VBUS is OK" mask="0x400"/>
          <bitfield name="L1RESUME" caption="Send L1 Resume" mask="0x800"/>
        </register>
        <register name="HSOFC" offset="0xA" rw="RW" size="1" initval="0x00" caption="HOST Host Start Of Frame Control">
          <bitfield name="FLENC" caption="Frame Length Control" mask="0xF"/>
          <bitfield name="FLENCE" caption="Frame Length Control Enable" mask="0x80"/>
        </register>
        <register name="STATUS" offset="0xC" rw="RW" size="1" initval="0x00" caption="HOST Status">
          <bitfield name="SPEED" caption="Speed Status" mask="0xC"/>
          <bitfield name="LINESTATE" caption="USB Line State Status" mask="0xC0"/>
        </register>
        <register name="FSMSTATUS" offset="0xD" rw="R" size="1" initval="0x01" caption="Finite State Machine Status">
          <bitfield name="FSMSTATE" caption="Fine State Machine Status" mask="0x7F" values="USB_FSMSTATUS__FSMSTATE"/>
        </register>
        <register name="FNUM" offset="0x10" rw="RW" size="2" initval="0x0000" caption="HOST Host Frame Number">
          <bitfield name="MFNUM" caption="Micro Frame Number" mask="0x7"/>
          <bitfield name="FNUM" caption="Frame Number" mask="0x3FF8"/>
        </register>
        <register name="FLENHIGH" offset="0x12" rw="R" size="1" initval="0x00" caption="HOST Host Frame Length">
          <bitfield name="FLENHIGH" caption="Frame Length" mask="0xFF"/>
        </register>
        <register name="INTENCLR" offset="0x14" rw="RW" size="2" atomic-op="clear:INTENCLR" initval="0x0000" caption="HOST Host Interrupt Enable Clear">
          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Disable" mask="0x4"/>
          <bitfield name="RST" caption="BUS Reset Interrupt Disable" mask="0x8"/>
          <bitfield name="WAKEUP" caption="Wake Up Interrupt Disable" mask="0x10"/>
          <bitfield name="DNRSM" caption="DownStream to Device Interrupt Disable" mask="0x20"/>
          <bitfield name="UPRSM" caption="Upstream Resume from Device Interrupt Disable" mask="0x40"/>
          <bitfield name="RAMACER" caption="Ram Access Interrupt Disable" mask="0x80"/>
          <bitfield name="DCONN" caption="Device Connection Interrupt Disable" mask="0x100"/>
          <bitfield name="DDISC" caption="Device Disconnection Interrupt Disable" mask="0x200"/>
        </register>
        <register name="INTENSET" offset="0x18" rw="RW" size="2" atomic-op="set:INTENSET" initval="0x0000" caption="HOST Host Interrupt Enable Set">
          <bitfield name="HSOF" caption="Host Start Of Frame Interrupt Enable" mask="0x4"/>
          <bitfield name="RST" caption="Bus Reset Interrupt Enable" mask="0x8"/>
          <bitfield name="WAKEUP" caption="Wake Up Interrupt Enable" mask="0x10"/>
          <bitfield name="DNRSM" caption="DownStream to the Device Interrupt Enable" mask="0x20"/>
          <bitfield name="UPRSM" caption="Upstream Resume fromthe device Interrupt Enable" mask="0x40"/>
          <bitfield name="RAMACER" caption="Ram Access Interrupt Enable" mask="0x80"/>
          <bitfield name="DCONN" caption="Link Power Management Interrupt Enable" mask="0x100"/>
          <bitfield name="DDISC" caption="Device Disconnection Interrupt Enable" mask="0x200"/>
        </register>
        <register name="INTFLAG" offset="0x1C" rw="RW" size="2" atomic-op="clear:INTFLAG" initval="0x0000" caption="HOST Host Interrupt Flag">
          <bitfield name="HSOF" caption="Host Start Of Frame" mask="0x4"/>
          <bitfield name="RST" caption="Bus Reset" mask="0x8"/>
          <bitfield name="WAKEUP" caption="Wake Up" mask="0x10"/>
          <bitfield name="DNRSM" caption="Downstream" mask="0x20"/>
          <bitfield name="UPRSM" caption="Upstream Resume from the Device" mask="0x40"/>
          <bitfield name="RAMACER" caption="Ram Access" mask="0x80"/>
          <bitfield name="DCONN" caption="Device Connection" mask="0x100"/>
          <bitfield name="DDISC" caption="Device Disconnection" mask="0x200"/>
        </register>
        <register name="PINTSMRY" offset="0x20" rw="R" size="2" initval="0x0000" caption="HOST Pipe Interrupt Summary">
          <bitfield name="EPINT0" caption="Pipe 0 Interrupt" mask="0x1"/>
          <bitfield name="EPINT1" caption="Pipe 1 Interrupt" mask="0x2"/>
          <bitfield name="EPINT2" caption="Pipe 2 Interrupt" mask="0x4"/>
          <bitfield name="EPINT3" caption="Pipe 3 Interrupt" mask="0x8"/>
          <bitfield name="EPINT4" caption="Pipe 4 Interrupt" mask="0x10"/>
          <bitfield name="EPINT5" caption="Pipe 5 Interrupt" mask="0x20"/>
          <bitfield name="EPINT6" caption="Pipe 6 Interrupt" mask="0x40"/>
          <bitfield name="EPINT7" caption="Pipe 7 Interrupt" mask="0x80"/>
        </register>
        <register name="DESCADD" offset="0x24" rw="RW" size="4" initval="0x00000000" caption="Descriptor Address">
          <bitfield name="DESCADD" caption="Descriptor Address Value" mask="0xFFFFFFFF"/>
        </register>
        <register name="PADCAL" offset="0x28" rw="RW" size="2" initval="0x0000" caption="USB PAD Calibration">
          <bitfield name="TRANSP" caption="USB Pad Transp calibration" mask="0x1F"/>
          <bitfield name="TRANSN" caption="USB Pad Transn calibration" mask="0x7C0"/>
          <bitfield name="TRIM" caption="USB Pad Trim calibration" mask="0x7000"/>
        </register>
        <register-group name="HOST_PIPE" name-in-module="HOST_PIPE" offset="0x100" count="8"/>
      </register-group>
      <register-group name="USB_HOST_DESCRIPTOR" caption="Universal Serial Bus - USB is Host">
        <register-group name="HOST_DESC_BANK" name-in-module="HOST_DESC_BANK" offset="0x000" count="2"/>
      </register-group>
      <value-group name="USB_CTRLA__MODE">
        <value name="DEVICE" caption="Device Mode" value="0"/>
        <value name="HOST" caption="Host Mode" value="1"/>
      </value-group>
      <value-group name="USB_DEVICE_CTRLB__LPMHDSK">
        <value name="NO" caption="No handshake. LPM is not supported" value="0"/>
        <value name="ACK" caption="ACK" value="1"/>
        <value name="NYET" caption="NYET" value="2"/>
        <value name="STALL" caption="STALL" value="3"/>
      </value-group>
      <value-group name="USB_DEVICE_CTRLB__SPDCONF">
        <value name="FS" caption="FS : Full Speed" value="0x0"/>
        <value name="LS" caption="LS : Low Speed" value="0x1"/>
        <value name="HS" caption="HS : High Speed capable" value="0x2"/>
        <value name="HSTM" caption="HSTM: High Speed Test Mode (force high-speed mode for test mode)" value="0x3"/>
      </value-group>
      <value-group name="USB_HOST_CTRLB__SPDCONF">
        <value name="NORMAL" caption="Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable." value="0x0"/>
        <value name="FS" caption="Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only." value="0x3"/>
      </value-group>
      <value-group name="USB_DEVICE_STATUS__LINESTATE">
        <value name="0" caption="SE0/RESET" value="0x0"/>
        <value name="1" caption="FS-J or LS-K State" value="0x1"/>
        <value name="2" caption="FS-K or LS-J State" value="0x2"/>
      </value-group>
      <value-group name="USB_DEVICE_STATUS__SPEED">
        <value name="FS" caption="Full-speed mode" value="0x0"/>
        <value name="LS" caption="Low-speed mode" value="0x1"/>
        <value name="HS" caption="High-speed mode" value="0x2"/>
      </value-group>
      <value-group name="USB_FSMSTATUS__FSMSTATE">
        <value name="OFF" caption="OFF (L3). It corresponds to the powered-off, disconnected, and disabled state" value="0x1"/>
        <value name="ON" caption="ON (L0). It corresponds to the Idle and Active states" value="0x2"/>
        <value name="SUSPEND" caption="SUSPEND (L2)" value="0x4"/>
        <value name="SLEEP" caption="SLEEP (L1)" value="0x8"/>
        <value name="DNRESUME" caption="DNRESUME. Down Stream Resume." value="0x10"/>
        <value name="UPRESUME" caption="UPRESUME. Up Stream Resume." value="0x20"/>
        <value name="RESET" caption="RESET. USB lines Reset." value="0x40"/>
      </value-group>
    </module>
    <module name="WDT" id="U2251" version="1.1.0" caption="Watchdog Timer">
      <register-group name="WDT" caption="Watchdog Timer">
        <register name="CTRLA" offset="0x0" rw="RW" access="WSYNC" size="1" initval="0x00" caption="Control">
          <bitfield name="ENABLE" caption="Enable" mask="0x2"/>
          <bitfield name="WEN" caption="Watchdog Timer Window Mode Enable" mask="0x4"/>
          <bitfield name="ALWAYSON" caption="Always-On" mask="0x80"/>
        </register>
        <register name="CONFIG" offset="0x1" rw="RW" size="1" initval="0xBB" caption="Configuration">
          <bitfield name="PER" caption="Time-Out Period" mask="0xF" values="WDT_CONFIG__PER"/>
          <bitfield name="WINDOW" caption="Window Mode Time-Out Period" mask="0xF0" values="WDT_CONFIG__WINDOW"/>
        </register>
        <register name="EWCTRL" offset="0x2" rw="RW" size="1" initval="0x0B" caption="Early Warning Interrupt Control">
          <bitfield name="EWOFFSET" caption="Early Warning Interrupt Time Offset" mask="0xF" values="WDT_EWCTRL__EWOFFSET"/>
        </register>
        <register name="INTENCLR" offset="0x4" rw="RW" size="1" atomic-op="clear:INTENCLR" initval="0x00" caption="Interrupt Enable Clear">
          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
        </register>
        <register name="INTENSET" offset="0x5" rw="RW" size="1" atomic-op="set:INTENSET" initval="0x00" caption="Interrupt Enable Set">
          <bitfield name="EW" caption="Early Warning Interrupt Enable" mask="0x1"/>
        </register>
        <register name="INTFLAG" offset="0x6" rw="RW" size="1" atomic-op="clear:INTFLAG" initval="0x00" caption="Interrupt Flag Status and Clear">
          <bitfield name="EW" caption="Early Warning" mask="0x1"/>
        </register>
        <register name="SYNCBUSY" offset="0x8" rw="R" size="4" initval="0x00000000" caption="Synchronization Busy">
          <bitfield name="ENABLE" caption="Enable Synchronization Busy" mask="0x2"/>
          <bitfield name="WEN" caption="Window Enable Synchronization Busy" mask="0x4"/>
          <bitfield name="ALWAYSON" caption="Always-On Synchronization Busy" mask="0x8"/>
          <bitfield name="CLEAR" caption="Clear Synchronization Busy" mask="0x10"/>
        </register>
        <register name="CLEAR" offset="0xC" rw="W" access="WSYNC" size="1" initval="0x00" caption="Clear">
          <bitfield name="CLEAR" caption="Watchdog Clear" mask="0xFF" values="WDT_CLEAR__CLEAR"/>
        </register>
      </register-group>
      <value-group name="WDT_CONFIG__PER">
        <value name="CYC8" caption="8 clock cycles" value="0x0"/>
        <value name="CYC16" caption="16 clock cycles" value="0x1"/>
        <value name="CYC32" caption="32 clock cycles" value="0x2"/>
        <value name="CYC64" caption="64 clock cycles" value="0x3"/>
        <value name="CYC128" caption="128 clock cycles" value="0x4"/>
        <value name="CYC256" caption="256 clock cycles" value="0x5"/>
        <value name="CYC512" caption="512 clock cycles" value="0x6"/>
        <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
        <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
        <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
        <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
        <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
      </value-group>
      <value-group name="WDT_CONFIG__WINDOW">
        <value name="CYC8" caption="8 clock cycles" value="0x0"/>
        <value name="CYC16" caption="16 clock cycles" value="0x1"/>
        <value name="CYC32" caption="32 clock cycles" value="0x2"/>
        <value name="CYC64" caption="64 clock cycles" value="0x3"/>
        <value name="CYC128" caption="128 clock cycles" value="0x4"/>
        <value name="CYC256" caption="256 clock cycles" value="0x5"/>
        <value name="CYC512" caption="512 clock cycles" value="0x6"/>
        <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
        <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
        <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
        <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
        <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
      </value-group>
      <value-group name="WDT_EWCTRL__EWOFFSET">
        <value name="CYC8" caption="8 clock cycles" value="0x0"/>
        <value name="CYC16" caption="16 clock cycles" value="0x1"/>
        <value name="CYC32" caption="32 clock cycles" value="0x2"/>
        <value name="CYC64" caption="64 clock cycles" value="0x3"/>
        <value name="CYC128" caption="128 clock cycles" value="0x4"/>
        <value name="CYC256" caption="256 clock cycles" value="0x5"/>
        <value name="CYC512" caption="512 clock cycles" value="0x6"/>
        <value name="CYC1024" caption="1024 clock cycles" value="0x7"/>
        <value name="CYC2048" caption="2048 clock cycles" value="0x8"/>
        <value name="CYC4096" caption="4096 clock cycles" value="0x9"/>
        <value name="CYC8192" caption="8192 clock cycles" value="0xA"/>
        <value name="CYC16384" caption="16384 clock cycles" value="0xB"/>
      </value-group>
      <value-group name="WDT_CLEAR__CLEAR">
        <value name="KEY" caption="Clear Key" value="0xA5"/>
      </value-group>
    </module>
  <module name="SystemControl" caption="System Control Registers">
            <register-group name="SystemControl" caption="System Control Registers">
                <register offset="0x00000008" size="4" name="ACTLR" initval="0" caption="Auxiliary Control Register,">
                    <bitfield mask="0x00000001" name="DISMCYCINT" caption="Disables interruption of multi-cycle instructions."/>
                    <bitfield mask="0x00000002" name="DISDEFWBUF" caption="Disables write buffer use during default memory map accesses."/>
                    <bitfield mask="0x00000004" name="DISFOLD" caption="Disables folding of IT instructions."/>
                </register>
                <register offset="0x00000d00" size="4" name="CPUID" initval="0x410FC240" caption="CPUID Base Register">
                    <bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
                    <bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
                    <bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
                    <bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
                </register>
                <register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
                    <bitfield mask="0x000001ff" name="VECTACTIVE" caption="Active exception number"/>
                    <bitfield mask="0x00000800" name="RETTOBASE" values="RETTOBASE" caption="no description available"/>
                    <bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
                    <bitfield mask="0x00400000" name="ISRPENDING" caption="no description available"/>
                    <bitfield mask="0x00800000" name="ISRPREEMPT" values="ISRPREEMPT" caption="no description available"/>
                    <bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
                    <bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
                    <bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
                    <bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
                    <bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
                </register>
                <register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
                    <bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
                </register>
                <register offset="0x00000d0c" size="4" name="AIRCR" initval="0" caption="Application Interrupt and Reset Control Register">
                    <bitfield mask="0x00000001" name="VECTRESET" caption="no description available"/>
                    <bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
                    <bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
                    <bitfield mask="0x00000700" name="PRIGROUP" caption="Interrupt priority grouping field. This field determines the split of group priority from subpriority."/>
                    <bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
                    <bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
                </register>
                <register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
                    <bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
                    <bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
                    <bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
                </register>
                <register offset="0x00000d14" size="4" name="CCR" initval="0" caption="Configuration and Control Register">
                    <bitfield mask="0x00000001" name="NONBASETHRDENA" values="NONBASETHRDENA" caption="no description available"/>
                    <bitfield mask="0x00000002" name="USERSETMPEND" values="USERSETMPEND" caption="Enables unprivileged software access to the STIR"/>
                    <bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
                    <bitfield mask="0x00000010" name="DIV_0_TRP" values="DIV_0_TRP" caption="Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0"/>
                    <bitfield mask="0x00000100" name="BFHFNMIGN" values="BFHFNMIGN" caption="Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions."/>
                    <bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
                </register>
                <register offset="0x00000d18" size="4" name="SHPR1" initval="0" caption="System Handler Priority Register 1">
                    <bitfield mask="0x000000ff" name="PRI_4" caption="Priority of system handler 4, MemManage"/>
                    <bitfield mask="0x0000ff00" name="PRI_5" caption="Priority of system handler 5, BusFault"/>
                    <bitfield mask="0x00ff0000" name="PRI_6" caption="Priority of system handler 6, UsageFault"/>
                </register>
                <register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
                    <bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
                </register>
                <register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
                    <bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
                    <bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
                </register>
                <register offset="0x00000d24" size="4" name="SHCSR" initval="0" caption="System Handler Control and State Register">
                    <bitfield mask="0x00000001" name="MEMFAULTACT" values="MEMFAULTACT" caption="no description available"/>
                    <bitfield mask="0x00000002" name="BUSFAULTACT" values="BUSFAULTACT" caption="no description available"/>
                    <bitfield mask="0x00000008" name="USGFAULTACT" values="USGFAULTACT" caption="no description available"/>
                    <bitfield mask="0x00000080" name="SVCALLACT" values="SVCALLACT" caption="no description available"/>
                    <bitfield mask="0x00000100" name="MONITORACT" values="MONITORACT" caption="no description available"/>
                    <bitfield mask="0x00000400" name="PENDSVACT" values="PENDSVACT" caption="no description available"/>
                    <bitfield mask="0x00000800" name="SYSTICKACT" values="SYSTICKACT" caption="no description available"/>
                    <bitfield mask="0x00001000" name="USGFAULTPENDED" values="USGFAULTPENDED" caption="no description available"/>
                    <bitfield mask="0x00002000" name="MEMFAULTPENDED" values="MEMFAULTPENDED" caption="no description available"/>
                    <bitfield mask="0x00004000" name="BUSFAULTPENDED" values="BUSFAULTPENDED" caption="no description available"/>
                    <bitfield mask="0x00008000" name="SVCALLPENDED" values="SVCALLPENDED" caption="no description available"/>
                    <bitfield mask="0x00010000" name="MEMFAULTENA" values="MEMFAULTENA" caption="no description available"/>
                    <bitfield mask="0x00020000" name="BUSFAULTENA" values="BUSFAULTENA" caption="no description available"/>
                    <bitfield mask="0x00040000" name="USGFAULTENA" values="USGFAULTENA" caption="no description available"/>
                </register>
                <register offset="0x00000d28" size="4" name="CFSR" initval="0" caption="Configurable Fault Status Registers">
                    <bitfield mask="0x00000001" name="IACCVIOL" values="IACCVIOL" caption="no description available"/>
                    <bitfield mask="0x00000002" name="DACCVIOL" values="DACCVIOL" caption="no description available"/>
                    <bitfield mask="0x00000008" name="MUNSTKERR" values="MUNSTKERR" caption="no description available"/>
                    <bitfield mask="0x00000010" name="MSTKERR" values="MSTKERR" caption="no description available"/>
                    <bitfield mask="0x00000020" name="MLSPERR" values="MLSPERR" caption="no description available"/>
                    <bitfield mask="0x00000080" name="MMARVALID" values="MMARVALID" caption="no description available"/>
                    <bitfield mask="0x00000100" name="IBUSERR" values="IBUSERR" caption="no description available"/>
                    <bitfield mask="0x00000200" name="PRECISERR" values="PRECISERR" caption="no description available"/>
                    <bitfield mask="0x00000400" name="IMPRECISERR" values="IMPRECISERR" caption="no description available"/>
                    <bitfield mask="0x00000800" name="UNSTKERR" values="UNSTKERR" caption="no description available"/>
                    <bitfield mask="0x00001000" name="STKERR" values="STKERR" caption="no description available"/>
                    <bitfield mask="0x00002000" name="LSPERR" values="LSPERR" caption="no description available"/>
                    <bitfield mask="0x00008000" name="BFARVALID" values="BFARVALID" caption="no description available"/>
                    <bitfield mask="0x00010000" name="UNDEFINSTR" values="UNDEFINSTR" caption="no description available"/>
                    <bitfield mask="0x00020000" name="INVSTATE" values="INVSTATE" caption="no description available"/>
                    <bitfield mask="0x00040000" name="INVPC" values="INVPC" caption="no description available"/>
                    <bitfield mask="0x00080000" name="NOCP" values="NOCP" caption="no description available"/>
                    <bitfield mask="0x01000000" name="UNALIGNED" values="UNALIGNED" caption="no description available"/>
                    <bitfield mask="0x02000000" name="DIVBYZERO" values="DIVBYZERO" caption="no description available"/>
                </register>
                <register offset="0x00000d2c" size="4" name="HFSR" initval="0" caption="HardFault Status register">
                    <bitfield mask="0x00000002" name="VECTTBL" values="VECTTBL" caption="no description available"/>
                    <bitfield mask="0x40000000" name="FORCED" values="FORCED" caption="no description available"/>
                    <bitfield mask="0x80000000" name="DEBUGEVT" caption="no description available"/>
                </register>
                <register offset="0x00000d30" size="4" name="DFSR" initval="0" caption="Debug Fault Status Register">
                    <bitfield mask="0x00000001" name="HALTED" values="HALTED" caption="no description available"/>
                    <bitfield mask="0x00000002" name="BKPT" values="BKPT" caption="no description available"/>
                    <bitfield mask="0x00000004" name="DWTTRAP" values="DWTTRAP" caption="no description available"/>
                    <bitfield mask="0x00000008" name="VCATCH" values="VCATCH" caption="no description available"/>
                    <bitfield mask="0x00000010" name="EXTERNAL" values="EXTERNAL" caption="no description available"/>
                </register>
                <register offset="0x00000d34" size="4" name="MMFAR" initval="0" caption="MemManage Address Register">
                    <bitfield mask="0xffffffff" name="ADDRESS" caption="Address of MemManage fault location"/>
                </register>
                <register offset="0x00000d38" size="4" name="BFAR" initval="0" caption="BusFault Address Register">
                    <bitfield mask="0xffffffff" name="ADDRESS" caption="Address of the BusFault location"/>
                </register>
                <register offset="0x00000d3c" size="4" name="AFSR" initval="0" caption="Auxiliary Fault Status Register">
                    <bitfield mask="0xffffffff" name="AUXFAULT" caption="Latched version of the AUXFAULT inputs"/>
                </register>
            </register-group>
            <value-group name="RETTOBASE">
                <value value="0" name="VALUE_0" caption="there are preempted active exceptions to execute"/>
                <value value="1" name="VALUE_1" caption="there are no active exceptions, or the currently-executing exception is the only active exception"/>
            </value-group>
            <value-group name="ISRPREEMPT">
                <value value="0" name="VALUE_0" caption="Will not service"/>
                <value value="1" name="VALUE_1" caption="Will service a pending exception"/>
            </value-group>
            <value-group name="PENDSTCLR">
                <value value="0" name="VALUE_0" caption="no effect"/>
                <value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
            </value-group>
            <value-group name="PENDSTSET">
                <value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
                <value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
            </value-group>
            <value-group name="PENDSVCLR">
                <value value="0" name="VALUE_0" caption="no effect"/>
                <value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
            </value-group>
            <value-group name="PENDSVSET">
                <value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
                <value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
            </value-group>
            <value-group name="NMIPENDSET">
                <value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
                <value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
            </value-group>
            <value-group name="SYSRESETREQ">
                <value value="0" name="VALUE_0" caption="no system reset request"/>
                <value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
            </value-group>
            <value-group name="ENDIANNESS">
                <value value="0" name="VALUE_0" caption="Little-endian"/>
                <value value="1" name="VALUE_1" caption="Big-endian"/>
            </value-group>
            <value-group name="SLEEPONEXIT">
                <value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
                <value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
            </value-group>
            <value-group name="SLEEPDEEP">
                <value value="0" name="VALUE_0" caption="sleep"/>
                <value value="1" name="VALUE_1" caption="deep sleep"/>
            </value-group>
            <value-group name="SEVONPEND">
                <value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
                <value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
            </value-group>
            <value-group name="NONBASETHRDENA">
                <value value="0" name="VALUE_0" caption="processor can enter Thread mode only when no exception is active"/>
                <value value="1" name="VALUE_1" caption="processor can enter Thread mode from any level under the control of an EXC_RETURN value"/>
            </value-group>
            <value-group name="USERSETMPEND">
                <value value="0" name="VALUE_0" caption="disable"/>
                <value value="1" name="VALUE_1" caption="enable"/>
            </value-group>
            <value-group name="UNALIGN_TRP">
                <value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
                <value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
            </value-group>
            <value-group name="DIV_0_TRP">
                <value value="0" name="VALUE_0" caption="do not trap divide by 0"/>
                <value value="1" name="VALUE_1" caption="trap divide by 0"/>
            </value-group>
            <value-group name="BFHFNMIGN">
                <value value="0" name="VALUE_0" caption="data bus faults caused by load and store instructions cause a lock-up"/>
                <value value="1" name="VALUE_1" caption="handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions"/>
            </value-group>
            <value-group name="STKALIGN">
                <value value="0" name="VALUE_0" caption="4-byte aligned"/>
                <value value="1" name="VALUE_1" caption="8-byte aligned"/>
            </value-group>
            <value-group name="MEMFAULTACT">
                <value value="0" name="VALUE_0" caption="exception is not active"/>
                <value value="1" name="VALUE_1" caption="exception is active"/>
            </value-group>
            <value-group name="BUSFAULTACT">
                <value value="0" name="VALUE_0" caption="exception is not active"/>
                <value value="1" name="VALUE_1" caption="exception is active"/>
            </value-group>
            <value-group name="USGFAULTACT">
                <value value="0" name="VALUE_0" caption="exception is not active"/>
                <value value="1" name="VALUE_1" caption="exception is active"/>
            </value-group>
            <value-group name="SVCALLACT">
                <value value="0" name="VALUE_0" caption="exception is not active"/>
                <value value="1" name="VALUE_1" caption="exception is active"/>
            </value-group>
            <value-group name="MONITORACT">
                <value value="0" name="VALUE_0" caption="exception is not active"/>
                <value value="1" name="VALUE_1" caption="exception is active"/>
            </value-group>
            <value-group name="PENDSVACT">
                <value value="0" name="VALUE_0" caption="exception is not active"/>
                <value value="1" name="VALUE_1" caption="exception is active"/>
            </value-group>
            <value-group name="SYSTICKACT">
                <value value="0" name="VALUE_0" caption="exception is not active"/>
                <value value="1" name="VALUE_1" caption="exception is active"/>
            </value-group>
            <value-group name="USGFAULTPENDED">
                <value value="0" name="VALUE_0" caption="exception is not pending"/>
                <value value="1" name="VALUE_1" caption="exception is pending"/>
            </value-group>
            <value-group name="MEMFAULTPENDED">
                <value value="0" name="VALUE_0" caption="exception is not pending"/>
                <value value="1" name="VALUE_1" caption="exception is pending"/>
            </value-group>
            <value-group name="BUSFAULTPENDED">
                <value value="0" name="VALUE_0" caption="exception is not pending"/>
                <value value="1" name="VALUE_1" caption="exception is pending"/>
            </value-group>
            <value-group name="SVCALLPENDED">
                <value value="0" name="VALUE_0" caption="exception is not pending"/>
                <value value="1" name="VALUE_1" caption="exception is pending"/>
            </value-group>
            <value-group name="MEMFAULTENA">
                <value value="0" name="VALUE_0" caption="disable the exception"/>
                <value value="1" name="VALUE_1" caption="enable the exception"/>
            </value-group>
            <value-group name="BUSFAULTENA">
                <value value="0" name="VALUE_0" caption="disable the exception"/>
                <value value="1" name="VALUE_1" caption="enable the exception"/>
            </value-group>
            <value-group name="USGFAULTENA">
                <value value="0" name="VALUE_0" caption="disable the exception"/>
                <value value="1" name="VALUE_1" caption="enable the exception"/>
            </value-group>
            <value-group name="IACCVIOL">
                <value value="0" name="VALUE_0" caption="no instruction access violation fault"/>
                <value value="1" name="VALUE_1" caption="the processor attempted an instruction fetch from a location that does not permit execution"/>
            </value-group>
            <value-group name="DACCVIOL">
                <value value="0" name="VALUE_0" caption="no data access violation fault"/>
                <value value="1" name="VALUE_1" caption="the processor attempted a load or store at a location that does not permit the operation"/>
            </value-group>
            <value-group name="MUNSTKERR">
                <value value="0" name="VALUE_0" caption="no unstacking fault"/>
                <value value="1" name="VALUE_1" caption="unstack for an exception return has caused one or more access violations"/>
            </value-group>
            <value-group name="MSTKERR">
                <value value="0" name="VALUE_0" caption="no stacking fault"/>
                <value value="1" name="VALUE_1" caption="stacking for an exception entry has caused one or more access violations"/>
            </value-group>
            <value-group name="MLSPERR">
                <value value="0" name="VALUE_0" caption="No MemManage fault occurred during floating-point lazy state preservation"/>
                <value value="1" name="VALUE_1" caption="A MemManage fault occurred during floating-point lazy state preservation"/>
            </value-group>
            <value-group name="MMARVALID">
                <value value="0" name="VALUE_0" caption="value in MMAR is not a valid fault address"/>
                <value value="1" name="VALUE_1" caption="MMAR holds a valid fault address"/>
            </value-group>
            <value-group name="IBUSERR">
                <value value="0" name="VALUE_0" caption="no instruction bus error"/>
                <value value="1" name="VALUE_1" caption="instruction bus error"/>
            </value-group>
            <value-group name="PRECISERR">
                <value value="0" name="VALUE_0" caption="no precise data bus error"/>
                <value value="1" name="VALUE_1" caption="a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault"/>
            </value-group>
            <value-group name="IMPRECISERR">
                <value value="0" name="VALUE_0" caption="no imprecise data bus error"/>
                <value value="1" name="VALUE_1" caption="a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error"/>
            </value-group>
            <value-group name="UNSTKERR">
                <value value="0" name="VALUE_0" caption="no unstacking fault"/>
                <value value="1" name="VALUE_1" caption="unstack for an exception return has caused one or more BusFaults"/>
            </value-group>
            <value-group name="STKERR">
                <value value="0" name="VALUE_0" caption="no stacking fault"/>
                <value value="1" name="VALUE_1" caption="stacking for an exception entry has caused one or more BusFaults"/>
            </value-group>
            <value-group name="LSPERR">
                <value value="0" name="VALUE_0" caption="No bus fault occurred during floating-point lazy state preservation"/>
                <value value="1" name="VALUE_1" caption="A bus fault occurred during floating-point lazy state preservation"/>
            </value-group>
            <value-group name="BFARVALID">
                <value value="0" name="VALUE_0" caption="value in BFAR is not a valid fault address"/>
                <value value="1" name="VALUE_1" caption="BFAR holds a valid fault address"/>
            </value-group>
            <value-group name="UNDEFINSTR">
                <value value="0" name="VALUE_0" caption="no undefined instruction UsageFault"/>
                <value value="1" name="VALUE_1" caption="the processor has attempted to execute an undefined instruction"/>
            </value-group>
            <value-group name="INVSTATE">
                <value value="0" name="VALUE_0" caption="no invalid state UsageFault"/>
                <value value="1" name="VALUE_1" caption="the processor has attempted to execute an instruction that makes illegal use of the EPSR"/>
            </value-group>
            <value-group name="INVPC">
                <value value="0" name="VALUE_0" caption="no invalid PC load UsageFault"/>
                <value value="1" name="VALUE_1" caption="the processor has attempted an illegal load of EXC_RETURN to the PC"/>
            </value-group>
            <value-group name="NOCP">
                <value value="0" name="VALUE_0" caption="no UsageFault caused by attempting to access a coprocessor"/>
                <value value="1" name="VALUE_1" caption="the processor has attempted to access a coprocessor"/>
            </value-group>
            <value-group name="UNALIGNED">
                <value value="0" name="VALUE_0" caption="no unaligned access fault, or unaligned access trapping not enabled"/>
                <value value="1" name="VALUE_1" caption="the processor has made an unaligned memory access"/>
            </value-group>
            <value-group name="DIVBYZERO">
                <value value="0" name="VALUE_0" caption="no divide by zero fault, or divide by zero trapping not enabled"/>
                <value value="1" name="VALUE_1" caption="the processor has executed an SDIV or UDIV instruction with a divisor of 0"/>
            </value-group>
            <value-group name="VECTTBL">
                <value value="0" name="VALUE_0" caption="no BusFault on vector table read"/>
                <value value="1" name="VALUE_1" caption="BusFault on vector table read"/>
            </value-group>
            <value-group name="FORCED">
                <value value="0" name="VALUE_0" caption="no forced HardFault"/>
                <value value="1" name="VALUE_1" caption="forced HardFault"/>
            </value-group>
            <value-group name="HALTED">
                <value value="0" name="VALUE_0" caption="No active halt request debug event"/>
                <value value="1" name="VALUE_1" caption="Halt request debug event active"/>
            </value-group>
            <value-group name="BKPT">
                <value value="0" name="VALUE_0" caption="No current breakpoint debug event"/>
                <value value="1" name="VALUE_1" caption="At least one current breakpoint debug event"/>
            </value-group>
            <value-group name="DWTTRAP">
                <value value="0" name="VALUE_0" caption="No current debug events generated by the DWT"/>
                <value value="1" name="VALUE_1" caption="At least one current debug event generated by the DWT"/>
            </value-group>
            <value-group name="VCATCH">
                <value value="0" name="VALUE_0" caption="No Vector catch triggered"/>
                <value value="1" name="VALUE_1" caption="Vector catch triggered"/>
            </value-group>
            <value-group name="EXTERNAL">
                <value value="0" name="VALUE_0" caption="No EDBGRQ debug event"/>
                <value value="1" name="VALUE_1" caption="EDBGRQ debug event"/>
            </value-group>
        </module><module name="SysTick" caption="System timer">
            <register-group name="SysTick" caption="System timer">
                <register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
                    <bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
                    <bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
                    <bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
                    <bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
                </register>
                <register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
                    <bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
                </register>
                <register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
                    <bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
                </register>
                <register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
                    <bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
                    <bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
                    <bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
                </register>
            </register-group>
            <value-group name="ENABLE">
                <value value="0" name="VALUE_0" caption="counter disabled"/>
                <value value="1" name="VALUE_1" caption="counter enabled"/>
            </value-group>
            <value-group name="TICKINT">
                <value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
                <value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
            </value-group>
            <value-group name="CLKSOURCE">
                <value value="0" name="VALUE_0" caption="external clock"/>
                <value value="1" name="VALUE_1" caption="processor clock"/>
            </value-group>
            <value-group name="SKEW">
                <value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
                <value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
            </value-group>
            <value-group name="NOREF">
                <value value="0" name="VALUE_0" caption="The reference clock is provided"/>
                <value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
            </value-group>
        </module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
            <register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
                <register offset="0x00000000" size="4" name="NVICISER0" initval="0" caption="Interrupt Set Enable Register n">
                    <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
                </register>
                <register offset="0x00000004" size="4" name="NVICISER1" initval="0" caption="Interrupt Set Enable Register n">
                    <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
                </register>
                <register offset="0x00000008" size="4" name="NVICISER2" initval="0" caption="Interrupt Set Enable Register n">
                    <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
                </register>
                <register offset="0x0000000c" size="4" name="NVICISER3" initval="0" caption="Interrupt Set Enable Register n">
                    <bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
                </register>
                <register offset="0x00000080" size="4" name="NVICICER0" initval="0" caption="Interrupt Clear Enable Register n">
                    <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
                </register>
                <register offset="0x00000084" size="4" name="NVICICER1" initval="0" caption="Interrupt Clear Enable Register n">
                    <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
                </register>
                <register offset="0x00000088" size="4" name="NVICICER2" initval="0" caption="Interrupt Clear Enable Register n">
                    <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
                </register>
                <register offset="0x0000008c" size="4" name="NVICICER3" initval="0" caption="Interrupt Clear Enable Register n">
                    <bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
                </register>
                <register offset="0x00000100" size="4" name="NVICISPR0" initval="0" caption="Interrupt Set Pending Register n">
                    <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
                </register>
                <register offset="0x00000104" size="4" name="NVICISPR1" initval="0" caption="Interrupt Set Pending Register n">
                    <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
                </register>
                <register offset="0x00000108" size="4" name="NVICISPR2" initval="0" caption="Interrupt Set Pending Register n">
                    <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
                </register>
                <register offset="0x0000010c" size="4" name="NVICISPR3" initval="0" caption="Interrupt Set Pending Register n">
                    <bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
                </register>
                <register offset="0x00000180" size="4" name="NVICICPR0" initval="0" caption="Interrupt Clear Pending Register n">
                    <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
                </register>
                <register offset="0x00000184" size="4" name="NVICICPR1" initval="0" caption="Interrupt Clear Pending Register n">
                    <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
                </register>
                <register offset="0x00000188" size="4" name="NVICICPR2" initval="0" caption="Interrupt Clear Pending Register n">
                    <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
                </register>
                <register offset="0x0000018c" size="4" name="NVICICPR3" initval="0" caption="Interrupt Clear Pending Register n">
                    <bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
                </register>
                <register offset="0x00000200" size="4" name="NVICIABR0" initval="0" caption="Interrupt Active bit Register n">
                    <bitfield mask="0xffffffff" name="ACTIVE" caption="Interrupt active flags"/>
                </register>
                <register offset="0x00000204" size="4" name="NVICIABR1" initval="0" caption="Interrupt Active bit Register n">
                    <bitfield mask="0xffffffff" name="ACTIVE" caption="Interrupt active flags"/>
                </register>
                <register offset="0x00000208" size="4" name="NVICIABR2" initval="0" caption="Interrupt Active bit Register n">
                    <bitfield mask="0xffffffff" name="ACTIVE" caption="Interrupt active flags"/>
                </register>
                <register offset="0x0000020c" size="4" name="NVICIABR3" initval="0" caption="Interrupt Active bit Register n">
                    <bitfield mask="0xffffffff" name="ACTIVE" caption="Interrupt active flags"/>
                </register>
                <register offset="0x00000300" size="1" name="NVICIP0" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
                </register>
                <register offset="0x00000301" size="1" name="NVICIP1" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI1" caption="Priority of interrupt 1"/>
                </register>
                <register offset="0x00000302" size="1" name="NVICIP2" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI2" caption="Priority of interrupt 2"/>
                </register>
                <register offset="0x00000303" size="1" name="NVICIP3" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI3" caption="Priority of interrupt 3"/>
                </register>
                <register offset="0x00000304" size="1" name="NVICIP4" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
                </register>
                <register offset="0x00000305" size="1" name="NVICIP5" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI5" caption="Priority of interrupt 5"/>
                </register>
                <register offset="0x00000306" size="1" name="NVICIP6" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI6" caption="Priority of interrupt 6"/>
                </register>
                <register offset="0x00000307" size="1" name="NVICIP7" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI7" caption="Priority of interrupt 7"/>
                </register>
                <register offset="0x00000308" size="1" name="NVICIP8" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
                </register>
                <register offset="0x00000309" size="1" name="NVICIP9" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI9" caption="Priority of interrupt 9"/>
                </register>
                <register offset="0x0000030a" size="1" name="NVICIP10" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI10" caption="Priority of interrupt 10"/>
                </register>
                <register offset="0x0000030b" size="1" name="NVICIP11" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI11" caption="Priority of interrupt 11"/>
                </register>
                <register offset="0x0000030c" size="1" name="NVICIP12" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
                </register>
                <register offset="0x0000030d" size="1" name="NVICIP13" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI13" caption="Priority of interrupt 13"/>
                </register>
                <register offset="0x0000030e" size="1" name="NVICIP14" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI14" caption="Priority of interrupt 14"/>
                </register>
                <register offset="0x0000030f" size="1" name="NVICIP15" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI15" caption="Priority of interrupt 15"/>
                </register>
                <register offset="0x00000310" size="1" name="NVICIP16" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
                </register>
                <register offset="0x00000311" size="1" name="NVICIP17" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI17" caption="Priority of interrupt 17"/>
                </register>
                <register offset="0x00000312" size="1" name="NVICIP18" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI18" caption="Priority of interrupt 18"/>
                </register>
                <register offset="0x00000313" size="1" name="NVICIP19" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI19" caption="Priority of interrupt 19"/>
                </register>
                <register offset="0x00000314" size="1" name="NVICIP20" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
                </register>
                <register offset="0x00000315" size="1" name="NVICIP21" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI21" caption="Priority of interrupt 21"/>
                </register>
                <register offset="0x00000316" size="1" name="NVICIP22" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI22" caption="Priority of interrupt 22"/>
                </register>
                <register offset="0x00000317" size="1" name="NVICIP23" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI23" caption="Priority of interrupt 23"/>
                </register>
                <register offset="0x00000318" size="1" name="NVICIP24" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
                </register>
                <register offset="0x00000319" size="1" name="NVICIP25" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI25" caption="Priority of interrupt 25"/>
                </register>
                <register offset="0x0000031a" size="1" name="NVICIP26" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI26" caption="Priority of interrupt 26"/>
                </register>
                <register offset="0x0000031b" size="1" name="NVICIP27" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI27" caption="Priority of interrupt 27"/>
                </register>
                <register offset="0x0000031c" size="1" name="NVICIP28" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
                </register>
                <register offset="0x0000031d" size="1" name="NVICIP29" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI29" caption="Priority of interrupt 29"/>
                </register>
                <register offset="0x0000031e" size="1" name="NVICIP30" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI30" caption="Priority of interrupt 30"/>
                </register>
                <register offset="0x0000031f" size="1" name="NVICIP31" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI31" caption="Priority of interrupt 31"/>
                </register>
                <register offset="0x00000320" size="1" name="NVICIP32" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI32" caption="Priority of interrupt 32"/>
                </register>
                <register offset="0x00000321" size="1" name="NVICIP33" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI33" caption="Priority of interrupt 33"/>
                </register>
                <register offset="0x00000322" size="1" name="NVICIP34" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI34" caption="Priority of interrupt 34"/>
                </register>
                <register offset="0x00000323" size="1" name="NVICIP35" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI35" caption="Priority of interrupt 35"/>
                </register>
                <register offset="0x00000324" size="1" name="NVICIP36" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI36" caption="Priority of interrupt 36"/>
                </register>
                <register offset="0x00000325" size="1" name="NVICIP37" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI37" caption="Priority of interrupt 37"/>
                </register>
                <register offset="0x00000326" size="1" name="NVICIP38" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI38" caption="Priority of interrupt 38"/>
                </register>
                <register offset="0x00000327" size="1" name="NVICIP39" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI39" caption="Priority of interrupt 39"/>
                </register>
                <register offset="0x00000328" size="1" name="NVICIP40" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI40" caption="Priority of interrupt 40"/>
                </register>
                <register offset="0x00000329" size="1" name="NVICIP41" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI41" caption="Priority of interrupt 41"/>
                </register>
                <register offset="0x0000032a" size="1" name="NVICIP42" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI42" caption="Priority of interrupt 42"/>
                </register>
                <register offset="0x0000032b" size="1" name="NVICIP43" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI43" caption="Priority of interrupt 43"/>
                </register>
                <register offset="0x0000032c" size="1" name="NVICIP44" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI44" caption="Priority of interrupt 44"/>
                </register>
                <register offset="0x0000032d" size="1" name="NVICIP45" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI45" caption="Priority of interrupt 45"/>
                </register>
                <register offset="0x0000032e" size="1" name="NVICIP46" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI46" caption="Priority of interrupt 46"/>
                </register>
                <register offset="0x0000032f" size="1" name="NVICIP47" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI47" caption="Priority of interrupt 47"/>
                </register>
                <register offset="0x00000330" size="1" name="NVICIP48" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI48" caption="Priority of interrupt 48"/>
                </register>
                <register offset="0x00000331" size="1" name="NVICIP49" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI49" caption="Priority of interrupt 49"/>
                </register>
                <register offset="0x00000332" size="1" name="NVICIP50" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI50" caption="Priority of interrupt 50"/>
                </register>
                <register offset="0x00000333" size="1" name="NVICIP51" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI51" caption="Priority of interrupt 51"/>
                </register>
                <register offset="0x00000334" size="1" name="NVICIP52" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI52" caption="Priority of interrupt 52"/>
                </register>
                <register offset="0x00000335" size="1" name="NVICIP53" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI53" caption="Priority of interrupt 53"/>
                </register>
                <register offset="0x00000336" size="1" name="NVICIP54" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI54" caption="Priority of interrupt 54"/>
                </register>
                <register offset="0x00000337" size="1" name="NVICIP55" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI55" caption="Priority of interrupt 55"/>
                </register>
                <register offset="0x00000338" size="1" name="NVICIP56" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI56" caption="Priority of interrupt 56"/>
                </register>
                <register offset="0x00000339" size="1" name="NVICIP57" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI57" caption="Priority of interrupt 57"/>
                </register>
                <register offset="0x0000033a" size="1" name="NVICIP58" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI58" caption="Priority of interrupt 58"/>
                </register>
                <register offset="0x0000033b" size="1" name="NVICIP59" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI59" caption="Priority of interrupt 59"/>
                </register>
                <register offset="0x0000033c" size="1" name="NVICIP60" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI60" caption="Priority of interrupt 60"/>
                </register>
                <register offset="0x0000033d" size="1" name="NVICIP61" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI61" caption="Priority of interrupt 61"/>
                </register>
                <register offset="0x0000033e" size="1" name="NVICIP62" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI62" caption="Priority of interrupt 62"/>
                </register>
                <register offset="0x0000033f" size="1" name="NVICIP63" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI63" caption="Priority of interrupt 63"/>
                </register>
                <register offset="0x00000340" size="1" name="NVICIP64" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI64" caption="Priority of interrupt 64"/>
                </register>
                <register offset="0x00000341" size="1" name="NVICIP65" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI65" caption="Priority of interrupt 65"/>
                </register>
                <register offset="0x00000342" size="1" name="NVICIP66" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI66" caption="Priority of interrupt 66"/>
                </register>
                <register offset="0x00000343" size="1" name="NVICIP67" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI67" caption="Priority of interrupt 67"/>
                </register>
                <register offset="0x00000344" size="1" name="NVICIP68" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI68" caption="Priority of interrupt 68"/>
                </register>
                <register offset="0x00000345" size="1" name="NVICIP69" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI69" caption="Priority of interrupt 69"/>
                </register>
                <register offset="0x00000346" size="1" name="NVICIP70" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI70" caption="Priority of interrupt 70"/>
                </register>
                <register offset="0x00000347" size="1" name="NVICIP71" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI71" caption="Priority of interrupt 71"/>
                </register>
                <register offset="0x00000348" size="1" name="NVICIP72" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI72" caption="Priority of interrupt 72"/>
                </register>
                <register offset="0x00000349" size="1" name="NVICIP73" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI73" caption="Priority of interrupt 73"/>
                </register>
                <register offset="0x0000034a" size="1" name="NVICIP74" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI74" caption="Priority of interrupt 74"/>
                </register>
                <register offset="0x0000034b" size="1" name="NVICIP75" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI75" caption="Priority of interrupt 75"/>
                </register>
                <register offset="0x0000034c" size="1" name="NVICIP76" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI76" caption="Priority of interrupt 76"/>
                </register>
                <register offset="0x0000034d" size="1" name="NVICIP77" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI77" caption="Priority of interrupt 77"/>
                </register>
                <register offset="0x0000034e" size="1" name="NVICIP78" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI78" caption="Priority of interrupt 78"/>
                </register>
                <register offset="0x0000034f" size="1" name="NVICIP79" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI79" caption="Priority of interrupt 79"/>
                </register>
                <register offset="0x00000350" size="1" name="NVICIP80" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI80" caption="Priority of interrupt 80"/>
                </register>
                <register offset="0x00000351" size="1" name="NVICIP81" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI81" caption="Priority of interrupt 81"/>
                </register>
                <register offset="0x00000352" size="1" name="NVICIP82" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI82" caption="Priority of interrupt 82"/>
                </register>
                <register offset="0x00000353" size="1" name="NVICIP83" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI83" caption="Priority of interrupt 83"/>
                </register>
                <register offset="0x00000354" size="1" name="NVICIP84" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI84" caption="Priority of interrupt 84"/>
                </register>
                <register offset="0x00000355" size="1" name="NVICIP85" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI85" caption="Priority of interrupt 85"/>
                </register>
                <register offset="0x00000356" size="1" name="NVICIP86" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI86" caption="Priority of interrupt 86"/>
                </register>
                <register offset="0x00000357" size="1" name="NVICIP87" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI87" caption="Priority of interrupt 87"/>
                </register>
                <register offset="0x00000358" size="1" name="NVICIP88" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI88" caption="Priority of interrupt 88"/>
                </register>
                <register offset="0x00000359" size="1" name="NVICIP89" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI89" caption="Priority of interrupt 89"/>
                </register>
                <register offset="0x0000035a" size="1" name="NVICIP90" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI90" caption="Priority of interrupt 90"/>
                </register>
                <register offset="0x0000035b" size="1" name="NVICIP91" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI91" caption="Priority of interrupt 91"/>
                </register>
                <register offset="0x0000035c" size="1" name="NVICIP92" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI92" caption="Priority of interrupt 92"/>
                </register>
                <register offset="0x0000035d" size="1" name="NVICIP93" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI93" caption="Priority of interrupt 93"/>
                </register>
                <register offset="0x0000035e" size="1" name="NVICIP94" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI94" caption="Priority of interrupt 94"/>
                </register>
                <register offset="0x0000035f" size="1" name="NVICIP95" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI95" caption="Priority of interrupt 95"/>
                </register>
                <register offset="0x00000360" size="1" name="NVICIP96" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI96" caption="Priority of interrupt 96"/>
                </register>
                <register offset="0x00000361" size="1" name="NVICIP97" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI97" caption="Priority of interrupt 97"/>
                </register>
                <register offset="0x00000362" size="1" name="NVICIP98" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI98" caption="Priority of interrupt 98"/>
                </register>
                <register offset="0x00000363" size="1" name="NVICIP99" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI99" caption="Priority of interrupt 99"/>
                </register>
                <register offset="0x00000364" size="1" name="NVICIP100" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI100" caption="Priority of interrupt 100"/>
                </register>
                <register offset="0x00000365" size="1" name="NVICIP101" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI101" caption="Priority of interrupt 101"/>
                </register>
                <register offset="0x00000366" size="1" name="NVICIP102" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI102" caption="Priority of interrupt 102"/>
                </register>
                <register offset="0x00000367" size="1" name="NVICIP103" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI103" caption="Priority of interrupt 103"/>
                </register>
                <register offset="0x00000368" size="1" name="NVICIP104" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI104" caption="Priority of interrupt 104"/>
                </register>
                <register offset="0x00000369" size="1" name="NVICIP105" initval="0" caption="Interrupt Priority Register n">
                    <bitfield mask="0x000000ff" name="PRI105" caption="Priority of interrupt 105"/>
                </register>
                <register offset="0x00000e00" size="4" name="NVICSTIR" initval="0" caption="Software Trigger Interrupt Register">
                    <bitfield mask="0x000001ff" name="INTID" caption="Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3."/>
                </register>
            </register-group>
        </module><module name="MPU" caption="Memory Protection Unit Registers">
            <register-group name="MPU" caption="Memory Protection Unit">
                <register offset="0x00000000" size="4" name="MPU_TYPE" initval="0x00000800" caption="MPU Type Register" rw="R">
                    <bitfield mask="0x00000001" name="SEPARATE" caption="Indicates support for unified or separate instruction and date memory maps."/>
                    <bitfield mask="0x0000FF00" name="DREGION" caption="Indicates the number of supported MPU instruction regions."/>
                    <bitfield mask="0x00FF0000" name="IREGION" caption="Indicates the number of supported MPU data regions."/>
                </register>
                <register offset="0x00000004" size="4" name="MPU_CTRL" initval="0x00000000" caption="MPU Control Register" rw="RW">
                    <bitfield mask="0x00000001" name="ENABLE" caption="Enables the MPU"/>
                    <bitfield mask="0x00000002" name="HFNMIENA" caption="Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers."/>
                    <bitfield mask="0x00000004" name="PRIVDEFENA" caption="Enables privileged software access to the default memory map."/>
                </register>
                <register offset="0x00000008" size="4" name="MPU_RNR" initval="0x00000000" caption="MPU Region Number Register" rw="RW">
                    <bitfield mask="0x000000FF" name="REGION" caption="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers."/>
                </register>
                <register offset="0x0000000C" size="4" name="MPU_RBAR" initval="0x00000000" caption="MPU Region Base Address Register" rw="RW">
                    <bitfield mask="0x0000000F" name="REGION" caption="MPU region field."/>
                    <bitfield mask="0x00000010" name="VALID" caption="MPU Region Number valid bit."/>
                    <bitfield mask="0xFFFFFFE0" name="ADDR" caption="Region base address field."/>
                </register>
                <register offset="0x00000010" size="4" name="MPU_RASR" initval="0x00000000" caption="MPU Region Attribute and Size Register" rw="RW">
                    <bitfield mask="0x00000001" name="ENABLE" caption="Region enable bit."/>
                    <bitfield mask="0x0000003E" name="SIZE" caption="Specifies the size of the MPU protection region."/>
                    <bitfield mask="0x0000FF00" name="SRD" caption="Subregion disable bits."/>
                    <bitfield mask="0x00010000" name="B" caption="MPU access permission attributes."/>
                    <bitfield mask="0x00020000" name="C" caption="MPU access permission attributes."/>
                    <bitfield mask="0x00040000" name="S" caption="Shareable bit."/>
                    <bitfield mask="0x00380000" name="TEX" caption="MPU access permission attributes."/>
                    <bitfield mask="0x07000000" name="AP" caption="Access permission field."/>
                    <bitfield mask="0x10000000" name="XN" caption="Instruction access disable bit."/>
                </register>
            </register-group>
        </module></modules>
  <pinouts>
    <pinout name="SAMD51P" caption="SAMD51P">
      <pin position="1" pad="PA00"/>
      <pin position="2" pad="PA01"/>
      <pin position="3" pad="PC00"/>
      <pin position="4" pad="PC01"/>
      <pin position="6" pad="VDDANA"/>
      <pin position="7" pad="PC02"/>
      <pin position="8" pad="PC03"/>
      <pin position="9" pad="PA02"/>
      <pin position="10" pad="PA03"/>
      <pin position="11" pad="PB04"/>
      <pin position="12" pad="PB05"/>
      <pin position="13" pad="PD00"/>
      <pin position="14" pad="GNDANA"/>
      <pin position="15" pad="VDDANA"/>
      <pin position="16" pad="PD01"/>
      <pin position="17" pad="PB06"/>
      <pin position="18" pad="PB07"/>
      <pin position="19" pad="PB08"/>
      <pin position="20" pad="PB09"/>
      <pin position="21" pad="PA04"/>
      <pin position="22" pad="PA05"/>
      <pin position="23" pad="PA06"/>
      <pin position="24" pad="PA07"/>
      <pin position="25" pad="GNDANA"/>
      <pin position="26" pad="VDDANA"/>
      <pin position="27" pad="PC04"/>
      <pin position="28" pad="PC05"/>
      <pin position="29" pad="PC06"/>
      <pin position="30" pad="PC07"/>
      <pin position="31" pad="GND"/>
      <pin position="32" pad="VDDIO"/>
      <pin position="33" pad="PA08"/>
      <pin position="34" pad="PA09"/>
      <pin position="35" pad="PA10"/>
      <pin position="36" pad="PA11"/>
      <pin position="37" pad="VDDIO"/>
      <pin position="38" pad="GND"/>
      <pin position="39" pad="PB10"/>
      <pin position="40" pad="PB11"/>
      <pin position="41" pad="PB12"/>
      <pin position="42" pad="PB13"/>
      <pin position="43" pad="PB14"/>
      <pin position="44" pad="PB15"/>
      <pin position="45" pad="GND"/>
      <pin position="46" pad="VDDIO"/>
      <pin position="47" pad="PD08"/>
      <pin position="48" pad="PD09"/>
      <pin position="49" pad="PD10"/>
      <pin position="50" pad="PD11"/>
      <pin position="51" pad="PD12"/>
      <pin position="52" pad="PC10"/>
      <pin position="53" pad="GND"/>
      <pin position="54" pad="VDDIO"/>
      <pin position="55" pad="PC11"/>
      <pin position="56" pad="PC12"/>
      <pin position="57" pad="PC13"/>
      <pin position="58" pad="PC14"/>
      <pin position="59" pad="PC15"/>
      <pin position="60" pad="PA12"/>
      <pin position="61" pad="PA13"/>
      <pin position="62" pad="PA14"/>
      <pin position="63" pad="PA15"/>
      <pin position="64" pad="GND"/>
      <pin position="65" pad="VDDIO"/>
      <pin position="66" pad="PA16"/>
      <pin position="67" pad="PA17"/>
      <pin position="68" pad="PA18"/>
      <pin position="69" pad="PA19"/>
      <pin position="70" pad="PC16"/>
      <pin position="71" pad="PC17"/>
      <pin position="72" pad="PC18"/>
      <pin position="73" pad="PC19"/>
      <pin position="74" pad="PC20"/>
      <pin position="75" pad="PC21"/>
      <pin position="76" pad="PC22"/>
      <pin position="77" pad="PC23"/>
      <pin position="78" pad="GND"/>
      <pin position="79" pad="VDDIO"/>
      <pin position="80" pad="PD20"/>
      <pin position="81" pad="PD21"/>
      <pin position="82" pad="PB16"/>
      <pin position="83" pad="PB17"/>
      <pin position="84" pad="PB18"/>
      <pin position="85" pad="PB19"/>
      <pin position="86" pad="PB20"/>
      <pin position="87" pad="PB21"/>
      <pin position="88" pad="PA20"/>
      <pin position="89" pad="PA21"/>
      <pin position="90" pad="GND"/>
      <pin position="91" pad="VDDIO"/>
      <pin position="92" pad="PA22"/>
      <pin position="93" pad="PA23"/>
      <pin position="94" pad="PA24"/>
      <pin position="95" pad="PA25"/>
      <pin position="96" pad="GND"/>
      <pin position="97" pad="VDDIO"/>
      <pin position="98" pad="PB22"/>
      <pin position="99" pad="PB23"/>
      <pin position="100" pad="PB24"/>
      <pin position="101" pad="PB25"/>
      <pin position="102" pad="PB26"/>
      <pin position="103" pad="PB27"/>
      <pin position="104" pad="PB28"/>
      <pin position="105" pad="PB29"/>
      <pin position="106" pad="GND"/>
      <pin position="107" pad="VDDIO"/>
      <pin position="108" pad="PC24"/>
      <pin position="109" pad="PC25"/>
      <pin position="110" pad="PC26"/>
      <pin position="111" pad="PC27"/>
      <pin position="112" pad="PC28"/>
      <pin position="113" pad="PA27"/>
      <pin position="114" pad="RESET_N"/>
      <pin position="115" pad="VDDCORE"/>
      <pin position="116" pad="GND"/>
      <pin position="117" pad="VSW"/>
      <pin position="118" pad="VDDIO"/>
      <pin position="119" pad="PA30"/>
      <pin position="120" pad="PA31"/>
      <pin position="121" pad="PB30"/>
      <pin position="122" pad="PB31"/>
      <pin position="123" pad="PC30"/>
      <pin position="124" pad="PC31"/>
      <pin position="125" pad="PB00"/>
      <pin position="126" pad="PB01"/>
      <pin position="127" pad="PB02"/>
      <pin position="128" pad="PB03"/>
    </pinout>
  </pinouts>
</avr-tools-device-file>