| CMSIS-Driver Version 2.02 Peripheral Interface for Middleware and Application Code

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Data Structures | Macros | Typedefs
Driver_MCI.h File Reference

## Data Structures

struct | ARM_MCI_STATUS
| MCI Status. More...
struct | ARM_MCI_CAPABILITIES
| MCI Driver Capabilities. More...
struct | ARM_DRIVER_MCI
| Access structure of the MCI Driver. More...

## Macros

#define | ARM_MCI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,02) /* API version */
#define | ARM_MCI_RESPONSE_Pos 0
#define | ARM_MCI_RESPONSE_Msk (3UL << ARM_MCI_RESPONSE_Pos)
#define | ARM_MCI_RESPONSE_NONE (0UL << ARM_MCI_RESPONSE_Pos)
| No response expected (default)
#define | ARM_MCI_RESPONSE_SHORT (1UL << ARM_MCI_RESPONSE_Pos)
| Short response (48-bit)
#define | ARM_MCI_RESPONSE_SHORT_BUSY (2UL << ARM_MCI_RESPONSE_Pos)
| Short response with busy signal (48-bit)
#define | ARM_MCI_RESPONSE_LONG (3UL << ARM_MCI_RESPONSE_Pos)
| Long response (136-bit)
#define | ARM_MCI_RESPONSE_INDEX (1UL << 2)
| Check command index in response.
#define | ARM_MCI_RESPONSE_CRC (1UL << 3)
| Check CRC in response.
#define | ARM_MCI_WAIT_BUSY (1UL << 4)
| Wait until busy before sending the command.
#define | ARM_MCI_TRANSFER_DATA (1UL << 5)
| Activate Data transfer.
#define | ARM_MCI_CARD_INITIALIZE (1UL << 6)
| Execute Memory Card initialization sequence.
#define | ARM_MCI_INTERRUPT_COMMAND (1UL << 7)
| Send Interrupt command (CMD40 - MMC only)
#define | ARM_MCI_INTERRUPT_RESPONSE (1UL << 8)
| Send Interrupt response (CMD40 - MMC only)
#define | ARM_MCI_BOOT_OPERATION (1UL << 9)
| Execute Boot operation (MMC only)
#define | ARM_MCI_BOOT_ALTERNATIVE (1UL << 10)
| Execute Alternative Boot operation (MMC only)
#define | ARM_MCI_BOOT_ACK (1UL << 11)
| Expect Boot Acknowledge (MMC only)
#define | ARM_MCI_CCSD (1UL << 12)
| Send Command Completion Signal Disable (CCSD) for CE-ATA device.
#define | ARM_MCI_CCS (1UL << 13)
| Expect Command Completion Signal (CCS) for CE-ATA device.
#define | ARM_MCI_TRANSFER_READ (0UL << 0)
| Data Read Transfer (from MCI)
#define | ARM_MCI_TRANSFER_WRITE (1UL << 0)
| Data Write Transfer (to MCI)
#define | ARM_MCI_TRANSFER_BLOCK (0UL << 1)
| Block Data transfer (default)
#define | ARM_MCI_TRANSFER_STREAM (1UL << 1)
| Stream Data transfer (MMC only)
#define | ARM_MCI_BUS_SPEED (0x01)
| Set Bus Speed; arg = requested speed in bits/s; returns configured speed in bits/s.
#define | ARM_MCI_BUS_SPEED_MODE (0x02)
| Set Bus Speed Mode as specified with arg.
#define | ARM_MCI_BUS_CMD_MODE (0x03)
| Set CMD Line Mode as specified with arg.
#define | ARM_MCI_BUS_DATA_WIDTH (0x04)
| Set Bus Data Width as specified with arg.
#define | ARM_MCI_DRIVER_STRENGTH (0x05)
| Set SD UHS-I Driver Strength as specified with arg.
#define | ARM_MCI_CONTROL_RESET (0x06)
| Control optional RST_n Pin (eMMC); arg: 0=inactive, 1=active.
#define | ARM_MCI_CONTROL_CLOCK_IDLE (0x07)
| Control Clock generation on CLK Pin when idle; arg: 0=disabled, 1=enabled.
#define | ARM_MCI_UHS_TUNING_OPERATION (0x08)
| Sampling clock Tuning operation (SD UHS-I); arg: 0=reset, 1=execute.
#define | ARM_MCI_UHS_TUNING_RESULT (0x09)
| Sampling clock Tuning result (SD UHS-I); returns: 0=done, 1=in progress, -1=error.
#define | ARM_MCI_DATA_TIMEOUT (0x0A)
| Set Data timeout; arg = timeout in bus cycles.
#define | ARM_MCI_CSS_TIMEOUT (0x0B)
| Set Command Completion Signal (CCS) timeout; arg = timeout in bus cycles.
#define | ARM_MCI_MONITOR_SDIO_INTERRUPT (0x0C)
| Monitor SD I/O interrupt: arg: 0=disabled, 1=enabled.
#define | ARM_MCI_CONTROL_READ_WAIT (0x0D)
| Control Read/Wait for SD I/O; arg: 0=disabled, 1=enabled.
#define | ARM_MCI_SUSPEND_TRANSFER (0x0E)
| Suspend Data transfer (SD I/O); returns number of remaining bytes to transfer.
#define | ARM_MCI_RESUME_TRANSFER (0x0F)
| Resume Data transfer (SD I/O)
#define | ARM_MCI_BUS_DEFAULT_SPEED (0x00)
| SD/MMC: Default Speed mode up to 25/26MHz.
#define | ARM_MCI_BUS_HIGH_SPEED (0x01)
| SD/MMC: High Speed mode up to 50/52MHz.
#define | ARM_MCI_BUS_UHS_SDR12 (0x02)
| SD: SDR12 (Single Data Rate) up to 25MHz, 12.5MB/s: UHS-I (Ultra High Speed) 1.8V signaling.
#define | ARM_MCI_BUS_UHS_SDR25 (0x03)
| SD: SDR25 (Single Data Rate) up to 50MHz, 25 MB/s: UHS-I (Ultra High Speed) 1.8V signaling.
#define | ARM_MCI_BUS_UHS_SDR50 (0x04)
| SD: SDR50 (Single Data Rate) up to 100MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling.
#define | ARM_MCI_BUS_UHS_SDR104 (0x05)
| SD: SDR104 (Single Data Rate) up to 208MHz, 104 MB/s: UHS-I (Ultra High Speed) 1.8V signaling.
#define | ARM_MCI_BUS_UHS_DDR50 (0x06)
| SD: DDR50 (Dual Data Rate) up to 50MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling.
#define | ARM_MCI_BUS_CMD_PUSH_PULL (0x00)
| Push-Pull CMD line (default)
#define | ARM_MCI_BUS_CMD_OPEN_DRAIN (0x01)
| Open Drain CMD line (MMC only)
#define | ARM_MCI_BUS_DATA_WIDTH_1 (0x00)
| Bus data width: 1 bit (default)
#define | ARM_MCI_BUS_DATA_WIDTH_4 (0x01)
| Bus data width: 4 bits.
#define | ARM_MCI_BUS_DATA_WIDTH_8 (0x02)
| Bus data width: 8 bits.
#define | ARM_MCI_BUS_DATA_WIDTH_4_DDR (0x03)
| Bus data width: 4 bits, DDR (Dual Data Rate) - MMC only.
#define | ARM_MCI_BUS_DATA_WIDTH_8_DDR (0x04)
| Bus data width: 8 bits, DDR (Dual Data Rate) - MMC only.
#define | ARM_MCI_DRIVER_TYPE_A (0x01)
| SD UHS-I Driver Type A.
#define | ARM_MCI_DRIVER_TYPE_B (0x00)
| SD UHS-I Driver Type B (default)
#define | ARM_MCI_DRIVER_TYPE_C (0x02)
| SD UHS-I Driver Type C.
#define | ARM_MCI_DRIVER_TYPE_D (0x03)
| SD UHS-I Driver Type D.
#define | ARM_MCI_POWER_VDD_Pos 0
#define | ARM_MCI_POWER_VDD_Msk (0x0FUL << ARM_MCI_POWER_VDD_Pos)
#define | ARM_MCI_POWER_VDD_OFF (0x01UL << ARM_MCI_POWER_VDD_Pos)
| VDD (VCC) turned off.
#define | ARM_MCI_POWER_VDD_3V3 (0x02UL << ARM_MCI_POWER_VDD_Pos)
| VDD (VCC) = 3.3V.
#define | ARM_MCI_POWER_VDD_1V8 (0x03UL << ARM_MCI_POWER_VDD_Pos)
| VDD (VCC) = 1.8V.
#define | ARM_MCI_POWER_VCCQ_Pos 4
#define | ARM_MCI_POWER_VCCQ_Msk (0x0FUL << ARM_MCI_POWER_VCCQ_Pos)
#define | ARM_MCI_POWER_VCCQ_OFF (0x01UL << ARM_MCI_POWER_VCCQ_Pos)
| eMMC VCCQ turned off
#define | ARM_MCI_POWER_VCCQ_3V3 (0x02UL << ARM_MCI_POWER_VCCQ_Pos)
| eMMC VCCQ = 3.3V
#define | ARM_MCI_POWER_VCCQ_1V8 (0x03UL << ARM_MCI_POWER_VCCQ_Pos)
| eMMC VCCQ = 1.8V
#define | ARM_MCI_POWER_VCCQ_1V2 (0x04UL << ARM_MCI_POWER_VCCQ_Pos)
| eMMC VCCQ = 1.2V
#define | ARM_MCI_EVENT_CARD_INSERTED (1UL << 0)
| Memory Card inserted.
#define | ARM_MCI_EVENT_CARD_REMOVED (1UL << 1)
| Memory Card removed.
#define | ARM_MCI_EVENT_COMMAND_COMPLETE (1UL << 2)
| Command completed.
#define | ARM_MCI_EVENT_COMMAND_TIMEOUT (1UL << 3)
| Command timeout.
#define | ARM_MCI_EVENT_COMMAND_ERROR (1UL << 4)
| Command response error (CRC error or invalid response)
#define | ARM_MCI_EVENT_TRANSFER_COMPLETE (1UL << 5)
| Data transfer completed.
#define | ARM_MCI_EVENT_TRANSFER_TIMEOUT (1UL << 6)
| Data transfer timeout.
#define | ARM_MCI_EVENT_TRANSFER_ERROR (1UL << 7)
| Data transfer CRC failed.
#define | ARM_MCI_EVENT_SDIO_INTERRUPT (1UL << 8)
| SD I/O Interrupt.
#define | ARM_MCI_EVENT_CCS (1UL << 9)
| Command Completion Signal (CCS)
#define | ARM_MCI_EVENT_CCS_TIMEOUT (1UL << 10)
| Command Completion Signal (CCS) Timeout.

## Typedefs

typedef void(* | ARM_MCI_SignalEvent_t )(uint32_t event)
| Pointer to ARM_MCI_SignalEvent : Signal MCI Card Event.

## Macro Definition Documentation

#define ARM_MCI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,02) /* API version */

#define ARM_MCI_POWER_VCCQ_Msk (0x0FUL << ARM_MCI_POWER_VCCQ_Pos)

#define ARM_MCI_POWER_VCCQ_Pos 4

#define ARM_MCI_POWER_VDD_Msk (0x0FUL << ARM_MCI_POWER_VDD_Pos)

#define ARM_MCI_POWER_VDD_Pos 0

#define ARM_MCI_RESPONSE_Msk (3UL << ARM_MCI_RESPONSE_Pos)

#define ARM_MCI_RESPONSE_Pos 0