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16 commits
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feather_m4
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| cdb7fb1f0e | |||
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228 changed files with 455659 additions and 7 deletions
4
Makefile
4
Makefile
|
|
@ -56,12 +56,16 @@ INCLUDES += -Ilib/samd21/samd21a/include/
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|||
endif
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||||
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ifeq ($(CHIP_FAMILY), samd51)
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ifeq ($(findstring SAME51,$(CHIP_VARIANT)),SAME51)
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INCLUDES += -Ilib/same51/include/
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else
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ifeq ($(findstring SAME54,$(CHIP_VARIANT)),SAME54)
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INCLUDES += -Ilib/same54/include/
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else
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INCLUDES += -Ilib/samd51/include/
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endif
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endif
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endif
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||||
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COMMON_SRC = \
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src/flash_$(CHIP_FAMILY).c \
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|
|
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|||
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@ -30,7 +30,7 @@ a UF2 file is written and immediately write it to flash.
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* USB CDC (Serial emulation) monitor mode compatible with Arduino
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(including XYZ commands) and BOSSA flashing tool
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* USB MSC interface for writing UF2 files
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* reading of the contests of the flash as an UF2 file via USB MSC
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* reading of the content of the flash as an UF2 file via USB MSC
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* UART Serial (real serial wire) monitor mode (typically disabled due to space constraints)
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* In-memory logging for debugging - use the `logs` target to extract the logs using `openocd`
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* double-tap reset to stay in the bootloader mode
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@ -145,7 +145,7 @@ The default board is `zero`. You can build a different one using:
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make BOARD=metro_m0
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```
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If you're working on different board, it's best to create `Makefile.local`
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If you're working on different board, it's best to create `Makefile.user`
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with say `BOARD=metro` to change the default.
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The names `zero` and `metro` refer to subdirectories of `boards/`.
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|
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2
boards/XIAO_m0/board.mk
Normal file
2
boards/XIAO_m0/board.mk
Normal file
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@ -0,0 +1,2 @@
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CHIP_FAMILY = samd21
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CHIP_VARIANT = SAMD21G18A
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23
boards/XIAO_m0/board_config.h
Normal file
23
boards/XIAO_m0/board_config.h
Normal file
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@ -0,0 +1,23 @@
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#ifndef BOARD_CONFIG_H
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#define BOARD_CONFIG_H
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#define VENDOR_NAME "Seeed Studio"
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#define PRODUCT_NAME "Seeeduino XIAO"
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#define VOLUME_LABEL "Seeed XIAO"
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#define INDEX_URL "https://www.seeedstudio.com/"
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#define BOARD_ID "SAMD21G18A-XIAO-v0"
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#define USB_VID 0x2886
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#define USB_PID 0x002F
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#define LED_PIN PIN_PA17
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#define LED_TX_PIN PIN_PA19
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#define LED_RX_PIN PIN_PA18
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#define LED_PIN_PULLUP
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#define LED_TX_PIN_PULLUP
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#define LED_RX_PIN_PULLUP
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#endif
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2
boards/blm_badge/board.mk
Normal file
2
boards/blm_badge/board.mk
Normal file
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@ -0,0 +1,2 @@
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CHIP_FAMILY = samd21
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CHIP_VARIANT = SAMD21E18A
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20
boards/blm_badge/board_config.h
Normal file
20
boards/blm_badge/board_config.h
Normal file
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@ -0,0 +1,20 @@
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#ifndef BOARD_CONFIG_H
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#define BOARD_CONFIG_H
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#define CRYSTALLESS 1
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#define VENDOR_NAME "Adafruit Industries"
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#define PRODUCT_NAME "BLM Badge"
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#define VOLUME_LABEL "BADGEBOOT"
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#define INDEX_URL "https://www.adafruit.com/blacklivesmatter"
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#define BOARD_ID "SAMD21E18A-BLMbadge-v0"
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#define USB_VID 0x239A
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#define USB_PID 0x00BF
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#define LED_PIN PIN_PA03
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#define BOARD_NEOPIXEL_PIN PIN_PA05
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#define BOARD_NEOPIXEL_COUNT 6
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#endif
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2
boards/feather_m4_can/board.mk
Normal file
2
boards/feather_m4_can/board.mk
Normal file
|
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@ -0,0 +1,2 @@
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CHIP_FAMILY = samd51
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CHIP_VARIANT = SAME51J19A
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29
boards/feather_m4_can/board_config.h
Normal file
29
boards/feather_m4_can/board_config.h
Normal file
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@ -0,0 +1,29 @@
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#ifndef BOARD_CONFIG_H
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#define BOARD_CONFIG_H
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#define VENDOR_NAME "Adafruit Industries"
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#define PRODUCT_NAME "Feather M4 CAN Express"
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#define VOLUME_LABEL "FTHRCANBOOT"
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#define INDEX_URL "http://adafru.it/4759"
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#define BOARD_ID "SAME51J19A-FeatherM4-v0"
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#define USB_VID 0x239A
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#define USB_PID 0x00CD
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#define LED_PIN PIN_PA23
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#define BOARD_NEOPIXEL_PIN PIN_PB03
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#define BOARD_NEOPIXEL_COUNT 1
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#define BOOT_USART_MODULE SERCOM0
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#define BOOT_USART_MASK APBAMASK
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#define BOOT_USART_BUS_CLOCK_INDEX MCLK_APBAMASK_SERCOM0
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#define BOOT_USART_PAD_SETTINGS UART_RX_PAD3_TX_PAD0
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#define BOOT_USART_PAD3 PINMUX_PA07D_SERCOM0_PAD3
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#define BOOT_USART_PAD2 PINMUX_UNUSED
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#define BOOT_USART_PAD1 PINMUX_UNUSED
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#define BOOT_USART_PAD0 PINMUX_PA04D_SERCOM0_PAD0
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#define BOOT_GCLK_ID_CORE SERCOM0_GCLK_ID_CORE
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#define BOOT_GCLK_ID_SLOW SERCOM0_GCLK_ID_SLOW
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#endif
|
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2
boards/same54_xplained/board.mk
Normal file
2
boards/same54_xplained/board.mk
Normal file
|
|
@ -0,0 +1,2 @@
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CHIP_FAMILY = samd51
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CHIP_VARIANT = SAME54P20A
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29
boards/same54_xplained/board_config.h
Normal file
29
boards/same54_xplained/board_config.h
Normal file
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|
@ -0,0 +1,29 @@
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|||
#ifndef BOARD_CONFIG_H
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#define BOARD_CONFIG_H
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#define VENDOR_NAME "Microchip"
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#define PRODUCT_NAME "SAME54 Xplained"
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#define VOLUME_LABEL "E54XBOOT"
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#define INDEX_URL "https://www.microchip.com/developmenttools/ProductDetails/atsame54-xpro"
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#define BOARD_ID "SAME54P20A-Xplained-v0"
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#define USB_VID 0x239A
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#define USB_PID 0x00B5
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#define LED_PIN PIN_PC18
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#define BOARD_NEOPIXEL_PIN PIN_PC24
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#define BOARD_NEOPIXEL_COUNT 0
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#define BOOT_USART_MODULE SERCOM0
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#define BOOT_USART_MASK APBAMASK
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#define BOOT_USART_BUS_CLOCK_INDEX MCLK_APBAMASK_SERCOM0
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#define BOOT_USART_PAD_SETTINGS UART_RX_PAD1_TX_PAD0
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#define BOOT_USART_PAD3 PINMUX_UNUSED
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#define BOOT_USART_PAD2 PINMUX_UNUSED
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#define BOOT_USART_PAD1 PINMUX_PB25C_SERCOM0_PAD1
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#define BOOT_USART_PAD0 PINMUX_PB24C_SERCOM0_PAD0
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#define BOOT_GCLK_ID_CORE SERCOM0_GCLK_ID_CORE
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#define BOOT_GCLK_ID_SLOW SERCOM0_GCLK_ID_SLOW
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#endif
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37
inc/uf2.h
37
inc/uf2.h
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@ -275,8 +275,13 @@ void RGBLED_set_color(uint32_t color);
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// Not all targets have a LED
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#if defined(LED_PIN)
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#if !defined(LED_PIN_PULLUP)
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#define LED_MSC_OFF() PINOP(LED_PIN, OUTCLR)
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#define LED_MSC_ON() PINOP(LED_PIN, OUTSET)
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#else
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#define LED_MSC_OFF() PINOP(LED_PIN, OUTSET)
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#define LED_MSC_ON() PINOP(LED_PIN, OUTCLR)
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#endif
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#define LED_MSC_TGL() PINOP(LED_PIN, OUTTGL)
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#else
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#define LED_MSC_OFF()
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@ -284,6 +289,38 @@ void RGBLED_set_color(uint32_t color);
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#define LED_MSC_TGL()
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#endif
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// Not all targets have a TX LED
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#if defined(LED_TX_PIN)
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#if defined(LED_TX_PIN_PULLUP)
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#define LED_TX_OFF() PINOP(LED_TX_PIN, OUTSET)
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#define LED_TX_ON() PINOP(LED_TX_PIN, OUTCLR)
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#else
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#define LED_TX_OFF() PINOP(LED_TX_PIN, OUTCLR)
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#define LED_TX_ON() PINOP(LED_TX_PIN, OUTSET)
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#endif
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#define LED_TX_TGL() PINOP(LED_TX_PIN, OUTTGL)
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#else
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#define LED_TX_OFF()
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#define LED_TX_ON()
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#define LED_TX_TGL()
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#endif
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// Not all targets have a RX LED
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#if defined(LED_RX_PIN)
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#if defined(LED_RX_PIN_PULLUP)
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#define LED_RX_OFF() PINOP(LED_RX_PIN, OUTSET)
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#define LED_RX_ON() PINOP(LED_RX_PIN, OUTCLR)
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#else
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#define LED_RX_OFF() PINOP(LED_RX_PIN, OUTCLR)
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#define LED_RX_ON() PINOP(LED_RX_PIN, OUTSET)
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#endif
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#define LED_RX_TGL() PINOP(LED_RX_PIN, OUTTGL)
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#else
|
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#define LED_RX_OFF()
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#define LED_RX_ON()
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#define LED_RX_TGL()
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#endif
|
||||
|
||||
extern uint32_t timerHigh, resetHorizon;
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void timerTick(void);
|
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void delay(uint32_t ms);
|
||||
|
|
|
|||
727
lib/same51/Atmel.SAME51_DFP.pdsc
Normal file
727
lib/same51/Atmel.SAME51_DFP.pdsc
Normal file
|
|
@ -0,0 +1,727 @@
|
|||
<?xml version='1.0' encoding='ASCII'?>
|
||||
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.3" xs:schemaLocation="http://www.atmel.com/schemas/pack-device-atmel-extension PACK.DEVICE.ATMEL.EXTENSION.xsd" xs:noNamespaceSchemaLocation="PACK.xsd">
|
||||
<vendor>Atmel</vendor>
|
||||
<url>http://packs.download.atmel.com/</url>
|
||||
<name>SAME51_DFP</name>
|
||||
<description>Atmel SAME51 Series Device Support</description>
|
||||
<releases>
|
||||
<release version="1.1.139" date="2019-11-05">Support for ATSAME51G18A and ATSAME51G19A</release>
|
||||
<release version="1.1.129" date="2019-04-09">Fix: Modes in SVD, Value-group for USER_FUSES, define in GCLK. Added python programming and debugging scripts for MPLAB X.</release>
|
||||
<release version="1.0.85">Added ATSAME51J20A. Aligned PTC signal description with other SAM DFPs.</release>
|
||||
<release version="1.0.56">Initial version.</release>
|
||||
</releases>
|
||||
<keywords>
|
||||
<keyword>Atmel</keyword>
|
||||
<keyword>Device Family Package Atmel</keyword>
|
||||
<keyword>Device Support</keyword>
|
||||
<keyword>SAME51</keyword>
|
||||
</keywords>
|
||||
<devices>
|
||||
<family Dfamily="SAME51" Dvendor="Atmel:3">
|
||||
<environment name="microchip">
|
||||
<mchp:extension xmlns:mchp="http://crownking/pack-device-microchip-extension" schemaVersion="1.0">
|
||||
<mchp:prerequisite component="MPLAB X IDE" version="[5.10-"/>
|
||||
</mchp:extension>
|
||||
</environment>
|
||||
<device Dname="ATSAME51J19A">
|
||||
<processor Dcore="Cortex-M4" Dendian="Little-endian" Dmpu="MPU" Dfpu="SP_FPU"/>
|
||||
<compile header="include/sam.h" define="__SAME51J19A__"/>
|
||||
<debug svd="svd/ATSAME51J19A.svd"/>
|
||||
<memory id="IROM1" start="0x00000000" size="0x80000" default="1" startup="1"/>
|
||||
<memory id="IRAM1" start="0x20000000" size="0x30000" default="1"/>
|
||||
<memory id="IRAM2" start="0x20000000" size="0x8000"/>
|
||||
<memory id="IRAM3" start="0x20000000" size="0x8000"/>
|
||||
<memory id="IRAM4" start="0x47000000" size="0x2000"/>
|
||||
<algorithm name="keil/arm_addon/flash/ATSAME51_512.FLM" start="0x00000000" size="0x80000" default="1"/>
|
||||
<environment name="atmel">
|
||||
<at:extension xmlns:at="http://www.atmel.com/schemas/pack-device-atmel-extension" schemaVersion="1.0">
|
||||
<at:atdf name="atdf/ATSAME51J19A.atdf"/>
|
||||
<at:variant ordercode="SAME51J19A-MU" vccmin="1.71" vccmax="3.60" tempmin="-40" tempmax="85"/>
|
||||
<at:variant ordercode="SAME51J19A-MF" vccmin="1.71" vccmax="3.60" tempmin="-40" tempmax="125"/>
|
||||
<at:variant ordercode="SAME51J19A-MZ" vccmin="1.71" vccmax="3.60" tempmin="-40" tempmax="125"/>
|
||||
<at:variant ordercode="SAME51J19A-AU" vccmin="1.71" vccmax="3.60" tempmin="-40" tempmax="85"/>
|
||||
<at:variant ordercode="SAME51J19A-AF" vccmin="1.71" vccmax="3.60" tempmin="-40" tempmax="125"/>
|
||||
<at:variant ordercode="SAME51J19A-AZ" vccmin="1.71" vccmax="3.60" tempmin="-40" tempmax="125"/>
|
||||
<at:memory name="FLASH" start="0x00000000" size="0x80000" type="flash" pagesize="512" rw="RW" exec="true" address-space="base"/>
|
||||
<at:memory name="SW0" start="0x00800080" size="0x10" type="fuses" rw="R" address-space="base"/>
|
||||
<at:memory name="TEMP_LOG" start="0x00800100" size="0x200" type="fuses" pagesize="512" rw="RW" address-space="base"/>
|
||||
<at:memory name="USER_PAGE" start="0x00804000" size="0x200" type="user_page" pagesize="512" rw="RW" address-space="base"/>
|
||||
<at:memory name="CMCC" start="0x03000000" size="0x1000000" type="io" rw="RW" address-space="base"/>
|
||||
<at:memory name="CMCC_DATARAM" start="0x3000000" size="0x1000" type="io" rw="RW" address-space="base"/>
|
||||
<at:memory name="CMCC_TAGRAM" start="0x3001000" size="0x400" type="io" rw="RW" address-space="base"/>
|
||||
<at:memory name="CMCC_VALIDRAM" start="0x3002000" size="0x40" type="io" rw="RW" address-space="base"/>
|
||||
<at:memory name="QSPI" start="0x04000000" size="0x1000000" type="other" rw="RW" exec="true" external="true" address-space="base"/>
|
||||
<at:memory name="HSRAM" start="0x20000000" size="0x30000" type="ram" rw="RW" exec="true" address-space="base"/>
|
||||
<at:memory name="HSRAM_ETB" start="0x20000000" size="0x8000" type="ram" rw="RW" exec="true" address-space="base"/>
|
||||
<at:memory name="HSRAM_RET1" start="0x20000000" size="0x8000" type="ram" rw="RW" exec="true" address-space="base"/>
|
||||
<at:memory name="HPB0" start="0x40000000" size="0x4400" type="io" rw="RW" address-space="base"/>
|
||||
<at:memory name="HPB1" start="0x41000000" size="0x22000" type="io" rw="RW" address-space="base"/>
|
||||
<at:memory name="HPB2" start="0x42000000" size="0x3C00" type="io" rw="RW" address-space="base"/>
|
||||
<at:memory name="HPB3" start="0x43000000" size="0x3000" type="io" rw="RW" address-space="base"/>
|
||||
<at:memory name="SEEPROM" start="0x44000000" size="0x20000" type="io" rw="RW" address-space="base"/>
|
||||
<at:memory name="SDHC0" start="0x45000000" size="0xC00" type="io" rw="RW" address-space="base"/>
|
||||
<at:memory name="BKUPRAM" start="0x47000000" size="0x2000" type="ram" rw="RW" exec="true" address-space="base"/>
|
||||
<at:memory name="PPB" start="0xE0000000" size="0x100000" type="io" rw="RW" address-space="base"/>
|
||||
<at:memory name="SCS" start="0xE000E000" size="0x00001000" type="io" rw="RW" address-space="base"/>
|
||||
<at:interface type="swd" name="SWD"/>
|
||||
<at:tool id="com.atmel.avrdbg.tool.medbg"/>
|
||||
<at:tool id="com.atmel.avrdbg.tool.atmelice"/>
|
||||
<at:tool id="com.atmel.avrdbg.tool.pickit4"/>
|
||||
<at:tool id="com.atmel.avrdbg.tool.jtagicemk3"/>
|
||||
<at:tool id="com.atmel.avrdbg.tool.samice"/>
|
||||
<at:tool id="com.atmel.avrdbg.tool.snap"/>
|
||||
<at:tool id="com.atmel.avrdbg.tool.nedbg"/>
|
||||
<at:tool id="com.atmel.avrdbg.tool.edbgc"/>
|
||||
<at:tool id="com.atmel.avrdbg.tool.edbg"/>
|
||||
<at:tool id="com.atmel.avrdbg.tool.jtagice3plus"/>
|
||||
<at:tool id="com.atmel.avrdbg.tool.powerdebugger"/>
|
||||
<at:tool id="com.atmel.avrdbg.tool.edbg"/>
|
||||
<at:project name="Barebone C Project">
|
||||
<at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
|
||||
<at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
|
||||
<at:template select="Main file (.c)"/>
|
||||
</at:component>
|
||||
</at:project>
|
||||
<at:project name="Barebone Cpp Project">
|
||||
<at:component Cvendor="ARM" Cclass="CMSIS" Cgroup="CORE"/>
|
||||
<at:component Cvendor="Atmel" Cclass="Device" Cgroup="Startup">
|
||||
<at:template select="Main file (.cpp)"/>
|
||||
</at:component>
|
||||
</at:project>
|
||||
<at:prerequisite context="compiling" Tcompiler="GCC" component="ARM-GCC"/>
|
||||
<at:prerequisite context="compiling" Tcompiler="IAR" component="ARM-IAR"/>
|
||||
<at:prerequisite context="compiling" Tcompiler="ARMCC" component="ARMCC"/>
|
||||
</at:extension>
|
||||
</environment>
|
||||
<book name="https://www.microchip.com/wwwproducts/Devices.aspx?product=ATSAME51J19A" title="Device page for ATSAME51J19A"/>
|
||||
<book name="https://www.microchip.com/wwwproducts/productds/ATSAME51J19A" title="Datasheet"/>
|
||||
</device>
|
||||
<device Dname="ATSAME51J20A">
|
||||
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|
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
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|
||||
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||||
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|
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||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
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|
||||
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|
||||
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|
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|
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|
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|
||||
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||||
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|
||||
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|
||||
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|
||||
<book name="https://www.microchip.com/wwwproducts/productds/ATSAME51J18A" title="Datasheet"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
</condition>
|
||||
<condition id="GCC">
|
||||
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|
||||
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|
||||
<condition id="GCC Exe">
|
||||
<accept Tcompiler="GCC" Toutput="exe"/>
|
||||
</condition>
|
||||
<condition id="IAR">
|
||||
<accept Tcompiler="IAR"/>
|
||||
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|
||||
<condition id="IAR Exe">
|
||||
<accept Tcompiler="IAR" Toutput="exe"/>
|
||||
</condition>
|
||||
<condition id="C">
|
||||
<accept Tcompiler="ARMCC"/>
|
||||
<accept Tcompiler="GCC"/>
|
||||
<accept Tcompiler="IAR"/>
|
||||
</condition>
|
||||
<condition id="C Exe">
|
||||
<accept Tcompiler="ARMCC" Toutput="exe"/>
|
||||
<accept Tcompiler="GCC" Toutput="exe"/>
|
||||
<accept Tcompiler="IAR" Toutput="exe"/>
|
||||
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|
||||
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|
||||
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|
||||
<accept Tcompiler="GCC" Toutput="lib"/>
|
||||
<accept Tcompiler="IAR" Toutput="lib"/>
|
||||
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|
||||
<condition id="ATSAME51J19A">
|
||||
<require Dvendor="Atmel:3" Dname="ATSAME51J19A"/>
|
||||
<require Cclass="CMSIS" Cgroup="CORE"/>
|
||||
</condition>
|
||||
<condition id="ATSAME51J20A">
|
||||
<require Dvendor="Atmel:3" Dname="ATSAME51J20A"/>
|
||||
<require Cclass="CMSIS" Cgroup="CORE"/>
|
||||
</condition>
|
||||
<condition id="ATSAME51G19A">
|
||||
<require Dvendor="Atmel:3" Dname="ATSAME51G19A"/>
|
||||
<require Cclass="CMSIS" Cgroup="CORE"/>
|
||||
</condition>
|
||||
<condition id="ATSAME51G18A">
|
||||
<require Dvendor="Atmel:3" Dname="ATSAME51G18A"/>
|
||||
<require Cclass="CMSIS" Cgroup="CORE"/>
|
||||
</condition>
|
||||
<condition id="ATSAME51N19A">
|
||||
<require Dvendor="Atmel:3" Dname="ATSAME51N19A"/>
|
||||
<require Cclass="CMSIS" Cgroup="CORE"/>
|
||||
</condition>
|
||||
<condition id="ATSAME51N20A">
|
||||
<require Dvendor="Atmel:3" Dname="ATSAME51N20A"/>
|
||||
<require Cclass="CMSIS" Cgroup="CORE"/>
|
||||
</condition>
|
||||
<condition id="ATSAME51J18A">
|
||||
<require Dvendor="Atmel:3" Dname="ATSAME51J18A"/>
|
||||
<require Cclass="CMSIS" Cgroup="CORE"/>
|
||||
</condition>
|
||||
</conditions>
|
||||
<components>
|
||||
<component Cvendor="Atmel" Cclass="Device" Cgroup="Startup" Cversion="1.1.0" condition="ATSAME51J19A">
|
||||
<description>Headers and startup code for Atmel ATSAME51J19A</description>
|
||||
<files>
|
||||
<file condition="C" category="include" name="include"/>
|
||||
<file condition="C" category="header" name="include/sam.h"/>
|
||||
<file condition="C Exe" category="source" name="templates/main.c" attr="template" select="Main file (.c)"/>
|
||||
<file condition="C Exe" category="source" name="templates/main.cpp" attr="template" select="Main file (.cpp)"/>
|
||||
<file condition="C Lib" category="source" name="templates/library.c" attr="template" select="Main file (.c)"/>
|
||||
<file condition="C Lib" category="source" name="templates/library.cpp" attr="template" select="Main file (.cpp)"/>
|
||||
<file condition="GCC Exe" category="source" name="gcc/system_same51.c" attr="config"/>
|
||||
<file condition="GCC Exe" category="source" name="gcc/gcc/startup_same51.c" attr="config"/>
|
||||
<file condition="GCC Exe" category="linkerScript" name="gcc/gcc/same51j19a_flash.ld" attr="config"/>
|
||||
<file condition="GCC Exe" category="other" name="gcc/gcc/same51j19a_sram.ld" attr="config"/>
|
||||
<file condition="ARMCC Exe" category="source" name="armcc/arm_addon/armcc/system_same51.c" attr="config"/>
|
||||
<file condition="ARMCC Exe" category="source" name="armcc/arm_addon/armcc/arm/startup_same51.s" attr="config"/>
|
||||
<file condition="IAR Exe" category="source" name="iar/system_same51.c" attr="config"/>
|
||||
<file condition="IAR Exe" category="source" name="iar/iar/startup_same51.c" attr="config"/>
|
||||
<file condition="IAR Exe" category="linkerScript" name="iar/iar/same51j19a_flash.icf" attr="config"/>
|
||||
<file condition="IAR Exe" category="other" name="iar/iar/same51j19a_sram.icf" attr="config"/>
|
||||
</files>
|
||||
</component>
|
||||
<component Cvendor="Atmel" Cclass="Device" Cgroup="Startup" Cversion="1.1.0" condition="ATSAME51J20A">
|
||||
<description>Headers and startup code for Atmel ATSAME51J20A</description>
|
||||
<files>
|
||||
<file condition="C" category="include" name="include"/>
|
||||
<file condition="C" category="header" name="include/sam.h"/>
|
||||
<file condition="C Exe" category="source" name="templates/main.c" attr="template" select="Main file (.c)"/>
|
||||
<file condition="C Exe" category="source" name="templates/main.cpp" attr="template" select="Main file (.cpp)"/>
|
||||
<file condition="C Lib" category="source" name="templates/library.c" attr="template" select="Main file (.c)"/>
|
||||
<file condition="C Lib" category="source" name="templates/library.cpp" attr="template" select="Main file (.cpp)"/>
|
||||
<file condition="GCC Exe" category="source" name="gcc/system_same51.c" attr="config"/>
|
||||
<file condition="GCC Exe" category="source" name="gcc/gcc/startup_same51.c" attr="config"/>
|
||||
<file condition="GCC Exe" category="linkerScript" name="gcc/gcc/same51j20a_flash.ld" attr="config"/>
|
||||
<file condition="GCC Exe" category="other" name="gcc/gcc/same51j20a_sram.ld" attr="config"/>
|
||||
<file condition="IAR Exe" category="source" name="iar/system_same51.c" attr="config"/>
|
||||
<file condition="IAR Exe" category="source" name="iar/iar/startup_same51.c" attr="config"/>
|
||||
<file condition="IAR Exe" category="linkerScript" name="iar/iar/same51j20a_flash.icf" attr="config"/>
|
||||
<file condition="IAR Exe" category="other" name="iar/iar/same51j20a_sram.icf" attr="config"/>
|
||||
</files>
|
||||
</component>
|
||||
<component Cvendor="Atmel" Cclass="Device" Cgroup="Startup" Cversion="1.1.0" condition="ATSAME51G19A">
|
||||
<description>Headers and startup code for Atmel ATSAME51G19A</description>
|
||||
<files>
|
||||
<file condition="C" category="include" name="include"/>
|
||||
<file condition="C" category="header" name="include/sam.h"/>
|
||||
<file condition="C Exe" category="source" name="templates/main.c" attr="template" select="Main file (.c)"/>
|
||||
<file condition="C Exe" category="source" name="templates/main.cpp" attr="template" select="Main file (.cpp)"/>
|
||||
<file condition="C Lib" category="source" name="templates/library.c" attr="template" select="Main file (.c)"/>
|
||||
<file condition="C Lib" category="source" name="templates/library.cpp" attr="template" select="Main file (.cpp)"/>
|
||||
<file condition="GCC Exe" category="source" name="gcc/system_same51.c" attr="config"/>
|
||||
<file condition="GCC Exe" category="source" name="gcc/gcc/startup_same51.c" attr="config"/>
|
||||
<file condition="GCC Exe" category="linkerScript" name="gcc/gcc/same51g19a_flash.ld" attr="config"/>
|
||||
<file condition="GCC Exe" category="other" name="gcc/gcc/same51g19a_sram.ld" attr="config"/>
|
||||
<file condition="IAR Exe" category="source" name="iar/system_same51.c" attr="config"/>
|
||||
<file condition="IAR Exe" category="source" name="iar/iar/startup_same51.c" attr="config"/>
|
||||
<file condition="IAR Exe" category="linkerScript" name="iar/iar/same51g19a_flash.icf" attr="config"/>
|
||||
<file condition="IAR Exe" category="other" name="iar/iar/same51g19a_sram.icf" attr="config"/>
|
||||
</files>
|
||||
</component>
|
||||
<component Cvendor="Atmel" Cclass="Device" Cgroup="Startup" Cversion="1.1.0" condition="ATSAME51G18A">
|
||||
<description>Headers and startup code for Atmel ATSAME51G18A</description>
|
||||
<files>
|
||||
<file condition="C" category="include" name="include"/>
|
||||
<file condition="C" category="header" name="include/sam.h"/>
|
||||
<file condition="C Exe" category="source" name="templates/main.c" attr="template" select="Main file (.c)"/>
|
||||
<file condition="C Exe" category="source" name="templates/main.cpp" attr="template" select="Main file (.cpp)"/>
|
||||
<file condition="C Lib" category="source" name="templates/library.c" attr="template" select="Main file (.c)"/>
|
||||
<file condition="C Lib" category="source" name="templates/library.cpp" attr="template" select="Main file (.cpp)"/>
|
||||
<file condition="GCC Exe" category="source" name="gcc/system_same51.c" attr="config"/>
|
||||
<file condition="GCC Exe" category="source" name="gcc/gcc/startup_same51.c" attr="config"/>
|
||||
<file condition="GCC Exe" category="linkerScript" name="gcc/gcc/same51g18a_flash.ld" attr="config"/>
|
||||
<file condition="GCC Exe" category="other" name="gcc/gcc/same51g18a_sram.ld" attr="config"/>
|
||||
<file condition="IAR Exe" category="source" name="iar/system_same51.c" attr="config"/>
|
||||
<file condition="IAR Exe" category="source" name="iar/iar/startup_same51.c" attr="config"/>
|
||||
<file condition="IAR Exe" category="linkerScript" name="iar/iar/same51g18a_flash.icf" attr="config"/>
|
||||
<file condition="IAR Exe" category="other" name="iar/iar/same51g18a_sram.icf" attr="config"/>
|
||||
</files>
|
||||
</component>
|
||||
<component Cvendor="Atmel" Cclass="Device" Cgroup="Startup" Cversion="1.1.0" condition="ATSAME51N19A">
|
||||
<description>Headers and startup code for Atmel ATSAME51N19A</description>
|
||||
<files>
|
||||
<file condition="C" category="include" name="include"/>
|
||||
<file condition="C" category="header" name="include/sam.h"/>
|
||||
<file condition="C Exe" category="source" name="templates/main.c" attr="template" select="Main file (.c)"/>
|
||||
<file condition="C Exe" category="source" name="templates/main.cpp" attr="template" select="Main file (.cpp)"/>
|
||||
<file condition="C Lib" category="source" name="templates/library.c" attr="template" select="Main file (.c)"/>
|
||||
<file condition="C Lib" category="source" name="templates/library.cpp" attr="template" select="Main file (.cpp)"/>
|
||||
<file condition="GCC Exe" category="source" name="gcc/system_same51.c" attr="config"/>
|
||||
<file condition="GCC Exe" category="source" name="gcc/gcc/startup_same51.c" attr="config"/>
|
||||
<file condition="GCC Exe" category="linkerScript" name="gcc/gcc/same51n19a_flash.ld" attr="config"/>
|
||||
<file condition="GCC Exe" category="other" name="gcc/gcc/same51n19a_sram.ld" attr="config"/>
|
||||
<file condition="ARMCC Exe" category="source" name="armcc/arm_addon/armcc/system_same51.c" attr="config"/>
|
||||
<file condition="ARMCC Exe" category="source" name="armcc/arm_addon/armcc/arm/startup_same51.s" attr="config"/>
|
||||
<file condition="IAR Exe" category="source" name="iar/system_same51.c" attr="config"/>
|
||||
<file condition="IAR Exe" category="source" name="iar/iar/startup_same51.c" attr="config"/>
|
||||
<file condition="IAR Exe" category="linkerScript" name="iar/iar/same51n19a_flash.icf" attr="config"/>
|
||||
<file condition="IAR Exe" category="other" name="iar/iar/same51n19a_sram.icf" attr="config"/>
|
||||
</files>
|
||||
</component>
|
||||
<component Cvendor="Atmel" Cclass="Device" Cgroup="Startup" Cversion="1.1.0" condition="ATSAME51N20A">
|
||||
<description>Headers and startup code for Atmel ATSAME51N20A</description>
|
||||
<files>
|
||||
<file condition="C" category="include" name="include"/>
|
||||
<file condition="C" category="header" name="include/sam.h"/>
|
||||
<file condition="C Exe" category="source" name="templates/main.c" attr="template" select="Main file (.c)"/>
|
||||
<file condition="C Exe" category="source" name="templates/main.cpp" attr="template" select="Main file (.cpp)"/>
|
||||
<file condition="C Lib" category="source" name="templates/library.c" attr="template" select="Main file (.c)"/>
|
||||
<file condition="C Lib" category="source" name="templates/library.cpp" attr="template" select="Main file (.cpp)"/>
|
||||
<file condition="GCC Exe" category="source" name="gcc/system_same51.c" attr="config"/>
|
||||
<file condition="GCC Exe" category="source" name="gcc/gcc/startup_same51.c" attr="config"/>
|
||||
<file condition="GCC Exe" category="linkerScript" name="gcc/gcc/same51n20a_flash.ld" attr="config"/>
|
||||
<file condition="GCC Exe" category="other" name="gcc/gcc/same51n20a_sram.ld" attr="config"/>
|
||||
<file condition="ARMCC Exe" category="source" name="armcc/arm_addon/armcc/system_same51.c" attr="config"/>
|
||||
<file condition="ARMCC Exe" category="source" name="armcc/arm_addon/armcc/arm/startup_same51.s" attr="config"/>
|
||||
<file condition="IAR Exe" category="source" name="iar/system_same51.c" attr="config"/>
|
||||
<file condition="IAR Exe" category="source" name="iar/iar/startup_same51.c" attr="config"/>
|
||||
<file condition="IAR Exe" category="linkerScript" name="iar/iar/same51n20a_flash.icf" attr="config"/>
|
||||
<file condition="IAR Exe" category="other" name="iar/iar/same51n20a_sram.icf" attr="config"/>
|
||||
</files>
|
||||
</component>
|
||||
<component Cvendor="Atmel" Cclass="Device" Cgroup="Startup" Cversion="1.1.0" condition="ATSAME51J18A">
|
||||
<description>Headers and startup code for Atmel ATSAME51J18A</description>
|
||||
<files>
|
||||
<file condition="C" category="include" name="include"/>
|
||||
<file condition="C" category="header" name="include/sam.h"/>
|
||||
<file condition="C Exe" category="source" name="templates/main.c" attr="template" select="Main file (.c)"/>
|
||||
<file condition="C Exe" category="source" name="templates/main.cpp" attr="template" select="Main file (.cpp)"/>
|
||||
<file condition="C Lib" category="source" name="templates/library.c" attr="template" select="Main file (.c)"/>
|
||||
<file condition="C Lib" category="source" name="templates/library.cpp" attr="template" select="Main file (.cpp)"/>
|
||||
<file condition="GCC Exe" category="source" name="gcc/system_same51.c" attr="config"/>
|
||||
<file condition="GCC Exe" category="source" name="gcc/gcc/startup_same51.c" attr="config"/>
|
||||
<file condition="GCC Exe" category="linkerScript" name="gcc/gcc/same51j18a_flash.ld" attr="config"/>
|
||||
<file condition="GCC Exe" category="other" name="gcc/gcc/same51j18a_sram.ld" attr="config"/>
|
||||
<file condition="ARMCC Exe" category="source" name="armcc/arm_addon/armcc/system_same51.c" attr="config"/>
|
||||
<file condition="ARMCC Exe" category="source" name="armcc/arm_addon/armcc/arm/startup_same51.s" attr="config"/>
|
||||
<file condition="IAR Exe" category="source" name="iar/system_same51.c" attr="config"/>
|
||||
<file condition="IAR Exe" category="source" name="iar/iar/startup_same51.c" attr="config"/>
|
||||
<file condition="IAR Exe" category="linkerScript" name="iar/iar/same51j18a_flash.icf" attr="config"/>
|
||||
<file condition="IAR Exe" category="other" name="iar/iar/same51j18a_sram.icf" attr="config"/>
|
||||
</files>
|
||||
</component>
|
||||
</components>
|
||||
</package>
|
||||
588
lib/same51/armcc/arm_addon/armcc/arm/startup_same51.s
Normal file
588
lib/same51/armcc/arm_addon/armcc/arm/startup_same51.s
Normal file
|
|
@ -0,0 +1,588 @@
|
|||
;/*****************************************************************************
|
||||
; * @file startup_same51.s
|
||||
; * @brief CMSIS Cortex-M4 Core Device Startup File for
|
||||
; * Atmel SAME51 Device Series
|
||||
; * @version V1.0.0
|
||||
; * @date 16. January 2017
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2017 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000200
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD PM_Handler ; 0 Power Manager
|
||||
DCD MCLK_Handler ; 1 Main Clock
|
||||
DCD OSCCTRL_0_Handler ; 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0
|
||||
DCD OSCCTRL_1_Handler ; 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1
|
||||
DCD OSCCTRL_2_Handler ; 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY
|
||||
DCD OSCCTRL_3_Handler ; 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0
|
||||
DCD OSCCTRL_4_Handler ; 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1
|
||||
DCD OSC32KCTRL_Handler ; 7 32kHz Oscillators Control
|
||||
DCD SUPC_0_Handler ; 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY
|
||||
DCD SUPC_1_Handler ; 9 SUPC_BOD12DET, SUPC_BOD33DET
|
||||
DCD WDT_Handler ; 10 Watchdog Timer
|
||||
DCD RTC_Handler ; 11 Real-Time Counter
|
||||
DCD EIC_0_Handler ; 12 EIC_EXTINT_0
|
||||
DCD EIC_1_Handler ; 13 EIC_EXTINT_1
|
||||
DCD EIC_2_Handler ; 14 EIC_EXTINT_2
|
||||
DCD EIC_3_Handler ; 15 EIC_EXTINT_3
|
||||
DCD EIC_4_Handler ; 16 EIC_EXTINT_4
|
||||
DCD EIC_5_Handler ; 17 EIC_EXTINT_5
|
||||
DCD EIC_6_Handler ; 18 EIC_EXTINT_6
|
||||
DCD EIC_7_Handler ; 19 EIC_EXTINT_7
|
||||
DCD EIC_8_Handler ; 20 EIC_EXTINT_8
|
||||
DCD EIC_9_Handler ; 21 EIC_EXTINT_9
|
||||
DCD EIC_10_Handler ; 22 EIC_EXTINT_10
|
||||
DCD EIC_11_Handler ; 23 EIC_EXTINT_11
|
||||
DCD EIC_12_Handler ; 24 EIC_EXTINT_12
|
||||
DCD EIC_13_Handler ; 25 EIC_EXTINT_13
|
||||
DCD EIC_14_Handler ; 26 EIC_EXTINT_14
|
||||
DCD EIC_15_Handler ; 27 EIC_EXTINT_15
|
||||
DCD FREQM_Handler ; 28 Frequency Meter
|
||||
DCD NVMCTRL_0_Handler ; 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7
|
||||
DCD NVMCTRL_1_Handler ; 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9
|
||||
DCD DMAC_0_Handler ; 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0
|
||||
DCD DMAC_1_Handler ; 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1
|
||||
DCD DMAC_2_Handler ; 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2
|
||||
DCD DMAC_3_Handler ; 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3
|
||||
DCD DMAC_4_Handler ; 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9
|
||||
DCD EVSYS_0_Handler ; 36 EVSYS_EVD_0, EVSYS_OVR_0
|
||||
DCD EVSYS_1_Handler ; 37 EVSYS_EVD_1, EVSYS_OVR_1
|
||||
DCD EVSYS_2_Handler ; 38 EVSYS_EVD_2, EVSYS_OVR_2
|
||||
DCD EVSYS_3_Handler ; 39 EVSYS_EVD_3, EVSYS_OVR_3
|
||||
DCD EVSYS_4_Handler ; 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9
|
||||
DCD PAC_Handler ; 41 Peripheral Access Controller
|
||||
DCD TAL_0_Handler ; 42 TAL_BRK
|
||||
DCD TAL_1_Handler ; 43 TAL_IPS_0, TAL_IPS_1
|
||||
DCD 0 ; 44 Reserved
|
||||
DCD RAMECC_Handler ; 45 RAM ECC
|
||||
DCD SERCOM0_0_Handler ; 46 SERCOM0_0
|
||||
DCD SERCOM0_1_Handler ; 47 SERCOM0_1
|
||||
DCD SERCOM0_2_Handler ; 48 SERCOM0_2
|
||||
DCD SERCOM0_3_Handler ; 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6
|
||||
DCD SERCOM1_0_Handler ; 50 SERCOM1_0
|
||||
DCD SERCOM1_1_Handler ; 51 SERCOM1_1
|
||||
DCD SERCOM1_2_Handler ; 52 SERCOM1_2
|
||||
DCD SERCOM1_3_Handler ; 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6
|
||||
DCD SERCOM2_0_Handler ; 54 SERCOM2_0
|
||||
DCD SERCOM2_1_Handler ; 55 SERCOM2_1
|
||||
DCD SERCOM2_2_Handler ; 56 SERCOM2_2
|
||||
DCD SERCOM2_3_Handler ; 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6
|
||||
DCD SERCOM3_0_Handler ; 58 SERCOM3_0
|
||||
DCD SERCOM3_1_Handler ; 59 SERCOM3_1
|
||||
DCD SERCOM3_2_Handler ; 60 SERCOM3_2
|
||||
DCD SERCOM3_3_Handler ; 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6
|
||||
DCD SERCOM4_0_Handler ; 62 SERCOM4_0
|
||||
DCD SERCOM4_1_Handler ; 63 SERCOM4_1
|
||||
DCD SERCOM4_2_Handler ; 64 SERCOM4_2
|
||||
DCD SERCOM4_3_Handler ; 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6
|
||||
DCD SERCOM5_0_Handler ; 66 SERCOM5_0
|
||||
DCD SERCOM5_1_Handler ; 67 SERCOM5_1
|
||||
DCD SERCOM5_2_Handler ; 68 SERCOM5_2
|
||||
DCD SERCOM5_3_Handler ; 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6
|
||||
DCD SERCOM6_0_Handler ; 70 SERCOM6_0
|
||||
DCD SERCOM6_1_Handler ; 71 SERCOM6_1
|
||||
DCD SERCOM6_2_Handler ; 72 SERCOM6_2
|
||||
DCD SERCOM6_3_Handler ; 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6
|
||||
DCD SERCOM7_0_Handler ; 74 SERCOM7_0
|
||||
DCD SERCOM7_1_Handler ; 75 SERCOM7_1
|
||||
DCD SERCOM7_2_Handler ; 76 SERCOM7_2
|
||||
DCD SERCOM7_3_Handler ; 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6
|
||||
DCD CAN0_Handler ; 78 Control Area Network 0
|
||||
DCD CAN1_Handler ; 79 Control Area Network 1
|
||||
DCD USB_0_Handler ; 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP
|
||||
DCD USB_1_Handler ; 81 USB_SOF_HSOF
|
||||
DCD USB_2_Handler ; 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7
|
||||
DCD USB_3_Handler ; 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7
|
||||
DCD GMAC_Handler ; 84 Ethernet MAC
|
||||
DCD TCC0_0_Handler ; 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A
|
||||
DCD TCC0_1_Handler ; 86 TCC0_MC_0
|
||||
DCD TCC0_2_Handler ; 87 TCC0_MC_1
|
||||
DCD TCC0_3_Handler ; 88 TCC0_MC_2
|
||||
DCD TCC0_4_Handler ; 89 TCC0_MC_3
|
||||
DCD TCC0_5_Handler ; 90 TCC0_MC_4
|
||||
DCD TCC0_6_Handler ; 91 TCC0_MC_5
|
||||
DCD TCC1_0_Handler ; 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A
|
||||
DCD TCC1_1_Handler ; 93 TCC1_MC_0
|
||||
DCD TCC1_2_Handler ; 94 TCC1_MC_1
|
||||
DCD TCC1_3_Handler ; 95 TCC1_MC_2
|
||||
DCD TCC1_4_Handler ; 96 TCC1_MC_3
|
||||
DCD TCC2_0_Handler ; 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A
|
||||
DCD TCC2_1_Handler ; 98 TCC2_MC_0
|
||||
DCD TCC2_2_Handler ; 99 TCC2_MC_1
|
||||
DCD TCC2_3_Handler ; 100 TCC2_MC_2
|
||||
DCD TCC3_0_Handler ; 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A
|
||||
DCD TCC3_1_Handler ; 102 TCC3_MC_0
|
||||
DCD TCC3_2_Handler ; 103 TCC3_MC_1
|
||||
DCD TCC4_0_Handler ; 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A
|
||||
DCD TCC4_1_Handler ; 105 TCC4_MC_0
|
||||
DCD TCC4_2_Handler ; 106 TCC4_MC_1
|
||||
DCD TC0_Handler ; 107 Basic Timer Counter 0
|
||||
DCD TC1_Handler ; 108 Basic Timer Counter 1
|
||||
DCD TC2_Handler ; 109 Basic Timer Counter 2
|
||||
DCD TC3_Handler ; 110 Basic Timer Counter 3
|
||||
DCD TC4_Handler ; 111 Basic Timer Counter 4
|
||||
DCD TC5_Handler ; 112 Basic Timer Counter 5
|
||||
DCD TC6_Handler ; 113 Basic Timer Counter 6
|
||||
DCD TC7_Handler ; 114 Basic Timer Counter 7
|
||||
DCD PDEC_0_Handler ; 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A
|
||||
DCD PDEC_1_Handler ; 116 PDEC_MC_0
|
||||
DCD PDEC_2_Handler ; 117 PDEC_MC_1
|
||||
DCD ADC0_0_Handler ; 118 ADC0_OVERRUN, ADC0_WINMON
|
||||
DCD ADC0_1_Handler ; 119 ADC0_RESRDY
|
||||
DCD ADC1_0_Handler ; 120 ADC1_OVERRUN, ADC1_WINMON
|
||||
DCD ADC1_1_Handler ; 121 ADC1_RESRDY
|
||||
DCD AC_Handler ; 122 Analog Comparators
|
||||
DCD DAC_0_Handler ; 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1
|
||||
DCD DAC_1_Handler ; 124 DAC_EMPTY_0
|
||||
DCD DAC_2_Handler ; 125 DAC_EMPTY_1
|
||||
DCD DAC_3_Handler ; 126 DAC_RESRDY_0
|
||||
DCD DAC_4_Handler ; 127 DAC_RESRDY_1
|
||||
DCD I2S_Handler ; 128 Inter-IC Sound Interface
|
||||
DCD PCC_Handler ; 129 Parallel Capture Controller
|
||||
DCD AES_Handler ; 130 Advanced Encryption Standard
|
||||
DCD TRNG_Handler ; 131 True Random Generator
|
||||
DCD ICM_Handler ; 132 Integrity Check Monitor
|
||||
DCD PUKCC_Handler ; 133 PUblic-Key Cryptography Controller
|
||||
DCD QSPI_Handler ; 134 Quad SPI interface
|
||||
DCD SDHC0_Handler ; 135 SD/MMC Host Controller 0
|
||||
DCD SDHC1_Handler ; 136 SD/MMC Host Controller 1
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT PM_Handler [WEAK]
|
||||
EXPORT MCLK_Handler [WEAK]
|
||||
EXPORT OSCCTRL_0_Handler [WEAK]
|
||||
EXPORT OSCCTRL_1_Handler [WEAK]
|
||||
EXPORT OSCCTRL_2_Handler [WEAK]
|
||||
EXPORT OSCCTRL_3_Handler [WEAK]
|
||||
EXPORT OSCCTRL_4_Handler [WEAK]
|
||||
EXPORT OSC32KCTRL_Handler [WEAK]
|
||||
EXPORT SUPC_0_Handler [WEAK]
|
||||
EXPORT SUPC_1_Handler [WEAK]
|
||||
EXPORT WDT_Handler [WEAK]
|
||||
EXPORT RTC_Handler [WEAK]
|
||||
EXPORT EIC_0_Handler [WEAK]
|
||||
EXPORT EIC_1_Handler [WEAK]
|
||||
EXPORT EIC_2_Handler [WEAK]
|
||||
EXPORT EIC_3_Handler [WEAK]
|
||||
EXPORT EIC_4_Handler [WEAK]
|
||||
EXPORT EIC_5_Handler [WEAK]
|
||||
EXPORT EIC_6_Handler [WEAK]
|
||||
EXPORT EIC_7_Handler [WEAK]
|
||||
EXPORT EIC_8_Handler [WEAK]
|
||||
EXPORT EIC_9_Handler [WEAK]
|
||||
EXPORT EIC_10_Handler [WEAK]
|
||||
EXPORT EIC_11_Handler [WEAK]
|
||||
EXPORT EIC_12_Handler [WEAK]
|
||||
EXPORT EIC_13_Handler [WEAK]
|
||||
EXPORT EIC_14_Handler [WEAK]
|
||||
EXPORT EIC_15_Handler [WEAK]
|
||||
EXPORT FREQM_Handler [WEAK]
|
||||
EXPORT NVMCTRL_0_Handler [WEAK]
|
||||
EXPORT NVMCTRL_1_Handler [WEAK]
|
||||
EXPORT DMAC_0_Handler [WEAK]
|
||||
EXPORT DMAC_1_Handler [WEAK]
|
||||
EXPORT DMAC_2_Handler [WEAK]
|
||||
EXPORT DMAC_3_Handler [WEAK]
|
||||
EXPORT DMAC_4_Handler [WEAK]
|
||||
EXPORT EVSYS_0_Handler [WEAK]
|
||||
EXPORT EVSYS_1_Handler [WEAK]
|
||||
EXPORT EVSYS_2_Handler [WEAK]
|
||||
EXPORT EVSYS_3_Handler [WEAK]
|
||||
EXPORT EVSYS_4_Handler [WEAK]
|
||||
EXPORT PAC_Handler [WEAK]
|
||||
EXPORT TAL_0_Handler [WEAK]
|
||||
EXPORT TAL_1_Handler [WEAK]
|
||||
EXPORT RAMECC_Handler [WEAK]
|
||||
EXPORT SERCOM0_0_Handler [WEAK]
|
||||
EXPORT SERCOM0_1_Handler [WEAK]
|
||||
EXPORT SERCOM0_2_Handler [WEAK]
|
||||
EXPORT SERCOM0_3_Handler [WEAK]
|
||||
EXPORT SERCOM1_0_Handler [WEAK]
|
||||
EXPORT SERCOM1_1_Handler [WEAK]
|
||||
EXPORT SERCOM1_2_Handler [WEAK]
|
||||
EXPORT SERCOM1_3_Handler [WEAK]
|
||||
EXPORT SERCOM2_0_Handler [WEAK]
|
||||
EXPORT SERCOM2_1_Handler [WEAK]
|
||||
EXPORT SERCOM2_2_Handler [WEAK]
|
||||
EXPORT SERCOM2_3_Handler [WEAK]
|
||||
EXPORT SERCOM3_0_Handler [WEAK]
|
||||
EXPORT SERCOM3_1_Handler [WEAK]
|
||||
EXPORT SERCOM3_2_Handler [WEAK]
|
||||
EXPORT SERCOM3_3_Handler [WEAK]
|
||||
EXPORT SERCOM4_0_Handler [WEAK]
|
||||
EXPORT SERCOM4_1_Handler [WEAK]
|
||||
EXPORT SERCOM4_2_Handler [WEAK]
|
||||
EXPORT SERCOM4_3_Handler [WEAK]
|
||||
EXPORT SERCOM5_0_Handler [WEAK]
|
||||
EXPORT SERCOM5_1_Handler [WEAK]
|
||||
EXPORT SERCOM5_2_Handler [WEAK]
|
||||
EXPORT SERCOM5_3_Handler [WEAK]
|
||||
EXPORT SERCOM6_0_Handler [WEAK]
|
||||
EXPORT SERCOM6_1_Handler [WEAK]
|
||||
EXPORT SERCOM6_2_Handler [WEAK]
|
||||
EXPORT SERCOM6_3_Handler [WEAK]
|
||||
EXPORT SERCOM7_0_Handler [WEAK]
|
||||
EXPORT SERCOM7_1_Handler [WEAK]
|
||||
EXPORT SERCOM7_2_Handler [WEAK]
|
||||
EXPORT SERCOM7_3_Handler [WEAK]
|
||||
EXPORT CAN0_Handler [WEAK]
|
||||
EXPORT CAN1_Handler [WEAK]
|
||||
EXPORT USB_0_Handler [WEAK]
|
||||
EXPORT USB_1_Handler [WEAK]
|
||||
EXPORT USB_2_Handler [WEAK]
|
||||
EXPORT USB_3_Handler [WEAK]
|
||||
EXPORT GMAC_Handler [WEAK]
|
||||
EXPORT TCC0_0_Handler [WEAK]
|
||||
EXPORT TCC0_1_Handler [WEAK]
|
||||
EXPORT TCC0_2_Handler [WEAK]
|
||||
EXPORT TCC0_3_Handler [WEAK]
|
||||
EXPORT TCC0_4_Handler [WEAK]
|
||||
EXPORT TCC0_5_Handler [WEAK]
|
||||
EXPORT TCC0_6_Handler [WEAK]
|
||||
EXPORT TCC1_0_Handler [WEAK]
|
||||
EXPORT TCC1_1_Handler [WEAK]
|
||||
EXPORT TCC1_2_Handler [WEAK]
|
||||
EXPORT TCC1_3_Handler [WEAK]
|
||||
EXPORT TCC1_4_Handler [WEAK]
|
||||
EXPORT TCC2_0_Handler [WEAK]
|
||||
EXPORT TCC2_1_Handler [WEAK]
|
||||
EXPORT TCC2_2_Handler [WEAK]
|
||||
EXPORT TCC2_3_Handler [WEAK]
|
||||
EXPORT TCC3_0_Handler [WEAK]
|
||||
EXPORT TCC3_1_Handler [WEAK]
|
||||
EXPORT TCC3_2_Handler [WEAK]
|
||||
EXPORT TCC4_0_Handler [WEAK]
|
||||
EXPORT TCC4_1_Handler [WEAK]
|
||||
EXPORT TCC4_2_Handler [WEAK]
|
||||
EXPORT TC0_Handler [WEAK]
|
||||
EXPORT TC1_Handler [WEAK]
|
||||
EXPORT TC2_Handler [WEAK]
|
||||
EXPORT TC3_Handler [WEAK]
|
||||
EXPORT TC4_Handler [WEAK]
|
||||
EXPORT TC5_Handler [WEAK]
|
||||
EXPORT TC6_Handler [WEAK]
|
||||
EXPORT TC7_Handler [WEAK]
|
||||
EXPORT PDEC_0_Handler [WEAK]
|
||||
EXPORT PDEC_1_Handler [WEAK]
|
||||
EXPORT PDEC_2_Handler [WEAK]
|
||||
EXPORT ADC0_0_Handler [WEAK]
|
||||
EXPORT ADC0_1_Handler [WEAK]
|
||||
EXPORT ADC1_0_Handler [WEAK]
|
||||
EXPORT ADC1_1_Handler [WEAK]
|
||||
EXPORT AC_Handler [WEAK]
|
||||
EXPORT DAC_0_Handler [WEAK]
|
||||
EXPORT DAC_1_Handler [WEAK]
|
||||
EXPORT DAC_2_Handler [WEAK]
|
||||
EXPORT DAC_3_Handler [WEAK]
|
||||
EXPORT DAC_4_Handler [WEAK]
|
||||
EXPORT I2S_Handler [WEAK]
|
||||
EXPORT PCC_Handler [WEAK]
|
||||
EXPORT AES_Handler [WEAK]
|
||||
EXPORT TRNG_Handler [WEAK]
|
||||
EXPORT ICM_Handler [WEAK]
|
||||
EXPORT PUKCC_Handler [WEAK]
|
||||
EXPORT QSPI_Handler [WEAK]
|
||||
EXPORT SDHC0_Handler [WEAK]
|
||||
EXPORT SDHC1_Handler [WEAK]
|
||||
|
||||
PM_Handler
|
||||
MCLK_Handler
|
||||
OSCCTRL_0_Handler
|
||||
OSCCTRL_1_Handler
|
||||
OSCCTRL_2_Handler
|
||||
OSCCTRL_3_Handler
|
||||
OSCCTRL_4_Handler
|
||||
OSC32KCTRL_Handler
|
||||
SUPC_0_Handler
|
||||
SUPC_1_Handler
|
||||
WDT_Handler
|
||||
RTC_Handler
|
||||
EIC_0_Handler
|
||||
EIC_1_Handler
|
||||
EIC_2_Handler
|
||||
EIC_3_Handler
|
||||
EIC_4_Handler
|
||||
EIC_5_Handler
|
||||
EIC_6_Handler
|
||||
EIC_7_Handler
|
||||
EIC_8_Handler
|
||||
EIC_9_Handler
|
||||
EIC_10_Handler
|
||||
EIC_11_Handler
|
||||
EIC_12_Handler
|
||||
EIC_13_Handler
|
||||
EIC_14_Handler
|
||||
EIC_15_Handler
|
||||
FREQM_Handler
|
||||
NVMCTRL_0_Handler
|
||||
NVMCTRL_1_Handler
|
||||
DMAC_0_Handler
|
||||
DMAC_1_Handler
|
||||
DMAC_2_Handler
|
||||
DMAC_3_Handler
|
||||
DMAC_4_Handler
|
||||
EVSYS_0_Handler
|
||||
EVSYS_1_Handler
|
||||
EVSYS_2_Handler
|
||||
EVSYS_3_Handler
|
||||
EVSYS_4_Handler
|
||||
PAC_Handler
|
||||
TAL_0_Handler
|
||||
TAL_1_Handler
|
||||
RAMECC_Handler
|
||||
SERCOM0_0_Handler
|
||||
SERCOM0_1_Handler
|
||||
SERCOM0_2_Handler
|
||||
SERCOM0_3_Handler
|
||||
SERCOM1_0_Handler
|
||||
SERCOM1_1_Handler
|
||||
SERCOM1_2_Handler
|
||||
SERCOM1_3_Handler
|
||||
SERCOM2_0_Handler
|
||||
SERCOM2_1_Handler
|
||||
SERCOM2_2_Handler
|
||||
SERCOM2_3_Handler
|
||||
SERCOM3_0_Handler
|
||||
SERCOM3_1_Handler
|
||||
SERCOM3_2_Handler
|
||||
SERCOM3_3_Handler
|
||||
SERCOM4_0_Handler
|
||||
SERCOM4_1_Handler
|
||||
SERCOM4_2_Handler
|
||||
SERCOM4_3_Handler
|
||||
SERCOM5_0_Handler
|
||||
SERCOM5_1_Handler
|
||||
SERCOM5_2_Handler
|
||||
SERCOM5_3_Handler
|
||||
SERCOM6_0_Handler
|
||||
SERCOM6_1_Handler
|
||||
SERCOM6_2_Handler
|
||||
SERCOM6_3_Handler
|
||||
SERCOM7_0_Handler
|
||||
SERCOM7_1_Handler
|
||||
SERCOM7_2_Handler
|
||||
SERCOM7_3_Handler
|
||||
CAN0_Handler
|
||||
CAN1_Handler
|
||||
USB_0_Handler
|
||||
USB_1_Handler
|
||||
USB_2_Handler
|
||||
USB_3_Handler
|
||||
GMAC_Handler
|
||||
TCC0_0_Handler
|
||||
TCC0_1_Handler
|
||||
TCC0_2_Handler
|
||||
TCC0_3_Handler
|
||||
TCC0_4_Handler
|
||||
TCC0_5_Handler
|
||||
TCC0_6_Handler
|
||||
TCC1_0_Handler
|
||||
TCC1_1_Handler
|
||||
TCC1_2_Handler
|
||||
TCC1_3_Handler
|
||||
TCC1_4_Handler
|
||||
TCC2_0_Handler
|
||||
TCC2_1_Handler
|
||||
TCC2_2_Handler
|
||||
TCC2_3_Handler
|
||||
TCC3_0_Handler
|
||||
TCC3_1_Handler
|
||||
TCC3_2_Handler
|
||||
TCC4_0_Handler
|
||||
TCC4_1_Handler
|
||||
TCC4_2_Handler
|
||||
TC0_Handler
|
||||
TC1_Handler
|
||||
TC2_Handler
|
||||
TC3_Handler
|
||||
TC4_Handler
|
||||
TC5_Handler
|
||||
TC6_Handler
|
||||
TC7_Handler
|
||||
PDEC_0_Handler
|
||||
PDEC_1_Handler
|
||||
PDEC_2_Handler
|
||||
ADC0_0_Handler
|
||||
ADC0_1_Handler
|
||||
ADC1_0_Handler
|
||||
ADC1_1_Handler
|
||||
AC_Handler
|
||||
DAC_0_Handler
|
||||
DAC_1_Handler
|
||||
DAC_2_Handler
|
||||
DAC_3_Handler
|
||||
DAC_4_Handler
|
||||
I2S_Handler
|
||||
PCC_Handler
|
||||
AES_Handler
|
||||
TRNG_Handler
|
||||
ICM_Handler
|
||||
PUKCC_Handler
|
||||
QSPI_Handler
|
||||
SDHC0_Handler
|
||||
SDHC1_Handler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
70
lib/same51/armcc/arm_addon/armcc/system_same51.c
Normal file
70
lib/same51/armcc/arm_addon/armcc/system_same51.c
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup.
|
||||
*
|
||||
* Copyright (c) 2016 Atmel Corporation,
|
||||
* a wholly owned subsidiary of Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same51.h"
|
||||
|
||||
/**
|
||||
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
|
||||
* the source for the main clock at chip startup.
|
||||
*/
|
||||
#define __SYSTEM_CLOCK (48000000)
|
||||
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if __FPU_USED
|
||||
/* Enable FPU */
|
||||
SCB->CPACR |= (0xFu << 20);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
// Keep the default device state after reset
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
// Not implemented
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
10623
lib/same51/atdf/ATSAME51G18A.atdf
Normal file
10623
lib/same51/atdf/ATSAME51G18A.atdf
Normal file
File diff suppressed because it is too large
Load diff
10623
lib/same51/atdf/ATSAME51G19A.atdf
Normal file
10623
lib/same51/atdf/ATSAME51G19A.atdf
Normal file
File diff suppressed because it is too large
Load diff
10908
lib/same51/atdf/ATSAME51J18A.atdf
Normal file
10908
lib/same51/atdf/ATSAME51J18A.atdf
Normal file
File diff suppressed because it is too large
Load diff
10908
lib/same51/atdf/ATSAME51J19A.atdf
Normal file
10908
lib/same51/atdf/ATSAME51J19A.atdf
Normal file
File diff suppressed because it is too large
Load diff
10908
lib/same51/atdf/ATSAME51J20A.atdf
Normal file
10908
lib/same51/atdf/ATSAME51J20A.atdf
Normal file
File diff suppressed because it is too large
Load diff
11294
lib/same51/atdf/ATSAME51N19A.atdf
Normal file
11294
lib/same51/atdf/ATSAME51N19A.atdf
Normal file
File diff suppressed because it is too large
Load diff
11294
lib/same51/atdf/ATSAME51N20A.atdf
Normal file
11294
lib/same51/atdf/ATSAME51N20A.atdf
Normal file
File diff suppressed because it is too large
Load diff
163
lib/same51/gcc/gcc/same51g18a_flash.ld
Normal file
163
lib/same51/gcc/gcc/same51g18a_flash.ld
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51G18A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
162
lib/same51/gcc/gcc/same51g18a_sram.ld
Normal file
162
lib/same51/gcc/gcc/same51g18a_sram.ld
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51G18A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
163
lib/same51/gcc/gcc/same51g19a_flash.ld
Normal file
163
lib/same51/gcc/gcc/same51g19a_flash.ld
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51G19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
162
lib/same51/gcc/gcc/same51g19a_sram.ld
Normal file
162
lib/same51/gcc/gcc/same51g19a_sram.ld
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51G19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
163
lib/same51/gcc/gcc/same51j18a_flash.ld
Normal file
163
lib/same51/gcc/gcc/same51j18a_flash.ld
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51J18A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
162
lib/same51/gcc/gcc/same51j18a_sram.ld
Normal file
162
lib/same51/gcc/gcc/same51j18a_sram.ld
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51J18A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
163
lib/same51/gcc/gcc/same51j19a_flash.ld
Normal file
163
lib/same51/gcc/gcc/same51j19a_flash.ld
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51J19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
162
lib/same51/gcc/gcc/same51j19a_sram.ld
Normal file
162
lib/same51/gcc/gcc/same51j19a_sram.ld
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51J19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
163
lib/same51/gcc/gcc/same51j20a_flash.ld
Normal file
163
lib/same51/gcc/gcc/same51j20a_flash.ld
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51J20A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
162
lib/same51/gcc/gcc/same51j20a_sram.ld
Normal file
162
lib/same51/gcc/gcc/same51j20a_sram.ld
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51J20A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
163
lib/same51/gcc/gcc/same51n19a_flash.ld
Normal file
163
lib/same51/gcc/gcc/same51n19a_flash.ld
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51N19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
162
lib/same51/gcc/gcc/same51n19a_sram.ld
Normal file
162
lib/same51/gcc/gcc/same51n19a_sram.ld
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51N19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
163
lib/same51/gcc/gcc/same51n20a_flash.ld
Normal file
163
lib/same51/gcc/gcc/same51n20a_flash.ld
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51N20A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
162
lib/same51/gcc/gcc/same51n20a_sram.ld
Normal file
162
lib/same51/gcc/gcc/same51n20a_sram.ld
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51N20A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
|
||||
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
|
||||
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
.bkupram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sbkupram = .;
|
||||
*(.bkupram .bkupram.*);
|
||||
. = ALIGN(8);
|
||||
_ebkupram = .;
|
||||
} > bkupram
|
||||
|
||||
.qspi (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sqspi = .;
|
||||
*(.qspi .qspi.*);
|
||||
. = ALIGN(8);
|
||||
_eqspi = .;
|
||||
} > qspi
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
}
|
||||
546
lib/same51/gcc/gcc/startup_same51.c
Normal file
546
lib/same51/gcc/gcc/startup_same51.c
Normal file
|
|
@ -0,0 +1,546 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief gcc starttup file for SAME51
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same51.h"
|
||||
|
||||
/* Initialize segments */
|
||||
extern uint32_t _sfixed;
|
||||
extern uint32_t _efixed;
|
||||
extern uint32_t _etext;
|
||||
extern uint32_t _srelocate;
|
||||
extern uint32_t _erelocate;
|
||||
extern uint32_t _szero;
|
||||
extern uint32_t _ezero;
|
||||
extern uint32_t _sstack;
|
||||
extern uint32_t _estack;
|
||||
|
||||
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
|
||||
int main(void);
|
||||
/** \endcond */
|
||||
|
||||
void __libc_init_array(void);
|
||||
|
||||
/* Default empty handler */
|
||||
void Dummy_Handler(void);
|
||||
|
||||
/* Cortex-M4 core handlers */
|
||||
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void MemManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
|
||||
/* Peripherals handlers */
|
||||
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void OSCCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
|
||||
void OSCCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
|
||||
void OSCCTRL_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
|
||||
void OSCCTRL_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
|
||||
void OSCCTRL_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
|
||||
void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SUPC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
|
||||
void SUPC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
|
||||
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void EIC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
|
||||
void EIC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
|
||||
void EIC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
|
||||
void EIC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
|
||||
void EIC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
|
||||
void EIC_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
|
||||
void EIC_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
|
||||
void EIC_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
|
||||
void EIC_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
|
||||
void EIC_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
|
||||
void EIC_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
|
||||
void EIC_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
|
||||
void EIC_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
|
||||
void EIC_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
|
||||
void EIC_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
|
||||
void EIC_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
|
||||
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
|
||||
void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
|
||||
void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
|
||||
void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
|
||||
void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
|
||||
void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
|
||||
void DMAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
|
||||
void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
|
||||
void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
|
||||
void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
|
||||
void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
|
||||
void EVSYS_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
|
||||
void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
|
||||
void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
|
||||
void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
|
||||
void SERCOM0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
|
||||
void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
|
||||
void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
|
||||
void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
|
||||
void SERCOM1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
|
||||
void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
|
||||
void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
|
||||
void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
|
||||
void SERCOM2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
|
||||
void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
|
||||
void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
|
||||
void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
|
||||
void SERCOM3_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
|
||||
#ifdef ID_SERCOM4
|
||||
void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
|
||||
void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
|
||||
void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
|
||||
void SERCOM4_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
|
||||
void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
|
||||
void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
|
||||
void SERCOM5_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM6
|
||||
void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
|
||||
void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
|
||||
void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
|
||||
void SERCOM6_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM7
|
||||
void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
|
||||
void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
|
||||
void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
|
||||
void SERCOM7_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
|
||||
#endif
|
||||
#ifdef ID_CAN0
|
||||
void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_CAN1
|
||||
void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_USB
|
||||
void USB_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
|
||||
void USB_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
|
||||
void USB_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
|
||||
void USB_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
|
||||
#endif
|
||||
#ifdef ID_GMAC
|
||||
void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void TCC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
|
||||
void TCC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
|
||||
void TCC0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
|
||||
void TCC0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
|
||||
void TCC0_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
|
||||
void TCC0_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
|
||||
void TCC0_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
|
||||
void TCC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
|
||||
void TCC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
|
||||
void TCC1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
|
||||
void TCC1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
|
||||
void TCC1_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
|
||||
void TCC2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
|
||||
void TCC2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
|
||||
void TCC2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
|
||||
void TCC2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
|
||||
#ifdef ID_TCC3
|
||||
void TCC3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
|
||||
void TCC3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
|
||||
void TCC3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
|
||||
#endif
|
||||
#ifdef ID_TCC4
|
||||
void TCC4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
|
||||
void TCC4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
|
||||
void TCC4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
|
||||
#endif
|
||||
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_TC4
|
||||
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC5
|
||||
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC6
|
||||
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_TC7
|
||||
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void PDEC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
|
||||
void PDEC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
|
||||
void PDEC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
|
||||
void ADC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
|
||||
void ADC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
|
||||
void ADC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
|
||||
void ADC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
|
||||
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
|
||||
void DAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
|
||||
void DAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
|
||||
void DAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
|
||||
void DAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
|
||||
#ifdef ID_I2S
|
||||
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_ICM
|
||||
void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_PUKCC
|
||||
void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#ifdef ID_SDHC0
|
||||
void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
#ifdef ID_SDHC1
|
||||
void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif
|
||||
|
||||
/* Exception Table */
|
||||
__attribute__ ((section(".vectors")))
|
||||
const DeviceVectors exception_table = {
|
||||
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
.pvStack = (void*) (&_estack),
|
||||
|
||||
.pfnReset_Handler = (void*) Reset_Handler,
|
||||
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
|
||||
.pfnHardFault_Handler = (void*) HardFault_Handler,
|
||||
.pfnMemManagement_Handler = (void*) MemManagement_Handler,
|
||||
.pfnBusFault_Handler = (void*) BusFault_Handler,
|
||||
.pfnUsageFault_Handler = (void*) UsageFault_Handler,
|
||||
.pvReservedM9 = (void*) (0UL), /* Reserved */
|
||||
.pvReservedM8 = (void*) (0UL), /* Reserved */
|
||||
.pvReservedM7 = (void*) (0UL), /* Reserved */
|
||||
.pvReservedM6 = (void*) (0UL), /* Reserved */
|
||||
.pfnSVCall_Handler = (void*) SVCall_Handler,
|
||||
.pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
|
||||
.pvReservedM3 = (void*) (0UL), /* Reserved */
|
||||
.pfnPendSV_Handler = (void*) PendSV_Handler,
|
||||
.pfnSysTick_Handler = (void*) SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
.pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
|
||||
.pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */
|
||||
.pfnOSCCTRL_0_Handler = (void*) OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
|
||||
.pfnOSCCTRL_1_Handler = (void*) OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
|
||||
.pfnOSCCTRL_2_Handler = (void*) OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
|
||||
.pfnOSCCTRL_3_Handler = (void*) OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
|
||||
.pfnOSCCTRL_4_Handler = (void*) OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
|
||||
.pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
|
||||
.pfnSUPC_0_Handler = (void*) SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
|
||||
.pfnSUPC_1_Handler = (void*) SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */
|
||||
.pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */
|
||||
.pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */
|
||||
.pfnEIC_0_Handler = (void*) EIC_0_Handler, /* 12 EIC_EXTINT_0 */
|
||||
.pfnEIC_1_Handler = (void*) EIC_1_Handler, /* 13 EIC_EXTINT_1 */
|
||||
.pfnEIC_2_Handler = (void*) EIC_2_Handler, /* 14 EIC_EXTINT_2 */
|
||||
.pfnEIC_3_Handler = (void*) EIC_3_Handler, /* 15 EIC_EXTINT_3 */
|
||||
.pfnEIC_4_Handler = (void*) EIC_4_Handler, /* 16 EIC_EXTINT_4 */
|
||||
.pfnEIC_5_Handler = (void*) EIC_5_Handler, /* 17 EIC_EXTINT_5 */
|
||||
.pfnEIC_6_Handler = (void*) EIC_6_Handler, /* 18 EIC_EXTINT_6 */
|
||||
.pfnEIC_7_Handler = (void*) EIC_7_Handler, /* 19 EIC_EXTINT_7 */
|
||||
.pfnEIC_8_Handler = (void*) EIC_8_Handler, /* 20 EIC_EXTINT_8 */
|
||||
.pfnEIC_9_Handler = (void*) EIC_9_Handler, /* 21 EIC_EXTINT_9 */
|
||||
.pfnEIC_10_Handler = (void*) EIC_10_Handler, /* 22 EIC_EXTINT_10 */
|
||||
.pfnEIC_11_Handler = (void*) EIC_11_Handler, /* 23 EIC_EXTINT_11 */
|
||||
.pfnEIC_12_Handler = (void*) EIC_12_Handler, /* 24 EIC_EXTINT_12 */
|
||||
.pfnEIC_13_Handler = (void*) EIC_13_Handler, /* 25 EIC_EXTINT_13 */
|
||||
.pfnEIC_14_Handler = (void*) EIC_14_Handler, /* 26 EIC_EXTINT_14 */
|
||||
.pfnEIC_15_Handler = (void*) EIC_15_Handler, /* 27 EIC_EXTINT_15 */
|
||||
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */
|
||||
.pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
|
||||
.pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
|
||||
.pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
|
||||
.pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
|
||||
.pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
|
||||
.pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
|
||||
.pfnDMAC_4_Handler = (void*) DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
|
||||
.pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
|
||||
.pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
|
||||
.pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
|
||||
.pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
|
||||
.pfnEVSYS_4_Handler = (void*) EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
|
||||
.pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */
|
||||
.pvReserved42 = (void*) (0UL), /* 42 Reserved */
|
||||
.pvReserved43 = (void*) (0UL), /* 43 Reserved */
|
||||
.pvReserved44 = (void*) (0UL), /* 44 Reserved */
|
||||
.pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */
|
||||
.pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 SERCOM0_0 */
|
||||
.pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 SERCOM0_1 */
|
||||
.pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 SERCOM0_2 */
|
||||
.pfnSERCOM0_3_Handler = (void*) SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
|
||||
.pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 SERCOM1_0 */
|
||||
.pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 SERCOM1_1 */
|
||||
.pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 SERCOM1_2 */
|
||||
.pfnSERCOM1_3_Handler = (void*) SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
|
||||
.pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 SERCOM2_0 */
|
||||
.pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 SERCOM2_1 */
|
||||
.pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 SERCOM2_2 */
|
||||
.pfnSERCOM2_3_Handler = (void*) SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
|
||||
.pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 SERCOM3_0 */
|
||||
.pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 SERCOM3_1 */
|
||||
.pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 SERCOM3_2 */
|
||||
.pfnSERCOM3_3_Handler = (void*) SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
|
||||
#ifdef ID_SERCOM4
|
||||
.pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 SERCOM4_0 */
|
||||
.pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 SERCOM4_1 */
|
||||
.pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 SERCOM4_2 */
|
||||
.pfnSERCOM4_3_Handler = (void*) SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
|
||||
#else
|
||||
.pvReserved62 = (void*) (0UL), /* 62 Reserved */
|
||||
.pvReserved63 = (void*) (0UL), /* 63 Reserved */
|
||||
.pvReserved64 = (void*) (0UL), /* 64 Reserved */
|
||||
.pvReserved65 = (void*) (0UL), /* 65 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
.pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 SERCOM5_0 */
|
||||
.pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 SERCOM5_1 */
|
||||
.pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 SERCOM5_2 */
|
||||
.pfnSERCOM5_3_Handler = (void*) SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
|
||||
#else
|
||||
.pvReserved66 = (void*) (0UL), /* 66 Reserved */
|
||||
.pvReserved67 = (void*) (0UL), /* 67 Reserved */
|
||||
.pvReserved68 = (void*) (0UL), /* 68 Reserved */
|
||||
.pvReserved69 = (void*) (0UL), /* 69 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM6
|
||||
.pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 SERCOM6_0 */
|
||||
.pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 SERCOM6_1 */
|
||||
.pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 SERCOM6_2 */
|
||||
.pfnSERCOM6_3_Handler = (void*) SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
|
||||
#else
|
||||
.pvReserved70 = (void*) (0UL), /* 70 Reserved */
|
||||
.pvReserved71 = (void*) (0UL), /* 71 Reserved */
|
||||
.pvReserved72 = (void*) (0UL), /* 72 Reserved */
|
||||
.pvReserved73 = (void*) (0UL), /* 73 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM7
|
||||
.pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 SERCOM7_0 */
|
||||
.pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 SERCOM7_1 */
|
||||
.pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 SERCOM7_2 */
|
||||
.pfnSERCOM7_3_Handler = (void*) SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
|
||||
#else
|
||||
.pvReserved74 = (void*) (0UL), /* 74 Reserved */
|
||||
.pvReserved75 = (void*) (0UL), /* 75 Reserved */
|
||||
.pvReserved76 = (void*) (0UL), /* 76 Reserved */
|
||||
.pvReserved77 = (void*) (0UL), /* 77 Reserved */
|
||||
#endif
|
||||
#ifdef ID_CAN0
|
||||
.pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network 0 */
|
||||
#else
|
||||
.pvReserved78 = (void*) (0UL), /* 78 Reserved */
|
||||
#endif
|
||||
#ifdef ID_CAN1
|
||||
.pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network 1 */
|
||||
#else
|
||||
.pvReserved79 = (void*) (0UL), /* 79 Reserved */
|
||||
#endif
|
||||
#ifdef ID_USB
|
||||
.pfnUSB_0_Handler = (void*) USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
|
||||
.pfnUSB_1_Handler = (void*) USB_1_Handler, /* 81 USB_SOF_HSOF */
|
||||
.pfnUSB_2_Handler = (void*) USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
|
||||
.pfnUSB_3_Handler = (void*) USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
|
||||
#else
|
||||
.pvReserved80 = (void*) (0UL), /* 80 Reserved */
|
||||
.pvReserved81 = (void*) (0UL), /* 81 Reserved */
|
||||
.pvReserved82 = (void*) (0UL), /* 82 Reserved */
|
||||
.pvReserved83 = (void*) (0UL), /* 83 Reserved */
|
||||
#endif
|
||||
#ifdef ID_GMAC
|
||||
.pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */
|
||||
#else
|
||||
.pvReserved84 = (void*) (0UL), /* 84 Reserved */
|
||||
#endif
|
||||
.pfnTCC0_0_Handler = (void*) TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
|
||||
.pfnTCC0_1_Handler = (void*) TCC0_1_Handler, /* 86 TCC0_MC_0 */
|
||||
.pfnTCC0_2_Handler = (void*) TCC0_2_Handler, /* 87 TCC0_MC_1 */
|
||||
.pfnTCC0_3_Handler = (void*) TCC0_3_Handler, /* 88 TCC0_MC_2 */
|
||||
.pfnTCC0_4_Handler = (void*) TCC0_4_Handler, /* 89 TCC0_MC_3 */
|
||||
.pfnTCC0_5_Handler = (void*) TCC0_5_Handler, /* 90 TCC0_MC_4 */
|
||||
.pfnTCC0_6_Handler = (void*) TCC0_6_Handler, /* 91 TCC0_MC_5 */
|
||||
.pfnTCC1_0_Handler = (void*) TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
|
||||
.pfnTCC1_1_Handler = (void*) TCC1_1_Handler, /* 93 TCC1_MC_0 */
|
||||
.pfnTCC1_2_Handler = (void*) TCC1_2_Handler, /* 94 TCC1_MC_1 */
|
||||
.pfnTCC1_3_Handler = (void*) TCC1_3_Handler, /* 95 TCC1_MC_2 */
|
||||
.pfnTCC1_4_Handler = (void*) TCC1_4_Handler, /* 96 TCC1_MC_3 */
|
||||
.pfnTCC2_0_Handler = (void*) TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
|
||||
.pfnTCC2_1_Handler = (void*) TCC2_1_Handler, /* 98 TCC2_MC_0 */
|
||||
.pfnTCC2_2_Handler = (void*) TCC2_2_Handler, /* 99 TCC2_MC_1 */
|
||||
.pfnTCC2_3_Handler = (void*) TCC2_3_Handler, /* 100 TCC2_MC_2 */
|
||||
#ifdef ID_TCC3
|
||||
.pfnTCC3_0_Handler = (void*) TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
|
||||
.pfnTCC3_1_Handler = (void*) TCC3_1_Handler, /* 102 TCC3_MC_0 */
|
||||
.pfnTCC3_2_Handler = (void*) TCC3_2_Handler, /* 103 TCC3_MC_1 */
|
||||
#else
|
||||
.pvReserved101 = (void*) (0UL), /* 101 Reserved */
|
||||
.pvReserved102 = (void*) (0UL), /* 102 Reserved */
|
||||
.pvReserved103 = (void*) (0UL), /* 103 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TCC4
|
||||
.pfnTCC4_0_Handler = (void*) TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
|
||||
.pfnTCC4_1_Handler = (void*) TCC4_1_Handler, /* 105 TCC4_MC_0 */
|
||||
.pfnTCC4_2_Handler = (void*) TCC4_2_Handler, /* 106 TCC4_MC_1 */
|
||||
#else
|
||||
.pvReserved104 = (void*) (0UL), /* 104 Reserved */
|
||||
.pvReserved105 = (void*) (0UL), /* 105 Reserved */
|
||||
.pvReserved106 = (void*) (0UL), /* 106 Reserved */
|
||||
#endif
|
||||
.pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter 0 */
|
||||
.pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter 1 */
|
||||
.pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter 2 */
|
||||
.pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter 3 */
|
||||
#ifdef ID_TC4
|
||||
.pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter 4 */
|
||||
#else
|
||||
.pvReserved111 = (void*) (0UL), /* 111 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC5
|
||||
.pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter 5 */
|
||||
#else
|
||||
.pvReserved112 = (void*) (0UL), /* 112 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC6
|
||||
.pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter 6 */
|
||||
#else
|
||||
.pvReserved113 = (void*) (0UL), /* 113 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC7
|
||||
.pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter 7 */
|
||||
#else
|
||||
.pvReserved114 = (void*) (0UL), /* 114 Reserved */
|
||||
#endif
|
||||
.pfnPDEC_0_Handler = (void*) PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
|
||||
.pfnPDEC_1_Handler = (void*) PDEC_1_Handler, /* 116 PDEC_MC_0 */
|
||||
.pfnPDEC_2_Handler = (void*) PDEC_2_Handler, /* 117 PDEC_MC_1 */
|
||||
.pfnADC0_0_Handler = (void*) ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */
|
||||
.pfnADC0_1_Handler = (void*) ADC0_1_Handler, /* 119 ADC0_RESRDY */
|
||||
.pfnADC1_0_Handler = (void*) ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */
|
||||
.pfnADC1_1_Handler = (void*) ADC1_1_Handler, /* 121 ADC1_RESRDY */
|
||||
.pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */
|
||||
.pfnDAC_0_Handler = (void*) DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
|
||||
.pfnDAC_1_Handler = (void*) DAC_1_Handler, /* 124 DAC_EMPTY_0 */
|
||||
.pfnDAC_2_Handler = (void*) DAC_2_Handler, /* 125 DAC_EMPTY_1 */
|
||||
.pfnDAC_3_Handler = (void*) DAC_3_Handler, /* 126 DAC_RESRDY_0 */
|
||||
.pfnDAC_4_Handler = (void*) DAC_4_Handler, /* 127 DAC_RESRDY_1 */
|
||||
#ifdef ID_I2S
|
||||
.pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */
|
||||
#else
|
||||
.pvReserved128 = (void*) (0UL), /* 128 Reserved */
|
||||
#endif
|
||||
.pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */
|
||||
.pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */
|
||||
.pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */
|
||||
#ifdef ID_ICM
|
||||
.pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */
|
||||
#else
|
||||
.pvReserved132 = (void*) (0UL), /* 132 Reserved */
|
||||
#endif
|
||||
#ifdef ID_PUKCC
|
||||
.pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
|
||||
#else
|
||||
.pvReserved133 = (void*) (0UL), /* 133 Reserved */
|
||||
#endif
|
||||
.pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */
|
||||
#ifdef ID_SDHC0
|
||||
.pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */
|
||||
#else
|
||||
.pvReserved135 = (void*) (0UL), /* 135 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SDHC1
|
||||
.pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller 1 */
|
||||
#else
|
||||
.pvReserved136 = (void*) (0UL) /* 136 Reserved */
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* \brief This is the code that gets called on processor reset.
|
||||
* To initialize the device, and call the main() routine.
|
||||
*/
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
uint32_t *pSrc, *pDest;
|
||||
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext;
|
||||
pDest = &_srelocate;
|
||||
|
||||
if (pSrc != pDest) {
|
||||
for (; pDest < &_erelocate;) {
|
||||
*pDest++ = *pSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the zero segment */
|
||||
for (pDest = &_szero; pDest < &_ezero;) {
|
||||
*pDest++ = 0;
|
||||
}
|
||||
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *) & _sfixed;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
#if __FPU_USED
|
||||
/* Enable FPU */
|
||||
SCB->CPACR |= (0xFu << 20);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
/* Initialize the C library */
|
||||
__libc_init_array();
|
||||
|
||||
/* Branch to main function */
|
||||
main();
|
||||
|
||||
/* Infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Default interrupt handler for unused IRQs.
|
||||
*/
|
||||
void Dummy_Handler(void)
|
||||
{
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
64
lib/same51/gcc/system_same51.c
Normal file
64
lib/same51/gcc/system_same51.c
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup.
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same51.h"
|
||||
|
||||
/**
|
||||
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
|
||||
* the source for the main clock at chip startup.
|
||||
*/
|
||||
#define __SYSTEM_CLOCK (48000000)
|
||||
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
// Keep the default device state after reset
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
// Not implemented
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
35
lib/same51/iar/config/debugger/Atmel/ATSAME51G18A.ddf
Normal file
35
lib/same51/iar/config/debugger/Atmel/ATSAME51G18A.ddf
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
|
||||
;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Used to define address zones within the ARM address space (Memory).
|
||||
;;
|
||||
;; Name may be almost anything
|
||||
;; AdrSpace must be Memory
|
||||
;; StartAdr start of memory block
|
||||
;; EndAdr end of memory block
|
||||
;; AccType type of access, read-only (R), read-write (RW) or SFR (W)
|
||||
|
||||
[Memory]
|
||||
;; Name AdrSpace StartAdr EndAdr AccType
|
||||
Memory0 = NVMCTRL0 Memory 0x00000000 0x00FFFFFF R
|
||||
Memory1 = NVMCTRL1 Memory 0x00000000 0x00FFFFFF R
|
||||
Memory2 = PUKCC Memory 0x02000000 0x02011FFF RW
|
||||
Memory3 = QSPI Memory 0x04000000 0x04FFFFFF RW
|
||||
Memory4 = HSRAM Memory 0x20000000 0x2003FFFF RW
|
||||
Memory5 = BKUPRAM Memory 0x47000000 0x47001FFF RW
|
||||
Memory6 = HPB0 Memory 0x40000000 0x400043FF W
|
||||
Memory7 = HPB1 Memory 0x41000000 0x41021FFF W
|
||||
Memory8 = HPB2 Memory 0x42000000 0x42003BFF W
|
||||
Memory9 = HPB3 Memory 0x43000000 0x43002FFF W
|
||||
Memory10 = NVMCTRL2 Memory 0x44000000 0x4401FFFF W
|
||||
Memory11 = SDHC0 Memory 0x45000000 0x45000BFF W
|
||||
Memory12 = SDHC1 Memory 0x46000000 0x46000BFF W
|
||||
Memory13 = CMCC_DATARAM Memory 0x03000000 0x03000FFF RW
|
||||
Memory14 = CMCC_TAGRAM Memory 0x03001000 0x030013FF RW
|
||||
Memory15 = CMCC_VALIDRAM Memory 0x03002000 0x0300203F RW
|
||||
|
||||
TrustedRanges = true
|
||||
UseSfrFilter = true
|
||||
|
||||
[SfrInclude]
|
||||
File = ATSAME51G18A.svd
|
||||
35
lib/same51/iar/config/debugger/Atmel/ATSAME51G19A.ddf
Normal file
35
lib/same51/iar/config/debugger/Atmel/ATSAME51G19A.ddf
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
|
||||
;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Used to define address zones within the ARM address space (Memory).
|
||||
;;
|
||||
;; Name may be almost anything
|
||||
;; AdrSpace must be Memory
|
||||
;; StartAdr start of memory block
|
||||
;; EndAdr end of memory block
|
||||
;; AccType type of access, read-only (R), read-write (RW) or SFR (W)
|
||||
|
||||
[Memory]
|
||||
;; Name AdrSpace StartAdr EndAdr AccType
|
||||
Memory0 = NVMCTRL0 Memory 0x00000000 0x00FFFFFF R
|
||||
Memory1 = NVMCTRL1 Memory 0x00000000 0x00FFFFFF R
|
||||
Memory2 = PUKCC Memory 0x02000000 0x02011FFF RW
|
||||
Memory3 = QSPI Memory 0x04000000 0x04FFFFFF RW
|
||||
Memory4 = HSRAM Memory 0x20000000 0x2003FFFF RW
|
||||
Memory5 = BKUPRAM Memory 0x47000000 0x47001FFF RW
|
||||
Memory6 = HPB0 Memory 0x40000000 0x400043FF W
|
||||
Memory7 = HPB1 Memory 0x41000000 0x41021FFF W
|
||||
Memory8 = HPB2 Memory 0x42000000 0x42003BFF W
|
||||
Memory9 = HPB3 Memory 0x43000000 0x43002FFF W
|
||||
Memory10 = NVMCTRL2 Memory 0x44000000 0x4401FFFF W
|
||||
Memory11 = SDHC0 Memory 0x45000000 0x45000BFF W
|
||||
Memory12 = SDHC1 Memory 0x46000000 0x46000BFF W
|
||||
Memory13 = CMCC_DATARAM Memory 0x03000000 0x03000FFF RW
|
||||
Memory14 = CMCC_TAGRAM Memory 0x03001000 0x030013FF RW
|
||||
Memory15 = CMCC_VALIDRAM Memory 0x03002000 0x0300203F RW
|
||||
|
||||
TrustedRanges = true
|
||||
UseSfrFilter = true
|
||||
|
||||
[SfrInclude]
|
||||
File = ATSAME51G19A.svd
|
||||
35
lib/same51/iar/config/debugger/Atmel/ATSAME51J18A.ddf
Normal file
35
lib/same51/iar/config/debugger/Atmel/ATSAME51J18A.ddf
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
|
||||
;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Used to define address zones within the ARM address space (Memory).
|
||||
;;
|
||||
;; Name may be almost anything
|
||||
;; AdrSpace must be Memory
|
||||
;; StartAdr start of memory block
|
||||
;; EndAdr end of memory block
|
||||
;; AccType type of access, read-only (R), read-write (RW) or SFR (W)
|
||||
|
||||
[Memory]
|
||||
;; Name AdrSpace StartAdr EndAdr AccType
|
||||
Memory0 = NVMCTRL0 Memory 0x00000000 0x00FFFFFF R
|
||||
Memory1 = NVMCTRL1 Memory 0x00000000 0x00FFFFFF R
|
||||
Memory2 = PUKCC Memory 0x02000000 0x02011FFF RW
|
||||
Memory3 = QSPI Memory 0x04000000 0x04FFFFFF RW
|
||||
Memory4 = HSRAM Memory 0x20000000 0x2003FFFF RW
|
||||
Memory5 = BKUPRAM Memory 0x47000000 0x47001FFF RW
|
||||
Memory6 = HPB0 Memory 0x40000000 0x400043FF W
|
||||
Memory7 = HPB1 Memory 0x41000000 0x41021FFF W
|
||||
Memory8 = HPB2 Memory 0x42000000 0x42003BFF W
|
||||
Memory9 = HPB3 Memory 0x43000000 0x43002FFF W
|
||||
Memory10 = NVMCTRL2 Memory 0x44000000 0x4401FFFF W
|
||||
Memory11 = SDHC0 Memory 0x45000000 0x45000BFF W
|
||||
Memory12 = SDHC1 Memory 0x46000000 0x46000BFF W
|
||||
Memory13 = CMCC_DATARAM Memory 0x03000000 0x03000FFF RW
|
||||
Memory14 = CMCC_TAGRAM Memory 0x03001000 0x030013FF RW
|
||||
Memory15 = CMCC_VALIDRAM Memory 0x03002000 0x0300203F RW
|
||||
|
||||
TrustedRanges = true
|
||||
UseSfrFilter = true
|
||||
|
||||
[SfrInclude]
|
||||
File = ATSAME51J18A.svd
|
||||
35
lib/same51/iar/config/debugger/Atmel/ATSAME51J19A.ddf
Normal file
35
lib/same51/iar/config/debugger/Atmel/ATSAME51J19A.ddf
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
|
||||
;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Used to define address zones within the ARM address space (Memory).
|
||||
;;
|
||||
;; Name may be almost anything
|
||||
;; AdrSpace must be Memory
|
||||
;; StartAdr start of memory block
|
||||
;; EndAdr end of memory block
|
||||
;; AccType type of access, read-only (R), read-write (RW) or SFR (W)
|
||||
|
||||
[Memory]
|
||||
;; Name AdrSpace StartAdr EndAdr AccType
|
||||
Memory0 = NVMCTRL0 Memory 0x00000000 0x00FFFFFF R
|
||||
Memory1 = NVMCTRL1 Memory 0x00000000 0x00FFFFFF R
|
||||
Memory2 = PUKCC Memory 0x02000000 0x02011FFF RW
|
||||
Memory3 = QSPI Memory 0x04000000 0x04FFFFFF RW
|
||||
Memory4 = HSRAM Memory 0x20000000 0x2003FFFF RW
|
||||
Memory5 = BKUPRAM Memory 0x47000000 0x47001FFF RW
|
||||
Memory6 = HPB0 Memory 0x40000000 0x400043FF W
|
||||
Memory7 = HPB1 Memory 0x41000000 0x41021FFF W
|
||||
Memory8 = HPB2 Memory 0x42000000 0x42003BFF W
|
||||
Memory9 = HPB3 Memory 0x43000000 0x43002FFF W
|
||||
Memory10 = NVMCTRL2 Memory 0x44000000 0x4401FFFF W
|
||||
Memory11 = SDHC0 Memory 0x45000000 0x45000BFF W
|
||||
Memory12 = SDHC1 Memory 0x46000000 0x46000BFF W
|
||||
Memory13 = CMCC_DATARAM Memory 0x03000000 0x03000FFF RW
|
||||
Memory14 = CMCC_TAGRAM Memory 0x03001000 0x030013FF RW
|
||||
Memory15 = CMCC_VALIDRAM Memory 0x03002000 0x0300203F RW
|
||||
|
||||
TrustedRanges = true
|
||||
UseSfrFilter = true
|
||||
|
||||
[SfrInclude]
|
||||
File = ATSAME51J19A.svd
|
||||
35
lib/same51/iar/config/debugger/Atmel/ATSAME51J20A.ddf
Normal file
35
lib/same51/iar/config/debugger/Atmel/ATSAME51J20A.ddf
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
|
||||
;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Used to define address zones within the ARM address space (Memory).
|
||||
;;
|
||||
;; Name may be almost anything
|
||||
;; AdrSpace must be Memory
|
||||
;; StartAdr start of memory block
|
||||
;; EndAdr end of memory block
|
||||
;; AccType type of access, read-only (R), read-write (RW) or SFR (W)
|
||||
|
||||
[Memory]
|
||||
;; Name AdrSpace StartAdr EndAdr AccType
|
||||
Memory0 = NVMCTRL0 Memory 0x00000000 0x00FFFFFF R
|
||||
Memory1 = NVMCTRL1 Memory 0x00000000 0x00FFFFFF R
|
||||
Memory2 = PUKCC Memory 0x02000000 0x02011FFF RW
|
||||
Memory3 = QSPI Memory 0x04000000 0x04FFFFFF RW
|
||||
Memory4 = HSRAM Memory 0x20000000 0x2003FFFF RW
|
||||
Memory5 = BKUPRAM Memory 0x47000000 0x47001FFF RW
|
||||
Memory6 = HPB0 Memory 0x40000000 0x400043FF W
|
||||
Memory7 = HPB1 Memory 0x41000000 0x41021FFF W
|
||||
Memory8 = HPB2 Memory 0x42000000 0x42003BFF W
|
||||
Memory9 = HPB3 Memory 0x43000000 0x43002FFF W
|
||||
Memory10 = NVMCTRL2 Memory 0x44000000 0x4401FFFF W
|
||||
Memory11 = SDHC0 Memory 0x45000000 0x45000BFF W
|
||||
Memory12 = SDHC1 Memory 0x46000000 0x46000BFF W
|
||||
Memory13 = CMCC_DATARAM Memory 0x03000000 0x03000FFF RW
|
||||
Memory14 = CMCC_TAGRAM Memory 0x03001000 0x030013FF RW
|
||||
Memory15 = CMCC_VALIDRAM Memory 0x03002000 0x0300203F RW
|
||||
|
||||
TrustedRanges = true
|
||||
UseSfrFilter = true
|
||||
|
||||
[SfrInclude]
|
||||
File = ATSAME51J20A.svd
|
||||
35
lib/same51/iar/config/debugger/Atmel/ATSAME51N19A.ddf
Normal file
35
lib/same51/iar/config/debugger/Atmel/ATSAME51N19A.ddf
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
|
||||
;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Used to define address zones within the ARM address space (Memory).
|
||||
;;
|
||||
;; Name may be almost anything
|
||||
;; AdrSpace must be Memory
|
||||
;; StartAdr start of memory block
|
||||
;; EndAdr end of memory block
|
||||
;; AccType type of access, read-only (R), read-write (RW) or SFR (W)
|
||||
|
||||
[Memory]
|
||||
;; Name AdrSpace StartAdr EndAdr AccType
|
||||
Memory0 = NVMCTRL0 Memory 0x00000000 0x00FFFFFF R
|
||||
Memory1 = NVMCTRL1 Memory 0x00000000 0x00FFFFFF R
|
||||
Memory2 = PUKCC Memory 0x02000000 0x02011FFF RW
|
||||
Memory3 = QSPI Memory 0x04000000 0x04FFFFFF RW
|
||||
Memory4 = HSRAM Memory 0x20000000 0x2003FFFF RW
|
||||
Memory5 = BKUPRAM Memory 0x47000000 0x47001FFF RW
|
||||
Memory6 = HPB0 Memory 0x40000000 0x400043FF W
|
||||
Memory7 = HPB1 Memory 0x41000000 0x41021FFF W
|
||||
Memory8 = HPB2 Memory 0x42000000 0x42003BFF W
|
||||
Memory9 = HPB3 Memory 0x43000000 0x43002FFF W
|
||||
Memory10 = NVMCTRL2 Memory 0x44000000 0x4401FFFF W
|
||||
Memory11 = SDHC0 Memory 0x45000000 0x45000BFF W
|
||||
Memory12 = SDHC1 Memory 0x46000000 0x46000BFF W
|
||||
Memory13 = CMCC_DATARAM Memory 0x03000000 0x03000FFF RW
|
||||
Memory14 = CMCC_TAGRAM Memory 0x03001000 0x030013FF RW
|
||||
Memory15 = CMCC_VALIDRAM Memory 0x03002000 0x0300203F RW
|
||||
|
||||
TrustedRanges = true
|
||||
UseSfrFilter = true
|
||||
|
||||
[SfrInclude]
|
||||
File = ATSAME51N19A.svd
|
||||
35
lib/same51/iar/config/debugger/Atmel/ATSAME51N20A.ddf
Normal file
35
lib/same51/iar/config/debugger/Atmel/ATSAME51N20A.ddf
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
|
||||
;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Used to define address zones within the ARM address space (Memory).
|
||||
;;
|
||||
;; Name may be almost anything
|
||||
;; AdrSpace must be Memory
|
||||
;; StartAdr start of memory block
|
||||
;; EndAdr end of memory block
|
||||
;; AccType type of access, read-only (R), read-write (RW) or SFR (W)
|
||||
|
||||
[Memory]
|
||||
;; Name AdrSpace StartAdr EndAdr AccType
|
||||
Memory0 = NVMCTRL0 Memory 0x00000000 0x00FFFFFF R
|
||||
Memory1 = NVMCTRL1 Memory 0x00000000 0x00FFFFFF R
|
||||
Memory2 = PUKCC Memory 0x02000000 0x02011FFF RW
|
||||
Memory3 = QSPI Memory 0x04000000 0x04FFFFFF RW
|
||||
Memory4 = HSRAM Memory 0x20000000 0x2003FFFF RW
|
||||
Memory5 = BKUPRAM Memory 0x47000000 0x47001FFF RW
|
||||
Memory6 = HPB0 Memory 0x40000000 0x400043FF W
|
||||
Memory7 = HPB1 Memory 0x41000000 0x41021FFF W
|
||||
Memory8 = HPB2 Memory 0x42000000 0x42003BFF W
|
||||
Memory9 = HPB3 Memory 0x43000000 0x43002FFF W
|
||||
Memory10 = NVMCTRL2 Memory 0x44000000 0x4401FFFF W
|
||||
Memory11 = SDHC0 Memory 0x45000000 0x45000BFF W
|
||||
Memory12 = SDHC1 Memory 0x46000000 0x46000BFF W
|
||||
Memory13 = CMCC_DATARAM Memory 0x03000000 0x03000FFF RW
|
||||
Memory14 = CMCC_TAGRAM Memory 0x03001000 0x030013FF RW
|
||||
Memory15 = CMCC_VALIDRAM Memory 0x03002000 0x0300203F RW
|
||||
|
||||
TrustedRanges = true
|
||||
UseSfrFilter = true
|
||||
|
||||
[SfrInclude]
|
||||
File = ATSAME51N20A.svd
|
||||
78
lib/same51/iar/config/debugger/Atmel/Trace_SAME51.dmac
Normal file
78
lib/same51/iar/config/debugger/Atmel/Trace_SAME51.dmac
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
// ---------------------------------------------------------
|
||||
// ATMEL Microcontroller Software Support - NANTES -
|
||||
// ---------------------------------------------------------
|
||||
// The software is delivered "AS IS" without warranty or
|
||||
// condition of any kind, either express, implied or
|
||||
// statutory. This includes without limitation any warranty
|
||||
// or condition with respect to merchantability or fitness
|
||||
// for any particular purpose, or against the infringements of
|
||||
// intellectual property rights of others.
|
||||
// ---------------------------------------------------------
|
||||
// File: Trace_SAME51.dmac
|
||||
// User setup file for CSPY debugger.
|
||||
// ---------------------------------------------------------
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* execUserReset()
|
||||
* Called once after the target application is downloaded.
|
||||
* Implement this macro to set up the memory map, breakpoints,
|
||||
* interrupts, register macro files, etc.
|
||||
*
|
||||
*/
|
||||
execUserReset()
|
||||
{
|
||||
__message "------------------------------ execUserReset ---------------------------------";
|
||||
__message "-------------------------------Set PC Reset ----------------------------------";
|
||||
__writeMemory32(0x05FA0004,0xE000ED0C,"Memory");
|
||||
//__hwReset(0);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* execUserPreload()
|
||||
* Called after communication with the target system is established
|
||||
* but before downloading the target application.
|
||||
* Implement this macro to initialize memory locations and/or
|
||||
* registers which are vital for loading data properly.
|
||||
*
|
||||
*/
|
||||
execUserPreload()
|
||||
{
|
||||
__message "------------------------------ execUserPreload ---------------------------------";
|
||||
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* execUserFlashInit()
|
||||
*
|
||||
* Called once before the flash loader is downloaded to RAM.
|
||||
* Implement this macro typically for setting up the memory map
|
||||
* required by the flash loader. This macro is only called when you
|
||||
* are programming flash, and it should only be used for flash loader
|
||||
* functionality.
|
||||
*
|
||||
*/
|
||||
|
||||
execUserFlashInit()
|
||||
{
|
||||
|
||||
__message "------------------------------ execUserFlashInit ---------------------------------";
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* execUserFlashExit()
|
||||
* Called once when the debug session ends.
|
||||
* Implement this macro to save status data etc. This macro is useful
|
||||
* for flash loader functionality
|
||||
*
|
||||
*/
|
||||
execUserFlashExit()
|
||||
{
|
||||
__message "------------------------------ execUserFlashExit ---------------------------------";
|
||||
//__hwReset(0);
|
||||
}
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
[FILEFORMAT]
|
||||
rev=1.6
|
||||
|
||||
[CHIP]
|
||||
// Chip name
|
||||
name=ATSAME51G18A
|
||||
|
||||
// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
|
||||
endiansupport=le
|
||||
|
||||
// Does the chip support the thumb instruction set? (true(default), false)
|
||||
thumbsupport=true
|
||||
|
||||
// Does the chip support the arm instruction set? (true(default), false)
|
||||
armsupport=false
|
||||
|
||||
// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFPv5_SP, VFP9-S, MaverickCrunch, None(default))
|
||||
fpu=VFPv4
|
||||
|
||||
// Chip specific macros
|
||||
//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAME51.mac
|
||||
|
||||
//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
|
||||
JTAG=false
|
||||
RTCK=false
|
||||
SWD=true
|
||||
SWO_TraceD0=false
|
||||
|
||||
[CORE]
|
||||
// Name of ARM processor core
|
||||
name=Cortex-M4
|
||||
|
||||
[DDF FILE]
|
||||
name=Atmel\ATSAME51G18A.ddf
|
||||
|
||||
[LINKER FILE]
|
||||
//Name of the linker config file
|
||||
name=$TOOLKIT_DIR$\config\linker\Atmel\same51g18a\flash.icf
|
||||
|
||||
[FLASH LOADER]
|
||||
little=$TOOLKIT_DIR$\config\flashloader\Atmel\same51g18a\same51g18a-flash.board
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<optionMenuItem>
|
||||
<tag>ATSAME51G18A</tag>
|
||||
<display>Atmel ATSAME51G18A</display>
|
||||
<data>$CUR_DIR$\ATSAME51G18A.i79</data>
|
||||
</optionMenuItem>
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
[FILEFORMAT]
|
||||
rev=1.6
|
||||
|
||||
[CHIP]
|
||||
// Chip name
|
||||
name=ATSAME51G19A
|
||||
|
||||
// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
|
||||
endiansupport=le
|
||||
|
||||
// Does the chip support the thumb instruction set? (true(default), false)
|
||||
thumbsupport=true
|
||||
|
||||
// Does the chip support the arm instruction set? (true(default), false)
|
||||
armsupport=false
|
||||
|
||||
// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFPv5_SP, VFP9-S, MaverickCrunch, None(default))
|
||||
fpu=VFPv4
|
||||
|
||||
// Chip specific macros
|
||||
//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAME51.mac
|
||||
|
||||
//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
|
||||
JTAG=false
|
||||
RTCK=false
|
||||
SWD=true
|
||||
SWO_TraceD0=false
|
||||
|
||||
[CORE]
|
||||
// Name of ARM processor core
|
||||
name=Cortex-M4
|
||||
|
||||
[DDF FILE]
|
||||
name=Atmel\ATSAME51G19A.ddf
|
||||
|
||||
[LINKER FILE]
|
||||
//Name of the linker config file
|
||||
name=$TOOLKIT_DIR$\config\linker\Atmel\same51g19a\flash.icf
|
||||
|
||||
[FLASH LOADER]
|
||||
little=$TOOLKIT_DIR$\config\flashloader\Atmel\same51g19a\same51g19a-flash.board
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<optionMenuItem>
|
||||
<tag>ATSAME51G19A</tag>
|
||||
<display>Atmel ATSAME51G19A</display>
|
||||
<data>$CUR_DIR$\ATSAME51G19A.i79</data>
|
||||
</optionMenuItem>
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
[FILEFORMAT]
|
||||
rev=1.6
|
||||
|
||||
[CHIP]
|
||||
// Chip name
|
||||
name=ATSAME51J18A
|
||||
|
||||
// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
|
||||
endiansupport=le
|
||||
|
||||
// Does the chip support the thumb instruction set? (true(default), false)
|
||||
thumbsupport=true
|
||||
|
||||
// Does the chip support the arm instruction set? (true(default), false)
|
||||
armsupport=false
|
||||
|
||||
// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFPv5_SP, VFP9-S, MaverickCrunch, None(default))
|
||||
fpu=VFPv4
|
||||
|
||||
// Chip specific macros
|
||||
//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAME51.mac
|
||||
|
||||
//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
|
||||
JTAG=false
|
||||
RTCK=false
|
||||
SWD=true
|
||||
SWO_TraceD0=false
|
||||
|
||||
[CORE]
|
||||
// Name of ARM processor core
|
||||
name=Cortex-M4
|
||||
|
||||
[DDF FILE]
|
||||
name=Atmel\ATSAME51J18A.ddf
|
||||
|
||||
[LINKER FILE]
|
||||
//Name of the linker config file
|
||||
name=$TOOLKIT_DIR$\config\linker\Atmel\same51j18a\flash.icf
|
||||
|
||||
[FLASH LOADER]
|
||||
little=$TOOLKIT_DIR$\config\flashloader\Atmel\same51j18a\same51j18a-flash.board
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<optionMenuItem>
|
||||
<tag>ATSAME51J18A</tag>
|
||||
<display>Atmel ATSAME51J18A</display>
|
||||
<data>$CUR_DIR$\ATSAME51J18A.i79</data>
|
||||
</optionMenuItem>
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
[FILEFORMAT]
|
||||
rev=1.6
|
||||
|
||||
[CHIP]
|
||||
// Chip name
|
||||
name=ATSAME51J19A
|
||||
|
||||
// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
|
||||
endiansupport=le
|
||||
|
||||
// Does the chip support the thumb instruction set? (true(default), false)
|
||||
thumbsupport=true
|
||||
|
||||
// Does the chip support the arm instruction set? (true(default), false)
|
||||
armsupport=false
|
||||
|
||||
// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFPv5_SP, VFP9-S, MaverickCrunch, None(default))
|
||||
fpu=VFPv4
|
||||
|
||||
// Chip specific macros
|
||||
//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAME51.mac
|
||||
|
||||
//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
|
||||
JTAG=false
|
||||
RTCK=false
|
||||
SWD=true
|
||||
SWO_TraceD0=false
|
||||
|
||||
[CORE]
|
||||
// Name of ARM processor core
|
||||
name=Cortex-M4
|
||||
|
||||
[DDF FILE]
|
||||
name=Atmel\ATSAME51J19A.ddf
|
||||
|
||||
[LINKER FILE]
|
||||
//Name of the linker config file
|
||||
name=$TOOLKIT_DIR$\config\linker\Atmel\same51j19a\flash.icf
|
||||
|
||||
[FLASH LOADER]
|
||||
little=$TOOLKIT_DIR$\config\flashloader\Atmel\same51j19a\same51j19a-flash.board
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<optionMenuItem>
|
||||
<tag>ATSAME51J19A</tag>
|
||||
<display>Atmel ATSAME51J19A</display>
|
||||
<data>$CUR_DIR$\ATSAME51J19A.i79</data>
|
||||
</optionMenuItem>
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
[FILEFORMAT]
|
||||
rev=1.6
|
||||
|
||||
[CHIP]
|
||||
// Chip name
|
||||
name=ATSAME51J20A
|
||||
|
||||
// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
|
||||
endiansupport=le
|
||||
|
||||
// Does the chip support the thumb instruction set? (true(default), false)
|
||||
thumbsupport=true
|
||||
|
||||
// Does the chip support the arm instruction set? (true(default), false)
|
||||
armsupport=false
|
||||
|
||||
// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFPv5_SP, VFP9-S, MaverickCrunch, None(default))
|
||||
fpu=VFPv4
|
||||
|
||||
// Chip specific macros
|
||||
//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAME51.mac
|
||||
|
||||
//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
|
||||
JTAG=false
|
||||
RTCK=false
|
||||
SWD=true
|
||||
SWO_TraceD0=false
|
||||
|
||||
[CORE]
|
||||
// Name of ARM processor core
|
||||
name=Cortex-M4
|
||||
|
||||
[DDF FILE]
|
||||
name=Atmel\ATSAME51J20A.ddf
|
||||
|
||||
[LINKER FILE]
|
||||
//Name of the linker config file
|
||||
name=$TOOLKIT_DIR$\config\linker\Atmel\same51j20a\flash.icf
|
||||
|
||||
[FLASH LOADER]
|
||||
little=$TOOLKIT_DIR$\config\flashloader\Atmel\same51j20a\same51j20a-flash.board
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<optionMenuItem>
|
||||
<tag>ATSAME51J20A</tag>
|
||||
<display>Atmel ATSAME51J20A</display>
|
||||
<data>$CUR_DIR$\ATSAME51J20A.i79</data>
|
||||
</optionMenuItem>
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
[FILEFORMAT]
|
||||
rev=1.6
|
||||
|
||||
[CHIP]
|
||||
// Chip name
|
||||
name=ATSAME51N19A
|
||||
|
||||
// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
|
||||
endiansupport=le
|
||||
|
||||
// Does the chip support the thumb instruction set? (true(default), false)
|
||||
thumbsupport=true
|
||||
|
||||
// Does the chip support the arm instruction set? (true(default), false)
|
||||
armsupport=false
|
||||
|
||||
// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFPv5_SP, VFP9-S, MaverickCrunch, None(default))
|
||||
fpu=VFPv4
|
||||
|
||||
// Chip specific macros
|
||||
//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAME51.mac
|
||||
|
||||
//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
|
||||
JTAG=false
|
||||
RTCK=false
|
||||
SWD=true
|
||||
SWO_TraceD0=false
|
||||
|
||||
[CORE]
|
||||
// Name of ARM processor core
|
||||
name=Cortex-M4
|
||||
|
||||
[DDF FILE]
|
||||
name=Atmel\ATSAME51N19A.ddf
|
||||
|
||||
[LINKER FILE]
|
||||
//Name of the linker config file
|
||||
name=$TOOLKIT_DIR$\config\linker\Atmel\same51n19a\flash.icf
|
||||
|
||||
[FLASH LOADER]
|
||||
little=$TOOLKIT_DIR$\config\flashloader\Atmel\same51n19a\same51n19a-flash.board
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<optionMenuItem>
|
||||
<tag>ATSAME51N19A</tag>
|
||||
<display>Atmel ATSAME51N19A</display>
|
||||
<data>$CUR_DIR$\ATSAME51N19A.i79</data>
|
||||
</optionMenuItem>
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
[FILEFORMAT]
|
||||
rev=1.6
|
||||
|
||||
[CHIP]
|
||||
// Chip name
|
||||
name=ATSAME51N20A
|
||||
|
||||
// What endian modes does the chip support? (le_be8_be32(default), le_be8, le_be32, le, be8_be32, be8, be32)
|
||||
endiansupport=le
|
||||
|
||||
// Does the chip support the thumb instruction set? (true(default), false)
|
||||
thumbsupport=true
|
||||
|
||||
// Does the chip support the arm instruction set? (true(default), false)
|
||||
armsupport=false
|
||||
|
||||
// Does the chip have an FPU coprocessor? (VFPv1, VFPv2, VFPv4, VFPv5_SP, VFP9-S, MaverickCrunch, None(default))
|
||||
fpu=VFPv4
|
||||
|
||||
// Chip specific macros
|
||||
//DeviceMacros=$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAME51.mac
|
||||
|
||||
//Debugger interface, default JTAG=true, RTCK=true, SWD=true if Cortex cores, SWD=false if ARM cores, SWO_TraceD0=false
|
||||
JTAG=false
|
||||
RTCK=false
|
||||
SWD=true
|
||||
SWO_TraceD0=false
|
||||
|
||||
[CORE]
|
||||
// Name of ARM processor core
|
||||
name=Cortex-M4
|
||||
|
||||
[DDF FILE]
|
||||
name=Atmel\ATSAME51N20A.ddf
|
||||
|
||||
[LINKER FILE]
|
||||
//Name of the linker config file
|
||||
name=$TOOLKIT_DIR$\config\linker\Atmel\same51n20a\flash.icf
|
||||
|
||||
[FLASH LOADER]
|
||||
little=$TOOLKIT_DIR$\config\flashloader\Atmel\same51n20a\same51n20a-flash.board
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<optionMenuItem>
|
||||
<tag>ATSAME51N20A</tag>
|
||||
<display>Atmel ATSAME51N20A</display>
|
||||
<data>$CUR_DIR$\ATSAME51N20A.i79</data>
|
||||
</optionMenuItem>
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_board>
|
||||
<pass>
|
||||
<loader>$TOOLKIT_DIR$\config\flashloader\Atmel\same51g18a\same51g18a-flash.flash</loader>
|
||||
<range>CODE 0x00000000 0x0003FFFF</range>
|
||||
<rel_offset>0x0</rel_offset>
|
||||
</pass>
|
||||
</flash_board>
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>$TOOLKIT_DIR$\config\flashloader\Atmel\same51g18a\same51g18a-flash.out</exe>
|
||||
<flash_base>0x00000000</flash_base>
|
||||
<page>512</page>
|
||||
<block>32 0x2000</block> <!-- 32 blocks of 8192 bytes -->
|
||||
<macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAME51.mac</macro>
|
||||
<aggregate>0</aggregate>
|
||||
<args/>
|
||||
<args_doc>--debug : Print debug information such flash size and step done during flashloader process
|
||||
--dump_buffer : dump input buffer of function FlashWrite
|
||||
--dump_flash : dump flash after programming given buffer from FlashWrite function
|
||||
</args_doc>
|
||||
</flash_device>
|
||||
Binary file not shown.
|
|
@ -0,0 +1,9 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_board>
|
||||
<pass>
|
||||
<loader>$TOOLKIT_DIR$\config\flashloader\Atmel\same51g19a\same51g19a-flash.flash</loader>
|
||||
<range>CODE 0x00000000 0x0007FFFF</range>
|
||||
<rel_offset>0x0</rel_offset>
|
||||
</pass>
|
||||
</flash_board>
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>$TOOLKIT_DIR$\config\flashloader\Atmel\same51g19a\same51g19a-flash.out</exe>
|
||||
<flash_base>0x00000000</flash_base>
|
||||
<page>512</page>
|
||||
<block>64 0x2000</block> <!-- 64 blocks of 8192 bytes -->
|
||||
<macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAME51.mac</macro>
|
||||
<aggregate>0</aggregate>
|
||||
<args/>
|
||||
<args_doc>--debug : Print debug information such flash size and step done during flashloader process
|
||||
--dump_buffer : dump input buffer of function FlashWrite
|
||||
--dump_flash : dump flash after programming given buffer from FlashWrite function
|
||||
</args_doc>
|
||||
</flash_device>
|
||||
Binary file not shown.
|
|
@ -0,0 +1,9 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_board>
|
||||
<pass>
|
||||
<loader>$TOOLKIT_DIR$\config\flashloader\Atmel\same51j18a\same51j18a-flash.flash</loader>
|
||||
<range>CODE 0x00000000 0x0003FFFF</range>
|
||||
<rel_offset>0x0</rel_offset>
|
||||
</pass>
|
||||
</flash_board>
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>$TOOLKIT_DIR$\config\flashloader\Atmel\same51j18a\same51j18a-flash.out</exe>
|
||||
<flash_base>0x00000000</flash_base>
|
||||
<page>512</page>
|
||||
<block>32 0x2000</block> <!-- 32 blocks of 8192 bytes -->
|
||||
<macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAME51.mac</macro>
|
||||
<aggregate>0</aggregate>
|
||||
<args/>
|
||||
<args_doc>--debug : Print debug information such flash size and step done during flashloader process
|
||||
--dump_buffer : dump input buffer of function FlashWrite
|
||||
--dump_flash : dump flash after programming given buffer from FlashWrite function
|
||||
</args_doc>
|
||||
</flash_device>
|
||||
Binary file not shown.
|
|
@ -0,0 +1,9 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_board>
|
||||
<pass>
|
||||
<loader>$TOOLKIT_DIR$\config\flashloader\Atmel\same51j19a\same51j19a-flash.flash</loader>
|
||||
<range>CODE 0x00000000 0x0007FFFF</range>
|
||||
<rel_offset>0x0</rel_offset>
|
||||
</pass>
|
||||
</flash_board>
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>$TOOLKIT_DIR$\config\flashloader\Atmel\same51j19a\same51j19a-flash.out</exe>
|
||||
<flash_base>0x00000000</flash_base>
|
||||
<page>512</page>
|
||||
<block>64 0x2000</block> <!-- 64 blocks of 8192 bytes -->
|
||||
<macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAME51.mac</macro>
|
||||
<aggregate>0</aggregate>
|
||||
<args/>
|
||||
<args_doc>--debug : Print debug information such flash size and step done during flashloader process
|
||||
--dump_buffer : dump input buffer of function FlashWrite
|
||||
--dump_flash : dump flash after programming given buffer from FlashWrite function
|
||||
</args_doc>
|
||||
</flash_device>
|
||||
Binary file not shown.
|
|
@ -0,0 +1,9 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_board>
|
||||
<pass>
|
||||
<loader>$TOOLKIT_DIR$\config\flashloader\Atmel\same51j20a\same51j20a-flash.flash</loader>
|
||||
<range>CODE 0x00000000 0x000FFFFF</range>
|
||||
<rel_offset>0x0</rel_offset>
|
||||
</pass>
|
||||
</flash_board>
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>$TOOLKIT_DIR$\config\flashloader\Atmel\same51j20a\same51j20a-flash.out</exe>
|
||||
<flash_base>0x00000000</flash_base>
|
||||
<page>512</page>
|
||||
<block>128 0x2000</block> <!-- 128 blocks of 8192 bytes -->
|
||||
<macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAME51.mac</macro>
|
||||
<aggregate>0</aggregate>
|
||||
<args/>
|
||||
<args_doc>--debug : Print debug information such flash size and step done during flashloader process
|
||||
--dump_buffer : dump input buffer of function FlashWrite
|
||||
--dump_flash : dump flash after programming given buffer from FlashWrite function
|
||||
</args_doc>
|
||||
</flash_device>
|
||||
Binary file not shown.
|
|
@ -0,0 +1,9 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_board>
|
||||
<pass>
|
||||
<loader>$TOOLKIT_DIR$\config\flashloader\Atmel\same51n19a\same51n19a-flash.flash</loader>
|
||||
<range>CODE 0x00000000 0x0007FFFF</range>
|
||||
<rel_offset>0x0</rel_offset>
|
||||
</pass>
|
||||
</flash_board>
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>$TOOLKIT_DIR$\config\flashloader\Atmel\same51n19a\same51n19a-flash.out</exe>
|
||||
<flash_base>0x00000000</flash_base>
|
||||
<page>512</page>
|
||||
<block>64 0x2000</block> <!-- 64 blocks of 8192 bytes -->
|
||||
<macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAME51.mac</macro>
|
||||
<aggregate>0</aggregate>
|
||||
<args/>
|
||||
<args_doc>--debug : Print debug information such flash size and step done during flashloader process
|
||||
--dump_buffer : dump input buffer of function FlashWrite
|
||||
--dump_flash : dump flash after programming given buffer from FlashWrite function
|
||||
</args_doc>
|
||||
</flash_device>
|
||||
Binary file not shown.
|
|
@ -0,0 +1,9 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_board>
|
||||
<pass>
|
||||
<loader>$TOOLKIT_DIR$\config\flashloader\Atmel\same51n20a\same51n20a-flash.flash</loader>
|
||||
<range>CODE 0x00000000 0x000FFFFF</range>
|
||||
<rel_offset>0x0</rel_offset>
|
||||
</pass>
|
||||
</flash_board>
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>$TOOLKIT_DIR$\config\flashloader\Atmel\same51n20a\same51n20a-flash.out</exe>
|
||||
<flash_base>0x00000000</flash_base>
|
||||
<page>512</page>
|
||||
<block>128 0x2000</block> <!-- 128 blocks of 8192 bytes -->
|
||||
<macro>$TOOLKIT_DIR$\config\debugger\Atmel\Trace_SAME51.mac</macro>
|
||||
<aggregate>0</aggregate>
|
||||
<args/>
|
||||
<args_doc>--debug : Print debug information such flash size and step done during flashloader process
|
||||
--dump_buffer : dump input buffer of function FlashWrite
|
||||
--dump_flash : dump flash after programming given buffer from FlashWrite function
|
||||
</args_doc>
|
||||
</flash_device>
|
||||
Binary file not shown.
71
lib/same51/iar/iar/same51g18a_flash.icf
Normal file
71
lib/same51/iar/iar/same51g18a_flash.icf
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51G18A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF;
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x8000;
|
||||
}
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
initialize manually { section .qspi };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place at end of RAM_region { block CSTACK, block HEAP };
|
||||
place in BKUPRAM_region { section .bkupram };
|
||||
place in QSPI_region { section .qspi };
|
||||
68
lib/same51/iar/iar/same51g18a_sram.icf
Normal file
68
lib/same51/iar/iar/same51g18a_sram.icf
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51G18A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF;
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x8000;
|
||||
}
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy with packing=none { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
initialize manually { section .qspi };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in RAM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place at end of RAM_region { block CSTACK, block HEAP };
|
||||
place in BKUPRAM_region { section .bkupram };
|
||||
place in QSPI_region { section .qspi };
|
||||
71
lib/same51/iar/iar/same51g19a_flash.icf
Normal file
71
lib/same51/iar/iar/same51g19a_flash.icf
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51G19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF;
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = 0xC000;
|
||||
}
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
initialize manually { section .qspi };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place at end of RAM_region { block CSTACK, block HEAP };
|
||||
place in BKUPRAM_region { section .bkupram };
|
||||
place in QSPI_region { section .qspi };
|
||||
68
lib/same51/iar/iar/same51g19a_sram.icf
Normal file
68
lib/same51/iar/iar/same51g19a_sram.icf
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51G19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF;
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = 0xC000;
|
||||
}
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy with packing=none { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
initialize manually { section .qspi };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in RAM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place at end of RAM_region { block CSTACK, block HEAP };
|
||||
place in BKUPRAM_region { section .bkupram };
|
||||
place in QSPI_region { section .qspi };
|
||||
71
lib/same51/iar/iar/same51j18a_flash.icf
Normal file
71
lib/same51/iar/iar/same51j18a_flash.icf
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51J18A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF;
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x8000;
|
||||
}
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
initialize manually { section .qspi };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place at end of RAM_region { block CSTACK, block HEAP };
|
||||
place in BKUPRAM_region { section .bkupram };
|
||||
place in QSPI_region { section .qspi };
|
||||
68
lib/same51/iar/iar/same51j18a_sram.icf
Normal file
68
lib/same51/iar/iar/same51j18a_sram.icf
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51J18A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF;
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x8000;
|
||||
}
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy with packing=none { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
initialize manually { section .qspi };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in RAM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place at end of RAM_region { block CSTACK, block HEAP };
|
||||
place in BKUPRAM_region { section .bkupram };
|
||||
place in QSPI_region { section .qspi };
|
||||
71
lib/same51/iar/iar/same51j19a_flash.icf
Normal file
71
lib/same51/iar/iar/same51j19a_flash.icf
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51J19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF;
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = 0xC000;
|
||||
}
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
initialize manually { section .qspi };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place at end of RAM_region { block CSTACK, block HEAP };
|
||||
place in BKUPRAM_region { section .bkupram };
|
||||
place in QSPI_region { section .qspi };
|
||||
68
lib/same51/iar/iar/same51j19a_sram.icf
Normal file
68
lib/same51/iar/iar/same51j19a_sram.icf
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51J19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF;
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = 0xC000;
|
||||
}
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy with packing=none { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
initialize manually { section .qspi };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in RAM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place at end of RAM_region { block CSTACK, block HEAP };
|
||||
place in BKUPRAM_region { section .bkupram };
|
||||
place in QSPI_region { section .qspi };
|
||||
71
lib/same51/iar/iar/same51j20a_flash.icf
Normal file
71
lib/same51/iar/iar/same51j20a_flash.icf
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51J20A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF;
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x10000;
|
||||
}
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
initialize manually { section .qspi };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place at end of RAM_region { block CSTACK, block HEAP };
|
||||
place in BKUPRAM_region { section .bkupram };
|
||||
place in QSPI_region { section .qspi };
|
||||
68
lib/same51/iar/iar/same51j20a_sram.icf
Normal file
68
lib/same51/iar/iar/same51j20a_sram.icf
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51J20A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF;
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x10000;
|
||||
}
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy with packing=none { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
initialize manually { section .qspi };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in RAM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place at end of RAM_region { block CSTACK, block HEAP };
|
||||
place in BKUPRAM_region { section .bkupram };
|
||||
place in QSPI_region { section .qspi };
|
||||
71
lib/same51/iar/iar/same51n19a_flash.icf
Normal file
71
lib/same51/iar/iar/same51n19a_flash.icf
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51N19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF;
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = 0xC000;
|
||||
}
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
initialize manually { section .qspi };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place at end of RAM_region { block CSTACK, block HEAP };
|
||||
place in BKUPRAM_region { section .bkupram };
|
||||
place in QSPI_region { section .qspi };
|
||||
68
lib/same51/iar/iar/same51n19a_sram.icf
Normal file
68
lib/same51/iar/iar/same51n19a_sram.icf
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51N19A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF;
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = 0xC000;
|
||||
}
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy with packing=none { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
initialize manually { section .qspi };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in RAM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place at end of RAM_region { block CSTACK, block HEAP };
|
||||
place in BKUPRAM_region { section .bkupram };
|
||||
place in QSPI_region { section .qspi };
|
||||
71
lib/same51/iar/iar/same51n20a_flash.icf
Normal file
71
lib/same51/iar/iar/same51n20a_flash.icf
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal FLASH on the SAME51N20A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF;
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x10000;
|
||||
}
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
initialize manually { section .qspi };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place at end of RAM_region { block CSTACK, block HEAP };
|
||||
place in BKUPRAM_region { section .bkupram };
|
||||
place in QSPI_region { section .qspi };
|
||||
68
lib/same51/iar/iar/same51n20a_sram.icf
Normal file
68
lib/same51/iar/iar/same51n20a_sram.icf
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Linker script for running in internal SRAM on the SAME51N20A
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000;
|
||||
define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF;
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF;
|
||||
/*-Sizes-*/
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x10000;
|
||||
}
|
||||
if (!isdefinedsymbol(__ICFEDIT_size_heap__)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy with packing=none { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
initialize manually { section .qspi };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in RAM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place at end of RAM_region { block CSTACK, block HEAP };
|
||||
place in BKUPRAM_region { section .bkupram };
|
||||
place in QSPI_region { section .qspi };
|
||||
516
lib/same51/iar/iar/startup_same51.c
Normal file
516
lib/same51/iar/iar/startup_same51.c
Normal file
|
|
@ -0,0 +1,516 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same51.h"
|
||||
|
||||
typedef void (*intfunc) (void);
|
||||
typedef union { intfunc __fun; void * __ptr; } intvec_elem;
|
||||
|
||||
void __iar_program_start(void);
|
||||
int __low_level_init(void);
|
||||
|
||||
/* Default empty handler */
|
||||
void Dummy_Handler(void);
|
||||
|
||||
/* Cortex-M4 core handlers */
|
||||
#pragma weak NonMaskableInt_Handler = Dummy_Handler
|
||||
#pragma weak HardFault_Handler = Dummy_Handler
|
||||
#pragma weak MemManagement_Handler = Dummy_Handler
|
||||
#pragma weak BusFault_Handler = Dummy_Handler
|
||||
#pragma weak UsageFault_Handler = Dummy_Handler
|
||||
#pragma weak SVCall_Handler = Dummy_Handler
|
||||
#pragma weak DebugMonitor_Handler = Dummy_Handler
|
||||
#pragma weak PendSV_Handler = Dummy_Handler
|
||||
#pragma weak SysTick_Handler = Dummy_Handler
|
||||
|
||||
/* Peripherals handlers */
|
||||
#pragma weak PM_Handler = Dummy_Handler
|
||||
#pragma weak MCLK_Handler = Dummy_Handler
|
||||
#pragma weak OSCCTRL_0_Handler = Dummy_Handler /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
|
||||
#pragma weak OSCCTRL_1_Handler = Dummy_Handler /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
|
||||
#pragma weak OSCCTRL_2_Handler = Dummy_Handler /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
|
||||
#pragma weak OSCCTRL_3_Handler = Dummy_Handler /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
|
||||
#pragma weak OSCCTRL_4_Handler = Dummy_Handler /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
|
||||
#pragma weak OSC32KCTRL_Handler = Dummy_Handler
|
||||
#pragma weak SUPC_0_Handler = Dummy_Handler /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
|
||||
#pragma weak SUPC_1_Handler = Dummy_Handler /* SUPC_BOD12DET, SUPC_BOD33DET */
|
||||
#pragma weak WDT_Handler = Dummy_Handler
|
||||
#pragma weak RTC_Handler = Dummy_Handler
|
||||
#pragma weak EIC_0_Handler = Dummy_Handler /* EIC_EXTINT_0 */
|
||||
#pragma weak EIC_1_Handler = Dummy_Handler /* EIC_EXTINT_1 */
|
||||
#pragma weak EIC_2_Handler = Dummy_Handler /* EIC_EXTINT_2 */
|
||||
#pragma weak EIC_3_Handler = Dummy_Handler /* EIC_EXTINT_3 */
|
||||
#pragma weak EIC_4_Handler = Dummy_Handler /* EIC_EXTINT_4 */
|
||||
#pragma weak EIC_5_Handler = Dummy_Handler /* EIC_EXTINT_5 */
|
||||
#pragma weak EIC_6_Handler = Dummy_Handler /* EIC_EXTINT_6 */
|
||||
#pragma weak EIC_7_Handler = Dummy_Handler /* EIC_EXTINT_7 */
|
||||
#pragma weak EIC_8_Handler = Dummy_Handler /* EIC_EXTINT_8 */
|
||||
#pragma weak EIC_9_Handler = Dummy_Handler /* EIC_EXTINT_9 */
|
||||
#pragma weak EIC_10_Handler = Dummy_Handler /* EIC_EXTINT_10 */
|
||||
#pragma weak EIC_11_Handler = Dummy_Handler /* EIC_EXTINT_11 */
|
||||
#pragma weak EIC_12_Handler = Dummy_Handler /* EIC_EXTINT_12 */
|
||||
#pragma weak EIC_13_Handler = Dummy_Handler /* EIC_EXTINT_13 */
|
||||
#pragma weak EIC_14_Handler = Dummy_Handler /* EIC_EXTINT_14 */
|
||||
#pragma weak EIC_15_Handler = Dummy_Handler /* EIC_EXTINT_15 */
|
||||
#pragma weak FREQM_Handler = Dummy_Handler
|
||||
#pragma weak NVMCTRL_0_Handler = Dummy_Handler /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
|
||||
#pragma weak NVMCTRL_1_Handler = Dummy_Handler /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
|
||||
#pragma weak DMAC_0_Handler = Dummy_Handler /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
|
||||
#pragma weak DMAC_1_Handler = Dummy_Handler /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
|
||||
#pragma weak DMAC_2_Handler = Dummy_Handler /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
|
||||
#pragma weak DMAC_3_Handler = Dummy_Handler /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
|
||||
#pragma weak DMAC_4_Handler = Dummy_Handler /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
|
||||
#pragma weak EVSYS_0_Handler = Dummy_Handler /* EVSYS_EVD_0, EVSYS_OVR_0 */
|
||||
#pragma weak EVSYS_1_Handler = Dummy_Handler /* EVSYS_EVD_1, EVSYS_OVR_1 */
|
||||
#pragma weak EVSYS_2_Handler = Dummy_Handler /* EVSYS_EVD_2, EVSYS_OVR_2 */
|
||||
#pragma weak EVSYS_3_Handler = Dummy_Handler /* EVSYS_EVD_3, EVSYS_OVR_3 */
|
||||
#pragma weak EVSYS_4_Handler = Dummy_Handler /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
|
||||
#pragma weak PAC_Handler = Dummy_Handler
|
||||
#pragma weak RAMECC_Handler = Dummy_Handler
|
||||
#pragma weak SERCOM0_0_Handler = Dummy_Handler /* SERCOM0_0 */
|
||||
#pragma weak SERCOM0_1_Handler = Dummy_Handler /* SERCOM0_1 */
|
||||
#pragma weak SERCOM0_2_Handler = Dummy_Handler /* SERCOM0_2 */
|
||||
#pragma weak SERCOM0_3_Handler = Dummy_Handler /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
|
||||
#pragma weak SERCOM1_0_Handler = Dummy_Handler /* SERCOM1_0 */
|
||||
#pragma weak SERCOM1_1_Handler = Dummy_Handler /* SERCOM1_1 */
|
||||
#pragma weak SERCOM1_2_Handler = Dummy_Handler /* SERCOM1_2 */
|
||||
#pragma weak SERCOM1_3_Handler = Dummy_Handler /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
|
||||
#pragma weak SERCOM2_0_Handler = Dummy_Handler /* SERCOM2_0 */
|
||||
#pragma weak SERCOM2_1_Handler = Dummy_Handler /* SERCOM2_1 */
|
||||
#pragma weak SERCOM2_2_Handler = Dummy_Handler /* SERCOM2_2 */
|
||||
#pragma weak SERCOM2_3_Handler = Dummy_Handler /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
|
||||
#pragma weak SERCOM3_0_Handler = Dummy_Handler /* SERCOM3_0 */
|
||||
#pragma weak SERCOM3_1_Handler = Dummy_Handler /* SERCOM3_1 */
|
||||
#pragma weak SERCOM3_2_Handler = Dummy_Handler /* SERCOM3_2 */
|
||||
#pragma weak SERCOM3_3_Handler = Dummy_Handler /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
|
||||
#ifdef ID_SERCOM4
|
||||
#pragma weak SERCOM4_0_Handler = Dummy_Handler /* SERCOM4_0 */
|
||||
#pragma weak SERCOM4_1_Handler = Dummy_Handler /* SERCOM4_1 */
|
||||
#pragma weak SERCOM4_2_Handler = Dummy_Handler /* SERCOM4_2 */
|
||||
#pragma weak SERCOM4_3_Handler = Dummy_Handler /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
#pragma weak SERCOM5_0_Handler = Dummy_Handler /* SERCOM5_0 */
|
||||
#pragma weak SERCOM5_1_Handler = Dummy_Handler /* SERCOM5_1 */
|
||||
#pragma weak SERCOM5_2_Handler = Dummy_Handler /* SERCOM5_2 */
|
||||
#pragma weak SERCOM5_3_Handler = Dummy_Handler /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM6
|
||||
#pragma weak SERCOM6_0_Handler = Dummy_Handler /* SERCOM6_0 */
|
||||
#pragma weak SERCOM6_1_Handler = Dummy_Handler /* SERCOM6_1 */
|
||||
#pragma weak SERCOM6_2_Handler = Dummy_Handler /* SERCOM6_2 */
|
||||
#pragma weak SERCOM6_3_Handler = Dummy_Handler /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
|
||||
#endif
|
||||
#ifdef ID_SERCOM7
|
||||
#pragma weak SERCOM7_0_Handler = Dummy_Handler /* SERCOM7_0 */
|
||||
#pragma weak SERCOM7_1_Handler = Dummy_Handler /* SERCOM7_1 */
|
||||
#pragma weak SERCOM7_2_Handler = Dummy_Handler /* SERCOM7_2 */
|
||||
#pragma weak SERCOM7_3_Handler = Dummy_Handler /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
|
||||
#endif
|
||||
#ifdef ID_CAN0
|
||||
#pragma weak CAN0_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_CAN1
|
||||
#pragma weak CAN1_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_USB
|
||||
#pragma weak USB_0_Handler = Dummy_Handler /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
|
||||
#pragma weak USB_1_Handler = Dummy_Handler /* USB_SOF_HSOF */
|
||||
#pragma weak USB_2_Handler = Dummy_Handler /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
|
||||
#pragma weak USB_3_Handler = Dummy_Handler /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
|
||||
#endif
|
||||
#ifdef ID_GMAC
|
||||
#pragma weak GMAC_Handler = Dummy_Handler
|
||||
#endif
|
||||
#pragma weak TCC0_0_Handler = Dummy_Handler /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
|
||||
#pragma weak TCC0_1_Handler = Dummy_Handler /* TCC0_MC_0 */
|
||||
#pragma weak TCC0_2_Handler = Dummy_Handler /* TCC0_MC_1 */
|
||||
#pragma weak TCC0_3_Handler = Dummy_Handler /* TCC0_MC_2 */
|
||||
#pragma weak TCC0_4_Handler = Dummy_Handler /* TCC0_MC_3 */
|
||||
#pragma weak TCC0_5_Handler = Dummy_Handler /* TCC0_MC_4 */
|
||||
#pragma weak TCC0_6_Handler = Dummy_Handler /* TCC0_MC_5 */
|
||||
#pragma weak TCC1_0_Handler = Dummy_Handler /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
|
||||
#pragma weak TCC1_1_Handler = Dummy_Handler /* TCC1_MC_0 */
|
||||
#pragma weak TCC1_2_Handler = Dummy_Handler /* TCC1_MC_1 */
|
||||
#pragma weak TCC1_3_Handler = Dummy_Handler /* TCC1_MC_2 */
|
||||
#pragma weak TCC1_4_Handler = Dummy_Handler /* TCC1_MC_3 */
|
||||
#pragma weak TCC2_0_Handler = Dummy_Handler /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
|
||||
#pragma weak TCC2_1_Handler = Dummy_Handler /* TCC2_MC_0 */
|
||||
#pragma weak TCC2_2_Handler = Dummy_Handler /* TCC2_MC_1 */
|
||||
#pragma weak TCC2_3_Handler = Dummy_Handler /* TCC2_MC_2 */
|
||||
#ifdef ID_TCC3
|
||||
#pragma weak TCC3_0_Handler = Dummy_Handler /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
|
||||
#pragma weak TCC3_1_Handler = Dummy_Handler /* TCC3_MC_0 */
|
||||
#pragma weak TCC3_2_Handler = Dummy_Handler /* TCC3_MC_1 */
|
||||
#endif
|
||||
#ifdef ID_TCC4
|
||||
#pragma weak TCC4_0_Handler = Dummy_Handler /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
|
||||
#pragma weak TCC4_1_Handler = Dummy_Handler /* TCC4_MC_0 */
|
||||
#pragma weak TCC4_2_Handler = Dummy_Handler /* TCC4_MC_1 */
|
||||
#endif
|
||||
#pragma weak TC0_Handler = Dummy_Handler
|
||||
#pragma weak TC1_Handler = Dummy_Handler
|
||||
#pragma weak TC2_Handler = Dummy_Handler
|
||||
#pragma weak TC3_Handler = Dummy_Handler
|
||||
#ifdef ID_TC4
|
||||
#pragma weak TC4_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_TC5
|
||||
#pragma weak TC5_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_TC6
|
||||
#pragma weak TC6_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_TC7
|
||||
#pragma weak TC7_Handler = Dummy_Handler
|
||||
#endif
|
||||
#pragma weak PDEC_0_Handler = Dummy_Handler /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
|
||||
#pragma weak PDEC_1_Handler = Dummy_Handler /* PDEC_MC_0 */
|
||||
#pragma weak PDEC_2_Handler = Dummy_Handler /* PDEC_MC_1 */
|
||||
#pragma weak ADC0_0_Handler = Dummy_Handler /* ADC0_OVERRUN, ADC0_WINMON */
|
||||
#pragma weak ADC0_1_Handler = Dummy_Handler /* ADC0_RESRDY */
|
||||
#pragma weak ADC1_0_Handler = Dummy_Handler /* ADC1_OVERRUN, ADC1_WINMON */
|
||||
#pragma weak ADC1_1_Handler = Dummy_Handler /* ADC1_RESRDY */
|
||||
#pragma weak AC_Handler = Dummy_Handler
|
||||
#pragma weak DAC_0_Handler = Dummy_Handler /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
|
||||
#pragma weak DAC_1_Handler = Dummy_Handler /* DAC_EMPTY_0 */
|
||||
#pragma weak DAC_2_Handler = Dummy_Handler /* DAC_EMPTY_1 */
|
||||
#pragma weak DAC_3_Handler = Dummy_Handler /* DAC_RESRDY_0 */
|
||||
#pragma weak DAC_4_Handler = Dummy_Handler /* DAC_RESRDY_1 */
|
||||
#ifdef ID_I2S
|
||||
#pragma weak I2S_Handler = Dummy_Handler
|
||||
#endif
|
||||
#pragma weak PCC_Handler = Dummy_Handler
|
||||
#pragma weak AES_Handler = Dummy_Handler
|
||||
#pragma weak TRNG_Handler = Dummy_Handler
|
||||
#ifdef ID_ICM
|
||||
#pragma weak ICM_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_PUKCC
|
||||
#pragma weak PUKCC_Handler = Dummy_Handler
|
||||
#endif
|
||||
#pragma weak QSPI_Handler = Dummy_Handler
|
||||
#ifdef ID_SDHC0
|
||||
#pragma weak SDHC0_Handler = Dummy_Handler
|
||||
#endif
|
||||
#ifdef ID_SDHC1
|
||||
#pragma weak SDHC1_Handler = Dummy_Handler
|
||||
#endif
|
||||
|
||||
/* Exception Table */
|
||||
#pragma language = extended
|
||||
#pragma segment = "CSTACK"
|
||||
|
||||
/* The name "__vector_table" has special meaning for C-SPY: */
|
||||
/* it is where the SP start value is found, and the NVIC vector */
|
||||
/* table register (VTOR) is initialized to this address if != 0 */
|
||||
|
||||
#pragma section = ".intvec"
|
||||
#pragma location = ".intvec"
|
||||
const DeviceVectors __vector_table[] = {
|
||||
(void*) __sfe("CSTACK"),
|
||||
(void*) Reset_Handler,
|
||||
(void*) NonMaskableInt_Handler,
|
||||
(void*) HardFault_Handler,
|
||||
(void*) MemManagement_Handler,
|
||||
(void*) BusFault_Handler,
|
||||
(void*) UsageFault_Handler,
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) SVCall_Handler,
|
||||
(void*) DebugMonitor_Handler,
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) PendSV_Handler,
|
||||
(void*) SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
(void*) PM_Handler, /* 0 Power Manager */
|
||||
(void*) MCLK_Handler, /* 1 Main Clock */
|
||||
(void*) OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
|
||||
(void*) OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
|
||||
(void*) OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
|
||||
(void*) OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
|
||||
(void*) OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
|
||||
(void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
|
||||
(void*) SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
|
||||
(void*) SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */
|
||||
(void*) WDT_Handler, /* 10 Watchdog Timer */
|
||||
(void*) RTC_Handler, /* 11 Real-Time Counter */
|
||||
(void*) EIC_0_Handler, /* 12 EIC_EXTINT_0 */
|
||||
(void*) EIC_1_Handler, /* 13 EIC_EXTINT_1 */
|
||||
(void*) EIC_2_Handler, /* 14 EIC_EXTINT_2 */
|
||||
(void*) EIC_3_Handler, /* 15 EIC_EXTINT_3 */
|
||||
(void*) EIC_4_Handler, /* 16 EIC_EXTINT_4 */
|
||||
(void*) EIC_5_Handler, /* 17 EIC_EXTINT_5 */
|
||||
(void*) EIC_6_Handler, /* 18 EIC_EXTINT_6 */
|
||||
(void*) EIC_7_Handler, /* 19 EIC_EXTINT_7 */
|
||||
(void*) EIC_8_Handler, /* 20 EIC_EXTINT_8 */
|
||||
(void*) EIC_9_Handler, /* 21 EIC_EXTINT_9 */
|
||||
(void*) EIC_10_Handler, /* 22 EIC_EXTINT_10 */
|
||||
(void*) EIC_11_Handler, /* 23 EIC_EXTINT_11 */
|
||||
(void*) EIC_12_Handler, /* 24 EIC_EXTINT_12 */
|
||||
(void*) EIC_13_Handler, /* 25 EIC_EXTINT_13 */
|
||||
(void*) EIC_14_Handler, /* 26 EIC_EXTINT_14 */
|
||||
(void*) EIC_15_Handler, /* 27 EIC_EXTINT_15 */
|
||||
(void*) FREQM_Handler, /* 28 Frequency Meter */
|
||||
(void*) NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
|
||||
(void*) NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
|
||||
(void*) DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
|
||||
(void*) DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
|
||||
(void*) DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
|
||||
(void*) DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
|
||||
(void*) DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
|
||||
(void*) EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
|
||||
(void*) EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
|
||||
(void*) EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
|
||||
(void*) EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
|
||||
(void*) EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
|
||||
(void*) PAC_Handler, /* 41 Peripheral Access Controller */
|
||||
(void*) (0UL), /* 42 Reserved */
|
||||
(void*) (0UL), /* 43 Reserved */
|
||||
(void*) (0UL), /* 44 Reserved */
|
||||
(void*) RAMECC_Handler, /* 45 RAM ECC */
|
||||
(void*) SERCOM0_0_Handler, /* 46 SERCOM0_0 */
|
||||
(void*) SERCOM0_1_Handler, /* 47 SERCOM0_1 */
|
||||
(void*) SERCOM0_2_Handler, /* 48 SERCOM0_2 */
|
||||
(void*) SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
|
||||
(void*) SERCOM1_0_Handler, /* 50 SERCOM1_0 */
|
||||
(void*) SERCOM1_1_Handler, /* 51 SERCOM1_1 */
|
||||
(void*) SERCOM1_2_Handler, /* 52 SERCOM1_2 */
|
||||
(void*) SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
|
||||
(void*) SERCOM2_0_Handler, /* 54 SERCOM2_0 */
|
||||
(void*) SERCOM2_1_Handler, /* 55 SERCOM2_1 */
|
||||
(void*) SERCOM2_2_Handler, /* 56 SERCOM2_2 */
|
||||
(void*) SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
|
||||
(void*) SERCOM3_0_Handler, /* 58 SERCOM3_0 */
|
||||
(void*) SERCOM3_1_Handler, /* 59 SERCOM3_1 */
|
||||
(void*) SERCOM3_2_Handler, /* 60 SERCOM3_2 */
|
||||
(void*) SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
|
||||
#ifdef ID_SERCOM4
|
||||
(void*) SERCOM4_0_Handler, /* 62 SERCOM4_0 */
|
||||
(void*) SERCOM4_1_Handler, /* 63 SERCOM4_1 */
|
||||
(void*) SERCOM4_2_Handler, /* 64 SERCOM4_2 */
|
||||
(void*) SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
|
||||
#else
|
||||
(void*) (0UL), /* 62 Reserved */
|
||||
(void*) (0UL), /* 63 Reserved */
|
||||
(void*) (0UL), /* 64 Reserved */
|
||||
(void*) (0UL), /* 65 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM5
|
||||
(void*) SERCOM5_0_Handler, /* 66 SERCOM5_0 */
|
||||
(void*) SERCOM5_1_Handler, /* 67 SERCOM5_1 */
|
||||
(void*) SERCOM5_2_Handler, /* 68 SERCOM5_2 */
|
||||
(void*) SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
|
||||
#else
|
||||
(void*) (0UL), /* 66 Reserved */
|
||||
(void*) (0UL), /* 67 Reserved */
|
||||
(void*) (0UL), /* 68 Reserved */
|
||||
(void*) (0UL), /* 69 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM6
|
||||
(void*) SERCOM6_0_Handler, /* 70 SERCOM6_0 */
|
||||
(void*) SERCOM6_1_Handler, /* 71 SERCOM6_1 */
|
||||
(void*) SERCOM6_2_Handler, /* 72 SERCOM6_2 */
|
||||
(void*) SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
|
||||
#else
|
||||
(void*) (0UL), /* 70 Reserved */
|
||||
(void*) (0UL), /* 71 Reserved */
|
||||
(void*) (0UL), /* 72 Reserved */
|
||||
(void*) (0UL), /* 73 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SERCOM7
|
||||
(void*) SERCOM7_0_Handler, /* 74 SERCOM7_0 */
|
||||
(void*) SERCOM7_1_Handler, /* 75 SERCOM7_1 */
|
||||
(void*) SERCOM7_2_Handler, /* 76 SERCOM7_2 */
|
||||
(void*) SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
|
||||
#else
|
||||
(void*) (0UL), /* 74 Reserved */
|
||||
(void*) (0UL), /* 75 Reserved */
|
||||
(void*) (0UL), /* 76 Reserved */
|
||||
(void*) (0UL), /* 77 Reserved */
|
||||
#endif
|
||||
#ifdef ID_CAN0
|
||||
(void*) CAN0_Handler, /* 78 Control Area Network 0 */
|
||||
#else
|
||||
(void*) (0UL), /* 78 Reserved */
|
||||
#endif
|
||||
#ifdef ID_CAN1
|
||||
(void*) CAN1_Handler, /* 79 Control Area Network 1 */
|
||||
#else
|
||||
(void*) (0UL), /* 79 Reserved */
|
||||
#endif
|
||||
#ifdef ID_USB
|
||||
(void*) USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
|
||||
(void*) USB_1_Handler, /* 81 USB_SOF_HSOF */
|
||||
(void*) USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
|
||||
(void*) USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
|
||||
#else
|
||||
(void*) (0UL), /* 80 Reserved */
|
||||
(void*) (0UL), /* 81 Reserved */
|
||||
(void*) (0UL), /* 82 Reserved */
|
||||
(void*) (0UL), /* 83 Reserved */
|
||||
#endif
|
||||
#ifdef ID_GMAC
|
||||
(void*) GMAC_Handler, /* 84 Ethernet MAC */
|
||||
#else
|
||||
(void*) (0UL), /* 84 Reserved */
|
||||
#endif
|
||||
(void*) TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
|
||||
(void*) TCC0_1_Handler, /* 86 TCC0_MC_0 */
|
||||
(void*) TCC0_2_Handler, /* 87 TCC0_MC_1 */
|
||||
(void*) TCC0_3_Handler, /* 88 TCC0_MC_2 */
|
||||
(void*) TCC0_4_Handler, /* 89 TCC0_MC_3 */
|
||||
(void*) TCC0_5_Handler, /* 90 TCC0_MC_4 */
|
||||
(void*) TCC0_6_Handler, /* 91 TCC0_MC_5 */
|
||||
(void*) TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
|
||||
(void*) TCC1_1_Handler, /* 93 TCC1_MC_0 */
|
||||
(void*) TCC1_2_Handler, /* 94 TCC1_MC_1 */
|
||||
(void*) TCC1_3_Handler, /* 95 TCC1_MC_2 */
|
||||
(void*) TCC1_4_Handler, /* 96 TCC1_MC_3 */
|
||||
(void*) TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
|
||||
(void*) TCC2_1_Handler, /* 98 TCC2_MC_0 */
|
||||
(void*) TCC2_2_Handler, /* 99 TCC2_MC_1 */
|
||||
(void*) TCC2_3_Handler, /* 100 TCC2_MC_2 */
|
||||
#ifdef ID_TCC3
|
||||
(void*) TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
|
||||
(void*) TCC3_1_Handler, /* 102 TCC3_MC_0 */
|
||||
(void*) TCC3_2_Handler, /* 103 TCC3_MC_1 */
|
||||
#else
|
||||
(void*) (0UL), /* 101 Reserved */
|
||||
(void*) (0UL), /* 102 Reserved */
|
||||
(void*) (0UL), /* 103 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TCC4
|
||||
(void*) TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
|
||||
(void*) TCC4_1_Handler, /* 105 TCC4_MC_0 */
|
||||
(void*) TCC4_2_Handler, /* 106 TCC4_MC_1 */
|
||||
#else
|
||||
(void*) (0UL), /* 104 Reserved */
|
||||
(void*) (0UL), /* 105 Reserved */
|
||||
(void*) (0UL), /* 106 Reserved */
|
||||
#endif
|
||||
(void*) TC0_Handler, /* 107 Basic Timer Counter 0 */
|
||||
(void*) TC1_Handler, /* 108 Basic Timer Counter 1 */
|
||||
(void*) TC2_Handler, /* 109 Basic Timer Counter 2 */
|
||||
(void*) TC3_Handler, /* 110 Basic Timer Counter 3 */
|
||||
#ifdef ID_TC4
|
||||
(void*) TC4_Handler, /* 111 Basic Timer Counter 4 */
|
||||
#else
|
||||
(void*) (0UL), /* 111 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC5
|
||||
(void*) TC5_Handler, /* 112 Basic Timer Counter 5 */
|
||||
#else
|
||||
(void*) (0UL), /* 112 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC6
|
||||
(void*) TC6_Handler, /* 113 Basic Timer Counter 6 */
|
||||
#else
|
||||
(void*) (0UL), /* 113 Reserved */
|
||||
#endif
|
||||
#ifdef ID_TC7
|
||||
(void*) TC7_Handler, /* 114 Basic Timer Counter 7 */
|
||||
#else
|
||||
(void*) (0UL), /* 114 Reserved */
|
||||
#endif
|
||||
(void*) PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
|
||||
(void*) PDEC_1_Handler, /* 116 PDEC_MC_0 */
|
||||
(void*) PDEC_2_Handler, /* 117 PDEC_MC_1 */
|
||||
(void*) ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */
|
||||
(void*) ADC0_1_Handler, /* 119 ADC0_RESRDY */
|
||||
(void*) ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */
|
||||
(void*) ADC1_1_Handler, /* 121 ADC1_RESRDY */
|
||||
(void*) AC_Handler, /* 122 Analog Comparators */
|
||||
(void*) DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
|
||||
(void*) DAC_1_Handler, /* 124 DAC_EMPTY_0 */
|
||||
(void*) DAC_2_Handler, /* 125 DAC_EMPTY_1 */
|
||||
(void*) DAC_3_Handler, /* 126 DAC_RESRDY_0 */
|
||||
(void*) DAC_4_Handler, /* 127 DAC_RESRDY_1 */
|
||||
#ifdef ID_I2S
|
||||
(void*) I2S_Handler, /* 128 Inter-IC Sound Interface */
|
||||
#else
|
||||
(void*) (0UL), /* 128 Reserved */
|
||||
#endif
|
||||
(void*) PCC_Handler, /* 129 Parallel Capture Controller */
|
||||
(void*) AES_Handler, /* 130 Advanced Encryption Standard */
|
||||
(void*) TRNG_Handler, /* 131 True Random Generator */
|
||||
#ifdef ID_ICM
|
||||
(void*) ICM_Handler, /* 132 Integrity Check Monitor */
|
||||
#else
|
||||
(void*) (0UL), /* 132 Reserved */
|
||||
#endif
|
||||
#ifdef ID_PUKCC
|
||||
(void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
|
||||
#else
|
||||
(void*) (0UL), /* 133 Reserved */
|
||||
#endif
|
||||
(void*) QSPI_Handler, /* 134 Quad SPI interface */
|
||||
#ifdef ID_SDHC0
|
||||
(void*) SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */
|
||||
#else
|
||||
(void*) (0UL), /* 135 Reserved */
|
||||
#endif
|
||||
#ifdef ID_SDHC1
|
||||
(void*) SDHC1_Handler /* 136 SD/MMC Host Controller 1 */
|
||||
#else
|
||||
(void*) (0UL) /* 136 Reserved */
|
||||
#endif
|
||||
};
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
int __low_level_init(void)
|
||||
{
|
||||
uint32_t *pSrc = __section_begin(".intvec");
|
||||
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
return 1; /* if return 0, the data sections will not be initialized */
|
||||
}
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
__iar_program_start();
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Default interrupt handler for unused IRQs.
|
||||
*/
|
||||
void Dummy_Handler(void)
|
||||
{
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
64
lib/same51/iar/system_same51.c
Normal file
64
lib/same51/iar/system_same51.c
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup.
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same51.h"
|
||||
|
||||
/**
|
||||
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
|
||||
* the source for the main clock at chip startup.
|
||||
*/
|
||||
#define __SYSTEM_CLOCK (48000000)
|
||||
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
// Keep the default device state after reset
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
// Not implemented
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
64
lib/same51/include/component-version.h
Normal file
64
lib/same51/include/component-version.h
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component version header file
|
||||
*
|
||||
* Copyright (c) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _COMPONENT_VERSION_H_INCLUDED
|
||||
#define _COMPONENT_VERSION_H_INCLUDED
|
||||
|
||||
#define COMPONENT_VERSION_MAJOR 1
|
||||
#define COMPONENT_VERSION_MINOR 1
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION define is composed of the major and the minor version number.
|
||||
//
|
||||
// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
|
||||
// The rest of the COMPONENT_VERSION is the major version.
|
||||
//
|
||||
#define COMPONENT_VERSION 10001
|
||||
|
||||
//
|
||||
// The build number does not refer to the component, but to the build number
|
||||
// of the device pack that provides the component.
|
||||
//
|
||||
#define BUILD_NUMBER 139
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
|
||||
//
|
||||
#define COMPONENT_VERSION_STRING "1.1"
|
||||
|
||||
//
|
||||
// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
|
||||
//
|
||||
// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
|
||||
//
|
||||
// "%Y-%m-%d %H:%M:%S"
|
||||
//
|
||||
//
|
||||
#define COMPONENT_DATE_STRING "2019-11-05 13:35:15"
|
||||
|
||||
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
|
||||
|
||||
598
lib/same51/include/component/ac.h
Normal file
598
lib/same51/include/component/ac.h
Normal file
|
|
@ -0,0 +1,598 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for AC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAME51_AC_COMPONENT_
|
||||
#define _SAME51_AC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR AC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAME51_AC Analog Comparators */
|
||||
/*@{*/
|
||||
|
||||
#define AC_U2501
|
||||
#define REV_AC 0x100
|
||||
|
||||
/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_CTRLA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
|
||||
#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */
|
||||
|
||||
#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
|
||||
#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos)
|
||||
#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
|
||||
#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos)
|
||||
#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */
|
||||
|
||||
/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
|
||||
uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_CTRLB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
|
||||
#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */
|
||||
|
||||
#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
|
||||
#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos)
|
||||
#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
|
||||
#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos)
|
||||
#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
|
||||
#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos)
|
||||
#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
|
||||
#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */
|
||||
|
||||
/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
|
||||
uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
|
||||
uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
|
||||
uint16_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */
|
||||
uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */
|
||||
uint16_t :2; /*!< bit: 10..11 Reserved */
|
||||
uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */
|
||||
uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */
|
||||
uint16_t :2; /*!< bit: 14..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
|
||||
uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
|
||||
uint16_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */
|
||||
uint16_t :2; /*!< bit: 10..11 Reserved */
|
||||
uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */
|
||||
uint16_t :2; /*!< bit: 14..15 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} AC_EVCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
|
||||
#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */
|
||||
|
||||
#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
|
||||
#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos)
|
||||
#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
|
||||
#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos)
|
||||
#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
|
||||
#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos)
|
||||
#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
|
||||
#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
|
||||
#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos)
|
||||
#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
|
||||
#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos)
|
||||
#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
|
||||
#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */
|
||||
#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos)
|
||||
#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */
|
||||
#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos)
|
||||
#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */
|
||||
#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos)
|
||||
#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
|
||||
#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */
|
||||
#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos)
|
||||
#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */
|
||||
#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos)
|
||||
#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */
|
||||
#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos)
|
||||
#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos))
|
||||
#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
|
||||
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
|
||||
uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
|
||||
uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
|
||||
#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos)
|
||||
#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
|
||||
#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos)
|
||||
#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
|
||||
#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos)
|
||||
#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
|
||||
#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
|
||||
#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos)
|
||||
#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
|
||||
#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos)
|
||||
#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
|
||||
#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
|
||||
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
|
||||
uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
|
||||
uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
|
||||
#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
|
||||
#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos)
|
||||
#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
|
||||
#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos)
|
||||
#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
|
||||
#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos)
|
||||
#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
|
||||
#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
|
||||
#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos)
|
||||
#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
|
||||
#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos)
|
||||
#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
|
||||
#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
|
||||
__I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
|
||||
__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
__I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
|
||||
__I uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
__I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
|
||||
__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
__I uint8_t WIN:1; /*!< bit: 4 Window x */
|
||||
__I uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
|
||||
#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
||||
|
||||
#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
|
||||
#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos)
|
||||
#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
|
||||
#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos)
|
||||
#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
|
||||
#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos)
|
||||
#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
|
||||
#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
|
||||
#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos)
|
||||
#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
|
||||
#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos)
|
||||
#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
|
||||
#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
|
||||
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
|
||||
uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_STATUSA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */
|
||||
#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */
|
||||
|
||||
#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
|
||||
#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos)
|
||||
#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
|
||||
#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos)
|
||||
#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
|
||||
#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos)
|
||||
#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
|
||||
#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
|
||||
#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos)
|
||||
#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
|
||||
#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */
|
||||
#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */
|
||||
#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */
|
||||
#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
|
||||
#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
|
||||
#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
|
||||
#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */
|
||||
|
||||
/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
|
||||
uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_STATUSB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */
|
||||
#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */
|
||||
|
||||
#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
|
||||
#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos)
|
||||
#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
|
||||
#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos)
|
||||
#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
|
||||
#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos)
|
||||
#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
|
||||
#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */
|
||||
|
||||
/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_DBGCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */
|
||||
#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */
|
||||
|
||||
#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */
|
||||
#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos)
|
||||
#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */
|
||||
|
||||
/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
|
||||
uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_WINCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */
|
||||
#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */
|
||||
|
||||
#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
|
||||
#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos)
|
||||
#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
|
||||
#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos)
|
||||
#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
|
||||
#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */
|
||||
#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
|
||||
#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */
|
||||
#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
|
||||
#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
|
||||
#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
|
||||
#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
|
||||
#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
|
||||
#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */
|
||||
|
||||
/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_SCALER_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */
|
||||
#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */
|
||||
|
||||
#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
|
||||
#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos)
|
||||
#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
|
||||
#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */
|
||||
|
||||
/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :1; /*!< bit: 0 Reserved */
|
||||
uint32_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */
|
||||
uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */
|
||||
uint32_t :1; /*!< bit: 5 Reserved */
|
||||
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
|
||||
uint32_t :1; /*!< bit: 7 Reserved */
|
||||
uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
|
||||
uint32_t :1; /*!< bit: 11 Reserved */
|
||||
uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */
|
||||
uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
|
||||
uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */
|
||||
uint32_t :1; /*!< bit: 18 Reserved */
|
||||
uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */
|
||||
uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */
|
||||
uint32_t :2; /*!< bit: 22..23 Reserved */
|
||||
uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
|
||||
uint32_t :1; /*!< bit: 27 Reserved */
|
||||
uint32_t OUT:2; /*!< bit: 28..29 Output */
|
||||
uint32_t :2; /*!< bit: 30..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AC_COMPCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
|
||||
#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
|
||||
|
||||
#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */
|
||||
#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos)
|
||||
#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
|
||||
#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos)
|
||||
#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */
|
||||
#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos)
|
||||
#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
|
||||
#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
|
||||
#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
|
||||
#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
|
||||
#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
|
||||
#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
|
||||
#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
|
||||
#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
|
||||
#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
|
||||
#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */
|
||||
#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
|
||||
#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
|
||||
#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
|
||||
#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
|
||||
#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
|
||||
#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
|
||||
#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */
|
||||
#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */
|
||||
#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
|
||||
#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */
|
||||
#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
|
||||
#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
|
||||
#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
|
||||
#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
|
||||
#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
|
||||
#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
|
||||
#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */
|
||||
#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos)
|
||||
#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
|
||||
#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos)
|
||||
#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */
|
||||
#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos)
|
||||
#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
|
||||
#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */
|
||||
#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
|
||||
#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
|
||||
#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos)
|
||||
#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */
|
||||
#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos)
|
||||
#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos))
|
||||
#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */
|
||||
#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */
|
||||
#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */
|
||||
#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos)
|
||||
#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos)
|
||||
#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos)
|
||||
#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
|
||||
#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos)
|
||||
#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
|
||||
#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */
|
||||
#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
|
||||
#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
|
||||
#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
|
||||
#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
|
||||
#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
|
||||
#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */
|
||||
#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos)
|
||||
#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
|
||||
#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
|
||||
#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
|
||||
#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
|
||||
#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
|
||||
#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
|
||||
#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
|
||||
#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */
|
||||
|
||||
/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
|
||||
uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
|
||||
uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */
|
||||
uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */
|
||||
uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */
|
||||
uint32_t :27; /*!< bit: 5..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t :3; /*!< bit: 0.. 2 Reserved */
|
||||
uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */
|
||||
uint32_t :27; /*!< bit: 5..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AC_SYNCBUSY_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */
|
||||
#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */
|
||||
|
||||
#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */
|
||||
#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos)
|
||||
#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */
|
||||
#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos)
|
||||
#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */
|
||||
#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos)
|
||||
#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */
|
||||
#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos)
|
||||
#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */
|
||||
#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos)
|
||||
#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */
|
||||
#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos)
|
||||
#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos))
|
||||
#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */
|
||||
|
||||
/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */
|
||||
uint16_t :14; /*!< bit: 2..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} AC_CALIB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */
|
||||
#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */
|
||||
|
||||
#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */
|
||||
#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos)
|
||||
#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos))
|
||||
#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */
|
||||
|
||||
/** \brief AC hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
|
||||
__O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
|
||||
__IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
|
||||
__IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
|
||||
__IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
|
||||
__IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
|
||||
__I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */
|
||||
__I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */
|
||||
__IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */
|
||||
__IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */
|
||||
RoReg8 Reserved1[0x1];
|
||||
__IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */
|
||||
RoReg8 Reserved2[0x2];
|
||||
__IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
|
||||
RoReg8 Reserved3[0x8];
|
||||
__I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */
|
||||
__IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */
|
||||
} Ac;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAME51_AC_COMPONENT_ */
|
||||
871
lib/same51/include/component/adc.h
Normal file
871
lib/same51/include/component/adc.h
Normal file
|
|
@ -0,0 +1,871 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for ADC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAME51_ADC_COMPONENT_
|
||||
#define _SAME51_ADC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR ADC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAME51_ADC Analog Digital Converter */
|
||||
/*@{*/
|
||||
|
||||
#define ADC_U2500
|
||||
#define REV_ADC 0x100
|
||||
|
||||
/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint16_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint16_t :1; /*!< bit: 2 Reserved */
|
||||
uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */
|
||||
uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */
|
||||
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
|
||||
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
|
||||
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
|
||||
uint16_t :4; /*!< bit: 11..14 Reserved */
|
||||
uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_CTRLA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
|
||||
#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */
|
||||
|
||||
#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
|
||||
#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos)
|
||||
#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
|
||||
#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos)
|
||||
#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */
|
||||
#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos)
|
||||
#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos))
|
||||
#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */
|
||||
#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
|
||||
#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos)
|
||||
#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos)
|
||||
#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */
|
||||
#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos)
|
||||
#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */
|
||||
#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos)
|
||||
#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */
|
||||
#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos)
|
||||
#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */
|
||||
#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos)
|
||||
#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos))
|
||||
#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */
|
||||
#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */
|
||||
#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */
|
||||
#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */
|
||||
#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */
|
||||
#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */
|
||||
#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */
|
||||
#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */
|
||||
#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos)
|
||||
#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos)
|
||||
#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos)
|
||||
#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos)
|
||||
#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos)
|
||||
#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos)
|
||||
#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos)
|
||||
#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos)
|
||||
#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */
|
||||
#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos)
|
||||
#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */
|
||||
|
||||
/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */
|
||||
uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */
|
||||
uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */
|
||||
uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */
|
||||
uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
|
||||
uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_EVCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */
|
||||
#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */
|
||||
|
||||
#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */
|
||||
#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos)
|
||||
#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */
|
||||
#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos)
|
||||
#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */
|
||||
#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos)
|
||||
#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */
|
||||
#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos)
|
||||
#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
|
||||
#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos)
|
||||
#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
|
||||
#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos)
|
||||
#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_DBGCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */
|
||||
#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
|
||||
|
||||
#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
|
||||
#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos)
|
||||
#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
|
||||
uint16_t :2; /*!< bit: 5.. 6 Reserved */
|
||||
uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */
|
||||
uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
|
||||
uint16_t :2; /*!< bit: 13..14 Reserved */
|
||||
uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_INPUTCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */
|
||||
#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
|
||||
|
||||
#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
|
||||
#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
|
||||
#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */
|
||||
#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
|
||||
#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
|
||||
#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
|
||||
#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */
|
||||
#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
|
||||
#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */
|
||||
#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos)
|
||||
#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */
|
||||
uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */
|
||||
uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */
|
||||
uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */
|
||||
uint16_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */
|
||||
uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */
|
||||
uint16_t :4; /*!< bit: 12..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_CTRLB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */
|
||||
#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */
|
||||
|
||||
#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
|
||||
#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos)
|
||||
#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */
|
||||
#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos)
|
||||
#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */
|
||||
#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos)
|
||||
#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
|
||||
#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos)
|
||||
#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
|
||||
#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */
|
||||
#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */
|
||||
#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */
|
||||
#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */
|
||||
#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
|
||||
#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
|
||||
#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
|
||||
#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
|
||||
#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */
|
||||
#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos)
|
||||
#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos))
|
||||
#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */
|
||||
#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */
|
||||
#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */
|
||||
#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */
|
||||
#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */
|
||||
#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos)
|
||||
#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos)
|
||||
#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos)
|
||||
#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos)
|
||||
#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos)
|
||||
#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */
|
||||
#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos)
|
||||
#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */
|
||||
|
||||
/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
|
||||
uint8_t :3; /*!< bit: 4.. 6 Reserved */
|
||||
uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_REFCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */
|
||||
#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */
|
||||
|
||||
#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
|
||||
#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
|
||||
#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */
|
||||
#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */
|
||||
#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */
|
||||
#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */
|
||||
#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */
|
||||
#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */
|
||||
#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
|
||||
#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos)
|
||||
#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
|
||||
uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
|
||||
uint8_t :1; /*!< bit: 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_AVGCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */
|
||||
#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */
|
||||
|
||||
#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
|
||||
#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
|
||||
#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos)
|
||||
#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
|
||||
#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
|
||||
uint8_t :1; /*!< bit: 6 Reserved */
|
||||
uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_SAMPCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */
|
||||
#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */
|
||||
|
||||
#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
|
||||
#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)
|
||||
#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
|
||||
#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */
|
||||
#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos)
|
||||
#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_WINLT_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
|
||||
#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
|
||||
|
||||
#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
|
||||
#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos)
|
||||
#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
|
||||
#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */
|
||||
|
||||
/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_WINUT_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
|
||||
#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
|
||||
|
||||
#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
|
||||
#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos)
|
||||
#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
|
||||
#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */
|
||||
|
||||
/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
|
||||
uint16_t :4; /*!< bit: 12..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_GAINCORR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */
|
||||
#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
|
||||
|
||||
#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
|
||||
#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)
|
||||
#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
|
||||
#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */
|
||||
|
||||
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
|
||||
uint16_t :4; /*!< bit: 12..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_OFFSETCORR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
|
||||
#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
|
||||
|
||||
#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
|
||||
#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)
|
||||
#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
|
||||
#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */
|
||||
|
||||
/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
|
||||
uint8_t START:1; /*!< bit: 1 Start ADC Conversion */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_SWTRIG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */
|
||||
#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
|
||||
|
||||
#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
|
||||
#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos)
|
||||
#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */
|
||||
#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos)
|
||||
#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */
|
||||
|
||||
/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */
|
||||
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */
|
||||
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */
|
||||
#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos)
|
||||
#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */
|
||||
#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos)
|
||||
#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */
|
||||
#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos)
|
||||
#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
|
||||
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
|
||||
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
|
||||
#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
|
||||
#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos)
|
||||
#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
|
||||
#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos)
|
||||
#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
|
||||
#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos)
|
||||
#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */
|
||||
__I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */
|
||||
__I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */
|
||||
__I uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
|
||||
#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
||||
|
||||
#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */
|
||||
#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos)
|
||||
#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */
|
||||
#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos)
|
||||
#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */
|
||||
#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos)
|
||||
#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */
|
||||
uint8_t :1; /*!< bit: 1 Reserved */
|
||||
uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_STATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */
|
||||
#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */
|
||||
|
||||
#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */
|
||||
#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos)
|
||||
#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */
|
||||
#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos)
|
||||
#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos))
|
||||
#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */
|
||||
|
||||
/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */
|
||||
uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */
|
||||
uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */
|
||||
uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */
|
||||
uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */
|
||||
uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */
|
||||
uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */
|
||||
uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */
|
||||
uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */
|
||||
uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */
|
||||
uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */
|
||||
uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */
|
||||
uint32_t :20; /*!< bit: 12..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} ADC_SYNCBUSY_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */
|
||||
#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */
|
||||
|
||||
#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */
|
||||
#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos)
|
||||
#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */
|
||||
#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos)
|
||||
#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */
|
||||
#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos)
|
||||
#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */
|
||||
#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos)
|
||||
#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */
|
||||
#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos)
|
||||
#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */
|
||||
#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos)
|
||||
#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */
|
||||
#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos)
|
||||
#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */
|
||||
#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos)
|
||||
#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */
|
||||
#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos)
|
||||
#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */
|
||||
#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos)
|
||||
#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */
|
||||
#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos)
|
||||
#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */
|
||||
#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos)
|
||||
#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */
|
||||
|
||||
/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} ADC_DSEQDATA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */
|
||||
#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */
|
||||
|
||||
#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */
|
||||
#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos)
|
||||
#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos))
|
||||
#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */
|
||||
|
||||
/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */
|
||||
uint32_t CTRLB:1; /*!< bit: 1 Control B */
|
||||
uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */
|
||||
uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */
|
||||
uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */
|
||||
uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */
|
||||
uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */
|
||||
uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */
|
||||
uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */
|
||||
uint32_t :22; /*!< bit: 9..30 Reserved */
|
||||
uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} ADC_DSEQCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */
|
||||
#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */
|
||||
|
||||
#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */
|
||||
#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos)
|
||||
#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */
|
||||
#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos)
|
||||
#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */
|
||||
#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos)
|
||||
#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */
|
||||
#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos)
|
||||
#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */
|
||||
#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos)
|
||||
#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */
|
||||
#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos)
|
||||
#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */
|
||||
#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos)
|
||||
#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */
|
||||
#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos)
|
||||
#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */
|
||||
#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos)
|
||||
#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */
|
||||
#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos)
|
||||
#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */
|
||||
uint32_t CTRLB:1; /*!< bit: 1 Control B */
|
||||
uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */
|
||||
uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */
|
||||
uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */
|
||||
uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */
|
||||
uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */
|
||||
uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */
|
||||
uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */
|
||||
uint32_t :22; /*!< bit: 9..30 Reserved */
|
||||
uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} ADC_DSEQSTAT_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */
|
||||
#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */
|
||||
|
||||
#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */
|
||||
#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos)
|
||||
#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */
|
||||
#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos)
|
||||
#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */
|
||||
#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos)
|
||||
#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */
|
||||
#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos)
|
||||
#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */
|
||||
#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos)
|
||||
#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */
|
||||
#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos)
|
||||
#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */
|
||||
#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos)
|
||||
#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */
|
||||
#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos)
|
||||
#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */
|
||||
#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos)
|
||||
#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */
|
||||
#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos)
|
||||
#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */
|
||||
|
||||
/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_RESULT_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */
|
||||
#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */
|
||||
|
||||
#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
|
||||
#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos)
|
||||
#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
|
||||
#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */
|
||||
|
||||
/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_RESS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */
|
||||
#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */
|
||||
|
||||
#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */
|
||||
#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos)
|
||||
#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos))
|
||||
#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */
|
||||
|
||||
/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */
|
||||
uint16_t :1; /*!< bit: 3 Reserved */
|
||||
uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */
|
||||
uint16_t :1; /*!< bit: 7 Reserved */
|
||||
uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */
|
||||
uint16_t :5; /*!< bit: 11..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} ADC_CALIB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */
|
||||
#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */
|
||||
|
||||
#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */
|
||||
#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos)
|
||||
#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))
|
||||
#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */
|
||||
#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos)
|
||||
#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos))
|
||||
#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */
|
||||
#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos)
|
||||
#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))
|
||||
#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */
|
||||
|
||||
/** \brief ADC hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
|
||||
__IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */
|
||||
__IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */
|
||||
__IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */
|
||||
__IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */
|
||||
__IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */
|
||||
RoReg8 Reserved1[0x1];
|
||||
__IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */
|
||||
__IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */
|
||||
__IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */
|
||||
__IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */
|
||||
__IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */
|
||||
__IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */
|
||||
__IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */
|
||||
RoReg8 Reserved2[0x17];
|
||||
__IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */
|
||||
__IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */
|
||||
__IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */
|
||||
__I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */
|
||||
__I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */
|
||||
__O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */
|
||||
__IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */
|
||||
__I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */
|
||||
__I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */
|
||||
RoReg8 Reserved3[0x2];
|
||||
__I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */
|
||||
RoReg8 Reserved4[0x2];
|
||||
__IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */
|
||||
} Adc;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAME51_ADC_COMPONENT_ */
|
||||
375
lib/same51/include/component/aes.h
Normal file
375
lib/same51/include/component/aes.h
Normal file
|
|
@ -0,0 +1,375 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for AES
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAME51_AES_COMPONENT_
|
||||
#define _SAME51_AES_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR AES */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAME51_AES Advanced Encryption Standard */
|
||||
/*@{*/
|
||||
|
||||
#define AES_U2238
|
||||
#define REV_AES 0x220
|
||||
|
||||
/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint32_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */
|
||||
uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */
|
||||
uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */
|
||||
uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */
|
||||
uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */
|
||||
uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */
|
||||
uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */
|
||||
uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */
|
||||
uint32_t :1; /*!< bit: 15 Reserved */
|
||||
uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */
|
||||
uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_CTRLA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */
|
||||
#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */
|
||||
|
||||
#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */
|
||||
#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos)
|
||||
#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */
|
||||
#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
|
||||
#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */
|
||||
#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
|
||||
#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */
|
||||
#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */
|
||||
#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */
|
||||
#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */
|
||||
#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */
|
||||
#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */
|
||||
#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */
|
||||
#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */
|
||||
#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
|
||||
#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */
|
||||
#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
|
||||
#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
|
||||
#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */
|
||||
#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */
|
||||
#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */
|
||||
#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos)
|
||||
#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos)
|
||||
#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos)
|
||||
#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */
|
||||
#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
|
||||
#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */
|
||||
#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */
|
||||
#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos)
|
||||
#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos)
|
||||
#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */
|
||||
#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
|
||||
#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */
|
||||
#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */
|
||||
#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)
|
||||
#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos)
|
||||
#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */
|
||||
#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos)
|
||||
#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
|
||||
#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */
|
||||
#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos)
|
||||
#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos)
|
||||
#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */
|
||||
#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
|
||||
#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
|
||||
#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */
|
||||
#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos)
|
||||
#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos)
|
||||
#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */
|
||||
#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
|
||||
#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
|
||||
#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
|
||||
#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos)
|
||||
#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos)
|
||||
#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */
|
||||
#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
|
||||
#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
|
||||
#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */
|
||||
|
||||
/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */
|
||||
uint8_t NEWMSG:1; /*!< bit: 1 New message */
|
||||
uint8_t EOM:1; /*!< bit: 2 End of message */
|
||||
uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_CTRLB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */
|
||||
#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */
|
||||
|
||||
#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */
|
||||
#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos)
|
||||
#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */
|
||||
#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
|
||||
#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */
|
||||
#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos)
|
||||
#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */
|
||||
#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
|
||||
#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */
|
||||
|
||||
/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
|
||||
uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */
|
||||
#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
|
||||
#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */
|
||||
#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
|
||||
#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
|
||||
uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */
|
||||
#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */
|
||||
#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
|
||||
#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */
|
||||
#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
|
||||
#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */
|
||||
|
||||
/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */
|
||||
__I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */
|
||||
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */
|
||||
#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */
|
||||
|
||||
#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */
|
||||
#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
|
||||
#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */
|
||||
#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
|
||||
#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_DATABUFPTR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */
|
||||
#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */
|
||||
|
||||
#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */
|
||||
#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
|
||||
#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
|
||||
#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */
|
||||
|
||||
/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_DBGCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */
|
||||
#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */
|
||||
|
||||
#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */
|
||||
#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
|
||||
#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */
|
||||
|
||||
/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_KEYWORD_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */
|
||||
#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */
|
||||
#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */
|
||||
|
||||
/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_INDATA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */
|
||||
#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */
|
||||
#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */
|
||||
|
||||
/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_INTVECTV_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */
|
||||
#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */
|
||||
#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */
|
||||
|
||||
/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_HASHKEY_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */
|
||||
#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */
|
||||
#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */
|
||||
|
||||
/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_GHASH_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */
|
||||
#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */
|
||||
#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */
|
||||
|
||||
/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_CIPLEN_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */
|
||||
#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */
|
||||
#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */
|
||||
|
||||
/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_RANDSEED_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */
|
||||
#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */
|
||||
#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */
|
||||
|
||||
/** \brief AES hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
|
||||
__IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */
|
||||
__IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */
|
||||
__IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */
|
||||
__IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */
|
||||
__IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */
|
||||
__IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */
|
||||
RoReg8 Reserved1[0x2];
|
||||
__O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */
|
||||
RoReg8 Reserved2[0xC];
|
||||
__IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */
|
||||
__O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
|
||||
RoReg8 Reserved3[0x10];
|
||||
__IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */
|
||||
__IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
|
||||
RoReg8 Reserved4[0x4];
|
||||
__IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
|
||||
__IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */
|
||||
} Aes;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAME51_AES_COMPONENT_ */
|
||||
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Reference in a new issue