almost no flash left :/

.clang-format

@@ -2,4 +2,3 @@ BasedOnStyle: LLVM
 IndentWidth: 4
 UseTab: Never
 ColumnLimit: 100
-SortIncludes: false

.gitignore

@@ -4,7 +4,3 @@ uf2-bootloader.elf
 tmp
 *.sw?
 Makefile.user
-node_modules
-scripts/clean-ifaces/*.plist
-.vscode/c_cpp_properties.json
-TAGS

.gitignore.bk

@@ -1,10 +0,0 @@
-build/
-.vs/
-uf2-bootloader.elf
-tmp
-*.sw?
-Makefile.user
-node_modules
-scripts/clean-ifaces/*.plist
-.vscode/c_cpp_properties.json
-TAGS

.gitmodules

@@ -1,3 +0,0 @@
-[submodule "lib/uf2"]
-	path = lib/uf2
-	url = https://github.com/Microsoft/uf2.git

.travis.yml

@@ -1,28 +0,0 @@
-language: node_js
-sudo: false
-node_js:
-  - "5.7.0"
-notifications:
-  email:
-    - yelm-eng@microsoft.com
-addons:
-  apt:
-    packages:
-      - libc6-i386
-
-node_js:
-  - "6"
-
-cache:
-  directories:
-    - $HOME/gcc-arm-none-eabi-9-2019-q4-major
-
-install:
-  - export GCC_DIR=$HOME/gcc-arm-none-eabi-9-2019-q4-major
-  - export GCC_ARCHIVE=$HOME/gcc-arm-none-eabi-9-2019-q4-major-x86_64-linux.tar.bz2
-  - export GCC_URL=https://developer.arm.com/-/media/Files/downloads/gnu-rm/9-2019q4/gcc-arm-none-eabi-9-2019-q4-major-x86_64-linux.tar.bz2
-  - if [ ! -e $GCC_DIR/bin/arm-none-eabi-g++ ]; then wget $GCC_URL -O $GCC_ARCHIVE; tar xfj $GCC_ARCHIVE -C $HOME; fi
-  - export PATH=$PATH:$GCC_DIR/bin
-
-script:
-    - make all-boards

.vscode/c_cpp_properties.json

@@ -0,0 +1,28 @@
+{
+    "configurations": [
+        {
+            "name": "Mac",
+            "includePath": ["/usr/include"],
+            "browse" : {
+                "limitSymbolsToIncludedHeaders" : true,
+                "databaseFilename" : ""
+            }
+        },
+        {
+            "name": "Linux",
+            "includePath": ["/usr/include"],
+            "browse" : {
+                "limitSymbolsToIncludedHeaders" : true,
+                "databaseFilename" : ""
+            }
+        },
+        {
+            "name": "Win32",
+            "includePath": ["c:/Program Files (x86)/Microsoft Visual Studio 14.0/VC/include"],
+            "browse" : {
+                "limitSymbolsToIncludedHeaders" : true,
+                "databaseFilename" : ""
+            }
+        }
+    ]
+}

.vscode/settings.json

@@ -1,3 +0,0 @@
-{
-    "files.associations": {}
-}

Makefile

@@ -1,19 +1,13 @@
 BOARD=zero
 -include Makefile.user
-include boards/$(BOARD)/board.mk
 CC=arm-none-eabi-gcc
-ifeq ($(CHIP_FAMILY), samd21)
-COMMON_FLAGS = -mthumb -mcpu=cortex-m0plus -Os -g -DSAMD21
-endif
-ifeq ($(CHIP_FAMILY), samd51)
-COMMON_FLAGS = -mthumb -mcpu=cortex-m4 -O2 -g -DSAMD51
-endif
+COMMON_FLAGS = -mthumb -mcpu=cortex-m0plus -Os -g
 WFLAGS = \
--Werror -Wall -Wstrict-prototypes \
+-Wall -Wstrict-prototypes \
 -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 \
 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 \
 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch \
--Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wno-undef \
+-Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef \
 -Wbad-function-cast -Wwrite-strings -Waggregate-return \
 -Wformat -Wmissing-format-attribute \
 -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs \
@@ -22,54 +16,27 @@ WFLAGS = \
 CFLAGS = $(COMMON_FLAGS) \
 -x c -c -pipe -nostdlib \
 --param max-inline-insns-single=500 \
--fno-strict-aliasing -fdata-sections -ffunction-sections \
--D__$(CHIP_VARIANT)__ \
+-fno-strict-aliasing -fdata-sections -ffunction-sections -mlong-calls \
 $(WFLAGS)
 
-UF2_VERSION_BASE = $(shell git describe --dirty --always --tags)
-
-ifeq ($(CHIP_FAMILY), samd21)
-LINKER_SCRIPT=scripts/samd21j18a.ld
-BOOTLOADER_SIZE=8192
-SELF_LINKER_SCRIPT=scripts/samd21j18a_self.ld
-endif
-
-ifeq ($(CHIP_FAMILY), samd51)
-LINKER_SCRIPT=scripts/samd51j19a.ld
-BOOTLOADER_SIZE=16384
-SELF_LINKER_SCRIPT=scripts/samd51j19a_self.ld
-endif
-
 LDFLAGS= $(COMMON_FLAGS) \
 -Wall -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--unresolved-symbols=report-all -Wl,--warn-common \
--Wl,--warn-section-align \
--save-temps -nostartfiles \
---specs=nano.specs --specs=nosys.specs
+-Wl,--warn-section-align -Wl,--warn-unresolved-symbols \
+-save-temps  \
+--specs=nano.specs --specs=nosys.specs 
 BUILD_PATH=build/$(BOARD)
-INCLUDES = -I. -I./inc -I./inc/preprocessor
-INCLUDES += -I./boards/$(BOARD) -Ilib/cmsis/CMSIS/Include -Ilib/usb_msc
-INCLUDES += -I$(BUILD_PATH)
-
-
-ifeq ($(CHIP_FAMILY), samd21)
-INCLUDES += -Ilib/samd21/samd21a/include/
-endif
-
-ifeq ($(CHIP_FAMILY), samd51)
-ifeq ($(findstring SAME54,$(CHIP_VARIANT)),SAME54)
-INCLUDES += -Ilib/same54/include/
-else
-INCLUDES += -Ilib/samd51/include/
-endif
-endif
+INCLUDES = -I./inc -I./inc/preprocessor
+INCLUDES += -I./asf/sam0/utils/cmsis/samd21/include -I./asf/thirdparty/CMSIS/Include -I./asf/sam0/utils/cmsis/samd21/source
+INCLUDES += -I./asf/common -I./asf/common/utils -I./asf/sam0/utils/header_files -I./asf/sam0/utils -I./asf/common/utils/interrupt
+INCLUDES += -I./asf/sam0/drivers/system/interrupt -I./asf/sam0/drivers/system/interrupt/system_interrupt_samd21
+INCLUDES += -I./boards/$(BOARD)
 
 COMMON_SRC = \
-	src/flash_$(CHIP_FAMILY).c \
-	src/init_$(CHIP_FAMILY).c \
-	src/startup_$(CHIP_FAMILY).c \
+        src/neopixel.c \
+	src/flash.c \
+	src/init.c \
+	src/startup_samd21.c \
 	src/usart_sam_ba.c \
-	src/screen.c \
-	src/images.c \
 	src/utils.c
 
 SOURCES = $(COMMON_SRC) \
@@ -87,59 +54,21 @@ SELF_SOURCES = $(COMMON_SRC) \
 OBJECTS = $(patsubst src/%.c,$(BUILD_PATH)/%.o,$(SOURCES))
 SELF_OBJECTS = $(patsubst src/%.c,$(BUILD_PATH)/%.o,$(SELF_SOURCES)) $(BUILD_PATH)/selfdata.o
 
-NAME=bootloader-$(BOARD)-$(UF2_VERSION_BASE)
+NAME=uf2-bootloader
 EXECUTABLE=$(BUILD_PATH)/$(NAME).bin
-SELF_EXECUTABLE=$(BUILD_PATH)/update-$(NAME).uf2
-SELF_EXECUTABLE_INO=$(BUILD_PATH)/update-$(NAME).ino
+SELF_EXECUTABLE=$(BUILD_PATH)/self-$(NAME).uf2
 
-SUBMODULES = lib/uf2/README.md
-
-all: $(SUBMODULES) dirs $(EXECUTABLE) $(SELF_EXECUTABLE)
+all: dirs $(EXECUTABLE) $(SELF_EXECUTABLE)
 
 r: run
 b: burn
 l: logs
 
 burn: all
-	node scripts/dbgtool.js fuses
 	node scripts/dbgtool.js $(BUILD_PATH)/$(NAME).bin
 
 run: burn wait logs
 
-# This currently only works on macOS with a BMP debugger attached.
-# It's meant to flash the bootloader in a loop.
-BMP = $(shell ls -1 /dev/cu.usbmodem* | head -1)
-BMP_ARGS = --nx -ex "set mem inaccessible-by-default off" -ex "set confirm off" -ex "target extended-remote $(BMP)" -ex "mon tpwr enable" -ex "mon swdp_scan" -ex "attach 1"
-GDB = arm-none-eabi-gdb
-
-bmp-flash: $(BUILD_PATH)/$(NAME).bin
-	@test "X$(BMP)" != "X"
-	$(GDB) $(BMP_ARGS) -ex "load" -ex "quit" $(BUILD_PATH)/$(NAME).elf | tee build/flash.log
-	@grep -q "Transfer rate" build/flash.log
-
-bmp-flashone:
-	while : ; do $(MAKE) bmp-flash && exit 0 ; sleep 1 ; done
-	afplay /System/Library/PrivateFrameworks/ScreenReader.framework/Versions/A/Resources/Sounds/Error.aiff
-
-bmp-loop:
-	while : ; do $(MAKE) bmp-flashone ; sleep 5 ; done
-
-bmp-gdb: $(BUILD_PATH)/$(NAME).bin
-	$(GDB) $(BMP_ARGS) $(BUILD_PATH)/$(NAME).elf
-
-$(BUILD_PATH)/flash.jlink: $(BUILD_PATH)/$(NAME).bin
-	echo " \n\
-r \n\
-h \n\
-loadbin \"$(BUILD_PATH)/$(NAME).bin\", 0x0 \n\
-verifybin \"$(BUILD_PATH)/$(NAME).bin\", 0x0 \n\
-r \n\
-qc \n\
-" > $(BUILD_PATH)/flash.jlink
-
-jlink-flash: $(BUILD_PATH)/$(NAME).bin $(BUILD_PATH)/flash.jlink
-	jlinkexe -if swd -device AT$(CHIP_VARIANT) -speed 4000 -CommanderScript $(BUILD_PATH)/flash.jlink
-
 wait:
 	sleep 5
 
@@ -147,40 +76,38 @@ logs:
 	node scripts/dbgtool.js $(BUILD_PATH)/$(NAME).map
 
 selflogs:
-	node scripts/dbgtool.js $(BUILD_PATH)/update-$(NAME).map
+	node scripts/dbgtool.js $(BUILD_PATH)/self-$(NAME).map
 
 dirs:
 	@echo "Building $(BOARD)"
 	-@mkdir -p $(BUILD_PATH)
 
-$(EXECUTABLE): $(OBJECTS)
+$(EXECUTABLE): $(OBJECTS) 
 	$(CC) -L$(BUILD_PATH) $(LDFLAGS) \
-		 -T$(LINKER_SCRIPT) \
+		 -T./asf/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld \
 		 -Wl,-Map,$(BUILD_PATH)/$(NAME).map -o $(BUILD_PATH)/$(NAME).elf $(OBJECTS)
 	arm-none-eabi-objcopy -O binary $(BUILD_PATH)/$(NAME).elf $@
 	@echo
-	-@arm-none-eabi-size $(BUILD_PATH)/$(NAME).elf | awk '{ s=$$1+$$2; print } END { print ""; print "Space left: " ($(BOOTLOADER_SIZE)-s) }'
+	-@arm-none-eabi-size $(BUILD_PATH)/$(NAME).elf | awk '{ s=$$1+$$2; print } END { print ""; print "Space left: " (8192-s) }'
 	@echo
 
-$(BUILD_PATH)/uf2_version.h: Makefile
-	echo "#define UF2_VERSION_BASE \"$(UF2_VERSION_BASE)\""> $@
 
 $(SELF_EXECUTABLE): $(SELF_OBJECTS)
 	$(CC) -L$(BUILD_PATH) $(LDFLAGS) \
-		 -T$(SELF_LINKER_SCRIPT) \
-		 -Wl,-Map,$(BUILD_PATH)/update-$(NAME).map -o $(BUILD_PATH)/update-$(NAME).elf $(SELF_OBJECTS)
-	arm-none-eabi-objcopy -O binary $(BUILD_PATH)/update-$(NAME).elf $(BUILD_PATH)/update-$(NAME).bin
-	python3 lib/uf2/utils/uf2conv.py -b $(BOOTLOADER_SIZE) -c -o $@ $(BUILD_PATH)/update-$(NAME).bin
+		 -T./scripts/samd21j18a_self.ld \
+		 -Wl,-Map,$(BUILD_PATH)/self-$(NAME).map -o $(BUILD_PATH)/self-$(NAME).elf $(SELF_OBJECTS)
+	arm-none-eabi-objcopy -O binary $(BUILD_PATH)/self-$(NAME).elf $(BUILD_PATH)/self-$(NAME).bin
+	node scripts/bin2uf2.js $(BUILD_PATH)/self-$(NAME).bin $@
 
-$(BUILD_PATH)/%.o: src/%.c $(wildcard inc/*.h boards/*/*.h) $(BUILD_PATH)/uf2_version.h
-	echo "$<"
-	$(CC) $(CFLAGS) $(BLD_EXTA_FLAGS) $(INCLUDES) $< -o $@
+$(BUILD_PATH)/%.o: src/%.c $(wildcard inc/*.h boards/*/*.h)
+	@echo "$<"
+	@$(CC) $(CFLAGS) $(BLD_EXTA_FLAGS) $(INCLUDES) $< -o $@
 
 $(BUILD_PATH)/%.o: $(BUILD_PATH)/%.c
-	$(CC) $(CFLAGS) $(BLD_EXTA_FLAGS) $(INCLUDES) $< -o $@
+	@$(CC) $(CFLAGS) $(BLD_EXTA_FLAGS) $(INCLUDES) $< -o $@
 
-$(BUILD_PATH)/selfdata.c: $(EXECUTABLE) scripts/gendata.py src/sketch.cpp
-	python3 scripts/gendata.py $(BOOTLOADER_SIZE) $(EXECUTABLE)
+$(BUILD_PATH)/selfdata.c: $(EXECUTABLE) scripts/gendata.js
+	node scripts/gendata.js $(BUILD_PATH) $(NAME).bin
 
 clean:
 	rm -rf build
@@ -188,41 +115,22 @@ clean:
 gdb:
 	arm-none-eabi-gdb $(BUILD_PATH)/$(NAME).elf
 
-tui:
-	arm-none-eabi-gdb -tui $(BUILD_PATH)/$(NAME).elf
-
-%.asmdump: %.o
-	arm-none-eabi-objdump -d $< > $@
-
-applet0: $(BUILD_PATH)/flash.asmdump
-	node scripts/genapplet.js $< flash_write
-
-applet1: $(BUILD_PATH)/utils.asmdump
-	node scripts/genapplet.js $< resetIntoApp
-
 drop-board: all
 	@echo "*** Copy files for $(BOARD)"
 	mkdir -p build/drop
 	rm -rf build/drop/$(BOARD)
 	mkdir -p build/drop/$(BOARD)
-	cp $(SELF_EXECUTABLE) build/drop/$(BOARD)/
-	cp $(EXECUTABLE) build/drop/$(BOARD)/
-# .ino works only for SAMD21 right now; suppress for SAMD51
-ifeq ($(CHIP_FAMILY),samd21)
-	cp $(SELF_EXECUTABLE_INO) build/drop/$(BOARD)/
-	cp boards/$(BOARD)/board_config.h build/drop/$(BOARD)/
-endif
+	cp $(SELF_EXECUTABLE) build/drop/$(BOARD)/update-bootloader.uf2
+	cp $(EXECUTABLE) build/drop/$(BOARD)/bootloader.bin
+	cp $(BUILD_PATH)/bootloader.ino build/drop/$(BOARD)/bootloader.ino
+	cp boards/$(BOARD)/board_config.h build/drop/$(BOARD)/board_config.h
 
 drop-pkg:
-	mv build/drop build/uf2-samd21-$(UF2_VERSION_BASE)
-	cp bin-README.md build/uf2-samd21-$(UF2_VERSION_BASE)/README.md
-	cd build; 7z a uf2-samd21-$(UF2_VERSION_BASE).zip uf2-samd21-$(UF2_VERSION_BASE)
-	rm -rf build/uf2-samd21-$(UF2_VERSION_BASE)
+	mv build/drop build/uf2-samd21-$(VERSION)
+	cd build; 7z a uf2-samd21-$(VERSION).zip uf2-samd21-$(VERSION)
+	rm -rf build/uf2-samd21-$(VERSION)
 
-all-boards:
-	for f in `cd boards; ls` ; do "$(MAKE)" BOARD=$$f drop-board || break -1; done
+drop:
+	for f in `cd boards; ls` ; do $(MAKE) BOARD=$$f drop-board ; done
+	$(MAKE) VERSION=`awk '/define UF2_VERSION_BASE/ { gsub(/"v?/, ""); print $$3 }' inc/uf2.h` drop-pkg
 
-drop: all-boards drop-pkg
-
-$(SUBMODULES):
-	git submodule update --init --recursive

README.md

@@ -4,11 +4,9 @@ This repository contains a bootloader, derived from Atmel's SAM-BA,
 which in addition to the USB CDC (serial) protocol, also supports
 the USB MSC (mass storage).
 
-[![Build Status](https://travis-ci.org/Microsoft/uf2-samd21.svg?branch=master)](https://travis-ci.org/Microsoft/uf2-samd21)
+## UF2 
 
-## UF2
-
-**UF2 (USB Flashing Format)** is a name of a file format, developed by Microsoft, that is particularly
+UF2 (USB Flashing Format) is a name of a file format, that is particularly 
 suitable for flashing devices over MSC devices. The file consists
 of 512 byte blocks, each of which is self-contained and independent
 of others.
@@ -22,12 +20,13 @@ Each 512 byte block consist of (see `uf2format.h` for details):
 Thus, it's really easy for the microcontroller to recognize a block of
 a UF2 file is written and immediately write it to flash.
 
+In `uf2conv.c` you can find a small converter from `.bin` to `.uf2`.
+
 * **UF2 specification repo:** https://github.com/Microsoft/uf2
-* [#DeskOfLadyada UF24U ! LIVE @adafruit #adafruit #programming](https://youtu.be/WxCuB6jxLs0)
 
 ## Features
 
-* USB CDC (Serial emulation) monitor mode compatible with Arduino
+* USB CDC (Serial emulation) monitor mode compatible with Arduino 
   (including XYZ commands) and BOSSA flashing tool
 * USB MSC interface for writing UF2 files
 * reading of the contests of the flash as an UF2 file via USB MSC
@@ -38,7 +37,7 @@ a UF2 file is written and immediately write it to flash.
 
 ## Board identification
 
-Configuration files for board `foo` are in `boards/foo/board_config.h` and `board.mk`. You can
+Configuration files for board `foo` is in `boards/foo/board_config.h`. You can
 build it with `make BOARD=foo`. You can also create `Makefile.user` file with `BOARD=foo`
 to change the default.
 
@@ -75,49 +74,24 @@ Thus, to update the bootloader, one can ship a user-space program,
 that contains the new version of the bootloader and copies it to the
 appropriate place in flash.
 
-Such a program is generated during build in files `update-bootloader*.uf2`.
-If you're already running UF2 bootloader, the easiest way to update
-it, is to just copy this file to the exposed MSD drive.
-
-The build also generates `update-bootloader*.ino` with an equivalent Arduino
-sketch. You can copy&paste it into Arduino IDE and upload it to the device.
+Such a program is generated during build in files `self-uf2-bootloader.bin`
+and `self-uf2-bootloader.uf2`.
 
 ## Fuses
 
-### SAMD21
-
-The SAMD21 supports a `BOOTPROT` fuse, which write-protects the flash area of
+The SAMD21 supports a BOOTPROT fuse, which write-protects the flash area of
 the bootloader. Changes to this fuse only take effect after device reset.
 
-OpenOCD exposes `at91samd bootloader` command to set this fuse. **This command is buggy.**
-It seems to reset both fuse words to `0xffffffff`, which prevents the device
-from operating correctly (it seems to reboot very frequently).
-In `scripts/fuses.tcl` there is an OpenOCD script
-which correctly sets the fuse. It's invoked by `dbgtool.js fuses`. It can be also
-used to reset the fuses to sane values - just look at the comment at the top.
+This fuse is currently not utilized by this bootloader. It needs to be investigated.
 
-The bootloader update programs (both the `.uf2` file and the Arduino sketch)
-clear the `BOOTPROT` (i.e., set it to `0x7`) before trying to flash anything.
-After flashing is done, they set `BOOTPROT` to 8 kilobyte bootloader size (i.e, `0x2`).
-
-### SAMD51
-
-The SAMD51s bootloader protection can be temporarily disabled through an NVM
-command rather than a full erase and write of the AUX page. The boot protection
-will be checked and set by the self updaters.
-
-So, if you've used self-updaters but want to load it directly, then you'll need
-to temporarily turn off the protection. In gdb the command is:
-
-`set ((Nvmctrl  *)0x41004000UL)->CTRLB.reg = (0xA5 << 8) | 0x1a`
 
 ## Build
 
 ### Requirements
 
 * `make` and an Unix environment
-* `node`.js in path (optional)
-* `arm-none-eabi-gcc` in the path (the one coming with Yotta will do just fine). You can get the latest version from ARM: https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads
+* `node`.js in path
+* `arm-none-eabi-gcc` in the path (the one coming with Yotta will do just fine)
 * `openocd` - you can use the one coming with Arduino (after your install the M0 board support)
 
 Atmel Studio is not supported.
@@ -132,7 +106,7 @@ Otherwise, you can use other SAMD21 board and an external `openocd` compatible
 debugger. IBDAP is cheap and seems to work just fine. Another option is to use
 Raspberry Pi and native bit-banging.
 
-`openocd` will flash 16k, meaning that on SAMD21 the beginning of user program (if any) will
+`openocd` will flash 16k, meaning the beginning of user program (if any) will
 be overwritten with `0xff`. This also means that after fresh flashing of bootloader
 no double-tap reset is necessary, as the bootloader will not try to start application
 at `0xffffffff`.
@@ -142,10 +116,10 @@ at `0xffffffff`.
 The default board is `zero`. You can build a different one using:
 
 ```
-make BOARD=metro_m0
+make BOARD=metro
 ```
 
-If you're working on different board, it's best to create `Makefile.local`
+If you're working on different board, it's best to create `Makefile.local` 
 with say `BOARD=metro` to change the default.
 The names `zero` and `metro` refer to subdirectories of `boards/`.
 
@@ -166,34 +140,31 @@ make r
 There is a number of configuration parameters at the top of `uf2.h` file.
 Adjust them to your liking.
 
-By default, you cannot enable all the features, as the bootloader would exceed
-the 8k(SAMD21)/16k(SAMD51) allocated to it by Arduino etc. It will assert on startup that it's not bigger
-than 8k(SAMD21)/16k(SAMD51). Also, the linker script will not allow it.
+By default, you cannot enable all the features, as the bootloader would exceed 
+the 8k allocated to it by Arduino etc. It will assert on startup that it's not bigger
+than 8k. Also, the linker script will not allow it.
 
 Three typical configurations are:
 
-* HID, WebUSB, MSC, plus flash reading via FAT; UART and CDC disabled;
+* HID, WebUSB, MSC, plus flash reading via FAT; UART and CDC disabled; 
   logging optional; **recommended**
-* USB CDC and MSC, plus flash reading via FAT; UART disabled;
+* USB CDC and MSC, plus flash reading via FAT; UART disabled; 
   logging optional; this may have Windows driver problems
-* USB CDC and MSC, no flash reading via FAT (or at least `index.htm` disabled); UART enabled;
-  logging disabled; no handover; no HID;
+* USB CDC and MSC, no flash reading via FAT; UART enabled; 
+  logging disabled; 
   only this one if you need the UART support in bootloader for whatever reason
 
 CDC and MSC together will work on Linux and Mac with no drivers.
-On Windows, if you have drivers installed for the USB ID chosen,
+On Windows, if you have drivers installed for the USB ID chosen, 
 then CDC might work and MSC will not work;
 otherwise, if you have no drivers, MSC will work, and CDC will work on Windows 10 only.
 Thus, it's best to set the USB ID to one for which there are no drivers.
 
-The bootloader sits at 0x00000000, and the application starts at 0x00002000 (SAMD21) or 0x00004000 (SAMD51).
+The bootloader sits at 0x00000000, and the application starts at 0x00002000.
 
-## Code of Conduct
-
-This project has adopted the [Microsoft Open Source Code of Conduct](https://opensource.microsoft.com/codeofconduct/). For more information see the [Code of Conduct FAQ](https://opensource.microsoft.com/codeofconduct/faq/) or contact [opencode@microsoft.com](mailto:opencode@microsoft.com) with any additional questions or comments.
 
 ## License
 
-See THIRD-PARTY-NOTICES.txt for the original SAM-BA bootloader license from Atmel.
+The original SAM-BA bootloader is licensed under BSD-like license from Atmel.
 
 The new code is licensed under MIT.

THIRD-PARTY-NOTICES.txt

@@ -1,161 +0,0 @@
-/*!----------------- UF2-SAMD21 ThirdPartyNotices -------------------------------------------------------
-
-
-
-UF2-SAMD21 uses third party material from the projects listed below.
-
-The original copyright notice and the license under which Microsoft
-
-received such third party material are set forth below. Microsoft
-
-reserves all other rights not expressly granted, whether by
-
-implication, estoppel or otherwise.
-
-
-
-In the event that we accidentally failed to list a required notice, please
-
-bring it to our attention. Post an issue or email us:
-
-
-
-           yelmteam@microsoft.com
-
-
-
----------------------------------------------
-
-Third Party Code Components
-
----------------------------------------------
-
------------------ SAM Software Package License -------------------
-
-Copyright (c) 2011-2014, Atmel Corporation
-
-All rights reserved.
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following condition is met:
-
-Redistributions of source code must retain the above copyright notice,
-this list of conditions and the disclaimer below.
-
-Atmel's name may not be used to endorse or promote products derived from
-this software without specific prior written permission.
-
-DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-
------------------ Atmel Software Framework (ASF)--------------------------------------
-
-Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
-
-\asf_license_start
-
-\page License
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-1. Redistributions of source code must retain the above copyright notice,
-   this list of conditions and the following disclaimer.
-
-2. Redistributions in binary form must reproduce the above copyright notice,
-   this list of conditions and the following disclaimer in the documentation
-   and/or other materials provided with the distribution.
-
-3. The name of Atmel may not be used to endorse or promote products derived
-   from this software without specific prior written permission.
-
-4. This software may only be redistributed and used in connection with an
-   Atmel microcontroller product.
-
-THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
-
-\asf_license_stop
- ----------------------------------------------------------------------------
-
------------------ Atmel Software Framework (ASF)--------------------------------------
-Copyright (c) 2016 Atmel Corporation. All rights reserved.
-
-\asf_license_start
-
-\page License
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-1. Redistributions of source code must retain the above copyright notice,
-   this list of conditions and the following disclaimer.
-
-2. Redistributions in binary form must reproduce the above copyright notice,
-   this list of conditions and the following disclaimer in the documentation
-   and/or other materials provided with the distribution.
-
-3. The name of Atmel may not be used to endorse or promote products derived
-   from this software without specific prior written permission.
-
-4. This software may only be redistributed and used in connection with an
-   Atmel microcontroller product.
-
-THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------
-
----------------------------ARM-------------------------------------------------
-
-Copyright (c) 2009 - 2014 ARM LIMITED
-
-All rights reserved.
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-- Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-- Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-- Neither the name of ARM nor the names of its contributors may be used
-    to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------

TODO.md

@@ -0,0 +1,24 @@
+## Current
+* [x] separate logs out
+* [x] no volume label shows under Windows
+* [x] extend magic with "UF2\n" string
+* [x] align data in block to 32 bytes (for hex viewer)
+* [x] show board serial number and name in info file
+* [x] organize board configs in directories
+* [x] if `!USE_CDC && !USE_UART` - don't compile monitor
+* [x] if `!USE_CDC` don't compile the CDC code (not only exclude descriptors)
+* [x] write user program for updating bootloader
+* [ ] document self-updater
+* [ ] write u2fconv in .js
+* [x] investigate some blinking; also RX/TX leds
+* [ ] add optional logic to self-updater to check if existing bootloader has the same board-id
+* [x] detect end of transmission by block numbers
+* [ ] add UF2 write support to PXT
+* [ ] add UF2 read support to PXT
+
+## Bigger
+* [ ] look into reset into bootloader from host to continue flashing
+* [ ] use BOOTPROT bits - requires device reset to set
+* [ ] investigate no-reset on the MSD device
+* [ ] investigate webusb
+

asf/common/boards/board.h

@@ -0,0 +1,445 @@
+/**
+ * \file
+ *
+ * \brief Standard board header file.
+ *
+ * This file includes the appropriate board header file according to the
+ * defined board (parameter BOARD).
+ *
+ * Copyright (c) 2009-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/**
+ * \defgroup group_common_boards Generic board support
+ *
+ * The generic board support module includes board-specific definitions
+ * and function prototypes, such as the board initialization function.
+ *
+ * \{
+ */
+
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*! \name Base Boards
+ */
+//! @{
+#define EVK1100                     1  //!< AT32UC3A EVK1100 board.
+#define EVK1101                     2  //!< AT32UC3B EVK1101 board.
+#define UC3C_EK                     3  //!< AT32UC3C UC3C-EK board.
+#define EVK1104                     4  //!< AT32UC3A3 EVK1104 board.
+#define EVK1105                     5  //!< AT32UC3A EVK1105 board.
+#define STK600_RCUC3L0              6  //!< STK600 RCUC3L0 board.
+#define UC3L_EK                     7  //!< AT32UC3L-EK board.
+#define XPLAIN                      8  //!< ATxmega128A1 Xplain board.
+#define STK600_RC064X              10  //!< ATxmega256A3 STK600 board.
+#define STK600_RC100X              11  //!< ATxmega128A1 STK600 board.
+#define UC3_A3_XPLAINED            13  //!< ATUC3A3 UC3-A3 Xplained board.
+#define UC3_L0_XPLAINED            15  //!< ATUC3L0 UC3-L0 Xplained board.
+#define STK600_RCUC3D              16  //!< STK600 RCUC3D board.
+#define STK600_RCUC3C0             17  //!< STK600 RCUC3C board.
+#define XMEGA_B1_XPLAINED          18  //!< ATxmega128B1 Xplained board.
+#define XMEGA_A1_XPLAINED          19  //!< ATxmega128A1 Xplain-A1 board.
+#define XMEGA_A1U_XPLAINED_PRO     20  //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
+#define STK600_RCUC3L4             21  //!< ATUCL4 STK600 board.
+#define UC3_L0_XPLAINED_BC         22  //!< ATUC3L0 UC3-L0 Xplained board controller board.
+#define MEGA1284P_XPLAINED_BC      23  //!< ATmega1284P-Xplained board controller board.
+#define STK600_RC044X              24  //!< STK600 with RC044X routing card board.
+#define STK600_RCUC3B0             25  //!< STK600 RCUC3B0 board.
+#define UC3_L0_QT600               26  //!< QT600 UC3L0 MCU board.
+#define XMEGA_A3BU_XPLAINED        27  //!< ATxmega256A3BU Xplained board.
+#define STK600_RC064X_LCDX         28  //!< XMEGAB3 STK600 RC064X LCDX board.
+#define STK600_RC100X_LCDX         29  //!< XMEGAB1 STK600 RC100X LCDX board.
+#define UC3B_BOARD_CONTROLLER      30  //!< AT32UC3B1 board controller for Atmel boards.
+#define RZ600                      31  //!< AT32UC3A RZ600 MCU board.
+#define SAM3S_EK                   32  //!< SAM3S-EK board.
+#define SAM3U_EK                   33  //!< SAM3U-EK board.
+#define SAM3X_EK                   34  //!< SAM3X-EK board.
+#define SAM3N_EK                   35  //!< SAM3N-EK board.
+#define SAM3S_EK2                  36  //!< SAM3S-EK2 board.
+#define SAM4S_EK                   37  //!< SAM4S-EK board.
+#define STK600_RCUC3A0             38  //!< STK600 RCUC3A0 board.
+#define STK600_MEGA                39  //!< STK600 MEGA board.
+#define MEGA_1284P_XPLAINED        40  //!< ATmega1284P Xplained board.
+#define SAM4S_XPLAINED             41  //!< SAM4S Xplained board.
+#define ATXMEGA128A1_QT600         42  //!< QT600 ATXMEGA128A1 MCU board.
+#define ARDUINO_DUE_X              43  //!< Arduino Due/X board.
+#define STK600_RCUC3L3             44  //!< ATUCL3 STK600 board.
+#define SAM4L_EK                   45  //!< SAM4L-EK board.
+#define STK600_MEGA_RF             46  //!< STK600 MEGA RF EVK board.
+#define XMEGA_C3_XPLAINED          47  //!< ATxmega384C3 Xplained board.
+#define STK600_RC032X              48  //!< STK600 with RC032X routing card board.
+#define SAM4S_EK2                  49  //!< SAM4S-EK2 board.
+#define XMEGA_E5_XPLAINED          50  //!< ATxmega32E5 Xplained board.
+#define SAM4E_EK                   51  //!< SAM4E-EK board.
+#define ATMEGA256RFR2_XPLAINED_PRO 52  //!< ATmega256RFR2 Xplained Pro board.
+#define SAM4S_XPLAINED_PRO         53  //!< SAM4S Xplained Pro board.
+#define SAM4L_XPLAINED_PRO         54  //!< SAM4L Xplained Pro board.
+#define ATMEGA256RFR2_ZIGBIT       55  //!< ATmega256RFR2 zigbit.
+#define XMEGA_RF233_ZIGBIT         56  //!< ATxmega256A3U with AT86RF233 Zigbit.
+#define XMEGA_RF212B_ZIGBIT        57  //!< ATxmega256A3U with AT86RF212B Zigbit.
+#define SAM4S_WPIR_RD              58  //!< SAM4S-WPIR-RD board.
+#define SAMD20_XPLAINED_PRO        59  //!< SAM D20 Xplained Pro board.
+#define SAM4L8_XPLAINED_PRO        60  //!< SAM4L8 Xplained Pro board.
+#define SAM4N_XPLAINED_PRO         61  //!< SAM4N Xplained Pro board.
+#define XMEGA_A3_REB_CBB           62  //!< XMEGA REB Controller Base board.
+#define ATMEGARFX_RCB              63  //!< RFR2 & RFA1 RCB.
+#define SAM4C_EK                   64  //!< SAM4C-EK board.
+#define RCB256RFR2_XPRO            65  //!< RFR2 RCB Xplained Pro board.
+#define SAMG53_XPLAINED_PRO        66  //!< SAMG53 Xplained Pro board.
+#define SAM4CP16BMB                67  //!< SAM4CP16BMB board.
+#define SAM4E_XPLAINED_PRO         68  //!< SAM4E Xplained Pro board.
+#define SAMD21_XPLAINED_PRO        69  //!< SAM D21 Xplained Pro board.
+#define SAMR21_XPLAINED_PRO        70  //!< SAM R21 Xplained Pro board.
+#define SAM4CMP_DB                 71  //!< SAM4CMP demo board.
+#define SAM4CMS_DB                 72  //!< SAM4CMS demo board.
+#define ATPL230AMB                 73  //!< ATPL230AMB board.
+#define SAMD11_XPLAINED_PRO        74  //!< SAM D11 Xplained Pro board.
+#define SAMG55_XPLAINED_PRO        75  //!< SAMG55 Xplained Pro board.
+#define SAML21_XPLAINED_PRO        76  //!< SAM L21 Xplained Pro board.
+#define SAMD10_XPLAINED_MINI       77  //!< SAM D10 Xplained Mini board.
+#define SAMDA1_XPLAINED_PRO        78  //!< SAM DA1 Xplained Pro board.
+#define SAMW25_XPLAINED_PRO        79  //!< SAMW25 Xplained Pro board.
+#define SAMC21_XPLAINED_PRO        80  //!< SAM C21 Xplained Pro board.
+#define SAMV71_XPLAINED_ULTRA      81  //!< SAMV71 Xplained Ultra board.
+#define ATMEGA328P_XPLAINED_MINI   82  //!< ATMEGA328P Xplained MINI board.
+#define ATMEGA328PB_XPLAINED_MINI  83  //!< ATMEGA328PB Xplained MINI board.
+#define SAMB11_XPLAINED_PRO        84  //!< SAM B11 Xplained Pro board.
+#define SAME70_XPLAINED            85  //!< SAME70 Xplained board.
+#define SAML22_XPLAINED_PRO        86  //!< SAM L22 Xplained Pro board.
+#define SAML22_XPLAINED_PRO_B      87  //!< SAM L22 Xplained Pro board.
+#define SAMR21ZLL_EK               88  //!< SAMR21ZLL-EK board.
+#define ATMEGA168PB_XPLAINED_MINI  89  //!< ATMEGA168PB Xplained MINI board.
+#define ATMEGA324PB_XPLAINED_PRO   90  //!< ATMEGA324PB Xplained Pro board.
+#define SAMB11CSP_XPLAINED_PRO     91  //!< SAM B11 CSP Xplained Pro board.
+#define SAMB11ZR_XPLAINED_PRO      92  //!< SAM B11 ZR Xplained Pro board.
+#define SAMR30_XPLAINED_PRO        93  //!< SAM R30 Xplained Pro board.
+#define SIMULATOR_XMEGA_A1         97  //!< Simulator for XMEGA A1 devices.
+#define AVR_SIMULATOR_UC3          98  //!< Simulator for the AVR UC3 device family.
+#define USER_BOARD                 99  //!< User-reserved board (if any).
+#define DUMMY_BOARD               100  //!< Dummy board to support board-independent applications (e.g. bootloader).
+//! @}
+
+/*! \name Extension Boards
+ */
+//! @{
+#define EXT1102                      1  //!< AT32UC3B EXT1102 board
+#define MC300                        2  //!< AT32UC3 MC300 board
+#define SENSORS_XPLAINED_INERTIAL_1  3  //!< Xplained inertial sensor board 1
+#define SENSORS_XPLAINED_INERTIAL_2  4  //!< Xplained inertial sensor board 2
+#define SENSORS_XPLAINED_PRESSURE_1  5  //!< Xplained pressure sensor board
+#define SENSORS_XPLAINED_LIGHTPROX_1 6  //!< Xplained light & proximity sensor board
+#define SENSORS_XPLAINED_INERTIAL_A1 7  //!< Xplained inertial sensor board "A"
+#define RZ600_AT86RF231              8  //!< AT86RF231 RF board in RZ600
+#define RZ600_AT86RF230B             9  //!< AT86RF230B RF board in RZ600
+#define RZ600_AT86RF212             10  //!< AT86RF212 RF board in RZ600
+#define SENSORS_XPLAINED_BREADBOARD 11  //!< Xplained sensor development breadboard
+#define SECURITY_XPLAINED           12  //!< Xplained ATSHA204 board
+#define USER_EXT_BOARD              99  //!< User-reserved extension board (if any).
+//! @}
+
+#if BOARD == EVK1100
+#  include "evk1100/evk1100.h"
+#elif BOARD == EVK1101
+#  include "evk1101/evk1101.h"
+#elif BOARD == UC3C_EK
+#  include "uc3c_ek/uc3c_ek.h"
+#elif BOARD == EVK1104
+#  include "evk1104/evk1104.h"
+#elif BOARD == EVK1105
+#  include "evk1105/evk1105.h"
+#elif BOARD == STK600_RCUC3L0
+#  include "stk600/rcuc3l0/stk600_rcuc3l0.h"
+#elif BOARD == UC3L_EK
+#  include "uc3l_ek/uc3l_ek.h"
+#elif BOARD == STK600_RCUC3L4
+#  include "stk600/rcuc3l4/stk600_rcuc3l4.h"
+#elif BOARD == XPLAIN
+#  include "xplain/xplain.h"
+#elif BOARD == STK600_MEGA
+  /*No header-file to include*/
+#elif BOARD == STK600_MEGA_RF
+#  include "stk600.h"
+#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO
+#  include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"
+#elif BOARD == ATMEGA256RFR2_ZIGBIT
+#  include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"
+#elif BOARD == STK600_RC032X
+#  include "stk600/rc032x/stk600_rc032x.h"
+#elif BOARD == STK600_RC044X
+#  include "stk600/rc044x/stk600_rc044x.h"
+#elif BOARD == STK600_RC064X
+#  include "stk600/rc064x/stk600_rc064x.h"
+#elif BOARD == STK600_RC100X
+#  include "stk600/rc100x/stk600_rc100x.h"
+#elif BOARD == UC3_A3_XPLAINED
+#  include "uc3_a3_xplained/uc3_a3_xplained.h"
+#elif BOARD == UC3_L0_XPLAINED
+#  include "uc3_l0_xplained/uc3_l0_xplained.h"
+#elif BOARD == STK600_RCUC3B0
+#  include "stk600/rcuc3b0/stk600_rcuc3b0.h"
+#elif BOARD == STK600_RCUC3D
+#  include "stk600/rcuc3d/stk600_rcuc3d.h"
+#elif BOARD == STK600_RCUC3C0
+#  include "stk600/rcuc3c0/stk600_rcuc3c0.h"
+#elif BOARD == SAMG53_XPLAINED_PRO
+#  include "samg53_xplained_pro/samg53_xplained_pro.h"
+#elif BOARD == SAMG55_XPLAINED_PRO
+#  include "samg55_xplained_pro/samg55_xplained_pro.h"
+#elif BOARD == XMEGA_B1_XPLAINED
+#  include "xmega_b1_xplained/xmega_b1_xplained.h"
+#elif BOARD == STK600_RC064X_LCDX
+#  include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"
+#elif BOARD == STK600_RC100X_LCDX
+#  include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"
+#elif BOARD == XMEGA_A1_XPLAINED
+#  include "xmega_a1_xplained/xmega_a1_xplained.h"
+#elif BOARD == XMEGA_A1U_XPLAINED_PRO
+#  include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h"
+#elif BOARD == UC3_L0_XPLAINED_BC
+#  include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"
+#elif BOARD == SAM3S_EK
+#  include "sam3s_ek/sam3s_ek.h"
+#  include "system_sam3s.h"
+#elif BOARD == SAM3S_EK2
+#  include "sam3s_ek2/sam3s_ek2.h"
+#  include "system_sam3sd8.h"
+#elif BOARD == SAM3U_EK
+#  include "sam3u_ek/sam3u_ek.h"
+#  include "system_sam3u.h"
+#elif BOARD == SAM3X_EK
+#  include "sam3x_ek/sam3x_ek.h"
+#  include "system_sam3x.h"
+#elif BOARD == SAM3N_EK
+#  include "sam3n_ek/sam3n_ek.h"
+#  include "system_sam3n.h"
+#elif BOARD == SAM4S_EK
+#  include "sam4s_ek/sam4s_ek.h"
+#  include "system_sam4s.h"
+#elif BOARD == SAM4S_WPIR_RD
+#  include "sam4s_wpir_rd/sam4s_wpir_rd.h"
+#  include "system_sam4s.h"
+#elif BOARD == SAM4S_XPLAINED
+#  include "sam4s_xplained/sam4s_xplained.h"
+#  include "system_sam4s.h"
+#elif BOARD == SAM4S_EK2
+#  include "sam4s_ek2/sam4s_ek2.h"
+#  include "system_sam4s.h"
+#elif BOARD == MEGA_1284P_XPLAINED
+  /*No header-file to include*/
+#elif BOARD == ARDUINO_DUE_X
+#  include "arduino_due_x/arduino_due_x.h"
+#  include "system_sam3x.h"
+#elif BOARD == SAM4L_EK
+#  include "sam4l_ek/sam4l_ek.h"
+#elif BOARD == SAM4E_EK
+#  include "sam4e_ek/sam4e_ek.h"
+#elif BOARD == SAMD20_XPLAINED_PRO
+#  include "samd20_xplained_pro/samd20_xplained_pro.h"
+#elif BOARD == SAMD21_XPLAINED_PRO
+#  include "samd21_xplained_pro/samd21_xplained_pro.h"
+#elif BOARD == SAMR21_XPLAINED_PRO
+#  include "samr21_xplained_pro/samr21_xplained_pro.h"
+#elif BOARD == SAMR30_XPLAINED_PRO
+#  include "samr30_xplained_pro/samr30_xplained_pro.h"
+#elif BOARD == SAMR21ZLL_EK
+#  include "samr21zll_ek/samr21zll_ek.h"
+#elif BOARD == SAMD11_XPLAINED_PRO
+#  include "samd11_xplained_pro/samd11_xplained_pro.h"
+#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__)
+#  include "saml21_xplained_pro/saml21_xplained_pro.h"
+#elif BOARD == SAML22_XPLAINED_PRO
+#  include "saml22_xplained_pro/saml22_xplained_pro.h"
+#elif BOARD == SAML22_XPLAINED_PRO_B
+#  include "saml22_xplained_pro_b/saml22_xplained_pro_b.h"
+#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__)
+#  include "saml21_xplained_pro_b/saml21_xplained_pro.h"
+#elif BOARD == SAMD10_XPLAINED_MINI
+#  include "samd10_xplained_mini/samd10_xplained_mini.h"
+#elif BOARD == SAMDA1_XPLAINED_PRO
+#  include "samda1_xplained_pro/samda1_xplained_pro.h"
+#elif BOARD == SAMC21_XPLAINED_PRO
+#  include "samc21_xplained_pro/samc21_xplained_pro.h"
+#elif BOARD == SAM4N_XPLAINED_PRO
+#  include "sam4n_xplained_pro/sam4n_xplained_pro.h"
+#elif BOARD == SAMW25_XPLAINED_PRO
+#  include "samw25_xplained_pro/samw25_xplained_pro.h"
+#elif BOARD == SAMV71_XPLAINED_ULTRA
+#  include "samv71_xplained_ultra/samv71_xplained_ultra.h"
+#elif BOARD == MEGA1284P_XPLAINED_BC
+#  include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"
+#elif BOARD == UC3_L0_QT600
+#  include "uc3_l0_qt600/uc3_l0_qt600.h"
+#elif BOARD == XMEGA_A3BU_XPLAINED
+#  include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"
+#elif BOARD == XMEGA_E5_XPLAINED
+#  include "xmega_e5_xplained/xmega_e5_xplained.h"
+#elif BOARD == UC3B_BOARD_CONTROLLER
+#  include "uc3b_board_controller/uc3b_board_controller.h"
+#elif BOARD == RZ600
+#  include "rz600/rz600.h"
+#elif BOARD == STK600_RCUC3A0
+#  include "stk600/rcuc3a0/stk600_rcuc3a0.h"
+#elif BOARD == ATXMEGA128A1_QT600
+#  include "atxmega128a1_qt600/atxmega128a1_qt600.h"
+#elif BOARD == STK600_RCUC3L3
+#  include "stk600/rcuc3l3/stk600_rcuc3l3.h"
+#elif BOARD == SAM4S_XPLAINED_PRO
+#  include "sam4s_xplained_pro/sam4s_xplained_pro.h"
+#elif BOARD == SAM4L_XPLAINED_PRO
+#  include "sam4l_xplained_pro/sam4l_xplained_pro.h"
+#elif BOARD == SAM4L8_XPLAINED_PRO
+#  include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"
+#elif BOARD == SAM4C_EK
+#  include "sam4c_ek/sam4c_ek.h"
+#elif BOARD == SAM4CMP_DB
+#  include "sam4cmp_db/sam4cmp_db.h"
+#elif BOARD == SAM4CMS_DB
+#  include "sam4cms_db/sam4cms_db.h"
+#elif BOARD == SAM4CP16BMB
+#  include "sam4cp16bmb/sam4cp16bmb.h"
+#elif BOARD == ATPL230AMB
+#  include "atpl230amb/atpl230amb.h"
+#elif BOARD == XMEGA_C3_XPLAINED
+#  include "xmega_c3_xplained/xmega_c3_xplained.h"
+#elif BOARD == XMEGA_RF233_ZIGBIT
+#  include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"
+#elif BOARD == XMEGA_A3_REB_CBB
+#  include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"
+#elif BOARD == ATMEGARFX_RCB
+#  include "atmegarfx_rcb/atmegarfx_rcb.h"
+#elif BOARD == RCB256RFR2_XPRO
+#  include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h"
+#elif BOARD == XMEGA_RF212B_ZIGBIT
+#  include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"
+#elif BOARD == SAM4E_XPLAINED_PRO
+#  include "sam4e_xplained_pro/sam4e_xplained_pro.h"
+#elif BOARD == ATMEGA328P_XPLAINED_MINI
+#  include "atmega328p_xplained_mini/atmega328p_xplained_mini.h"
+#elif BOARD == ATMEGA328PB_XPLAINED_MINI
+#  include "atmega328pb_xplained_mini/atmega328pb_xplained_mini.h"
+#elif BOARD == SAMB11_XPLAINED_PRO
+#  include "samb11_xplained_pro/samb11_xplained_pro.h"
+#elif BOARD == SAME70_XPLAINED
+#  include "same70_xplained/same70_xplained.h"
+#elif BOARD == ATMEGA168PB_XPLAINED_MINI
+#  include "atmega168pb_xplained_mini/atmega168pb_xplained_mini.h"
+#elif BOARD == ATMEGA324PB_XPLAINED_PRO
+#  include "atmega324pb_xplained_pro/atmega324pb_xplained_pro.h"
+#elif BOARD == SAMB11CSP_XPLAINED_PRO
+#  include "samb11csp_xplained_pro/samb11csp_xplained_pro.h"
+#elif BOARD == SAMB11ZR_XPLAINED_PRO
+#  include "samb11zr_xplained_pro/samb11zr_xplained_pro.h"
+#elif BOARD == SIMULATOR_XMEGA_A1
+#  include "simulator/xmega_a1/simulator_xmega_a1.h"
+#elif BOARD == AVR_SIMULATOR_UC3
+#  include "avr_simulator_uc3/avr_simulator_uc3.h"
+#elif BOARD == USER_BOARD
+  // User-reserved area: #include the header file of your board here (if any).
+#  include "user_board.h"
+#elif BOARD == DUMMY_BOARD
+#  include "dummy/dummy_board.h"
+#else
+#  error No known Atmel board defined
+#endif
+
+#if (defined EXT_BOARD)
+#  if EXT_BOARD == MC300
+#    include "mc300/mc300.h"
+#  elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1)  || \
+        (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2)  || \
+        (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \
+        (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1)  || \
+        (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \
+        (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
+#    include "sensors_xplained/sensors_xplained.h"
+#  elif EXT_BOARD == RZ600_AT86RF231
+#     include "at86rf231/at86rf231.h"
+#  elif EXT_BOARD == RZ600_AT86RF230B
+#    include "at86rf230b/at86rf230b.h"
+#  elif EXT_BOARD == RZ600_AT86RF212
+#    include "at86rf212/at86rf212.h"
+#  elif EXT_BOARD == SECURITY_XPLAINED
+#    include "security_xplained.h"
+#  elif EXT_BOARD == USER_EXT_BOARD
+    // User-reserved area: #include the header file of your extension board here
+    // (if any).
+#  endif
+#endif
+
+
+#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+/*! \brief This function initializes the board target resources
+ *
+ * This function should be called to ensure proper initialization of the target
+ * board hardware connected to the part.
+ */
+extern void board_init(void);
+
+#endif  // #ifdef __AVR32_ABI_COMPILER__
+#else
+/*! \brief This function initializes the board target resources
+ *
+ * This function should be called to ensure proper initialization of the target
+ * board hardware connected to the part.
+ */
+extern void board_init(void);
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \}
+ */
+
+#endif  // _BOARD_H_

asf/common/components/memory/virtual_mem/virtual_mem.c

@@ -0,0 +1,339 @@
+/**
+ * \file
+ *
+ * \brief Management of the virtual memory.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \defgroup group_common_components_memory_virtual_mem Virtual Memory in RAM
+ *
+ * The component manages a disk on a volatile memory (internal RAM).
+ * This can be connected to a File System management or a USB Device
+ * Mass Storage Interface via the service Memory Control Access.
+ *
+ * \{
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+//_____  I N C L U D E S ___________________________________________________
+
+#include "conf_access.h"
+#include "conf_virtual_mem.h"
+
+
+#if VIRTUAL_MEM == ENABLE
+
+#include "virtual_mem.h"
+#include <string.h>
+
+
+#ifndef VMEM_NB_SECTOR
+#  error Define VMEM_NB_SECTOR in conf_virtual_mem.h file
+#endif
+
+//_____ M A C R O S ________________________________________________________
+
+//_____ P R I V A T E   D E C L A R A T I O N S ____________________________
+
+
+//_____ D E F I N I T I O N S ______________________________________________
+
+#ifdef VMEM_ADDRESS
+// Virtual disk memory start address is defined in conf_virtual_mem.h
+# if (0 != (VMEM_ADDRESS & 0x3))
+#   error VMEM_ADDRESS defined in conf_virtual_mem.h must be a WORD address
+# endif
+# if (VMEM_ADDRESS + (VMEM_NB_SECTOR * VMEM_SECTOR_SIZE) - 1) > UINTPTR_MAX
+#  include <hugemem.h>
+static hugemem_ptr_t vmem_data = (hugemem_ptr_t)VMEM_ADDRESS;
+# else
+static uint8_t* vmem_data = (uint8_t*)VMEM_ADDRESS;
+# endif
+#else
+COMPILER_WORD_ALIGNED
+static uint8_t vmem_data[VMEM_NB_SECTOR * VMEM_SECTOR_SIZE];
+#endif
+
+static bool b_vmem_unloaded = false;
+
+//_____ D E C L A R A T I O N S ____________________________________________
+
+//! This function tests memory state, and starts memory initialization
+//! @return                            Ctrl_status
+//!   It is ready                ->    CTRL_GOOD
+//!   Memory unplug              ->    CTRL_NO_PRESENT
+//!   Not initialized or changed ->    CTRL_BUSY
+//!   An error occurred          ->    CTRL_FAIL
+Ctrl_status virtual_test_unit_ready(void)
+{
+	return b_vmem_unloaded ? CTRL_NO_PRESENT : CTRL_GOOD;
+}
+
+
+//! This function returns the address of the last valid sector
+//! @param uint32_t_nb_sector  Pointer to number of sectors (sector=512 bytes)
+//! @return                            Ctrl_status
+//!   It is ready                ->    CTRL_GOOD
+//!   Memory unplug              ->    CTRL_NO_PRESENT
+//!   Not initialized or changed ->    CTRL_BUSY
+//!   An error occurred          ->    CTRL_FAIL
+Ctrl_status virtual_read_capacity(uint32_t *uint32_t_nb_sector)
+{
+	if (b_vmem_unloaded) {
+		return CTRL_NO_PRESENT;
+	}
+
+	if (VMEM_NB_SECTOR<8) {
+		*uint32_t_nb_sector = 8-1;
+	} else {
+		*uint32_t_nb_sector = VMEM_NB_SECTOR- 1;
+	}
+	return CTRL_GOOD;
+}
+
+
+//! This function returns the write-protected mode
+//!
+//! @return true if the memory is protected
+//!
+bool virtual_wr_protect(void)
+{
+	return false;
+}
+
+
+//! This function informs about the memory type
+//!
+//! @return true if the memory is removable
+//!
+bool virtual_removal(void)
+{
+	return true;
+}
+
+
+//! This function unloads/loads the memory
+//!
+//! @return true if the memory is unloaded
+//!
+bool virtual_unload(bool unload)
+{
+	b_vmem_unloaded = unload;
+	return true;
+}
+
+//------------ SPECIFIC FUNCTIONS FOR TRANSFER BY USB -------------------------
+
+#if ACCESS_USB == true
+
+#include "udi_msc.h"
+
+//! This function transfers the data between memory and USB MSC interface
+//!
+//! @param addr         Sector address to start read
+//! @param nb_sector    Number of sectors to transfer (sector=512 bytes)
+//! @param b_read       Memory to USB, if true
+//!
+//! @return                            Ctrl_status
+//!   It is ready                ->    CTRL_GOOD
+//!   Memory unplug              ->    CTRL_NO_PRESENT
+//!   Not initialized or changed ->    CTRL_BUSY
+//!   An error occurred          ->    CTRL_FAIL
+//!
+static Ctrl_status virtual_usb_trans(uint32_t addr, uint16_t nb_sector,
+		bool b_read)
+{
+/* USB DMA for XMEGA only works on internal RAM, so use a temporal buffer if
+ * it's outside this.
+ */
+#if defined(VMEM_ADDRESS) && ((VMEM_ADDRESS + (VMEM_NB_SECTOR * VMEM_SECTOR_SIZE) - 1) > UINTPTR_MAX)
+	uint8_t       buffer[VMEM_SECTOR_SIZE];
+	hugemem_ptr_t ptr_cram;
+
+	if ((addr > VMEM_NB_SECTOR) ||  (addr + nb_sector > VMEM_NB_SECTOR)) {
+		return CTRL_FAIL;
+	}
+
+	while (nb_sector) {
+		ptr_cram = (hugemem_ptr_t)((uint32_t)vmem_data
+				+ (addr++ * VMEM_SECTOR_SIZE));
+		if (b_read) {
+			hugemem_read_block(buffer, ptr_cram, VMEM_SECTOR_SIZE);
+			if (!udi_msc_trans_block(b_read, buffer,
+						VMEM_SECTOR_SIZE, NULL)) {
+				return CTRL_FAIL; // transfer aborted
+			}
+		} else {
+			if (!udi_msc_trans_block(b_read, buffer,
+						VMEM_SECTOR_SIZE, NULL)) {
+				return CTRL_FAIL; // transfer aborted
+			}
+			hugemem_write_block(ptr_cram, buffer,
+					VMEM_SECTOR_SIZE);
+		}
+		nb_sector -= 1;
+	}
+#else
+	uint8_t *ptr_cram;
+	uint8_t nb_sector_trans;
+
+	if ((addr > VMEM_NB_SECTOR) ||  (addr + nb_sector > VMEM_NB_SECTOR)) {
+		return CTRL_FAIL;
+	}
+
+	while (nb_sector) {
+		// udi_msc_trans_block() is limited to 64KB
+		nb_sector_trans = min(nb_sector, 64*(1024/VMEM_SECTOR_SIZE));
+		ptr_cram = &vmem_data[addr++ * VMEM_SECTOR_SIZE];
+		if (!udi_msc_trans_block( b_read, ptr_cram,
+				nb_sector_trans*VMEM_SECTOR_SIZE, NULL)) {
+			return CTRL_FAIL; // transfer aborted
+		}
+		nb_sector -= nb_sector_trans;
+	}
+#endif
+
+	return CTRL_GOOD;
+}
+
+//! This function transfers the memory data to the USB MSC interface
+//!
+//! @param addr         Sector address to start read
+//! @param nb_sector    Number of sectors to transfer (sector=512 bytes)
+//!
+//! @return                            Ctrl_status
+//!   It is ready                ->    CTRL_GOOD
+//!   Memory unplug              ->    CTRL_NO_PRESENT
+//!   Not initialized or changed ->    CTRL_BUSY
+//!   An error occurred          ->    CTRL_FAIL
+//!
+Ctrl_status virtual_usb_read_10(uint32_t addr, uint16_t nb_sector)
+{
+	return virtual_usb_trans(addr, nb_sector, true);
+}
+
+
+//! This function transfers the USB MSC data to the memory
+//!
+//! @param addr         Sector address to start write
+//! @param nb_sector    Number of sectors to transfer (sector=512 bytes)
+//!
+//! @return                            Ctrl_status
+//!   It is ready                ->    CTRL_GOOD
+//!   Memory unplug              ->    CTRL_NO_PRESENT
+//!   Not initialized or changed ->    CTRL_BUSY
+//!   An error occurred          ->    CTRL_FAIL
+//!
+Ctrl_status virtual_usb_write_10(uint32_t addr, uint16_t nb_sector)
+{
+	return virtual_usb_trans(addr, nb_sector, false);
+}
+
+#endif  // ACCESS_USB == true
+
+
+//------------ SPECIFIC FUNCTIONS FOR TRANSFER BY RAM --------------------------
+
+#if ACCESS_MEM_TO_RAM == true
+
+#include <string.h>
+
+//! This function transfers 1 data sector from memory to RAM
+//! sector = 512 bytes
+//! @param addr         Sector address to start read
+//! @param ram          Address of RAM buffer
+//! @return                            Ctrl_status
+//!   It is ready                ->    CTRL_GOOD
+//!   Memory unplug              ->    CTRL_NO_PRESENT
+//!   Not initialized or changed ->    CTRL_BUSY
+//!   An error occurred          ->    CTRL_FAIL
+Ctrl_status virtual_mem_2_ram(uint32_t addr, void *ram)
+{
+	if (addr + 1 > Max(VMEM_NB_SECTOR, 8)) {
+		return CTRL_FAIL;
+	}
+
+	// If overflow (possible with size virtual mem < 8 sectors) then read the last sector
+	addr = min(addr, VMEM_NB_SECTOR - 1);
+#if defined(VMEM_ADDRESS) && ((VMEM_ADDRESS + (VMEM_NB_SECTOR * VMEM_SECTOR_SIZE) - 1) > UINTPTR_MAX)
+	hugemem_read_block(ram, (hugemem_ptr_t)((uint32_t)vmem_data + addr
+				* VMEM_SECTOR_SIZE), VMEM_SECTOR_SIZE);
+#else
+	memcpy(ram, &vmem_data[addr * VMEM_SECTOR_SIZE], VMEM_SECTOR_SIZE);
+#endif
+
+	return CTRL_GOOD;
+}
+
+
+//! This function transfers 1 data sector from memory to RAM
+//! sector = 512 bytes
+//! @param addr         Sector address to start write
+//! @param ram          Address of RAM buffer
+//! @return                            Ctrl_status
+//!   It is ready                ->    CTRL_GOOD
+//!   Memory unplug              ->    CTRL_NO_PRESENT
+//!   Not initialized or changed ->    CTRL_BUSY
+//!   An error occurred          ->    CTRL_FAIL
+Ctrl_status virtual_ram_2_mem(uint32_t addr, const void *ram)
+{
+	if (addr + 1 > VMEM_NB_SECTOR) {
+		return CTRL_FAIL;
+	}
+
+#if defined(VMEM_ADDRESS) && ((VMEM_ADDRESS + (VMEM_NB_SECTOR * VMEM_SECTOR_SIZE) - 1) > UINTPTR_MAX)
+	hugemem_write_block((hugemem_ptr_t)((uint32_t)vmem_data + addr
+				* VMEM_SECTOR_SIZE), ram, VMEM_SECTOR_SIZE);
+#else
+	memcpy(&vmem_data[addr * VMEM_SECTOR_SIZE], ram, VMEM_SECTOR_SIZE);
+#endif
+	return CTRL_GOOD;
+}
+
+#endif  // ACCESS_MEM_TO_RAM == true
+
+
+#endif  // VIRTUAL_MEM == ENABLE
+
+/**
+ * \}
+ */

asf/common/components/memory/virtual_mem/virtual_mem.h

@@ -0,0 +1,97 @@
+/**
+ * \file
+ *
+ * \brief Management of the virtual memory.
+ *
+ * This file manages the virtual memory.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _VIRTUAL_MEM_H_
+#define _VIRTUAL_MEM_H_
+
+
+#include "conf_access.h"
+
+#if VIRTUAL_MEM == ENABLE
+
+#include "ctrl_access.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//_____ D E F I N I T I O N S ______________________________________________
+
+#define VMEM_SECTOR_SIZE   512
+
+
+//---- CONTROL FUNCTIONS ----
+
+extern Ctrl_status  virtual_test_unit_ready(void);
+extern Ctrl_status  virtual_read_capacity(uint32_t *u32_nb_sector);
+extern bool         virtual_wr_protect(void);
+extern bool         virtual_removal(void);
+extern bool         virtual_unload(bool unload);
+
+
+//---- ACCESS DATA FUNCTIONS ----
+
+// USB interface
+#if ACCESS_USB == true
+extern Ctrl_status  virtual_usb_read_10 (uint32_t addr, uint16_t nb_sector);
+extern Ctrl_status  virtual_usb_write_10(uint32_t addr, uint16_t nb_sector);
+#endif
+
+// RAM interface
+#if ACCESS_MEM_TO_RAM == true
+extern Ctrl_status  virtual_mem_2_ram(uint32_t addr,       void *ram);
+extern Ctrl_status  virtual_ram_2_mem(uint32_t addr, const void *ram);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif  // _VIRTUAL_MEM_H_

asf/common/services/sleepmgr/samd/sleepmgr.c

@@ -1,9 +1,9 @@
 /**
  * \file
  *
- * \brief Instance description for PUKCC
+ * \brief Chip-specific sleep manager configuration
  *
- * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
@@ -40,18 +40,14 @@
  * \asf_license_stop
  *
  */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <compiler.h>
+#include <sleepmgr.h>
 
-#ifndef _SAMD51_PUKCC_INSTANCE_
-#define _SAMD51_PUKCC_INSTANCE_
+#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__)
 
-/* ========== Register definition for PUKCC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#else
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES];
 
-/* ========== Instance parameters for PUKCC peripheral ========== */
-#define PUKCC_CLK_AHB_ID            20      
-#define PUKCC_RAM_ADDR_SIZE         12      
-#define PUKCC_ROM_ADDR_SIZE         16      
-
-#endif /* _SAMD51_PUKCC_INSTANCE_ */
+#endif /* CONFIG_SLEEPMGR_ENABLE */

asf/common/services/sleepmgr/samd/sleepmgr.h

@@ -0,0 +1,128 @@
+/**
+ * \file
+ *
+ * \brief Chip-specific sleep manager configuration
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SAM_SLEEPMGR_INCLUDED
+#define SAM_SLEEPMGR_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <conf_sleepmgr.h>
+#include <interrupt.h>
+#include "system.h"
+
+/**
+ * \weakgroup sleepmgr_group
+ * @{
+ */
+
+enum sleepmgr_mode {
+	/** Active mode. */
+	SLEEPMGR_ACTIVE = 0,
+
+	/**
+	 *  Idle 0 mode.
+	 *  Potential Wake Up sources: Synchronous(APB, AHB), asynchronous.
+	 */
+	SLEEPMGR_IDLE_0,
+
+	/**
+	 *  Idle 1 mode.
+	 *  Potential Wake Up sources: Synchronous (APB), asynchronous
+	 */
+	SLEEPMGR_IDLE_1,
+
+	/**
+	 *  Idle 2 mode.
+	 *  Potential Wake Up sources: Asynchronous
+	 */
+	SLEEPMGR_IDLE_2,
+
+	/**
+	 * Standby mode.
+	 * Potential Wake Up sources: Asynchronous
+	 */
+	SLEEPMGR_STANDBY,
+
+	SLEEPMGR_NR_OF_MODES,
+};
+
+/**
+ * \internal
+ * \name Internal arrays
+ * @{
+ */
+#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__)
+/** Sleep mode lock counters */
+extern uint8_t sleepmgr_locks[];
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+/** @} */
+
+static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode)
+{
+	Assert(sleep_mode != SLEEPMGR_ACTIVE);
+#ifdef CONFIG_SLEEPMGR_ENABLE
+	cpu_irq_disable();
+
+	/* Enter the sleep mode. */
+	system_set_sleepmode((enum system_sleepmode)(sleep_mode - 1));
+	cpu_irq_enable();
+	system_sleep();
+#else
+	UNUSED(sleep_mode);
+	cpu_irq_enable();
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SAM_SLEEPMGR_INCLUDED */

asf/common/services/sleepmgr/sleepmgr.h

@@ -0,0 +1,273 @@
+/**
+ * \file
+ *
+ * \brief Sleep manager
+ *
+ * Copyright (c) 2010-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SLEEPMGR_H
+#define SLEEPMGR_H
+
+#include <compiler.h>
+#include <parts.h>
+
+#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAMS70 || SAME70)
+# include "sam/sleepmgr.h"
+#elif XMEGA
+# include "xmega/sleepmgr.h"
+#elif UC3
+# include "uc3/sleepmgr.h"
+#elif SAM4L
+# include "sam4l/sleepmgr.h"
+#elif MEGA
+# include "mega/sleepmgr.h"
+#elif (SAMD20 || SAMD21 || SAMR21 || SAMD11 || SAMDA1)
+# include "samd/sleepmgr.h"
+#elif (SAML21 || SAML22 || SAMR30)
+# include "saml/sleepmgr.h"
+#elif (SAMC21)
+# include "samc/sleepmgr.h"
+#else
+# error Unsupported device.
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup sleepmgr_group Sleep manager
+ *
+ * The sleep manager is a service for ensuring that the device is not put to
+ * sleep in deeper sleep modes than the system (e.g., peripheral drivers,
+ * services or the application) allows at any given time.
+ *
+ * It is based on the use of lock counting for the individual sleep modes, and
+ * will put the device to sleep in the shallowest sleep mode that has a non-zero
+ * lock count. The drivers/services/application can change these counts by use
+ * of \ref sleepmgr_lock_mode and \ref sleepmgr_unlock_mode.
+ * Refer to \ref sleepmgr_mode for a list of the sleep modes available for
+ * locking, and the device datasheet for information on their effect.
+ *
+ * The application must supply the file \ref conf_sleepmgr.h.
+ *
+ * For the sleep manager to be enabled, the symbol \ref CONFIG_SLEEPMGR_ENABLE
+ * must be defined, e.g., in \ref conf_sleepmgr.h. If this symbol is not
+ * defined, the functions are replaced with dummy functions and no RAM is used.
+ *
+ * @{
+ */
+
+/**
+ * \def CONFIG_SLEEPMGR_ENABLE
+ * \brief Configuration symbol for enabling the sleep manager
+ *
+ * If this symbol is not defined, the functions of this service are replaced
+ * with dummy functions. This is useful for reducing code size and execution
+ * time if the sleep manager is not needed in the application.
+ *
+ * This symbol may be defined in \ref conf_sleepmgr.h.
+ */
+#if defined(__DOXYGEN__) && !defined(CONFIG_SLEEPMGR_ENABLE)
+#  define CONFIG_SLEEPMGR_ENABLE
+#endif
+
+/**
+ * \enum sleepmgr_mode
+ * \brief Sleep mode locks
+ *
+ * Identifiers for the different sleep mode locks.
+ */
+
+/**
+ * \brief Initialize the lock counts
+ *
+ * Sets all lock counts to 0, except the very last one, which is set to 1. This
+ * is done to simplify the algorithm for finding the deepest allowable sleep
+ * mode in \ref sleepmgr_enter_sleep.
+ */
+static inline void sleepmgr_init(void)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+	uint8_t i;
+
+	for (i = 0; i < SLEEPMGR_NR_OF_MODES - 1; i++) {
+		sleepmgr_locks[i] = 0;
+	}
+	sleepmgr_locks[SLEEPMGR_NR_OF_MODES - 1] = 1;
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+/**
+ * \brief Increase lock count for a sleep mode
+ *
+ * Increases the lock count for \a mode to ensure that the sleep manager does
+ * not put the device to sleep in the deeper sleep modes.
+ *
+ * \param mode Sleep mode to lock.
+ */
+static inline void sleepmgr_lock_mode(enum sleepmgr_mode mode)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+	irqflags_t flags;
+
+	if(sleepmgr_locks[mode] >= 0xff) {
+		while (true) {
+			// Warning: maximum value of sleepmgr_locks buffer is no more than 255.
+			// Check APP or change the data type to uint16_t.
+		}
+	}
+
+	// Enter a critical section
+	flags = cpu_irq_save();
+
+	++sleepmgr_locks[mode];
+
+	// Leave the critical section
+	cpu_irq_restore(flags);
+#else
+	UNUSED(mode);
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+/**
+ * \brief Decrease lock count for a sleep mode
+ *
+ * Decreases the lock count for \a mode. If the lock count reaches 0, the sleep
+ * manager can put the device to sleep in the deeper sleep modes.
+ *
+ * \param mode Sleep mode to unlock.
+ */
+static inline void sleepmgr_unlock_mode(enum sleepmgr_mode mode)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+	irqflags_t flags;
+
+	if(sleepmgr_locks[mode] == 0) {
+		while (true) {
+			// Warning: minimum value of sleepmgr_locks buffer is no less than 0.
+			// Check APP.
+		}
+	}
+
+	// Enter a critical section
+	flags = cpu_irq_save();
+
+	--sleepmgr_locks[mode];
+
+	// Leave the critical section
+	cpu_irq_restore(flags);
+#else
+	UNUSED(mode);
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+ /**
+ * \brief Retrieves the deepest allowable sleep mode
+ *
+ * Searches through the sleep mode lock counts, starting at the shallowest sleep
+ * mode, until the first non-zero lock count is found. The deepest allowable
+ * sleep mode is then returned.
+ */
+static inline enum sleepmgr_mode sleepmgr_get_sleep_mode(void)
+{
+	enum sleepmgr_mode sleep_mode = SLEEPMGR_ACTIVE;
+
+#ifdef CONFIG_SLEEPMGR_ENABLE
+	uint8_t *lock_ptr = sleepmgr_locks;
+
+	// Find first non-zero lock count, starting with the shallowest modes.
+	while (!(*lock_ptr)) {
+		lock_ptr++;
+		sleep_mode = (enum sleepmgr_mode)(sleep_mode + 1);
+	}
+
+	// Catch the case where one too many sleepmgr_unlock_mode() call has been
+	// performed on the deepest sleep mode.
+	Assert((uintptr_t)(lock_ptr - sleepmgr_locks) < SLEEPMGR_NR_OF_MODES);
+
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+
+	return sleep_mode;
+}
+
+/**
+ * \fn sleepmgr_enter_sleep
+ * \brief Go to sleep in the deepest allowed mode
+ *
+ * Searches through the sleep mode lock counts, starting at the shallowest sleep
+ * mode, until the first non-zero lock count is found. The device is then put to
+ * sleep in the sleep mode that corresponds to the lock.
+ *
+ * \note This function enables interrupts before going to sleep, and will leave
+ * them enabled upon return. This also applies if sleep is skipped due to ACTIVE
+ * mode being locked.
+ */
+
+static inline void sleepmgr_enter_sleep(void)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+	enum sleepmgr_mode sleep_mode;
+
+	cpu_irq_disable();
+
+	// Find the deepest allowable sleep mode
+	sleep_mode = sleepmgr_get_sleep_mode();
+	// Return right away if first mode (ACTIVE) is locked.
+	if (sleep_mode==SLEEPMGR_ACTIVE) {
+		cpu_irq_enable();
+		return;
+	}
+	// Enter the deepest allowable sleep mode with interrupts enabled
+	sleepmgr_sleep(sleep_mode);
+#else
+	cpu_irq_enable();
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+
+//! @}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SLEEPMGR_H */

asf/common/services/storage/ctrl_access/ctrl_access.c

@@ -0,0 +1,644 @@
+/*****************************************************************************
+ *
+ * \file
+ *
+ * \brief Abstraction layer for memory interfaces.
+ *
+ * This module contains the interfaces:
+ *   - MEM <-> USB;
+ *   - MEM <-> RAM;
+ *   - MEM <-> MEM.
+ *
+ * This module may be configured and expanded to support the following features:
+ *   - write-protected globals;
+ *   - password-protected data;
+ *   - specific features;
+ *   - etc.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ ******************************************************************************/
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+//_____ I N C L U D E S ____________________________________________________
+
+#include "compiler.h"
+#include "preprocessor.h"
+#ifdef FREERTOS_USED
+#include "FreeRTOS.h"
+#include "semphr.h"
+#endif
+#include "ctrl_access.h"
+
+
+//_____ D E F I N I T I O N S ______________________________________________
+
+#ifdef FREERTOS_USED
+
+/*! \name LUN Access Protection Macros
+ */
+//! @{
+
+/*! \brief Locks accesses to LUNs.
+ *
+ * \return \c true if the access was successfully locked, else \c false.
+ */
+#define Ctrl_access_lock()    ctrl_access_lock()
+
+/*! \brief Unlocks accesses to LUNs.
+ */
+#define Ctrl_access_unlock()  xSemaphoreGive(ctrl_access_semphr)
+
+//! @}
+
+//! Handle to the semaphore protecting accesses to LUNs.
+static xSemaphoreHandle ctrl_access_semphr = NULL;
+
+#else
+
+/*! \name LUN Access Protection Macros
+ */
+//! @{
+
+/*! \brief Locks accesses to LUNs.
+ *
+ * \return \c true if the access was successfully locked, else \c false.
+ */
+#define Ctrl_access_lock()    true
+
+/*! \brief Unlocks accesses to LUNs.
+ */
+#define Ctrl_access_unlock()
+
+//! @}
+
+#endif  // FREERTOS_USED
+
+
+#if MAX_LUN
+
+/*! \brief Initializes an entry of the LUN descriptor table.
+ *
+ * \param lun Logical Unit Number.
+ *
+ * \return LUN descriptor table entry initializer.
+ */
+#if ACCESS_USB == true && ACCESS_MEM_TO_RAM == true
+#define Lun_desc_entry(lun) \
+  {\
+    TPASTE3(Lun_, lun, _test_unit_ready),\
+    TPASTE3(Lun_, lun, _read_capacity),\
+    TPASTE3(Lun_, lun, _unload),\
+    TPASTE3(Lun_, lun, _wr_protect),\
+    TPASTE3(Lun_, lun, _removal),\
+    TPASTE3(Lun_, lun, _usb_read_10),\
+    TPASTE3(Lun_, lun, _usb_write_10),\
+    TPASTE3(Lun_, lun, _mem_2_ram),\
+    TPASTE3(Lun_, lun, _ram_2_mem),\
+    TPASTE3(LUN_, lun, _NAME)\
+  }
+#elif ACCESS_USB == true
+#define Lun_desc_entry(lun) \
+  {\
+    TPASTE3(Lun_, lun, _test_unit_ready),\
+    TPASTE3(Lun_, lun, _read_capacity),\
+    TPASTE3(Lun_, lun, _unload),\
+    TPASTE3(Lun_, lun, _wr_protect),\
+    TPASTE3(Lun_, lun, _removal),\
+    TPASTE3(Lun_, lun, _usb_read_10),\
+    TPASTE3(Lun_, lun, _usb_write_10),\
+    TPASTE3(LUN_, lun, _NAME)\
+  }
+#elif ACCESS_MEM_TO_RAM == true
+#define Lun_desc_entry(lun) \
+  {\
+    TPASTE3(Lun_, lun, _test_unit_ready),\
+    TPASTE3(Lun_, lun, _read_capacity),\
+    TPASTE3(Lun_, lun, _unload),\
+    TPASTE3(Lun_, lun, _wr_protect),\
+    TPASTE3(Lun_, lun, _removal),\
+    TPASTE3(Lun_, lun, _mem_2_ram),\
+    TPASTE3(Lun_, lun, _ram_2_mem),\
+    TPASTE3(LUN_, lun, _NAME)\
+  }
+#else
+#define Lun_desc_entry(lun) \
+  {\
+    TPASTE3(Lun_, lun, _test_unit_ready),\
+    TPASTE3(Lun_, lun, _read_capacity),\
+    TPASTE3(Lun_, lun, _unload),\
+    TPASTE3(Lun_, lun, _wr_protect),\
+    TPASTE3(Lun_, lun, _removal),\
+    TPASTE3(LUN_, lun, _NAME)\
+  }
+#endif
+
+//! LUN descriptor table.
+static const struct
+{
+  Ctrl_status (*test_unit_ready)(void);
+  Ctrl_status (*read_capacity)(U32 *);
+  bool (*unload)(bool);
+  bool (*wr_protect)(void);
+  bool (*removal)(void);
+#if ACCESS_USB == true
+  Ctrl_status (*usb_read_10)(U32, U16);
+  Ctrl_status (*usb_write_10)(U32, U16);
+#endif
+#if ACCESS_MEM_TO_RAM == true
+  Ctrl_status (*mem_2_ram)(U32, void *);
+  Ctrl_status (*ram_2_mem)(U32, const void *);
+#endif
+  const char *name;
+} lun_desc[MAX_LUN] =
+{
+#if LUN_0 == ENABLE
+# ifndef Lun_0_unload
+#  define Lun_0_unload NULL
+# endif
+  Lun_desc_entry(0),
+#endif
+#if LUN_1 == ENABLE
+# ifndef Lun_1_unload
+#  define Lun_1_unload NULL
+# endif
+  Lun_desc_entry(1),
+#endif
+#if LUN_2 == ENABLE
+# ifndef Lun_2_unload
+#  define Lun_2_unload NULL
+# endif
+  Lun_desc_entry(2),
+#endif
+#if LUN_3 == ENABLE
+# ifndef Lun_3_unload
+#  define Lun_3_unload NULL
+# endif
+  Lun_desc_entry(3),
+#endif
+#if LUN_4 == ENABLE
+# ifndef Lun_4_unload
+#  define Lun_4_unload NULL
+# endif
+  Lun_desc_entry(4),
+#endif
+#if LUN_5 == ENABLE
+# ifndef Lun_5_unload
+#  define Lun_5_unload NULL
+# endif
+  Lun_desc_entry(5),
+#endif
+#if LUN_6 == ENABLE
+# ifndef Lun_6_unload
+#  define Lun_6_unload NULL
+# endif
+  Lun_desc_entry(6),
+#endif
+#if LUN_7 == ENABLE
+# ifndef Lun_7_unload
+#  define Lun_7_unload NULL
+# endif
+  Lun_desc_entry(7)
+#endif
+};
+
+#endif
+
+
+#if GLOBAL_WR_PROTECT == true
+bool g_wr_protect;
+#endif
+
+
+/*! \name Control Interface
+ */
+//! @{
+
+
+#ifdef FREERTOS_USED
+
+bool ctrl_access_init(void)
+{
+  // If the handle to the protecting semaphore is not valid,
+  if (!ctrl_access_semphr)
+  {
+    // try to create the semaphore.
+    vSemaphoreCreateBinary(ctrl_access_semphr);
+
+    // If the semaphore could not be created, there is no backup solution.
+    if (!ctrl_access_semphr) return false;
+  }
+
+  return true;
+}
+
+
+/*! \brief Locks accesses to LUNs.
+ *
+ * \return \c true if the access was successfully locked, else \c false.
+ */
+static bool ctrl_access_lock(void)
+{
+  // If the semaphore could not be created, there is no backup solution.
+  if (!ctrl_access_semphr) return false;
+
+  // Wait for the semaphore.
+  while (!xSemaphoreTake(ctrl_access_semphr, portMAX_DELAY));
+
+  return true;
+}
+
+#endif  // FREERTOS_USED
+
+
+U8 get_nb_lun(void)
+{
+#if MEM_USB == ENABLE
+#  ifndef Lun_usb_get_lun
+#    define Lun_usb_get_lun()  host_get_lun()
+#  endif
+  U8 nb_lun;
+
+  if (!Ctrl_access_lock()) return MAX_LUN;
+
+  nb_lun = MAX_LUN + Lun_usb_get_lun();
+
+  Ctrl_access_unlock();
+
+  return nb_lun;
+#else
+  return MAX_LUN;
+#endif
+}
+
+
+U8 get_cur_lun(void)
+{
+  return LUN_ID_0;
+}
+
+
+Ctrl_status mem_test_unit_ready(U8 lun)
+{
+  Ctrl_status status;
+
+  if (!Ctrl_access_lock()) return CTRL_FAIL;
+
+  status =
+#if MAX_LUN
+         (lun < MAX_LUN) ? lun_desc[lun].test_unit_ready() :
+#endif
+#if LUN_USB == ENABLE
+                             Lun_usb_test_unit_ready(lun - LUN_ID_USB);
+#else
+                             CTRL_FAIL;
+#endif
+
+  Ctrl_access_unlock();
+
+  return status;
+}
+
+
+Ctrl_status mem_read_capacity(U8 lun, U32 *u32_nb_sector)
+{
+  Ctrl_status status;
+
+  if (!Ctrl_access_lock()) return CTRL_FAIL;
+
+  status =
+#if MAX_LUN
+         (lun < MAX_LUN) ? lun_desc[lun].read_capacity(u32_nb_sector) :
+#endif
+#if LUN_USB == ENABLE
+                             Lun_usb_read_capacity(lun - LUN_ID_USB, u32_nb_sector);
+#else
+                             CTRL_FAIL;
+#endif
+
+  Ctrl_access_unlock();
+
+  return status;
+}
+
+
+U8 mem_sector_size(U8 lun)
+{
+  U8 sector_size;
+
+  if (!Ctrl_access_lock()) return 0;
+
+  sector_size =
+#if MAX_LUN
+              (lun < MAX_LUN) ? 1 :
+#endif
+#if LUN_USB == ENABLE
+                                  Lun_usb_read_sector_size(lun - LUN_ID_USB);
+#else
+                                  0;
+#endif
+
+  Ctrl_access_unlock();
+
+  return sector_size;
+}
+
+
+bool mem_unload(U8 lun, bool unload)
+{
+  bool unloaded;
+#if !MAX_LUN || !defined(Lun_usb_unload)
+  UNUSED(lun);
+#endif
+
+  if (!Ctrl_access_lock()) return false;
+
+  unloaded =
+#if MAX_LUN
+          (lun < MAX_LUN) ?
+              (lun_desc[lun].unload ?
+                  lun_desc[lun].unload(unload) : !unload) :
+#endif
+#if LUN_USB == ENABLE
+# if defined(Lun_usb_unload)
+              Lun_usb_unload(lun - LUN_ID_USB, unload);
+# else
+              !unload; /* Can not unload: load success, unload fail */
+# endif
+#else
+              false; /* No mem, unload/load fail */
+#endif
+
+  Ctrl_access_unlock();
+
+  return unloaded;
+}
+
+bool mem_wr_protect(U8 lun)
+{
+  bool wr_protect;
+
+  if (!Ctrl_access_lock()) return true;
+
+  wr_protect =
+#if MAX_LUN
+             (lun < MAX_LUN) ? lun_desc[lun].wr_protect() :
+#endif
+#if LUN_USB == ENABLE
+                                 Lun_usb_wr_protect(lun - LUN_ID_USB);
+#else
+                                 true;
+#endif
+
+  Ctrl_access_unlock();
+
+  return wr_protect;
+}
+
+
+bool mem_removal(U8 lun)
+{
+  bool removal;
+#if MAX_LUN==0
+  UNUSED(lun);
+#endif
+
+  if (!Ctrl_access_lock()) return true;
+
+  removal =
+#if MAX_LUN
+          (lun < MAX_LUN) ? lun_desc[lun].removal() :
+#endif
+#if LUN_USB == ENABLE
+                              Lun_usb_removal();
+#else
+                              true;
+#endif
+
+  Ctrl_access_unlock();
+
+  return removal;
+}
+
+
+const char *mem_name(U8 lun)
+{
+#if MAX_LUN==0
+  UNUSED(lun);
+#endif
+  return
+#if MAX_LUN
+       (lun < MAX_LUN) ? lun_desc[lun].name :
+#endif
+#if LUN_USB == ENABLE
+                           LUN_USB_NAME;
+#else
+                           NULL;
+#endif
+}
+
+
+//! @}
+
+
+#if ACCESS_USB == true
+
+/*! \name MEM <-> USB Interface
+ */
+//! @{
+
+
+Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector)
+{
+  Ctrl_status status;
+
+  if (!Ctrl_access_lock()) return CTRL_FAIL;
+
+  memory_start_read_action(nb_sector);
+  status =
+#if MAX_LUN
+           (lun < MAX_LUN) ? lun_desc[lun].usb_read_10(addr, nb_sector) :
+#endif
+                             CTRL_FAIL;
+  memory_stop_read_action();
+
+  Ctrl_access_unlock();
+
+  return status;
+}
+
+
+Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector)
+{
+  Ctrl_status status;
+
+  if (!Ctrl_access_lock()) return CTRL_FAIL;
+
+  memory_start_write_action(nb_sector);
+  status =
+#if MAX_LUN
+           (lun < MAX_LUN) ? lun_desc[lun].usb_write_10(addr, nb_sector) :
+#endif
+                             CTRL_FAIL;
+  memory_stop_write_action();
+
+  Ctrl_access_unlock();
+
+  return status;
+}
+
+
+//! @}
+
+#endif  // ACCESS_USB == true
+
+
+#if ACCESS_MEM_TO_RAM == true
+
+/*! \name MEM <-> RAM Interface
+ */
+//! @{
+
+
+Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram)
+{
+  Ctrl_status status;
+#if MAX_LUN==0
+  UNUSED(lun);
+#endif
+
+  if (!Ctrl_access_lock()) return CTRL_FAIL;
+
+  memory_start_read_action(1);
+  status =
+#if MAX_LUN
+           (lun < MAX_LUN) ? lun_desc[lun].mem_2_ram(addr, ram) :
+#endif
+#if LUN_USB == ENABLE
+                             Lun_usb_mem_2_ram(addr, ram);
+#else
+                             CTRL_FAIL;
+#endif
+  memory_stop_read_action();
+
+  Ctrl_access_unlock();
+
+  return status;
+}
+
+
+Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram)
+{
+  Ctrl_status status;
+#if MAX_LUN==0
+  UNUSED(lun);
+#endif
+
+  if (!Ctrl_access_lock()) return CTRL_FAIL;
+
+  memory_start_write_action(1);
+  status =
+#if MAX_LUN
+           (lun < MAX_LUN) ? lun_desc[lun].ram_2_mem(addr, ram) :
+#endif
+#if LUN_USB == ENABLE
+                             Lun_usb_ram_2_mem(addr, ram);
+#else
+                             CTRL_FAIL;
+#endif
+  memory_stop_write_action();
+
+  Ctrl_access_unlock();
+
+  return status;
+}
+
+
+//! @}
+
+#endif  // ACCESS_MEM_TO_RAM == true
+
+
+#if ACCESS_STREAM == true
+
+/*! \name Streaming MEM <-> MEM Interface
+ */
+//! @{
+
+
+  #if ACCESS_MEM_TO_MEM == true
+
+#include "fat.h"
+
+Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_addr, U16 nb_sector)
+{
+  COMPILER_ALIGNED(4)
+  static U8 sector_buf[FS_512B];
+  Ctrl_status status = CTRL_GOOD;
+
+  while (nb_sector--)
+  {
+    if ((status = memory_2_ram(src_lun, src_addr++, sector_buf)) != CTRL_GOOD) break;
+    if ((status = ram_2_memory(dest_lun, dest_addr++, sector_buf)) != CTRL_GOOD) break;
+  }
+
+  return status;
+}
+
+  #endif  // ACCESS_MEM_TO_MEM == true
+
+
+Ctrl_status stream_state(U8 id)
+{
+  UNUSED(id);
+  return CTRL_GOOD;
+}
+
+
+U16 stream_stop(U8 id)
+{
+  UNUSED(id);
+  return 0;
+}
+
+
+//! @}
+
+#endif  // ACCESS_STREAM == true

asf/common/services/storage/ctrl_access/ctrl_access.h

@@ -0,0 +1,402 @@
+/*****************************************************************************
+ *
+ * \file
+ *
+ * \brief Abstraction layer for memory interfaces.
+ *
+ * This module contains the interfaces:
+ *   - MEM <-> USB;
+ *   - MEM <-> RAM;
+ *   - MEM <-> MEM.
+ *
+ * This module may be configured and expanded to support the following features:
+ *   - write-protected globals;
+ *   - password-protected data;
+ *   - specific features;
+ *   - etc.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ ******************************************************************************/
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+#ifndef _CTRL_ACCESS_H_
+#define _CTRL_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup group_common_services_storage_ctrl_access Memory Control Access
+ *
+ * Common abstraction layer for memory interfaces. It provides interfaces between:
+ * Memory and USB, Memory and RAM, Memory and Memory. Common API for XMEGA and UC3.
+ *
+ * \{
+ */
+
+#include "compiler.h"
+#include "conf_access.h"
+
+#ifndef SECTOR_SIZE
+#define SECTOR_SIZE  512
+#endif
+
+//! Status returned by CTRL_ACCESS interfaces.
+typedef enum
+{
+  CTRL_GOOD       = PASS,     //!< Success, memory ready.
+  CTRL_FAIL       = FAIL,     //!< An error occurred.
+  CTRL_NO_PRESENT = FAIL + 1, //!< Memory unplugged.
+  CTRL_BUSY       = FAIL + 2  //!< Memory not initialized or changed.
+} Ctrl_status;
+
+
+// FYI: Each Logical Unit Number (LUN) corresponds to a memory.
+
+// Check LUN defines.
+#ifndef LUN_0
+  #error LUN_0 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_1
+  #error LUN_1 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_2
+  #error LUN_2 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_3
+  #error LUN_3 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_4
+  #error LUN_4 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_5
+  #error LUN_5 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_6
+  #error LUN_6 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_7
+  #error LUN_7 must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+#ifndef LUN_USB
+  #error LUN_USB must be defined as ENABLE or DISABLE in conf_access.h
+#endif
+
+/*! \name LUN IDs
+ */
+//! @{
+#define LUN_ID_0        (0)                 //!< First static LUN.
+#define LUN_ID_1        (LUN_ID_0 + LUN_0)
+#define LUN_ID_2        (LUN_ID_1 + LUN_1)
+#define LUN_ID_3        (LUN_ID_2 + LUN_2)
+#define LUN_ID_4        (LUN_ID_3 + LUN_3)
+#define LUN_ID_5        (LUN_ID_4 + LUN_4)
+#define LUN_ID_6        (LUN_ID_5 + LUN_5)
+#define LUN_ID_7        (LUN_ID_6 + LUN_6)
+#define MAX_LUN         (LUN_ID_7 + LUN_7)  //!< Number of static LUNs.
+#define LUN_ID_USB      (MAX_LUN)           //!< First dynamic LUN (USB host mass storage).
+//! @}
+
+
+// Include LUN header files.
+#if LUN_0 == ENABLE
+  #include LUN_0_INCLUDE
+#endif
+#if LUN_1 == ENABLE
+  #include LUN_1_INCLUDE
+#endif
+#if LUN_2 == ENABLE
+  #include LUN_2_INCLUDE
+#endif
+#if LUN_3 == ENABLE
+  #include LUN_3_INCLUDE
+#endif
+#if LUN_4 == ENABLE
+  #include LUN_4_INCLUDE
+#endif
+#if LUN_5 == ENABLE
+  #include LUN_5_INCLUDE
+#endif
+#if LUN_6 == ENABLE
+  #include LUN_6_INCLUDE
+#endif
+#if LUN_7 == ENABLE
+  #include LUN_7_INCLUDE
+#endif
+#if LUN_USB == ENABLE
+  #include LUN_USB_INCLUDE
+#endif
+
+
+// Check the configuration of write protection in conf_access.h.
+#ifndef GLOBAL_WR_PROTECT
+  #error GLOBAL_WR_PROTECT must be defined as true or false in conf_access.h
+#endif
+
+
+#if GLOBAL_WR_PROTECT == true
+
+//! Write protect.
+extern bool g_wr_protect;
+
+#endif
+
+
+/*! \name Control Interface
+ */
+//! @{
+
+#ifdef FREERTOS_USED
+
+/*! \brief Initializes the LUN access locker.
+ *
+ * \return \c true if the locker was successfully initialized, else \c false.
+ */
+extern bool ctrl_access_init(void);
+
+#endif  // FREERTOS_USED
+
+/*! \brief Returns the number of LUNs.
+ *
+ * \return Number of LUNs in the system.
+ */
+extern U8 get_nb_lun(void);
+
+/*! \brief Returns the current LUN.
+ *
+ * \return Current LUN.
+ *
+ * \todo Implement.
+ */
+extern U8 get_cur_lun(void);
+
+/*! \brief Tests the memory state and initializes the memory if required.
+ *
+ * The TEST UNIT READY SCSI primary command allows an application client to poll
+ * a LUN until it is ready without having to allocate memory for returned data.
+ *
+ * This command may be used to check the media status of LUNs with removable
+ * media.
+ *
+ * \param lun Logical Unit Number.
+ *
+ * \return Status.
+ */
+extern Ctrl_status mem_test_unit_ready(U8 lun);
+
+/*! \brief Returns the address of the last valid sector (512 bytes) in the
+ *         memory.
+ *
+ * \param lun           Logical Unit Number.
+ * \param u32_nb_sector Pointer to the address of the last valid sector.
+ *
+ * \return Status.
+ */
+extern Ctrl_status mem_read_capacity(U8 lun, U32 *u32_nb_sector);
+
+/*! \brief Returns the size of the physical sector.
+ *
+ * \param lun Logical Unit Number.
+ *
+ * \return Sector size (unit: 512 bytes).
+ */
+extern U8 mem_sector_size(U8 lun);
+
+/*! \brief Unload/load the medium.
+ *
+ * \param lun Logical Unit Number.
+ * \param unload \c true to unload the medium, \c false to load the medium.
+ *
+ * \return \c true if unload/load success, else \c false.
+ */
+extern bool mem_unload(U8 lun, bool unload);
+
+/*! \brief Returns the write-protection state of the memory.
+ *
+ * \param lun Logical Unit Number.
+ *
+ * \return \c true if the memory is write-protected, else \c false.
+ *
+ * \note Only used by removable memories with hardware-specific write
+ *       protection.
+ */
+extern bool mem_wr_protect(U8 lun);
+
+/*! \brief Tells whether the memory is removable.
+ *
+ * \param lun Logical Unit Number.
+ *
+ * \return \c true if the memory is removable, else \c false.
+ */
+extern bool mem_removal(U8 lun);
+
+/*! \brief Returns a pointer to the LUN name.
+ *
+ * \param lun Logical Unit Number.
+ *
+ * \return Pointer to the LUN name string.
+ */
+extern const char *mem_name(U8 lun);
+
+//! @}
+
+
+#if ACCESS_USB == true
+
+/*! \name MEM <-> USB Interface
+ */
+//! @{
+
+/*! \brief Transfers data from the memory to USB.
+ *
+ * \param lun       Logical Unit Number.
+ * \param addr      Address of first memory sector to read.
+ * \param nb_sector Number of sectors to transfer.
+ *
+ * \return Status.
+ */
+extern Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector);
+
+/*! \brief Transfers data from USB to the memory.
+ *
+ * \param lun       Logical Unit Number.
+ * \param addr      Address of first memory sector to write.
+ * \param nb_sector Number of sectors to transfer.
+ *
+ * \return Status.
+ */
+extern Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector);
+
+//! @}
+
+#endif  // ACCESS_USB == true
+
+
+#if ACCESS_MEM_TO_RAM == true
+
+/*! \name MEM <-> RAM Interface
+ */
+//! @{
+
+/*! \brief Copies 1 data sector from the memory to RAM.
+ *
+ * \param lun   Logical Unit Number.
+ * \param addr  Address of first memory sector to read.
+ * \param ram   Pointer to RAM buffer to write.
+ *
+ * \return Status.
+ */
+extern Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram);
+
+/*! \brief Copies 1 data sector from RAM to the memory.
+ *
+ * \param lun   Logical Unit Number.
+ * \param addr  Address of first memory sector to write.
+ * \param ram   Pointer to RAM buffer to read.
+ *
+ * \return Status.
+ */
+extern Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram);
+
+//! @}
+
+#endif  // ACCESS_MEM_TO_RAM == true
+
+
+#if ACCESS_STREAM == true
+
+/*! \name Streaming MEM <-> MEM Interface
+ */
+//! @{
+
+//! Erroneous streaming data transfer ID.
+#define ID_STREAM_ERR         0xFF
+
+  #if ACCESS_MEM_TO_MEM == true
+
+/*! \brief Copies data from one memory to another.
+ *
+ * \param src_lun   Source Logical Unit Number.
+ * \param src_addr  Source address of first memory sector to read.
+ * \param dest_lun  Destination Logical Unit Number.
+ * \param dest_addr Destination address of first memory sector to write.
+ * \param nb_sector Number of sectors to copy.
+ *
+ * \return Status.
+ */
+extern Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_addr, U16 nb_sector);
+
+  #endif  // ACCESS_MEM_TO_MEM == true
+
+/*! \brief Returns the state of a streaming data transfer.
+ *
+ * \param id  Transfer ID.
+ *
+ * \return Status.
+ *
+ * \todo Implement.
+ */
+extern Ctrl_status stream_state(U8 id);
+
+/*! \brief Stops a streaming data transfer.
+ *
+ * \param id  Transfer ID.
+ *
+ * \return Number of remaining sectors.
+ *
+ * \todo Implement.
+ */
+extern U16 stream_stop(U8 id);
+
+//! @}
+
+#endif  // ACCESS_STREAM == true
+
+/**
+ * \}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // _CTRL_ACCESS_H_

asf/common/services/usb/class/cdc/device/udi_cdc.h

@@ -0,0 +1,810 @@
+/**
+ * \file
+ *
+ * \brief USB Device Communication Device Class (CDC) interface definitions.
+ *
+ * Copyright (c) 2009-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _UDI_CDC_H_
+#define _UDI_CDC_H_
+
+#include "conf_usb.h"
+#include "usb_protocol.h"
+#include "usb_protocol_cdc.h"
+#include "udd.h"
+#include "udc_desc.h"
+#include "udi.h"
+
+// Check the number of port
+#ifndef  UDI_CDC_PORT_NB
+# define  UDI_CDC_PORT_NB 1
+#endif
+#if (UDI_CDC_PORT_NB < 1) || (UDI_CDC_PORT_NB > 7)
+# error UDI_CDC_PORT_NB must be between 1 and 7
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup udi_cdc_group_udc
+ * @{
+ */
+
+//! Global structure which contains standard UDI API for UDC
+extern UDC_DESC_STORAGE udi_api_t udi_api_cdc_comm;
+extern UDC_DESC_STORAGE udi_api_t udi_api_cdc_data;
+//@}
+
+/**
+ * \ingroup udi_cdc_group
+ * \defgroup udi_cdc_group_desc USB interface descriptors
+ *
+ * The following structures provide predefined USB interface descriptors.
+ * It must be used to define the final USB descriptors.
+ */
+//@{
+
+/**
+ * \brief Communication Class interface descriptor
+ *
+ * Interface descriptor with associated functional and endpoint
+ * descriptors for the CDC Communication Class interface.
+ */
+typedef struct {
+	//! Standard interface descriptor
+	usb_iface_desc_t iface;
+	//! CDC Header functional descriptor
+	usb_cdc_hdr_desc_t header;
+	//! CDC Abstract Control Model functional descriptor
+	usb_cdc_acm_desc_t acm;
+	//! CDC Union functional descriptor
+	usb_cdc_union_desc_t union_desc;
+	//! CDC Call Management functional descriptor
+	usb_cdc_call_mgmt_desc_t call_mgmt;
+	//! Notification endpoint descriptor
+	usb_ep_desc_t ep_notify;
+} udi_cdc_comm_desc_t;
+
+
+/**
+ * \brief Data Class interface descriptor
+ *
+ * Interface descriptor with associated endpoint descriptors for the
+ * CDC Data Class interface.
+ */
+typedef struct {
+	//! Standard interface descriptor
+	usb_iface_desc_t iface;
+	//! Data IN/OUT endpoint descriptors
+	usb_ep_desc_t ep_in;
+	usb_ep_desc_t ep_out;
+} udi_cdc_data_desc_t;
+
+
+//! CDC communication endpoints size for all speeds
+#define UDI_CDC_COMM_EP_SIZE        64
+//! CDC data endpoints size for FS speed (8B, 16B, 32B, 64B)
+#define UDI_CDC_DATA_EPS_FS_SIZE    64
+//! CDC data endpoints size for HS speed (512B only)
+#define UDI_CDC_DATA_EPS_HS_SIZE    512
+
+/**
+ * \name Content of interface descriptors
+ * Up to 7 CDC interfaces can be implemented on a USB device.
+ */
+//@{
+//! By default no string associated to these interfaces
+#ifndef UDI_CDC_IAD_STRING_ID_0
+#define UDI_CDC_IAD_STRING_ID_0   0
+#endif
+#ifndef UDI_CDC_COMM_STRING_ID_0
+#define UDI_CDC_COMM_STRING_ID_0   0
+#endif
+#ifndef UDI_CDC_DATA_STRING_ID_0
+#define UDI_CDC_DATA_STRING_ID_0   0
+#endif
+#define UDI_CDC_IAD_DESC_0      UDI_CDC_IAD_DESC(0)
+#define UDI_CDC_COMM_DESC_0     UDI_CDC_COMM_DESC(0)
+#define UDI_CDC_DATA_DESC_0_FS  UDI_CDC_DATA_DESC_FS(0)
+#define UDI_CDC_DATA_DESC_0_HS  UDI_CDC_DATA_DESC_HS(0)
+
+//! By default no string associated to these interfaces
+#ifndef UDI_CDC_IAD_STRING_ID_1
+#define UDI_CDC_IAD_STRING_ID_1  0
+#endif
+#ifndef UDI_CDC_COMM_STRING_ID_1
+#define UDI_CDC_COMM_STRING_ID_1 0
+#endif
+#ifndef UDI_CDC_DATA_STRING_ID_1
+#define UDI_CDC_DATA_STRING_ID_1 0
+#endif
+#define UDI_CDC_IAD_DESC_1      UDI_CDC_IAD_DESC(1)
+#define UDI_CDC_COMM_DESC_1     UDI_CDC_COMM_DESC(1)
+#define UDI_CDC_DATA_DESC_1_FS  UDI_CDC_DATA_DESC_FS(1)
+#define UDI_CDC_DATA_DESC_1_HS  UDI_CDC_DATA_DESC_HS(1)
+
+//! By default no string associated to these interfaces
+#ifndef UDI_CDC_IAD_STRING_ID_2
+#define UDI_CDC_IAD_STRING_ID_2   0
+#endif
+#ifndef UDI_CDC_COMM_STRING_ID_2
+#define UDI_CDC_COMM_STRING_ID_2   0
+#endif
+#ifndef UDI_CDC_DATA_STRING_ID_2
+#define UDI_CDC_DATA_STRING_ID_2   0
+#endif
+#define UDI_CDC_IAD_DESC_2      UDI_CDC_IAD_DESC(2)
+#define UDI_CDC_COMM_DESC_2     UDI_CDC_COMM_DESC(2)
+#define UDI_CDC_DATA_DESC_2_FS  UDI_CDC_DATA_DESC_FS(2)
+#define UDI_CDC_DATA_DESC_2_HS  UDI_CDC_DATA_DESC_HS(2)
+
+//! By default no string associated to these interfaces
+#ifndef UDI_CDC_IAD_STRING_ID_3
+#define UDI_CDC_IAD_STRING_ID_3   0
+#endif
+#ifndef UDI_CDC_COMM_STRING_ID_3
+#define UDI_CDC_COMM_STRING_ID_3   0
+#endif
+#ifndef UDI_CDC_DATA_STRING_ID_3
+#define UDI_CDC_DATA_STRING_ID_3   0
+#endif
+#define UDI_CDC_IAD_DESC_3      UDI_CDC_IAD_DESC(3)
+#define UDI_CDC_COMM_DESC_3     UDI_CDC_COMM_DESC(3)
+#define UDI_CDC_DATA_DESC_3_FS  UDI_CDC_DATA_DESC_FS(3)
+#define UDI_CDC_DATA_DESC_3_HS  UDI_CDC_DATA_DESC_HS(3)
+
+//! By default no string associated to these interfaces
+#ifndef UDI_CDC_IAD_STRING_ID_4
+#define UDI_CDC_IAD_STRING_ID_4   0
+#endif
+#ifndef UDI_CDC_COMM_STRING_ID_4
+#define UDI_CDC_COMM_STRING_ID_4   0
+#endif
+#ifndef UDI_CDC_DATA_STRING_ID_4
+#define UDI_CDC_DATA_STRING_ID_4   0
+#endif
+#define UDI_CDC_IAD_DESC_4      UDI_CDC_IAD_DESC(4)
+#define UDI_CDC_COMM_DESC_4     UDI_CDC_COMM_DESC(4)
+#define UDI_CDC_DATA_DESC_4_FS  UDI_CDC_DATA_DESC_FS(4)
+#define UDI_CDC_DATA_DESC_4_HS  UDI_CDC_DATA_DESC_HS(4)
+
+//! By default no string associated to these interfaces
+#ifndef UDI_CDC_IAD_STRING_ID_5
+#define UDI_CDC_IAD_STRING_ID_5   0
+#endif
+#ifndef UDI_CDC_COMM_STRING_ID_5
+#define UDI_CDC_COMM_STRING_ID_5   0
+#endif
+#ifndef UDI_CDC_DATA_STRING_ID_5
+#define UDI_CDC_DATA_STRING_ID_5   0
+#endif
+#define UDI_CDC_IAD_DESC_5      UDI_CDC_IAD_DESC(5)
+#define UDI_CDC_COMM_DESC_5     UDI_CDC_COMM_DESC(5)
+#define UDI_CDC_DATA_DESC_5_FS  UDI_CDC_DATA_DESC_FS(5)
+#define UDI_CDC_DATA_DESC_5_HS  UDI_CDC_DATA_DESC_HS(5)
+
+//! By default no string associated to these interfaces
+#ifndef UDI_CDC_IAD_STRING_ID_6
+#define UDI_CDC_IAD_STRING_ID_6   0
+#endif
+#ifndef UDI_CDC_COMM_STRING_ID_6
+#define UDI_CDC_COMM_STRING_ID_6   0
+#endif
+#ifndef UDI_CDC_DATA_STRING_ID_6
+#define UDI_CDC_DATA_STRING_ID_6   0
+#endif
+#define UDI_CDC_IAD_DESC_6      UDI_CDC_IAD_DESC(6)
+#define UDI_CDC_COMM_DESC_6     UDI_CDC_COMM_DESC(6)
+#define UDI_CDC_DATA_DESC_6_FS  UDI_CDC_DATA_DESC_FS(6)
+#define UDI_CDC_DATA_DESC_6_HS  UDI_CDC_DATA_DESC_HS(6)
+//@}
+
+
+//! Content of CDC IAD interface descriptor for all speeds
+#define UDI_CDC_IAD_DESC(port) { \
+   .bLength                      = sizeof(usb_iad_desc_t),\
+   .bDescriptorType              = USB_DT_IAD,\
+   .bInterfaceCount              = 2,\
+   .bFunctionClass               = CDC_CLASS_COMM,\
+   .bFunctionSubClass            = CDC_SUBCLASS_ACM,\
+   .bFunctionProtocol            = CDC_PROTOCOL_V25TER,\
+   .bFirstInterface              = UDI_CDC_COMM_IFACE_NUMBER_##port,\
+   .iFunction                    = UDI_CDC_IAD_STRING_ID_##port,\
+   }
+
+//! Content of CDC COMM interface descriptor for all speeds
+#define UDI_CDC_COMM_DESC(port) { \
+   .iface.bLength                = sizeof(usb_iface_desc_t),\
+   .iface.bDescriptorType        = USB_DT_INTERFACE,\
+   .iface.bAlternateSetting      = 0,\
+   .iface.bNumEndpoints          = 1,\
+   .iface.bInterfaceClass        = CDC_CLASS_COMM,\
+   .iface.bInterfaceSubClass     = CDC_SUBCLASS_ACM,\
+   .iface.bInterfaceProtocol     = CDC_PROTOCOL_V25TER,\
+   .header.bFunctionLength       = sizeof(usb_cdc_hdr_desc_t),\
+   .header.bDescriptorType       = CDC_CS_INTERFACE,\
+   .header.bDescriptorSubtype    = CDC_SCS_HEADER,\
+   .header.bcdCDC                = LE16(0x0110),\
+   .call_mgmt.bFunctionLength    = sizeof(usb_cdc_call_mgmt_desc_t),\
+   .call_mgmt.bDescriptorType    = CDC_CS_INTERFACE,\
+   .call_mgmt.bDescriptorSubtype = CDC_SCS_CALL_MGMT,\
+   .call_mgmt.bmCapabilities     = \
+			CDC_CALL_MGMT_SUPPORTED | CDC_CALL_MGMT_OVER_DCI,\
+   .acm.bFunctionLength          = sizeof(usb_cdc_acm_desc_t),\
+   .acm.bDescriptorType          = CDC_CS_INTERFACE,\
+   .acm.bDescriptorSubtype       = CDC_SCS_ACM,\
+   .acm.bmCapabilities           = CDC_ACM_SUPPORT_LINE_REQUESTS,\
+   .union_desc.bFunctionLength   = sizeof(usb_cdc_union_desc_t),\
+   .union_desc.bDescriptorType   = CDC_CS_INTERFACE,\
+   .union_desc.bDescriptorSubtype= CDC_SCS_UNION,\
+   .ep_notify.bLength            = sizeof(usb_ep_desc_t),\
+   .ep_notify.bDescriptorType    = USB_DT_ENDPOINT,\
+   .ep_notify.bmAttributes       = USB_EP_TYPE_INTERRUPT,\
+   .ep_notify.wMaxPacketSize     = LE16(UDI_CDC_COMM_EP_SIZE),\
+   .ep_notify.bInterval          = 0x10,\
+   .ep_notify.bEndpointAddress   = UDI_CDC_COMM_EP_##port,\
+   .iface.bInterfaceNumber       = UDI_CDC_COMM_IFACE_NUMBER_##port,\
+   .call_mgmt.bDataInterface     = UDI_CDC_DATA_IFACE_NUMBER_##port,\
+   .union_desc.bMasterInterface  = UDI_CDC_COMM_IFACE_NUMBER_##port,\
+   .union_desc.bSlaveInterface0  = UDI_CDC_DATA_IFACE_NUMBER_##port,\
+   .iface.iInterface             = UDI_CDC_COMM_STRING_ID_##port,\
+   }
+
+//! Content of CDC DATA interface descriptors
+#define UDI_CDC_DATA_DESC_COMMON \
+   .iface.bLength                = sizeof(usb_iface_desc_t),\
+   .iface.bDescriptorType        = USB_DT_INTERFACE,\
+   .iface.bAlternateSetting      = 0,\
+   .iface.bNumEndpoints          = 2,\
+   .iface.bInterfaceClass        = CDC_CLASS_DATA,\
+   .iface.bInterfaceSubClass     = 0,\
+   .iface.bInterfaceProtocol     = 0,\
+   .ep_in.bLength                = sizeof(usb_ep_desc_t),\
+   .ep_in.bDescriptorType        = USB_DT_ENDPOINT,\
+   .ep_in.bmAttributes           = USB_EP_TYPE_BULK,\
+   .ep_in.bInterval              = 0,\
+   .ep_out.bLength               = sizeof(usb_ep_desc_t),\
+   .ep_out.bDescriptorType       = USB_DT_ENDPOINT,\
+   .ep_out.bmAttributes          = USB_EP_TYPE_BULK,\
+   .ep_out.bInterval             = 0,
+
+#define UDI_CDC_DATA_DESC_FS(port) { \
+   UDI_CDC_DATA_DESC_COMMON \
+   .ep_in.wMaxPacketSize         = LE16(UDI_CDC_DATA_EPS_FS_SIZE),\
+   .ep_out.wMaxPacketSize        = LE16(UDI_CDC_DATA_EPS_FS_SIZE),\
+   .ep_in.bEndpointAddress       = UDI_CDC_DATA_EP_IN_##port,\
+   .ep_out.bEndpointAddress      = UDI_CDC_DATA_EP_OUT_##port,\
+   .iface.bInterfaceNumber       = UDI_CDC_DATA_IFACE_NUMBER_##port,\
+   .iface.iInterface             = UDI_CDC_DATA_STRING_ID_##port,\
+   }
+
+#define UDI_CDC_DATA_DESC_HS(port) { \
+   UDI_CDC_DATA_DESC_COMMON \
+   .ep_in.wMaxPacketSize         = LE16(UDI_CDC_DATA_EPS_HS_SIZE),\
+   .ep_out.wMaxPacketSize        = LE16(UDI_CDC_DATA_EPS_HS_SIZE),\
+   .ep_in.bEndpointAddress       = UDI_CDC_DATA_EP_IN_##port,\
+   .ep_out.bEndpointAddress      = UDI_CDC_DATA_EP_OUT_##port,\
+   .iface.bInterfaceNumber       = UDI_CDC_DATA_IFACE_NUMBER_##port,\
+   .iface.iInterface             = UDI_CDC_DATA_STRING_ID_##port,\
+   }
+
+//@}
+
+/**
+ * \ingroup udi_group
+ * \defgroup udi_cdc_group USB Device Interface (UDI) for Communication Class Device (CDC)
+ *
+ * Common APIs used by high level application to use this USB class.
+ *
+ * These routines are used to transfer and control data
+ * to/from USB CDC endpoint.
+ *
+ * See \ref udi_cdc_quickstart.
+ * @{
+ */
+
+/**
+ * \name Interface for application with single CDC interface support
+ */
+//@{
+
+/**
+ * \brief Notify a state change of DCD signal
+ *
+ * \param b_set      DCD is enabled if true, else disabled
+ */
+void udi_cdc_ctrl_signal_dcd(bool b_set);
+
+/**
+ * \brief Notify a state change of DSR signal
+ *
+ * \param b_set      DSR is enabled if true, else disabled
+ */
+void udi_cdc_ctrl_signal_dsr(bool b_set);
+
+/**
+ * \brief Notify a framing error
+ */
+void udi_cdc_signal_framing_error(void);
+
+/**
+ * \brief Notify a parity error
+ */
+void udi_cdc_signal_parity_error(void);
+
+/**
+ * \brief Notify a overrun
+ */
+void udi_cdc_signal_overrun(void);
+
+/**
+ * \brief Gets the number of byte received
+ *
+ * \return the number of data available
+ */
+iram_size_t udi_cdc_get_nb_received_data(void);
+
+/**
+ * \brief This function checks if a character has been received on the CDC line
+ *
+ * \return \c 1 if a byte is ready to be read.
+ */
+bool udi_cdc_is_rx_ready(void);
+
+/**
+ * \brief Waits and gets a value on CDC line
+ *
+ * \return value read on CDC line
+ */
+int udi_cdc_getc(void);
+
+/**
+ * \brief Reads a RAM buffer on CDC line
+ *
+ * \param buf       Values read
+ * \param size      Number of value read
+ *
+ * \return the number of data remaining
+ */
+iram_size_t udi_cdc_read_buf(void* buf, iram_size_t size);
+
+/**
+ * \brief Non polling reads of a up to 'size' data from CDC line
+ *
+ * \param port      Communication port number to manage
+ * \param buf       Buffer where to store read data
+ * \param size      Maximum number of data to read (size of buffer)
+ *
+ * \return the number of data effectively read
+ */
+iram_size_t udi_cdc_read_no_polling(void* buf, iram_size_t size);
+
+/**
+ * \brief Gets the number of free byte in TX buffer
+ *
+ * \return the number of free byte in TX buffer
+ */
+iram_size_t udi_cdc_get_free_tx_buffer(void);
+
+/**
+ * \brief This function checks if a new character sent is possible
+ * The type int is used to support scanf redirection from compiler LIB.
+ *
+ * \return \c 1 if a new character can be sent
+ */
+bool udi_cdc_is_tx_ready(void);
+
+/**
+ * \brief Puts a byte on CDC line
+ * The type int is used to support printf redirection from compiler LIB.
+ *
+ * \param value      Value to put
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+int udi_cdc_putc(int value);
+
+/**
+ * \brief Writes a RAM buffer on CDC line
+ *
+ * \param buf       Values to write
+ * \param size      Number of value to write
+ *
+ * \return the number of data remaining
+ */
+iram_size_t udi_cdc_write_buf(const void* buf, iram_size_t size);
+//@}
+
+/**
+ * \name Interface for application with multi CDC interfaces support
+ */
+//@{
+
+/**
+ * \brief Notify a state change of DCD signal
+ *
+ * \param port       Communication port number to manage
+ * \param b_set      DCD is enabled if true, else disabled
+ */
+void udi_cdc_multi_ctrl_signal_dcd(uint8_t port, bool b_set);
+
+/**
+ * \brief Notify a state change of DSR signal
+ *
+ * \param port       Communication port number to manage
+ * \param b_set      DSR is enabled if true, else disabled
+ */
+void udi_cdc_multi_ctrl_signal_dsr(uint8_t port, bool b_set);
+
+/**
+ * \brief Notify a framing error
+ *
+ * \param port       Communication port number to manage
+ */
+void udi_cdc_multi_signal_framing_error(uint8_t port);
+
+/**
+ * \brief Notify a parity error
+ *
+ * \param port       Communication port number to manage
+ */
+void udi_cdc_multi_signal_parity_error(uint8_t port);
+
+/**
+ * \brief Notify a overrun
+ *
+ * \param port       Communication port number to manage
+ */
+void udi_cdc_multi_signal_overrun(uint8_t port);
+
+/**
+ * \brief Gets the number of byte received
+ *
+ * \param port       Communication port number to manage
+ *
+ * \return the number of data available
+ */
+iram_size_t udi_cdc_multi_get_nb_received_data(uint8_t port);
+
+/**
+ * \brief This function checks if a character has been received on the CDC line
+ *
+ * \param port       Communication port number to manage
+ *
+ * \return \c 1 if a byte is ready to be read.
+ */
+bool udi_cdc_multi_is_rx_ready(uint8_t port);
+
+/**
+ * \brief Waits and gets a value on CDC line
+ *
+ * \param port       Communication port number to manage
+ *
+ * \return value read on CDC line
+ */
+int udi_cdc_multi_getc(uint8_t port);
+
+/**
+ * \brief Reads a RAM buffer on CDC line
+ *
+ * \param port       Communication port number to manage
+ * \param buf       Values read
+ * \param size      Number of values read
+ *
+ * \return the number of data remaining
+ */
+iram_size_t udi_cdc_multi_read_buf(uint8_t port, void* buf, iram_size_t size);
+
+/**
+ * \brief Gets the number of free byte in TX buffer
+ *
+ * \param port       Communication port number to manage
+ *
+ * \return the number of free byte in TX buffer
+ */
+iram_size_t udi_cdc_multi_get_free_tx_buffer(uint8_t port);
+
+/**
+ * \brief This function checks if a new character sent is possible
+ * The type int is used to support scanf redirection from compiler LIB.
+ *
+ * \param port       Communication port number to manage
+ *
+ * \return \c 1 if a new character can be sent
+ */
+bool udi_cdc_multi_is_tx_ready(uint8_t port);
+
+/**
+ * \brief Puts a byte on CDC line
+ * The type int is used to support printf redirection from compiler LIB.
+ *
+ * \param port       Communication port number to manage
+ * \param value      Value to put
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+int udi_cdc_multi_putc(uint8_t port, int value);
+
+/**
+ * \brief Writes a RAM buffer on CDC line
+ *
+ * \param port       Communication port number to manage
+ * \param buf       Values to write
+ * \param size      Number of value to write
+ *
+ * \return the number of data remaining
+ */
+iram_size_t udi_cdc_multi_write_buf(uint8_t port, const void* buf, iram_size_t size);
+//@}
+
+//@}
+
+/**
+ * \page udi_cdc_quickstart Quick start guide for USB device Communication Class Device module (UDI CDC)
+ *
+ * This is the quick start guide for the \ref udi_cdc_group
+ * "USB device interface CDC module (UDI CDC)" with step-by-step instructions on
+ * how to configure and use the modules in a selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section udi_cdc_basic_use_case Basic use case
+ * In this basic use case, the "USB CDC (Single Interface Device)" module is used
+ * with only one communication port.
+ * The "USB CDC (Composite Device)" module usage is described in \ref udi_cdc_use_cases
+ * "Advanced use cases".
+ *
+ * \section udi_cdc_basic_use_case_setup Setup steps
+ * \subsection udi_cdc_basic_use_case_setup_prereq Prerequisites
+ * \copydetails udc_basic_use_case_setup_prereq
+ * \subsection udi_cdc_basic_use_case_setup_code Example code
+ * \copydetails udc_basic_use_case_setup_code
+ * \subsection udi_cdc_basic_use_case_setup_flow Workflow
+ * \copydetails udc_basic_use_case_setup_flow
+ *
+ * \section udi_cdc_basic_use_case_usage Usage steps
+ *
+ * \subsection udi_cdc_basic_use_case_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+	 #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable()
+	 extern bool my_callback_cdc_enable(void);
+	 #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable()
+	 extern void my_callback_cdc_disable(void);
+	 #define  UDI_CDC_LOW_RATE
+
+	 #define  UDI_CDC_DEFAULT_RATE             115200
+	 #define  UDI_CDC_DEFAULT_STOPBITS         CDC_STOP_BITS_1
+	 #define  UDI_CDC_DEFAULT_PARITY           CDC_PAR_NONE
+	 #define  UDI_CDC_DEFAULT_DATABITS         8
+
+	 #include "udi_cdc_conf.h" // At the end of conf_usb.h file
+\endcode
+ *
+ * Add to application C-file:
+ * \code
+	 static bool my_flag_autorize_cdc_transfert = false;
+	 bool my_callback_cdc_enable(void)
+	 {
+	    my_flag_autorize_cdc_transfert = true;
+	    return true;
+	 }
+	 void my_callback_cdc_disable(void)
+	 {
+	    my_flag_autorize_cdc_transfert = false;
+	 }
+
+	 void task(void)
+	 {
+	    if (my_flag_autorize_cdc_transfert) {
+	        udi_cdc_putc('A');
+	        udi_cdc_getc();
+	    }
+	 }
+\endcode
+ *
+ * \subsection udi_cdc_basic_use_case_setup_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following configuration,
+ * which is the USB device CDC configuration:
+ *   - \code #define USB_DEVICE_SERIAL_NAME  "12...EF" // Disk SN for CDC \endcode
+ *     \note The USB serial number is mandatory when a CDC interface is used.
+ *   - \code #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable()
+	 extern bool my_callback_cdc_enable(void); \endcode
+ *     \note After the device enumeration (detecting and identifying USB devices),
+ *     the USB host starts the device configuration. When the USB CDC interface
+ *     from the device is accepted by the host, the USB host enables this interface and the
+ *     UDI_CDC_ENABLE_EXT() callback function is called and return true.
+ *     Thus, when this event is received, the data transfer on CDC interface are authorized.
+ *   - \code #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable()
+	 extern void my_callback_cdc_disable(void); \endcode
+ *     \note When the USB device is unplugged or is reset by the USB host, the USB
+ *     interface is disabled and the UDI_CDC_DISABLE_EXT() callback function
+ *     is called. Thus, the data transfer must be stopped on CDC interface.
+ *   - \code #define  UDI_CDC_LOW_RATE \endcode
+ *     \note  Define it when the transfer CDC Device to Host is a low rate
+ *     (<512000 bauds) to reduce CDC buffers size.
+ *   - \code #define  UDI_CDC_DEFAULT_RATE             115200
+	#define  UDI_CDC_DEFAULT_STOPBITS         CDC_STOP_BITS_1
+	#define  UDI_CDC_DEFAULT_PARITY           CDC_PAR_NONE
+	#define  UDI_CDC_DEFAULT_DATABITS         8 \endcode
+ *     \note Default configuration of communication port at startup.
+ * -# Send or wait data on CDC line:
+ *   - \code // Waits and gets a value on CDC line
+	int udi_cdc_getc(void);
+	// Reads a RAM buffer on CDC line
+	iram_size_t udi_cdc_read_buf(int* buf, iram_size_t size);
+	// Puts a byte on CDC line
+	int udi_cdc_putc(int value);
+	// Writes a RAM buffer on CDC line
+	iram_size_t udi_cdc_write_buf(const int* buf, iram_size_t size); \endcode
+ *
+ * \section udi_cdc_use_cases Advanced use cases
+ * For more advanced use of the UDI CDC module, see the following use cases:
+ * - \subpage udi_cdc_use_case_composite
+ * - \subpage udc_use_case_1
+ * - \subpage udc_use_case_2
+ * - \subpage udc_use_case_3
+ * - \subpage udc_use_case_4
+ * - \subpage udc_use_case_5
+ * - \subpage udc_use_case_6
+ */
+
+/**
+ * \page udi_cdc_use_case_composite CDC in a composite device
+ *
+ * A USB Composite Device is a USB Device which uses more than one USB class.
+ * In this use case, the "USB CDC (Composite Device)" module is used to
+ * create a USB composite device. Thus, this USB module can be associated with
+ * another "Composite Device" module, like "USB HID Mouse (Composite Device)".
+ *
+ * Also, you can refer to application note
+ * <A href="http://www.atmel.com/dyn/resources/prod_documents/doc8445.pdf">
+ * AVR4902 ASF - USB Composite Device</A>.
+ *
+ * \section udi_cdc_use_case_composite_setup Setup steps
+ * For the setup code of this use case to work, the
+ * \ref udi_cdc_basic_use_case "basic use case" must be followed.
+ *
+ * \section udi_cdc_use_case_composite_usage Usage steps
+ *
+ * \subsection udi_cdc_use_case_composite_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+	 #define USB_DEVICE_EP_CTRL_SIZE  64
+	 #define USB_DEVICE_NB_INTERFACE (X+2)
+	 #define USB_DEVICE_MAX_EP (X+3)
+
+	 #define  UDI_CDC_DATA_EP_IN_0          (1 | USB_EP_DIR_IN)  // TX
+	 #define  UDI_CDC_DATA_EP_OUT_0         (2 | USB_EP_DIR_OUT) // RX
+	 #define  UDI_CDC_COMM_EP_0             (3 | USB_EP_DIR_IN)  // Notify endpoint
+	 #define  UDI_CDC_COMM_IFACE_NUMBER_0   X+0
+	 #define  UDI_CDC_DATA_IFACE_NUMBER_0   X+1
+
+	 #define UDI_COMPOSITE_DESC_T \
+	    usb_iad_desc_t udi_cdc_iad; \
+	    udi_cdc_comm_desc_t udi_cdc_comm; \
+	    udi_cdc_data_desc_t udi_cdc_data; \
+	    ...
+	 #define UDI_COMPOSITE_DESC_FS \
+	    .udi_cdc_iad               = UDI_CDC_IAD_DESC_0, \
+	    .udi_cdc_comm              = UDI_CDC_COMM_DESC_0, \
+	    .udi_cdc_data              = UDI_CDC_DATA_DESC_0_FS, \
+	    ...
+	 #define UDI_COMPOSITE_DESC_HS \
+	    .udi_cdc_iad               = UDI_CDC_IAD_DESC_0, \
+	    .udi_cdc_comm              = UDI_CDC_COMM_DESC_0, \
+	    .udi_cdc_data              = UDI_CDC_DATA_DESC_0_HS, \
+	    ...
+	 #define UDI_COMPOSITE_API \
+	    &udi_api_cdc_comm,       \
+	    &udi_api_cdc_data,       \
+	    ...
+\endcode
+ *
+ * \subsection udi_cdc_use_case_composite_usage_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following parameters
+ * required for a USB composite device configuration:
+ *   - \code // Endpoint control size, This must be:
+	// - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM)
+	// - 64 for a high speed device
+	#define USB_DEVICE_EP_CTRL_SIZE  64
+	// Total Number of interfaces on this USB device.
+	// Add 2 for CDC.
+	#define USB_DEVICE_NB_INTERFACE (X+2)
+	// Total number of endpoints on this USB device.
+	// This must include each endpoint for each interface.
+	// Add 3 for CDC.
+	#define USB_DEVICE_MAX_EP (X+3) \endcode
+ * -# Ensure that conf_usb.h contains the description of
+ * composite device:
+ *   - \code // The endpoint numbers chosen by you for the CDC.
+	// The endpoint numbers starting from 1.
+	#define  UDI_CDC_DATA_EP_IN_0            (1 | USB_EP_DIR_IN)  // TX
+	#define  UDI_CDC_DATA_EP_OUT_0           (2 | USB_EP_DIR_OUT) // RX
+	#define  UDI_CDC_COMM_EP_0               (3 | USB_EP_DIR_IN)  // Notify endpoint
+	// The interface index of an interface starting from 0
+	#define  UDI_CDC_COMM_IFACE_NUMBER_0     X+0
+	#define  UDI_CDC_DATA_IFACE_NUMBER_0     X+1 \endcode
+ * -# Ensure that conf_usb.h contains the following parameters
+ * required for a USB composite device configuration:
+ *   - \code // USB Interfaces descriptor structure
+	#define UDI_COMPOSITE_DESC_T \
+	   ...
+	   usb_iad_desc_t udi_cdc_iad; \
+	   udi_cdc_comm_desc_t udi_cdc_comm; \
+	   udi_cdc_data_desc_t udi_cdc_data; \
+	   ...
+	// USB Interfaces descriptor value for Full Speed
+	#define UDI_COMPOSITE_DESC_FS \
+	   ...
+	   .udi_cdc_iad               = UDI_CDC_IAD_DESC_0, \
+	   .udi_cdc_comm              = UDI_CDC_COMM_DESC_0, \
+	   .udi_cdc_data              = UDI_CDC_DATA_DESC_0_FS, \
+	   ...
+	// USB Interfaces descriptor value for High Speed
+	#define UDI_COMPOSITE_DESC_HS \
+	   ...
+	   .udi_cdc_iad               = UDI_CDC_IAD_DESC_0, \
+	   .udi_cdc_comm              = UDI_CDC_COMM_DESC_0, \
+	   .udi_cdc_data              = UDI_CDC_DATA_DESC_0_HS, \
+	   ...
+	// USB Interface APIs
+	#define UDI_COMPOSITE_API \
+	   ...
+	   &udi_api_cdc_comm,       \
+	   &udi_api_cdc_data,       \
+	   ... \endcode
+ *   - \note The descriptors order given in the four lists above must be the
+ *     same as the order defined by all interface indexes. The interface index
+ *     orders are defined through UDI_X_IFACE_NUMBER defines.\n
+ *     Also, the CDC requires a USB Interface Association Descriptor (IAD) for
+ *     composite device.
+ */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // _UDI_CDC_H_

asf/common/services/usb/class/cdc/device/udi_cdc_conf.h

@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Default CDC configuration for a USB Device with a single interface
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _UDI_CDC_CONF_H_
+#define _UDI_CDC_CONF_H_
+
+#include "usb_protocol_cdc.h"
+#include "conf_usb.h"
+
+#ifndef  UDI_CDC_PORT_NB
+# define  UDI_CDC_PORT_NB 1
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup udi_cdc_group_single_desc
+ * @{
+ */
+
+//! Control endpoint size (Endpoint 0)
+#define  USB_DEVICE_EP_CTRL_SIZE       64
+
+#if XMEGA
+/**
+ * \name Endpoint configuration on XMEGA
+ * The XMEGA supports a IN and OUT endpoint with the same number endpoint,
+ * thus XMEGA can support up to 7 CDC interfaces.
+ */
+//@{
+#define  UDI_CDC_DATA_EP_IN_0          ( 1 | USB_EP_DIR_IN)  // TX
+#define  UDI_CDC_DATA_EP_OUT_0         ( 2 | USB_EP_DIR_OUT) // RX
+#define  UDI_CDC_COMM_EP_0             ( 2 | USB_EP_DIR_IN)  // Notify endpoint
+#define  UDI_CDC_DATA_EP_IN_1          ( 3 | USB_EP_DIR_IN)  // TX
+#define  UDI_CDC_DATA_EP_OUT_1         ( 4 | USB_EP_DIR_OUT) // RX
+#define  UDI_CDC_COMM_EP_1             ( 4 | USB_EP_DIR_IN)  // Notify endpoint
+#define  UDI_CDC_DATA_EP_IN_2          ( 5 | USB_EP_DIR_IN)  // TX
+#define  UDI_CDC_DATA_EP_OUT_2         ( 6 | USB_EP_DIR_OUT) // RX
+#define  UDI_CDC_COMM_EP_2             ( 6 | USB_EP_DIR_IN)  // Notify endpoint
+#define  UDI_CDC_DATA_EP_IN_3          ( 7 | USB_EP_DIR_IN)  // TX
+#define  UDI_CDC_DATA_EP_OUT_3         ( 8 | USB_EP_DIR_OUT) // RX
+#define  UDI_CDC_COMM_EP_3             ( 8 | USB_EP_DIR_IN)  // Notify endpoint
+#define  UDI_CDC_DATA_EP_IN_4          ( 9 | USB_EP_DIR_IN)  // TX
+#define  UDI_CDC_DATA_EP_OUT_4         (10 | USB_EP_DIR_OUT) // RX
+#define  UDI_CDC_COMM_EP_4             (10 | USB_EP_DIR_IN)  // Notify endpoint
+#define  UDI_CDC_DATA_EP_IN_5          (11 | USB_EP_DIR_IN)  // TX
+#define  UDI_CDC_DATA_EP_OUT_5         (12 | USB_EP_DIR_OUT) // RX
+#define  UDI_CDC_COMM_EP_5             (12 | USB_EP_DIR_IN)  // Notify endpoint
+#define  UDI_CDC_DATA_EP_IN_6          (13 | USB_EP_DIR_IN)  // TX
+#define  UDI_CDC_DATA_EP_OUT_6         (14 | USB_EP_DIR_OUT) // RX
+#define  UDI_CDC_COMM_EP_6             (14 | USB_EP_DIR_IN)  // Notify endpoint
+//! 2 endpoints numbers used per CDC interface
+#define  USB_DEVICE_MAX_EP             (2*UDI_CDC_PORT_NB)
+//@}
+
+#else
+
+/**
+ * \name Default endpoint configuration
+ * The USBB, UDP, UDPHS and UOTGHS interfaces can support up to 2 CDC interfaces.
+ */
+//@{
+#  if UDI_CDC_PORT_NB > 2
+#    error USBB, UDP, UDPHS and UOTGHS interfaces have not enought endpoints.
+#  endif
+#define  UDI_CDC_DATA_EP_IN_0          (1 | USB_EP_DIR_IN)  // TX
+#define  UDI_CDC_DATA_EP_OUT_0         (2 | USB_EP_DIR_OUT) // RX
+#define  UDI_CDC_COMM_EP_0             (3 | USB_EP_DIR_IN)  // Notify endpoint
+#  if SAM3U
+     /* For 3U max endpoint size of 4 is 64, use 5 and 6 as bulk tx and rx */
+#    define  UDI_CDC_DATA_EP_IN_1          (6 | USB_EP_DIR_IN)  // TX
+#    define  UDI_CDC_DATA_EP_OUT_1         (5 | USB_EP_DIR_OUT) // RX
+#    define  UDI_CDC_COMM_EP_1             (4 | USB_EP_DIR_IN)  // Notify
+#  else
+#    define  UDI_CDC_DATA_EP_IN_1          (4 | USB_EP_DIR_IN)  // TX
+#    define  UDI_CDC_DATA_EP_OUT_1         (5 | USB_EP_DIR_OUT) // RX
+#    define  UDI_CDC_COMM_EP_1             (6 | USB_EP_DIR_IN)  // Notify
+#  endif
+//! 3 endpoints used per CDC interface
+#undef USB_DEVICE_MAX_EP   // undefine this definition in header file
+#define  USB_DEVICE_MAX_EP             (3*UDI_CDC_PORT_NB)
+//@}
+
+#endif
+
+/**
+ * \name Default Interface numbers
+ */
+//@{
+#define  UDI_CDC_COMM_IFACE_NUMBER_0   0
+#define  UDI_CDC_DATA_IFACE_NUMBER_0   1
+#define  UDI_CDC_COMM_IFACE_NUMBER_1   2
+#define  UDI_CDC_DATA_IFACE_NUMBER_1   3
+#define  UDI_CDC_COMM_IFACE_NUMBER_2   4
+#define  UDI_CDC_DATA_IFACE_NUMBER_2   5
+#define  UDI_CDC_COMM_IFACE_NUMBER_3   6
+#define  UDI_CDC_DATA_IFACE_NUMBER_3   7
+#define  UDI_CDC_COMM_IFACE_NUMBER_4   8
+#define  UDI_CDC_DATA_IFACE_NUMBER_4   9
+#define  UDI_CDC_COMM_IFACE_NUMBER_5   10
+#define  UDI_CDC_DATA_IFACE_NUMBER_5   11
+#define  UDI_CDC_COMM_IFACE_NUMBER_6   12
+#define  UDI_CDC_DATA_IFACE_NUMBER_6   13
+//@}
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+#endif // _UDI_CDC_CONF_H_

asf/common/services/usb/class/cdc/device/udi_cdc_desc.c

@@ -0,0 +1,254 @@
+/**
+ * \file
+ *
+ * \brief Default descriptors for a USB Device with a single interface CDC
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "conf_usb.h"
+#include "udd.h"
+#include "udc_desc.h"
+#include "udi_cdc.h"
+
+
+/**
+ * \defgroup udi_cdc_group_single_desc USB device descriptors for a single interface
+ *
+ * The following structures provide the USB device descriptors required for
+ * USB Device with a single interface CDC.
+ *
+ * It is ready to use and do not require more definition.
+ *
+ * @{
+ */
+
+//! Two interfaces for a CDC device
+#define  USB_DEVICE_NB_INTERFACE       (2*UDI_CDC_PORT_NB)
+
+#ifdef USB_DEVICE_LPM_SUPPORT
+# define USB_VERSION   USB_V2_1
+#else
+# define USB_VERSION   USB_V2_0
+#endif
+
+//! USB Device Descriptor
+COMPILER_WORD_ALIGNED
+UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc = {
+	.bLength                   = sizeof(usb_dev_desc_t),
+	.bDescriptorType           = USB_DT_DEVICE,
+	.bcdUSB                    = LE16(USB_VERSION),
+#if UDI_CDC_PORT_NB > 1
+	.bDeviceClass              = 0,
+#else
+	.bDeviceClass              = CDC_CLASS_DEVICE,
+#endif
+	.bDeviceSubClass           = 0,
+	.bDeviceProtocol           = 0,
+	.bMaxPacketSize0           = USB_DEVICE_EP_CTRL_SIZE,
+	.idVendor                  = LE16(USB_DEVICE_VENDOR_ID),
+	.idProduct                 = LE16(USB_DEVICE_PRODUCT_ID),
+	.bcdDevice                 = LE16((USB_DEVICE_MAJOR_VERSION << 8)
+			| USB_DEVICE_MINOR_VERSION),
+#ifdef USB_DEVICE_MANUFACTURE_NAME
+	.iManufacturer = 1,
+#else
+	.iManufacturer             = 0,  // No manufacture string
+#endif
+#ifdef USB_DEVICE_PRODUCT_NAME
+	.iProduct = 2,
+#else
+	.iProduct                  = 0,  // No product string
+#endif
+#ifdef USB_DEVICE_SERIAL_NAME
+	.iSerialNumber = 3,
+#else
+	.iSerialNumber             = 0,  // No serial string
+#endif
+	.bNumConfigurations = 1
+};
+
+
+#ifdef USB_DEVICE_HS_SUPPORT
+//! USB Device Qualifier Descriptor for HS
+COMPILER_WORD_ALIGNED
+UDC_DESC_STORAGE usb_dev_qual_desc_t udc_device_qual = {
+	.bLength                   = sizeof(usb_dev_qual_desc_t),
+	.bDescriptorType           = USB_DT_DEVICE_QUALIFIER,
+	.bcdUSB                    = LE16(USB_VERSION),
+#if UDI_CDC_PORT_NB > 1
+	.bDeviceClass              = 0,
+#else
+	.bDeviceClass              = CDC_CLASS_DEVICE,
+#endif
+	.bDeviceSubClass           = 0,
+	.bDeviceProtocol           = 0,
+	.bMaxPacketSize0           = USB_DEVICE_EP_CTRL_SIZE,
+	.bNumConfigurations        = 1
+};
+#endif
+
+#ifdef USB_DEVICE_LPM_SUPPORT
+//! USB Device Qualifier Descriptor
+COMPILER_WORD_ALIGNED
+UDC_DESC_STORAGE usb_dev_lpm_desc_t udc_device_lpm = {
+	.bos.bLength               = sizeof(usb_dev_bos_desc_t),
+	.bos.bDescriptorType       = USB_DT_BOS,
+	.bos.wTotalLength          = LE16(sizeof(usb_dev_bos_desc_t) + sizeof(usb_dev_capa_ext_desc_t)),
+	.bos.bNumDeviceCaps        = 1,
+	.capa_ext.bLength          = sizeof(usb_dev_capa_ext_desc_t),
+	.capa_ext.bDescriptorType  = USB_DT_DEVICE_CAPABILITY,
+	.capa_ext.bDevCapabilityType = USB_DC_USB20_EXTENSION,
+	.capa_ext.bmAttributes     = USB_DC_EXT_LPM,
+};
+#endif
+
+//! Structure for USB Device Configuration Descriptor
+COMPILER_PACK_SET(1)
+typedef struct {
+	usb_conf_desc_t conf;
+#if UDI_CDC_PORT_NB == 1
+	udi_cdc_comm_desc_t udi_cdc_comm_0;
+	udi_cdc_data_desc_t udi_cdc_data_0;
+#else
+#  define UDI_CDC_DESC_STRUCTURE(index, unused) \
+	usb_iad_desc_t      udi_cdc_iad_##index; \
+	udi_cdc_comm_desc_t udi_cdc_comm_##index; \
+	udi_cdc_data_desc_t udi_cdc_data_##index;
+	MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_STRUCTURE, ~)
+#  undef UDI_CDC_DESC_STRUCTURE
+#endif
+} udc_desc_t;
+COMPILER_PACK_RESET()
+
+//! USB Device Configuration Descriptor filled for full and high speed
+COMPILER_WORD_ALIGNED
+UDC_DESC_STORAGE udc_desc_t udc_desc_fs = {
+	.conf.bLength              = sizeof(usb_conf_desc_t),
+	.conf.bDescriptorType      = USB_DT_CONFIGURATION,
+	.conf.wTotalLength         = LE16(sizeof(udc_desc_t)),
+	.conf.bNumInterfaces       = USB_DEVICE_NB_INTERFACE,
+	.conf.bConfigurationValue  = 1,
+	.conf.iConfiguration       = 0,
+	.conf.bmAttributes         = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR,
+	.conf.bMaxPower            = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER),
+#if UDI_CDC_PORT_NB == 1
+	.udi_cdc_comm_0            = UDI_CDC_COMM_DESC_0,
+	.udi_cdc_data_0            = UDI_CDC_DATA_DESC_0_FS,
+#else
+#  define UDI_CDC_DESC_FS(index, unused) \
+	.udi_cdc_iad_##index             = UDI_CDC_IAD_DESC_##index,\
+	.udi_cdc_comm_##index            = UDI_CDC_COMM_DESC_##index,\
+	.udi_cdc_data_##index            = UDI_CDC_DATA_DESC_##index##_FS,
+	MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_FS, ~)
+#  undef UDI_CDC_DESC_FS
+#endif
+};
+
+#ifdef USB_DEVICE_HS_SUPPORT
+COMPILER_WORD_ALIGNED
+UDC_DESC_STORAGE udc_desc_t udc_desc_hs = {
+	.conf.bLength              = sizeof(usb_conf_desc_t),
+	.conf.bDescriptorType      = USB_DT_CONFIGURATION,
+	.conf.wTotalLength         = LE16(sizeof(udc_desc_t)),
+	.conf.bNumInterfaces       = USB_DEVICE_NB_INTERFACE,
+	.conf.bConfigurationValue  = 1,
+	.conf.iConfiguration       = 0,
+	.conf.bmAttributes         = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR,
+	.conf.bMaxPower            = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER),
+#if UDI_CDC_PORT_NB == 1
+	.udi_cdc_comm_0            = UDI_CDC_COMM_DESC_0,
+	.udi_cdc_data_0            = UDI_CDC_DATA_DESC_0_HS,
+#else
+#  define UDI_CDC_DESC_HS(index, unused) \
+	.udi_cdc_iad_##index             = UDI_CDC_IAD_DESC_##index, \
+	.udi_cdc_comm_##index            = UDI_CDC_COMM_DESC_##index, \
+	.udi_cdc_data_##index            = UDI_CDC_DATA_DESC_##index##_HS,
+	MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_HS, ~)
+#  undef UDI_CDC_DESC_HS
+#endif
+};
+#endif
+
+/**
+ * \name UDC structures which content all USB Device definitions
+ */
+//@{
+
+//! Associate an UDI for each USB interface
+UDC_DESC_STORAGE udi_api_t *udi_apis[USB_DEVICE_NB_INTERFACE] = {
+#  define UDI_CDC_API(index, unused) \
+	&udi_api_cdc_comm, \
+	&udi_api_cdc_data,
+	MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_API, ~)
+#  undef UDI_CDC_API
+};
+
+//! Add UDI with USB Descriptors FS & HS
+UDC_DESC_STORAGE udc_config_speed_t udc_config_fs[1] = { {
+	.desc          = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_fs,
+	.udi_apis = udi_apis,
+}};
+#ifdef USB_DEVICE_HS_SUPPORT
+UDC_DESC_STORAGE udc_config_speed_t udc_config_hs[1] = { {
+	.desc          = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_hs,
+	.udi_apis = udi_apis,
+}};
+#endif
+
+//! Add all information about USB Device in global structure for UDC
+UDC_DESC_STORAGE udc_config_t udc_config = {
+	.confdev_lsfs = &udc_device_desc,
+	.conf_lsfs = udc_config_fs,
+#ifdef USB_DEVICE_HS_SUPPORT
+	.confdev_hs = &udc_device_desc,
+	.qualifier = &udc_device_qual,
+	.conf_hs = udc_config_hs,
+#endif
+#ifdef USB_DEVICE_LPM_SUPPORT
+	.conf_bos = &udc_device_lpm.bos,
+#else
+	.conf_bos = NULL,
+#endif
+};
+
+//@}
+//@}

asf/common/services/usb/class/cdc/usb_protocol_cdc.h

@@ -0,0 +1,318 @@
+/**
+ * \file
+ *
+ * \brief USB Communication Device Class (CDC) protocol definitions
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef _USB_PROTOCOL_CDC_H_
+#define _USB_PROTOCOL_CDC_H_
+
+#include "compiler.h"
+
+/**
+ * \ingroup usb_protocol_group
+ * \defgroup cdc_protocol_group Communication Device Class Definitions
+ * @{
+ */
+
+/**
+ * \name Possible values of class
+ */
+//@{
+#define  CDC_CLASS_DEVICE     0x02	//!< USB Communication Device Class
+#define  CDC_CLASS_COMM       0x02	//!< CDC Communication Class Interface
+#define  CDC_CLASS_DATA       0x0A	//!< CDC Data Class Interface
+//@}
+
+//! \name USB CDC Subclass IDs
+//@{
+#define  CDC_SUBCLASS_DLCM    0x01	//!< Direct Line Control Model
+#define  CDC_SUBCLASS_ACM     0x02	//!< Abstract Control Model
+#define  CDC_SUBCLASS_TCM     0x03	//!< Telephone Control Model
+#define  CDC_SUBCLASS_MCCM    0x04	//!< Multi-Channel Control Model
+#define  CDC_SUBCLASS_CCM     0x05	//!< CAPI Control Model
+#define  CDC_SUBCLASS_ETH     0x06	//!< Ethernet Networking Control Model
+#define  CDC_SUBCLASS_ATM     0x07	//!< ATM Networking Control Model
+//@}
+
+//! \name USB CDC Communication Interface Protocol IDs
+//@{
+#define  CDC_PROTOCOL_V25TER  0x01	//!< Common AT commands
+//@}
+
+//! \name USB CDC Data Interface Protocol IDs
+//@{
+#define  CDC_PROTOCOL_I430    0x30	//!< ISDN BRI
+#define  CDC_PROTOCOL_HDLC    0x31	//!< HDLC
+#define  CDC_PROTOCOL_TRANS   0x32	//!< Transparent
+#define  CDC_PROTOCOL_Q921M   0x50	//!< Q.921 management protocol
+#define  CDC_PROTOCOL_Q921    0x51	//!< Q.931 [sic] Data link protocol
+#define  CDC_PROTOCOL_Q921TM  0x52	//!< Q.921 TEI-multiplexor
+#define  CDC_PROTOCOL_V42BIS  0x90	//!< Data compression procedures
+#define  CDC_PROTOCOL_Q931    0x91	//!< Euro-ISDN protocol control
+#define  CDC_PROTOCOL_V120    0x92	//!< V.24 rate adaption to ISDN
+#define  CDC_PROTOCOL_CAPI20  0x93	//!< CAPI Commands
+#define  CDC_PROTOCOL_HOST    0xFD	//!< Host based driver
+/**
+ * \brief Describes the Protocol Unit Functional Descriptors [sic]
+ * on Communication Class Interface
+ */
+#define  CDC_PROTOCOL_PUFD    0xFE
+//@}
+
+//! \name USB CDC Functional Descriptor Types
+//@{
+#define  CDC_CS_INTERFACE     0x24	//!< Interface Functional Descriptor
+#define  CDC_CS_ENDPOINT      0x25	//!< Endpoint Functional Descriptor
+//@}
+
+//! \name USB CDC Functional Descriptor Subtypes
+//@{
+#define  CDC_SCS_HEADER       0x00	//!< Header Functional Descriptor
+#define  CDC_SCS_CALL_MGMT    0x01	//!< Call Management
+#define  CDC_SCS_ACM          0x02	//!< Abstract Control Management
+#define  CDC_SCS_UNION        0x06	//!< Union Functional Descriptor
+//@}
+
+//! \name USB CDC Request IDs
+//@{
+#define  USB_REQ_CDC_SEND_ENCAPSULATED_COMMAND                   0x00
+#define  USB_REQ_CDC_GET_ENCAPSULATED_RESPONSE                   0x01
+#define  USB_REQ_CDC_SET_COMM_FEATURE                            0x02
+#define  USB_REQ_CDC_GET_COMM_FEATURE                            0x03
+#define  USB_REQ_CDC_CLEAR_COMM_FEATURE                          0x04
+#define  USB_REQ_CDC_SET_AUX_LINE_STATE                          0x10
+#define  USB_REQ_CDC_SET_HOOK_STATE                              0x11
+#define  USB_REQ_CDC_PULSE_SETUP                                 0x12
+#define  USB_REQ_CDC_SEND_PULSE                                  0x13
+#define  USB_REQ_CDC_SET_PULSE_TIME                              0x14
+#define  USB_REQ_CDC_RING_AUX_JACK                               0x15
+#define  USB_REQ_CDC_SET_LINE_CODING                             0x20
+#define  USB_REQ_CDC_GET_LINE_CODING                             0x21
+#define  USB_REQ_CDC_SET_CONTROL_LINE_STATE                      0x22
+#define  USB_REQ_CDC_SEND_BREAK                                  0x23
+#define  USB_REQ_CDC_SET_RINGER_PARMS                            0x30
+#define  USB_REQ_CDC_GET_RINGER_PARMS                            0x31
+#define  USB_REQ_CDC_SET_OPERATION_PARMS                         0x32
+#define  USB_REQ_CDC_GET_OPERATION_PARMS                         0x33
+#define  USB_REQ_CDC_SET_LINE_PARMS                              0x34
+#define  USB_REQ_CDC_GET_LINE_PARMS                              0x35
+#define  USB_REQ_CDC_DIAL_DIGITS                                 0x36
+#define  USB_REQ_CDC_SET_UNIT_PARAMETER                          0x37
+#define  USB_REQ_CDC_GET_UNIT_PARAMETER                          0x38
+#define  USB_REQ_CDC_CLEAR_UNIT_PARAMETER                        0x39
+#define  USB_REQ_CDC_GET_PROFILE                                 0x3A
+#define  USB_REQ_CDC_SET_ETHERNET_MULTICAST_FILTERS              0x40
+#define  USB_REQ_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x41
+#define  USB_REQ_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x42
+#define  USB_REQ_CDC_SET_ETHERNET_PACKET_FILTER                  0x43
+#define  USB_REQ_CDC_GET_ETHERNET_STATISTIC                      0x44
+#define  USB_REQ_CDC_SET_ATM_DATA_FORMAT                         0x50
+#define  USB_REQ_CDC_GET_ATM_DEVICE_STATISTICS                   0x51
+#define  USB_REQ_CDC_SET_ATM_DEFAULT_VC                          0x52
+#define  USB_REQ_CDC_GET_ATM_VC_STATISTICS                       0x53
+// Added bNotification codes according cdc spec 1.1 chapter 6.3
+#define  USB_REQ_CDC_NOTIFY_RING_DETECT                          0x09
+#define  USB_REQ_CDC_NOTIFY_SERIAL_STATE                         0x20
+#define  USB_REQ_CDC_NOTIFY_CALL_STATE_CHANGE                    0x28
+#define  USB_REQ_CDC_NOTIFY_LINE_STATE_CHANGE                    0x29
+//@}
+
+/*
+ * Need to pack structures tightly, or the compiler might insert padding
+ * and violate the spec-mandated layout.
+ */
+COMPILER_PACK_SET(1)
+
+//! \name USB CDC Descriptors
+//@{
+
+
+//! CDC Header Functional Descriptor
+typedef struct {
+	uint8_t bFunctionLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubtype;
+	le16_t bcdCDC;
+} usb_cdc_hdr_desc_t;
+
+//! CDC Call Management Functional Descriptor
+typedef struct {
+	uint8_t bFunctionLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubtype;
+	uint8_t bmCapabilities;
+	uint8_t bDataInterface;
+} usb_cdc_call_mgmt_desc_t;
+
+//! CDC ACM Functional Descriptor
+typedef struct {
+	uint8_t bFunctionLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubtype;
+	uint8_t bmCapabilities;
+} usb_cdc_acm_desc_t;
+
+//! CDC Union Functional Descriptor
+typedef struct {
+	uint8_t bFunctionLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubtype;
+	uint8_t bMasterInterface;
+	uint8_t bSlaveInterface0;
+} usb_cdc_union_desc_t;
+
+
+//! \name USB CDC Call Management Capabilities
+//@{
+//! Device handles call management itself
+#define  CDC_CALL_MGMT_SUPPORTED             (1 << 0)
+//! Device can send/receive call management info over a Data Class interface
+#define  CDC_CALL_MGMT_OVER_DCI              (1 << 1)
+//@}
+
+//! \name USB CDC ACM Capabilities
+//@{
+//! Device supports the request combination of
+//! Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature.
+#define  CDC_ACM_SUPPORT_FEATURE_REQUESTS    (1 << 0)
+//! Device supports the request combination of
+//! Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding,
+//! and the notification Serial_State.
+#define  CDC_ACM_SUPPORT_LINE_REQUESTS       (1 << 1)
+//! Device supports the request Send_Break
+#define  CDC_ACM_SUPPORT_SENDBREAK_REQUESTS  (1 << 2)
+//! Device supports the notification Network_Connection.
+#define  CDC_ACM_SUPPORT_NOTIFY_REQUESTS     (1 << 3)
+//@}
+//@}
+
+//! \name USB CDC line control
+//@{
+
+//! \name USB CDC line coding
+//@{
+//! Line Coding structure
+typedef struct {
+	le32_t dwDTERate;
+	uint8_t bCharFormat;
+	uint8_t bParityType;
+	uint8_t bDataBits;
+} usb_cdc_line_coding_t;
+//! Possible values of bCharFormat
+enum cdc_char_format {
+	CDC_STOP_BITS_1 = 0,	//!< 1 stop bit
+	CDC_STOP_BITS_1_5 = 1,	//!< 1.5 stop bits
+	CDC_STOP_BITS_2 = 2,	//!< 2 stop bits
+};
+//! Possible values of bParityType
+enum cdc_parity {
+	CDC_PAR_NONE = 0,	//!< No parity
+	CDC_PAR_ODD = 1,	//!< Odd parity
+	CDC_PAR_EVEN = 2,	//!< Even parity
+	CDC_PAR_MARK = 3,	//!< Parity forced to 0 (space)
+	CDC_PAR_SPACE = 4,	//!< Parity forced to 1 (mark)
+};
+//@}
+
+//! \name USB CDC control signals
+//! spec 1.1 chapter 6.2.14
+//@{
+
+//! Control signal structure
+typedef struct {
+	uint16_t value;
+} usb_cdc_control_signal_t;
+
+//! \name Possible values in usb_cdc_control_signal_t
+//@{
+//! Carrier control for half duplex modems.
+//! This signal corresponds to V.24 signal 105 and RS-232 signal RTS.
+//! The device ignores the value of this bit
+//! when operating in full duplex mode.
+#define  CDC_CTRL_SIGNAL_ACTIVATE_CARRIER    (1 << 1)
+//! Indicates to DCE if DTE is present or not.
+//! This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR.
+#define  CDC_CTRL_SIGNAL_DTE_PRESENT         (1 << 0)
+//@}
+//@}
+
+
+//! \name USB CDC notification message
+//@{
+
+typedef struct {
+	uint8_t bmRequestType;
+	uint8_t bNotification;
+	le16_t wValue;
+	le16_t wIndex;
+	le16_t wLength;
+} usb_cdc_notify_msg_t;
+
+//! \name USB CDC serial state
+//@{*
+
+//! Hardware handshake support (cdc spec 1.1 chapter 6.3.5)
+typedef struct {
+	usb_cdc_notify_msg_t header;
+	le16_t value;
+} usb_cdc_notify_serial_state_t;
+
+//! \name Possible values in usb_cdc_notify_serial_state_t
+//@{
+#define  CDC_SERIAL_STATE_DCD       CPU_TO_LE16((1<<0))
+#define  CDC_SERIAL_STATE_DSR       CPU_TO_LE16((1<<1))
+#define  CDC_SERIAL_STATE_BREAK     CPU_TO_LE16((1<<2))
+#define  CDC_SERIAL_STATE_RING      CPU_TO_LE16((1<<3))
+#define  CDC_SERIAL_STATE_FRAMING   CPU_TO_LE16((1<<4))
+#define  CDC_SERIAL_STATE_PARITY    CPU_TO_LE16((1<<5))
+#define  CDC_SERIAL_STATE_OVERRUN   CPU_TO_LE16((1<<6))
+//@}
+//! @}
+
+//! @}
+
+COMPILER_PACK_RESET()
+
+//! @}
+
+#endif // _USB_PROTOCOL_CDC_H_

asf/common/services/usb/class/composite/device/example4/samd21j18a_samd21_xplained_pro/ui.c

@@ -0,0 +1,147 @@
+/**
+ * \file
+ *
+ * \brief User Interface
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <asf.h>
+#include "ui.h"
+
+void ui_init(void)
+{
+	/* Initialize LEDs */
+	LED_On(LED_0_PIN);
+}
+
+void ui_powerdown(void)
+{
+	LED_Off(LED_0_PIN);
+}
+
+void ui_wakeup(void)
+{
+	LED_On(LED_0_PIN);
+}
+
+
+void ui_com_open(uint8_t port)
+{
+	UNUSED(port);
+}
+
+
+void ui_com_close(uint8_t port)
+{
+	UNUSED(port);
+}
+
+
+void ui_com_rx_start(void)
+{
+
+}
+
+
+void ui_com_rx_stop(void)
+{
+
+}
+
+
+void ui_com_tx_start(void)
+{
+
+}
+
+
+void ui_com_tx_stop(void)
+{
+
+}
+
+
+void ui_com_error(void)
+{
+
+}
+
+
+void ui_com_overflow(void)
+{
+
+}
+
+void ui_start_read(void)
+{
+}
+
+void ui_stop_read(void)
+{
+}
+
+void ui_start_write(void)
+{
+}
+
+void ui_stop_write(void)
+{
+}
+
+void ui_process(uint16_t framenumber)
+{
+	if ((framenumber % 1000) == 0) {
+		LED_On(LED_0_PIN);
+	}
+	if ((framenumber % 1000) == 500) {
+		LED_Off(LED_0_PIN);
+	}
+}
+
+
+/**
+ * \defgroup UI User Interface
+ *
+ * Human interface on SAMD21-XPlain:
+ * - LED0 blinks when USB host has checked and enabled CDC and MSC interface
+ *
+ */

asf/common/services/usb/class/composite/device/udi_composite_conf.h

@@ -0,0 +1,50 @@
+/**
+ * \file
+ *
+ * \brief Descriptors for an USB Composite Device MSC and HID mouse
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _UDI_COMPOSITE_CONF_H_
+#define _UDI_COMPOSITE_CONF_H_
+
+#endif // _UDI_COMPOSITE_CONF_H_

asf/common/services/usb/class/composite/device/udi_composite_desc.c

@@ -0,0 +1,184 @@
+/**
+ * \file
+ *
+ * \brief Descriptors for an USB Composite Device
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "conf_usb.h"
+#include "udd.h"
+#include "udc_desc.h"
+
+/**
+ * \defgroup udi_group_desc Descriptors for a USB Device
+ * composite
+ *
+ * @{
+ */
+
+/**INDENT-OFF**/
+
+//! USB Device Descriptor
+COMPILER_WORD_ALIGNED
+UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc = {
+	.bLength                   = sizeof(usb_dev_desc_t),
+	.bDescriptorType           = USB_DT_DEVICE,
+	.bcdUSB                    = LE16(USB_V2_0),
+	.bDeviceClass              = 0,
+	.bDeviceSubClass           = 0,
+	.bDeviceProtocol           = 0,
+	.bMaxPacketSize0           = USB_DEVICE_EP_CTRL_SIZE,
+	.idVendor                  = LE16(USB_DEVICE_VENDOR_ID),
+	.idProduct                 = LE16(USB_DEVICE_PRODUCT_ID),
+	.bcdDevice                 = LE16((USB_DEVICE_MAJOR_VERSION << 8)
+		| USB_DEVICE_MINOR_VERSION),
+#ifdef USB_DEVICE_MANUFACTURE_NAME
+	.iManufacturer             = 1,
+#else
+	.iManufacturer             = 0,  // No manufacture string
+#endif
+#ifdef USB_DEVICE_PRODUCT_NAME
+	.iProduct                  = 2,
+#else
+	.iProduct                  = 0,  // No product string
+#endif
+#ifdef USB_DEVICE_SERIAL_NAME
+	.iSerialNumber             = 3,
+#else
+	.iSerialNumber             = 0,  // No serial string
+#endif
+	.bNumConfigurations        = 1
+};
+
+
+#ifdef USB_DEVICE_HS_SUPPORT
+//! USB Device Qualifier Descriptor for HS
+COMPILER_WORD_ALIGNED
+UDC_DESC_STORAGE usb_dev_qual_desc_t udc_device_qual = {
+	.bLength                   = sizeof(usb_dev_qual_desc_t),
+	.bDescriptorType           = USB_DT_DEVICE_QUALIFIER,
+	.bcdUSB                    = LE16(USB_V2_0),
+	.bDeviceClass              = 0,
+	.bDeviceSubClass           = 0,
+	.bDeviceProtocol           = 0,
+	.bMaxPacketSize0           = USB_DEVICE_EP_CTRL_SIZE,
+	.bNumConfigurations        = 1
+};
+#endif
+
+//! Structure for USB Device Configuration Descriptor
+COMPILER_PACK_SET(1)
+typedef struct {
+	usb_conf_desc_t conf;
+	UDI_COMPOSITE_DESC_T;
+} udc_desc_t;
+COMPILER_PACK_RESET()
+
+//! USB Device Configuration Descriptor filled for FS
+COMPILER_WORD_ALIGNED
+UDC_DESC_STORAGE udc_desc_t udc_desc_fs = {
+	.conf.bLength              = sizeof(usb_conf_desc_t),
+	.conf.bDescriptorType      = USB_DT_CONFIGURATION,
+	.conf.wTotalLength         = LE16(sizeof(udc_desc_t)),
+	.conf.bNumInterfaces       = USB_DEVICE_NB_INTERFACE,
+	.conf.bConfigurationValue  = 1,
+	.conf.iConfiguration       = 0,
+	.conf.bmAttributes         = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR,
+	.conf.bMaxPower            = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER),
+	UDI_COMPOSITE_DESC_FS
+};
+
+#ifdef USB_DEVICE_HS_SUPPORT
+//! USB Device Configuration Descriptor filled for HS
+COMPILER_WORD_ALIGNED
+UDC_DESC_STORAGE udc_desc_t udc_desc_hs = {
+	.conf.bLength              = sizeof(usb_conf_desc_t),
+	.conf.bDescriptorType      = USB_DT_CONFIGURATION,
+	.conf.wTotalLength         = LE16(sizeof(udc_desc_t)),
+	.conf.bNumInterfaces       = USB_DEVICE_NB_INTERFACE,
+	.conf.bConfigurationValue  = 1,
+	.conf.iConfiguration       = 0,
+	.conf.bmAttributes         = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR,
+	.conf.bMaxPower            = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER),
+	UDI_COMPOSITE_DESC_HS
+};
+#endif
+
+
+/**
+ * \name UDC structures which contains all USB Device definitions
+ */
+//@{
+
+//! Associate an UDI for each USB interface
+UDC_DESC_STORAGE udi_api_t *udi_apis[USB_DEVICE_NB_INTERFACE] = {
+	UDI_COMPOSITE_API
+};
+
+//! Add UDI with USB Descriptors FS
+UDC_DESC_STORAGE udc_config_speed_t   udc_config_lsfs[1] = {{
+	.desc          = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_fs,
+	.udi_apis      = udi_apis,
+}};
+
+#ifdef USB_DEVICE_HS_SUPPORT
+//! Add UDI with USB Descriptors HS
+UDC_DESC_STORAGE udc_config_speed_t   udc_config_hs[1] = {{
+	.desc          = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_hs,
+	.udi_apis      = udi_apis,
+}};
+#endif
+
+//! Add all information about USB Device in global structure for UDC
+UDC_DESC_STORAGE udc_config_t udc_config = {
+	.confdev_lsfs = &udc_device_desc,
+	.conf_lsfs = udc_config_lsfs,
+#ifdef USB_DEVICE_HS_SUPPORT
+	.confdev_hs = &udc_device_desc,
+	.qualifier = &udc_device_qual,
+	.conf_hs = udc_config_hs,
+#endif
+};
+
+//@}
+/**INDENT-ON**/
+//@}

asf/common/services/usb/class/msc/device/udi_msc.h

@@ -0,0 +1,376 @@
+/**
+ * \file
+ *
+ * \brief USB Device Mass Storage Class (MSC) interface definitions.
+ *
+ * Copyright (c) 2009-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _UDI_MSC_H_
+#define _UDI_MSC_H_
+
+#include "conf_usb.h"
+#include "usb_protocol.h"
+#include "usb_protocol_msc.h"
+#include "udd.h"
+#include "udc_desc.h"
+#include "udi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup udi_msc_group_udc
+ * @{
+ */
+//! Global structure which contains standard UDI interface for UDC
+extern UDC_DESC_STORAGE udi_api_t udi_api_msc;
+//@}
+
+/**
+ * \ingroup udi_msc_group
+ * \defgroup udi_msc_group USB interface descriptors
+ *
+ * The following structures provide predefined USB interface descriptors.
+ * It must be used to define the final USB descriptors.
+ */
+//@{
+
+//! Interface descriptor structure for MSC
+typedef struct {
+	usb_iface_desc_t iface;
+	usb_ep_desc_t ep_in;
+	usb_ep_desc_t ep_out;
+} udi_msc_desc_t;
+
+//! By default no string associated to this interface
+#ifndef UDI_MSC_STRING_ID
+#define UDI_MSC_STRING_ID     0
+#endif
+
+//! MSC endpoints size for full speed
+#define UDI_MSC_EPS_SIZE_FS   64
+//! MSC endpoints size for high speed
+#define UDI_MSC_EPS_SIZE_HS   512
+
+//! Content of MSC interface descriptor for all speeds
+#define UDI_MSC_DESC      \
+   .iface.bLength             = sizeof(usb_iface_desc_t),\
+   .iface.bDescriptorType     = USB_DT_INTERFACE,\
+   .iface.bInterfaceNumber    = UDI_MSC_IFACE_NUMBER,\
+   .iface.bAlternateSetting   = 0,\
+   .iface.bNumEndpoints       = 2,\
+   .iface.bInterfaceClass     = MSC_CLASS,\
+   .iface.bInterfaceSubClass  = MSC_SUBCLASS_TRANSPARENT,\
+   .iface.bInterfaceProtocol  = MSC_PROTOCOL_BULK,\
+   .iface.iInterface          = UDI_MSC_STRING_ID,\
+   .ep_in.bLength             = sizeof(usb_ep_desc_t),\
+   .ep_in.bDescriptorType     = USB_DT_ENDPOINT,\
+   .ep_in.bEndpointAddress    = UDI_MSC_EP_IN,\
+   .ep_in.bmAttributes        = USB_EP_TYPE_BULK,\
+   .ep_in.bInterval           = 0,\
+   .ep_out.bLength            = sizeof(usb_ep_desc_t),\
+   .ep_out.bDescriptorType    = USB_DT_ENDPOINT,\
+   .ep_out.bEndpointAddress   = UDI_MSC_EP_OUT,\
+   .ep_out.bmAttributes       = USB_EP_TYPE_BULK,\
+   .ep_out.bInterval          = 0,
+
+//! Content of MSC interface descriptor for full speed only
+#define UDI_MSC_DESC_FS   {\
+   UDI_MSC_DESC \
+   .ep_in.wMaxPacketSize      = LE16(UDI_MSC_EPS_SIZE_FS),\
+   .ep_out.wMaxPacketSize     = LE16(UDI_MSC_EPS_SIZE_FS),\
+   }
+
+//! Content of MSC interface descriptor for high speed only
+#define UDI_MSC_DESC_HS   {\
+   UDI_MSC_DESC \
+   .ep_in.wMaxPacketSize      = LE16(UDI_MSC_EPS_SIZE_HS),\
+   .ep_out.wMaxPacketSize     = LE16(UDI_MSC_EPS_SIZE_HS),\
+   }
+//@}
+
+
+/**
+ * \ingroup udi_group
+ * \defgroup udi_msc_group USB Device Interface (UDI) for Mass Storage Class (MSC)
+ *
+ * Common APIs used by high level application to use this USB class.
+ *
+ * These routines are used by memory to transfer its data
+ * to/from USB MSC endpoints.
+ *
+ * See \ref udi_msc_quickstart.
+ * @{
+ */
+
+/**
+ * \brief Process the background read/write commands
+ *
+ * Routine called by the main loop
+ */
+bool udi_msc_process_trans(void);
+
+/**
+ * \brief Transfers data to/from USB MSC endpoints
+ *
+ *
+ * \param b_read        Memory to USB, if true
+ * \param block         Buffer on Internal RAM to send or fill
+ * \param block_size    Buffer size to send or fill
+ * \param callback      Function to call at the end of transfer.
+ *                      If NULL then the routine exit when transfer is finish.
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+bool udi_msc_trans_block(bool b_read, uint8_t * block, iram_size_t block_size,
+		void (*callback) (udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep));
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/**
+ * \page udi_msc_quickstart Quick start guide for USB device Mass Storage module (UDI MSC)
+ *
+ * This is the quick start guide for the \ref udi_msc_group 
+ * "USB device interface MSC module (UDI MSC)" with step-by-step instructions on 
+ * how to configure and use the modules in a selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ * 
+ * \section udi_msc_basic_use_case Basic use case
+ * In this basic use case, the "USB MSC (Single Interface Device)" module is used.
+ * The "USB MSC (Composite Device)" module usage is described in \ref udi_msc_use_cases
+ * "Advanced use cases".
+ *
+ * \section udi_msc_basic_use_case_setup Setup steps
+ * \subsection udi_msc_basic_use_case_setup_prereq Prerequisites
+ * \copydetails udc_basic_use_case_setup_prereq
+ * \subsection udi_msc_basic_use_case_setup_code Example code
+ * \copydetails udc_basic_use_case_setup_code
+ * \subsection udi_msc_basic_use_case_setup_flow Workflow
+ * \copydetails udc_basic_use_case_setup_flow
+ *
+ * \section udi_msc_basic_use_case_usage Usage steps
+ *
+ * \subsection udi_msc_basic_use_case_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+	#define  USB_DEVICE_SERIAL_NAME  "12...EF" // Disk SN for MSC
+	#define UDI_MSC_GLOBAL_VENDOR_ID \
+	   'A', 'T', 'M', 'E', 'L', ' ', ' ', ' '
+	#define UDI_MSC_GLOBAL_PRODUCT_VERSION \
+	   '1', '.', '0', '0'
+	#define UDI_MSC_ENABLE_EXT() my_callback_msc_enable()
+	extern bool my_callback_msc_enable(void);
+	#define UDI_MSC_DISABLE_EXT() my_callback_msc_disable()
+	extern void my_callback_msc_disable(void);
+	#include "udi_msc_conf.h" // At the end of conf_usb.h file
+\endcode
+ *
+ * Add to application C-file:
+ * \code
+	 static bool my_flag_autorize_msc_transfert = false;
+	 bool my_callback_msc_enable(void)
+	 {
+	    my_flag_autorize_msc_transfert = true;
+	    return true;
+	 }
+	 void my_callback_msc_disable(void)
+	 {
+	    my_flag_autorize_msc_transfert = false;
+	 }
+
+	 void task(void)
+	 {
+	    udi_msc_process_trans();
+	 }
+\endcode
+ *
+ * \subsection udi_msc_basic_use_case_setup_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following configuration,
+ * which is the USB device MSC configuration:
+ *   - \code #define USB_DEVICE_SERIAL_NAME  "12...EF" // Disk SN for MSC \endcode
+ *     \note The USB serial number is mandatory when a MSC interface is used.
+ *   - \code //! Vendor name and Product version of MSC interface
+	#define UDI_MSC_GLOBAL_VENDOR_ID \
+	   'A', 'T', 'M', 'E', 'L', ' ', ' ', ' '
+	#define UDI_MSC_GLOBAL_PRODUCT_VERSION \
+	   '1', '.', '0', '0' \endcode
+ *     \note The USB MSC interface requires a vendor ID (8 ASCII characters)
+ *     and a product version (4 ASCII characters).
+ *   - \code #define UDI_MSC_ENABLE_EXT() my_callback_msc_enable()
+	extern bool my_callback_msc_enable(void); \endcode
+ *     \note After the device enumeration (detecting and identifying USB devices),
+ *     the USB host starts the device configuration. When the USB MSC interface 
+ *     from the device is accepted by the host, the USB host enables this interface and the
+ *     UDI_MSC_ENABLE_EXT() callback function is called and return true.
+ *     Thus, when this event is received, the tasks which call
+ *     udi_msc_process_trans() must be enabled.
+ *   - \code #define UDI_MSC_DISABLE_EXT() my_callback_msc_disable()
+	extern void my_callback_msc_disable(void); \endcode
+ *     \note When the USB device is unplugged or is reset by the USB host, the USB
+ *     interface is disabled and the UDI_MSC_DISABLE_EXT() callback function
+ *     is called. Thus, it is recommended to disable the task which is called udi_msc_process_trans().
+ * -# The MSC is automatically linked with memory control access component 
+ * which provides the memories interfaces. However, the memory data transfers
+ * must be done outside USB interrupt routine. This is done in the MSC process
+ * ("udi_msc_process_trans()") called by main loop:
+ *   - \code  * void task(void) {
+	udi_msc_process_trans();
+	} \endcode
+ * -# The MSC speed depends on task periodicity. To get the best speed
+ * the notification callback "UDI_MSC_NOTIFY_TRANS_EXT" can be used to wakeup
+ * this task (Example, through a mutex):
+ *   - \code #define  UDI_MSC_NOTIFY_TRANS_EXT()    msc_notify_trans()
+	void msc_notify_trans(void) {
+	wakeup_my_task();
+	} \endcode
+ *
+ * \section udi_msc_use_cases Advanced use cases
+ * For more advanced use of the UDI MSC module, see the following use cases:
+ * - \subpage udi_msc_use_case_composite
+ * - \subpage udc_use_case_1
+ * - \subpage udc_use_case_2
+ * - \subpage udc_use_case_3
+ * - \subpage udc_use_case_5
+ * - \subpage udc_use_case_6
+ */
+
+/**
+ * \page udi_msc_use_case_composite MSC in a composite device
+ *
+ * A USB Composite Device is a USB Device which uses more than one USB class.
+ * In this use case, the "USB MSC (Composite Device)" module is used to
+ * create a USB composite device. Thus, this USB module can be associated with
+ * another "Composite Device" module, like "USB HID Mouse (Composite Device)".
+ * 
+ * Also, you can refer to application note
+ * <A href="http://www.atmel.com/dyn/resources/prod_documents/doc8445.pdf">
+ * AVR4902 ASF - USB Composite Device</A>.
+ *
+ * \section udi_msc_use_case_composite_setup Setup steps
+ * For the setup code of this use case to work, the
+ * \ref udi_msc_basic_use_case "basic use case" must be followed.
+ *
+ * \section udi_msc_use_case_composite_usage Usage steps
+ *
+ * \subsection udi_msc_use_case_composite_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+	 #define USB_DEVICE_EP_CTRL_SIZE  64
+	 #define USB_DEVICE_NB_INTERFACE (X+1)
+	 #define USB_DEVICE_MAX_EP (X+2)
+
+	 #define UDI_MSC_EP_IN  (X | USB_EP_DIR_IN)
+	 #define UDI_MSC_EP_OUT (Y | USB_EP_DIR_OUT)
+	 #define UDI_MSC_IFACE_NUMBER  X
+
+	 #define UDI_COMPOSITE_DESC_T \
+	    udi_msc_desc_t udi_msc; \
+	    ...
+	 #define UDI_COMPOSITE_DESC_FS \
+	    .udi_msc = UDI_MSC_DESC, \
+	    ...
+	 #define UDI_COMPOSITE_DESC_HS \
+	    .udi_msc = UDI_MSC_DESC, \
+	    ...
+	 #define UDI_COMPOSITE_API \
+	    &udi_api_msc, \
+	    ...
+\endcode
+ *
+ * \subsection udi_msc_use_case_composite_usage_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following parameters
+ * required for a USB composite device configuration:
+ *   - \code // Endpoint control size, This must be:
+	// - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM)
+	// - 64 for a high speed device
+	#define USB_DEVICE_EP_CTRL_SIZE  64
+	// Total Number of interfaces on this USB device.
+	// Add 1 for MSC.
+	#define USB_DEVICE_NB_INTERFACE (X+1)
+	// Total number of endpoints on this USB device.
+	// This must include each endpoint for each interface.
+	// Add 2 for MSC.
+	#define USB_DEVICE_MAX_EP (X+2) \endcode
+ * -# Ensure that conf_usb.h contains the description of
+ * composite device:
+ *   - \code // The endpoint numbers chosen by you for the MSC.
+	// The endpoint numbers starting from 1.
+	#define UDI_MSC_EP_IN  (X | USB_EP_DIR_IN)
+	#define UDI_MSC_EP_OUT (Y | USB_EP_DIR_OUT)
+	// The interface index of an interface starting from 0
+	#define UDI_MSC_IFACE_NUMBER  X \endcode
+ * -# Ensure that conf_usb.h contains the following parameters
+ * required for a USB composite device configuration:
+ *   - \code // USB Interfaces descriptor structure
+	#define UDI_COMPOSITE_DESC_T \
+	   ...
+	   udi_msc_desc_t udi_msc; \
+	   ...
+	// USB Interfaces descriptor value for Full Speed
+	#define UDI_COMPOSITE_DESC_FS \
+	   ...
+	   .udi_msc = UDI_MSC_DESC_FS, \
+	   ...
+	// USB Interfaces descriptor value for High Speed
+	#define UDI_COMPOSITE_DESC_HS \
+	   ...
+	   .udi_msc = UDI_MSC_DESC_HS, \
+	   ...
+	// USB Interface APIs
+	#define UDI_COMPOSITE_API \
+	   ...
+	   &udi_api_msc, \
+	   ... \endcode
+ *   - \note The descriptors order given in the four lists above must be the
+ *     same as the order defined by all interface indexes. The interface index
+ *     orders are defined through UDI_X_IFACE_NUMBER defines.
+ */
+
+#endif // _UDI_MSC_H_

asf/common/services/usb/class/msc/sbc_protocol.h

@@ -14,7 +14,7 @@
  *   - SBC-2 depends on SPC-3
  *   - SBC-3 depends on SPC-4
  *
- * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
@@ -51,10 +51,12 @@
  * \asf_license_stop
  *
  */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
 #ifndef _SBC_PROTOCOL_H_
 #define _SBC_PROTOCOL_H_
 
-#include "lib/usb_msc/usb_includes.h"
 
 /**
  * \ingroup usb_msc_protocol
@@ -63,86 +65,90 @@
  * @{
  */
 
-/** \name SCSI commands defined by SBC-2 */
-#define SBC_FORMAT_UNIT 0x04
-#define SBC_READ6 0x08
-#define SBC_WRITE6 0x0A
-#define SBC_START_STOP_UNIT 0x1B
-#define SBC_READ_CAPACITY10 0x25
-#define SBC_READ10 0x28
-#define SBC_WRITE10 0x2A
-#define SBC_VERIFY10 0x2F
+//! \name SCSI commands defined by SBC-2
+//@{
+#define  SBC_FORMAT_UNIT         0x04
+#define  SBC_READ6               0x08
+#define  SBC_WRITE6              0x0A
+#define  SBC_START_STOP_UNIT     0x1B
+#define  SBC_READ_CAPACITY10     0x25
+#define  SBC_READ10              0x28
+#define  SBC_WRITE10             0x2A
+#define  SBC_VERIFY10            0x2F
+//@}
+
+//! \name SBC-2 Mode page definitions
+//@{
 
-/** \name SBC-2 Mode page definitions */
 enum scsi_sbc_mode {
-	SCSI_MS_MODE_RW_ERR_RECOV  = 0x01, /**< Read-Write Error Recovery mode page */
-	SCSI_MS_MODE_FORMAT_DEVICE = 0x03, /**< Format Device mode page */
-	SCSI_MS_MODE_FLEXIBLE_DISK = 0x05, /**< Flexible Disk mode page */
-	SCSI_MS_MODE_CACHING       = 0x08
+	SCSI_MS_MODE_RW_ERR_RECOV = 0x01,	//!< Read-Write Error Recovery mode page
+	SCSI_MS_MODE_FORMAT_DEVICE = 0x03,	//!< Format Device mode page
+	SCSI_MS_MODE_FLEXIBLE_DISK = 0x05,	//!< Flexible Disk mode page
+	SCSI_MS_MODE_CACHING = 0x08,	//!< Caching mode page
 };
 
-/** \name SBC-2 Device-Specific Parameter */
-#define SCSI_MS_SBC_WP 0x80     /**< Write Protected */
-#define SCSI_MS_SBC_DPOFUA 0x10 /**< DPO and FUA supported */
+
+//! \name SBC-2 Device-Specific Parameter
+//@{
+#define SCSI_MS_SBC_WP              0x80	//!< Write Protected
+#define SCSI_MS_SBC_DPOFUA          0x10	//!< DPO and FUA supported
+//@}
 
 /**
  * \brief SBC-2 Short LBA mode parameter block descriptor
- * \note Fields are MSB first (BE)
  */
 struct sbc_slba_block_desc {
-	be32_t nr_blocks;                       /**< Number of Blocks (BE32) */
-	be32_t block_len;                       /**< Block Length (BE32) */
-#define SBC_SLBA_BLOCK_LEN_MASK 0x00FFFFFFU /**< Mask reserved bits */
+	be32_t nr_blocks;	//!< Number of Blocks
+	be32_t block_len;	//!< Block Length
+#define SBC_SLBA_BLOCK_LEN_MASK   0x00FFFFFFU	//!< Mask reserved bits
 };
 
 /**
  * \brief SBC-2 Caching mode page
- * \note Fields are MSB first (BE)
  */
 struct sbc_caching_mode_page {
 	uint8_t page_code;
 	uint8_t page_length;
 	uint8_t flags2;
-#define SBC_MP_CACHE_IC (1 << 7)   /**< Initiator Control */
-#define SBC_MP_CACHE_ABPF (1 << 6) /**< Abort Pre-Fetch */
-#define SBC_MP_CACHE_CAP (1 << 5)  /**< Catching Analysis Permitted */
-#define SBC_MP_CACHE_DISC (1 << 4) /**< Discontinuity */
-#define SBC_MP_CACHE_SIZE (1 << 3) /**< Size enable */
-#define SBC_MP_CACHE_WCE (1 << 2)  /**< Write back Cache Enable */
-#define SBC_MP_CACHE_MF (1 << 1)   /**< Multiplication Factor */
-#define SBC_MP_CACHE_RCD (1 << 0)  /**< Read Cache Disable */
+#define  SBC_MP_CACHE_IC      (1 << 7)	//!< Initiator Control
+#define  SBC_MP_CACHE_ABPF    (1 << 6)	//!< Abort Pre-Fetch
+#define  SBC_MP_CACHE_CAP     (1 << 5)	//!< Catching Analysis Permitted
+#define  SBC_MP_CACHE_DISC    (1 << 4)	//!< Discontinuity
+#define  SBC_MP_CACHE_SIZE    (1 << 3)	//!< Size enable
+#define  SBC_MP_CACHE_WCE     (1 << 2)	//!< Write back Cache Enable
+#define  SBC_MP_CACHE_MF      (1 << 1)	//!< Multiplication Factor
+#define  SBC_MP_CACHE_RCD     (1 << 0)	//!< Read Cache Disable
 	uint8_t retention;
-	be16_t  dis_pf_transfer_len;
-	be16_t  min_prefetch;
-	be16_t  max_prefetch;
-	be16_t  max_prefetch_ceil;
+	be16_t dis_pf_transfer_len;
+	be16_t min_prefetch;
+	be16_t max_prefetch;
+	be16_t max_prefetch_ceil;
 	uint8_t flags12;
-#define SBC_MP_CACHE_FSW (1 << 7)    /**< Force Sequential Write */
-#define SBC_MP_CACHE_LBCSS (1 << 6)  /**< Logical Blk Cache Seg Sz */
-#define SBC_MP_CACHE_DRA (1 << 5)    /**< Disable Read-Ahead */
-#define SBC_MP_CACHE_NV_DIS (1 << 0) /**< Non-Volatile Cache Disable */
+#define  SBC_MP_CACHE_FSW     (1 << 7)	//!< Force Sequential Write
+#define  SBC_MP_CACHE_LBCSS   (1 << 6)	//!< Logical Blk Cache Seg Sz
+#define  SBC_MP_CACHE_DRA     (1 << 5)	//!< Disable Read-Ahead
+#define  SBC_MP_CACHE_NV_DIS  (1 << 0)	//!< Non-Volatile Cache Disable
 	uint8_t nr_cache_segments;
-	be16_t  cache_segment_size;
+	be16_t cache_segment_size;
 	uint8_t reserved[4];
 };
 
 /**
  * \brief SBC-2 Read-Write Error Recovery mode page
- * \note Fields are MSB first (BE)
  */
 struct sbc_rdwr_error_recovery_mode_page {
 	uint8_t page_code;
 	uint8_t page_length;
-#define SPC_MP_RW_ERR_RECOV_PAGE_LENGTH 0x0A
+#define  SPC_MP_RW_ERR_RECOV_PAGE_LENGTH    0x0A
 	uint8_t flags1;
-#define SBC_MP_RW_ERR_RECOV_AWRE (1 << 7)
-#define SBC_MP_RW_ERR_RECOV_ARRE (1 << 6)
-#define SBC_MP_RW_ERR_RECOV_TB (1 << 5)
-#define SBC_MP_RW_ERR_RECOV_RC (1 << 4)
-#define SBC_MP_RW_ERR_RECOV_ERR (1 << 3)
-#define SBC_MP_RW_ERR_RECOV_PER (1 << 2)
-#define SBC_MP_RW_ERR_RECOV_DTE (1 << 1)
-#define SBC_MP_RW_ERR_RECOV_DCR (1 << 0)
+#define  SBC_MP_RW_ERR_RECOV_AWRE   (1 << 7)
+#define  SBC_MP_RW_ERR_RECOV_ARRE   (1 << 6)
+#define  SBC_MP_RW_ERR_RECOV_TB     (1 << 5)
+#define  SBC_MP_RW_ERR_RECOV_RC     (1 << 4)
+#define  SBC_MP_RW_ERR_RECOV_ERR    (1 << 3)
+#define  SBC_MP_RW_ERR_RECOV_PER    (1 << 2)
+#define  SBC_MP_RW_ERR_RECOV_DTE    (1 << 1)
+#define  SBC_MP_RW_ERR_RECOV_DCR    (1 << 0)
 	uint8_t read_retry_count;
 	uint8_t correction_span;
 	uint8_t head_offset_count;
@@ -150,16 +156,18 @@ struct sbc_rdwr_error_recovery_mode_page {
 	uint8_t flags2;
 	uint8_t write_retry_count;
 	uint8_t flags3;
-	be16_t  recovery_time_limit;
+	be16_t recovery_time_limit;
 };
+//@}
 
 /**
- * \brief SBC-2 READ CAPACITY (10) parameter data (8 bytes)
- * \note Fields are MSB first (BE)
+ * \brief SBC-2 READ CAPACITY (10) parameter data
  */
 struct sbc_read_capacity10_data {
-	be32_t max_lba;   /**< LBA of last logical block (BE32) */
-	be32_t block_len; /**< Number of bytes in the last logical block (BE32) */
+	be32_t max_lba;	//!< LBA of last logical block
+	be32_t block_len;	//!< Number of bytes in the last logical block
 };
 
-#endif /*_SBC_PROTOCOL_H_*/
+//@}
+
+#endif // _SBC_PROTOCOL_H_

asf/common/services/usb/class/msc/spc_protocol.h

@@ -0,0 +1,337 @@
+/**
+ * \file
+ *
+ * \brief SCSI Primary Commands
+ *
+ * This file contains definitions of some of the commands found in the
+ * SPC-2 standard.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef  _SPC_PROTOCOL_H_
+#define  _SPC_PROTOCOL_H_
+
+
+/**
+ * \ingroup usb_msc_protocol
+ * \defgroup usb_spc_protocol SCSI Primary Commands protocol definitions
+ *
+ * @{
+ */
+
+//! \name SCSI commands defined by SPC-2
+//@{
+#define  SPC_TEST_UNIT_READY              0x00
+#define  SPC_REQUEST_SENSE                0x03
+#define  SPC_INQUIRY                      0x12
+#define  SPC_MODE_SELECT6                 0x15
+#define  SPC_MODE_SENSE6                  0x1A
+#define  SPC_SEND_DIAGNOSTIC              0x1D
+#define  SPC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E
+#define  SPC_MODE_SENSE10                 0x5A
+#define  SPC_REPORT_LUNS                  0xA0
+//@}
+
+//! \brief May be set in byte 0 of the INQUIRY CDB
+//@{
+//! Enable Vital Product Data
+#define  SCSI_INQ_REQ_EVPD    0x01
+//! Command Support Data specified by the PAGE OR OPERATION CODE field
+#define  SCSI_INQ_REQ_CMDT    0x02
+//@}
+
+COMPILER_PACK_SET(1)
+
+/**
+ * \brief SCSI Standard Inquiry data structure
+ */
+struct scsi_inquiry_data {
+	uint8_t pq_pdt; //!< Peripheral Qual / Peripheral Dev Type
+#define  SCSI_INQ_PQ_CONNECTED   0x00   //!< Peripheral connected
+#define  SCSI_INQ_PQ_NOT_CONN    0x20   //!< Peripheral not connected
+#define  SCSI_INQ_PQ_NOT_SUPP    0x60   //!< Peripheral not supported
+#define  SCSI_INQ_DT_DIR_ACCESS  0x00   //!< Direct Access (SBC)
+#define  SCSI_INQ_DT_SEQ_ACCESS  0x01   //!< Sequential Access
+#define  SCSI_INQ_DT_PRINTER     0x02   //!< Printer
+#define  SCSI_INQ_DT_PROCESSOR   0x03   //!< Processor device
+#define  SCSI_INQ_DT_WRITE_ONCE  0x04   //!< Write-once device
+#define  SCSI_INQ_DT_CD_DVD      0x05   //!< CD/DVD device
+#define  SCSI_INQ_DT_OPTICAL     0x07   //!< Optical Memory
+#define  SCSI_INQ_DT_MC          0x08   //!< Medium Changer
+#define  SCSI_INQ_DT_ARRAY       0x0c   //!< Storage Array Controller
+#define  SCSI_INQ_DT_ENCLOSURE   0x0d   //!< Enclosure Services
+#define  SCSI_INQ_DT_RBC         0x0e   //!< Simplified Direct Access
+#define  SCSI_INQ_DT_OCRW        0x0f   //!< Optical card reader/writer
+#define  SCSI_INQ_DT_BCC         0x10   //!< Bridge Controller Commands
+#define  SCSI_INQ_DT_OSD         0x11   //!< Object-based Storage
+#define  SCSI_INQ_DT_NONE        0x1f   //!< No Peripheral
+	uint8_t flags1; //!< Flags (byte 1)
+#define  SCSI_INQ_RMB            0x80   //!< Removable Medium
+	uint8_t version; //!< Version
+#define  SCSI_INQ_VER_NONE       0x00   //!< No standards conformance
+#define  SCSI_INQ_VER_SPC        0x03   //!< SCSI Primary Commands     (link to SBC)
+#define  SCSI_INQ_VER_SPC2       0x04   //!< SCSI Primary Commands - 2 (link to SBC-2)
+#define  SCSI_INQ_VER_SPC3       0x05   //!< SCSI Primary Commands - 3 (link to SBC-2)
+#define  SCSI_INQ_VER_SPC4       0x06   //!< SCSI Primary Commands - 4 (link to SBC-3)
+	uint8_t flags3; //!< Flags (byte 3)
+#define  SCSI_INQ_NORMACA        0x20   //!< Normal ACA Supported
+#define  SCSI_INQ_HISUP          0x10   //!< Hierarchal LUN addressing
+#define  SCSI_INQ_RSP_SPC2       0x02   //!< SPC-2 / SPC-3 response format
+	uint8_t addl_len; //!< Additional Length (n-4)
+#define  SCSI_INQ_ADDL_LEN(tot)  ((tot)-5) //!< Total length is \a tot
+	uint8_t flags5; //!< Flags (byte 5)
+#define  SCSI_INQ_SCCS           0x80
+	uint8_t flags6; //!< Flags (byte 6)
+#define  SCSI_INQ_BQUE           0x80
+#define  SCSI_INQ_ENCSERV        0x40
+#define  SCSI_INQ_MULTIP         0x10
+#define  SCSI_INQ_MCHGR          0x08
+#define  SCSI_INQ_ADDR16         0x01
+	uint8_t flags7; //!< Flags (byte 7)
+#define  SCSI_INQ_WBUS16         0x20
+#define  SCSI_INQ_SYNC           0x10
+#define  SCSI_INQ_LINKED         0x08
+#define  SCSI_INQ_CMDQUE         0x02
+	uint8_t vendor_id[8];   //!< T10 Vendor Identification
+	uint8_t product_id[16]; //!< Product Identification
+	uint8_t product_rev[4]; //!< Product Revision Level
+};
+
+/**
+ * \brief SCSI Standard Request sense data structure
+ */
+struct scsi_request_sense_data {
+	/* 1st byte: REQUEST SENSE response flags*/
+	uint8_t valid_reponse_code;
+#define  SCSI_SENSE_VALID              0x80 //!< Indicates the INFORMATION field contains valid information
+#define  SCSI_SENSE_RESPONSE_CODE_MASK 0x7F
+#define  SCSI_SENSE_CURRENT            0x70 //!< Response code 70h (current errors)
+#define  SCSI_SENSE_DEFERRED           0x71
+
+	/* 2nd byte */
+	uint8_t obsolete;
+
+	/* 3rd byte */
+	uint8_t sense_flag_key;
+#define  SCSI_SENSE_FILEMARK        0x80 //!< Indicates that the current command has read a filemark or setmark.
+#define  SCSI_SENSE_EOM             0x40 //!< Indicates that an end-of-medium condition exists.
+#define  SCSI_SENSE_ILI             0x20 //!< Indicates that the requested logical block length did not match the logical block length of the data on the medium.
+#define  SCSI_SENSE_RESERVED        0x10 //!< Reserved
+#define  SCSI_SENSE_KEY(x)          (x&0x0F) //!< Sense Key
+
+	/* 4th to 7th bytes - INFORMATION field */
+	uint8_t information[4];
+
+	/* 8th byte  - ADDITIONAL SENSE LENGTH field */
+	uint8_t AddSenseLen;
+#define  SCSI_SENSE_ADDL_LEN(total_len)   ((total_len) - 8)
+
+	/* 9th to 12th byte  - COMMAND-SPECIFIC INFORMATION field */
+	uint8_t CmdSpecINFO[4];
+
+	/* 13th byte  - ADDITIONAL SENSE CODE field */
+	uint8_t AddSenseCode;
+
+	/* 14th byte  - ADDITIONAL SENSE CODE QUALIFIER field */
+	uint8_t AddSnsCodeQlfr;
+
+	/* 15th byte  - FIELD REPLACEABLE UNIT CODE field */
+	uint8_t FldReplUnitCode;
+
+	/* 16th byte */
+	uint8_t SenseKeySpec[3];
+#define  SCSI_SENSE_SKSV            0x80 //!< Indicates the SENSE-KEY SPECIFIC field contains valid information
+};
+
+COMPILER_PACK_RESET()
+
+/* Vital Product Data page codes */
+enum scsi_vpd_page_code {
+	SCSI_VPD_SUPPORTED_PAGES = 0x00,
+	SCSI_VPD_UNIT_SERIAL_NUMBER = 0x80,
+	SCSI_VPD_DEVICE_IDENTIFICATION = 0x83,
+};
+#define  SCSI_VPD_HEADER_SIZE       4
+
+/* Constants associated with the Device Identification VPD page */
+#define  SCSI_VPD_ID_HEADER_SIZE    4
+
+#define  SCSI_VPD_CODE_SET_BINARY   1
+#define  SCSI_VPD_CODE_SET_ASCII    2
+#define  SCSI_VPD_CODE_SET_UTF8     3
+
+#define  SCSI_VPD_ID_TYPE_T10       1
+
+
+/* Sense keys */
+enum scsi_sense_key {
+	SCSI_SK_NO_SENSE = 0x0,
+	SCSI_SK_RECOVERED_ERROR = 0x1,
+	SCSI_SK_NOT_READY = 0x2,
+	SCSI_SK_MEDIUM_ERROR = 0x3,
+	SCSI_SK_HARDWARE_ERROR = 0x4,
+	SCSI_SK_ILLEGAL_REQUEST = 0x5,
+	SCSI_SK_UNIT_ATTENTION = 0x6,
+	SCSI_SK_DATA_PROTECT = 0x7,
+	SCSI_SK_BLANK_CHECK = 0x8,
+	SCSI_SK_VENDOR_SPECIFIC = 0x9,
+	SCSI_SK_COPY_ABORTED = 0xa,
+	SCSI_SK_ABORTED_COMMAND = 0xb,
+	SCSI_SK_VOLUME_OVERFLOW = 0xd,
+	SCSI_SK_MISCOMPARE = 0xe,
+};
+
+/* Additional Sense Code / Additional Sense Code Qualifier pairs */
+enum scsi_asc_ascq {
+	SCSI_ASC_NO_ADDITIONAL_SENSE_INFO = 0x0000,
+	SCSI_ASC_LU_NOT_READY_REBUILD_IN_PROGRESS = 0x0405,
+	SCSI_ASC_WRITE_ERROR = 0x0c00,
+	SCSI_ASC_UNRECOVERED_READ_ERROR = 0x1100,
+	SCSI_ASC_INVALID_COMMAND_OPERATION_CODE = 0x2000,
+	SCSI_ASC_INVALID_FIELD_IN_CDB = 0x2400,
+	SCSI_ASC_WRITE_PROTECTED = 0x2700,
+	SCSI_ASC_NOT_READY_TO_READY_CHANGE = 0x2800,
+	SCSI_ASC_MEDIUM_NOT_PRESENT = 0x3A00,
+	SCSI_ASC_INTERNAL_TARGET_FAILURE = 0x4400,
+};
+
+/**
+ * \brief SPC-2 Mode parameter
+ * This subclause describes the block descriptors and the pages
+ * used with MODE SELECT and MODE SENSE commands
+ * that are applicable to all SCSI devices.
+ */
+enum scsi_spc_mode {
+	SCSI_MS_MODE_VENDOR_SPEC = 0x00,
+	SCSI_MS_MODE_INFEXP = 0x1C,    // Informational exceptions control page
+	SCSI_MS_MODE_ALL = 0x3f,
+};
+
+/**
+ * \brief SPC-2 Informational exceptions control page
+ * See chapter 8.3.8
+ */
+struct spc_control_page_info_execpt {
+	uint8_t page_code;
+	uint8_t page_length;
+#define  SPC_MP_INFEXP_PAGE_LENGTH     0x0A
+	uint8_t flags1;
+#define  SPC_MP_INFEXP_PERF            (1<<7)   //!< Initiator Control
+#define  SPC_MP_INFEXP_EBF             (1<<5)   //!< Caching Analysis Permitted
+#define  SPC_MP_INFEXP_EWASC           (1<<4)   //!< Discontinuity
+#define  SPC_MP_INFEXP_DEXCPT          (1<<3)   //!< Size enable
+#define  SPC_MP_INFEXP_TEST            (1<<2)   //!< Writeback Cache Enable
+#define  SPC_MP_INFEXP_LOGERR          (1<<0)   //!< Log errors bit
+	uint8_t mrie;
+#define  SPC_MP_INFEXP_MRIE_NO_REPORT           0x00
+#define  SPC_MP_INFEXP_MRIE_ASYNC_EVENT         0x01
+#define  SPC_MP_INFEXP_MRIE_GEN_UNIT            0x02
+#define  SPC_MP_INFEXP_MRIE_COND_RECOV_ERROR    0x03
+#define  SPC_MP_INFEXP_MRIE_UNCOND_RECOV_ERROR  0x04
+#define  SPC_MP_INFEXP_MRIE_NO_SENSE            0x05
+#define  SPC_MP_INFEXP_MRIE_ONLY_REPORT         0x06
+	be32_t interval_timer;
+	be32_t report_count;
+};
+
+
+enum scsi_spc_mode_sense_pc {
+	SCSI_MS_SENSE_PC_CURRENT = 0,
+	SCSI_MS_SENSE_PC_CHANGEABLE = 1,
+	SCSI_MS_SENSE_PC_DEFAULT = 2,
+	SCSI_MS_SENSE_PC_SAVED = 3,
+};
+
+
+
+static inline bool scsi_mode_sense_dbd_is_set(const uint8_t * cdb)
+{
+	return (cdb[1] >> 3) & 1;
+}
+
+static inline uint8_t scsi_mode_sense_get_page_code(const uint8_t * cdb)
+{
+	return cdb[2] & 0x3f;
+}
+
+static inline uint8_t scsi_mode_sense_get_pc(const uint8_t * cdb)
+{
+	return cdb[2] >> 6;
+}
+
+/**
+ * \brief SCSI Mode Parameter Header used by MODE SELECT(6) and MODE
+ * SENSE(6)
+ */
+struct scsi_mode_param_header6 {
+	uint8_t mode_data_length;	//!< Number of bytes after this
+	uint8_t medium_type;	//!< Medium Type
+	uint8_t device_specific_parameter;	//!< Defined by command set
+	uint8_t block_descriptor_length;	//!< Length of block descriptors
+};
+
+/**
+ * \brief SCSI Mode Parameter Header used by MODE SELECT(10) and MODE
+ * SENSE(10)
+ */
+struct scsi_mode_param_header10 {
+	be16_t mode_data_length;	//!< Number of bytes after this
+	uint8_t medium_type;	//!< Medium Type
+	uint8_t device_specific_parameter;	//!< Defined by command set
+	uint8_t flags4;	//!< LONGLBA in bit 0
+	uint8_t reserved;
+	be16_t block_descriptor_length;	//!< Length of block descriptors
+};
+
+/**
+ * \brief SCSI Page_0 Mode Page header (SPF not set)
+ */
+struct scsi_mode_page_0_header {
+	uint8_t page_code;
+#define  SCSI_PAGE_CODE_PS          (1 << 7)	//!< Parameters Saveable
+#define  SCSI_PAGE_CODE_SPF         (1 << 6)	//!< SubPage Format
+	uint8_t page_length;	//!< Number of bytes after this
+#define  SCSI_MS_PAGE_LEN(total)   ((total) - 2)
+};
+
+//@}
+
+#endif // SPC_PROTOCOL_H_

asf/common/services/usb/class/msc/usb_protocol_msc.h

@@ -0,0 +1,147 @@
+/**
+ * \file
+ *
+ * \brief USB Mass Storage Class (MSC) protocol definitions.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _USB_PROTOCOL_MSC_H_
+#define _USB_PROTOCOL_MSC_H_
+
+
+/**
+ * \ingroup usb_protocol_group
+ * \defgroup usb_msc_protocol USB Mass Storage Class (MSC) protocol definitions
+ *
+ * @{
+ */
+
+/**
+ * \name Possible Class value
+ */
+//@{
+#define  MSC_CLASS                  0x08
+//@}
+
+/**
+ * \name Possible SubClass value
+ * \note In practise, most devices should use
+ * #MSC_SUBCLASS_TRANSPARENT and specify the actual command set in
+ * the standard INQUIRY data block, even if the MSC spec indicates
+ * otherwise. In particular, RBC is not supported by certain major
+ * operating systems like Windows XP.
+ */
+//@{
+#define  MSC_SUBCLASS_RBC           0x01	//!< Reduced Block Commands
+#define  MSC_SUBCLASS_ATAPI         0x02	//!< CD/DVD devices
+#define  MSC_SUBCLASS_QIC_157       0x03	//!< Tape devices
+#define  MSC_SUBCLASS_UFI           0x04	//!< Floppy disk drives
+#define  MSC_SUBCLASS_SFF_8070I     0x05	//!< Floppy disk drives
+#define  MSC_SUBCLASS_TRANSPARENT   0x06	//!< Determined by INQUIRY
+//@}
+
+/**
+ * \name Possible protocol value
+ * \note Only the BULK protocol should be used in new designs.
+ */
+//@{
+#define  MSC_PROTOCOL_CBI           0x00	//!< Command/Bulk/Interrupt
+#define  MSC_PROTOCOL_CBI_ALT       0x01	//!< W/o command completion
+#define  MSC_PROTOCOL_BULK          0x50	//!< Bulk-only
+//@}
+
+
+/**
+ * \brief MSC USB requests (bRequest)
+ */
+enum usb_reqid_msc {
+	USB_REQ_MSC_BULK_RESET = 0xFF,	//!< Mass Storage Reset
+	USB_REQ_MSC_GET_MAX_LUN = 0xFE,	//!< Get Max LUN
+};
+
+
+COMPILER_PACK_SET(1)
+
+/**
+ * \name A Command Block Wrapper (CBW).
+ */
+//@{
+struct usb_msc_cbw {
+	le32_t dCBWSignature;	//!< Must contain 'USBC'
+	le32_t dCBWTag;	//!< Unique command ID
+	le32_t dCBWDataTransferLength;	//!< Number of bytes to transfer
+	uint8_t bmCBWFlags;	//!< Direction in bit 7
+	uint8_t bCBWLUN;	//!< Logical Unit Number
+	uint8_t bCBWCBLength;	//!< Number of valid CDB bytes
+	uint8_t CDB[16];	//!< SCSI Command Descriptor Block
+};
+
+#define  USB_CBW_SIGNATURE          0x55534243	//!< dCBWSignature value
+#define  USB_CBW_DIRECTION_IN       (1<<7)	//!< Data from device to host
+#define  USB_CBW_DIRECTION_OUT      (0<<7)	//!< Data from host to device
+#define  USB_CBW_LUN_MASK           0x0F	//!< Valid bits in bCBWLUN
+#define  USB_CBW_LEN_MASK           0x1F	//!< Valid bits in bCBWCBLength
+//@}
+
+
+/**
+ * \name A Command Status Wrapper (CSW).
+ */
+//@{
+struct usb_msc_csw {
+	le32_t dCSWSignature;	//!< Must contain 'USBS'
+	le32_t dCSWTag;	//!< Same as dCBWTag
+	le32_t dCSWDataResidue;	//!< Number of bytes not transfered
+	uint8_t bCSWStatus;	//!< Status code
+};
+
+#define  USB_CSW_SIGNATURE          0x55534253	//!< dCSWSignature value
+#define  USB_CSW_STATUS_PASS        0x00	//!< Command Passed
+#define  USB_CSW_STATUS_FAIL        0x01	//!< Command Failed
+#define  USB_CSW_STATUS_PE          0x02	//!< Phase Error
+//@}
+
+COMPILER_PACK_RESET()
+
+//@}
+
+#endif // _USB_PROTOCOL_MSC_H_

asf/common/services/usb/udc/udc.h

@@ -0,0 +1,697 @@
+/**
+ * \file
+ *
+ * \brief Interface of the USB Device Controller (UDC)
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _UDC_H_
+#define _UDC_H_
+
+#include "conf_usb.h"
+#include "usb_protocol.h"
+#include "udc_desc.h"
+#include "udd.h"
+
+#if USB_DEVICE_VENDOR_ID == 0
+#   error USB_DEVICE_VENDOR_ID cannot be equal to 0
+#endif
+
+#if USB_DEVICE_PRODUCT_ID == 0
+#   error USB_DEVICE_PRODUCT_ID cannot be equal to 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup usb_device_group
+ * \defgroup udc_group USB Device Controller (UDC)
+ *
+ * The UDC provides a high-level abstraction of the usb device.
+ * You can use these functions to control the main device state
+ * (start/attach/wakeup).
+ *
+ * \section USB_DEVICE_CONF USB Device Custom configuration
+ * The following USB Device configuration must be included in the conf_usb.h
+ * file of the application.
+ *
+ * USB_DEVICE_VENDOR_ID (Word)<br>
+ * Vendor ID provided by USB org (ATMEL 0x03EB).
+ *
+ * USB_DEVICE_PRODUCT_ID (Word)<br>
+ * Product ID (Referenced in usb_atmel.h).
+ *
+ * USB_DEVICE_MAJOR_VERSION (Byte)<br>
+ * Major version of the device
+ *
+ * USB_DEVICE_MINOR_VERSION (Byte)<br>
+ * Minor version of the device
+ *
+ * USB_DEVICE_MANUFACTURE_NAME (string)<br>
+ * ASCII name for the manufacture
+ *
+ * USB_DEVICE_PRODUCT_NAME (string)<br>
+ * ASCII name for the product
+ *
+ * USB_DEVICE_SERIAL_NAME (string)<br>
+ * ASCII name to enable and set a serial number
+ *
+ * USB_DEVICE_POWER (Numeric)<br>
+ * (unit mA) Maximum device power
+ *
+ * USB_DEVICE_ATTR (Byte)<br>
+ * USB attributes available:
+ *  - USB_CONFIG_ATTR_SELF_POWERED
+ *  - USB_CONFIG_ATTR_REMOTE_WAKEUP
+ *  Note: if remote wake enabled then defines remotewakeup callbacks,
+ * see Table 5-2. External API from UDC - Callback
+ *
+ * USB_DEVICE_LOW_SPEED (Only defined)<br>
+ * Force the USB Device to run in low speed
+ *
+ * USB_DEVICE_HS_SUPPORT (Only defined)<br>
+ * Authorize the USB Device to run in high speed
+ *
+ * USB_DEVICE_MAX_EP (Byte)<br>
+ * Define the maximum endpoint number used by the USB Device.<br>
+ * This one is already defined in UDI default configuration.
+ * Ex:
+ * - When endpoint control 0x00, endpoint 0x01 and
+ *   endpoint 0x82 is used then USB_DEVICE_MAX_EP=2
+ * - When only endpoint control 0x00 is used then USB_DEVICE_MAX_EP=0
+ * - When endpoint 0x01 and endpoint 0x81 is used then USB_DEVICE_MAX_EP=1<br>
+ *   (configuration not possible on USBB interface)
+ * @{
+ */
+
+/**
+ * \brief Authorizes the VBUS event
+ *
+ * \return true, if the VBUS monitoring is possible.
+ *
+ * \section udc_vbus_monitoring VBus monitoring used cases
+ *
+ * The VBus monitoring is used only for USB SELF Power application.
+ *
+ * - By default the USB device is automatically attached when Vbus is high
+ * or when USB is start for devices without internal Vbus monitoring.
+ * conf_usb.h file does not contains define USB_DEVICE_ATTACH_AUTO_DISABLE.
+ * \code //#define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode
+ *
+ * - Add custom VBUS monitoring. conf_usb.h file contains define
+ * USB_DEVICE_ATTACH_AUTO_DISABLE:
+ * \code #define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode
+ * User C file contains:
+ * \code  
+	// Authorize VBUS monitoring
+	if (!udc_include_vbus_monitoring()) {
+	  // Implement custom VBUS monitoring via GPIO or other
+	}
+	Event_VBUS_present() // VBUS interrupt or GPIO interrupt or other
+	{
+	  // Attach USB Device
+	  udc_attach();
+	}
+\endcode
+ *
+ * - Case of battery charging. conf_usb.h file contains define
+ * USB_DEVICE_ATTACH_AUTO_DISABLE:
+ * \code #define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode
+ * User C file contains:
+ * \code  
+	Event VBUS present() // VBUS interrupt or GPIO interrupt or ..
+	{
+	  // Authorize battery charging, but wait key press to start USB.
+	}
+	Event Key press()
+	{
+	  // Stop batteries charging
+	  // Start USB
+	  udc_attach();
+	}
+\endcode
+ */
+static inline bool udc_include_vbus_monitoring(void)
+{
+	return udd_include_vbus_monitoring();
+}
+
+/*! \brief Start the USB Device stack
+ */
+void udc_start(void);
+
+/*! \brief Stop the USB Device stack
+ */
+void udc_stop(void);
+
+/**
+ * \brief Attach device to the bus when possible
+ *
+ * \warning If a VBus control is included in driver,
+ * then it will attach device when an acceptable Vbus
+ * level from the host is detected.
+ */
+static inline void udc_attach(void)
+{
+	udd_attach();
+}
+
+
+/**
+ * \brief Detaches the device from the bus
+ *
+ * The driver must remove pull-up on USB line D- or D+.
+ */
+static inline void udc_detach(void)
+{
+	udd_detach();
+}
+
+
+/*! \brief The USB driver sends a resume signal called \e "Upstream Resume"
+ * This is authorized only when the remote wakeup feature is enabled by host.
+ */
+static inline void udc_remotewakeup(void)
+{
+	udd_send_remotewakeup();
+}
+
+
+/**
+ * \brief Returns a pointer on the current interface descriptor
+ *
+ * \return pointer on the current interface descriptor.
+ */
+usb_iface_desc_t UDC_DESC_STORAGE *udc_get_interface_desc(void);
+
+//@}
+
+/**
+ * \ingroup usb_group
+ * \defgroup usb_device_group USB Stack Device
+ *
+ * This module includes USB Stack Device implementation.
+ * The stack is divided in three parts:
+ * - USB Device Controller (UDC) provides USB chapter 9 compliance
+ * - USB Device Interface (UDI) provides USB Class compliance
+ * - USB Device Driver (UDD) provides USB Driver for each Atmel MCU
+
+ * Many USB Device applications can be implemented on Atmel MCU.
+ * Atmel provides many application notes for different applications:
+ * - AVR4900, provides general information about Device Stack
+ * - AVR4901, explains how to create a new class
+ * - AVR4902, explains how to create a composite device
+ * - AVR49xx, all device classes provided in ASF have an application note
+ *
+ * A basic USB knowledge is required to understand the USB Device
+ * Class application notes (HID,MS,CDC,PHDC,...).
+ * Then, to create an USB device with
+ * only one class provided by ASF, refer directly to the application note
+ * corresponding to this USB class. The USB Device application note for
+ * New Class and Composite is dedicated to advanced USB users.
+ *
+ * @{
+ */
+
+//! @}
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \ingroup udc_group
+ * \defgroup udc_basic_use_case_setup_prereq USB Device Controller (UDC) - Prerequisites
+ * Common prerequisites for all USB devices.
+ *
+ * This module is based on USB device stack full interrupt driven, and supporting
+ * \ref sleepmgr_group sleepmgr. For AVR and SAM3/4 devices the \ref clk_group clock services
+ * is supported. For SAMD devices the \ref asfdoc_sam0_system_clock_group clock driver is supported.
+ *
+ * The following procedure must be executed to setup the project correctly:
+ * - Specify the clock configuration:
+ *   - XMEGA USB devices need 48MHz clock input.\n
+ *     XMEGA USB devices need CPU frequency higher than 12MHz.\n
+ *     You can use either an internal RC48MHz auto calibrated by Start of Frames
+ *     or an external OSC.
+ *   - UC3 and SAM3/4 devices without USB high speed support need 48MHz clock input.\n
+ *     You must use a PLL and an external OSC.
+ *   - UC3 and SAM3/4 devices with USB high speed support need 12MHz clock input.\n
+ *     You must use an external OSC.
+ *   - UC3 devices with USBC hardware need CPU frequency higher than 25MHz.
+ *   - SAMD devices without USB high speed support need 48MHz clock input.\n
+ *     You should use DFLL with USBCRM.
+ * - In conf_board.h, the define CONF_BOARD_USB_PORT must be added to enable USB lines.
+ * (Not mandatory for all boards)
+ * - Enable interrupts
+ * - Initialize the clock service
+ *
+ * The usage of \ref sleepmgr_group sleepmgr service is optional, but recommended to reduce power
+ * consumption:
+ * - Initialize the sleep manager service
+ * - Activate sleep mode when the application is in IDLE state
+ *
+ * \subpage udc_conf_clock.
+ *
+ * for AVR and SAM3/4 devices, add to the initialization code:
+ * \code
+	sysclk_init();
+	irq_initialize_vectors();
+	cpu_irq_enable();
+	board_init();
+	sleepmgr_init(); // Optional
+\endcode
+ *
+ * For SAMD devices, add to the initialization code:
+ * \code
+	system_init();
+	irq_initialize_vectors();
+	cpu_irq_enable();
+	sleepmgr_init(); // Optional
+\endcode
+ * Add to the main IDLE loop:
+ * \code
+	sleepmgr_enter_sleep(); // Optional
+\endcode
+ *
+ */
+
+/**
+ * \ingroup udc_group
+ * \defgroup udc_basic_use_case_setup_code USB Device Controller (UDC) - Example code
+ * Common example code for all USB devices.
+ *
+ * Content of conf_usb.h:
+ * \code
+	#define USB_DEVICE_VENDOR_ID 0x03EB
+	#define USB_DEVICE_PRODUCT_ID 0xXXXX
+	#define USB_DEVICE_MAJOR_VERSION 1
+	#define USB_DEVICE_MINOR_VERSION 0
+	#define USB_DEVICE_POWER 100
+	#define USB_DEVICE_ATTR USB_CONFIG_ATTR_BUS_POWERED
+\endcode
+ *
+ * Add to application C-file:
+ * \code
+	void usb_init(void)
+	{
+	  udc_start();
+	}
+\endcode
+ */
+
+/**
+ * \ingroup udc_group
+ * \defgroup udc_basic_use_case_setup_flow USB Device Controller (UDC) - Workflow
+ * Common workflow for all USB devices.
+ *
+ * -# Ensure that conf_usb.h is available and contains the following configuration
+ * which is the main USB device configuration:
+ *   - \code // Vendor ID provided by USB org (ATMEL 0x03EB)
+	#define USB_DEVICE_VENDOR_ID 0x03EB // Type Word
+	// Product ID (Atmel PID referenced in usb_atmel.h)
+	#define USB_DEVICE_PRODUCT_ID 0xXXXX // Type Word
+	// Major version of the device
+	#define USB_DEVICE_MAJOR_VERSION 1 // Type Byte
+	// Minor version of the device
+	#define USB_DEVICE_MINOR_VERSION 0 // Type Byte
+	// Maximum device power (mA)
+	#define USB_DEVICE_POWER 100 // Type 9-bits
+	// USB attributes to enable features
+	#define USB_DEVICE_ATTR USB_CONFIG_ATTR_BUS_POWERED // Flags \endcode
+ * -# Call the USB device stack start function to enable stack and start USB:
+ *   - \code udc_start(); \endcode
+ *     \note In case of USB dual roles (Device and Host) managed through USB OTG connector
+ * (USB ID pin), the call of udc_start() must be removed and replaced by uhc_start().
+ * SeRefer to "AVR4950 section 6.1 Dual roles" for further information about dual roles.
+ */
+
+/**
+ * \page udc_conf_clock conf_clock.h examples with USB support
+ *
+ * Content of XMEGA conf_clock.h:
+ * \code
+	// Configuration based on internal RC:
+	// USB clock need of 48Mhz
+	#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_RCOSC
+	#define CONFIG_OSC_RC32_CAL         48000000UL
+	#define CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC  OSC_ID_USBSOF
+	// CPU clock need of clock > 12MHz to run with USB (Here 24MHz)
+	#define CONFIG_SYSCLK_SOURCE     SYSCLK_SRC_RC32MHZ
+	#define CONFIG_SYSCLK_PSADIV     SYSCLK_PSADIV_2
+	#define CONFIG_SYSCLK_PSBCDIV    SYSCLK_PSBCDIV_1_1
+\endcode
+ *
+ * Content of conf_clock.h for AT32UC3A0, AT32UC3A1, AT32UC3B devices (USBB):
+ * \code
+	// Configuration based on 12MHz external OSC:
+	#define CONFIG_PLL1_SOURCE          PLL_SRC_OSC0
+	#define CONFIG_PLL1_MUL             8
+	#define CONFIG_PLL1_DIV             2
+	#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_PLL1
+	#define CONFIG_USBCLK_DIV           1 // Fusb = Fsys/(2 ^ USB_div)
+\endcode
+ *
+ * Content of conf_clock.h for AT32UC3A3, AT32UC3A4 devices (USBB with high speed support):
+ * \code
+	// Configuration based on 12MHz external OSC:
+	#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_OSC0
+	#define CONFIG_USBCLK_DIV           1 // Fusb = Fsys/(2 ^ USB_div)
+\endcode
+ *
+ * Content of conf_clock.h for AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U devices (USBC):
+ * \code
+	// Configuration based on 12MHz external OSC:
+	#define CONFIG_PLL1_SOURCE          PLL_SRC_OSC0
+	#define CONFIG_PLL1_MUL             8
+	#define CONFIG_PLL1_DIV             2
+	#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_PLL1
+	#define CONFIG_USBCLK_DIV           1 // Fusb = Fsys/(2 ^ USB_div)
+	// CPU clock need of clock > 25MHz to run with USBC
+	#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLL1
+\endcode
+ *
+ * Content of conf_clock.h for SAM3S, SAM3SD, SAM4S devices (UPD: USB Peripheral Device):
+ * \code
+	// PLL1 (B) Options   (Fpll = (Fclk * PLL_mul) / PLL_div)
+	#define CONFIG_PLL1_SOURCE          PLL_SRC_MAINCK_XTAL
+	#define CONFIG_PLL1_MUL             16
+	#define CONFIG_PLL1_DIV             2
+	// USB Clock Source Options   (Fusb = FpllX / USB_div)
+	#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_PLL1
+	#define CONFIG_USBCLK_DIV           2
+\endcode
+ *
+ * Content of conf_clock.h for SAM3U device (UPDHS: USB Peripheral Device High Speed):
+ * \code
+	// USB Clock Source fixed at UPLL.
+\endcode
+ *
+ * Content of conf_clock.h for SAM3X, SAM3A devices (UOTGHS: USB OTG High Speed):
+ * \code
+	// USB Clock Source fixed at UPLL.
+	#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_UPLL
+	#define CONFIG_USBCLK_DIV           1
+\endcode
+ *
+ * Content of conf_clocks.h for SAMD devices (USB):
+ * \code
+	// System clock bus configuration
+	#  define CONF_CLOCK_FLASH_WAIT_STATES            2
+
+	// USB Clock Source fixed at DFLL.
+	// SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop
+	#  define CONF_CLOCK_DFLL_ENABLE                  true
+	#  define CONF_CLOCK_DFLL_LOOP_MODE               SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY
+	#  define CONF_CLOCK_DFLL_ON_DEMAND               true
+
+	// Set this to true to configure the GCLK when running clocks_init. 
+	// If set to false, none of the GCLK generators will be configured in clocks_init().
+	#  define CONF_CLOCK_CONFIGURE_GCLK               true
+
+	// Configure GCLK generator 0 (Main Clock)
+	#  define CONF_CLOCK_GCLK_0_ENABLE                true
+	#  define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY        true
+	#  define CONF_CLOCK_GCLK_0_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_DFLL
+	#  define CONF_CLOCK_GCLK_0_PRESCALER             1
+	#  define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE         false
+\endcode
+ */
+
+/**
+ * \page udc_use_case_1 Change USB speed
+ *
+ * In this use case, the USB device is used with different USB speeds.
+ *
+ * \section udc_use_case_1_setup Setup steps
+ *
+ * Prior to implement this use case, be sure to have already
+ * apply the UDI module "basic use case".
+ *
+ * \section udc_use_case_1_usage Usage steps
+ *
+ * \subsection udc_use_case_1_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+	 #if // Low speed
+	 #define USB_DEVICE_LOW_SPEED
+	 // #define USB_DEVICE_HS_SUPPORT
+
+	 #elif // Full speed
+	 // #define USB_DEVICE_LOW_SPEED
+	 // #define USB_DEVICE_HS_SUPPORT
+
+	 #elif // High speed
+	 // #define USB_DEVICE_LOW_SPEED
+	 #define USB_DEVICE_HS_SUPPORT
+
+	 #endif
+\endcode
+ *
+ * \subsection udc_use_case_1_usage_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following parameters
+ * required for a USB device low speed (1.5Mbit/s):
+ *   - \code #define USB_DEVICE_LOW_SPEED
+	 //#define  USB_DEVICE_HS_SUPPORT \endcode
+ * -# Ensure that conf_usb.h contains the following parameters
+ * required for a USB device full speed (12Mbit/s):
+ *   - \code //#define USB_DEVICE_LOW_SPEED
+	 //#define  USB_DEVICE_HS_SUPPORT \endcode
+ * -# Ensure that conf_usb.h contains the following parameters
+ * required for a USB device high speed (480Mbit/s):
+ *   - \code //#define USB_DEVICE_LOW_SPEED
+	 #define  USB_DEVICE_HS_SUPPORT \endcode
+ */
+
+/**
+ * \page udc_use_case_2 Use USB strings
+ *
+ * In this use case, the usual USB strings is added in the USB device.
+ *
+ * \section udc_use_case_2_setup Setup steps
+ * Prior to implement this use case, be sure to have already
+ * apply the UDI module "basic use case".
+ *
+ * \section udc_use_case_2_usage Usage steps
+ *
+ * \subsection udc_use_case_2_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+	#define  USB_DEVICE_MANUFACTURE_NAME      "Manufacture name"
+	#define  USB_DEVICE_PRODUCT_NAME          "Product name"
+	#define  USB_DEVICE_SERIAL_NAME           "12...EF"
+\endcode
+ *
+ * \subsection udc_use_case_2_usage_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following parameters
+ * required to enable different USB strings:
+ *   - \code // Static ASCII name for the manufacture
+	#define  USB_DEVICE_MANUFACTURE_NAME "Manufacture name" \endcode
+ *   - \code // Static ASCII name for the product
+	#define  USB_DEVICE_PRODUCT_NAME "Product name" \endcode
+ *   - \code // Static ASCII name to enable and set a serial number
+	#define  USB_DEVICE_SERIAL_NAME "12...EF" \endcode
+ */
+
+/**
+ * \page udc_use_case_3 Use USB remote wakeup feature
+ *
+ * In this use case, the USB remote wakeup feature is enabled.
+ *
+ * \section udc_use_case_3_setup Setup steps
+ * Prior to implement this use case, be sure to have already
+ * apply the UDI module "basic use case".
+ *
+ * \section udc_use_case_3_usage Usage steps
+ *
+ * \subsection udc_use_case_3_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+	#define  USB_DEVICE_ATTR \
+	  (USB_CONFIG_ATTR_REMOTE_WAKEUP | USB_CONFIG_ATTR_..._POWERED)
+	#define UDC_REMOTEWAKEUP_ENABLE() my_callback_remotewakeup_enable()
+	extern void my_callback_remotewakeup_enable(void);
+	#define UDC_REMOTEWAKEUP_DISABLE() my_callback_remotewakeup_disable()
+	extern void my_callback_remotewakeup_disable(void);
+\endcode
+ *
+ * Add to application C-file:
+ * \code
+	 void my_callback_remotewakeup_enable(void)
+	 {
+	    // Enable application wakeup events (e.g. enable GPIO interrupt)
+	 }
+	 void my_callback_remotewakeup_disable(void)
+	 {
+	    // Disable application wakeup events (e.g. disable GPIO interrupt)
+	 }
+
+	 void my_interrupt_event(void)
+	 {
+	    udc_remotewakeup();
+	 }
+\endcode
+ *
+ * \subsection udc_use_case_3_usage_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following parameters
+ * required to enable remote wakeup feature:
+ *   - \code // Authorizes the remote wakeup feature
+	     #define  USB_DEVICE_ATTR (USB_CONFIG_ATTR_REMOTE_WAKEUP | USB_CONFIG_ATTR_..._POWERED) \endcode
+ *   - \code // Define callback called when the host enables the remotewakeup feature
+	#define UDC_REMOTEWAKEUP_ENABLE() my_callback_remotewakeup_enable()
+	extern void my_callback_remotewakeup_enable(void); \endcode
+ *   - \code // Define callback called when the host disables the remotewakeup feature
+	#define UDC_REMOTEWAKEUP_DISABLE() my_callback_remotewakeup_disable()
+	extern void my_callback_remotewakeup_disable(void); \endcode
+ * -# Send a remote wakeup (USB upstream):
+ *   - \code udc_remotewakeup(); \endcode
+ */
+
+/**
+ * \page udc_use_case_5 Bus power application recommendations
+ *
+ * In this use case, the USB device BUS power feature is enabled.
+ * This feature requires a correct power consumption management.
+ *
+ * \section udc_use_case_5_setup Setup steps
+ * Prior to implement this use case, be sure to have already
+ * apply the UDI module "basic use case".
+ *
+ * \section udc_use_case_5_usage Usage steps
+ *
+ * \subsection udc_use_case_5_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+	#define  USB_DEVICE_ATTR (USB_CONFIG_ATTR_BUS_POWERED)
+	#define  UDC_SUSPEND_EVENT()         user_callback_suspend_action()
+	extern void user_callback_suspend_action(void)
+	#define  UDC_RESUME_EVENT()          user_callback_resume_action()
+	extern void user_callback_resume_action(void)
+\endcode
+ *
+ * Add to application C-file:
+ * \code
+	void user_callback_suspend_action(void)
+	{
+	   // Disable hardware component to reduce power consumption
+	}
+	void user_callback_resume_action(void)
+	{
+	   // Re-enable hardware component
+	}
+\endcode
+ *
+ * \subsection udc_use_case_5_usage_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following parameters:
+ *   - \code // Authorizes the BUS power feature
+	#define  USB_DEVICE_ATTR (USB_CONFIG_ATTR_BUS_POWERED) \endcode
+ *   - \code // Define callback called when the host suspend the USB line
+	#define UDC_SUSPEND_EVENT() user_callback_suspend_action()
+	extern void user_callback_suspend_action(void); \endcode
+ *   - \code // Define callback called when the host or device resume the USB line
+	#define UDC_RESUME_EVENT() user_callback_resume_action()
+	extern void user_callback_resume_action(void); \endcode
+ * -# Reduce power consumption in suspend mode (max. 2.5mA on Vbus):
+ *   - \code void user_callback_suspend_action(void)
+	{
+	turn_off_components();
+	} \endcode
+ */
+
+/**
+ * \page udc_use_case_6 USB dynamic serial number
+ *
+ * In this use case, the USB serial strings is dynamic.
+ * For a static serial string refer to \ref udc_use_case_2.
+ *
+ * \section udc_use_case_6_setup Setup steps
+ * Prior to implement this use case, be sure to have already
+ * apply the UDI module "basic use case".
+ *
+ * \section udc_use_case_6_usage Usage steps
+ *
+ * \subsection udc_use_case_6_usage_code Example code
+ * Content of conf_usb.h:
+ * \code
+	#define  USB_DEVICE_SERIAL_NAME
+	#define  USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number
+	#define  USB_DEVICE_GET_SERIAL_NAME_LENGTH  12
+	extern uint8_t serial_number[];
+\endcode
+ *
+ * Add to application C-file:
+ * \code
+	 uint8_t serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH];
+
+	 void init_build_usb_serial_number(void)
+	 {
+	 serial_number[0] = 'A';
+	 serial_number[1] = 'B';
+	 ...
+	 serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH-1] = 'C';
+	 } \endcode
+ *
+ * \subsection udc_use_case_6_usage_flow Workflow
+ * -# Ensure that conf_usb.h is available and contains the following parameters
+ * required to enable a USB serial number strings dynamically:
+ *   - \code #define  USB_DEVICE_SERIAL_NAME // Define this empty
+	#define  USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number // Give serial array pointer
+	#define  USB_DEVICE_GET_SERIAL_NAME_LENGTH  12 // Give size of serial array
+	extern uint8_t serial_number[]; // Declare external serial array \endcode
+ * -# Before start USB stack, initialize the serial array
+ *   - \code
+	 uint8_t serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH];
+
+	 void init_build_usb_serial_number(void)
+	 {
+	 serial_number[0] = 'A';
+	 serial_number[1] = 'B';
+	 ...
+	 serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH-1] = 'C';
+	 } \endcode
+ */
+
+
+
+#endif // _UDC_H_

asf/common/services/usb/udc/udc_desc.h

@@ -0,0 +1,135 @@
+/**
+ * \file
+ *
+ * \brief Common API for USB Device Interface
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _UDC_DESC_H_
+#define _UDC_DESC_H_
+
+#include "conf_usb.h"
+#include "usb_protocol.h"
+#include "udi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup udc_group
+ * \defgroup udc_desc_group USB Device Descriptor
+ *
+ * @{
+ */
+
+/**
+ * \brief Defines the memory's location of USB descriptors
+ *
+ * By default the Descriptor is stored in RAM
+ * (UDC_DESC_STORAGE is defined empty).
+ *
+ * If you have need to free RAM space,
+ * it is possible to put descriptor in flash in following case:
+ * - USB driver authorize flash transfer (USBB on UC3 and USB on Mega)
+ * - USB Device is not high speed (UDC no need to change USB descriptors)
+ *
+ * For UC3 application used "const".
+ *
+ * For Mega application used "code".
+ */
+#define  UDC_DESC_STORAGE
+	// Descriptor storage in internal RAM
+#if (defined UDC_DATA_USE_HRAM_SUPPORT)
+#	if defined(__GNUC__)
+#		define UDC_DATA(x)              COMPILER_WORD_ALIGNED __attribute__((__section__(".data_hram0")))
+#		define UDC_BSS(x)               COMPILER_ALIGNED(x)   __attribute__((__section__(".bss_hram0")))
+#	elif defined(__ICCAVR32__)
+#		define UDC_DATA(x)              COMPILER_ALIGNED(x)   __data32
+#		define UDC_BSS(x)               COMPILER_ALIGNED(x)   __data32
+#	endif
+#else
+#	define UDC_DATA(x)              COMPILER_ALIGNED(x)
+#	define UDC_BSS(x)               COMPILER_ALIGNED(x)
+#endif
+
+
+
+/**
+ * \brief Configuration descriptor and UDI link for one USB speed
+ */
+typedef struct {
+	//! USB configuration descriptor
+	usb_conf_desc_t UDC_DESC_STORAGE *desc;
+	//! Array of UDI API pointer
+	udi_api_t UDC_DESC_STORAGE *UDC_DESC_STORAGE * udi_apis;
+} udc_config_speed_t;
+
+
+/**
+ * \brief All information about the USB Device
+ */
+typedef struct {
+	//! USB device descriptor for low or full speed
+	usb_dev_desc_t UDC_DESC_STORAGE *confdev_lsfs;
+	//! USB configuration descriptor and UDI API pointers for low or full speed
+	udc_config_speed_t UDC_DESC_STORAGE *conf_lsfs;
+#ifdef USB_DEVICE_HS_SUPPORT
+	//! USB device descriptor for high speed
+	usb_dev_desc_t UDC_DESC_STORAGE *confdev_hs;
+	//! USB device qualifier, only use in high speed mode
+	usb_dev_qual_desc_t UDC_DESC_STORAGE *qualifier;
+	//! USB configuration descriptor and UDI API pointers for high speed
+	udc_config_speed_t UDC_DESC_STORAGE *conf_hs;
+#endif
+	usb_dev_bos_desc_t UDC_DESC_STORAGE *conf_bos;
+} udc_config_t;
+
+//! Global variables of USB Device Descriptor and UDI links
+extern UDC_DESC_STORAGE udc_config_t udc_config;
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+#endif // _UDC_DESC_H_

asf/common/services/usb/udc/udd.h

@@ -0,0 +1,396 @@
+/**
+ * \file
+ *
+ * \brief Common API for USB Device Drivers (UDD)
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _UDD_H_
+#define _UDD_H_
+
+#include "usb_protocol.h"
+#include "udc_desc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup usb_device_group
+ * \defgroup udd_group USB Device Driver (UDD)
+ *
+ * The UDD driver provides a low-level abstraction of the device
+ * controller hardware. Most events coming from the hardware such as
+ * interrupts, which may cause the UDD to call into the UDC and UDI.
+ *
+ * @{
+ */
+
+//! \brief Endpoint identifier
+typedef uint8_t udd_ep_id_t;
+
+//! \brief Endpoint transfer status
+//! Returned in parameters of callback register via udd_ep_run routine.
+typedef enum {
+	UDD_EP_TRANSFER_OK = 0,
+	UDD_EP_TRANSFER_ABORT = 1,
+} udd_ep_status_t;
+
+/**
+ * \brief Global variable to give and record information of the setup request management
+ *
+ * This global variable allows to decode and response a setup request.
+ * It can be updated by udc_process_setup() from UDC or *setup() from UDIs.
+ */
+typedef struct {
+	//! Data received in USB SETUP packet
+	//! Note: The swap of "req.wValues" from uin16_t to le16_t is done by UDD.
+	usb_setup_req_t req;
+
+	//! Point to buffer to send or fill with data following SETUP packet
+	//! This buffer must be word align for DATA IN phase (use prefix COMPILER_WORD_ALIGNED for buffer)
+	uint8_t *payload;
+
+	//! Size of buffer to send or fill, and content the number of byte transfered
+	uint16_t payload_size;
+
+	//! Callback called after reception of ZLP from setup request
+	void (*callback) (void);
+
+	//! Callback called when the buffer given (.payload) is full or empty.
+	//! This one return false to abort data transfer, or true with a new buffer in .payload.
+	bool(*over_under_run) (void);
+} udd_ctrl_request_t;
+extern udd_ctrl_request_t udd_g_ctrlreq;
+
+//! Return true if the setup request \a udd_g_ctrlreq indicates IN data transfer
+#define  Udd_setup_is_in()       \
+      (USB_REQ_DIR_IN == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
+
+//! Return true if the setup request \a udd_g_ctrlreq indicates OUT data transfer
+#define  Udd_setup_is_out()      \
+      (USB_REQ_DIR_OUT == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
+
+//! Return the type of the SETUP request \a udd_g_ctrlreq. \see usb_reqtype.
+#define  Udd_setup_type()        \
+      (udd_g_ctrlreq.req.bmRequestType & USB_REQ_TYPE_MASK)
+
+//! Return the recipient of the SETUP request \a udd_g_ctrlreq. \see usb_recipient
+#define  Udd_setup_recipient()   \
+      (udd_g_ctrlreq.req.bmRequestType & USB_REQ_RECIP_MASK)
+
+/**
+ * \brief End of halt callback function type.
+ * Registered by routine udd_ep_wait_stall_clear()
+ * Callback called when endpoint stall is cleared.
+ */
+typedef void (*udd_callback_halt_cleared_t) (void);
+
+/**
+ * \brief End of transfer callback function type.
+ * Registered by routine udd_ep_run()
+ * Callback called by USB interrupt after data transfer or abort (reset,...).
+ *
+ * \param status     UDD_EP_TRANSFER_OK, if transfer is complete
+ * \param status     UDD_EP_TRANSFER_ABORT, if transfer is aborted
+ * \param n          number of data transfered
+ */
+typedef void (*udd_callback_trans_t) (udd_ep_status_t status,
+		iram_size_t nb_transfered, udd_ep_id_t ep);
+
+/**
+ * \brief Authorizes the VBUS event
+ *
+ * \return true, if the VBUS monitoring is possible.
+ */
+bool udd_include_vbus_monitoring(void);
+
+/**
+ * \brief Enables the USB Device mode
+ */
+void udd_enable(void);
+
+/**
+ * \brief Disables the USB Device mode
+ */
+void udd_disable(void);
+
+/**
+ * \brief Attach device to the bus when possible
+ *
+ * \warning If a VBus control is included in driver,
+ * then it will attach device when an acceptable Vbus
+ * level from the host is detected.
+ */
+void udd_attach(void);
+
+/**
+ * \brief Detaches the device from the bus
+ *
+ * The driver must remove pull-up on USB line D- or D+.
+ */
+void udd_detach(void);
+
+/**
+ * \brief Test whether the USB Device Controller is running at high
+ * speed or not.
+ *
+ * \return \c true if the Device is running at high speed mode, otherwise \c false.
+ */
+bool udd_is_high_speed(void);
+
+/**
+ * \brief Changes the USB address of device
+ *
+ * \param address    New USB address
+ */
+void udd_set_address(uint8_t address);
+
+/**
+ * \brief Returns the USB address of device
+ *
+ * \return USB address
+ */
+uint8_t udd_getaddress(void);
+
+/**
+ * \brief Returns the current start of frame number
+ *
+ * \return current start of frame number.
+ */
+uint16_t udd_get_frame_number(void);
+
+/**
+ * \brief Returns the current micro start of frame number
+ *
+ * \return current micro start of frame number required in high speed mode.
+ */
+uint16_t udd_get_micro_frame_number(void);
+
+/*! \brief The USB driver sends a resume signal called Upstream Resume
+ */
+void udd_send_remotewakeup(void);
+
+/**
+ * \brief Load setup payload
+ *
+ * \param payload       Pointer on payload
+ * \param payload_size  Size of payload
+ */
+void udd_set_setup_payload( uint8_t *payload, uint16_t payload_size );
+
+
+/**
+ * \name Endpoint Management
+ *
+ * The following functions allow drivers to create and remove
+ * endpoints, as well as set, clear and query their "halted" and
+ * "wedged" states.
+ */
+//@{
+
+#if (USB_DEVICE_MAX_EP != 0)
+
+/**
+ * \brief Configures and enables an endpoint
+ *
+ * \param ep               Endpoint number including direction (USB_EP_DIR_IN/USB_EP_DIR_OUT).
+ * \param bmAttributes     Attributes of endpoint declared in the descriptor.
+ * \param MaxEndpointSize  Endpoint maximum size
+ *
+ * \return \c 1 if the endpoint is enabled, otherwise \c 0.
+ */
+bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes,
+		uint16_t MaxEndpointSize);
+
+/**
+ * \brief Disables an endpoint
+ *
+ * \param ep               Endpoint number including direction (USB_EP_DIR_IN/USB_EP_DIR_OUT).
+ */
+void udd_ep_free(udd_ep_id_t ep);
+
+/**
+ * \brief Check if the endpoint \a ep is halted.
+ *
+ * \param ep The ID of the endpoint to check.
+ *
+ * \return \c 1 if \a ep is halted, otherwise \c 0.
+ */
+bool udd_ep_is_halted(udd_ep_id_t ep);
+
+/**
+ * \brief Set the halted state of the endpoint \a ep
+ *
+ * After calling this function, any transaction on \a ep will result
+ * in a STALL handshake being sent. Any pending transactions will be
+ * performed first, however.
+ *
+ * \param ep The ID of the endpoint to be halted
+ *
+ * \return \c 1 if \a ep is halted, otherwise \c 0.
+ */
+bool udd_ep_set_halt(udd_ep_id_t ep);
+
+/**
+ * \brief Clear the halted state of the endpoint \a ep
+ *
+ * After calling this function, any transaction on \a ep will
+ * be handled normally, i.e. a STALL handshake will not be sent, and
+ * the data toggle sequence will start at DATA0.
+ *
+ * \param ep The ID of the endpoint to be un-halted
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+bool udd_ep_clear_halt(udd_ep_id_t ep);
+
+/**
+ * \brief Registers a callback to call when endpoint halt is cleared
+ *
+ * \param ep            The ID of the endpoint to use
+ * \param callback      NULL or function to call when endpoint halt is cleared
+ *
+ * \warning if the endpoint is not halted then the \a callback is called immediately.
+ *
+ * \return \c 1 if the register is accepted, otherwise \c 0.
+ */
+bool udd_ep_wait_stall_clear(udd_ep_id_t ep,
+		udd_callback_halt_cleared_t callback);
+
+/**
+ * \brief Allows to receive or send data on an endpoint
+ *
+ * The driver uses a specific DMA USB to transfer data
+ * from internal RAM to endpoint, if this one is available.
+ * When the transfer is finished or aborted (stall, reset, ...), the \a callback is called.
+ * The \a callback returns the transfer status and eventually the number of byte transfered.
+ * Note: The control endpoint is not authorized.
+ *
+ * \param ep            The ID of the endpoint to use
+ * \param b_shortpacket Enabled automatic short packet
+ * \param buf           Buffer on Internal RAM to send or fill.
+ *                      It must be align, then use COMPILER_WORD_ALIGNED.
+ * \param buf_size      Buffer size to send or fill
+ * \param callback      NULL or function to call at the end of transfer
+ *
+ * \warning About \a b_shortpacket, for IN endpoint it means that a short packet
+ * (or a Zero Length Packet) will be sent to the USB line to properly close the usb
+ * transfer at the end of the data transfer.
+ * For Bulk and Interrupt OUT endpoint, it will automatically stop the transfer
+ * at the end of the data transfer (received short packet).
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket,
+		uint8_t * buf, iram_size_t buf_size,
+		udd_callback_trans_t callback);
+/**
+ * \brief Aborts transfer on going on endpoint
+ *
+ * If a transfer is on going, then it is stopped and
+ * the callback registered is called to signal the end of transfer.
+ * Note: The control endpoint is not authorized.
+ *
+ * \param ep            Endpoint to abort
+ */
+void udd_ep_abort(udd_ep_id_t ep);
+
+#endif
+
+//@}
+
+
+/**
+ * \name High speed test mode management
+ *
+ * The following functions allow the device to jump to a specific test mode required in high speed mode.
+ */
+//@{
+void udd_test_mode_j(void);
+void udd_test_mode_k(void);
+void udd_test_mode_se0_nak(void);
+void udd_test_mode_packet(void);
+//@}
+
+
+/**
+ * \name UDC callbacks to provide for UDD
+ *
+ * The following callbacks are used by UDD.
+ */
+//@{
+
+/**
+ * \brief Decodes and manages a setup request
+ *
+ * The driver call it when a SETUP packet is received.
+ * The \c udd_g_ctrlreq contains the data of SETUP packet.
+ * If this callback accepts the setup request then it must
+ * return \c 1 and eventually update \c udd_g_ctrlreq to send or receive data.
+ *
+ * \return \c 1 if the request is accepted, otherwise \c 0.
+ */
+extern bool udc_process_setup(void);
+
+/**
+ * \brief Reset the UDC
+ *
+ * The UDC must reset all configuration.
+ */
+extern void udc_reset(void);
+
+/**
+ * \brief To signal that a SOF is occurred
+ *
+ * The UDC must send the signal to all UDIs enabled
+ */
+extern void udc_sof_notify(void);
+
+//@}
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+#endif // _UDD_H_

asf/common/services/usb/udc/udi.h

@@ -0,0 +1,133 @@
+/**
+ * \file
+ *
+ * \brief Common API for USB Device Interface
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _UDI_H_
+#define _UDI_H_
+
+#include "conf_usb.h"
+#include "usb_protocol.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup usb_device_group
+ * \defgroup udi_group USB Device Interface (UDI)
+ * The UDI provides a common API for all classes,
+ * and this is used by UDC for the main control of USB Device interface.
+ * @{
+ */
+
+/**
+ * \brief UDI API.
+ *
+ * The callbacks within this structure are called only by
+ * USB Device Controller (UDC)
+ *
+ * The udc_get_interface_desc() can be use by UDI to know the interface descriptor
+ * selected by UDC.
+ */
+typedef struct {
+	/**
+	 * \brief Enable the interface.
+	 *
+	 * This function is called when the host selects a configuration
+	 * to which this interface belongs through a Set Configuration
+	 * request, and when the host selects an alternate setting of
+	 * this interface through a Set Interface request.
+	 *
+	 * \return \c 1 if function was successfully done, otherwise \c 0.
+	 */
+	bool(*enable) (void);
+
+	/**
+	 * \brief Disable the interface.
+	 *
+	 * This function is called when this interface is currently
+	 * active, and
+	 * - the host selects any configuration through a Set
+	 *   Configuration request, or
+	 * - the host issues a USB reset, or
+	 * - the device is detached from the host (i.e. Vbus is no
+	 *   longer present)
+	 */
+	void (*disable) (void);
+
+	/**
+	 * \brief Handle a control request directed at an interface.
+	 *
+	 * This function is called when this interface is currently
+	 * active and the host sends a SETUP request
+	 * with this interface as the recipient.
+	 *
+	 * Use udd_g_ctrlreq to decode and response to SETUP request.
+	 *
+	 * \return \c 1 if this interface supports the SETUP request, otherwise \c 0.
+	 */
+	bool(*setup) (void);
+
+	/**
+	 * \brief Returns the current setting of the selected interface.
+	 *
+	 * This function is called when UDC when know alternate setting of selected interface.
+	 *
+	 * \return alternate setting of selected interface
+	 */
+	uint8_t(*getsetting) (void);
+
+	/**
+	 * \brief To signal that a SOF is occurred
+	 */
+	void(*sof_notify) (void);
+} udi_api_t;
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+#endif // _UDI_H_

asf/common/services/usb/usb_atmel.h

@@ -0,0 +1,191 @@
+/**
+ * \file
+ *
+ * \brief All USB VIDs and PIDs from Atmel USB applications
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _USB_ATMEL_H_
+#define _USB_ATMEL_H_
+
+/**
+ * \defgroup usb_group USB Stack
+ *
+ * This stack includes the USB Device Stack, USB Host Stack and common
+ * definitions.
+ * @{
+ */
+
+//! @}
+
+/**
+ * \ingroup usb_group
+ * \defgroup usb_atmel_ids_group Atmel USB Identifiers
+ *
+ * This module defines Atmel PID and VIDs constants.
+ *
+ * @{
+ */
+
+//! \name Vendor Identifier assigned by USB org to ATMEL
+#define  USB_VID_ATMEL                             0x03EB
+
+
+//! \name Product Identifier assigned by ATMEL to AVR applications
+//! @{
+
+//! \name The range from 2000h to 20FFh is reserved to the old PID for C51, MEGA, and others.
+//! @{
+#define  USB_PID_ATMEL_MEGA_HIDGENERIC             0x2013
+#define  USB_PID_ATMEL_MEGA_HIDKEYBOARD            0x2017
+#define  USB_PID_ATMEL_MEGA_CDC                    0x2018
+#define  USB_PID_ATMEL_MEGA_AUDIO_IN               0x2019
+#define  USB_PID_ATMEL_MEGA_MS                     0x201A
+#define  USB_PID_ATMEL_MEGA_AUDIO_IN_OUT           0x201B
+#define  USB_PID_ATMEL_MEGA_HIDMOUSE               0x201C
+#define  USB_PID_ATMEL_MEGA_HIDMOUSE_CERTIF_U4     0x201D
+#define  USB_PID_ATMEL_MEGA_CDC_MULTI              0x201E
+#define  USB_PID_ATMEL_MEGA_MS_HIDMS_HID_USBKEY    0x2022
+#define  USB_PID_ATMEL_MEGA_MS_HIDMS_HID_STK525    0x2023
+#define  USB_PID_ATMEL_MEGA_MS_2                   0x2029
+#define  USB_PID_ATMEL_MEGA_MS_HIDMS               0x202A
+#define  USB_PID_ATMEL_MEGA_MS_3                   0x2032
+#define  USB_PID_ATMEL_MEGA_LIBUSB                 0x2050
+//! @}
+
+//! \name The range 2100h to 21FFh is reserved to PIDs for AVR Tools.
+//! @{
+#define  USB_PID_ATMEL_XPLAINED                    0x2122
+#define  USB_PID_ATMEL_XMEGA_USB_ZIGBIT_2_4GHZ     0x214A
+#define  USB_PID_ATMEL_XMEGA_USB_ZIGBIT_SUBGHZ     0x214B
+//! @}
+
+//! \name The range 2300h to 23FFh is reserved to PIDs for demo from ASF1.7=>
+//! @{
+#define  USB_PID_ATMEL_UC3_ENUM                    0x2300
+#define  USB_PID_ATMEL_UC3_MS                      0x2301
+#define  USB_PID_ATMEL_UC3_MS_SDRAM_LOADER         0x2302
+#define  USB_PID_ATMEL_UC3_EVK1100_CTRLPANEL       0x2303
+#define  USB_PID_ATMEL_UC3_HID                     0x2304
+#define  USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID   0x2305
+#define  USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID_MS 0x2306
+#define  USB_PID_ATMEL_UC3_CDC                     0x2307
+#define  USB_PID_ATMEL_UC3_AUDIO_MICRO             0x2308
+#define  USB_PID_ATMEL_UC3_CDC_DEBUG               0x2310 // Virtual Com (debug interface) on EVK11xx
+#define  USB_PID_ATMEL_UC3_AUDIO_SPEAKER_MICRO     0x2311
+#define  USB_PID_ATMEL_UC3_CDC_MSC                 0x2312
+//! @}
+
+//! \name The range 2400h to 24FFh is reserved to PIDs for ASF applications
+//! @{
+#define  USB_PID_ATMEL_ASF_HIDMOUSE                0x2400
+#define  USB_PID_ATMEL_ASF_HIDKEYBOARD             0x2401
+#define  USB_PID_ATMEL_ASF_HIDGENERIC              0x2402
+#define  USB_PID_ATMEL_ASF_MSC                     0x2403
+#define  USB_PID_ATMEL_ASF_CDC                     0x2404
+#define  USB_PID_ATMEL_ASF_PHDC                    0x2405
+#define  USB_PID_ATMEL_ASF_HIDMTOUCH               0x2406
+#define  USB_PID_ATMEL_ASF_MSC_HIDMOUSE            0x2420
+#define  USB_PID_ATMEL_ASF_MSC_HIDS_CDC            0x2421
+#define  USB_PID_ATMEL_ASF_MSC_HIDKEYBOARD         0x2422
+#define  USB_PID_ATMEL_ASF_VENDOR_CLASS            0x2423
+#define  USB_PID_ATMEL_ASF_MSC_CDC                 0x2424
+#define  USB_PID_ATMEL_ASF_TWO_CDC                 0x2425
+#define  USB_PID_ATMEL_ASF_SEVEN_CDC               0x2426
+#define  USB_PID_ATMEL_ASF_XPLAIN_BC_POWERONLY     0x2430
+#define  USB_PID_ATMEL_ASF_XPLAIN_BC_TERMINAL      0x2431
+#define  USB_PID_ATMEL_ASF_XPLAIN_BC_TOUCH         0x2432
+#define  USB_PID_ATMEL_ASF_AUDIO_SPEAKER           0x2433
+#define  USB_PID_ATMEL_ASF_XMEGA_B1_XPLAINED       0x2434
+//! @}
+
+//! \name The range 2F00h to 2FFFh is reserved to official PIDs for AVR bootloaders
+//! Note, !!!! don't use this range for demos or examples !!!!
+//! @{
+#define  USB_PID_ATMEL_DFU_ATXMEGA64C3             0x2FD6
+#define  USB_PID_ATMEL_DFU_ATXMEGA128C3            0x2FD7
+#define  USB_PID_ATMEL_DFU_ATXMEGA16C4             0x2FD8
+#define  USB_PID_ATMEL_DFU_ATXMEGA32C4             0x2FD9
+#define  USB_PID_ATMEL_DFU_ATXMEGA256C3            0x2FDA
+#define  USB_PID_ATMEL_DFU_ATXMEGA384C3            0x2FDB
+#define  USB_PID_ATMEL_DFU_ATUCL3_L4               0x2FDC
+#define  USB_PID_ATMEL_DFU_ATXMEGA64A4U            0x2FDD
+#define  USB_PID_ATMEL_DFU_ATXMEGA128A4U           0x2FDE
+
+#define  USB_PID_ATMEL_DFU_ATXMEGA64B3             0x2FDF
+#define  USB_PID_ATMEL_DFU_ATXMEGA128B3            0x2FE0
+#define  USB_PID_ATMEL_DFU_ATXMEGA64B1             0x2FE1
+#define  USB_PID_ATMEL_DFU_ATXMEGA256A3BU          0x2FE2
+#define  USB_PID_ATMEL_DFU_ATXMEGA16A4U            0x2FE3
+#define  USB_PID_ATMEL_DFU_ATXMEGA32A4U            0x2FE4
+#define  USB_PID_ATMEL_DFU_ATXMEGA64A3U            0x2FE5
+#define  USB_PID_ATMEL_DFU_ATXMEGA128A3U           0x2FE6
+#define  USB_PID_ATMEL_DFU_ATXMEGA192A3U           0x2FE7
+#define  USB_PID_ATMEL_DFU_ATXMEGA64A1U            0x2FE8
+#define  USB_PID_ATMEL_DFU_ATUC3D                  0x2FE9
+#define  USB_PID_ATMEL_DFU_ATXMEGA128B1            0x2FEA
+#define  USB_PID_ATMEL_DFU_AT32UC3C                0x2FEB
+#define  USB_PID_ATMEL_DFU_ATXMEGA256A3U           0x2FEC
+#define  USB_PID_ATMEL_DFU_ATXMEGA128A1U           0x2FED
+#define  USB_PID_ATMEL_DFU_ATMEGA8U2               0x2FEE
+#define  USB_PID_ATMEL_DFU_ATMEGA16U2              0x2FEF
+#define  USB_PID_ATMEL_DFU_ATMEGA32U2              0x2FF0
+#define  USB_PID_ATMEL_DFU_AT32UC3A3               0x2FF1
+#define  USB_PID_ATMEL_DFU_ATMEGA32U6              0x2FF2
+#define  USB_PID_ATMEL_DFU_ATMEGA16U4              0x2FF3
+#define  USB_PID_ATMEL_DFU_ATMEGA32U4              0x2FF4
+#define  USB_PID_ATMEL_DFU_AT32AP7200              0x2FF5
+#define  USB_PID_ATMEL_DFU_AT32UC3B                0x2FF6
+#define  USB_PID_ATMEL_DFU_AT90USB82               0x2FF7
+#define  USB_PID_ATMEL_DFU_AT32UC3A                0x2FF8
+#define  USB_PID_ATMEL_DFU_AT90USB64               0x2FF9
+#define  USB_PID_ATMEL_DFU_AT90USB162              0x2FFA
+#define  USB_PID_ATMEL_DFU_AT90USB128              0x2FFB
+// 2FFCh to 2FFFh used by C51 family products
+//! @}
+
+//! @}
+
+//! @}
+
+
+#endif // _USB_ATMEL_H_

asf/common/services/usb/usb_protocol.h

@@ -0,0 +1,498 @@
+/**
+ * \file
+ *
+ * \brief USB protocol definitions.
+ *
+ * This file contains the USB definitions and data structures provided by the
+ * USB 2.0 specification.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _USB_PROTOCOL_H_
+#define _USB_PROTOCOL_H_
+
+#include "usb_atmel.h"
+
+/**
+ * \ingroup usb_group
+ * \defgroup usb_protocol_group USB Protocol Definitions
+ *
+ * This module defines constants and data structures provided by the USB
+ * 2.0 specification.
+ *
+ * @{
+ */
+
+//! Value for field bcdUSB
+#define  USB_V2_0    0x0200 //!< USB Specification version 2.00
+#define  USB_V2_1    0x0201 //!< USB Specification version 2.01
+
+/*! \name Generic definitions (Class, subclass and protocol)
+ */
+//! @{
+#define  NO_CLASS                0x00
+#define  CLASS_VENDOR_SPECIFIC   0xFF
+#define  NO_SUBCLASS             0x00
+#define  NO_PROTOCOL             0x00
+//! @}
+
+//! \name IAD (Interface Association Descriptor) constants
+//! @{
+#define  CLASS_IAD               0xEF
+#define  SUB_CLASS_IAD           0x02
+#define  PROTOCOL_IAD            0x01
+//! @}
+
+/**
+ * \brief USB request data transfer direction (bmRequestType)
+ */
+#define  USB_REQ_DIR_OUT         (0<<7) //!< Host to device
+#define  USB_REQ_DIR_IN          (1<<7) //!< Device to host
+#define  USB_REQ_DIR_MASK        (1<<7) //!< Mask
+
+/**
+ * \brief USB request types (bmRequestType)
+ */
+#define  USB_REQ_TYPE_STANDARD   (0<<5) //!< Standard request
+#define  USB_REQ_TYPE_CLASS      (1<<5) //!< Class-specific request
+#define  USB_REQ_TYPE_VENDOR     (2<<5) //!< Vendor-specific request
+#define  USB_REQ_TYPE_MASK       (3<<5) //!< Mask
+
+/**
+ * \brief USB recipient codes (bmRequestType)
+ */
+#define  USB_REQ_RECIP_DEVICE    (0<<0) //!< Recipient device
+#define  USB_REQ_RECIP_INTERFACE (1<<0) //!< Recipient interface
+#define  USB_REQ_RECIP_ENDPOINT  (2<<0) //!< Recipient endpoint
+#define  USB_REQ_RECIP_OTHER     (3<<0) //!< Recipient other
+#define  USB_REQ_RECIP_MASK      (0x1F) //!< Mask
+
+/**
+ * \brief Standard USB requests (bRequest)
+ */
+enum usb_reqid {
+	USB_REQ_GET_STATUS = 0,
+	USB_REQ_CLEAR_FEATURE = 1,
+	USB_REQ_SET_FEATURE = 3,
+	USB_REQ_SET_ADDRESS = 5,
+	USB_REQ_GET_DESCRIPTOR = 6,
+	USB_REQ_SET_DESCRIPTOR = 7,
+	USB_REQ_GET_CONFIGURATION = 8,
+	USB_REQ_SET_CONFIGURATION = 9,
+	USB_REQ_GET_INTERFACE = 10,
+	USB_REQ_SET_INTERFACE = 11,
+	USB_REQ_SYNCH_FRAME = 12,
+};
+
+/**
+ * \brief Standard USB device status flags
+ *
+ */
+enum usb_device_status {
+	USB_DEV_STATUS_BUS_POWERED = 0,
+	USB_DEV_STATUS_SELF_POWERED = 1,
+	USB_DEV_STATUS_REMOTEWAKEUP = 2
+};
+
+/**
+ * \brief Standard USB Interface status flags
+ *
+ */
+enum usb_interface_status {
+	USB_IFACE_STATUS_RESERVED = 0
+};
+
+/**
+ * \brief Standard USB endpoint status flags
+ *
+ */
+enum usb_endpoint_status {
+	USB_EP_STATUS_HALTED = 1,
+};
+
+/**
+ * \brief Standard USB device feature flags
+ *
+ * \note valid for SetFeature request.
+ */
+enum usb_device_feature {
+	USB_DEV_FEATURE_REMOTE_WAKEUP = 1, //!< Remote wakeup enabled
+	USB_DEV_FEATURE_TEST_MODE = 2,     //!< USB test mode
+	USB_DEV_FEATURE_OTG_B_HNP_ENABLE = 3,
+	USB_DEV_FEATURE_OTG_A_HNP_SUPPORT = 4,
+	USB_DEV_FEATURE_OTG_A_ALT_HNP_SUPPORT = 5
+};
+
+/**
+ * \brief Test Mode possible on HS USB device
+ *
+ * \note valid for USB_DEV_FEATURE_TEST_MODE request.
+ */
+enum usb_device_hs_test_mode {
+	USB_DEV_TEST_MODE_J = 1,
+	USB_DEV_TEST_MODE_K = 2,
+	USB_DEV_TEST_MODE_SE0_NAK = 3,
+	USB_DEV_TEST_MODE_PACKET = 4,
+	USB_DEV_TEST_MODE_FORCE_ENABLE = 5,
+};
+
+/**
+ * \brief Standard USB endpoint feature/status flags
+ */
+enum usb_endpoint_feature {
+	USB_EP_FEATURE_HALT = 0,
+};
+
+/**
+ * \brief Standard USB Test Mode Selectors
+ */
+enum usb_test_mode_selector {
+	USB_TEST_J = 0x01,
+	USB_TEST_K = 0x02,
+	USB_TEST_SE0_NAK = 0x03,
+	USB_TEST_PACKET = 0x04,
+	USB_TEST_FORCE_ENABLE = 0x05,
+};
+
+/**
+ * \brief Standard USB descriptor types
+ */
+enum usb_descriptor_type {
+	USB_DT_DEVICE = 1,
+	USB_DT_CONFIGURATION = 2,
+	USB_DT_STRING = 3,
+	USB_DT_INTERFACE = 4,
+	USB_DT_ENDPOINT = 5,
+	USB_DT_DEVICE_QUALIFIER = 6,
+	USB_DT_OTHER_SPEED_CONFIGURATION = 7,
+	USB_DT_INTERFACE_POWER = 8,
+	USB_DT_OTG = 9,
+	USB_DT_IAD = 0x0B,
+	USB_DT_BOS = 0x0F,
+	USB_DT_DEVICE_CAPABILITY = 0x10,
+};
+
+/**
+ * \brief USB Device Capability types
+ */
+enum usb_capability_type {
+	USB_DC_USB20_EXTENSION = 0x02,
+};
+
+/**
+ * \brief USB Device Capability - USB 2.0 Extension
+ * To fill bmAttributes field of usb_capa_ext_desc_t structure.
+ */
+enum usb_capability_extension_attr {
+	USB_DC_EXT_LPM  = 0x00000002,
+};
+
+#define HIRD_50_US    0
+#define HIRD_125_US   1
+#define HIRD_200_US   2
+#define HIRD_275_US   3
+#define HIRD_350_US   4
+#define HIRD_425_US   5
+#define HIRD_500_US   6
+#define HIRD_575_US  7
+#define HIRD_650_US  8
+#define HIRD_725_US  9
+#define HIRD_800_US  10
+#define HIRD_875_US  11
+#define HIRD_950_US  12
+#define HIRD_1025_US  13
+#define HIRD_1100_US  14
+#define HIRD_1175_US  15
+
+/** Fields definition from a LPM TOKEN  */
+#define  USB_LPM_ATTRIBUT_BLINKSTATE_MASK      (0xF << 0)
+#define  USB_LPM_ATTRIBUT_FIRD_MASK            (0xF << 4)
+#define  USB_LPM_ATTRIBUT_REMOTEWAKE_MASK      (1 << 8)
+#define  USB_LPM_ATTRIBUT_BLINKSTATE(value)    ((value & 0xF) << 0)
+#define  USB_LPM_ATTRIBUT_FIRD(value)          ((value & 0xF) << 4)
+#define  USB_LPM_ATTRIBUT_REMOTEWAKE(value)    ((value & 1) << 8)
+#define  USB_LPM_ATTRIBUT_BLINKSTATE_L1        USB_LPM_ATTRIBUT_BLINKSTATE(1)
+
+/**
+ * \brief Standard USB endpoint transfer types
+ */
+enum usb_ep_type {
+	USB_EP_TYPE_CONTROL = 0x00,
+	USB_EP_TYPE_ISOCHRONOUS = 0x01,
+	USB_EP_TYPE_BULK = 0x02,
+	USB_EP_TYPE_INTERRUPT = 0x03,
+	USB_EP_TYPE_MASK = 0x03,
+};
+
+/**
+ * \brief Standard USB language IDs for string descriptors
+ */
+enum usb_langid {
+	USB_LANGID_EN_US = 0x0409, //!< English (United States)
+};
+
+/**
+ * \brief Mask selecting the index part of an endpoint address
+ */
+#define  USB_EP_ADDR_MASK     0x0f
+
+//! \brief USB address identifier
+typedef uint8_t usb_add_t;
+
+/**
+ * \brief Endpoint transfer direction is IN
+ */
+#define  USB_EP_DIR_IN        0x80
+
+/**
+ * \brief Endpoint transfer direction is OUT
+ */
+#define  USB_EP_DIR_OUT       0x00
+
+//! \brief Endpoint identifier
+typedef uint8_t usb_ep_t;
+
+/**
+ * \brief Maximum length in bytes of a USB descriptor
+ *
+ * The maximum length of a USB descriptor is limited by the 8-bit
+ * bLength field.
+ */
+#define  USB_MAX_DESC_LEN     255
+
+/*
+ * 2-byte alignment requested for all USB structures.
+ */
+COMPILER_PACK_SET(1)
+
+/**
+ * \brief A USB Device SETUP request
+ *
+ * The data payload of SETUP packets always follows this structure.
+ */
+typedef struct {
+	uint8_t bmRequestType;
+	uint8_t bRequest;
+	le16_t wValue;
+	le16_t wIndex;
+	le16_t wLength;
+} usb_setup_req_t;
+
+/**
+ * \brief Standard USB device descriptor structure
+ */
+typedef struct {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	le16_t bcdUSB;
+	uint8_t bDeviceClass;
+	uint8_t bDeviceSubClass;
+	uint8_t bDeviceProtocol;
+	uint8_t bMaxPacketSize0;
+	le16_t idVendor;
+	le16_t idProduct;
+	le16_t bcdDevice;
+	uint8_t iManufacturer;
+	uint8_t iProduct;
+	uint8_t iSerialNumber;
+	uint8_t bNumConfigurations;
+} usb_dev_desc_t;
+
+/**
+ * \brief Standard USB device qualifier descriptor structure
+ *
+ * This descriptor contains information about the device when running at
+ * the "other" speed (i.e. if the device is currently operating at high
+ * speed, this descriptor can be used to determine what would change if
+ * the device was operating at full speed.)
+ */
+typedef struct {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	le16_t bcdUSB;
+	uint8_t bDeviceClass;
+	uint8_t bDeviceSubClass;
+	uint8_t bDeviceProtocol;
+	uint8_t bMaxPacketSize0;
+	uint8_t bNumConfigurations;
+	uint8_t bReserved;
+} usb_dev_qual_desc_t;
+
+/**
+ * \brief USB Device BOS descriptor structure
+ *
+ * The BOS descriptor (Binary device Object Store) defines a root
+ * descriptor that is similar to the configuration descriptor, and is
+ * the base descriptor for accessing a family of related descriptors.
+ * A host can read a BOS descriptor and learn from the wTotalLength field
+ * the entire size of the device-level descriptor set, or it can read in
+ * the entire BOS descriptor set of device capabilities.
+ * The host accesses this descriptor using the GetDescriptor() request.
+ * The descriptor type in the GetDescriptor() request is set to BOS.
+ */
+typedef struct {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	le16_t  wTotalLength;
+	uint8_t bNumDeviceCaps;
+} usb_dev_bos_desc_t;
+
+
+/**
+ * \brief USB Device Capabilities - USB 2.0 Extension Descriptor structure
+ *
+ * Defines the set of USB 1.1-specific device level capabilities.
+ */
+typedef struct {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDevCapabilityType;
+	le32_t  bmAttributes;
+} usb_dev_capa_ext_desc_t;
+
+/**
+ * \brief USB Device LPM Descriptor structure
+ *
+ * The BOS descriptor and capabilities descriptors for LPM.
+ */
+typedef struct {
+	usb_dev_bos_desc_t bos;
+	usb_dev_capa_ext_desc_t capa_ext;
+} usb_dev_lpm_desc_t;
+
+/**
+ * \brief Standard USB Interface Association Descriptor structure
+ */
+typedef struct {
+	uint8_t bLength;          //!< size of this descriptor in bytes
+	uint8_t bDescriptorType;  //!< INTERFACE descriptor type
+	uint8_t bFirstInterface;  //!< Number of interface
+	uint8_t bInterfaceCount;  //!< value to select alternate setting
+	uint8_t bFunctionClass;   //!< Class code assigned by the USB
+	uint8_t bFunctionSubClass;//!< Sub-class code assigned by the USB
+	uint8_t bFunctionProtocol;//!< Protocol code assigned by the USB
+	uint8_t iFunction;        //!< Index of string descriptor
+} usb_association_desc_t;
+
+
+/**
+ * \brief Standard USB configuration descriptor structure
+ */
+typedef struct {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	le16_t wTotalLength;
+	uint8_t bNumInterfaces;
+	uint8_t bConfigurationValue;
+	uint8_t iConfiguration;
+	uint8_t bmAttributes;
+	uint8_t bMaxPower;
+} usb_conf_desc_t;
+
+
+#define  USB_CONFIG_ATTR_MUST_SET         (1 << 7) //!< Must always be set
+#define  USB_CONFIG_ATTR_BUS_POWERED      (0 << 6) //!< Bus-powered
+#define  USB_CONFIG_ATTR_SELF_POWERED     (1 << 6) //!< Self-powered
+#define  USB_CONFIG_ATTR_REMOTE_WAKEUP    (1 << 5) //!< remote wakeup supported
+
+#define  USB_CONFIG_MAX_POWER(ma)         (((ma) + 1) / 2) //!< Max power in mA
+
+/**
+ * \brief Standard USB association descriptor structure
+ */
+typedef struct {
+	uint8_t bLength;              //!< Size of this descriptor in bytes
+	uint8_t bDescriptorType;      //!< Interface descriptor type
+	uint8_t bFirstInterface;      //!< Number of interface
+	uint8_t bInterfaceCount;      //!< value to select alternate setting
+	uint8_t bFunctionClass;       //!< Class code assigned by the USB
+	uint8_t bFunctionSubClass;    //!< Sub-class code assigned by the USB
+	uint8_t bFunctionProtocol;    //!< Protocol code assigned by the USB
+	uint8_t iFunction;            //!< Index of string descriptor
+} usb_iad_desc_t;
+
+/**
+ * \brief Standard USB interface descriptor structure
+ */
+typedef struct {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bInterfaceNumber;
+	uint8_t bAlternateSetting;
+	uint8_t bNumEndpoints;
+	uint8_t bInterfaceClass;
+	uint8_t bInterfaceSubClass;
+	uint8_t bInterfaceProtocol;
+	uint8_t iInterface;
+} usb_iface_desc_t;
+
+/**
+ * \brief Standard USB endpoint descriptor structure
+ */
+typedef struct {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bEndpointAddress;
+	uint8_t bmAttributes;
+	le16_t wMaxPacketSize;
+	uint8_t bInterval;
+} usb_ep_desc_t;
+
+
+/**
+ * \brief A standard USB string descriptor structure
+ */
+typedef struct {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+} usb_str_desc_t;
+
+typedef struct {
+	usb_str_desc_t desc;
+	le16_t string[1];
+} usb_str_lgid_desc_t;
+
+COMPILER_PACK_RESET()
+
+//! @}
+
+#endif /* _USB_PROTOCOL_H_ */

asf/common/utils/interrupt.h

@@ -0,0 +1,142 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for 8- and 32-bit AVR
+ *
+ * Copyright (c) 2010-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef UTILS_INTERRUPT_H
+#define UTILS_INTERRUPT_H
+
+#include <parts.h>
+
+#if XMEGA || MEGA
+#  include "interrupt/interrupt_avr8.h"
+#elif UC3
+#  include "interrupt/interrupt_avr32.h"
+#elif SAM || SAMB
+#  include "interrupt/interrupt_sam_nvic.h"
+#else
+#  error Unsupported device.
+#endif
+
+/**
+ * \defgroup interrupt_group Global interrupt management
+ *
+ * This is a driver for global enabling and disabling of interrupts.
+ *
+ * @{
+ */
+
+#if defined(__DOXYGEN__)
+/**
+ * \def CONFIG_INTERRUPT_FORCE_INTC
+ * \brief Force usage of the ASF INTC driver
+ *
+ * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.
+ * This is useful to ensure compatibility across compilers and shall be used only when required
+ * by the application needs.
+ */
+#  define CONFIG_INTERRUPT_FORCE_INTC
+#endif
+
+//! \name Global interrupt flags
+//@{
+/**
+ * \typedef irqflags_t
+ * \brief Type used for holding state of interrupt flag
+ */
+
+/**
+ * \def cpu_irq_enable
+ * \brief Enable interrupts globally
+ */
+
+/**
+ * \def cpu_irq_disable
+ * \brief Disable interrupts globally
+ */
+
+/**
+ * \fn irqflags_t cpu_irq_save(void)
+ * \brief Get and clear the global interrupt flags
+ *
+ * Use in conjunction with \ref cpu_irq_restore.
+ *
+ * \return Current state of interrupt flags.
+ *
+ * \note This function leaves interrupts disabled.
+ */
+
+/**
+ * \fn void cpu_irq_restore(irqflags_t flags)
+ * \brief Restore global interrupt flags
+ *
+ * Use in conjunction with \ref cpu_irq_save.
+ *
+ * \param flags State to set interrupt flag to.
+ */
+
+/**
+ * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)
+ * \brief Check if interrupts are globally enabled in supplied flags
+ *
+ * \param flags Currents state of interrupt flags.
+ *
+ * \return True if interrupts are enabled.
+ */
+
+/**
+ * \def cpu_irq_is_enabled
+ * \brief Check if interrupts are globally enabled
+ *
+ * \return True if interrupts are enabled.
+ */
+//@}
+
+//! @}
+
+/**
+ * \ingroup interrupt_group
+ * \defgroup interrupt_deprecated_group Deprecated interrupt definitions
+ */
+
+#endif /* UTILS_INTERRUPT_H */

asf/common/utils/interrupt/interrupt_sam_nvic.c

@@ -0,0 +1,86 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "interrupt_sam_nvic.h"
+
+#if !defined(__DOXYGEN__)
+/* Deprecated - global flag to determine the global interrupt state. Required by
+ * QTouch library, however new applications should use cpu_irq_is_enabled()
+ * which probes the true global interrupt state from the CPU special registers.
+ */
+volatile bool g_interrupt_enabled = true;
+#endif
+
+void cpu_irq_enter_critical(void)
+{
+	if (cpu_irq_critical_section_counter == 0) {
+		if (cpu_irq_is_enabled()) {
+			cpu_irq_disable();
+			cpu_irq_prev_interrupt_state = true;
+		} else {
+			/* Make sure the to save the prev state as false */
+			cpu_irq_prev_interrupt_state = false;
+		}
+
+	}
+
+	cpu_irq_critical_section_counter++;
+}
+
+void cpu_irq_leave_critical(void)
+{
+	/* Check if the user is trying to leave a critical section when not in a critical section */
+	Assert(cpu_irq_critical_section_counter > 0);
+
+	cpu_irq_critical_section_counter--;
+
+	/* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
+	   was enabled when entering critical state */
+	if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
+		cpu_irq_enable();
+	}
+}
+

asf/common/utils/interrupt/interrupt_sam_nvic.h

@@ -0,0 +1,189 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
+ *
+ * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef UTILS_INTERRUPT_INTERRUPT_H
+#define UTILS_INTERRUPT_INTERRUPT_H
+
+#include <compiler.h>
+#include <parts.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \weakgroup interrupt_group
+ *
+ * @{
+ */
+
+/**
+ * \name Interrupt Service Routine definition
+ *
+ * @{
+ */
+
+/**
+ * \brief Define service routine
+ *
+ * \note For NVIC devices the interrupt service routines are predefined to
+ *       add to vector table in binary generation, so there is no service
+ *       register at run time. The routine collections are in exceptions.h.
+ *
+ * Usage:
+ * \code
+	ISR(foo_irq_handler)
+	{
+	     // Function definition
+	     ...
+	}
+\endcode
+ *
+ * \param func Name for the function.
+ */
+#  define ISR(func)   \
+	void func (void)
+
+/**
+ * \brief Initialize interrupt vectors
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to initialize them, except defined the vector function with
+ * right name.
+ *
+ * This must be called prior to \ref irq_register_handler.
+ */
+#  define irq_initialize_vectors()   \
+	do {                             \
+	} while(0)
+
+/**
+ * \brief Register handler for interrupt
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to register them, except defined the vector function with
+ * right name.
+ *
+ * Usage:
+ * \code
+	irq_initialize_vectors();
+	irq_register_handler(foo_irq_handler);
+\endcode
+ *
+ * \note The function \a func must be defined with the \ref ISR macro.
+ * \note The functions prototypes can be found in the device exception header
+ *       files (exceptions.h).
+ */
+#  define irq_register_handler(int_num, int_prio)                      \
+	NVIC_ClearPendingIRQ(    (IRQn_Type)int_num);                      \
+	NVIC_SetPriority(    (IRQn_Type)int_num, int_prio);                \
+	NVIC_EnableIRQ(      (IRQn_Type)int_num);                          \
+
+//@}
+
+#  define cpu_irq_enable()                     \
+	do {                                       \
+		g_interrupt_enabled = true;            \
+		__DMB();                               \
+		__enable_irq();                        \
+	} while (0)
+#  define cpu_irq_disable()                    \
+	do {                                       \
+		__disable_irq();                       \
+		__DMB();                               \
+		g_interrupt_enabled = false;           \
+	} while (0)
+
+typedef uint32_t irqflags_t;
+
+#if !defined(__DOXYGEN__)
+extern volatile bool g_interrupt_enabled;
+#endif
+
+#define cpu_irq_is_enabled()    (__get_PRIMASK() == 0)
+
+static volatile uint32_t cpu_irq_critical_section_counter;
+static volatile bool     cpu_irq_prev_interrupt_state;
+
+static inline irqflags_t cpu_irq_save(void)
+{
+	volatile irqflags_t flags = cpu_irq_is_enabled();
+	cpu_irq_disable();
+	return flags;
+}
+
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
+{
+	return (flags);
+}
+
+static inline void cpu_irq_restore(irqflags_t flags)
+{
+	if (cpu_irq_is_enabled_flags(flags))
+		cpu_irq_enable();
+}
+
+void cpu_irq_enter_critical(void);
+void cpu_irq_leave_critical(void);
+
+/**
+ * \weakgroup interrupt_deprecated_group
+ * @{
+ */
+
+#define Enable_global_interrupt()            cpu_irq_enable()
+#define Disable_global_interrupt()           cpu_irq_disable()
+#define Is_global_interrupt_enabled()        cpu_irq_is_enabled()
+
+//@}
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */

asf/sam0/boards/samd21_xplained_pro/board_init.c

@@ -0,0 +1,90 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 Xplained Pro board initialization
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <compiler.h>
+#include <board.h>
+#include <conf_board.h>
+#include <port.h>
+
+#if defined(__GNUC__)
+void board_init(void) WEAK __attribute__((alias("system_board_init")));
+#elif defined(__ICCARM__)
+void board_init(void);
+#  pragma weak board_init=system_board_init
+#endif
+
+void system_board_init(void)
+{
+	struct port_config pin_conf;
+	port_get_config_defaults(&pin_conf);
+
+	/* Configure LEDs as outputs, turn them off */
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(LED_0_PIN, &pin_conf);
+	port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
+
+	/* Set buttons as inputs */
+	pin_conf.direction  = PORT_PIN_DIR_INPUT;
+	pin_conf.input_pull = PORT_PIN_PULL_UP;
+	port_pin_set_config(BUTTON_0_PIN, &pin_conf);
+	
+#ifdef CONF_BOARD_AT86RFX
+	port_get_config_defaults(&pin_conf);
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(AT86RFX_SPI_SCK, &pin_conf);
+	port_pin_set_config(AT86RFX_SPI_MOSI, &pin_conf);
+	port_pin_set_config(AT86RFX_SPI_CS, &pin_conf);
+	port_pin_set_config(AT86RFX_RST_PIN, &pin_conf);
+	port_pin_set_config(AT86RFX_SLP_PIN, &pin_conf);
+	port_pin_set_output_level(AT86RFX_SPI_SCK, true);
+	port_pin_set_output_level(AT86RFX_SPI_MOSI, true);
+	port_pin_set_output_level(AT86RFX_SPI_CS, true);
+	port_pin_set_output_level(AT86RFX_RST_PIN, true);
+	port_pin_set_output_level(AT86RFX_SLP_PIN, true);
+	pin_conf.direction  = PORT_PIN_DIR_INPUT;
+	port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
+#endif	
+}

asf/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h

@@ -0,0 +1,709 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 Xplained Pro board definition
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SAMD21_XPLAINED_PRO_H_INCLUDED
+#define SAMD21_XPLAINED_PRO_H_INCLUDED
+
+#include <conf_board.h>
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup group_common_boards
+ * \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board
+ *
+ * @{
+ */
+
+void system_board_init(void);
+
+/**
+ * \defgroup samd21_xplained_pro_features_group Features
+ *
+ * Symbols that describe features and capabilities of the board.
+ *
+ * @{
+ */
+
+/** Name string macro */
+#define BOARD_NAME                "SAMD21_XPLAINED_PRO"
+
+/** \name Resonator definitions
+ *  @{ */
+#define BOARD_FREQ_SLCK_XTAL      (32768U)
+#define BOARD_FREQ_SLCK_BYPASS    (32768U)
+#define BOARD_FREQ_MAINCK_XTAL    0 /* Not Mounted */
+#define BOARD_FREQ_MAINCK_BYPASS  0 /* Not Mounted */
+#define BOARD_MCK                 CHIP_FREQ_CPU_MAX
+#define BOARD_OSC_STARTUP_US      15625
+/** @} */
+
+/** \name LED0 definitions
+ *  @{ */
+#define LED0_PIN                  PIN_PB30
+#define LED0_ACTIVE               false
+#define LED0_INACTIVE             !LED0_ACTIVE
+/** @} */
+
+/** \name SW0 definitions
+ *  @{ */
+#define SW0_PIN                   PIN_PA15
+#define SW0_ACTIVE                false
+#define SW0_INACTIVE              !SW0_ACTIVE
+#define SW0_EIC_PIN               PIN_PA15A_EIC_EXTINT15
+#define SW0_EIC_MUX               MUX_PA15A_EIC_EXTINT15
+#define SW0_EIC_PINMUX            PINMUX_PA15A_EIC_EXTINT15
+#define SW0_EIC_LINE              15
+/** @} */
+
+/**
+ * \name LED #0 definitions
+ *
+ * Wrapper macros for LED0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ *  @{ */
+#define LED_0_NAME                "LED0 (yellow)"
+#define LED_0_PIN                 LED0_PIN
+#define LED_0_ACTIVE              LED0_ACTIVE
+#define LED_0_INACTIVE            LED0_INACTIVE
+#define LED0_GPIO                 LED0_PIN
+#define LED0                      LED0_PIN
+
+#define LED_0_PWM4CTRL_MODULE     TCC0
+#define LED_0_PWM4CTRL_CHANNEL    0
+#define LED_0_PWM4CTRL_OUTPUT     0
+#define LED_0_PWM4CTRL_PIN        PIN_PB30E_TCC0_WO0
+#define LED_0_PWM4CTRL_MUX        MUX_PB30E_TCC0_WO0
+#define LED_0_PWM4CTRL_PINMUX     PINMUX_PB30E_TCC0_WO0
+/** @} */
+
+/** Number of on-board LEDs */
+#define LED_COUNT                 1
+
+/**
+ * \name Serialflash definitions
+ *
+ * On board Serialflash definitions.
+ *
+ *  @{ */
+#define SERIALFLASH_SPI_MODULE      SERCOM5
+#define SERIALFLASH_SPI_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
+#define SERIALFLASH_SPI_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
+#define SERIALFLASH_SPI_PINMUX_PAD1 PINMUX_UNUSED
+#define SERIALFLASH_SPI_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
+#define SERIALFLASH_SPI_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
+#define SERIALFLASH_SPI_CS PIN_PA13
+/** @} */
+
+/**
+ * \name Button #0 definitions
+ *
+ * Wrapper macros for SW0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ *  @{ */
+#define BUTTON_0_NAME             "SW0"
+#define BUTTON_0_PIN              SW0_PIN
+#define BUTTON_0_ACTIVE           SW0_ACTIVE
+#define BUTTON_0_INACTIVE         SW0_INACTIVE
+#define BUTTON_0_EIC_PIN          SW0_EIC_PIN
+#define BUTTON_0_EIC_MUX          SW0_EIC_MUX
+#define BUTTON_0_EIC_PINMUX       SW0_EIC_PINMUX
+#define BUTTON_0_EIC_LINE         SW0_EIC_LINE
+/** @} */
+
+/** Number of on-board buttons */
+#define BUTTON_COUNT 1
+
+/** \name Extension header #1 pin definitions
+ *  @{
+ */
+#define EXT1_PIN_3                PIN_PB00
+#define EXT1_PIN_4                PIN_PB01
+#define EXT1_PIN_5                PIN_PB06
+#define EXT1_PIN_6                PIN_PB07
+#define EXT1_PIN_7                PIN_PB02
+#define EXT1_PIN_8                PIN_PB03
+#define EXT1_PIN_9                PIN_PB04
+#define EXT1_PIN_10               PIN_PB05
+#define EXT1_PIN_11               PIN_PA08
+#define EXT1_PIN_12               PIN_PA09
+#define EXT1_PIN_13               PIN_PB09
+#define EXT1_PIN_14               PIN_PB08
+#define EXT1_PIN_15               PIN_PA05
+#define EXT1_PIN_16               PIN_PA06
+#define EXT1_PIN_17               PIN_PA04
+#define EXT1_PIN_18               PIN_PA07
+/** @} */
+
+/** \name Extension header #1 pin definitions by function
+ *  @{
+ */
+#define EXT1_PIN_ADC_0            EXT1_PIN_3
+#define EXT1_PIN_ADC_1            EXT1_PIN_4
+#define EXT1_PIN_GPIO_0           EXT1_PIN_5
+#define EXT1_PIN_GPIO_1           EXT1_PIN_6
+#define EXT1_PIN_PWM_0            EXT1_PIN_7
+#define EXT1_PIN_PWM_1            EXT1_PIN_8
+#define EXT1_PIN_IRQ              EXT1_PIN_9
+#define EXT1_PIN_I2C_SDA          EXT1_PIN_11
+#define EXT1_PIN_I2C_SCL          EXT1_PIN_12
+#define EXT1_PIN_UART_RX          EXT1_PIN_13
+#define EXT1_PIN_UART_TX          EXT1_PIN_14
+#define EXT1_PIN_SPI_SS_1         EXT1_PIN_10
+#define EXT1_PIN_SPI_SS_0         EXT1_PIN_15
+#define EXT1_PIN_SPI_MOSI         EXT1_PIN_16
+#define EXT1_PIN_SPI_MISO         EXT1_PIN_17
+#define EXT1_PIN_SPI_SCK          EXT1_PIN_18
+/** @} */
+
+/** \name Extension header #1 ADC definitions
+ *  @{
+ */
+#define EXT1_ADC_MODULE           ADC
+#define EXT1_ADC_0_CHANNEL        8
+#define EXT1_ADC_0_PIN            PIN_PB00B_ADC_AIN8
+#define EXT1_ADC_0_MUX            MUX_PB00B_ADC_AIN8
+#define EXT1_ADC_0_PINMUX         PINMUX_PB00B_ADC_AIN8
+#define EXT1_ADC_1_CHANNEL        9
+#define EXT1_ADC_1_PIN            PIN_PB01B_ADC_AIN9
+#define EXT1_ADC_1_MUX            MUX_PB01B_ADC_AIN9
+#define EXT1_ADC_1_PINMUX         PINMUX_PB01B_ADC_AIN9
+/** @} */
+
+/** \name Extension header #1 PWM definitions
+ *  @{
+ */
+#define EXT1_PWM_MODULE           TC6
+#define EXT1_PWM_0_CHANNEL        0
+#define EXT1_PWM_0_PIN            PIN_PB02E_TC6_WO0
+#define EXT1_PWM_0_MUX            MUX_PB02E_TC6_WO0
+#define EXT1_PWM_0_PINMUX         PINMUX_PB02E_TC6_WO0
+#define EXT1_PWM_1_CHANNEL        1
+#define EXT1_PWM_1_PIN            PIN_PB03E_TC6_WO1
+#define EXT1_PWM_1_MUX            MUX_PB03E_TC6_WO1
+#define EXT1_PWM_1_PINMUX         PINMUX_PB03E_TC6_WO1
+/** @} */
+
+/** \name Extension header #1 IRQ/External interrupt definitions
+ *  @{
+ */
+#define EXT1_IRQ_MODULE           EIC
+#define EXT1_IRQ_INPUT            4
+#define EXT1_IRQ_PIN              PIN_PB04A_EIC_EXTINT4
+#define EXT1_IRQ_MUX              MUX_PB04A_EIC_EXTINT4
+#define EXT1_IRQ_PINMUX           PINMUX_PB04A_EIC_EXTINT4
+/** @} */
+
+/** \name Extension header #1 I2C definitions
+ *  @{
+ */
+#define EXT1_I2C_MODULE              SERCOM2
+#define EXT1_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EXT1_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+#define EXT1_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
+#define EXT1_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #1 UART definitions
+ *  @{
+ */
+#define EXT1_UART_MODULE              SERCOM4
+#define EXT1_UART_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
+#define EXT1_UART_SERCOM_PINMUX_PAD0  PINMUX_PB08D_SERCOM4_PAD0
+#define EXT1_UART_SERCOM_PINMUX_PAD1  PINMUX_PB09D_SERCOM4_PAD1
+#define EXT1_UART_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
+#define EXT1_UART_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
+#define EXT1_UART_SERCOM_DMAC_ID_TX   SERCOM4_DMAC_ID_TX
+#define EXT1_UART_SERCOM_DMAC_ID_RX   SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #1 SPI definitions
+ *  @{
+ */
+#define EXT1_SPI_MODULE              SERCOM0
+#define EXT1_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EXT1_SPI_SERCOM_PINMUX_PAD0  PINMUX_PA04D_SERCOM0_PAD0
+#define EXT1_SPI_SERCOM_PINMUX_PAD1  PINMUX_PA05D_SERCOM0_PAD1
+#define EXT1_SPI_SERCOM_PINMUX_PAD2  PINMUX_PA06D_SERCOM0_PAD2
+#define EXT1_SPI_SERCOM_PINMUX_PAD3  PINMUX_PA07D_SERCOM0_PAD3
+#define EXT1_SPI_SERCOM_DMAC_ID_TX   SERCOM0_DMAC_ID_TX
+#define EXT1_SPI_SERCOM_DMAC_ID_RX   SERCOM0_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 pin definitions
+ *  @{
+ */
+#define EXT2_PIN_3                PIN_PA10
+#define EXT2_PIN_4                PIN_PA11
+#define EXT2_PIN_5                PIN_PA20
+#define EXT2_PIN_6                PIN_PA21
+#define EXT2_PIN_7                PIN_PB12
+#define EXT2_PIN_8                PIN_PB13
+#define EXT2_PIN_9                PIN_PB14
+#define EXT2_PIN_10               PIN_PB15
+#define EXT2_PIN_11               PIN_PA08
+#define EXT2_PIN_12               PIN_PA09
+#define EXT2_PIN_13               PIN_PB11
+#define EXT2_PIN_14               PIN_PB10
+#define EXT2_PIN_15               PIN_PA17
+#define EXT2_PIN_16               PIN_PA18
+#define EXT2_PIN_17               PIN_PA16
+#define EXT2_PIN_18               PIN_PA19
+/** @} */
+
+/** \name Extension header #2 pin definitions by function
+ *  @{
+ */
+#define EXT2_PIN_ADC_0            EXT2_PIN_3
+#define EXT2_PIN_ADC_1            EXT2_PIN_4
+#define EXT2_PIN_GPIO_0           EXT2_PIN_5
+#define EXT2_PIN_GPIO_1           EXT2_PIN_6
+#define EXT2_PIN_PWM_0            EXT2_PIN_7
+#define EXT2_PIN_PWM_1            EXT2_PIN_8
+#define EXT2_PIN_IRQ              EXT2_PIN_9
+#define EXT2_PIN_I2C_SDA          EXT2_PIN_11
+#define EXT2_PIN_I2C_SCL          EXT2_PIN_12
+#define EXT2_PIN_UART_RX          EXT2_PIN_13
+#define EXT2_PIN_UART_TX          EXT2_PIN_14
+#define EXT2_PIN_SPI_SS_1         EXT2_PIN_10
+#define EXT2_PIN_SPI_SS_0         EXT2_PIN_15
+#define EXT2_PIN_SPI_MOSI         EXT2_PIN_16
+#define EXT2_PIN_SPI_MISO         EXT2_PIN_17
+#define EXT2_PIN_SPI_SCK          EXT2_PIN_18
+/** @} */
+
+/** \name Extension header #2 ADC definitions
+ *  @{
+ */
+#define EXT2_ADC_MODULE           ADC
+#define EXT2_ADC_0_CHANNEL        18
+#define EXT2_ADC_0_PIN            PIN_PA10B_ADC_AIN18
+#define EXT2_ADC_0_MUX            MUX_PA10B_ADC_AIN18
+#define EXT2_ADC_0_PINMUX         PINMUX_PA10B_ADC_AIN18
+#define EXT2_ADC_1_CHANNEL        19
+#define EXT2_ADC_1_PIN            PIN_PA11B_ADC_AIN19
+#define EXT2_ADC_1_MUX            MUX_PA11B_ADC_AIN19
+#define EXT2_ADC_1_PINMUX         PINMUX_PA11B_ADC_AIN19
+/** @} */
+
+/** \name Extension header #2 PWM definitions
+ *  @{
+ */
+#define EXT2_PWM_MODULE           TC4
+#define EXT2_PWM_0_CHANNEL        0
+#define EXT2_PWM_0_PIN            PIN_PB12E_TC4_WO0
+#define EXT2_PWM_0_MUX            MUX_PB12E_TC4_WO0
+#define EXT2_PWM_0_PINMUX         PINMUX_PB12E_TC4_WO0
+#define EXT2_PWM_1_CHANNEL        1
+#define EXT2_PWM_1_PIN            PIN_PB13E_TC4_WO1
+#define EXT2_PWM_1_MUX            MUX_PB13E_TC4_WO1
+#define EXT2_PWM_1_PINMUX         PINMUX_PB13E_TC4_WO1
+/** @} */
+
+/** \name Extension header #2 PWM for Control definitions
+ *  @{
+ */
+#define EXT2_PWM4CTRL_MODULE      TCC0
+#define EXT2_PWM4CTRL_0_CHANNEL   2
+#define EXT2_PWM4CTRL_0_OUTPUT    6
+#define EXT2_PWM4CTRL_0_PIN       PIN_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_0_MUX       MUX_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_0_PINMUX    PINMUX_PB12F_TCC0_WO6
+#define EXT2_PWM4CTRL_1_CHANNEL   3
+#define EXT2_PWM4CTRL_1_OUTPUT    7
+#define EXT2_PWM4CTRL_1_PIN       PIN_PB13F_TCC0_WO7
+#define EXT2_PWM4CTRL_1_MUX       MUX_PB13F_TCC0_WO7
+#define EXT2_PWM4CTRL_1_PINMUX    PINMUX_PB13F_TCC0_WO7
+/** @} */
+
+/** \name Extension header #2 IRQ/External interrupt definitions
+ *  @{
+ */
+#define EXT2_IRQ_MODULE           EIC
+#define EXT2_IRQ_INPUT            14
+#define EXT2_IRQ_PIN              PIN_PB14A_EIC_EXTINT14
+#define EXT2_IRQ_MUX              MUX_PB14A_EIC_EXTINT14
+#define EXT2_IRQ_PINMUX           PINMUX_PB14A_EIC_EXTINT14
+/** @} */
+
+ /** \name Extension header #2 I2C definitions
+ *  @{
+ */
+#define EXT2_I2C_MODULE              SERCOM2
+#define EXT2_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EXT2_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+#define EXT2_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
+#define EXT2_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 UART definitions
+ *  @{
+ */
+#define EXT2_UART_MODULE              SERCOM4
+#define EXT2_UART_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
+#define EXT2_UART_SERCOM_PINMUX_PAD0  PINMUX_PB12C_SERCOM4_PAD0
+#define EXT2_UART_SERCOM_PINMUX_PAD1  PINMUX_PB13C_SERCOM4_PAD1
+#define EXT2_UART_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
+#define EXT2_UART_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
+#define EXT2_UART_SERCOM_DMAC_ID_TX   SERCOM4_DMAC_ID_TX
+#define EXT2_UART_SERCOM_DMAC_ID_RX   SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #2 SPI definitions
+ *  @{
+ */
+#define EXT2_SPI_MODULE              SERCOM1
+#define EXT2_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EXT2_SPI_SERCOM_PINMUX_PAD0  PINMUX_PA16C_SERCOM1_PAD0
+#define EXT2_SPI_SERCOM_PINMUX_PAD1  PINMUX_PA17C_SERCOM1_PAD1
+#define EXT2_SPI_SERCOM_PINMUX_PAD2  PINMUX_PA18C_SERCOM1_PAD2
+#define EXT2_SPI_SERCOM_PINMUX_PAD3  PINMUX_PA19C_SERCOM1_PAD3
+#define EXT2_SPI_SERCOM_DMAC_ID_TX   SERCOM1_DMAC_ID_TX
+#define EXT2_SPI_SERCOM_DMAC_ID_RX   SERCOM1_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 pin definitions
+ *  @{
+ */
+#define EXT3_PIN_3                PIN_PA02
+#define EXT3_PIN_4                PIN_PA03
+#define EXT3_PIN_5                PIN_PB30
+#define EXT3_PIN_6                PIN_PA15
+#define EXT3_PIN_7                PIN_PA12
+#define EXT3_PIN_8                PIN_PA13
+#define EXT3_PIN_9                PIN_PA28
+#define EXT3_PIN_10               PIN_PA27
+#define EXT3_PIN_11               PIN_PA08
+#define EXT3_PIN_12               PIN_PA09
+#define EXT3_PIN_13               PIN_PB11
+#define EXT3_PIN_14               PIN_PB10
+#define EXT3_PIN_15               PIN_PB17
+#define EXT3_PIN_16               PIN_PB22
+#define EXT3_PIN_17               PIN_PB16
+#define EXT3_PIN_18               PIN_PB23
+/** @} */
+
+/** \name Extension header #3 pin definitions by function
+ *  @{
+ */
+#define EXT3_PIN_ADC_0            EXT3_PIN_3
+#define EXT3_PIN_ADC_1            EXT3_PIN_4
+#define EXT3_PIN_GPIO_0           EXT3_PIN_5
+#define EXT3_PIN_GPIO_1           EXT3_PIN_6
+#define EXT3_PIN_PWM_0            EXT3_PIN_7
+#define EXT3_PIN_PWM_1            EXT3_PIN_8
+#define EXT3_PIN_IRQ              EXT3_PIN_9
+#define EXT3_PIN_I2C_SDA          EXT3_PIN_11
+#define EXT3_PIN_I2C_SCL          EXT3_PIN_12
+#define EXT3_PIN_UART_RX          EXT3_PIN_13
+#define EXT3_PIN_UART_TX          EXT3_PIN_14
+#define EXT3_PIN_SPI_SS_1         EXT3_PIN_10
+#define EXT3_PIN_SPI_SS_0         EXT3_PIN_15
+#define EXT3_PIN_SPI_MOSI         EXT3_PIN_16
+#define EXT3_PIN_SPI_MISO         EXT3_PIN_17
+#define EXT3_PIN_SPI_SCK          EXT3_PIN_18
+/** @} */
+
+/** \name Extension header #3 ADC definitions
+ *  @{
+ */
+#define EXT3_ADC_MODULE           ADC
+#define EXT3_ADC_0_CHANNEL        0
+#define EXT3_ADC_0_PIN            PIN_PA02B_ADC_AIN0
+#define EXT3_ADC_0_MUX            MUX_PA02B_ADC_AIN0
+#define EXT3_ADC_0_PINMUX         PINMUX_PA02B_ADC_AIN0
+#define EXT3_ADC_1_CHANNEL        1
+#define EXT3_ADC_1_PIN            PIN_PA03B_ADC_AIN1
+#define EXT3_ADC_1_MUX            MUX_PA03B_ADC_AIN1
+#define EXT3_ADC_1_PINMUX         PINMUX_PA03B_ADC_AIN1
+/** @} */
+
+/** \name Extension header #3 PWM for Control definitions
+ *  @{
+ */
+#define EXT3_PWM4CTRL_MODULE      TCC2
+#define EXT3_PWM4CTRL_0_CHANNEL   0
+#define EXT3_PWM4CTRL_0_OUTPUT    0
+#define EXT3_PWM4CTRL_0_PIN       PIN_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_0_MUX       MUX_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_0_PINMUX    PINMUX_PA12E_TCC2_WO0
+#define EXT3_PWM4CTRL_1_CHANNEL   1
+#define EXT3_PWM4CTRL_1_OUTPUT    1
+#define EXT3_PWM4CTRL_1_PIN       PIN_PA13E_TCC2_WO1
+#define EXT3_PWM4CTRL_1_MUX       MUX_PA13E_TCC2_WO1
+#define EXT3_PWM4CTRL_1_PINMUX    PINMUX_PA13E_TCC2_WO1
+/** @} */
+
+/** \name Extension header #3 IRQ/External interrupt definitions
+ *  @{
+ */
+#define EXT3_IRQ_MODULE           EIC
+#define EXT3_IRQ_INPUT            8
+#define EXT3_IRQ_PIN              PIN_PA28A_EIC_EXTINT8
+#define EXT3_IRQ_MUX              MUX_PA28A_EIC_EXTINT8
+#define EXT3_IRQ_PINMUX           PINMUX_PA28A_EIC_EXTINT8
+/** @} */
+
+/** \name Extension header #3 I2C definitions
+ *  @{
+ */
+#define EXT3_I2C_MODULE              SERCOM2
+#define EXT3_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EXT3_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+#define EXT3_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
+#define EXT3_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 UART definitions
+ *  @{
+ */
+#define EXT3_UART_MODULE              SERCOM4
+#define EXT3_UART_SERCOM_MUX_SETTING  USART_RX_3_TX_2_XCK_3
+#define EXT3_UART_SERCOM_PINMUX_PAD0  PINMUX_UNUSED
+#define EXT3_UART_SERCOM_PINMUX_PAD1  PINMUX_UNUSED
+#define EXT3_UART_SERCOM_PINMUX_PAD2  PINMUX_PB10D_SERCOM4_PAD2
+#define EXT3_UART_SERCOM_PINMUX_PAD3  PINMUX_PB11D_SERCOM4_PAD3
+#define EXT3_UART_SERCOM_DMAC_ID_TX   SERCOM4_DMAC_ID_TX
+#define EXT3_UART_SERCOM_DMAC_ID_RX   SERCOM4_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 SPI definitions
+ *  @{
+ */
+#define EXT3_SPI_MODULE              SERCOM5
+#define EXT3_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EXT3_SPI_SERCOM_PINMUX_PAD0  PINMUX_PB16C_SERCOM5_PAD0
+#define EXT3_SPI_SERCOM_PINMUX_PAD1  PINMUX_PB17C_SERCOM5_PAD1
+#define EXT3_SPI_SERCOM_PINMUX_PAD2  PINMUX_PB22D_SERCOM5_PAD2
+#define EXT3_SPI_SERCOM_PINMUX_PAD3  PINMUX_PB23D_SERCOM5_PAD3
+#define EXT3_SPI_SERCOM_DMAC_ID_TX   SERCOM5_DMAC_ID_TX
+#define EXT3_SPI_SERCOM_DMAC_ID_RX   SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 Dataflash
+ *  @{
+ */
+#define EXT3_DATAFLASH_SPI_MODULE      EXT3_SPI_MODULE
+#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
+#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
+/** @} */
+
+/** \name USB definitions
+ * @{
+ */
+#define USB_ID
+#define USB_TARGET_DP_PIN            PIN_PA25G_USB_DP
+#define USB_TARGET_DP_MUX            MUX_PA25G_USB_DP
+#define USB_TARGET_DP_PINMUX         PINMUX_PA25G_USB_DP
+#define USB_TARGET_DM_PIN            PIN_PA24G_USB_DM
+#define USB_TARGET_DM_MUX            MUX_PA24G_USB_DM
+#define USB_TARGET_DM_PINMUX         PINMUX_PA24G_USB_DM
+#define USB_VBUS_PIN                 PIN_PA14
+#define USB_VBUS_EIC_LINE            14
+#define USB_VBUS_EIC_MUX             MUX_PA14A_EIC_EXTINT14
+#define USB_VBUS_EIC_PINMUX          PINMUX_PA14A_EIC_EXTINT14
+#define USB_ID_PIN                   PIN_PA03
+#define USB_ID_EIC_LINE              3
+#define USB_ID_EIC_MUX               MUX_PA03A_EIC_EXTINT3
+#define USB_ID_EIC_PINMUX            PINMUX_PA03A_EIC_EXTINT3
+/** @} */
+
+/** \name Embedded debugger GPIO interface definitions
+ * @{
+ */
+#define EDBG_GPIO0_PIN            PIN_PA27
+#define EDBG_GPIO1_PIN            PIN_PA28
+#define EDBG_GPIO2_PIN            PIN_PA20
+#define EDBG_GPIO3_PIN            PIN_PA21
+/** @} */
+
+/** \name Embedded debugger USART interface definitions
+ * @{
+ */
+#define EDBG_UART_MODULE          -1 /* Not available on this board */
+#define EDBG_UART_RX_PIN          -1 /* Not available on this board */
+#define EDBG_UART_RX_MUX          -1 /* Not available on this board */
+#define EDBG_UART_RX_PINMUX       -1 /* Not available on this board */
+#define EDBG_UART_RX_SERCOM_PAD   -1 /* Not available on this board */
+#define EDBG_UART_TX_PIN          -1 /* Not available on this board */
+#define EDBG_UART_TX_MUX          -1 /* Not available on this board */
+#define EDBG_UART_TX_PINMUX       -1 /* Not available on this board */
+#define EDBG_UART_TX_SERCOM_PAD   -1 /* Not available on this board */
+/** @} */
+
+/** \name Embedded debugger I2C interface definitions
+ * @{
+ */
+#define EDBG_I2C_MODULE              SERCOM2
+#define EDBG_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA08D_SERCOM2_PAD0
+#define EDBG_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA09D_SERCOM2_PAD1
+#define EDBG_I2C_SERCOM_DMAC_ID_TX   SERCOM2_DMAC_ID_TX
+#define EDBG_I2C_SERCOM_DMAC_ID_RX   SERCOM2_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger SPI interface definitions
+ * @{
+ */
+#define EDBG_SPI_MODULE              SERCOM5
+#define EDBG_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EDBG_SPI_SERCOM_PINMUX_PAD0  PINMUX_PB16C_SERCOM5_PAD0
+#define EDBG_SPI_SERCOM_PINMUX_PAD1  PINMUX_PB31D_SERCOM5_PAD1
+#define EDBG_SPI_SERCOM_PINMUX_PAD2  PINMUX_PB22D_SERCOM5_PAD2
+#define EDBG_SPI_SERCOM_PINMUX_PAD3  PINMUX_PB23D_SERCOM5_PAD3
+#define EDBG_SPI_SERCOM_DMAC_ID_TX   SERCOM5_DMAC_ID_TX
+#define EDBG_SPI_SERCOM_DMAC_ID_RX   SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger CDC Gateway USART interface definitions
+ * @{
+ */
+#define EDBG_CDC_MODULE              SERCOM3
+#define EDBG_CDC_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
+#define EDBG_CDC_SERCOM_PINMUX_PAD0  PINMUX_PA22C_SERCOM3_PAD0
+#define EDBG_CDC_SERCOM_PINMUX_PAD1  PINMUX_PA23C_SERCOM3_PAD1
+#define EDBG_CDC_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_DMAC_ID_TX   SERCOM3_DMAC_ID_TX
+#define EDBG_CDC_SERCOM_DMAC_ID_RX   SERCOM3_DMAC_ID_RX
+/** @} */
+
+/** @} */
+
+/** \name 802.15.4 TRX Interface definitions
+ * @{
+ */
+#ifndef EXT2_CONFIG
+#define AT86RFX_SPI                  EXT1_SPI_MODULE
+#define AT86RFX_RST_PIN              EXT1_PIN_7
+#define AT86RFX_MISC_PIN             EXT1_PIN_12
+#define AT86RFX_IRQ_PIN              EXT1_PIN_9
+#define AT86RFX_SLP_PIN              EXT1_PIN_10
+#define AT86RFX_SPI_CS               EXT1_PIN_15
+#define AT86RFX_SPI_MOSI             EXT1_PIN_16
+#define AT86RFX_SPI_MISO             EXT1_PIN_17
+#define AT86RFX_SPI_SCK              EXT1_PIN_18
+#define AT86RFX_CSD                  EXT1_PIN_5
+#define AT86RFX_CPS                  EXT1_PIN_8
+
+#define AT86RFX_SPI_SERCOM_MUX_SETTING   EXT1_SPI_SERCOM_MUX_SETTING
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD0   EXT1_SPI_SERCOM_PINMUX_PAD0
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD1   PINMUX_UNUSED
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD2   EXT1_SPI_SERCOM_PINMUX_PAD2
+#define AT86RFX_SPI_SERCOM_PINMUX_PAD3   EXT1_SPI_SERCOM_PINMUX_PAD3
+
+#define AT86RFX_IRQ_CHAN       EXT1_IRQ_INPUT
+#define AT86RFX_IRQ_PINMUX     EXT1_IRQ_PINMUX
+
+
+#endif
+/** Enables the transceiver main interrupt. */
+#define ENABLE_TRX_IRQ()     \
+		extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/** Disables the transceiver main interrupt. */
+#define DISABLE_TRX_IRQ()    \
+		extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/** Clears the transceiver main interrupt. */
+#define CLEAR_TRX_IRQ()      \
+		extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
+
+/*
+ * This macro saves the trx interrupt status and disables the trx interrupt.
+ */
+#define ENTER_TRX_REGION()   \
+		{ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+
+/*
+ *  This macro restores the transceiver interrupt status
+ */
+#define LEAVE_TRX_REGION()   \
+		extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
+
+/** @} */
+
+/**
+ * \brief Turns off the specified LEDs.
+ *
+ * \param led_gpio LED to turn off (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Off(led_gpio)     port_pin_set_output_level(led_gpio,true)
+
+/**
+ * \brief Turns on the specified LEDs.
+ *
+ * \param led_gpio LED to turn on (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_On(led_gpio)      port_pin_set_output_level(led_gpio,false)
+
+/**
+ * \brief Toggles the specified LEDs.
+ *
+ * \param led_gpio LED to toggle (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Toggle(led_gpio)  port_pin_toggle_output_level(led_gpio)
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* SAMD21_XPLAINED_PRO_H_INCLUDED */

asf/sam0/drivers/extint/extint.h

@@ -0,0 +1,707 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef EXTINT_H_INCLUDED
+#define EXTINT_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_extint_group SAM External Interrupt (EXTINT) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of external interrupts
+ * generated by the physical device pins, including edge detection.
+ * The following driver API modes are covered by this
+ * manual:
+ *
+ *  - Polled APIs
+ * \if EXTINT_CALLBACK_MODE
+ *  - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ *  - EIC (External Interrupt Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_extint_prerequisites
+ *  - \ref asfdoc_sam0_extint_module_overview
+ *  - \ref asfdoc_sam0_extint_special_considerations
+ *  - \ref asfdoc_sam0_extint_extra_info
+ *  - \ref asfdoc_sam0_extint_examples
+ *  - \ref asfdoc_sam0_extint_api_overview
+ *
+ *
+ * \section asfdoc_sam0_extint_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_extint_module_overview Module Overview
+ *
+ * The External Interrupt (EXTINT) module provides a method of asynchronously
+ * detecting rising edge, falling edge, or specific level detection on individual
+ * I/O pins of a device. This detection can then be used to trigger a software
+ * interrupt or event, or polled for later use if required. External interrupts
+ * can also optionally be used to automatically wake up the device from sleep
+ * mode, allowing the device to conserve power while still being able to react
+ * to an external stimulus in a timely manner.
+ *
+ * \subsection asfdoc_sam0_extint_logical_channels Logical Channels
+ * The External Interrupt module contains a number of logical channels, each of
+ * which is capable of being individually configured for a given pin routing,
+ * detection mode, and filtering/wake up characteristics.
+ *
+ * Each individual logical external interrupt channel may be routed to a single
+ * physical device I/O pin in order to detect a particular edge or level of the
+ * incoming signal.
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_nmi_chanel NMI Channels
+ *
+ * One or more Non Maskable Interrupt (NMI) channels are provided within each
+ * physical External Interrupt Controller module, allowing a single physical pin
+ * of the device to fire a single NMI interrupt in response to a particular
+ * edge or level stimulus. An NMI cannot, as the name suggests, be disabled in
+ * firmware and will take precedence over any in-progress interrupt sources.
+ *
+ * NMIs can be used to implement critical device features such as forced
+ * software reset or other functionality where the action should be executed in
+ * preference to all other running code with a minimum amount of latency.
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_filtering Input Filtering and Detection
+ *
+ * To reduce the possibility of noise or other transient signals causing
+ * unwanted device wake-ups, interrupts, and/or events via an external interrupt
+ * channel. A hardware signal filter can be enabled on individual channels. This
+ * filter provides a Majority-of-Three voter filter on the incoming signal, so
+ * that the input state is considered to be the majority vote of three
+ * subsequent samples of the pin input buffer. The possible sampled input and
+ * resulting filtered output when the filter is enabled is shown in
+ * \ref asfdoc_sam0_extint_filter_table "the table below".
+ *
+ * \anchor asfdoc_sam0_extint_filter_table
+ * <table>
+ *  <caption>Sampled Input and Resulting Filtered Output</caption>
+ *  <tr>
+ *      <th>Input Sample 1</th>
+ *      <th>Input Sample 2</th>
+ *      <th>Input Sample 3</th>
+ *      <th>Filtered Output</th>
+ *  </tr>
+ *  <tr>
+ *      <td>0</td> <td>0</td> <td>0</td> <td>0</td>
+ *  </tr>
+ *  <tr>
+ *      <td>0</td> <td>0</td> <td>1</td> <td>0</td>
+ *  </tr>
+ *  <tr>
+ *      <td>0</td> <td>1</td> <td>0</td> <td>0</td>
+ *  </tr>
+ *  <tr>
+ *      <td>0</td> <td>1</td> <td>1</td> <td>1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>1</td> <td>0</td> <td>0</td> <td>0</td>
+ *  </tr>
+ *  <tr>
+ *      <td>1</td> <td>0</td> <td>1</td> <td>1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>1</td> <td>1</td> <td>0</td> <td>1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>1</td> <td>1</td> <td>1</td> <td>1</td>
+ *  </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_events Events and Interrupts
+ *
+ * Channel detection states may be polled inside the application for synchronous
+ * detection, or events and interrupts may be used for asynchronous behavior.
+ * Each channel can be configured to give an asynchronous hardware event (which
+ * may in turn trigger actions in other hardware modules) or an asynchronous
+ * software interrupt.
+ *
+ * \note The connection of events between modules requires the use of the
+ *       \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ *       to route output event of one module to the input event of another.
+ *       For more information on event routing, refer to the event driver
+ *       documentation.
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_extint_int_connections "The diagram below" shows how this
+ * module is interconnected within the device.
+ *
+ * \anchor asfdoc_sam0_extint_int_connections
+ * \dot
+ * digraph overview {
+ *   node [label="Port Pad" shape=square] pad;
+ *
+ *   subgraph driver {
+ *     node [label="Peripheral MUX" shape=trapezium] pinmux;
+ *     node [label="EIC Module" shape=ellipse] eic;
+ *     node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ *   }
+ *
+ *   pinmux -> eic;
+ *   pad    -> pinmux;
+ *   pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ * \section asfdoc_sam0_extint_special_considerations Special Considerations
+ *
+ * Not all devices support disabling of the NMI channel(s) detection mode - see
+ * your device datasheet.
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_extint_extra. This includes:
+ *  - \ref asfdoc_sam0_extint_extra_acronyms
+ *  - \ref asfdoc_sam0_extint_extra_dependencies
+ *  - \ref asfdoc_sam0_extint_extra_errata
+ *  - \ref asfdoc_sam0_extint_extra_history
+ *
+ *
+ * \section asfdoc_sam0_extint_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_extint_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_extint_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <pinmux.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief External interrupt edge detection configuration enum.
+ *
+ * Enum for the possible signal edge detection modes of the External
+ * Interrupt Controller module.
+ */
+enum extint_detect {
+	/** No edge detection. Not allowed as a NMI detection mode on some
+	 *  devices. */
+	EXTINT_DETECT_NONE    = 0,
+	/** Detect rising signal edges */
+	EXTINT_DETECT_RISING  = 1,
+	/** Detect falling signal edges */
+	EXTINT_DETECT_FALLING = 2,
+	/** Detect both signal edges */
+	EXTINT_DETECT_BOTH    = 3,
+	/** Detect high signal levels */
+	EXTINT_DETECT_HIGH    = 4,
+	/** Detect low signal levels */
+	EXTINT_DETECT_LOW     = 5,
+};
+
+/**
+ * \brief External interrupt internal pull configuration enum.
+ *
+ * Enum for the possible pin internal pull configurations.
+ *
+ * \note Disabling the internal pull resistor is not recommended if the driver
+ *       is used in interrupt (callback) mode, due the possibility of floating
+ *       inputs generating continuous interrupts.
+ */
+enum extint_pull {
+	/** Internal pull-up resistor is enabled on the pin */
+	EXTINT_PULL_UP        = SYSTEM_PINMUX_PIN_PULL_UP,
+	/** Internal pull-down resistor is enabled on the pin */
+	EXTINT_PULL_DOWN      = SYSTEM_PINMUX_PIN_PULL_DOWN,
+	/** Internal pull resistor is disconnected from the pin */
+	EXTINT_PULL_NONE      = SYSTEM_PINMUX_PIN_PULL_NONE,
+};
+
+/** The EIC is clocked by GCLK_EIC. */
+#define EXTINT_CLK_GCLK   0
+/** The EIC is clocked by CLK_ULP32K. */
+#define EXTINT_CLK_ULP32K 1
+
+/**
+ * \brief External Interrupt Controller channel configuration structure.
+ *
+ *  Configuration structure for the edge detection mode of an external
+ *  interrupt channel.
+ */
+struct extint_chan_conf {
+	/** GPIO pin the NMI should be connected to */
+	uint32_t gpio_pin;
+	/** MUX position the GPIO pin should be configured to */
+	uint32_t gpio_pin_mux;
+	/** Internal pull to enable on the input pin */
+	enum extint_pull gpio_pin_pull;
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	/** Enable asynchronous edge detection. */
+	bool enable_async_edge_detection;
+#else
+	/** Wake up the device if the channel interrupt fires during sleep mode */
+	bool wake_if_sleeping;
+#endif
+	/** Filter the raw input signal to prevent noise from triggering an
+	 *  interrupt accidentally, using a three sample majority filter */
+	bool filter_input_signal;
+	/** Edge detection mode to use */
+	enum extint_detect detection_criteria;
+};
+
+/**
+ * \brief External Interrupt event enable/disable structure.
+ *
+ * Event flags for the \ref extint_enable_events() and
+ * \ref extint_disable_events().
+ */
+struct extint_events {
+	/** If \c true, an event will be generated when an external interrupt
+	 *  channel detection state changes */
+	bool generate_event_on_detect[32 * EIC_INST_NUM];
+};
+
+/**
+ * \brief External Interrupt Controller NMI configuration structure.
+ *
+ *  Configuration structure for the edge detection mode of an external
+ *  interrupt NMI channel.
+ */
+struct extint_nmi_conf {
+	/** GPIO pin the NMI should be connected to */
+	uint32_t gpio_pin;
+	/** MUX position the GPIO pin should be configured to */
+	uint32_t gpio_pin_mux;
+	/** Internal pull to enable on the input pin */
+	enum extint_pull gpio_pin_pull;
+	/** Filter the raw input signal to prevent noise from triggering an
+	 *  interrupt accidentally, using a three sample majority filter */
+	bool filter_input_signal;
+	/** Edge detection mode to use. Not all devices support all possible
+	 *  detection modes for NMIs.
+	 */
+	enum extint_detect detection_criteria;
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	/** Enable asynchronous edge detection. */
+	bool enable_async_edge_detection;
+#endif
+};
+
+#if EXTINT_CALLBACK_MODE == true
+/** Type definition for an EXTINT module callback function */
+typedef void (*extint_callback_t)(void);
+
+#ifndef EIC_NUMBER_OF_INTERRUPTS
+#  define EIC_NUMBER_OF_INTERRUPTS 16
+#endif
+#endif
+
+#if !defined(__DOXYGEN__)
+/** \internal
+ *  Internal EXTINT module device instance structure definition.
+ */
+struct _extint_module
+{
+#  if EXTINT_CALLBACK_MODE == true
+	/** Asynchronous channel callback table, for user-registered handlers */
+	extint_callback_t callbacks[EIC_NUMBER_OF_INTERRUPTS];
+#  else
+	/** Dummy value to ensure the struct has at least one member */
+	uint8_t _dummy;
+#  endif
+};
+
+/**
+ * \brief Retrieves the base EIC module address from a given channel number.
+ *
+ * Retrieves the base address of a EIC hardware module associated with the
+ * given external interrupt channel.
+ *
+ * \param[in] channel  External interrupt channel index to convert
+ *
+ * \return Base address of the associated EIC module.
+ */
+static inline Eic * _extint_get_eic_from_channel(
+		const uint8_t channel)
+{
+	uint8_t eic_index = (channel / 32);
+
+	if (eic_index < EIC_INST_NUM) {
+		/* Array of available EICs */
+		Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+		return eics[eic_index];
+	} else {
+		Assert(false);
+		return NULL;
+	}
+}
+
+/**
+ * \brief Retrieves the base EIC module address from a given NMI channel number.
+ *
+ * Retrieves the base address of a EIC hardware module associated with the
+ * given non-maskable external interrupt channel.
+ *
+ * \param[in] nmi_channel  Non-Maskable interrupt channel index to convert
+ *
+ * \return Base address of the associated EIC module.
+ */
+static inline Eic * _extint_get_eic_from_nmi(
+		const uint8_t nmi_channel)
+{
+	uint8_t eic_index = nmi_channel;
+
+	if (eic_index < EIC_INST_NUM) {
+		/* Array of available EICs */
+		Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+		return eics[eic_index];
+	} else {
+		Assert(false);
+		return NULL;
+	}
+}
+#endif
+
+/** \name Event Management
+ * @{
+ */
+
+void extint_enable_events(
+		struct extint_events *const events);
+
+void extint_disable_events(
+		struct extint_events *const events);
+
+/** @} */
+
+/** \name Configuration and Initialization (Channel)
+ * @{
+ */
+
+void extint_chan_get_config_defaults(
+		struct extint_chan_conf *const config);
+
+void extint_chan_set_config(
+		const uint8_t channel,
+		const struct extint_chan_conf *const config);
+
+/** @} */
+
+/** \name Configuration and Initialization (NMI)
+ * @{
+ */
+
+/**
+ * \brief Initializes an External Interrupt NMI channel configuration structure to defaults.
+ *
+ * Initializes a given External Interrupt NMI channel configuration structure
+ * to a set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Input filtering disabled
+ * \li Detect falling edges of a signal
+ * \li Asynchronous edge detection is disabled
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void extint_nmi_get_config_defaults(
+		struct extint_nmi_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->gpio_pin            = 0;
+	config->gpio_pin_mux        = 0;
+	config->gpio_pin_pull       = EXTINT_PULL_UP;
+	config->filter_input_signal = false;
+	config->detection_criteria  = EXTINT_DETECT_FALLING;
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
+	 config->enable_async_edge_detection = false;
+#endif
+
+}
+
+enum status_code extint_nmi_set_config(
+		const uint8_t nmi_channel,
+		const struct extint_nmi_conf *const config);
+
+/** @} */
+
+/** \name Detection testing and clearing (channel)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the edge detection state of a configured channel.
+ *
+ *  Reads the current state of a configured channel, and determines
+ *  if the detection criteria of the channel has been met.
+ *
+ *  \param[in] channel  External Interrupt channel index to check
+ *
+ *  \return Status of the requested channel's edge detection state.
+ *  \retval true   If the channel's edge/level detection criteria was met
+ *  \retval false  If the channel has not detected its configured criteria
+ */
+static inline bool extint_chan_is_detected(
+		const uint8_t channel)
+{
+	Eic *const eic_module = _extint_get_eic_from_channel(channel);
+	uint32_t eic_mask   = (1UL << (channel % 32));
+
+	return (eic_module->INTFLAG.reg & eic_mask);
+}
+
+/**
+ * \brief Clears the edge detection state of a configured channel.
+ *
+ *  Clears the current state of a configured channel, readying it for
+ *  the next level or edge detection.
+ *
+ *  \param[in] channel  External Interrupt channel index to check
+ */
+static inline void extint_chan_clear_detected(
+		const uint8_t channel)
+{
+	Eic *const eic_module = _extint_get_eic_from_channel(channel);
+	uint32_t eic_mask   = (1UL << (channel % 32));
+
+	eic_module->INTFLAG.reg = eic_mask;
+}
+
+/** @} */
+
+/** \name Detection Testing and Clearing (NMI)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the edge detection state of a configured NMI channel.
+ *
+ *  Reads the current state of a configured NMI channel, and determines
+ *  if the detection criteria of the NMI channel has been met.
+ *
+ *  \param[in] nmi_channel  External Interrupt NMI channel index to check
+ *
+ *  \return Status of the requested NMI channel's edge detection state.
+ *  \retval true   If the NMI channel's edge/level detection criteria was met
+ *  \retval false  If the NMI channel has not detected its configured criteria
+ */
+static inline bool extint_nmi_is_detected(
+		const uint8_t nmi_channel)
+{
+	Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
+
+	return (eic_module->NMIFLAG.reg & EIC_NMIFLAG_NMI);
+}
+
+/**
+ * \brief Clears the edge detection state of a configured NMI channel.
+ *
+ *  Clears the current state of a configured NMI channel, readying it for
+ *  the next level or edge detection.
+ *
+ *  \param[in] nmi_channel  External Interrupt NMI channel index to check
+ */
+static inline void extint_nmi_clear_detected(
+		const uint8_t nmi_channel)
+{
+	Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
+
+	eic_module->NMIFLAG.reg = EIC_NMIFLAG_NMI;
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#if EXTINT_CALLBACK_MODE == true
+#  include "extint_callback.h"
+#endif
+
+/**
+ * \page asfdoc_sam0_extint_extra Extra Information for EXTINT Driver
+ *
+ * \section asfdoc_sam0_extint_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>EIC</td>
+ *      <td>External Interrupt Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MUX</td>
+ *      <td>Multiplexer</td>
+ *  </tr>
+ *  <tr>
+ *      <td>NMI</td>
+ *      <td>Non-Maskable Interrupt</td>
+ *  </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>
+ *      \li Driver updated to follow driver type convention
+ *      \li Removed \c %extint_reset(), \c %extint_disable() and
+ *          \c extint_enable() functions. Added internal function
+ *          \c %_system_extint_init().
+ *      \li Added configuration EXTINT_CLOCK_SOURCE in conf_extint.h
+ *      \li Removed configuration EXTINT_CALLBACKS_MAX in conf_extint.h, and
+ *          added channel parameter in the register functions
+ *         \c %extint_register_callback() and \c %extint_unregister_callback()
+ *      </td>
+ *  </tr>
+ *  <tr>
+ *      <td>Updated interrupt handler to clear interrupt flag before calling
+ *          callback function</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Updated initialization function to also enable the digital interface
+ *          clock to the module if it is disabled</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_extint_exqsg Examples for EXTINT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_extint_group.
+ * QSGs are simple examples with step-by-step instructions to configure and
+ * use this driver in a selection of use cases. Note that a QSG can be compiled
+ * as a standalone application or be added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_extint_basic_use_case
+ * \if EXTINT_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_extint_callback_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_extint_document_revision_history Document Revision History
+ *
+ * <table>
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42112E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAM C21, SAM D09, and SAM DA1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42112D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42112C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42112B</td>
+ *      <td>06/2013</td>
+ *      <td>Added additional documentation on the event system. Corrected
+ *          documentation typos.</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42112A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
+ * </table>
+ */
+
+#endif

asf/sam0/drivers/extint/extint_callback.c

@@ -0,0 +1,232 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "extint.h"
+#include "extint_callback.h"
+
+/**
+ * \internal
+ * Internal driver device instance struct, declared in the main module driver.
+ */
+extern struct _extint_module _extint_dev;
+
+/**
+ * \internal
+ * This is the number of the channel whose callback is currently running.
+ */
+uint8_t _current_channel;
+
+/**
+ * \brief Registers an asynchronous callback function with the driver.
+ *
+ * Registers an asynchronous callback with the EXTINT driver, fired when a
+ * channel detects the configured channel detection criteria
+ * (e.g. edge or level). Callbacks are fired once for each detected channel.
+ *
+ * \note NMI channel callbacks cannot be registered via this function; the
+ *       device's NMI interrupt should be hooked directly in the user
+ *       application and the NMI flags manually cleared via
+ *       \ref extint_nmi_clear_detected().
+ *
+ * \param[in] callback  Pointer to the callback function to register
+ * \param[in] channel   Logical channel to register callback for
+ * \param[in] type      Type of callback function to register
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK               The callback was registered successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ * \retval STATUS_ERR_ALREADY_INITIALIZED    Callback function has been
+ *                                  registered, need unregister first
+ */
+enum status_code extint_register_callback(
+	const extint_callback_t callback,
+	const uint8_t channel,
+	const enum extint_callback_type type)
+{
+	/* Sanity check arguments */
+	Assert(callback);
+
+	if (type != EXTINT_CALLBACK_TYPE_DETECT) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	if (_extint_dev.callbacks[channel] == NULL) {
+		_extint_dev.callbacks[channel] = callback;
+		return STATUS_OK;
+	} else if (_extint_dev.callbacks[channel] == callback) {
+		return STATUS_OK;
+	}
+
+	return STATUS_ERR_ALREADY_INITIALIZED;
+}
+
+/**
+ * \brief Unregisters an asynchronous callback function with the driver.
+ *
+ * Unregisters an asynchronous callback with the EXTINT driver, removing it
+ * from the internal callback registration table.
+ *
+ * \param[in] callback  Pointer to the callback function to unregister
+ * \param[in] channel   Logical channel to unregister callback for
+ * \param[in] type      Type of callback function to unregister
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK               The callback was unregistered successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ * \retval STATUS_ERR_BAD_ADDRESS  No matching entry was found in the
+ *                                 registration table
+ */
+enum status_code extint_unregister_callback(
+	const extint_callback_t callback,
+	const uint8_t channel,
+	const enum extint_callback_type type)
+{
+	/* Sanity check arguments */
+	Assert(callback);
+
+	if (type != EXTINT_CALLBACK_TYPE_DETECT) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	if (_extint_dev.callbacks[channel] == callback) {
+		_extint_dev.callbacks[channel] = NULL;
+		return STATUS_OK;
+	}
+
+	return STATUS_ERR_BAD_ADDRESS;
+}
+
+/**
+ * \brief Enables asynchronous callback generation for a given channel and type.
+ *
+ * Enables asynchronous callbacks for a given logical external interrupt channel
+ * and type. This must be called before an external interrupt channel will
+ * generate callback events.
+ *
+ * \param[in] channel  Logical channel to enable callback generation for
+ * \param[in] type     Type of callback function callbacks to enable
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK               The callback was enabled successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ */
+enum status_code extint_chan_enable_callback(
+	const uint8_t channel,
+	const enum extint_callback_type type)
+{
+	if (type == EXTINT_CALLBACK_TYPE_DETECT) {
+		Eic *const eic = _extint_get_eic_from_channel(channel);
+
+		eic->INTENSET.reg = (1UL << channel);
+	}
+	else {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables asynchronous callback generation for a given channel and type.
+ *
+ * Disables asynchronous callbacks for a given logical external interrupt
+ * channel and type.
+ *
+ * \param[in] channel  Logical channel to disable callback generation for
+ * \param[in] type     Type of callback function callbacks to disable
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK               The callback was disabled successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ */
+enum status_code extint_chan_disable_callback(
+	const uint8_t channel,
+	const enum extint_callback_type type)
+{
+	if (type == EXTINT_CALLBACK_TYPE_DETECT) {
+		Eic *const eic = _extint_get_eic_from_channel(channel);
+
+		eic->INTENCLR.reg = (1UL << channel);
+	}
+	else {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Find what channel caused the callback.
+ *
+ * Can be used in an EXTINT callback function to find what channel caused
+ * the callback in case the same callback is used by multiple channels.
+ *
+ * \return Channel number.
+ */
+uint8_t extint_get_current_channel(void)
+{
+	return _current_channel;
+}
+
+/** Handler for the EXTINT hardware module interrupt. */
+void EIC_Handler(void)
+{
+	/* Find any triggered channels, run associated callback handlers */
+	for (_current_channel = 0; _current_channel < EIC_NUMBER_OF_INTERRUPTS ; _current_channel++) {
+		if (extint_chan_is_detected(_current_channel)) {
+			/* Clear flag */
+			extint_chan_clear_detected(_current_channel);
+			/* Find any associated callback entries in the callback table */
+			if (_extint_dev.callbacks[_current_channel] != NULL) {
+				/* Run the registered callback */
+				_extint_dev.callbacks[_current_channel]();
+			}
+		}
+	}
+}

asf/sam0/drivers/extint/extint_callback.h

@@ -0,0 +1,108 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef EXTINT_CALLBACK_H_INCLUDED
+#define EXTINT_CALLBACK_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_extint_group
+ *
+ * @{
+ */
+
+/** \name Callback Configuration and Initialization
+ * @{
+ */
+
+/** Enum for the possible callback types for the EXTINT module. */
+enum extint_callback_type
+{
+	/** Callback type for when an external interrupt detects the configured
+	 *  channel criteria (i.e. edge or level detection)
+	 */
+	EXTINT_CALLBACK_TYPE_DETECT,
+};
+
+enum status_code extint_register_callback(
+	const extint_callback_t callback,
+	const uint8_t channel,
+	const enum extint_callback_type type);
+
+enum status_code extint_unregister_callback(
+	const extint_callback_t callback,
+	const uint8_t channel,
+	const enum extint_callback_type type);
+
+uint8_t extint_get_current_channel(void);
+
+/** @} */
+
+/** \name Callback Enabling and Disabling (Channel)
+ * @{
+ */
+
+enum status_code extint_chan_enable_callback(
+	const uint8_t channel,
+	const enum extint_callback_type type);
+
+enum status_code extint_chan_disable_callback(
+	const uint8_t channel,
+	const enum extint_callback_type type);
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

asf/sam0/drivers/extint/extint_sam_d_r/extint.c

@@ -0,0 +1,425 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <system.h>
+#include <system_interrupt.h>
+#include <extint.h>
+#include <conf_extint.h>
+
+#if !defined(EXTINT_CLOCK_SOURCE) || defined(__DOXYGEN__)
+#  warning  EXTINT_CLOCK_SOURCE is not defined, assuming GCLK_GENERATOR_0.
+
+/** Configuration option, setting the EIC clock source which can be used for
+ *  EIC edge detection or filtering. This option may be overridden in the module
+ *  configuration header file \c conf_extint.h.
+ */
+#  define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0
+#endif
+
+/**
+ * \internal
+ * Internal driver device instance struct.
+ */
+struct _extint_module _extint_dev;
+
+/**
+ * \brief Determin if the general clock is required
+ *
+ * \param[in] filter_input_signal Filter the raw input signal to prevent noise
+ * \param[in] detection_criteria  Edge detection mode to use (\ref extint_detect)
+ */
+#define _extint_is_gclk_required(filter_input_signal, detection_criteria) \
+		((filter_input_signal) ? true : (\
+			(EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\
+			(EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\
+			(EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false))))
+
+static void _extint_enable(void);
+static void _extint_disable(void);
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true  If the module synchronization is ongoing
+ * \retval false If the module has completed synchronization
+ */
+static inline bool extint_is_syncing(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		if (eics[i]->STATUS.reg & EIC_STATUS_SYNCBUSY) {
+			return true;
+		}
+	}
+	return false;
+}
+/**
+ * \internal
+ * \brief Initializes and enables the External Interrupt driver.
+ *
+ * Enable the clocks used by External Interrupt driver.
+ *
+ * Resets the External Interrupt driver, resetting all hardware
+ * module registers to their power-on defaults, then enable it for further use.
+ *
+ * Reset the callback list if callback mode is used.
+ *
+ * This function must be called before attempting to use any NMI or standard
+ * external interrupt channel functions.
+ *
+ * \note When SYSTEM module is used, this function will be invoked by
+ * \ref system_init() automatically if the module is included.
+ */
+void _system_extint_init(void);
+void _system_extint_init(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_EIC);
+
+	/* Configure the generic clock for the module and enable it */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE;
+	system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf);
+
+	/* Enable the clock anyway, since when needed it will be requested
+	 * by External Interrupt driver */
+	system_gclk_chan_enable(EIC_GCLK_ID);
+
+	/* Reset all EIC hardware modules. */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRL.reg |= EIC_CTRL_SWRST;
+	}
+
+	while (extint_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+
+	/* Reset the software module */
+#if EXTINT_CALLBACK_MODE == true
+	/* Clear callback registration table */
+	for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) {
+		_extint_dev.callbacks[j] = NULL;
+	}
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC);
+#endif
+
+	/* Enables the driver for further use */
+	_extint_enable();
+}
+
+/**
+ * \internal
+ * \brief Enables the External Interrupt driver.
+ *
+ * Enables EIC modules.
+ * Registered callback list will not be affected if callback mode is used.
+ */
+void _extint_enable(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Enable all EIC hardware modules. */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRL.reg |= EIC_CTRL_ENABLE;
+	}
+
+	while (extint_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+}
+
+/**
+ * \internal
+ * \brief Disables the External Interrupt driver.
+ *
+ * Disables EIC modules that were previously started via a call to
+ * \ref _extint_enable().
+ * Registered callback list will not be affected if callback mode is used.
+ */
+void _extint_disable(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Disable all EIC hardware modules. */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRL.reg &= ~EIC_CTRL_ENABLE;
+	}
+
+	while (extint_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+}
+
+/**
+ * \brief Initializes an External Interrupt channel configuration structure to defaults.
+ *
+ * Initializes a given External Interrupt channel configuration structure to a
+ * set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Wake the device if an edge detection occurs whilst in sleep
+ * \li Input filtering disabled
+ * \li Internal pull-up enabled
+ * \li Detect falling edges of a signal
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+void extint_chan_get_config_defaults(
+		struct extint_chan_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->gpio_pin            = 0;
+	config->gpio_pin_mux        = 0;
+	config->gpio_pin_pull       = EXTINT_PULL_UP;
+	config->wake_if_sleeping    = true;
+	config->filter_input_signal = false;
+	config->detection_criteria  = EXTINT_DETECT_FALLING;
+}
+
+/**
+ * \brief Writes an External Interrupt channel configuration to the hardware module.
+ *
+ * Writes out a given configuration of an External Interrupt channel
+ * configuration to the hardware module. If the channel is already configured,
+ * the new configuration will replace the existing one.
+ *
+ * \param[in] channel   External Interrupt channel to configure
+ * \param[in] config    Configuration settings for the channel
+
+ */
+void extint_chan_set_config(
+		const uint8_t channel,
+		const struct extint_chan_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+	/* Sanity check clock requirements */
+	Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
+		_extint_is_gclk_required(config->filter_input_signal,
+			config->detection_criteria)));
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = config->gpio_pin_mux;
+	pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
+	system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
+
+	/* Get a pointer to the module hardware instance */
+	Eic *const EIC_module = _extint_get_eic_from_channel(channel);
+
+	uint32_t config_pos = (4 * (channel % 8));
+	uint32_t new_config;
+
+	/* Determine the channel's new edge detection configuration */
+	new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos);
+
+	/* Enable the hardware signal filter if requested in the config */
+	if (config->filter_input_signal) {
+		new_config |= EIC_CONFIG_FILTEN0;
+	}
+
+	/* Clear the existing and set the new channel configuration */
+	EIC_module->CONFIG[channel / 8].reg
+		= (EIC_module->CONFIG[channel / 8].reg &
+			~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) |
+			(new_config << config_pos);
+
+	/* Set the channel's new wake up mode setting */
+	if (config->wake_if_sleeping) {
+		EIC_module->WAKEUP.reg |=  (1UL << channel);
+	} else {
+		EIC_module->WAKEUP.reg &= ~(1UL << channel);
+	}
+}
+
+/**
+ * \brief Writes an External Interrupt NMI channel configuration to the hardware module.
+ *
+ *  Writes out a given configuration of an External Interrupt NMI channel
+ *  configuration to the hardware module. If the channel is already configured,
+ *  the new configuration will replace the existing one.
+ *
+ *  \param[in] nmi_channel   External Interrupt NMI channel to configure
+ *  \param[in] config        Configuration settings for the channel
+ *
+ * \returns Status code indicating the success or failure of the request.
+ * \retval  STATUS_OK                   Configuration succeeded
+ * \retval  STATUS_ERR_PIN_MUX_INVALID  An invalid pinmux value was supplied
+ * \retval  STATUS_ERR_BAD_FORMAT       An invalid detection mode was requested
+ */
+enum status_code extint_nmi_set_config(
+		const uint8_t nmi_channel,
+		const struct extint_nmi_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+	/* Sanity check clock requirements */
+	Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
+		_extint_is_gclk_required(config->filter_input_signal,
+			config->detection_criteria)));
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = config->gpio_pin_mux;
+	pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	pinmux_config.input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
+	system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
+
+	/* Get a pointer to the module hardware instance */
+	Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel);
+
+	uint32_t new_config;
+
+	/* Determine the NMI's new edge detection configuration */
+	new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos);
+
+	/* Enable the hardware signal filter if requested in the config */
+	if (config->filter_input_signal) {
+		new_config |= EIC_NMICTRL_NMIFILTEN;
+	}
+
+	/* Disable EIC and general clock to configure NMI */
+	_extint_disable();
+	system_gclk_chan_disable(EIC_GCLK_ID);
+
+	EIC_module->NMICTRL.reg = new_config;
+
+	/* Enable the general clock and EIC after configure NMI */
+	system_gclk_chan_enable(EIC_GCLK_ID);
+	_extint_enable();
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables an External Interrupt event output.
+ *
+ *  Enables one or more output events from the External Interrupt module. See
+ *  \ref extint_events "here" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] events    Struct containing flags of events to enable
+ */
+void extint_enable_events(
+		struct extint_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(events);
+
+	/* Array of available EICs. */
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Update the event control register for each physical EIC instance */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		uint32_t event_mask = 0;
+
+		/* Create an enable mask for the current EIC module */
+		for (uint32_t j = 0; j < 32; j++) {
+			if (events->generate_event_on_detect[(32 * i) + j]) {
+				event_mask |= (1UL << j);
+			}
+		}
+
+		/* Enable the masked events */
+		eics[i]->EVCTRL.reg |= event_mask;
+	}
+}
+
+/**
+ * \brief Disables an External Interrupt event output.
+ *
+ *  Disables one or more output events from the External Interrupt module. See
+ *  \ref extint_events "here" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] events    Struct containing flags of events to disable
+ */
+void extint_disable_events(
+		struct extint_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(events);
+
+	/* Array of available EICs. */
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Update the event control register for each physical EIC instance */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		uint32_t event_mask = 0;
+
+		/* Create a disable mask for the current EIC module */
+		for (uint32_t j = 0; j < 32; j++) {
+			if (events->generate_event_on_detect[(32 * i) + j]) {
+				event_mask |= (1UL << j);
+			}
+		}
+
+		/* Disable the masked events */
+		eics[i]->EVCTRL.reg &= ~event_mask;
+	}
+}

asf/sam0/drivers/port/port.c

@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <port.h>
+
+/**
+ *  \brief Writes a Port pin configuration to the hardware module.
+ *
+ *  Writes out a given configuration of a Port pin configuration to the hardware
+ *  module.
+ *
+ *  \note If the pin direction is set as an output, the pull-up/pull-down input
+ *        configuration setting is ignored.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to configure
+ *  \param[in] config    Configuration settings for the pin
+ */
+void port_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct port_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
+	pinmux_config.powersave    = config->powersave;
+
+	system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
+}
+
+/**
+ *  \brief Writes a Port group configuration group to the hardware module.
+ *
+ *  Writes out a given configuration of a Port group configuration to the
+ *  hardware module.
+ *
+ *  \note If the pin direction is set as an output, the pull-up/pull-down input
+ *        configuration setting is ignored.
+ *
+ *  \param[out] port    Base of the PORT module to write to
+ *  \param[in]  mask    Mask of the port pin(s) to configure
+ *  \param[in]  config  Configuration settings for the pin group
+ */
+void port_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct port_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(port);
+	Assert(config);
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
+	pinmux_config.powersave    = config->powersave;
+
+	system_pinmux_group_set_config(port, mask, &pinmux_config);
+}

asf/sam0/drivers/port/port.h

@@ -0,0 +1,792 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef PORT_H_INCLUDED
+#define PORT_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_port_group SAM Port (PORT) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's General
+ * Purpose Input/Output (GPIO) pin functionality, for manual pin state reading
+ * and writing.
+ *
+ * The following peripheral is used by this module:
+ *  - PORT (GPIO Management)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM R30
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_port_prerequisites
+ *  - \ref asfdoc_sam0_port_module_overview
+ *  - \ref asfdoc_sam0_port_special_considerations
+ *  - \ref asfdoc_sam0_port_extra_info
+ *  - \ref asfdoc_sam0_port_examples
+ *  - \ref asfdoc_sam0_port_api_overview
+ *
+ *
+ * \section asfdoc_sam0_port_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_port_module_overview Module Overview
+ *
+ * The device GPIO (PORT) module provides an interface between the user
+ * application logic and external hardware peripherals, when general pin state
+ * manipulation is required. This driver provides an easy-to-use interface to
+ * the physical pin input samplers and output drivers, so that pins can be read
+ * from or written to for general purpose external hardware control.
+ *
+ * \subsection asfdoc_sam0_port_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_PORT_INPUT_EVENT</td>
+ *    <td>SAM L21/L22/C20/C21/R30</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_port_module_overview_pin_numbering Physical and Logical GPIO Pins
+ * SAM devices use two naming conventions for the I/O pins in the device; one
+ * physical and one logical. Each physical pin on a device package is assigned
+ * both a physical port and pin identifier (e.g. "PORTA.0") as well as a
+ * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
+ * former is used to map physical pins to their physical internal device module
+ * counterparts, for simplicity the design of this driver uses the logical GPIO
+ * numbers instead.
+ *
+ * \subsection asfdoc_sam0_port_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_port_module_int_connections "The diagram below" shows how
+ * this module is interconnected within the device.
+ *
+ * \anchor asfdoc_sam0_port_module_int_connections
+ * \dot
+ * digraph overview {
+ *   node [label="Port Pad" shape=square] pad;
+ *
+ *   subgraph driver {
+ *     node [label="Peripheral MUX" shape=trapezium] pinmux;
+ *     node [label="GPIO Module" shape=ellipse] gpio;
+ *     node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ *   }
+ *
+ *   pinmux -> gpio;
+ *   pad    -> pinmux;
+ *   pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ *
+ * \section asfdoc_sam0_port_special_considerations Special Considerations
+ *
+ * The SAM port pin input sampler can be disabled when the pin is configured
+ * in pure output mode to save power; reading the pin state of a pin configured
+ * in output-only mode will read the logical output state that was last set.
+ *
+ * \section asfdoc_sam0_port_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_port_extra. This includes:
+ *  - \ref asfdoc_sam0_port_extra_acronyms
+ *  - \ref asfdoc_sam0_port_extra_dependencies
+ *  - \ref asfdoc_sam0_port_extra_errata
+ *  - \ref asfdoc_sam0_port_extra_history
+ *
+ *
+ * \section asfdoc_sam0_port_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_port_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_port_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <pinmux.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Driver Feature Definition
+ * Define port features set according to different device family.
+ * @{
+*/
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__)
+/** Event input control feature support for PORT group. */
+#  define FEATURE_PORT_INPUT_EVENT
+#endif
+/*@}*/
+
+/** \name PORT Alias Macros
+ * @{
+ */
+
+/** Convenience definition for GPIO module group A on the device (if
+ *  available). */
+#if (PORT_GROUPS > 0) || defined(__DOXYGEN__)
+#  define PORTA             PORT->Group[0]
+#endif
+
+#if (PORT_GROUPS > 1) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group B on the device (if
+ *  available). */
+#  define PORTB             PORT->Group[1]
+#endif
+
+#if (PORT_GROUPS > 2) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group C on the device (if
+ *  available). */
+#  define PORTC             PORT->Group[2]
+#endif
+
+#if (PORT_GROUPS > 3) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group D on the device (if
+ *  available). */
+#  define PORTD             PORT->Group[3]
+#endif
+
+/** @} */
+
+/**
+ *  \brief Port pin direction configuration enum.
+ *
+ *  Enum for the possible pin direction settings of the port pin configuration
+ *  structure, to indicate the direction the pin should use.
+ */
+enum port_pin_dir {
+	/** The pin's input buffer should be enabled, so that the pin state can
+	 *  be read */
+	PORT_PIN_DIR_INPUT               = SYSTEM_PINMUX_PIN_DIR_INPUT,
+	/** The pin's output buffer should be enabled, so that the pin state can
+	 *  be set */
+	PORT_PIN_DIR_OUTPUT              = SYSTEM_PINMUX_PIN_DIR_OUTPUT,
+	/** The pin's output and input buffers should be enabled, so that the pin
+	 *  state can be set and read back */
+	PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
+};
+
+/**
+ *  \brief Port pin input pull configuration enum.
+ *
+ *  Enum for the possible pin pull settings of the port pin configuration
+ *  structure, to indicate the type of logic level pull the pin should use.
+ */
+enum port_pin_pull {
+	/** No logical pull should be applied to the pin */
+	PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
+	/** Pin should be pulled up when idle */
+	PORT_PIN_PULL_UP   = SYSTEM_PINMUX_PIN_PULL_UP,
+	/** Pin should be pulled down when idle */
+	PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
+};
+
+#ifdef FEATURE_PORT_INPUT_EVENT
+/**
+ *  \brief Port input event action.
+ *
+ *  List of port input events action on pin.
+ */
+enum port_input_event_action {
+	/** Event out to pin */
+	PORT_INPUT_EVENT_ACTION_OUT = 0,
+	/** Set output register of pin on event */
+	PORT_INPUT_EVENT_ACTION_SET,
+	/** Clear output register pin on event */
+	PORT_INPUT_EVENT_ACTION_CLR,
+	/** Toggle output register pin on event */
+	PORT_INPUT_EVENT_ACTION_TGL,
+};
+
+/**
+ *  \brief Port input event.
+ *
+ *  List of port input events.
+ */
+enum port_input_event{
+	/** Port input event 0 */
+	PORT_INPUT_EVENT_0 = 0,
+	/** Port input event 1 */
+	PORT_INPUT_EVENT_1 = 1,
+	/** Port input event 2 */
+	PORT_INPUT_EVENT_2 = 2,
+	/** Port input event 3 */
+	PORT_INPUT_EVENT_3 = 3,
+};
+
+/**
+ *  \brief Port input event configuration structure.
+ *
+ *  Configuration structure for a port input event.
+ */
+struct port_input_event_config{
+	/** Port input event action */
+	enum port_input_event_action  action;
+	/** GPIO pin */
+	uint8_t gpio_pin;
+};
+#endif
+
+/**
+ *  \brief Port pin configuration structure.
+ *
+ *  Configuration structure for a port pin instance. This structure should be
+ *  initialized by the \ref port_get_config_defaults() function before being
+ *  modified by the user application.
+ */
+struct port_config {
+	/** Port buffer input/output direction */
+	enum port_pin_dir  direction;
+
+	/** Port pull-up/pull-down for input pins */
+	enum port_pin_pull input_pull;
+
+	/** Enable lowest possible powerstate on the pin
+	 *
+	 *  \note All other configurations will be ignored, the pin will be disabled.
+	 */
+	bool powersave;
+};
+
+/** \name State Reading/Writing (Physical Group Orientated)
+ * @{
+ */
+
+/**
+ *  \brief Retrieves the PORT module group instance from a given GPIO pin number.
+ *
+ *  Retrieves the PORT module group instance associated with a given logical
+ *  GPIO pin number.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to convert
+ *
+ *  \return Base address of the associated PORT module.
+ */
+static inline PortGroup* port_get_group_from_gpio_pin(
+		const uint8_t gpio_pin)
+{
+	return system_pinmux_get_group_from_gpio_pin(gpio_pin);
+}
+
+/**
+ *  \brief Retrieves the state of a group of port pins that are configured as inputs.
+ *
+ *  Reads the current logic level of a port module's pins and returns the
+ *  current levels as a bitmask.
+ *
+ *  \param[in] port  Base of the PORT module to read from
+ *  \param[in] mask  Mask of the port pin(s) to read
+ *
+ *  \return Status of the port pin(s) input buffers.
+ */
+static inline uint32_t port_group_get_input_level(
+		const PortGroup *const port,
+		const uint32_t mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	return (port->IN.reg & mask);
+}
+
+/**
+ *  \brief Retrieves the state of a group of port pins that are configured as outputs.
+ *
+ *  Reads the current logical output level of a port module's pins and returns
+ *  the current levels as a bitmask.
+ *
+ *  \param[in] port  Base of the PORT module to read from
+ *  \param[in] mask  Mask of the port pin(s) to read
+ *
+ *  \return Status of the port pin(s) output buffers.
+ */
+static inline uint32_t port_group_get_output_level(
+		const PortGroup *const port,
+		const uint32_t mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	return (port->OUT.reg & mask);
+}
+
+/**
+ *  \brief Sets the state of a group of port pins that are configured as outputs.
+ *
+ *  Sets the current output level of a port module's pins to a given logic
+ *  level.
+ *
+ *  \param[out] port        Base of the PORT module to write to
+ *  \param[in]  mask        Mask of the port pin(s) to change
+ *  \param[in]  level_mask  Mask of the port level(s) to set
+ */
+static inline void port_group_set_output_level(
+		PortGroup *const port,
+		const uint32_t mask,
+		const uint32_t level_mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	port->OUTSET.reg = (mask &  level_mask);
+	port->OUTCLR.reg = (mask & ~level_mask);
+}
+
+/**
+ *  \brief Toggles the state of a group of port pins that are configured as an outputs.
+ *
+ *  Toggles the current output levels of a port module's pins.
+ *
+ *  \param[out] port  Base of the PORT module to write to
+ *  \param[in]  mask  Mask of the port pin(s) to toggle
+ */
+static inline void port_group_toggle_output_level(
+		PortGroup *const port,
+		const uint32_t mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	port->OUTTGL.reg = mask;
+}
+
+/** @} */
+
+/** \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ *  \brief Initializes a Port pin/group configuration structure to defaults.
+ *
+ *  Initializes a given Port pin/group configuration structure to a set of
+ *  known default values. This function should be called on all new
+ *  instances of these configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is as follows:
+ *   \li Input mode with internal pull-up enabled
+ *
+ *  \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void port_get_config_defaults(
+		struct port_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->direction  = PORT_PIN_DIR_INPUT;
+	config->input_pull = PORT_PIN_PULL_UP;
+	config->powersave  = false;
+}
+
+void port_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct port_config *const config);
+
+void port_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct port_config *const config);
+
+/** @} */
+
+/** \name State Reading/Writing (Logical Pin Orientated)
+ * @{
+ */
+
+/**
+ *  \brief Retrieves the state of a port pin that is configured as an input.
+ *
+ *  Reads the current logic level of a port pin and returns the current
+ *  level as a Boolean value.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to read
+ *
+ *  \return Status of the port pin's input buffer.
+ */
+static inline bool port_pin_get_input_level(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	return (port_base->IN.reg & pin_mask);
+}
+
+/**
+ *  \brief Retrieves the state of a port pin that is configured as an output.
+ *
+ *  Reads the current logical output level of a port pin and returns the current
+ *  level as a Boolean value.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to read
+ *
+ *  \return Status of the port pin's output buffer.
+ */
+static inline bool port_pin_get_output_level(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	return (port_base->OUT.reg & pin_mask);
+}
+
+/**
+ *  \brief Sets the state of a port pin that is configured as an output.
+ *
+ *  Sets the current output level of a port pin to a given logic level.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to write to
+ *  \param[in] level     Logical level to set the given pin to
+ */
+static inline void port_pin_set_output_level(
+		const uint8_t gpio_pin,
+		const bool level)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	/* Set the pin to high or low atomically based on the requested level */
+	if (level) {
+		port_base->OUTSET.reg = pin_mask;
+	} else {
+		port_base->OUTCLR.reg = pin_mask;
+	}
+}
+
+/**
+ *  \brief Toggles the state of a port pin that is configured as an output.
+ *
+ *  Toggles the current output level of a port pin.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to toggle
+ */
+static inline void port_pin_toggle_output_level(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	/* Toggle pin output level */
+	port_base->OUTTGL.reg = pin_mask;
+}
+
+/** @} */
+
+#ifdef FEATURE_PORT_INPUT_EVENT
+
+/** \name Port Input Event
+ * @{
+ */
+
+/**
+ *  \brief Enable the port event input.
+ *
+ *  Enable the port event input with the given pin and event.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin
+ *  \param[in] n  Port input event
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
+ * \retval STATUS_OK               Successfully
+ */
+static inline enum status_code port_enable_input_event(
+		const uint8_t gpio_pin,
+		const enum port_input_event n)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	switch (n) {
+		case PORT_INPUT_EVENT_0:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+			break;
+		case PORT_INPUT_EVENT_1:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+			break;
+		case PORT_INPUT_EVENT_2:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+			break;
+		case PORT_INPUT_EVENT_3:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/**
+ *  \brief Disable the port event input.
+ *
+ *  Disable the port event input with the given pin and event.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin
+ *  \param[in] gpio_pin  Port input event
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
+ * \retval STATUS_OK               Successfully
+ */
+static inline enum status_code port_disable_input_event(
+		const uint8_t gpio_pin,
+		const enum port_input_event n)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	switch (n) {
+		case PORT_INPUT_EVENT_0:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+			break;
+		case PORT_INPUT_EVENT_1:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+			break;
+		case PORT_INPUT_EVENT_2:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+			break;
+		case PORT_INPUT_EVENT_3:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Retrieve the default configuration for port input event.
+ *
+ * Fills a configuration structure with the default configuration for port input event:
+ *   - Event output to pin
+ *   - Event action to be executed on PIN 0
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void port_input_event_get_config_defaults(
+		struct port_input_event_config *const config)
+{
+	Assert(config);
+	config->action   = PORT_INPUT_EVENT_ACTION_OUT;
+	config->gpio_pin = 0;
+}
+
+/**
+ * \brief Configure port input event.
+ *
+ * Configures port input event with the given configuration settings.
+ *
+ * \param[in] config  Port input even configuration structure containing the new config
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
+ * \retval STATUS_OK               Successfully
+ */
+
+static inline enum status_code port_input_event_set_config(
+		const enum port_input_event n,
+		struct port_input_event_config *const config)
+{
+	Assert(config);
+	PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin);
+	uint8_t pin_index = config->gpio_pin % 32;
+	struct port_config pin_conf;
+
+	port_get_config_defaults(&pin_conf);
+	/* Configure the GPIO pin as outputs*/
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(config->gpio_pin, &pin_conf);
+
+	switch (n) {
+		case PORT_INPUT_EVENT_0:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action)
+									| PORT_EVCTRL_PID0(pin_index);
+			break;
+		case PORT_INPUT_EVENT_1:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT1(config->action)
+						   		   | PORT_EVCTRL_PID1(pin_index);
+			break;
+		case PORT_INPUT_EVENT_2:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT2(config->action)
+						   		   | PORT_EVCTRL_PID2(pin_index);
+			break;
+		case PORT_INPUT_EVENT_3:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT3(config->action)
+						   		   | PORT_EVCTRL_PID3(pin_index);
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/** @} */
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_port_extra Extra Information for PORT Driver
+ *
+ * \section asfdoc_sam0_port_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>GPIO</td>
+ *		<td>General Purpose Input/Output</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MUX</td>
+ *		<td>Multiplexer</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_port_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_port_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_port_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Added input event feature</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_port_exqsg Examples for PORT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_port_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_port_basic_use_case
+ *
+ * \page asfdoc_sam0_port_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113E</td>
+ *		<td>12/2015</td>
+ *		<td>Added input event feature.
+ *			Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif

asf/sam0/drivers/port/quick_start/qs_port_basic.h

@@ -0,0 +1,108 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver Quick Start
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_port_basic_use_case Quick Start Guide for PORT - Basic
+ *
+ * In this use case, the PORT module is configured for:
+ *  \li One pin in input mode, with pull-up enabled
+ *  \li One pin in output mode
+ *
+ * This use case sets up the PORT to read the current state of a GPIO pin set as
+ * an input, and mirrors the opposite logical state on a pin configured as an
+ * output.
+ *
+ * \section asfdoc_sam0_port_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_code Code
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_port_basic.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_port_basic.c setup_init
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_flow Workflow
+ * -# Create a PORT module pin configuration struct, which can be filled out to
+ *    adjust the configuration of a single port pin.
+ *    \snippet qs_port_basic.c setup_1
+ * -# Initialize the pin configuration struct with the module's default values.
+ *    \snippet qs_port_basic.c setup_2
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Adjust the configuration struct to request an input pin.
+ *    \snippet qs_port_basic.c setup_3
+ * -# Configure push button pin with the initialized pin configuration struct, to enable
+ *    the input sampler on the pin.
+ *    \snippet qs_port_basic.c setup_4
+ * -# Adjust the configuration struct to request an output pin.
+ *    \snippet qs_port_basic.c setup_5
+ *    \note The existing configuration struct may be re-used, as long as any
+ *          values that have been altered from the default settings are taken
+ *          into account by the user application.
+ *
+ * -# Configure LED pin with the initialized pin configuration struct, to enable
+ *    the output driver on the pin.
+ *    \snippet qs_port_basic.c setup_6
+ *
+ * \section asfdoc_sam0_port_basic_use_case_use_main Use Case
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_port_basic.c main
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_flow Workflow
+ * -# Read in the current input sampler state of push button pin, which has been
+ *    configured as an input in the use-case setup code.
+ *    \snippet qs_port_basic.c main_1
+ * -# Write the inverted pin level state to LED pin, which has been configured as
+ *    an output in the use-case setup code.
+ *    \snippet qs_port_basic.c main_2
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */

asf/sam0/drivers/sercom/sercom.c

@@ -0,0 +1,296 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "sercom.h"
+
+#define SHIFT 32
+#define BAUD_INT_MAX   8192
+#define BAUD_FP_MAX     8
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal Configuration structure to save current gclk status.
+ */
+struct _sercom_conf {
+	/* Status of gclk generator initialization */
+	bool generator_is_set;
+	/* Sercom gclk generator used */
+	enum gclk_generator generator_source;
+};
+
+static struct _sercom_conf _sercom_config;
+
+
+/**
+ * \internal Calculate 64 bit division, ref can be found in
+ * http://en.wikipedia.org/wiki/Division_algorithm#Long_division
+ */
+static uint64_t long_division(uint64_t n, uint64_t d)
+{
+	int32_t i;
+	uint64_t q = 0, r = 0, bit_shift;
+	for (i = 63; i >= 0; i--) {
+		bit_shift = (uint64_t)1 << i;
+
+		r = r << 1;
+
+		if (n & bit_shift) {
+			r |= 0x01;
+		}
+
+		if (r >= d) {
+			r = r - d;
+			q |= bit_shift;
+		}
+	}
+
+	return q;
+}
+
+/**
+ * \internal Calculate synchronous baudrate value (SPI/UART)
+ */
+enum status_code _sercom_get_sync_baud_val(
+		const uint32_t baudrate,
+		const uint32_t external_clock,
+		uint16_t *const baudvalue)
+{
+	/* Baud value variable */
+	uint16_t baud_calculated = 0;
+	uint32_t clock_value = external_clock;
+
+
+	/* Check if baudrate is outside of valid range */
+	if (baudrate > (external_clock / 2)) {
+		/* Return with error code */
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	}
+
+	/* Calculate BAUD value from clock frequency and baudrate */
+	clock_value = external_clock / 2;
+	while (clock_value >= baudrate) {
+		clock_value = clock_value - baudrate;
+		baud_calculated++;
+	}
+	baud_calculated = baud_calculated - 1;
+
+	/* Check if BAUD value is more than 255, which is maximum
+	 * for synchronous mode */
+	if (baud_calculated > 0xFF) {
+		/* Return with an error code */
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	} else {
+		*baudvalue = baud_calculated;
+		return STATUS_OK;
+	}
+}
+
+/**
+ * \internal Calculate asynchronous baudrate value (UART)
+*/
+enum status_code _sercom_get_async_baud_val(
+		const uint32_t baudrate,
+		const uint32_t peripheral_clock,
+		uint16_t *const baudval,
+		enum sercom_asynchronous_operation_mode mode,
+		enum sercom_asynchronous_sample_num sample_num)
+{
+	/* Temporary variables  */
+	uint64_t ratio = 0;
+	uint64_t scale = 0;
+	uint64_t baud_calculated = 0;
+	uint8_t baud_fp;
+	uint32_t baud_int = 0;
+	uint64_t temp1, temp2;
+
+	/* Check if the baudrate is outside of valid range */
+	if ((baudrate * sample_num) > peripheral_clock) {
+		/* Return with error code */
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	}
+
+	if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) {
+		/* Calculate the BAUD value */
+		temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
+		ratio = long_division(temp1, peripheral_clock);
+		scale = ((uint64_t)1 << SHIFT) - ratio;
+		baud_calculated = (65536 * scale) >> SHIFT;
+	} else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) {
+		for(baud_fp = 0; baud_fp < BAUD_FP_MAX; baud_fp++) {
+			temp1 = BAUD_FP_MAX * (uint64_t)peripheral_clock;
+			temp2 = ((uint64_t)baudrate * sample_num);
+			baud_int = long_division(temp1, temp2);
+			baud_int -= baud_fp;
+			baud_int = baud_int / BAUD_FP_MAX;
+			if(baud_int < BAUD_INT_MAX) {
+				break;
+			}
+		}
+		if(baud_fp == BAUD_FP_MAX) {
+			return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+		}
+		baud_calculated = baud_int | (baud_fp << 13);
+	}
+
+	*baudval = baud_calculated;
+	return STATUS_OK;
+}
+#endif
+
+/**
+ * \brief Set GCLK channel to generator.
+ *
+ * This will set the appropriate GCLK channel to the requested GCLK generator.
+ * This will set the generator for all SERCOM instances, and the user will thus
+ * only be able to set the same generator that has previously been set, if any.
+ *
+ * After the generator has been set the first time, the generator can be changed
+ * using the \c force_change flag.
+ *
+ * \param[in]  generator_source The generator to use for SERCOM.
+ * \param[in]  force_change     Force change the generator.
+ *
+ * \return Status code indicating the GCLK generator change operation.
+ * \retval STATUS_OK                       If the generator update request was
+ *                                         successful.
+ * \retval STATUS_ERR_ALREADY_INITIALIZED  If a generator was already configured
+ *                                         and the new configuration was not
+ *                                         forced.
+ */
+enum status_code sercom_set_gclk_generator(
+		const enum gclk_generator generator_source,
+		const bool force_change)
+{
+	/* Check if valid option */
+	if (!_sercom_config.generator_is_set || force_change) {
+		/* Create and fill a GCLK configuration structure for the new config */
+		struct system_gclk_chan_config gclk_chan_conf;
+		system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+		gclk_chan_conf.source_generator = generator_source;
+		system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
+		system_gclk_chan_enable(SERCOM_GCLK_ID);
+
+		/* Save config */
+		_sercom_config.generator_source = generator_source;
+		_sercom_config.generator_is_set = true;
+
+		return STATUS_OK;
+	} else if (generator_source == _sercom_config.generator_source) {
+		/* Return status OK if same config */
+		return STATUS_OK;
+	}
+
+	/* Return invalid config to already initialized GCLK */
+	return STATUS_ERR_ALREADY_INITIALIZED;
+}
+
+/** \internal
+ * Creates a switch statement case entry to convert a SERCOM instance and pad
+ * index to the default SERCOM pad MUX setting.
+ */
+#define _SERCOM_PAD_DEFAULTS_CASE(n, pad) \
+		case (uintptr_t)SERCOM##n: \
+			switch (pad) { \
+				case 0: \
+					return SERCOM##n##_PAD0_DEFAULT; \
+				case 1: \
+					return SERCOM##n##_PAD1_DEFAULT; \
+				case 2: \
+					return SERCOM##n##_PAD2_DEFAULT; \
+				case 3: \
+					return SERCOM##n##_PAD3_DEFAULT; \
+			} \
+			break;
+
+/**
+ * \internal Gets the default PAD pinout for a given SERCOM.
+ *
+ * Returns the pinmux settings for the given SERCOM and pad. This is used
+ * for default configuration of pins.
+ *
+ * \param[in]  sercom_module   Pointer to the SERCOM module
+ * \param[in]  pad             PAD to get default pinout for
+ *
+ * \returns The default pinmux for the given SERCOM instance and PAD
+ *
+ */
+uint32_t _sercom_get_default_pad(
+		Sercom *const sercom_module,
+		const uint8_t pad)
+{
+	switch ((uintptr_t)sercom_module) {
+		/* Auto-generate a lookup table for the default SERCOM pad defaults */
+		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+	}
+
+	Assert(false);
+	return 0;
+}
+
+/**
+ * \internal
+ * Find index of given instance.
+ *
+ * \param[in] sercom_instance  Instance pointer.
+ *
+ * \return Index of given instance.
+ */
+uint8_t _sercom_get_sercom_inst_index(
+		Sercom *const sercom_instance)
+{
+	/* Save all available SERCOM instances for compare */
+	Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
+
+	/* Find index for sercom instance */
+	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+		if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
+			return i;
+		}
+	}
+
+	/* Invalid data given */
+	Assert(false);
+	return 0;
+}

asf/sam0/drivers/sercom/sercom.h

@@ -0,0 +1,118 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SERCOM_H_INCLUDED
+#define SERCOM_H_INCLUDED
+
+#include <compiler.h>
+#include <system.h>
+#include <clock.h>
+#include <system_interrupt.h>
+#include "sercom_pinout.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* SERCOM modules should share  same slow GCLK channel ID */
+#define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW
+
+#if (0x1ff >= REV_SERCOM)
+#  define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1
+#elif (0x400 >= REV_SERCOM)
+#  define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2
+#else
+#  error "Unknown SYNCBUSY scheme for this SERCOM revision"
+#endif
+
+/**
+ * \brief sercom asynchronous operation mode
+ *
+ * Select sercom asynchronous operation mode
+ */
+enum sercom_asynchronous_operation_mode {
+	SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0,
+	SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL,
+};
+
+/**
+ * \brief sercom asynchronous samples per bit
+ *
+ * Select number of samples per bit
+ */
+enum sercom_asynchronous_sample_num {
+	SERCOM_ASYNC_SAMPLE_NUM_3 = 3,
+	SERCOM_ASYNC_SAMPLE_NUM_8 = 8,
+	SERCOM_ASYNC_SAMPLE_NUM_16 = 16,
+};
+
+enum status_code sercom_set_gclk_generator(
+		const enum gclk_generator generator_source,
+		const bool force_change);
+
+enum status_code _sercom_get_sync_baud_val(
+		const uint32_t baudrate,
+		const uint32_t external_clock,
+		uint16_t *const baudval);
+
+enum status_code _sercom_get_async_baud_val(
+		const uint32_t baudrate,
+		const uint32_t peripheral_clock,
+		uint16_t *const baudval,
+		enum sercom_asynchronous_operation_mode mode,
+		enum sercom_asynchronous_sample_num sample_num);
+
+uint32_t _sercom_get_default_pad(
+		Sercom *const sercom_module,
+		const uint8_t pad);
+
+uint8_t _sercom_get_sercom_inst_index(
+		Sercom *const sercom_instance);
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SERCOM_H_INCLUDED

asf/sam0/drivers/sercom/sercom_interrupt.c

@@ -0,0 +1,141 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "sercom_interrupt.h"
+
+void *_sercom_instances[SERCOM_INST_NUM];
+
+/** Save status of initialized handlers */
+static bool _handler_table_initialized = false;
+
+/** Void pointers for saving device instance structures */
+static void (*_sercom_interrupt_handlers[SERCOM_INST_NUM])(const uint8_t instance);
+
+/**
+ * \internal
+ * Default interrupt handler.
+ *
+ * \param[in] instance SERCOM instance used.
+ */
+static void _sercom_default_handler(
+		const uint8_t instance)
+{
+	Assert(false);
+}
+
+/**
+ * \internal
+ * Saves the given callback handler.
+ *
+ * \param[in]  instance           Instance index.
+ * \param[in]  interrupt_handler  Pointer to instance callback handler.
+ */
+void _sercom_set_handler(
+		const uint8_t instance,
+		const sercom_handler_t interrupt_handler)
+{
+	/* Initialize handlers with default handler and device instances with 0 */
+	if (_handler_table_initialized == false) {
+		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+			_sercom_interrupt_handlers[i] = &_sercom_default_handler;
+			_sercom_instances[i] = NULL;
+		}
+
+		_handler_table_initialized = true;
+	}
+
+	/* Save interrupt handler */
+	_sercom_interrupt_handlers[instance] = interrupt_handler;
+}
+
+
+/** \internal
+ * Converts a given SERCOM index to its interrupt vector index.
+ */
+#define _SERCOM_INTERRUPT_VECT_NUM(n, unused) \
+		SYSTEM_INTERRUPT_MODULE_SERCOM##n,
+
+/** \internal
+ * Generates a SERCOM interrupt handler function for a given SERCOM index.
+ */
+#define _SERCOM_INTERRUPT_HANDLER(n, unused) \
+		void SERCOM##n##_Handler(void) \
+		{ \
+			_sercom_interrupt_handlers[n](n); \
+		}
+
+/**
+ * \internal
+ * Returns the system interrupt vector.
+ *
+ * \param[in]  sercom_instance  Instance pointer
+ *
+ * \return Enum of system interrupt vector
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM0
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM1
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM2
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM3
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM4
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM5
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM6
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM7
+ */
+enum system_interrupt_vector _sercom_get_interrupt_vector(
+		Sercom *const sercom_instance)
+{
+	const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
+		{
+			MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
+		};
+
+	/* Retrieve the index of the SERCOM being requested */
+	uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
+
+	/* Get the vector number from the lookup table for the requested SERCOM */
+	return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
+}
+
+/** Auto-generate a set of interrupt handlers for each SERCOM in the device */
+MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~)

asf/sam0/drivers/sercom/sercom_interrupt.h

@@ -1,9 +1,9 @@
 /**
  * \file
  *
- * \brief Low-level initialization functions called upon chip startup.
+ * \brief SAM Serial Peripheral Interface Driver
  *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
@@ -40,39 +40,33 @@
  * \asf_license_stop
  *
  */
-
-#include "samd21.h"
-
-/**
- * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
- *  the source for the main clock at chip startup.
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
  */
-#define __SYSTEM_CLOCK    (1000000)
+#ifndef SERCOM_INTERRUPT_H_INCLUDED
+#define SERCOM_INTERRUPT_H_INCLUDED
 
-uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+#include "sercom.h"
+#include <system_interrupt.h>
 
-/**
- * Initialize the system
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-void SystemInit(void)
-{
-	// Keep the default device state after reset
-	SystemCoreClock = __SYSTEM_CLOCK;
-	return;
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Look-up table for device instances */
+extern void *_sercom_instances[SERCOM_INST_NUM];
+
+typedef void (*sercom_handler_t)(uint8_t instance);
+
+enum system_interrupt_vector _sercom_get_interrupt_vector(
+		Sercom *const sercom_instance);
+
+void _sercom_set_handler(
+		const uint8_t instance,
+		const sercom_handler_t interrupt_handler);
+
+#ifdef __cplusplus
 }
+#endif
 
-/**
- * Update SystemCoreClock variable
- *
- * @brief  Updates the SystemCoreClock with current core Clock
- *         retrieved from cpu registers.
- */
-void SystemCoreClockUpdate(void)
-{
-	// Not implemented
-	SystemCoreClock = __SYSTEM_CLOCK;
-	return;
-}
+#endif /* SERCOM_INTERRUPT_H_INCLUDED */

asf/sam0/drivers/sercom/sercom_pinout.h

@@ -0,0 +1,526 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM Module Pinout Definitions
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SERCOM_PINOUT_H_INCLUDED
+#define SERCOM_PINOUT_H_INCLUDED
+
+#include <compiler.h>
+
+#if SAMR21E
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+# if SAM_PART_IS_DEFINED(SAMR21E19A)
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+# else
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA27F_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA28F_SERCOM3_PAD1
+#endif
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+	/* SERCOM4 */
+# if SAM_PART_IS_DEFINED(SAMR21E19A)
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+# else
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PC19F_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB31F_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB30F_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PC18F_SERCOM4_PAD3
+# endif
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB30D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB31D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+
+#elif SAMR21G
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PC19F_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB31F_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB30F_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PC18F_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+
+#elif (SAMD09)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA08D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA09D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA30C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA31C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA24C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA25C_SERCOM1_PAD3
+
+#elif (SAMD10DS) || (SAMD10DM) || (SAMD10DU) || (SAMD11DS) || (SAMD11DM) || (SAMD11DU) 
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA22C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA23C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA16D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA25D_SERCOM2_PAD3
+
+#elif (SAMD10C) || (SAMD11C)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA08D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA09D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA30C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA31C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA24C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA25C_SERCOM1_PAD3
+
+#elif SAM_PART_IS_DEFINED(SAMD21E15L) || SAM_PART_IS_DEFINED(SAMD21E16L)
+
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+#elif (SAML22N)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PB02C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PB21C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PB00C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PB01C_SERCOM3_PAD3
+
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12C_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13C_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14C_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15C_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB30D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB31D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB22D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB23D_SERCOM5_PAD3
+#elif (SAML22J)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PB02C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PB13C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PB00C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PB01C_SERCOM3_PAD3
+#elif (SAML22G)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
+#elif (SAMC20E) || (SAMC21E)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+#elif (SAMC20G) || (SAMC21G)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+  #ifdef ID_SERCOM4
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+  #endif
+
+  #ifdef ID_SERCOM5
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB02D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB03D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB22D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB23D_SERCOM5_PAD3
+  #endif
+
+#elif (SAMC20J) || (SAMC21J)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+  #ifdef ID_SERCOM4
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+  #endif
+
+  #ifdef ID_SERCOM5
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB02D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB03D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB00D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB01D_SERCOM5_PAD3
+  #endif
+
+#elif (SAMDA1)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+  #if (SAMDA1E)
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+  #else
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+  #endif
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+
+#elif (SAML21E) || (SAMR30E)
+
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+  #if !SAM_PART_IS_DEFINED(SAML21E18A) && !SAM_PART_IS_DEFINED(SAMR30E18A)
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+  #endif
+
+#else
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+#if SAM_PART_IS_DEFINED(SAMD21G15L) || SAM_PART_IS_DEFINED(SAMD21G16L)
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+#else
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+#endif
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+  #if !(SAMD20E || SAMD21E)
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+  #endif
+
+#endif
+
+#endif /* SERCOM_PINOUT_H_INCLUDED */

asf/sam0/drivers/sercom/usart/quick_start/qs_usart_basic_use.h

@@ -0,0 +1,116 @@
+/**
+ * \file
+ *
+ * \brief SAM USART Quick Start
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_basic_use_case Quick Start Guide for SERCOM USART - Basic
+ *
+ * This quick start will echo back characters typed into the terminal. In this
+ * use case the USART will be configured with the following settings:
+ * - Asynchronous mode
+ * - 9600 Baudrate
+ * - 8-bits, No Parity and one Stop Bit
+ * - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
+ *
+ * \section asfdoc_sam0_sercom_usart_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_usart_basic_use_case_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_setup_code Code
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_usart_basic_use.c module_inst
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_usart_basic_use.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_usart_basic_use.c setup_init
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_setup_flow Workflow
+ * -# Create a module software instance structure for the USART module to store
+ *    the USART driver state while it is in use.
+ *    \snippet qs_usart_basic_use.c module_inst
+ *    \note This should never go out of scope as long as the module is in use.
+ *          In most cases, this should be global.
+ *
+ * -# Configure the USART module.
+ *  -# Create a USART module configuration struct, which can be filled out to
+ *     adjust the configuration of a physical USART peripheral.
+ *     \snippet qs_usart_basic_use.c setup_config
+ *  -# Initialize the USART configuration struct with the module's default values.
+ *     \snippet qs_usart_basic_use.c setup_config_defaults
+ *     \note This should always be performed before using the configuration
+ *           struct to ensure that all values are initialized to known default
+ *           settings.
+ *
+ *  -# Alter the USART settings to configure the physical pinout, baudrate, and
+ *     other relevant parameters.
+ *     \snippet qs_usart_basic_use.c setup_change_config
+ *  -# Configure the USART module with the desired settings, retrying while the
+ *     driver is busy until the configuration is stressfully set.
+ *     \snippet qs_usart_basic_use.c setup_set_config
+ *  -# Enable the USART module.
+ *     \snippet qs_usart_basic_use.c setup_enable
+ *
+ *
+ * \section asfdoc_sam0_usart_basic_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_usart_basic_use.c main
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_main_flow Workflow
+ * -# Send a string to the USART to show the demo is running, blocking until
+ *    all characters have been sent.
+ *    \snippet qs_usart_basic_use.c main_send_string
+ * -# Enter an infinite loop to continuously echo received values on the USART.
+ *    \snippet qs_usart_basic_use.c main_loop
+ * -# Perform a blocking read of the USART, storing the received character into
+ *    the previously declared temporary variable.
+ *    \snippet qs_usart_basic_use.c main_read
+ * -# Echo the received variable back to the USART via a blocking write.
+ *    \snippet qs_usart_basic_use.c main_write
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */

asf/sam0/drivers/sercom/usart/quick_start_callback/qs_usart_callback.h

@@ -0,0 +1,130 @@
+/**
+ * \file
+ *
+ * \brief SAM USART Quick Start
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_callback_use_case Quick Start Guide for SERCOM USART - Callback
+ *
+ * This quick start will echo back characters typed into the terminal, using
+ * asynchronous TX and RX callbacks from the USART peripheral. In this use case
+ * the USART will be configured with the following settings:
+ * - Asynchronous mode
+ * - 9600 Baudrate
+ * - 8-bits, No Parity and one Stop Bit
+ * - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
+ *
+ * \section asfdoc_sam0_sercom_usart_callback_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_usart_callback_use_case_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_usart_callback_use_case_setup_code Code
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_usart_callback.c module_inst
+ * \snippet qs_usart_callback.c rx_buffer_var
+ *
+ * Copy-paste the following callback function code to your user application:
+ * \snippet qs_usart_callback.c callback_funcs
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_usart_callback.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_usart_callback.c setup_init
+ *
+ * \subsection asfdoc_sam0_usart_callback_use_case_setup_flow Workflow
+ * -# Create a module software instance structure for the USART module to store
+ *    the USART driver state while it is in use.
+ *    \snippet qs_usart_callback.c module_inst
+ *    \note This should never go out of scope as long as the module is in use.
+ *          In most cases, this should be global.
+ *
+ * -# Configure the USART module.
+ *  -# Create a USART module configuration struct, which can be filled out to
+ *     adjust the configuration of a physical USART peripheral.
+ *     \snippet qs_usart_callback.c setup_config
+ *  -# Initialize the USART configuration struct with the module's default values.
+ *     \snippet qs_usart_callback.c setup_config_defaults
+ *     \note This should always be performed before using the configuration
+ *           struct to ensure that all values are initialized to known default
+ *           settings.
+ *
+ *  -# Alter the USART settings to configure the physical pinout, baudrate, and
+ *     other relevant parameters.
+ *     \snippet qs_usart_callback.c setup_change_config
+ *  -# Configure the USART module with the desired settings, retrying while the
+ *     driver is busy until the configuration is stressfully set.
+ *     \snippet qs_usart_callback.c setup_set_config
+ *  -# Enable the USART module.
+ *     \snippet qs_usart_callback.c setup_enable
+ * -# Configure the USART callbacks.
+ *  -# Register the TX and RX callback functions with the driver.
+ *     \snippet qs_usart_callback.c setup_register_callbacks
+ *  -# Enable the TX and RX callbacks so that they will be called by the driver
+ *     when appropriate.
+ *     \snippet qs_usart_callback.c setup_enable_callbacks
+ *
+ * \section asfdoc_sam0_usart_callback_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_usart_callback_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_usart_callback.c main
+ *
+ * \subsection asfdoc_sam0_usart_callback_use_case_main_flow Workflow
+ * -# Enable global interrupts, so that the callbacks can be fired.
+ *    \snippet qs_usart_callback.c enable_global_interrupts
+ * -# Send a string to the USART to show the demo is running, blocking until
+ *    all characters have been sent.
+ *    \snippet qs_usart_callback.c main_send_string
+ * -# Enter an infinite loop to continuously echo received values on the USART.
+ *    \snippet qs_usart_callback.c main_loop
+ * -# Perform an asynchronous read of the USART, which will fire the registered
+ *    callback when characters are received.
+ *    \snippet qs_usart_callback.c main_read
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <asf.h>
+#include <conf_clocks.h>
+

asf/sam0/drivers/sercom/usart/quick_start_dma/qs_usart_dma_use.h

@@ -0,0 +1,217 @@
+/**
+ * \file
+ *
+ * \brief SAM Quick Start Guide for Using Usart driver with DMA
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_dma_use_case Quick Start Guide for Using DMA with SERCOM USART
+ *
+ * The supported board list:
+ *    - SAM D21 Xplained Pro
+ *    - SAM R21 Xplained Pro
+ *    - SAM D11 Xplained Pro
+ *    - SAM DA1 Xplained Pro
+ *    - SAM L21 Xplained Pro
+ *    - SAM L22 Xplained Pro
+ *    - SAM C21 Xplained Pro
+ *
+ * This quick start will receive eight bytes of data from the PC terminal and transmit back the string
+ * to the terminal through DMA. In this use case the USART will be configured with the following
+ * settings:
+ * - Asynchronous mode
+ * - 9600 Baudrate
+ * - 8-bits, No Parity and one Stop Bit
+ * - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
+ *
+ * \section asfdoc_sam0_sercom_usart_dma_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_usart_dma_use_case_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_setup_code Code
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_usart_dma_use.c module_inst
+ * \snippet qs_usart_dma_use.c dma_resource
+ * \snippet qs_usart_dma_use.c usart_buffer
+ * \snippet qs_usart_dma_use.c transfer_descriptor
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_usart_dma_use.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_usart_dma_use.c setup_init
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_setup_flow Workflow
+ *
+ * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_inst Create variables
+ * -# Create a module software instance structure for the USART module to store
+ *    the USART driver state while it is in use.
+ *    \snippet qs_usart_dma_use.c module_inst
+ *    \note This should never go out of scope as long as the module is in use.
+ *          In most cases, this should be global.
+ *
+ * -# Create module software instance structures for DMA resources to store
+ *    the DMA resource state while it is in use.
+ *    \snippet qs_usart_dma_use.c dma_resource
+ *    \note This should never go out of scope as long as the module is in use.
+ *          In most cases, this should be global.
+ *
+ * -# Create a buffer to store the data to be transferred /received.
+ *    \snippet qs_usart_dma_use.c usart_buffer
+ * -# Create DMA transfer descriptors for RX/TX.
+ *    \snippet qs_usart_dma_use.c transfer_descriptor
+ *
+ * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_usart Configure the USART
+ * -# Create a USART module configuration struct, which can be filled out to
+ *    adjust the configuration of a physical USART peripheral.
+ *    \snippet qs_usart_dma_use.c setup_config
+ * -# Initialize the USART configuration struct with the module's default values.
+ *    \snippet qs_usart_dma_use.c setup_config_defaults
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Alter the USART settings to configure the physical pinout, baudrate, and
+ *    other relevant parameters.
+ *    \snippet qs_usart_dma_use.c setup_change_config
+ * -# Configure the USART module with the desired settings, retrying while the
+ *    driver is busy until the configuration is stressfully set.
+ *    \snippet qs_usart_dma_use.c setup_set_config
+ * -# Enable the USART module.
+ *    \snippet qs_usart_dma_use.c setup_enable
+ *
+ * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_dma Configure DMA
+ * -# Create a callback function of receiver done.
+ *    \snippet qs_usart_dma_use.c transfer_done_rx
+ *
+ * -# Create a callback function of transmission done.
+ *    \snippet qs_usart_dma_use.c transfer_done_tx
+ *
+ * -# Create a DMA resource configuration structure, which can be filled out to
+ *    adjust the configuration of a single DMA transfer.
+ *    \snippet qs_usart_dma_use.c setup_rx_1
+ *
+ * -# Initialize the DMA resource configuration struct with the module's
+ *    default values.
+ *    \snippet qs_usart_dma_use.c setup_rx_2
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set extra configurations for the DMA resource. It is using peripheral
+ *    trigger. SERCOM TX empty trigger causes a beat transfer in
+ *    this example.
+ *    \snippet qs_usart_dma_use.c setup_rx_3
+ *
+ * -# Allocate a DMA resource with the configurations.
+ *    \snippet qs_usart_dma_use.c setup_rx_4
+ *
+ * -# Create a DMA transfer descriptor configuration structure, which can be
+ *    filled out to adjust the configuration of a single DMA transfer.
+ *    \snippet qs_usart_dma_use.c setup_rx_5
+ *
+ * -# Initialize the DMA transfer descriptor configuration struct with the module's
+ *    default values.
+ *    \snippet qs_usart_dma_use.c setup_rx_6
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set the specific parameters for a DMA transfer with transfer size, source
+ *    address, and destination address.
+ *    \snippet qs_usart_dma_use.c setup_rx_7
+ *
+ * -# Create the DMA transfer descriptor.
+ *    \snippet qs_usart_dma_use.c setup_rx_8
+ *
+ * -# Create a DMA resource configuration structure for TX, which can be filled
+ *    out to adjust the configuration of a single DMA transfer.
+ *    \snippet qs_usart_dma_use.c setup_tx_1
+ *
+ * -# Initialize the DMA resource configuration struct with the module's
+ *    default values.
+ *    \snippet qs_usart_dma_use.c setup_tx_2
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set extra configurations for the DMA resource. It is using peripheral
+ *    trigger. SERCOM RX Ready trigger causes a beat transfer in
+ *    this example.
+ *    \snippet qs_usart_dma_use.c setup_tx_3
+ *
+ * -# Allocate a DMA resource with the configurations.
+ *    \snippet qs_usart_dma_use.c setup_tx_4
+ *
+ * -# Create a DMA transfer descriptor configuration structure, which can be
+ *    filled out to adjust the configuration of a single DMA transfer.
+ *    \snippet qs_usart_dma_use.c setup_tx_5
+ *
+ * -# Initialize the DMA transfer descriptor configuration struct with the module's
+ *    default values.
+ *    \snippet qs_usart_dma_use.c setup_tx_6
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set the specific parameters for a DMA transfer with transfer size, source
+ *    address, and destination address.
+ *    \snippet qs_usart_dma_use.c setup_tx_7
+ *
+ * -# Create the DMA transfer descriptor.
+ *    \snippet qs_usart_dma_use.c setup_tx_8
+ *
+ * \section asfdoc_sam0_usart_dma_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_usart_dma_use.c main
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_main_flow Workflow
+ * -# Wait for receiving data.
+ *    \snippet qs_usart_dma_use.c main_1
+ *
+ * -# Enter endless loop.
+ *    \snippet qs_usart_dma_use.c endless_loop
+ */

asf/sam0/drivers/sercom/usart/quick_start_lin/qs_lin.h

@@ -0,0 +1,104 @@
+/**
+ * \file
+ *
+ * \brief SAM USART LIN Quick Start
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_lin_use_case Quick Start Guide for SERCOM USART LIN
+ *
+ * The supported board list:
+ *    - SAMC21 Xplained Pro
+ *
+ * This quick start will set up LIN frame format transmission according to your
+ * configuration \c CONF_LIN_NODE_TYPE.
+ * For LIN master, it will send LIN command after startup.
+ * For LIN salve, once received a format from LIN master with ID \c LIN_ID_FIELD_VALUE,
+ * it will reply four data bytes plus a checksum.
+ *
+ * \section asfdoc_sam0_sercom_usart_lin_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_usart_lin_use_case_prereq Prerequisites
+ * When verify data transmission between LIN master and slave, two boards are needed:
+ * one is for LIN master and the other is for LIN slave.
+ * connect LIN master LIN PIN with LIN slave LIN PIN.
+ *
+ * \subsection asfdoc_sam0_usart_lin_use_case_setup_code Code
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_lin.c module_var
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_lin.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_lin.c setup_init
+ *
+ * \subsection asfdoc_sam0_usart_lin_use_case_setup_flow Workflow
+ * -# Create USART CDC and LIN module software instance structure for the USART module to store
+ *    the USART driver state while it is in use.
+ *    \snippet qs_lin.c module_inst
+ * -# Define LIN ID field for header format.
+ *    \snippet qs_lin.c lin_id
+ *    \note The ID \c LIN_ID_FIELD_VALUE is eight bits as [P1,P0,ID5...ID0], when it's 0x64, the
+ * 		data field length is four bytes plus a checksum byte.
+ *
+ * -# Define LIN RX/TX buffer.
+ *    \snippet qs_lin.c lin_buffer
+ *    \note For \c tx_buffer and \c rx_buffer, the last byte is for checksum.
+ *
+ * -# Configure the USART CDC for output message.
+ *     \snippet qs_lin.c CDC_setup
+ *
+ * -# Configure the USART LIN module.
+ *     \snippet qs_lin.c lin_setup
+ *    \note The LIN frame format can be configured as master or slave, refer to \c CONF_LIN_NODE_TYPE .
+ *
+ * \section asfdoc_sam0_usart_lin_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_usart_lin_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_lin.c main_setup
+ *
+ * \subsection asfdoc_sam0_usart_lin_use_case_main_flow Workflow
+ * -# Set up USART LIN module.
+ *     \snippet qs_lin.c configure_lin
+ * -# For LIN master, sending LIN command. For LIN slaver, start reading data .
+ *     \snippet qs_lin.c lin_master_cmd
+ */

asf/sam0/drivers/sercom/usart/usart.c

@@ -0,0 +1,817 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "usart.h"
+#include <pinmux.h>
+#if USART_CALLBACK_MODE == true
+#  include "usart_interrupt.h"
+#endif
+
+/**
+ * \internal
+ * Set Configuration of the USART module
+ */
+static enum status_code _usart_set_config(
+		struct usart_module *const module,
+		const struct usart_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Index for generic clock */
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+	uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+	/* Cache new register values to minimize the number of register writes */
+	uint32_t ctrla = 0;
+	uint32_t ctrlb = 0;
+#ifdef FEATURE_USART_ISO7816
+	uint32_t ctrlc = 0;
+#endif
+	uint16_t baud  = 0;
+	uint32_t transfer_mode;
+
+	enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+	enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+
+#ifdef FEATURE_USART_OVER_SAMPLE
+	switch (config->sample_rate) {
+		case USART_SAMPLE_RATE_16X_ARITHMETIC:
+			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+			break;
+		case USART_SAMPLE_RATE_8X_ARITHMETIC:
+			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+			break;
+		case USART_SAMPLE_RATE_3X_ARITHMETIC:
+			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
+			break;
+		case USART_SAMPLE_RATE_16X_FRACTIONAL:
+			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+			break;
+		case USART_SAMPLE_RATE_8X_FRACTIONAL:
+			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+			break;
+	}
+#endif
+
+	/* Set data order, internal muxing, and clock polarity */
+	ctrla = (uint32_t)config->data_order |
+		(uint32_t)config->mux_setting |
+	#ifdef FEATURE_USART_OVER_SAMPLE
+		config->sample_adjustment |
+		config->sample_rate |
+	#endif
+	#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+		(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
+	#endif
+		(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
+
+	enum status_code status_code = STATUS_OK;
+
+	transfer_mode = (uint32_t)config->transfer_mode;
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		transfer_mode = config->iso7816_config.protocol_t;
+	}
+#endif
+	/* Get baud value from mode and clock */
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		baud = config->baudrate;
+	} else {
+#endif
+	switch (transfer_mode)
+	{
+		case USART_TRANSFER_SYNCHRONOUSLY:
+			if (!config->use_external_clock) {
+				status_code = _sercom_get_sync_baud_val(config->baudrate,
+						system_gclk_chan_get_hz(gclk_index), &baud);
+			}
+
+			break;
+
+		case USART_TRANSFER_ASYNCHRONOUSLY:
+			if (config->use_external_clock) {
+				status_code =
+						_sercom_get_async_baud_val(config->baudrate,
+							config->ext_clock_freq, &baud, mode, sample_num);
+			} else {
+				status_code =
+						_sercom_get_async_baud_val(config->baudrate,
+							system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num);
+			}
+
+			break;
+	}
+
+	/* Check if calculating the baudrate failed */
+	if (status_code != STATUS_OK) {
+		/* Abort */
+		return status_code;
+	}
+#ifdef FEATURE_USART_ISO7816
+	}
+#endif
+
+#ifdef FEATURE_USART_IRDA
+	if(config->encoding_format_enable) {
+		usart_hw->RXPL.reg = config->receive_pulse_length;
+	}
+#endif
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/*Set baud val */
+	usart_hw->BAUD.reg = baud;
+
+	/* Set sample mode */
+	ctrla |= transfer_mode;
+
+	if (config->use_external_clock == false) {
+		ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
+	}
+	else {
+		ctrla |= SERCOM_USART_CTRLA_MODE(0x0);
+	}
+
+	/* Set stopbits and enable transceivers */
+	ctrlb =  
+		#ifdef FEATURE_USART_IRDA
+			(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
+		#endif
+		#ifdef FEATURE_USART_START_FRAME_DECTION
+			(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
+		#endif
+		#ifdef FEATURE_USART_COLLISION_DECTION
+			(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
+		#endif
+			(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
+			(config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
+
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		ctrla |= SERCOM_USART_CTRLA_FORM(0x07);
+		if (config->iso7816_config.enable_inverse) {
+			ctrla |= SERCOM_USART_CTRLA_TXINV | SERCOM_USART_CTRLA_RXINV;
+		}
+		ctrlb |=  USART_CHARACTER_SIZE_8BIT;
+		
+		switch(config->iso7816_config.protocol_t) {
+			case ISO7816_PROTOCOL_T_0:
+				ctrlb |= (uint32_t)config->stopbits;	
+				ctrlc |= SERCOM_USART_CTRLC_GTIME(config->iso7816_config.guard_time) | \
+						(config->iso7816_config.inhibit_nack) | \
+						(config->iso7816_config.successive_recv_nack) | \
+						SERCOM_USART_CTRLC_MAXITER(config->iso7816_config.max_iterations);
+				break;	
+			case ISO7816_PROTOCOL_T_1:
+				ctrlb |= USART_STOPBITS_1;
+				break;		
+		}
+	} else {
+#endif
+	ctrlb |= (uint32_t)config->character_size;
+	/* Check parity mode bits */
+	if (config->parity != USART_PARITY_NONE) {
+		ctrla |= SERCOM_USART_CTRLA_FORM(1);
+		ctrlb |= config->parity;
+	} else {
+#ifdef FEATURE_USART_LIN_SLAVE
+		if(config->lin_slave_enable) {
+			ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
+		} else {
+			ctrla |= SERCOM_USART_CTRLA_FORM(0);
+		}
+#else
+		ctrla |= SERCOM_USART_CTRLA_FORM(0);
+#endif
+	}
+#ifdef FEATURE_USART_ISO7816
+	}
+#endif
+
+#ifdef FEATURE_USART_LIN_MASTER
+	usart_hw->CTRLC.reg = ((usart_hw->CTRLC.reg) & SERCOM_USART_CTRLC_GTIME_Msk)
+						| config->lin_header_delay
+						| config->lin_break_length;
+
+	if (config->lin_node != LIN_INVALID_MODE) {
+		ctrla &= ~(SERCOM_USART_CTRLA_FORM(0xf));
+		ctrla |= config->lin_node;
+	}
+#endif
+
+	/* Set whether module should run in standby. */
+	if (config->run_in_standby || system_is_debugger_present()) {
+		ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
+	}
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Write configuration to CTRLB */
+	usart_hw->CTRLB.reg = ctrlb;
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Write configuration to CTRLA */
+	usart_hw->CTRLA.reg = ctrla;
+
+#ifdef FEATURE_USART_RS485
+	if ((usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_FORM_Msk) != \
+		SERCOM_USART_CTRLA_FORM(0x07)) {
+		usart_hw->CTRLC.reg &= ~(SERCOM_USART_CTRLC_GTIME(0x7));
+		usart_hw->CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(config->rs485_guard_time);
+	}
+#endif
+
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		_usart_wait_for_sync(module);
+		usart_hw->CTRLC.reg = ctrlc;
+	}
+#endif
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the device
+ *
+ * Initializes the USART device based on the setting specified in the
+ * configuration struct.
+ *
+ * \param[out] module  Pointer to USART device
+ * \param[in]  hw      Pointer to USART hardware instance
+ * \param[in]  config  Pointer to configuration struct
+ *
+ * \return Status of the initialization.
+ *
+ * \retval STATUS_OK                       The initialization was successful
+ * \retval STATUS_BUSY                     The USART module is busy
+ *                                         resetting
+ * \retval STATUS_ERR_DENIED               The USART has not been disabled in
+ *                                         advance of initialization
+ * \retval STATUS_ERR_INVALID_ARG          The configuration struct contains
+ *                                         invalid configuration
+ * \retval STATUS_ERR_ALREADY_INITIALIZED  The SERCOM instance has already been
+ *                                         initialized with different clock
+ *                                         configuration
+ * \retval STATUS_ERR_BAUD_UNAVAILABLE     The BAUD rate given by the
+ *                                         configuration
+ *                                         struct cannot be reached with
+ *                                         the current clock configuration
+ */
+enum status_code usart_init(
+		struct usart_module *const module,
+		Sercom *const hw,
+		const struct usart_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	enum status_code status_code = STATUS_OK;
+
+	/* Assign module pointer to software instance struct */
+	module->hw = hw;
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+	uint32_t pm_index, gclk_index; 
+#if (SAML22) || (SAMC20) 
+	pm_index	= sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+	gclk_index	= sercom_index + SERCOM0_GCLK_ID_CORE;
+#elif (SAML21) || (SAMR30)
+	if (sercom_index == 5) {
+		pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
+		gclk_index   = SERCOM5_GCLK_ID_CORE;
+	} else {
+		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+	}
+#elif (SAMC21)
+	pm_index	= sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+	
+	if (sercom_index == 5){
+		gclk_index	= SERCOM5_GCLK_ID_CORE;
+    } else {
+    	gclk_index	= sercom_index + SERCOM0_GCLK_ID_CORE;
+    }
+#else
+	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+#endif
+
+	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
+		/* The module is busy resetting itself */
+		return STATUS_BUSY;
+	}
+
+	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
+		/* Check the module is enabled */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Turn on module in PM */
+#if (SAML21) || (SAMR30)
+	if (sercom_index == 5) {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
+	} else {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);	
+	}
+#else
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+#endif
+
+	/* Set up the GCLK for the module */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->generator_source;
+	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+	system_gclk_chan_enable(gclk_index);
+	sercom_set_gclk_generator(config->generator_source, false);
+
+	/* Set character size */
+	module->character_size = config->character_size;
+
+	/* Set transmitter and receiver status */
+	module->receiver_enabled = config->receiver_enable;
+	module->transmitter_enabled = config->transmitter_enable;
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	module->lin_slave_enabled = config->lin_slave_enable;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	module->start_frame_detection_enabled = config->start_frame_detection_enable;
+#endif
+#ifdef FEATURE_USART_ISO7816
+	module->iso7816_mode_enabled = config->iso7816_config.enabled;
+#endif
+	/* Set configuration according to the config struct */
+	status_code = _usart_set_config(module, config);
+	if(status_code != STATUS_OK) {
+		return status_code;
+	}
+
+	struct system_pinmux_config pin_conf;
+	system_pinmux_get_config_defaults(&pin_conf);
+	pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+
+	uint32_t pad_pinmuxes[] = {
+			config->pinmux_pad0, config->pinmux_pad1,
+			config->pinmux_pad2, config->pinmux_pad3
+		};
+
+	/* Configure the SERCOM pins according to the user configuration */
+	for (uint8_t pad = 0; pad < 4; pad++) {
+		uint32_t current_pinmux = pad_pinmuxes[pad];
+
+		if (current_pinmux == PINMUX_DEFAULT) {
+			current_pinmux = _sercom_get_default_pad(hw, pad);
+		}
+
+		if (current_pinmux != PINMUX_UNUSED) {
+			pin_conf.mux_position = current_pinmux & 0xFFFF;
+			system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
+		}
+	}
+
+#if USART_CALLBACK_MODE == true
+	/* Initialize parameters */
+	for (uint32_t i = 0; i < USART_CALLBACK_N; i++) {
+		module->callback[i]            = NULL;
+	}
+
+	module->tx_buffer_ptr              = NULL;
+	module->rx_buffer_ptr              = NULL;
+	module->remaining_tx_buffer_length = 0x0000;
+	module->remaining_rx_buffer_length = 0x0000;
+	module->callback_reg_mask          = 0x00;
+	module->callback_enable_mask       = 0x00;
+	module->rx_status                  = STATUS_OK;
+	module->tx_status                  = STATUS_OK;
+
+	/* Set interrupt handler and register USART software module struct in
+	 * look-up table */
+	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+	_sercom_set_handler(instance_index, _usart_interrupt_handler);
+	_sercom_instances[instance_index] = module;
+#endif
+
+	return status_code;
+}
+
+/**
+ * \brief Transmit a character via the USART
+ *
+ * This blocking function will transmit a single character via the
+ * USART.
+ *
+ * \param[in]  module   Pointer to the software instance struct
+ * \param[in]  tx_data  Data to transfer
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK         If the operation was completed
+ * \retval STATUS_BUSY       If the operation was not completed, due to the USART
+ *                           module being busy
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_write_wait(
+		struct usart_module *const module,
+		const uint16_t tx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+#if USART_CALLBACK_MODE == true
+	/* Check if the USART is busy doing asynchronous operation. */
+	if (module->remaining_tx_buffer_length > 0) {
+		return STATUS_BUSY;
+	}
+
+#else
+	/* Check if USART is ready for new data */
+	if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
+		/* Return error code */
+		return STATUS_BUSY;
+	}
+#endif
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Write data to USART module */
+	usart_hw->DATA.reg = tx_data;
+
+	while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
+		/* Wait until data is sent */
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Receive a character via the USART
+ *
+ * This blocking function will receive a character via the USART.
+ *
+ * \param[in]   module   Pointer to the software instance struct
+ * \param[out]  rx_data  Pointer to received data
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK                If the operation was completed
+ * \retval STATUS_BUSY              If the operation was not completed,
+ *                                  due to the USART module being busy
+ * \retval STATUS_ERR_BAD_FORMAT    If the operation was not completed,
+ *                                  due to configuration mismatch between USART
+ *                                  and the sender
+ * \retval STATUS_ERR_BAD_OVERFLOW  If the operation was not completed,
+ *                                  due to the baudrate being too low or the
+ *                                  system frequency being too high
+ * \retval STATUS_ERR_BAD_DATA      If the operation was not completed, due to
+ *                                  data being corrupted
+ * \retval STATUS_ERR_DENIED        If the receiver is not enabled
+ */
+enum status_code usart_read_wait(
+		struct usart_module *const module,
+		uint16_t *const rx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Error variable */
+	uint8_t error_code;
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Check that the receiver is enabled */
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+#if USART_CALLBACK_MODE == true
+	/* Check if the USART is busy doing asynchronous operation. */
+	if (module->remaining_rx_buffer_length > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	/* Check if USART has new data */
+	if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
+		/* Return error code */
+		return STATUS_BUSY;
+	}
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Read out the status code and mask away all but the 3 LSBs*/
+	error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+
+	/* Check if an error has occurred during the receiving */
+	if (error_code) {
+		/* Check which error occurred */
+		if (error_code & SERCOM_USART_STATUS_FERR) {
+			/* Clear flag by writing a 1 to it and
+			 * return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+
+			return STATUS_ERR_BAD_FORMAT;
+		} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+			/* Clear flag by writing a 1 to it and
+			 * return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+
+			return STATUS_ERR_OVERFLOW;
+		} else if (error_code & SERCOM_USART_STATUS_PERR) {
+			/* Clear flag by writing a 1 to it and
+			 * return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+
+			return STATUS_ERR_BAD_DATA;
+		}
+#ifdef FEATURE_USART_LIN_SLAVE
+		else if (error_code & SERCOM_USART_STATUS_ISF) {
+			/* Clear flag by writing 1 to it  and
+			 *  return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+
+			return STATUS_ERR_PROTOCOL;
+		}
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+		else if (error_code & SERCOM_USART_STATUS_COLL) {
+			/* Clear flag by writing 1 to it
+			 *  return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+
+			return STATUS_ERR_PACKET_COLLISION;
+		}
+#endif
+	}
+
+	/* Read data from USART module */
+	*rx_data = usart_hw->DATA.reg;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Transmit a buffer of characters via the USART
+ *
+ * This blocking function will transmit a block of \c length characters
+ * via the USART.
+ *
+ * \note Using this function in combination with the interrupt (\c _job) functions is
+ *       not recommended as it has no functionality to check if there is an
+ *       ongoing interrupt driven operation running or not.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Pointer to data to transmit
+ * \param[in]  length   Number of characters to transmit
+ *
+ * \note If using 9-bit data, the array that *tx_data point to should be defined 
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+          #define TX_LEN 3
+          uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
+          usart_write_buffer_wait(&module, (uint8_t*)tx_buf, TX_LEN);
+    \endcode
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK              If operation was completed
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ *                                arguments
+ * \retval STATUS_ERR_TIMEOUT     If operation was not completed, due to USART
+ *                                module timing out
+ * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
+ */
+enum status_code usart_write_buffer_wait(
+		struct usart_module *const module,
+		const uint8_t *tx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Check if the buffer length is valid */
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	uint16_t tx_pos = 0;
+
+	/* Blocks while buffer is being transferred */
+	while (length--) {
+		/* Wait for the USART to be ready for new data and abort
+		* operation if it doesn't get ready within the timeout*/
+		for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+			if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) {
+				break;
+			} else if (i == USART_TIMEOUT) {
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+
+		/* Data to send is at least 8 bits long */
+		uint16_t data_to_send = tx_data[tx_pos++];
+
+		/* Check if the character size exceeds 8 bit */
+		if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+			data_to_send |= (tx_data[tx_pos++] << 8);
+		}
+
+		/* Send the data through the USART module */
+		usart_write_wait(module, data_to_send);
+	}
+
+	/* Wait until Transmit is complete or timeout */
+	for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+		if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {
+			break;
+		} else if (i == USART_TIMEOUT) {
+			return STATUS_ERR_TIMEOUT;
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Receive a buffer of \c length characters via the USART
+ *
+ * This blocking function will receive a block of \c length characters
+ * via the USART.
+ *
+ * \note Using this function in combination with the interrupt (\c *_job)
+ *       functions is not recommended as it has no functionality to check if
+ *       there is an ongoing interrupt driven operation running or not.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[out] rx_data  Pointer to receive buffer
+ * \param[in]  length   Number of characters to receive
+ *
+ * \note If using 9-bit data, the array that *rx_data point to should be defined 
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+          #define RX_LEN 3
+          uint16_t rx_buf[RX_LEN] = {0x0,};
+          usart_read_buffer_wait(&module, (uint8_t*)rx_buf, RX_LEN);
+    \endcode
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK                If operation was completed
+ * \retval STATUS_ERR_INVALID_ARG   If operation was not completed, due to an
+ *                                  invalid argument being supplied
+ * \retval STATUS_ERR_TIMEOUT       If operation was not completed, due
+ *                                  to USART module timing out
+ * \retval STATUS_ERR_BAD_FORMAT    If the operation was not completed,
+ *                                  due to a configuration mismatch
+ *                                  between USART and the sender
+ * \retval STATUS_ERR_BAD_OVERFLOW  If the operation was not completed,
+ *                                  due to the baudrate being too low or the
+ *                                  system frequency being too high
+ * \retval STATUS_ERR_BAD_DATA      If the operation was not completed, due
+ *                                  to data being corrupted
+ * \retval STATUS_ERR_DENIED        If the receiver is not enabled
+ */
+enum status_code usart_read_buffer_wait(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Check if the buffer length is valid */
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the receiver is enabled */
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	uint16_t rx_pos = 0;
+
+	/* Blocks while buffer is being received */
+	while (length--) {
+		/* Wait for the USART to have new data and abort operation if it
+		 * doesn't get ready within the timeout*/
+		for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+			if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
+				break;
+			} else if (i == USART_TIMEOUT) {
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+
+		enum status_code retval;
+		uint16_t received_data = 0;
+
+		retval = usart_read_wait(module, &received_data);
+
+		if (retval != STATUS_OK) {
+			/* Overflow, abort */
+			return retval;
+		}
+
+		/* Read value will be at least 8-bits long */
+		rx_data[rx_pos++] = received_data;
+
+		/* If 9-bit data, write next received byte to the buffer */
+		if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+			rx_data[rx_pos++] = (received_data >> 8);
+		}
+	}
+
+	return STATUS_OK;
+}

asf/sam0/drivers/sercom/usart/usart_interrupt.c

@@ -0,0 +1,666 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Asynchronous Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "usart_interrupt.h"
+
+/**
+ * \internal
+ * Asynchronous write of a buffer with a given length
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Pointer to data to be transmitted
+ * \param[in]  length   Length of data buffer
+ *
+ */
+enum status_code _usart_write_buffer(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(tx_data);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	system_interrupt_enter_critical_section();
+
+	/* Check if the USART transmitter is busy */
+	if (module->remaining_tx_buffer_length > 0) {
+		system_interrupt_leave_critical_section();
+		return STATUS_BUSY;
+	}
+
+	/* Write parameters to the device instance */
+	module->remaining_tx_buffer_length = length;
+
+	system_interrupt_leave_critical_section();
+
+	module->tx_buffer_ptr              = tx_data;
+	module->tx_status                  = STATUS_BUSY;
+
+	/* Enable the Data Register Empty Interrupt */
+	usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_DRE;
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal
+ * Asynchronous read of a buffer with a given length
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  rx_data  Pointer to data to be received
+ * \param[in]  length   Length of data buffer
+ *
+ */
+enum status_code _usart_read_buffer(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(rx_data);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	system_interrupt_enter_critical_section();
+
+	/* Check if the USART receiver is busy */
+	if (module->remaining_rx_buffer_length > 0) {
+		system_interrupt_leave_critical_section();
+		return STATUS_BUSY;
+	}
+
+	/* Set length for the buffer and the pointer, and let
+	 * the interrupt handler do the rest */
+	module->remaining_rx_buffer_length = length;
+
+	system_interrupt_leave_critical_section();
+
+	module->rx_buffer_ptr              = rx_data;
+	module->rx_status                  = STATUS_BUSY;
+
+	/* Enable the RX Complete Interrupt */
+	usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXC;
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	/* Enable the break character is received Interrupt */
+	if(module->lin_slave_enabled) {
+		usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXBRK;
+	}
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	/* Enable a start condition is detected Interrupt */
+	if(module->start_frame_detection_enabled) {
+		usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXS;
+	}
+#endif
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Registers a callback
+ *
+ * Registers a callback function, which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usart_enable_callback
+ *       in order for the interrupt handler to call it when the conditions for
+ *       the callback type are met.
+ *
+ * \param[in]  module         Pointer to USART software instance struct
+ * \param[in]  callback_func  Pointer to callback function
+ * \param[in]  callback_type  Callback type given by an enum
+ *
+ */
+void usart_register_callback(
+		struct usart_module *const module,
+		usart_callback_t callback_func,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module->callback_reg_mask |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters a callback
+ *
+ * Unregisters a callback function, which is implemented by the user.
+ *
+ * \param[in,out]  module         Pointer to USART software instance struct
+ * \param[in]      callback_type  Callback type given by an enum
+ *
+ */
+void usart_unregister_callback(
+		struct usart_module *const module,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module->callback_reg_mask &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Asynchronous write a single char
+ *
+ * Sets up the driver to write the data given. If registered and enabled,
+ * a callback function will be called when the transmit is completed.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Data to transfer
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK         If operation was completed
+ * \retval STATUS_BUSY       If operation was not completed, due to the
+ *                           USART module being busy
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_write_job(
+		struct usart_module *const module,
+		const uint16_t *tx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(tx_data);
+
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Call internal write buffer function with length 1 */
+	return _usart_write_buffer(module, (uint8_t *)tx_data, 1);
+}
+
+/**
+ * \brief Asynchronous read a single char
+ *
+ * Sets up the driver to read data from the USART module to the data
+ * pointer given. If registered and enabled, a callback will be called
+ * when the receiving is completed.
+ *
+ * \param[in]   module   Pointer to USART software instance struct
+ * \param[out]  rx_data  Pointer to where received data should be put
+ *
+ * \returns Status of the operation.
+ * \retval  STATUS_OK    If operation was completed
+ * \retval  STATUS_BUSY  If operation was not completed
+ */
+enum status_code usart_read_job(
+		struct usart_module *const module,
+		uint16_t *const rx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(rx_data);
+
+	/* Call internal read buffer function with length 1 */
+	return _usart_read_buffer(module, (uint8_t *)rx_data, 1);
+}
+
+/**
+ * \brief Asynchronous buffer write
+ *
+ * Sets up the driver to write a given buffer over the USART. If registered and
+ * enabled, a callback function will be called.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Pointer do data buffer to transmit
+ * \param[in]  length   Length of the data to transmit
+ *
+ * \note If using 9-bit data, the array that *tx_data point to should be defined 
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+          #define TX_LEN 3
+          uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
+          usart_write_buffer_job(&module, (uint8_t*)tx_buf, TX_LEN);
+    \endcode
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK              If operation was completed successfully.
+ * \retval STATUS_BUSY            If operation was not completed, due to the
+ *                                USART module being busy
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ *                                arguments
+ * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
+ */
+enum status_code usart_write_buffer_job(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(tx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Issue internal asynchronous write */
+	return _usart_write_buffer(module, tx_data, length);
+}
+
+/**
+ * \brief Asynchronous buffer read
+ *
+ * Sets up the driver to read from the USART to a given buffer. If registered
+ * and enabled, a callback function will be called.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[out] rx_data  Pointer to data buffer to receive
+ * \param[in]  length   Data buffer length
+ *
+ * \note If using 9-bit data, the array that *rx_data point to should be defined
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+           #define RX_LEN 3
+           uint16_t rx_buf[RX_LEN] = {0x0,};
+           usart_read_buffer_job(&module, (uint8_t*)rx_buf, RX_LEN);
+    \endcode
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK              If operation was completed
+ * \retval STATUS_BUSY            If operation was not completed, due to the
+ *                                USART module being busy
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ *                                arguments
+ * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
+ */
+enum status_code usart_read_buffer_job(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(rx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the receiver is enabled */
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Issue internal asynchronous read */
+	return _usart_read_buffer(module, rx_data, length);
+}
+
+/**
+ * \brief Cancels ongoing read/write operation
+ *
+ * Cancels the ongoing read/write operation modifying parameters in the
+ * USART software struct.
+ *
+ * \param[in]  module            Pointer to USART software instance struct
+ * \param[in]  transceiver_type  Transfer type to cancel
+ */
+void usart_abort_job(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	switch(transceiver_type) {
+		case USART_TRANSCEIVER_RX:
+			/* Clear the interrupt flag in order to prevent the receive
+			 * complete callback to fire */
+			usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+
+			/* Clear the software reception buffer */
+			module->remaining_rx_buffer_length = 0;
+
+			break;
+
+		case USART_TRANSCEIVER_TX:
+			/* Clear the interrupt flag in order to prevent the receive
+			 * complete callback to fire */
+			usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+
+			/* Clear the software reception buffer */
+			module->remaining_tx_buffer_length = 0;
+
+			break;
+	}
+}
+
+/**
+ * \brief Get status from the ongoing or last asynchronous transfer operation
+ *
+ * Returns the error from a given ongoing or last asynchronous transfer operation.
+ * Either from a read or write transfer.
+ *
+ * \param[in]  module            Pointer to USART software instance struct
+ * \param[in]  transceiver_type  Transfer type to check
+  *
+ * \return Status of the given job.
+ * \retval STATUS_OK               No error occurred during the last transfer
+ * \retval STATUS_BUSY             A transfer is ongoing
+ * \retval STATUS_ERR_BAD_DATA     The last operation was aborted due to a
+ *                                 parity error. The transfer could be affected
+ *                                 by external noise
+ * \retval STATUS_ERR_BAD_FORMAT   The last operation was aborted due to a
+ *                                 frame error
+ * \retval STATUS_ERR_OVERFLOW     The last operation was aborted due to a
+ *                                 buffer overflow
+ * \retval STATUS_ERR_INVALID_ARG  An invalid transceiver enum given
+ */
+enum status_code usart_get_job_status(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Variable for status code */
+	enum status_code status_code;
+
+	switch(transceiver_type) {
+	case USART_TRANSCEIVER_RX:
+			status_code = module->rx_status;
+			break;
+
+	case USART_TRANSCEIVER_TX:
+			status_code = module->tx_status;
+			break;
+
+	default:
+			status_code = STATUS_ERR_INVALID_ARG;
+			break;
+	}
+
+	return status_code;
+}
+
+/**
+ * \internal
+ * Handles interrupts as they occur, and it will run callback functions
+ * which are registered and enabled.
+ *
+ * \param[in]  instance  ID of the SERCOM instance calling the interrupt
+ *                       handler.
+ */
+void _usart_interrupt_handler(
+		uint8_t instance)
+{
+	/* Temporary variables */
+	uint16_t interrupt_status;
+	uint16_t callback_status;
+	uint8_t error_code;
+
+
+	/* Get device instance from the look-up table */
+	struct usart_module *module
+		= (struct usart_module *)_sercom_instances[instance];
+
+	/* Pointer to the hardware module instance */
+	SercomUsart *const usart_hw
+		= &(module->hw->USART);
+
+	/* Wait for the synchronization to complete */
+	_usart_wait_for_sync(module);
+
+	/* Read and mask interrupt flag register */
+	interrupt_status = usart_hw->INTFLAG.reg;
+	interrupt_status &= usart_hw->INTENSET.reg;
+	callback_status = module->callback_reg_mask &
+			module->callback_enable_mask;
+
+	/* Check if a DATA READY interrupt has occurred,
+	 * and if there is more to transfer */
+	if (interrupt_status & SERCOM_USART_INTFLAG_DRE) {
+		if (module->remaining_tx_buffer_length) {
+			/* Write value will be at least 8-bits long */
+			uint16_t data_to_send = *(module->tx_buffer_ptr);
+			/* Increment 8-bit pointer */
+			(module->tx_buffer_ptr)++;
+
+			if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+				data_to_send |= (*(module->tx_buffer_ptr) << 8);
+				/* Increment 8-bit pointer */
+				(module->tx_buffer_ptr)++;
+			}
+			/* Write the data to send */
+			usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK);
+
+			if (--(module->remaining_tx_buffer_length) == 0) {
+				/* Disable the Data Register Empty Interrupt */
+				usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+				/* Enable Transmission Complete interrupt */
+				usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
+
+			}
+		} else {
+			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+		}
+	}
+
+	/* Check if the Transmission Complete interrupt has occurred and
+	 * that the transmit buffer is empty */
+	if (interrupt_status & SERCOM_USART_INTFLAG_TXC) {
+
+		/* Disable TX Complete Interrupt, and set STATUS_OK */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
+		module->tx_status = STATUS_OK;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) {
+			(*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module);
+		}
+	}
+
+	/* Check if the Receive Complete interrupt has occurred, and that
+	 * there's more data to receive */
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
+
+		if (module->remaining_rx_buffer_length) {
+			/* Read out the status code and mask away all but the 4 LSBs*/
+			error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+#if !SAMD20
+			/* CTS status should not be considered as an error */
+			if(error_code & SERCOM_USART_STATUS_CTS) {
+				error_code &= ~SERCOM_USART_STATUS_CTS;
+			}
+#endif
+#ifdef FEATURE_USART_LIN_MASTER
+			/* TXE status should not be considered as an error */
+			if(error_code & SERCOM_USART_STATUS_TXE) {
+				error_code &= ~SERCOM_USART_STATUS_TXE;
+			}
+#endif
+			/* Check if an error has occurred during the receiving */
+			if (error_code) {
+				/* Check which error occurred */
+				if (error_code & SERCOM_USART_STATUS_FERR) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_BAD_FORMAT;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+				} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_OVERFLOW;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+				} else if (error_code & SERCOM_USART_STATUS_PERR) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_BAD_DATA;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+				}
+#ifdef FEATURE_USART_LIN_SLAVE
+				else if (error_code & SERCOM_USART_STATUS_ISF) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_PROTOCOL;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+				}
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+				else if (error_code & SERCOM_USART_STATUS_COLL) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_PACKET_COLLISION;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+				}
+#endif
+
+				/* Run callback if registered and enabled */
+				if (callback_status
+						& (1 << USART_CALLBACK_ERROR)) {
+					(*(module->callback[USART_CALLBACK_ERROR]))(module);
+				}
+
+			} else {
+
+				/* Read current packet from DATA register,
+				 * increment buffer pointer and decrement buffer length */
+				uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK);
+
+				/* Read value will be at least 8-bits long */
+				*(module->rx_buffer_ptr) = received_data;
+				/* Increment 8-bit pointer */
+				module->rx_buffer_ptr += 1;
+
+				if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+					/* 9-bit data, write next received byte to the buffer */
+					*(module->rx_buffer_ptr) = (received_data >> 8);
+					/* Increment 8-bit pointer */
+					module->rx_buffer_ptr += 1;
+				}
+
+				/* Check if the last character have been received */
+				if(--(module->remaining_rx_buffer_length) == 0) {
+					/* Disable RX Complete Interrupt,
+					 * and set STATUS_OK */
+					usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+					module->rx_status = STATUS_OK;
+
+					/* Run callback if registered and enabled */
+					if (callback_status
+							& (1 << USART_CALLBACK_BUFFER_RECEIVED)) {
+						(*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module);
+					}
+				}
+			}
+		} else {
+			/* This should not happen. Disable Receive Complete interrupt. */
+			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+		}
+	}
+
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+	if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) {
+			(*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module);
+		}
+	}
+#endif
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) {
+			(*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module);
+		}
+	}
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) {
+			(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
+		}
+	}
+#endif
+}
+

asf/sam0/drivers/sercom/usart/usart_interrupt.h

@@ -0,0 +1,177 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Asynchronous Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef USART_INTERRUPT_H_INCLUDED
+#define USART_INTERRUPT_H_INCLUDED
+
+#include "usart.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(__DOXYGEN__)
+enum status_code _usart_write_buffer(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length);
+
+enum status_code _usart_read_buffer(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length);
+
+void _usart_interrupt_handler(
+		uint8_t instance);
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sercom_usart_group
+ *
+ * @{
+ */
+
+/**
+ * \name Callback Management
+ * @{
+ */
+void usart_register_callback(
+		struct usart_module *const module,
+		usart_callback_t callback_func,
+		enum usart_callback callback_type);
+
+void usart_unregister_callback(
+		struct usart_module *module,
+		enum usart_callback callback_type);
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback function registered by the \ref usart_register_callback.
+ * The callback function will be called from the interrupt handler when the
+ * conditions for the callback type are met.
+ *
+ * \param[in]  module         Pointer to USART software instance struct
+ * \param[in]  callback_type  Callback type given by an enum
+ */
+static inline void usart_enable_callback(
+		struct usart_module *const module,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Enable callback */
+	module->callback_enable_mask |= (1 << callback_type);
+
+}
+
+/**
+ * \brief Disable callback
+ *
+ * Disables the callback function registered by the \ref usart_register_callback,
+ * and the callback will not be called from the interrupt routine.
+ *
+ * \param[in]  module         Pointer to USART software instance struct
+ * \param[in]  callback_type  Callback type given by an enum
+ */
+static inline void usart_disable_callback(
+		struct usart_module *const module,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Disable callback */
+	module->callback_enable_mask &= ~(1 << callback_type);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Writing and Reading
+ * @{
+ */
+enum status_code usart_write_job(
+		struct usart_module *const module,
+		const uint16_t *tx_data);
+
+enum status_code usart_read_job(
+		struct usart_module *const module,
+		uint16_t *const rx_data);
+
+enum status_code usart_write_buffer_job(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length);
+
+enum status_code usart_read_buffer_job(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length);
+
+void usart_abort_job(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type);
+
+enum status_code usart_get_job_status(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USART_INTERRUPT_H_INCLUDED */
+

asf/sam0/drivers/system/clock/clock.h

@@ -0,0 +1,53 @@
+/**
+ * \file
+ *
+ * \brief SAM Clock Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SYSTEM_CLOCK_H_INCLUDED
+#define SYSTEM_CLOCK_H_INCLUDED
+
+#include <compiler.h>
+#include <gclk.h>
+#include <clock_feature.h>
+
+#endif /* SYSTEM_CLOCK_H_INCLUDED */

asf/sam0/drivers/system/clock/clock_samd21_r21_da/clock_config_check.h

@@ -0,0 +1,454 @@
+/**
+ * \file
+ *
+ * \brief SAM D21/R21/DA0/DA1 Clock Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CLOCK_CONFIG_CHECK_H
+#  define CLOCK_CONFIG_CHECK_H
+
+#if !defined(CONF_CLOCK_FLASH_WAIT_STATES)
+#  error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_CPU_DIVIDER)
+#  error CONF_CLOCK_CPU_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_APBA_DIVIDER)
+#  error CONF_CLOCK_APBA_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_APBB_DIVIDER)
+#  error CONF_CLOCK_APBB_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_APBC_DIVIDER)
+#  error CONF_CLOCK_APBC_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_PRESCALER)
+#  error CONF_CLOCK_OSC8M_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_ON_DEMAND)
+#  error CONF_CLOCK_OSC8M_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC8M_RUN_IN_STANDBY)
+#  error CONF_CLOCK_OSC8M_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_ENABLE)
+#  error CONF_CLOCK_XOSC_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL)
+#  error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY)
+#  error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME)
+#  error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL)
+#  error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_ON_DEMAND)
+#  error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY)
+#  error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE)
+#  error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL)
+#  error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME)
+#  error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL)
+#  error CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT)
+#  error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT)
+#  error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND)
+#  error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY)
+#  error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE)
+#  error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME)
+#  error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT)
+#  error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT)
+#  error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND)
+#  error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY)
+#  error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ENABLE)
+#  error CONF_CLOCK_DFLL_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_LOOP_MODE)
+#  error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ON_DEMAND)
+#  error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_FINE_VALUE)
+#  error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR)
+#  error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR)
+#  error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK)
+#  error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK)
+#  error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP)
+#  error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE)
+#  error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE)
+#  error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE)
+#  error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_ENABLE)
+#  error CONF_CLOCK_DPLL_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_ON_DEMAND)
+#  error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY)
+#  error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS)
+#  error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST)
+#  error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE)
+#  error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOCK_TIME)
+#  error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK)
+#  error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_FILTER)
+#  error CONF_CLOCK_DPLL_FILTER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY)
+#  error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_DIVIDER)
+#  error CONF_CLOCK_DPLL_REFERENCE_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY)
+#  error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR)
+#  error CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR)
+#  error CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_CONFIGURE_GCLK)
+#  error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_ENABLE)
+#  error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_PRESCALER)
+#  error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_ENABLE)
+#  error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_PRESCALER)
+#  error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_ENABLE)
+#  error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_PRESCALER)
+#  error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_ENABLE)
+#  error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_PRESCALER)
+#  error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_ENABLE)
+#  error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_PRESCALER)
+#  error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_ENABLE)
+#  error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_PRESCALER)
+#  error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_ENABLE)
+#  error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_PRESCALER)
+#  error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_ENABLE)
+#  error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_PRESCALER)
+#  error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_ENABLE)
+#  error CONF_CLOCK_GCLK_8_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_8_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_8_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_PRESCALER)
+#  error CONF_CLOCK_GCLK_8_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_8_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#endif /* CLOCK_CONFIG_CHECK_H */

asf/sam0/drivers/system/clock/clock_samd21_r21_da/gclk.c

@@ -0,0 +1,522 @@
+/**
+ * \file
+ *
+ * \brief SAM D21/R21/DA0/DA1 Generic Clock Driver
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <gclk.h>
+#include <clock.h>
+#include <system_interrupt.h>
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval false if the module has completed synchronization
+ * \retval true if the module synchronization is ongoing
+ */
+static inline bool system_gclk_is_syncing(void)
+{
+	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * \brief Initializes the GCLK driver.
+ *
+ * Initializes the Generic Clock module, disabling and resetting all active
+ * Generic Clock Generators and Channels to their power-on default values.
+ */
+void system_gclk_init(void)
+{
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
+
+	/* Software reset the module to ensure it is re-initialized correctly */
+	GCLK->CTRL.reg = GCLK_CTRL_SWRST;
+	while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
+		/* Wait for reset to complete */
+	}
+}
+
+/**
+ * \brief Writes a Generic Clock Generator configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Generic Clock Generator configuration
+ * to the hardware module.
+ *
+ * \note Changing the clock source on the fly (on a running
+ *       generator) can take additional time if the clock source is configured
+ *       to only run on-demand (ONDEMAND bit is set) and it is not currently
+ *       running (no peripheral is requesting the clock source). In this case
+ *       the GCLK will request the new clock while still keeping a request to
+ *       the old clock source until the new clock source is ready.
+ *
+ * \note This function will not start a generator that is not already running;
+ *       to start the generator, call \ref system_gclk_gen_enable()
+ *       after configuring a generator.
+ *
+ * \param[in] generator  Generic Clock Generator index to configure
+ * \param[in] config     Configuration settings for the generator
+ */
+void system_gclk_gen_set_config(
+		const uint8_t generator,
+		struct system_gclk_gen_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Cache new register configurations to minimize sync requirements. */
+	uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
+	uint32_t new_gendiv_config  = (generator << GCLK_GENDIV_ID_Pos);
+
+	/* Select the requested source clock for the generator */
+	new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
+
+	/* Configure the clock to be either high or low when disabled */
+	if (config->high_when_disabled) {
+		new_genctrl_config |= GCLK_GENCTRL_OOV;
+	}
+
+	/* Configure if the clock output to I/O pin should be enabled. */
+	if (config->output_enable) {
+		new_genctrl_config |= GCLK_GENCTRL_OE;
+	}
+
+	/* Set division factor */
+	if (config->division_factor > 1) {
+		/* Check if division is a power of two */
+		if (((config->division_factor & (config->division_factor - 1)) == 0)) {
+			/* Determine the index of the highest bit set to get the
+			 * division factor that must be loaded into the division
+			 * register */
+
+			uint32_t div2_count = 0;
+
+			uint32_t mask;
+			for (mask = (1UL << 1); mask < config->division_factor;
+						mask <<= 1) {
+				div2_count++;
+			}
+
+			/* Set binary divider power of 2 division factor */
+			new_gendiv_config  |= div2_count << GCLK_GENDIV_DIV_Pos;
+			new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
+		} else {
+			/* Set integer division factor */
+
+			new_gendiv_config  |=
+					(config->division_factor) << GCLK_GENDIV_DIV_Pos;
+
+			/* Enable non-binary division with increased duty cycle accuracy */
+			new_genctrl_config |= GCLK_GENCTRL_IDC;
+		}
+
+	}
+
+	/* Enable or disable the clock in standby mode */
+	if (config->run_in_standby) {
+		new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
+	}
+
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the correct generator */
+	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
+
+	/* Write the new generator configuration */
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+	GCLK->GENDIV.reg  = new_gendiv_config;
+
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+	GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Enables a Generic Clock Generator that was previously configured.
+ *
+ * Starts the clock generation of a Generic Clock Generator that was previously
+ * configured via a call to \ref system_gclk_gen_set_config().
+ *
+ * \param[in] generator  Generic Clock Generator index to enable
+ */
+void system_gclk_gen_enable(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	/* Enable generator */
+	GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Disables a Generic Clock Generator that was previously enabled.
+ *
+ * Stops the clock generation of a Generic Clock Generator that was previously
+ * started via a call to \ref system_gclk_gen_enable().
+ *
+ * \param[in] generator  Generic Clock Generator index to disable
+ */
+void system_gclk_gen_disable(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	/* Disable generator */
+	GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;
+	while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) {
+		/* Wait for clock to become disabled */
+	}
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock Generator is enabled.
+ *
+ * \param[in] generator  Generic Clock Generator index to check
+ *
+ * \return The enabled status.
+ * \retval true The Generic Clock Generator is enabled
+ * \retval false The Generic Clock Generator is disabled
+ */
+bool system_gclk_gen_is_enabled(
+		const uint8_t generator)
+{
+	bool enabled;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	/* Obtain the enabled status */
+	enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+
+	system_interrupt_leave_critical_section();
+
+	return enabled;
+}
+
+/**
+ * \brief Retrieves the clock frequency of a Generic Clock generator.
+ *
+ * Determines the clock frequency (in Hz) of a specified Generic Clock
+ * generator, used as a source to a Generic Clock Channel module.
+ *
+ * \param[in] generator  Generic Clock Generator index
+ *
+ * \return The frequency of the generic clock generator, in Hz.
+ */
+uint32_t system_gclk_gen_get_hz(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the appropriate generator */
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	/* Get the frequency of the source connected to the GCLK generator */
+	uint32_t gen_input_hz = system_clock_source_get_hz(
+			(enum system_clock_source)GCLK->GENCTRL.bit.SRC);
+
+	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+
+	uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
+
+	/* Select the appropriate generator division register */
+	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
+	while (system_gclk_is_syncing()) {
+		/* Wait for synchronization */
+	};
+
+	uint32_t divider = GCLK->GENDIV.bit.DIV;
+
+	system_interrupt_leave_critical_section();
+
+	/* Check if the generator is using fractional or binary division */
+	if (!divsel && divider > 1) {
+		gen_input_hz /= divider;
+	} else if (divsel) {
+		gen_input_hz >>= (divider+1);
+	}
+
+	return gen_input_hz;
+}
+
+/**
+ * \brief Writes a Generic Clock configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Generic Clock configuration to the
+ * hardware module. If the clock is currently running, it will be stopped.
+ *
+ * \note Once called the clock will not be running; to start the clock,
+ *       call \ref system_gclk_chan_enable() after configuring a clock channel.
+ *
+ * \param[in] channel   Generic Clock channel to configure
+ * \param[in] config    Configuration settings for the clock
+ *
+ */
+void system_gclk_chan_set_config(
+		const uint8_t channel,
+		struct system_gclk_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Cache the new config to reduce sync requirements */
+	uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);
+
+	/* Select the desired generic clock generator */
+	new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
+
+	/* Disable generic clock channel */
+	system_gclk_chan_disable(channel);
+
+	/* Write the new configuration */
+	GCLK->CLKCTRL.reg = new_clkctrl_config;
+}
+
+/**
+ * \brief Enables a Generic Clock that was previously configured.
+ *
+ * Starts the clock generation of a Generic Clock that was previously
+ * configured via a call to \ref system_gclk_chan_set_config().
+ *
+ * \param[in] channel   Generic Clock channel to enable
+ */
+void system_gclk_chan_enable(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+	/* Enable the generic clock */
+	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Disables a Generic Clock that was previously enabled.
+ *
+ * Stops the clock generation of a Generic Clock that was previously started
+ * via a call to \ref system_gclk_chan_enable().
+ *
+ * \param[in] channel  Generic Clock channel to disable
+ */
+void system_gclk_chan_disable(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+	/* Sanity check WRTLOCK */
+	Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
+
+	/* Switch to known-working source so that the channel can be disabled */
+	uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
+	GCLK->CLKCTRL.bit.GEN = 0;
+
+	/* Disable the generic clock */
+	GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
+	while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
+		/* Wait for clock to become disabled */
+	}
+
+	/* Restore previous configured clock generator */
+	GCLK->CLKCTRL.bit.GEN = prev_gen_id;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock channel is enabled.
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The enabled status.
+ * \retval true The Generic Clock channel is enabled
+ * \retval false The Generic Clock channel is disabled
+ */
+bool system_gclk_chan_is_enabled(
+		const uint8_t channel)
+{
+	bool enabled;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generic clock channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+	enabled = GCLK->CLKCTRL.bit.CLKEN;
+
+	system_interrupt_leave_critical_section();
+
+	return enabled;
+}
+
+/**
+ * \brief Locks a Generic Clock channel from further configuration writes.
+ *
+ * Locks a generic clock channel from further configuration writes. It is only
+ * possible to unlock the channel configuration through a power on reset.
+ *
+ * \param[in] channel   Generic Clock channel to enable
+ */
+void system_gclk_chan_lock(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generator channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+
+	/* Lock the generic clock */
+	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK | GCLK_CLKCTRL_CLKEN;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock channel is locked.
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The lock status.
+ * \retval true The Generic Clock channel is locked
+ * \retval false The Generic Clock channel is not locked
+ */
+bool system_gclk_chan_is_locked(
+		const uint8_t channel)
+{
+	bool locked;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generic clock channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+	locked = GCLK->CLKCTRL.bit.WRTLOCK;
+
+	system_interrupt_leave_critical_section();
+
+	return locked;
+}
+
+/**
+ * \brief Retrieves the clock frequency of a Generic Clock channel.
+ *
+ * Determines the clock frequency (in Hz) of a specified Generic Clock
+ * channel, used as a source to a device peripheral module.
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The frequency of the generic clock channel, in Hz.
+ */
+uint32_t system_gclk_chan_get_hz(
+		const uint8_t channel)
+{
+	uint8_t gen_id;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generic clock channel */
+	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+	gen_id = GCLK->CLKCTRL.bit.GEN;
+
+	system_interrupt_leave_critical_section();
+
+	/* Return the clock speed of the associated GCLK generator */
+	return system_gclk_gen_get_hz(gen_id);
+}

asf/sam0/drivers/system/clock/gclk.h

@@ -0,0 +1,307 @@
+/**
+ * \file
+ *
+ * \brief SAM Generic Clock Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SYSTEM_CLOCK_GCLK_H_INCLUDED
+#define SYSTEM_CLOCK_GCLK_H_INCLUDED
+
+/**
+ * \addtogroup asfdoc_sam0_system_clock_group
+ *
+ * @{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief List of available GCLK generators.
+ *
+ * List of Available GCLK generators. This enum is used in the peripheral
+ * device drivers to select the GCLK generator to be used for its operation.
+ *
+ * The number of GCLK generators available is device dependent.
+ */
+enum gclk_generator {
+	/** GCLK generator channel 0 */
+	GCLK_GENERATOR_0,
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0)
+	/** GCLK generator channel 1 */
+	GCLK_GENERATOR_1,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1)
+	/** GCLK generator channel 2 */
+	GCLK_GENERATOR_2,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2)
+	/** GCLK generator channel 3 */
+	GCLK_GENERATOR_3,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3)
+	/** GCLK generator channel 4 */
+	GCLK_GENERATOR_4,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4)
+	/** GCLK generator channel 5 */
+	GCLK_GENERATOR_5,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5)
+	/** GCLK generator channel 6 */
+	GCLK_GENERATOR_6,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6)
+	/** GCLK generator channel 7 */
+	GCLK_GENERATOR_7,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7)
+	/** GCLK generator channel 8 */
+	GCLK_GENERATOR_8,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8)
+	/** GCLK generator channel 9 */
+	GCLK_GENERATOR_9,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9)
+	/** GCLK generator channel 10 */
+	GCLK_GENERATOR_10,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10)
+	/** GCLK generator channel 11 */
+	GCLK_GENERATOR_11,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11)
+	/** GCLK generator channel 12 */
+	GCLK_GENERATOR_12,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12)
+	/** GCLK generator channel 13 */
+	GCLK_GENERATOR_13,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13)
+	/** GCLK generator channel 14 */
+	GCLK_GENERATOR_14,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14)
+	/** GCLK generator channel 15 */
+	GCLK_GENERATOR_15,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15)
+	/** GCLK generator channel 16 */
+	GCLK_GENERATOR_16,
+#endif
+};
+
+/**
+ * \brief Generic Clock Generator configuration structure.
+ *
+ * Configuration structure for a Generic Clock Generator channel. This
+ * structure should be initialized by the
+ * \ref system_gclk_gen_get_config_defaults() function before being modified by
+ * the user application.
+ */
+struct system_gclk_gen_config {
+	/** Source clock input channel index, see the \ref system_clock_source */
+	uint8_t source_clock;
+	/** If \c true, the generator output level is high when disabled */
+	bool high_when_disabled;
+	/** Integer division factor of the clock output compared to the input */
+	uint32_t division_factor;
+	/** If \c true, the clock is kept enabled during device standby mode */
+	bool run_in_standby;
+	/** If \c true, enables GCLK generator clock output to a GPIO pin */
+	bool output_enable;
+};
+
+/**
+ * \brief Generic Clock configuration structure.
+ *
+ * Configuration structure for a Generic Clock channel. This structure
+ * should be initialized by the \ref system_gclk_chan_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct system_gclk_chan_config {
+	/** Generic Clock Generator source channel */
+	enum gclk_generator source_generator;
+};
+
+/** \name Generic Clock Management
+ * @{
+ */
+void system_gclk_init(void);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Management (Generators)
+ * @{
+ */
+
+/**
+ * \brief Initializes a Generic Clock Generator configuration structure to defaults.
+ *
+ * Initializes a given Generic Clock Generator configuration structure to
+ * a set of known default values. This function should be called on all
+ * new instances of these configuration structures before being modified
+ * by the user application.
+ *
+ * The default configuration is:
+ *  \li The clock is generated undivided from the source frequency
+ *  \li The clock generator output is low when the generator is disabled
+ *  \li The input clock is sourced from input clock channel 0
+ *  \li The clock will be disabled during sleep
+ *  \li The clock output will not be routed to a physical GPIO pin
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void system_gclk_gen_get_config_defaults(
+		struct system_gclk_gen_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->division_factor    = 1;
+	config->high_when_disabled = false;
+#if SAML21 || SAML22  || SAMR30
+	config->source_clock       = GCLK_SOURCE_OSC16M;
+#elif (SAMC20) || (SAMC21)
+	config->source_clock       = GCLK_SOURCE_OSC48M;
+#else
+	config->source_clock       = GCLK_SOURCE_OSC8M;
+#endif
+	config->run_in_standby     = false;
+	config->output_enable      = false;
+}
+
+void system_gclk_gen_set_config(
+		const uint8_t generator,
+		struct system_gclk_gen_config *const config);
+
+void system_gclk_gen_enable(
+		const uint8_t generator);
+
+void system_gclk_gen_disable(
+		const uint8_t generator);
+
+bool system_gclk_gen_is_enabled(
+		const uint8_t generator);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Management (Channels)
+ * @{
+ */
+
+/**
+ * \brief Initializes a Generic Clock configuration structure to defaults.
+ *
+ * Initializes a given Generic Clock configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ *  \li The clock is sourced from the Generic Clock Generator channel 0
+ *  \li The clock configuration will not be write-locked when set
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void system_gclk_chan_get_config_defaults(
+		struct system_gclk_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->source_generator = GCLK_GENERATOR_0;
+}
+
+void system_gclk_chan_set_config(
+		const uint8_t channel,
+		struct system_gclk_chan_config *const config);
+
+void system_gclk_chan_enable(
+		const uint8_t channel);
+
+void system_gclk_chan_disable(
+		const uint8_t channel);
+
+bool system_gclk_chan_is_enabled(
+		const uint8_t channel);
+
+void system_gclk_chan_lock(
+		const uint8_t channel);
+
+bool system_gclk_chan_is_locked(
+		const uint8_t channel);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Frequency Retrieval
+ * @{
+ */
+
+uint32_t system_gclk_gen_get_hz(
+		const uint8_t generator);
+
+uint32_t system_gclk_chan_get_hz(
+		const uint8_t channel);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif

asf/sam0/drivers/system/interrupt/system_interrupt.c

@@ -0,0 +1,217 @@
+/**
+ * \file
+ *
+ * \brief SAM System Interrupt Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "system_interrupt.h"
+
+/**
+ * \brief Check if a interrupt line is pending.
+ *
+ * Checks if the requested interrupt vector is pending.
+ *
+ * \param[in] vector  Interrupt vector number to check
+ *
+ * \returns A boolean identifying if the requested interrupt vector is pending.
+ *
+ * \retval true   Specified interrupt vector is pending
+ * \retval false  Specified interrupt vector is not pending
+ *
+ */
+bool system_interrupt_is_pending(
+		const enum system_interrupt_vector vector)
+{
+	bool result;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		result = ((NVIC->ISPR[0] & (1 << vector)) != 0);
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0);
+	} else {
+		Assert(false);
+		result = false;
+	}
+
+	return result;
+}
+
+/**
+ * \brief Set a interrupt vector as pending.
+ *
+ * Set the requested interrupt vector as pending (i.e. issues a software
+ * interrupt request for the specified vector). The software handler will be
+ * handled (if enabled) in a priority order based on vector number and
+ * configured priority settings.
+ *
+ * \param[in] vector  Interrupt vector number which is set as pending
+ *
+ * \returns Status code identifying if the vector was successfully set as
+ *          pending.
+ *
+ * \retval STATUS_OK           If no error was detected
+ * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_set_pending(
+		const enum system_interrupt_vector vector)
+{
+	enum status_code status = STATUS_OK;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		NVIC->ISPR[0] = (1 << vector);
+	} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
+		/* Note: Because NMI has highest priority it will be executed
+		 * immediately after it has been set pending */
+		SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk;
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
+	} else {
+		/* The user want to set something unsupported as pending */
+		Assert(false);
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	return status;
+}
+
+/**
+ * \brief Clear pending interrupt vector.
+ *
+ * Clear a pending interrupt vector, so the software handler is not executed.
+ *
+ * \param[in] vector  Interrupt vector number to clear
+ *
+ * \returns A status code identifying if the interrupt pending state was
+ *          successfully cleared.
+ *
+ * \retval STATUS_OK           If no error was detected
+ * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_clear_pending(
+		const enum system_interrupt_vector vector)
+{
+	enum status_code status = STATUS_OK;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		NVIC->ICPR[0] = (1 << vector);
+	} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
+		/* Note: Clearing of NMI pending interrupts does not make sense and is
+		 * not supported by the device, as it has the highest priority and will
+		 * always be executed at the moment it is set */
+		return STATUS_ERR_INVALID_ARG;
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
+	} else {
+		Assert(false);
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	return status;
+}
+
+/**
+ * \brief Set interrupt vector priority level.
+ *
+ * Set the priority level of an external interrupt or exception.
+ *
+ * \param[in] vector          Interrupt vector to change
+ * \param[in] priority_level  New vector priority level to set
+ *
+ * \returns Status code indicating if the priority level of the interrupt was
+ *          successfully set.
+ *
+ * \retval STATUS_OK           If no error was detected
+ * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_set_priority(
+		const enum system_interrupt_vector vector,
+		const enum system_interrupt_priority_level priority_level)
+{
+	enum status_code status = STATUS_OK;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		uint8_t register_num = vector / 4;
+		uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
+
+		NVIC->IP[register_num] =
+				(NVIC->IP[register_num] & ~(_SYSTEM_INTERRUPT_PRIORITY_MASK << priority_pos)) |
+				(priority_level << priority_pos);
+
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS);
+	} else {
+		Assert(false);
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	return status;
+}
+
+/**
+ * \brief Get interrupt vector priority level.
+ *
+ * Retrieves the priority level of the requested external interrupt or exception.
+ *
+ * \param[in] vector  Interrupt vector of which the priority level will be read
+ *
+ * \return Currently configured interrupt priority level of the given interrupt
+ *         vector.
+ */
+enum system_interrupt_priority_level system_interrupt_get_priority(
+		const enum system_interrupt_vector vector)
+{
+	uint8_t register_num = vector / 4;
+	uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
+
+	enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0;
+
+	if (vector >= 0) {
+		priority = (enum system_interrupt_priority_level)
+				((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		priority = (enum system_interrupt_priority_level)
+				((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
+	}
+
+	return priority;
+}
+

asf/sam0/drivers/system/interrupt/system_interrupt.h

@@ -0,0 +1,429 @@
+/**
+ * \file
+ *
+ * \brief SAM System Interrupt Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SYSTEM_INTERRUPT_H_INCLUDED
+#define SYSTEM_INTERRUPT_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_interrupt_group SAM System Interrupt (SYSTEM INTERRUPT) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of internal software and
+ * hardware interrupts/exceptions.
+ *
+ * The following peripheral is used by this module:
+ *  - NVIC (Nested Vector Interrupt Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_interrupt_prerequisites
+ *  - \ref asfdoc_sam0_system_interrupt_module_overview
+ *  - \ref asfdoc_sam0_system_interrupt_special_considerations
+ *  - \ref asfdoc_sam0_system_interrupt_extra_info
+ *  - \ref asfdoc_sam0_system_interrupt_examples
+ *  - \ref asfdoc_sam0_system_interrupt_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_module_overview Module Overview
+ *
+ * The ARM&reg; Cortex&reg; M0+ core contains an interrupt and exception vector table, which
+ * can be used to configure the device's interrupt handlers; individual
+ * interrupts and exceptions can be enabled and disabled, as well as configured
+ * with a variable priority.
+ *
+ * This driver provides a set of wrappers around the core interrupt functions,
+ * to expose a simple API for the management of global and individual interrupts
+ * within the device.
+ *
+ * \subsection asfdoc_sam0_system_interrupt_module_overview_criticalsec Critical Sections
+ * In some applications it is important to ensure that no interrupts may be
+ * executed by the system whilst a critical portion of code is being run; for
+ * example, a buffer may be copied from one context to another - during which
+ * interrupts must be disabled to avoid corruption of the source buffer contents
+ * until the copy has completed. This driver provides a basic API to enter and
+ * exit nested critical sections, so that global interrupts can be kept disabled
+ * for as long as necessary to complete a critical application code section.
+ *
+ * \subsection asfdoc_sam0_system_interrupt_module_overview_softints Software Interrupts
+ * For some applications, it may be desirable to raise a module or core
+ * interrupt via software. For this reason, a set of APIs to set an interrupt or
+ * exception as pending are provided to the user application.
+ *
+ * \section asfdoc_sam0_system_interrupt_special_considerations Special Considerations
+ *
+ * Interrupts from peripherals in the SAM devices are on a per-module basis;
+ * an interrupt raised from any source within a module will cause a single,
+ * module-common handler to execute. It is the user application or driver's
+ * responsibility to de-multiplex the module-common interrupt to determine the
+ * exact interrupt cause.
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_interrupt_extra. This includes:
+ *  - \ref asfdoc_sam0_system_interrupt_extra_acronyms
+ *  - \ref asfdoc_sam0_system_interrupt_extra_dependencies
+ *  - \ref asfdoc_sam0_system_interrupt_extra_errata
+ *  - \ref asfdoc_sam0_system_interrupt_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_interrupt_exqsg.
+ *
+ * \section asfdoc_sam0_system_interrupt_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <core_cm0plus.h>
+#include "system_interrupt_features.h"
+
+/**
+ * \brief Table of possible system interrupt/exception vector priorities.
+ *
+ * Table of all possible interrupt and exception vector priorities within the
+ * device.
+ */
+enum system_interrupt_priority_level {
+	/** Priority level 0, the highest possible interrupt priority */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_0  = 0,
+	/** Priority level 1 */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_1  = 1,
+	/** Priority level 2 */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_2  = 2,
+	/** Priority level 3, the lowest possible interrupt priority */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_3  = 3,
+};
+
+/**
+ * \name Critical Section Management
+ * @{
+ */
+
+/**
+ * \brief Enters a critical section.
+ *
+ * Disables global interrupts. To support nested critical sections, an internal
+ * count of the critical section nesting will be kept, so that global interrupts
+ * are only re-enabled upon leaving the outermost nested critical section.
+ *
+ */
+static inline void system_interrupt_enter_critical_section(void)
+{
+	cpu_irq_enter_critical();
+}
+
+/**
+ * \brief Leaves a critical section.
+ *
+ * Enables global interrupts. To support nested critical sections, an internal
+ * count of the critical section nesting will be kept, so that global interrupts
+ * are only re-enabled upon leaving the outermost nested critical section.
+ *
+ */
+static inline void system_interrupt_leave_critical_section(void)
+{
+	cpu_irq_leave_critical();
+}
+
+/** @} */
+
+/**
+ * \name Interrupt Enabling/Disabling
+ * @{
+ */
+
+/**
+ * \brief Check if global interrupts are enabled.
+ *
+ * Checks if global interrupts are currently enabled.
+ *
+ * \returns A boolean that identifies if the global interrupts are enabled or not.
+ *
+ * \retval true   Global interrupts are currently enabled
+ * \retval false  Global interrupts are currently disabled
+ *
+ */
+static inline bool system_interrupt_is_global_enabled(void)
+{
+	return cpu_irq_is_enabled();
+}
+
+/**
+ * \brief Enables global interrupts.
+ *
+ * Enables global interrupts in the device to fire any enabled interrupt handlers.
+ */
+static inline void system_interrupt_enable_global(void)
+{
+	cpu_irq_enable();
+}
+
+/**
+ * \brief Disables global interrupts.
+ *
+ * Disabled global interrupts in the device, preventing any enabled interrupt
+ * handlers from executing.
+ */
+static inline void system_interrupt_disable_global(void)
+{
+	cpu_irq_disable();
+}
+
+/**
+ * \brief Checks if an interrupt vector is enabled or not.
+ *
+ * Checks if a specific interrupt vector is currently enabled.
+ *
+ * \param[in] vector  Interrupt vector number to check
+ *
+ * \returns A variable identifying if the requested interrupt vector is enabled.
+ *
+ * \retval true   Specified interrupt vector is currently enabled
+ * \retval false  Specified interrupt vector is currently disabled
+ *
+ */
+static inline bool system_interrupt_is_enabled(
+		const enum system_interrupt_vector vector)
+{
+	return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001);
+}
+
+/**
+ * \brief Enable interrupt vector.
+ *
+ * Enables execution of the software handler for the requested interrupt vector.
+ *
+ * \param[in] vector Interrupt vector to enable
+ */
+static inline void system_interrupt_enable(
+		const enum system_interrupt_vector vector)
+{
+	NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+}
+
+/**
+ * \brief Disable interrupt vector.
+ *
+ * Disables execution of the software handler for the requested interrupt vector.
+ *
+ * \param[in] vector  Interrupt vector to disable
+ */
+static inline void system_interrupt_disable(
+		const enum system_interrupt_vector vector)
+{
+	NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+}
+
+/** @} */
+
+/**
+ * \name Interrupt State Management
+ * @{
+ */
+
+/**
+ * \brief Get active interrupt (if any).
+ *
+ * Return the vector number for the current executing software handler, if any.
+ *
+ * \return Interrupt number that is currently executing.
+ */
+static inline enum system_interrupt_vector system_interrupt_get_active(void)
+{
+	uint32_t IPSR = __get_IPSR();
+	/* The IPSR returns the Exception number, which with an offset 16 to IRQ number. */
+	return (enum system_interrupt_vector)((IPSR & _SYSTEM_INTERRUPT_IPSR_MASK) - 16);
+}
+
+bool system_interrupt_is_pending(
+		const enum system_interrupt_vector vector);
+
+enum status_code system_interrupt_set_pending(
+		const enum system_interrupt_vector vector);
+
+enum status_code system_interrupt_clear_pending(
+		const enum system_interrupt_vector vector);
+
+/** @} */
+
+/**
+ * \name Interrupt Priority Management
+ * @{
+ */
+
+enum status_code system_interrupt_set_priority(
+		const enum system_interrupt_vector vector,
+		const enum system_interrupt_priority_level priority_level);
+
+enum system_interrupt_priority_level system_interrupt_get_priority(
+		const enum system_interrupt_vector vector);
+
+/** @} */
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_system_interrupt_extra Extra Information for SYSTEM INTERRUPT Driver
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>ISR</td>
+ *		<td>Interrupt Service Routine</td>
+ *	</tr>
+ *	<tr>
+ *		<td>NMI</td>
+ *		<td>Non-maskable Interrupt</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SERCOM</td>
+ *		<td>Serial Communication Interface</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_interrupt_exqsg Examples for SYSTEM INTERRUPT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_interrupt_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_system_interrupt_critsec_use_case
+ *  - \subpage asfdoc_sam0_system_interrupt_enablemodint_use_case
+ *
+ * \page asfdoc_sam0_system_interrupt_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42122E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // #ifndef SYSTEM_INTERRUPT_H_INCLUDED

asf/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h

@@ -0,0 +1,195 @@
+/**
+ * \file
+ *
+ * \brief SAM D21 System Interrupt Driver
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
+#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
+
+#if !defined(__DOXYGEN__)
+
+/* Generates a interrupt vector table enum list entry for a given module type
+   and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */
+#  define _MODULE_IRQn(n, module) \
+		SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
+
+/* Generates interrupt vector table enum list entries for all instances of a
+   given module type on the selected device. */
+#  define _SYSTEM_INTERRUPT_MODULES(name) \
+		MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
+
+#  define _SYSTEM_INTERRUPT_IPSR_MASK              0x0000003f
+#  define _SYSTEM_INTERRUPT_PRIORITY_MASK          0x00000003
+
+#  define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START  0
+
+#  define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS        30
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_interrupt_group
+ * @{
+ */
+
+/**
+ * \brief Table of possible system interrupt/exception vector numbers.
+ *
+ * Table of all possible interrupt and exception vector indexes within the
+ * SAM D21 device. Check peripherals configuration in SAM D21 datasheet for
+ * available vector index for specific device.
+ *
+ */
+#if defined(__DOXYGEN__)
+/** \note The actual enumeration name is "system_interrupt_vector". */
+enum system_interrupt_vector_samd21 {
+#else
+enum system_interrupt_vector {
+#endif
+	/** Interrupt vector index for a NMI interrupt */
+	SYSTEM_INTERRUPT_NON_MASKABLE      = NonMaskableInt_IRQn,
+	/** Interrupt vector index for a Hard Fault memory access exception */
+	SYSTEM_INTERRUPT_HARD_FAULT        = HardFault_IRQn,
+	/** Interrupt vector index for a Supervisor Call exception */
+	SYSTEM_INTERRUPT_SV_CALL           = SVCall_IRQn,
+	/** Interrupt vector index for a Pending Supervisor interrupt */
+	SYSTEM_INTERRUPT_PENDING_SV        = PendSV_IRQn,
+	/** Interrupt vector index for a System Tick interrupt */
+	SYSTEM_INTERRUPT_SYSTICK           = SysTick_IRQn,
+
+	/** Interrupt vector index for a Power Manager peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_PM         = PM_IRQn,
+	/** Interrupt vector index for a System Control peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_SYSCTRL    = SYSCTRL_IRQn,
+	/** Interrupt vector index for a Watch Dog peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_WDT        = WDT_IRQn,
+	/** Interrupt vector index for a Real Time Clock peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_RTC        = RTC_IRQn,
+	/** Interrupt vector index for an External Interrupt peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_EIC        = EIC_IRQn,
+	/** Interrupt vector index for a Non Volatile Memory Controller interrupt */
+	SYSTEM_INTERRUPT_MODULE_NVMCTRL    = NVMCTRL_IRQn,
+	/** Interrupt vector index for a Direct Memory Access interrupt */
+	SYSTEM_INTERRUPT_MODULE_DMA        = DMAC_IRQn,
+#if defined(__DOXYGEN__) || defined(ID_USB)
+	/** Interrupt vector index for a Universal Serial Bus interrupt */
+	SYSTEM_INTERRUPT_MODULE_USB        = USB_IRQn,
+#endif
+	/** Interrupt vector index for an Event System interrupt */
+	SYSTEM_INTERRUPT_MODULE_EVSYS      = EVSYS_IRQn,
+#if defined(__DOXYGEN__)
+	/** Interrupt vector index for a SERCOM peripheral interrupt.
+	 *
+	 *  Each specific device may contain several SERCOM peripherals; each module
+	 *  instance will have its own entry in the table, with the instance number
+	 *  substituted for "n" in the entry name (e.g.
+	 *  \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
+	 */
+	SYSTEM_INTERRUPT_MODULE_SERCOMn    = SERCOMn_IRQn,
+
+	/** Interrupt vector index for a Timer/Counter Control peripheral interrupt.
+	 *
+	 *  Each specific device may contain several TCC peripherals; each module
+	 *  instance will have its own entry in the table, with the instance number
+	 *  substituted for "n" in the entry name (e.g.
+	 *  \c SYSTEM_INTERRUPT_MODULE_TCC0).
+	 */
+	SYSTEM_INTERRUPT_MODULE_TCCn        = TCCn_IRQn,
+
+	/** Interrupt vector index for a Timer/Counter peripheral interrupt.
+	 *
+	 *  Each specific device may contain several TC peripherals; each module
+	 *  instance will have its own entry in the table, with the instance number
+	 *  substituted for "n" in the entry name (e.g.
+	 *  \c SYSTEM_INTERRUPT_MODULE_TC3).
+	 */
+	SYSTEM_INTERRUPT_MODULE_TCn        = TCn_IRQn,
+#else
+	_SYSTEM_INTERRUPT_MODULES(SERCOM)
+
+	_SYSTEM_INTERRUPT_MODULES(TCC)
+
+	SYSTEM_INTERRUPT_MODULE_TC3        = TC3_IRQn,
+	SYSTEM_INTERRUPT_MODULE_TC4        = TC4_IRQn,
+	SYSTEM_INTERRUPT_MODULE_TC5        = TC5_IRQn,
+#  if defined(ID_TC6)
+	SYSTEM_INTERRUPT_MODULE_TC6        = TC6_IRQn,
+#  endif
+#  if defined(ID_TC7)
+	SYSTEM_INTERRUPT_MODULE_TC7        = TC7_IRQn,
+#  endif
+#endif
+
+#if defined(__DOXYGEN__) || defined(ID_ADC)
+	/** Interrupt vector index for an Analog-to-Digital peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_ADC        = ADC_IRQn,
+#endif
+
+#if defined(__DOXYGEN__) || defined(ID_AC)
+	/** Interrupt vector index for an Analog Comparator peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_AC         = AC_IRQn,
+#endif
+
+#if defined(__DOXYGEN__) || defined(ID_DAC)
+	/** Interrupt vector index for a Digital-to-Analog peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_DAC        = DAC_IRQn,
+#endif
+#if defined(__DOXYGEN__) || defined(ID_PTC)
+	/** Interrupt vector index for a Peripheral Touch Controller peripheral
+	 *  interrupt */
+	SYSTEM_INTERRUPT_MODULE_PTC        = PTC_IRQn,
+#endif
+#if defined(__DOXYGEN__) || defined(ID_I2S)
+	/** Interrupt vector index for a Inter-IC Sound Interface peripheral
+	 *  interrupt */
+	SYSTEM_INTERRUPT_MODULE_I2S        = I2S_IRQn,
+#endif
+#if defined(__DOXYGEN__) || defined(ID_AC1)
+	/** Interrupt vector index for an Analog Comparator 1 peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_AC1        = AC1_IRQn,
+#endif
+};
+
+/** @} */
+
+#endif

asf/sam0/drivers/system/pinmux/pinmux.c

@@ -0,0 +1,311 @@
+/**
+ * \file
+ *
+ * \brief SAM Pin Multiplexer Driver
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <pinmux.h>
+
+/**
+ * \internal
+ * Writes out a given configuration of a Port pin configuration to the
+ * hardware module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ *       configuration setting is ignored.
+ *
+ * \param[in] port      Base of the PORT module to configure
+ * \param[in] pin_mask  Mask of the port pin to configure
+ * \param[in] config    Configuration settings for the pin
+ */
+static void _system_pinmux_config(
+		PortGroup *const port,
+		const uint32_t pin_mask,
+		const struct system_pinmux_config *const config)
+{
+	Assert(port);
+	Assert(config);
+
+	/* Track the configuration bits into a temporary variable before writing */
+	uint32_t pin_cfg = 0;
+
+	/* Enabled powersave mode, don't create configuration */
+	if (!config->powersave) {
+		/* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will
+		 * be written later) and store the new MUX mask */
+		if (config->mux_position != SYSTEM_PINMUX_GPIO) {
+			pin_cfg |= PORT_WRCONFIG_PMUXEN;
+			pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
+		}
+
+		/* Check if the user has requested that the input buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
+				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+			/* Enable input buffer flag */
+			pin_cfg |= PORT_WRCONFIG_INEN;
+
+			/* Enable pull-up/pull-down control flag if requested */
+			if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
+				pin_cfg |= PORT_WRCONFIG_PULLEN;
+			}
+
+			/* Clear the port DIR bits to disable the output buffer */
+			port->DIRCLR.reg = pin_mask;
+		}
+
+		/* Check if the user has requested that the output buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+			/* Cannot use a pull-up if the output driver is enabled,
+			 * if requested the input buffer can only sample the current
+			 * output state */
+			pin_cfg &= ~PORT_WRCONFIG_PULLEN;
+		}
+	} else {
+		port->DIRCLR.reg = pin_mask;
+	}
+
+	/* The Write Configuration register (WRCONFIG) requires the
+	 * pins to to grouped into two 16-bit half-words - split them out here */
+	uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
+	uint32_t upper_pin_mask = (pin_mask >> 16);
+
+	/* Configure the lower 16-bits of the port to the desired configuration,
+	 * including the pin peripheral multiplexer just in case it is enabled */
+	port->WRCONFIG.reg
+		= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
+
+	/* Configure the upper 16-bits of the port to the desired configuration,
+	 * including the pin peripheral multiplexer just in case it is enabled */
+	port->WRCONFIG.reg
+		= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
+			PORT_WRCONFIG_HWSEL;
+
+	if(!config->powersave) {
+		/* Set the pull-up state once the port pins are configured if one was
+		 * requested and it does not violate the valid set of port
+		 * configurations */
+		if (pin_cfg & PORT_WRCONFIG_PULLEN) {
+			/* Set the OUT register bits to enable the pull-up if requested,
+			 * clear to enable pull-down */
+			if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
+				port->OUTSET.reg = pin_mask;
+			} else {
+				port->OUTCLR.reg = pin_mask;
+			}
+		}
+
+		/* Check if the user has requested that the output buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+			/* Set the port DIR bits to enable the output buffer */
+			port->DIRSET.reg = pin_mask;
+		}
+	}
+}
+
+/**
+ * \brief Writes a Port pin configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Port pin configuration to the hardware
+ * module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ *       configuration setting is ignored.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] config    Configuration settings for the pin
+ */
+void system_pinmux_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct system_pinmux_config *const config)
+{
+	PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask = (1UL << (gpio_pin % 32));
+
+	_system_pinmux_config(port, pin_mask, config);
+}
+
+/**
+ * \brief Writes a Port pin group configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Port pin group configuration to the
+ * hardware module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ *       configuration setting is ignored.
+ *
+ * \param[in] port      Base of the PORT module to configure
+ * \param[in] mask      Mask of the port pin(s) to configure
+ * \param[in] config    Configuration settings for the pin
+ */
+void system_pinmux_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct system_pinmux_config *const config)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			_system_pinmux_config(port, (1UL << i), config);
+		}
+	}
+}
+
+/**
+ * \brief Configures the input sampling mode for a group of pins.
+ *
+ * Configures the input sampling mode for a group of pins, to
+ * control when the physical I/O pin value is sampled and
+ * stored inside the microcontroller.
+ *
+ * \param[in] port     Base of the PORT module to configure
+ * \param[in] mask     Mask of the port pin(s) to configure
+ * \param[in] mode     New pin sampling mode to configure
+ */
+void system_pinmux_group_set_input_sample_mode(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_sample mode)
+{
+	Assert(port);
+
+	if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
+		port->CTRL.reg |= mask;
+	} else {
+		port->CTRL.reg &= ~mask;
+	}
+}
+
+#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
+/**
+ * \brief Configures the output slew rate mode for a group of pins.
+ *
+ * Configures the output slew rate mode for a group of pins, to
+ * control the speed at which the physical output pin can react to
+ * logical changes of the I/O pin value.
+ *
+ * \param[in] port     Base of the PORT module to configure
+ * \param[in] mask     Mask of the port pin(s) to configure
+ * \param[in] mode     New pin slew rate mode to configure
+ */
+void system_pinmux_group_set_output_slew_rate(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_slew_rate mode)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
+				port->PINCFG[i].reg |=  PORT_PINCFG_SLEWLIM;
+			} else {
+				port->PINCFG[i].reg &= ~PORT_PINCFG_SLEWLIM;
+			}
+		}
+	}
+}
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+/**
+ * \brief Configures the output driver strength mode for a group of pins.
+ *
+ * Configures the output drive strength for a group of pins, to
+ * control the amount of current the pad is able to sink/source.
+ *
+ * \param[in] port     Base of the PORT module to configure
+ * \param[in] mask     Mask of the port pin(s) to configure
+ * \param[in] mode     New output driver strength mode to configure
+ */
+void system_pinmux_group_set_output_strength(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_strength mode)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
+				port->PINCFG[i].reg |=  PORT_PINCFG_DRVSTR;
+			} else {
+				port->PINCFG[i].reg &= ~PORT_PINCFG_DRVSTR;
+			}
+		}
+	}
+}
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN
+/**
+ * \brief Configures the output driver mode for a group of pins.
+ *
+ * Configures the output driver mode for a group of pins, to
+ * control the pad behavior.
+ *
+ * \param[in] port Base of the PORT module to configure
+ * \param[in] mask Mask of the port pin(s) to configure
+ * \param[in] mode New pad output driver mode to configure
+ */
+void system_pinmux_group_set_output_drive(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_drive mode)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
+				port->PINCFG[i].reg |= PORT_PINCFG_ODRAIN;
+			} else {
+				port->PINCFG[i].reg &= ~PORT_PINCFG_ODRAIN;
+			}
+		}
+	}
+}
+#endif

asf/sam0/drivers/system/pinmux/pinmux.h

@@ -0,0 +1,675 @@
+/**
+ * \file
+ *
+ * \brief SAM Pin Multiplexer Driver
+ *
+ * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef PINMUX_H_INCLUDED
+#define PINMUX_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_system_pinmux_group SAM System Pin Multiplexer (SYSTEM PINMUX) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's physical
+ * I/O Pins, to alter the direction and input/drive characteristics as well as
+ * to configure the pin peripheral multiplexer selection.
+ *
+ * The following peripheral is used by this module:
+ *  - PORT (Port I/O Management)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_pinmux_prerequisites
+ *  - \ref asfdoc_sam0_system_pinmux_module_overview
+ *  - \ref asfdoc_sam0_system_pinmux_special_considerations
+ *  - \ref asfdoc_sam0_system_pinmux_extra_info
+ *  - \ref asfdoc_sam0_system_pinmux_examples
+ *  - \ref asfdoc_sam0_system_pinmux_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_module_overview Module Overview
+ *
+ * The SAM devices contain a number of General Purpose I/O pins, used to
+ * interface the user application logic and internal hardware peripherals to
+ * an external system. The Pin Multiplexer (PINMUX) driver provides a method
+ * of configuring the individual pin peripheral multiplexers to select
+ * alternate pin functions.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH</td>
+ *    <td>SAM L21, SAM C20/C21</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_physical_logical_pins Physical and Logical GPIO Pins
+ * SAM devices use two naming conventions for the I/O pins in the device; one
+ * physical and one logical. Each physical pin on a device package is assigned
+ * both a physical port and pin identifier (e.g. "PORTA.0") as well as a
+ * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
+ * former is used to map physical pins to their physical internal device module
+ * counterparts, for simplicity the design of this driver uses the logical GPIO
+ * numbers instead.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_peripheral_muxing Peripheral Multiplexing
+ * SAM devices contain a peripheral MUX, which is individually controllable
+ * for each I/O pin of the device. The peripheral MUX allows you to select the
+ * function of a physical package pin - whether it will be controlled as a user
+ * controllable GPIO pin, or whether it will be connected internally to one of
+ * several peripheral modules (such as an I<SUP>2</SUP>C module). When a pin is
+ * configured in GPIO mode, other peripherals connected to the same pin will be
+ * disabled.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_pad_characteristics Special Pad Characteristics
+ * There are several special modes that can be selected on one or more I/O pins
+ * of the device, which alter the input and output characteristics of the pad.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_drive_strength Drive Strength
+ * The Drive Strength configures the strength of the output driver on the
+ * pad. Normally, there is a fixed current limit that each I/O pin can safely
+ * drive, however some I/O pads offer a higher drive mode which increases this
+ * limit for that I/O pin at the expense of an increased power consumption.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_slew_rate Slew Rate
+ * The Slew Rate configures the slew rate of the output driver, limiting the
+ * rate at which the pad output voltage can change with time.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_input_sample_mode Input Sample Mode
+ * The Input Sample Mode configures the input sampler buffer of the pad. By
+ * default, the input buffer is only sampled "on-demand", i.e. when the user
+ * application attempts to read from the input buffer. This mode is the most
+ * power efficient, but increases the latency of the input sample by two clock
+ * cycles of the port clock. To reduce latency, the input sampler can instead
+ * be configured to always sample the input buffer on each port clock cycle, at
+ * the expense of an increased power consumption.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_system_pinmux_intconnections "The diagram below" shows
+ * how this module is interconnected within the device:
+ *
+ * \anchor asfdoc_sam0_system_pinmux_intconnections
+ * \dot
+ * digraph overview {
+ *   node [label="Port Pad" shape=square] pad;
+ *
+ *   subgraph driver {
+ *     node [label="Peripheral MUX" shape=trapezium] pinmux;
+ *     node [label="GPIO Module" shape=ellipse shape=ellipse style=filled fillcolor=lightgray] gpio;
+ *     node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ *   }
+ *
+ *   pinmux -> gpio;
+ *   pad    -> pinmux;
+ *   pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ * \section asfdoc_sam0_system_pinmux_special_considerations Special Considerations
+ *
+ * The SAM port pin input sampling mode is set in groups of four physical
+ * pins; setting the sampling mode of any pin in a sub-group of eight I/O pins
+ * will configure the sampling mode of the entire sub-group.
+ *
+ * High Drive Strength output driver mode is not available on all device pins -
+ * refer to your device specific datasheet.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_pinmux_extra. This includes:
+ *  - \ref asfdoc_sam0_system_pinmux_extra_acronyms
+ *  - \ref asfdoc_sam0_system_pinmux_extra_dependencies
+ *  - \ref asfdoc_sam0_system_pinmux_extra_errata
+ *  - \ref asfdoc_sam0_system_pinmux_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_pinmux_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*@{*/
+#if (SAML21) || (SAMC20) || (SAMC21) || (SAMD21) || (SAMD10) || (SAMD11) || (SAMR30) || defined(__DOXYGEN__)
+/** Output Driver Strength Selection feature support */
+#  define FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+#endif
+/*@}*/
+
+/** Peripheral multiplexer index to select GPIO mode for a pin */
+#define SYSTEM_PINMUX_GPIO    (1 << 7)
+
+/**
+ * \brief Port pin direction configuration enum.
+ *
+ * Enum for the possible pin direction settings of the port pin configuration
+ * structure, to indicate the direction the pin should use.
+ */
+enum system_pinmux_pin_dir {
+	/** The pin's input buffer should be enabled, so that the pin state can
+	 *  be read */
+	SYSTEM_PINMUX_PIN_DIR_INPUT,
+	/** The pin's output buffer should be enabled, so that the pin state can
+	 *  be set (but not read back) */
+	SYSTEM_PINMUX_PIN_DIR_OUTPUT,
+	/** The pin's output and input buffers should both be enabled, so that the
+	 *  pin state can be set and read back */
+	SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
+};
+
+/**
+ * \brief Port pin input pull configuration enum.
+ *
+ * Enum for the possible pin pull settings of the port pin configuration
+ * structure, to indicate the type of logic level pull the pin should use.
+ */
+enum system_pinmux_pin_pull {
+	/** No logical pull should be applied to the pin */
+	SYSTEM_PINMUX_PIN_PULL_NONE,
+	/** Pin should be pulled up when idle */
+	SYSTEM_PINMUX_PIN_PULL_UP,
+	/** Pin should be pulled down when idle */
+	SYSTEM_PINMUX_PIN_PULL_DOWN,
+};
+
+/**
+ * \brief Port pin digital input sampling mode enum.
+ *
+ * Enum for the possible input sampling modes for the port pin configuration
+ * structure, to indicate the type of sampling a port pin should use.
+ */
+enum system_pinmux_pin_sample {
+	/** Pin input buffer should continuously sample the pin state */
+	SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS,
+	/** Pin input buffer should be enabled when the IN register is read */
+	SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND,
+};
+
+/**
+ * \brief Port pin configuration structure.
+ *
+ * Configuration structure for a port pin instance. This structure should
+ * be initialized by the \ref system_pinmux_get_config_defaults() function
+ * before being modified by the user application.
+ */
+struct system_pinmux_config {
+	/** MUX index of the peripheral that should control the pin, if peripheral
+	 *  control is desired. For GPIO use, this should be set to
+	 *  \ref SYSTEM_PINMUX_GPIO. */
+	uint8_t mux_position;
+
+	/** Port buffer input/output direction */
+	enum system_pinmux_pin_dir direction;
+
+	/** Logic level pull of the input buffer */
+	enum system_pinmux_pin_pull input_pull;
+
+	/** Enable lowest possible powerstate on the pin
+	 *
+	 *  \note All other configurations will be ignored, the pin will be disabled.
+	 */
+	bool powersave;
+};
+
+/** \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Initializes a Port pin configuration structure to defaults.
+ *
+ * Initializes a given Port pin configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ *  \li Non peripheral (i.e. GPIO) controlled
+ *  \li Input mode with internal pull-up enabled
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void system_pinmux_get_config_defaults(
+		struct system_pinmux_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->mux_position = SYSTEM_PINMUX_GPIO;
+	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	config->input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
+	config->powersave    = false;
+}
+
+void system_pinmux_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct system_pinmux_config *const config);
+
+void system_pinmux_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct system_pinmux_config *const config);
+
+/** @} */
+
+/** \name Special Mode Configuration (Physical Group Orientated)
+ *  @{
+ */
+
+/**
+ * \brief Retrieves the PORT module group instance from a given GPIO pin number.
+ *
+ * Retrieves the PORT module group instance associated with a given logical
+ * GPIO pin number.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to convert
+ *
+ * \return Base address of the associated PORT module.
+ */
+static inline PortGroup* system_pinmux_get_group_from_gpio_pin(
+		const uint8_t gpio_pin)
+{
+	uint8_t port_index  = (gpio_pin / 128);
+	uint8_t group_index = (gpio_pin / 32);
+
+	/* Array of available ports */
+	Port *const ports[PORT_INST_NUM] = PORT_INSTS;
+
+	if (port_index < PORT_INST_NUM) {
+		return &(ports[port_index]->Group[group_index]);
+	} else {
+		Assert(false);
+		return NULL;
+	}
+}
+
+void system_pinmux_group_set_input_sample_mode(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_sample mode);
+
+/** @} */
+
+/** \name Special Mode Configuration (Logical Pin Orientated)
+ *  @{
+ */
+
+/**
+ * \brief Retrieves the currently selected MUX position of a logical pin.
+ *
+ * Retrieves the selected MUX peripheral on a given logical GPIO pin.
+ *
+ * \param[in]  gpio_pin  Index of the GPIO pin to configure
+ *
+ * \return Currently selected peripheral index on the specified pin.
+ */
+static inline uint8_t system_pinmux_pin_get_mux_position(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_index = (gpio_pin % 32);
+
+	if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) {
+		return SYSTEM_PINMUX_GPIO;
+	}
+
+	uint32_t pmux_reg = port->PMUX[pin_index / 2].reg;
+
+	if (pin_index & 1) {
+		return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	}
+	else {
+		return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	}
+}
+
+/**
+ * \brief Configures the input sampling mode for a GPIO pin.
+ *
+ * Configures the input sampling mode for a GPIO input, to
+ * control when the physical I/O pin value is sampled and
+ * stored inside the microcontroller.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure
+ * \param[in] mode     New pin sampling mode to configure
+ */
+static inline void system_pinmux_pin_set_input_sample_mode(
+		const uint8_t gpio_pin,
+		const enum system_pinmux_pin_sample mode)
+{
+	PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_index = (gpio_pin % 32);
+
+	if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
+		port->CTRL.reg |= (1 << pin_index);
+	} else {
+		port->CTRL.reg &= ~(1 << pin_index);
+	}
+}
+
+/** @} */
+
+#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+/**
+ * \brief Port pin drive output strength enum.
+ *
+ * Enum for the possible output drive strengths for the port pin
+ * configuration structure, to indicate the driver strength the pin should
+ * use.
+ */
+enum system_pinmux_pin_strength {
+  /** Normal output driver strength */
+  SYSTEM_PINMUX_PIN_STRENGTH_NORMAL,
+  /** High current output driver strength */
+  SYSTEM_PINMUX_PIN_STRENGTH_HIGH,
+};
+
+/**
+ * \brief Configures the output driver strength mode for a GPIO pin.
+ *
+ * Configures the output drive strength for a GPIO output, to
+ * control the amount of current the pad is able to sink/source.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] mode      New output driver strength mode to configure
+ */
+static inline void system_pinmux_pin_set_output_strength(
+    const uint8_t gpio_pin,
+    const enum system_pinmux_pin_strength mode)
+{
+  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+  uint32_t pin_index = (gpio_pin % 32);
+
+  if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
+    port->PINCFG[pin_index].reg |=  PORT_PINCFG_DRVSTR;
+  }
+ else {
+    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_DRVSTR;
+ }
+}
+
+void system_pinmux_group_set_output_strength(
+    PortGroup *const port,
+    const uint32_t mask,
+    const enum system_pinmux_pin_strength mode);
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
+/**
+ * \brief Port pin output slew rate enum.
+ *
+ * Enum for the possible output drive slew rates for the port pin
+ * configuration structure, to indicate the driver slew rate the pin should
+ * use.
+ */
+enum system_pinmux_pin_slew_rate {
+  /** Normal pin output slew rate */
+  SYSTEM_PINMUX_PIN_SLEW_RATE_NORMAL,
+  /** Enable slew rate limiter on the pin */
+  SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED,
+};
+
+/**
+ * \brief Configures the output slew rate mode for a GPIO pin.
+ *
+ * Configures the output slew rate mode for a GPIO output, to
+ * control the speed at which the physical output pin can react to
+ * logical changes of the I/O pin value.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] mode      New pin slew rate mode to configure
+ */
+static inline void system_pinmux_pin_set_output_slew_rate(
+    const uint8_t gpio_pin,
+    const enum system_pinmux_pin_slew_rate mode)
+{
+  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+  uint32_t pin_index = (gpio_pin % 32);
+
+  if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
+    port->PINCFG[pin_index].reg |=  PORT_PINCFG_SLEWLIM;
+  }
+  else {
+    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_SLEWLIM;
+  }
+}
+
+void system_pinmux_group_set_output_slew_rate(
+   PortGroup *const port,
+    const uint32_t mask,
+    const enum system_pinmux_pin_slew_rate mode);
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN
+/**
+ * \brief Port pin output drive mode enum.
+ *
+ * Enum for the possible output drive modes for the port pin configuration
+ * structure, to indicate the output mode the pin should use.
+ */
+enum system_pinmux_pin_drive {
+  /** Use totem pole output drive mode */
+  SYSTEM_PINMUX_PIN_DRIVE_TOTEM,
+  /** Use open drain output drive mode */
+  SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN,
+};
+
+/**
+ * \brief Configures the output driver mode for a GPIO pin.
+ *
+ * Configures the output driver mode for a GPIO output, to
+ * control the pad behavior.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] mode      New pad output driver mode to configure
+ */
+static inline void system_pinmux_pin_set_output_drive(
+    const uint8_t gpio_pin,
+    const enum system_pinmux_pin_drive mode)
+{
+  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+  uint32_t pin_index = (gpio_pin % 32);
+
+  if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
+    port->PINCFG[pin_index].reg |=  PORT_PINCFG_ODRAIN;
+  }
+  else {
+    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_ODRAIN;
+  }
+}
+
+void system_pinmux_group_set_output_drive(
+    PortGroup *const port,
+    const uint32_t mask,
+    const enum system_pinmux_pin_drive mode);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_extra Extra Information for SYSTEM PINMUX Driver
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>GPIO</td>
+ *		<td>General Purpose Input/Output</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MUX</td>
+ *		<td>Multiplexer</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Removed code of open drain, slew limit and drive strength
+ *		features</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Fixed broken sampling mode function implementations, which wrote
+ *		    corrupt configuration values to the device registers</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added missing NULL pointer asserts to the PORT driver functions</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_exqsg Examples for SYSTEM PINMUX Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_pinmux_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in a
+ * selection of use cases. Note that a QSG can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_system_pinmux_basic_use_case
+ *
+ * \page asfdoc_sam0_system_pinmux_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121F</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121E</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121D</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121C</td>
+ *		<td>09/2013</td>
+ *		<td>Fixed incorrect documentation for the device pin sampling mode</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif

asf/sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h

@@ -0,0 +1,96 @@
+/**
+ * \file
+ *
+ * \brief SAM PINMUX Driver Quick Start
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_basic_use_case Quick Start Guide for SYSTEM PINMUX - Basic
+ *
+ * In this use case, the PINMUX module is configured for:
+ *  \li One pin in input mode, with pull-up enabled, connected to the GPIO
+ *      module
+ *  \li Sampling mode of the pin changed to sample on demand
+ *
+ * This use case sets up the PINMUX to configure a physical I/O pin set as
+ * an input with pull-up and changes the sampling mode of the pin to reduce
+ * power by only sampling the physical pin state when the user application
+ * attempts to read it.
+ *
+ * \section asfdoc_sam0_system_pinmux_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_code Code
+ * Copy-paste the following setup code to your application:
+ * \snippet qs_pinmux_basic.c setup
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_flow Workflow
+ * -# Create a PINMUX module pin configuration struct, which can be filled out
+ *    to adjust the configuration of a single port pin.
+ *    \snippet qs_pinmux_basic.c pinmux_config
+ * -# Initialize the pin configuration struct with the module's default values.
+ *    \snippet qs_pinmux_basic.c pinmux_config_defaults
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Adjust the configuration struct to request an input pin with pull-up
+ *    connected to the GPIO peripheral.
+ *  \snippet qs_pinmux_basic.c pinmux_update_config_values
+ * -# Configure GPIO10 with the initialized pin configuration struct, to enable
+ *    the input sampler on the pin.
+ *    \snippet qs_pinmux_basic.c pinmux_set_config
+ *
+ * \section asfdoc_sam0_system_pinmux_basic_use_case_use_main Use Case
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_pinmux_basic.c main
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_flow Workflow
+
+ * -# Adjust the configuration of the pin to enable on-demand sampling mode.
+ *    \snippet qs_pinmux_basic.c pinmux_change_input_sampling
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */

asf/sam0/drivers/system/power/power_sam_d_r/power.h

@@ -0,0 +1,224 @@
+/**
+ * \file
+ *
+ * \brief SAM Power related functionality
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef POWER_H_INCLUDED
+#define POWER_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_group
+ * @{
+ */
+
+/**
+ * \brief Voltage references within the device.
+ *
+ * List of available voltage references (VREF) that may be used within the
+ * device.
+ */
+enum system_voltage_reference {
+	/** Temperature sensor voltage reference */
+	SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
+	/** Bandgap voltage reference */
+	SYSTEM_VOLTAGE_REFERENCE_BANDGAP,
+};
+
+/**
+ * \brief Device sleep modes.
+ *
+ * List of available sleep modes in the device. A table of clocks available in
+ * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ */
+enum system_sleepmode {
+	/** IDLE 0 sleep mode */
+	SYSTEM_SLEEPMODE_IDLE_0,
+	/** IDLE 1 sleep mode */
+	SYSTEM_SLEEPMODE_IDLE_1,
+	/** IDLE 2 sleep mode */
+	SYSTEM_SLEEPMODE_IDLE_2,
+	/** Standby sleep mode */
+	SYSTEM_SLEEPMODE_STANDBY,
+};
+
+
+
+/**
+ * \name Voltage References
+ * @{
+ */
+
+/**
+ * \brief Enable the selected voltage reference
+ *
+ * Enables the selected voltage reference source, making the voltage reference
+ * available on a pin as well as an input source to the analog peripherals.
+ *
+ * \param[in] vref  Voltage reference to enable
+ */
+static inline void system_voltage_reference_enable(
+		const enum system_voltage_reference vref)
+{
+	switch (vref) {
+		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+			SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN;
+			break;
+
+		case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
+			SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
+			break;
+
+		default:
+			Assert(false);
+			return;
+	}
+}
+
+/**
+ * \brief Disable the selected voltage reference
+ *
+ * Disables the selected voltage reference source.
+ *
+ * \param[in] vref  Voltage reference to disable
+ */
+static inline void system_voltage_reference_disable(
+		const enum system_voltage_reference vref)
+{
+	switch (vref) {
+		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+			SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN;
+			break;
+
+		case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
+			SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN;
+			break;
+
+		default:
+			Assert(false);
+			return;
+	}
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * \name Device Sleep Control
+ * @{
+ */
+
+/**
+ * \brief Set the sleep mode of the device
+ *
+ * Sets the sleep mode of the device; the configured sleep mode will be entered
+ * upon the next call of the \ref system_sleep() function.
+ *
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ *
+ * \param[in] sleep_mode  Sleep mode to configure for the next sleep operation
+ *
+ * \retval STATUS_OK               Operation completed successfully
+ * \retval STATUS_ERR_INVALID_ARG  The requested sleep mode was invalid or not
+ *                                 available
+ */
+static inline enum status_code system_set_sleepmode(
+	const enum system_sleepmode sleep_mode)
+{
+#if (SAMD20)
+	/* Errata 13140: Make sure that the Flash does not power all the way down
+	 * when in sleep mode. This errata has been fixed as of revision D of SAMD21 */
+	NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val;
+#endif
+
+	switch (sleep_mode) {
+		case SYSTEM_SLEEPMODE_IDLE_0:
+		case SYSTEM_SLEEPMODE_IDLE_1:
+		case SYSTEM_SLEEPMODE_IDLE_2:
+			SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+			PM->SLEEP.reg = sleep_mode;
+			break;
+
+		case SYSTEM_SLEEPMODE_STANDBY:
+			SCB->SCR |=  SCB_SCR_SLEEPDEEP_Msk;
+			break;
+
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Put the system to sleep waiting for interrupt
+ *
+ * Executes a device DSB (Data Synchronization Barrier) instruction to ensure
+ * all ongoing memory accesses have completed, then a WFI (Wait For Interrupt)
+ * instruction to place the device into the sleep mode specified by
+ * \ref system_set_sleepmode until woken by an interrupt.
+ */
+static inline void system_sleep(void)
+{
+	__DSB();
+	__WFI();
+}
+
+/**
+ * @}
+ */
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* POWER_H_INCLUDED */

asf/sam0/drivers/system/reset/reset_sam_d_r/reset.h

@@ -0,0 +1,119 @@
+/**
+ * \file
+ *
+ * \brief SAM Reset related functionality
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef RESET_H_INCLUDED
+#define RESET_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_group
+ * @{
+ */
+
+/**
+ * \brief Reset causes of the system.
+ *
+ * List of possible reset causes of the system.
+ */
+enum system_reset_cause {
+	/** The system was last reset by a software reset */
+	SYSTEM_RESET_CAUSE_SOFTWARE       = PM_RCAUSE_SYST,
+	/** The system was last reset by the watchdog timer */
+	SYSTEM_RESET_CAUSE_WDT            = PM_RCAUSE_WDT,
+	/** The system was last reset because the external reset line was pulled low */
+	SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT,
+	/** The system was last reset by the BOD33 */
+	SYSTEM_RESET_CAUSE_BOD33          = PM_RCAUSE_BOD33,
+	/** The system was last reset by the BOD12 */
+	SYSTEM_RESET_CAUSE_BOD12          = PM_RCAUSE_BOD12,
+	/** The system was last reset by the POR (Power on reset) */
+	SYSTEM_RESET_CAUSE_POR            = PM_RCAUSE_POR,
+};
+
+
+/**
+ * \name Reset Control
+ * @{
+ */
+
+/**
+ * \brief Reset the MCU.
+ *
+ * Resets the MCU and all associated peripherals and registers, except RTC, all 32KHz sources,
+ * WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set).
+ *
+ */
+static inline void system_reset(void)
+{
+	NVIC_SystemReset();
+}
+
+/**
+ * \brief Return the reset cause.
+ *
+ * Retrieves the cause of the last system reset.
+ *
+ * \return An enum value indicating the cause of the last system reset.
+ */
+static inline enum system_reset_cause system_get_reset_cause(void)
+{
+	return (enum system_reset_cause)PM->RCAUSE.reg;
+}
+
+/**
+ * @}
+ */
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RESET_H_INCLUDED */

asf/sam0/drivers/system/system.c

@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief SAM System related functionality
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <system.h>
+
+/**
+ * \internal
+ * Dummy initialization function, used as a weak alias target for the various
+ * init functions called by \ref system_init().
+ */
+void _system_dummy_init(void);
+void _system_dummy_init(void)
+{
+	return;
+}
+
+#if !defined(__DOXYGEN__)
+#  if defined(__GNUC__)
+void system_clock_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void system_board_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_events_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_extint_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_divas_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+#  elif defined(__ICCARM__)
+void system_clock_init(void);
+void system_board_init(void);
+void _system_events_init(void);
+void _system_extint_init(void);
+void _system_divas_init(void);
+#    pragma weak system_clock_init=_system_dummy_init
+#    pragma weak system_board_init=_system_dummy_init
+#    pragma weak _system_events_init=_system_dummy_init
+#    pragma weak _system_extint_init=_system_dummy_init
+#    pragma weak _system_divas_init=_system_dummy_init
+#  endif
+#endif
+
+/**
+ * \brief Initialize system
+ *
+ * This function will call the various initialization functions within the
+ * system namespace. If a given optional system module is not available, the
+ * associated call will effectively be a NOP (No Operation).
+ *
+ * Currently the following initialization functions are supported:
+ *  - System clock initialization (via the SYSTEM CLOCK sub-module)
+ *  - Board hardware initialization (via the Board module)
+ *  - Event system driver initialization (via the EVSYS module)
+ *  - External Interrupt driver initialization (via the EXTINT module)
+ */
+void system_init(void)
+{
+	/* Configure GCLK and clock sources according to conf_clocks.h */
+	system_clock_init();
+
+	/* Initialize board hardware */
+	system_board_init();
+
+	/* Initialize EVSYS hardware */
+	_system_events_init();
+
+	/* Initialize External hardware */
+	_system_extint_init();
+	
+	/* Initialize DIVAS hardware */
+	_system_divas_init();
+}
+

asf/sam0/drivers/system/system.h

@@ -0,0 +1,728 @@
+/**
+ * \file
+ *
+ * \brief SAM System related functionality
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SYSTEM_H_INCLUDED
+#define SYSTEM_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+#include <pinmux.h>
+#include <power.h>
+#include <reset.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_group SAM System (SYSTEM) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's system relation functionality, necessary for
+ * the basic device operation. This is not limited to a single peripheral, but
+ * extends across multiple hardware peripherals.
+ *
+ * The following peripherals are used by this module:
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  - PM (Power Manager)
+ *  - RSTC (Reset Controller)
+ *  - SUPC (Supply Controller)
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  - PM (Power Manager)
+ *  - RSTC (Reset Controller)
+ *  - SUPC (Supply Controller)
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  - SYSCTRL (System Control)
+ *  - PM (Power Manager)
+ * \endif
+ *
+ * The following devices can use this module:
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  - Atmel | SMART SAM L21
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  - Atmel | SMART SAM C20/C21
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM DA1
+ * \endif
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_prerequisites
+ *  - \ref asfdoc_sam0_system_module_overview
+ *  - \ref asfdoc_sam0_system_special_considerations
+ *  - \ref asfdoc_sam0_system_extra_info
+ *  - \ref asfdoc_sam0_system_examples
+ *  - \ref asfdoc_sam0_system_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_module_overview Module Overview
+ *
+ * The System driver provides a collection of interfaces between the user
+ * application logic, and the core device functionality (such as clocks, reset
+ * cause determination, etc.) that is required for all applications. It contains
+ * a number of sub-modules that control one specific aspect of the device:
+ *
+ * - System Core (this module)
+ * - \ref asfdoc_sam0_system_clock_group "System Clock Control" (sub-module)
+ * - \ref asfdoc_sam0_system_interrupt_group "System Interrupt Control" (sub-module)
+ * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Control" (sub-module)
+ *
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * \subsection asfdoc_sam0_system_module_overview_vreg_l21 Voltage Regulator
+ * The SAM device controls the voltage regulators for the core (VDDCORE) and
+ * backup (VDDBU) domains. It sets the voltage regulators according to the sleep
+ * modes, the performance level, or the user configuration.
+ *
+ * In active mode, the voltage regulator can be chosen on the fly between a LDO
+ * or a Buck converter. In standby mode, the low power voltage regulator is used
+ * to supply VDDCORE.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_bbps Battery Backup Power Switch
+ * The SAM device supports connection of a battery backup to the VBAT power pin.
+ * It includes functionality that enables automatic power switching between main
+ * power and battery backup power. This will ensure power to the backup domain,
+ * when the main battery or power source is unavailable.
+ * \endif
+ *
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ * \subsection asfdoc_sam0_system_module_overview_vreg_c21 Voltage Regulator
+ * The SAM device controls the voltage regulators for the core (VDDCORE). It sets
+ * the voltage regulators according to the sleep modes.
+ *
+ * There are a selectable reference voltage and voltage dependent on the temperature
+ * which can be used by analog modules like the ADC.
+ * \endif
+ *
+ * \subsection asfdoc_sam0_system_module_overview_vref Voltage References
+ * The various analog modules within the SAM devices (such as AC, ADC, and
+ * DAC) require a voltage reference to be configured to act as a reference point
+ * for comparisons and conversions.
+ *
+ * The SAM devices contain multiple references, including an internal
+ * temperature sensor and a fixed band-gap voltage source. When enabled, the
+ * associated voltage reference can be selected within the desired peripheral
+ * where applicable.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_reset_cause System Reset Cause
+ * In some applications there may be a need to execute a different program
+ * flow based on how the device was reset. For example, if the cause of reset
+ * was the Watchdog timer (WDT), this might indicate an error in the application,
+ * and a form of error handling or error logging might be needed.
+ *
+ * For this reason, an API is provided to retrieve the cause of the last system
+ * reset, so that appropriate action can be taken.
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * There are three groups of reset sources:
+ *   - Power supply reset: Resets caused by an electrical issue. It covers POR and BOD reset.
+ *   - User reset: Resets caused by the application. It covers external reset,
+ *             system reset, and watchdog reset.
+ *   - Backup reset: Resets caused by a backup mode exit condition.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_performance_level Performance Level
+ * Performance level allows the user to adjust the regulator output voltage to reduce
+ * power consumption. The user can on the fly select the most suitable performance
+ * level, depending on the application demands.
+ *
+ * The SAM device can operate at two different performance levels (PL0 and PL2).
+ * When operating at PL0, the voltage applied on the full logic area is reduced
+ * by voltage scaling. This voltage scaling technique allows to reduce the active
+ * power consumption while decreasing the maximum frequency of the device. When
+ * operating at PL2, the voltage regulator supplies the highest voltage, allowing
+ * the device to run at higher clock speeds.
+ *
+ * Performance level transition is possible only when the device is in active
+ * mode. After a reset, the device starts at the lowest performance level
+ * (lowest power consumption and lowest max. frequency). The application can then
+ * switch to another performance level at any time without any stop in the code
+ * execution. As shown in \ref asfdoc_sam0_system_performance_level_transition_figure.
+ *
+ * \note When scaling down the performance level, the bus frequency should first be
+ *  scaled down in order to not exceed the maximum frequency allowed for the
+ *  low performance level.
+ *  When scaling up the performance level (e.g. from PL0 to PL2), check the performance
+ *  level status before increasing the bus frequency. It can be increased only
+ *  when the performance level transition is completed.
+ *
+ * \anchor asfdoc_sam0_system_performance_level_transition_figure
+ * \image html performance_level_transition.svg "Performance Level Transition"
+ *
+ * \subsection asfdoc_sam0_system_module_overview_power_domain Power Domain Gating
+ * Power domain gating allows power saving by reducing the voltage in logic
+ * areas in the device to a low-power supply. The feature is available in
+ * Standby sleep mode and will reduce the voltage in domains where all peripherals
+ * are idle. Internal logic will maintain its content, meaning the corresponding
+ * peripherals will not need to be reconfigured when normal operating voltage
+ * is returned. Most power domains can be in the following three states:
+ *
+ * - Active state: The power domain is powered on.
+ * - Retention state: The main voltage supply for the power domain is switched off,
+ * while maintaining a secondary low-power supply for the sequential cells. The
+ * logic context is restored when waking up.
+ * - Off state: The power domain is entirely powered off. The logic context is lost.
+ *
+ * The SAM L21 device  contains three power domains which can be controlled using
+ * power domain gating, namely PD0, PD1, and PD2. These power domains can be
+ * configured to the following cases:
+ * - Default with no sleepwalking peripherals: A power domain is automatically set
+ * to retention state in standby sleep mode if no activity require it. The application
+ * can force all power domains to remain in active state during standby sleep mode
+ * in order to accelerate wakeup time.
+ * - Default with sleepwalking peripherals: If one or more peripherals are enabled
+ * to perform sleepwalking tasks in standby sleep mode, the corresponding power
+ * domain (PDn) remains in active state as well as all inferior power domains (<PDn).
+ * - Sleepwalking with dynamic power domain gating: During standby sleep mode, a
+ * power domain (PDn) in active can wake up a superior power domain (>PDn) in order
+ * to perform a sleepwalking task. The superior power domain is then automatically
+ * set to active state. At the end of the sleepwalking task, the device can either
+ * be woken up or the superior power domain can return to retention state.
+ *
+ * Power domains can be linked to each other, it allows a power domain (PDn) to be kept
+ * in active state if the inferior power domain (PDn-1) is in active state too.
+ *
+ * \ref asfdoc_sam0_system_power_domain_overview_table illustrates the
+ * four cases to consider in standby mode.
+ *
+ * \anchor asfdoc_sam0_system_power_domain_overview_table
+ * <table>
+ *  <caption>Sleep Mode versus Power Domain State Overview</caption>
+ *  <tr>
+ *      <th>Sleep mode</th>
+ *      <th>PD0</th>
+ *      <th>PD1</th>
+ *      <th>PD2</th>
+ *      <th>PDTOP</th>
+ *      <th>PDBACKUP</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 1</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 2</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>retention</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 3</td>
+ *      <td>active</td>
+ *      <td>retention</td>
+ *      <td>retention</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 4</td>
+ *      <td>retention</td>
+ *      <td>retention</td>
+ *      <td>retention</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Backup</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *  </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_system_module_overview_ram_state RAMs Low Power Mode
+ * By default, in standby sleep mode, RAM is in low power mode (back biased)
+ * if its power domain is in retention state.
+ * \ref asfdoc_sam0_system_power_ram_state_table lists RAMs low power mode.
+ *
+ * \anchor asfdoc_sam0_system_power_ram_state_table
+ * <table>
+ *  <caption>RAM Back-biasing Mode</caption>
+ *  <tr>
+ *      <th>RAM mode</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Retention Back-biasing mode</td>
+ *      <td>RAM is back-biased if its power domain is in retention mode</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby Back-biasing mode</td>
+ *      <td>RAM is back-biased if the device is in standby mode</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby OFF mode</td>
+ *      <td>RAM is OFF if the device is in standby mode</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Always OFF mode</td>
+ *      <td>RAM is OFF if the device is in RET mode</td>
+ *  </tr>
+ * </table>
+ *
+ * \endif
+ *
+ * \subsection asfdoc_sam0_system_module_overview_sleep_mode Sleep Modes
+ * The SAM devices have several sleep modes. The sleep mode controls
+ * which clock systems on the device will remain enabled or disabled when the
+ * device enters a low power sleep mode.
+ * \ref asfdoc_sam0_system_module_sleep_mode_table "The table below" lists the
+ * clock settings of the different sleep modes.
+ *
+ * \anchor asfdoc_sam0_system_module_sleep_mode_table
+ * <table>
+ *  <caption>SAM Device Sleep Modes</caption>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <th>Sleep mode</th>
+ *      <th>System clock</th>
+ *      <th>CPU clock</th>
+ *      <th>AHB/AHB clock</th>
+ *      <th>GCLK clocks</th>
+ *      <th>Oscillators (ONDEMAND  = 0)</th>
+ *      <th>Oscillators (ONDEMAND  = 1)</th>
+ *      <th>Regulator mode</th>
+ *      <th>RAM mode</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle</td>
+ *      <td>Run</td>
+ *      <td>Stop</td>
+ *      <td>Run if requested</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run if requested</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Run if requested</td>
+ *      <td>Run if requested</td>
+ *      <td>Run if requested or RUNSTDBY  = 1</td>
+ *      <td>Run if requested</td>
+ *      <td>Low pwer</td>
+ *      <td>Low pwer</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Backup</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Backup</td>
+ *      <td>Off</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *  </tr>
+ * \else
+ *  <tr>
+ *      <th>Sleep mode</th>
+ *      <th>CPU clock</th>
+ *      <th>AHB clock</th>
+ *      <th>APB clocks</th>
+ *      <th>Clock sources</th>
+ *      <th>System clock</th>
+ *      <th>32KHz</th>
+ *      <th>Reg mode</th>
+ *      <th>RAM mode</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle 0</td>
+ *      <td>Stop</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle 1</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle 2</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Low Power</td>
+ *      <td>Source/Drain biasing</td>
+ *  </tr>
+ * \endif
+ * </table>
+ *
+ * Before entering device sleep, one of the available sleep modes must be set.
+ * The device will automatically wake up in response to an interrupt being
+ * generated or upon any other sleep mode exit condition.
+ *
+ * Some peripheral clocks will remain enabled during sleep, depending on their
+ * configuration. If desired, the modules can remain clocked during sleep to allow
+ * them continue to operate while other parts of the system are powered down
+ * to save power.
+ *
+ *
+ * \section asfdoc_sam0_system_special_considerations Special Considerations
+ *
+ * Most of the functions in this driver have device specific restrictions and
+ * caveats; refer to your device datasheet.
+ *
+ *
+ * \section asfdoc_sam0_system_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_extra. This includes:
+ *  - \ref asfdoc_sam0_system_extra_acronyms
+ *  - \ref asfdoc_sam0_system_extra_dependencies
+ *  - \ref asfdoc_sam0_system_extra_errata
+ *  - \ref asfdoc_sam0_system_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_examples Examples
+ *
+ * For SYSTEM module related examples, refer to the sub-modules listed in
+ * the \ref asfdoc_sam0_system_module_overview "Module Overview".
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_drivers_power_exqsg.
+ * \endif
+ *
+ *
+ * \section asfdoc_sam0_system_api_overview API Overview
+ * @{
+ */
+
+/**
+ * \name System Debugger
+ * @{
+ */
+
+/**
+ * \brief Check if debugger is present.
+ *
+ * Check if debugger is connected to the onboard debug system (DAP).
+ *
+ * \return A bool identifying if a debugger is present.
+ *
+ * \retval true  Debugger is connected to the system
+ * \retval false Debugger is not connected to the system
+ *
+ */
+static inline bool system_is_debugger_present(void)
+{
+	return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Identification
+ * @{
+ */
+
+/**
+ * \brief Retrieve the device identification signature.
+ *
+ * Retrieves the signature of the current device.
+ *
+ * \return Device ID signature as a 32-bit integer.
+ */
+static inline uint32_t system_get_device_id(void)
+{
+	return DSU->DID.reg;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Initialization
+ * @{
+ */
+
+void system_init(void);
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * \page asfdoc_sam0_drivers_power_exqsg Examples for SYSTEM Driver
+ *
+ * This is a list of the available Quick Start Guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_group. QSGs are simple examples with step-by-step instructions to
+ * configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_power_basic_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_system_extra Extra Information for SYSTEM Driver
+ *
+ * \section asfdoc_sam0_system_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Definition</th>
+ *  </tr>
+ *  <tr>
+ *      <td>PM</td>
+ *      <td>Power Manager</td>
+ *  </tr>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>SUPC</td>
+ *      <td>Supply Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>RSTC</td>
+ *      <td>Reset Controller</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>SUPC</td>
+ *      <td>Supply Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>RSTC</td>
+ *      <td>Reset Controller</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>SYSCTRL</td>
+ *      <td>System control interface</td>
+ *  </tr>
+ * \endif
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>Added new \c system_reset() to reset the complete MCU with some exceptions</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Added new \c system_get_device_id() function to retrieved the device
+ *          ID</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * \endif
+ * </table>
+ *
+ * \page asfdoc_sam0_system_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>42449A</td>
+ *      <td>07/2015</td>
+ *      <td>Initial document release</td>
+ * </tr>
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>42484A</td>
+ *      <td>12/2015</td>
+ *      <td>Initial document release.</td>
+ * </tr>
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>42120E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM DA1 and SAM D09</td>
+ * </tr>
+ *  <tr>
+ *      <td>42120D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ * </tr>
+ * <tr>
+ *      <td>42120C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42120B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42120A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial document release</td>
+ *  </tr>
+ * \endif
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_H_INCLUDED */
+

asf/sam0/drivers/usb/stack_interface/usb_dual.c

@@ -0,0 +1,178 @@
+/**
+ * \file
+ *
+ * \brief SAM USB Dual Role driver file.
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <compiler.h>
+#include "usb_dual.h"
+
+#ifndef UDD_ENABLE
+# define udc_start()
+# define udc_stop()
+#else
+#include <udc.h>
+#endif
+
+#ifndef UHD_ENABLE
+# define uhc_start(void)
+# define uhc_stop(b_id_stop)
+#else
+#include <uhc.h>
+#endif
+
+/* State of USB dual role initialization */
+static bool _initialized = false;
+
+#define _usb_is_id_device()         port_pin_get_input_level(USB_ID_PIN)
+
+#if USB_ID_EIC
+static void usb_id_handler(void);
+
+/**
+ * \name USB ID PAD management
+ *
+ * @{
+ */
+
+/**
+ * USB ID pin configuration
+ */
+static void usb_id_config(void)
+{
+	struct extint_chan_conf eint_chan_conf;
+	extint_chan_get_config_defaults(&eint_chan_conf);
+
+	eint_chan_conf.gpio_pin           = USB_ID_PIN;
+	eint_chan_conf.gpio_pin_mux       = USB_ID_EIC_MUX;
+	eint_chan_conf.detection_criteria = EXTINT_DETECT_BOTH;
+	eint_chan_conf.filter_input_signal = true;
+
+	extint_chan_disable_callback(USB_ID_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+	extint_chan_set_config(USB_ID_EIC_LINE, &eint_chan_conf);
+	extint_register_callback(usb_id_handler,
+			USB_ID_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+	extint_chan_enable_callback(USB_ID_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+}
+
+/**
+ * USB ID pin change handler
+ */
+static void usb_id_handler(void)
+{
+	extint_chan_disable_callback(USB_ID_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+	if (_usb_is_id_device()) {
+		uhc_stop(false);
+		UHC_MODE_CHANGE(false);
+		udc_start();
+	} else {
+		udc_stop();
+		UHC_MODE_CHANGE(true);
+		uhc_start();
+	}
+	extint_chan_enable_callback(USB_ID_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+}
+#endif
+/** @} */
+
+/**
+ * \brief Initialize the USB peripheral and set right role according to ID pin
+ *
+ * \return \c true if the ID pin management has been started, otherwise \c false.
+ */
+bool usb_dual_enable(void)
+{
+	if (_initialized) {
+		return false; // Dual role already initialized
+	}
+
+#if USB_ID_EIC
+	_initialized = true;
+
+	struct port_config pin_conf;
+	port_get_config_defaults(&pin_conf);
+
+	/* Set USB ID Pin as inputs */
+	pin_conf.direction  = PORT_PIN_DIR_INPUT;
+	pin_conf.input_pull = PORT_PIN_PULL_UP;
+	port_pin_set_config(USB_ID_PIN, &pin_conf);
+
+	usb_id_config();
+	if (_usb_is_id_device()) {
+		UHC_MODE_CHANGE(false);
+		udc_start();
+	} else {
+		UHC_MODE_CHANGE(true);
+		uhc_start();
+	}
+
+	/**
+	 * End of host or device startup,
+	 * the current mode selected is already started now
+	 */
+	return true; // ID pin management has been enabled
+#else
+	return false; // ID pin management has not been enabled
+#endif
+}
+
+/**
+ * \brief Deinitialize the dual role driver
+ */
+void usb_dual_disable(void)
+{
+	if (!_initialized) {
+		return; // Dual role not initialized
+	}
+	_initialized = false;
+
+#if USB_ID_EIC
+	extint_chan_disable_callback(USB_ID_EIC_LINE,
+			EXTINT_CALLBACK_TYPE_DETECT);
+#endif
+}
+

asf/sam0/drivers/usb/stack_interface/usb_dual.h

@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief SAM USB Dual Role driver header file.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _USB_DUAL_H_
+#define _USB_DUAL_H_
+
+#include "compiler.h"
+#include "preprocessor.h"
+
+/* Get USB pads pins configuration in board configuration */
+#include "conf_board.h"
+#include "board.h"
+#include "extint.h"
+#include "port.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup usb_group
+ * \defgroup usb_dual_group USB dual role driver
+ * USB low-level driver for dual role features
+ *
+ * @{
+ */
+
+bool usb_dual_enable(void);
+void usb_dual_disable(void);
+
+/**
+ * @name USB ID pin management
+ *
+ * The ID pin come from the USB connector (A and B receptable) and
+ * allows to select the USB mode between host or device.
+ * The ID pin can be managed through EIC pin.
+ * This feature is optional, and it is enabled if USB_ID_PIN
+ * is defined in board.h and CONF_BOARD_USB_ID_DETECT defined in
+ * conf_board.h.
+*
+* @{
+*/
+#define USB_ID_DETECT        (defined(CONF_BOARD_USB_ID_DETECT))
+#define USB_ID_EIC           (defined(USB_ID_PIN) && USB_ID_DETECT)
+/** @} */
+
+/**
+ * @name USB Vbus management
+ *
+ * The VBus line can be monitored through a EIC pin and
+ * a basic resistor voltage divider.
+ * This feature is optional, and it is enabled if USB_VBUS_PIN
+ * is defined in board.h and CONF_BOARD_USB_VBUS_DETECT defined in
+ * conf_board.h.
+ *
+ * @{
+ */
+#define USB_VBUS_DETECT      (defined(CONF_BOARD_USB_VBUS_DETECT))
+#define USB_VBUS_EIC         (defined(USB_VBUS_PIN) && USB_VBUS_DETECT)
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _USB_DUAL_H_

asf/sam0/drivers/usb/usb.h

@@ -0,0 +1,833 @@
+/**
+ * \file
+ *
+ * \brief SAM USB Driver
+ *
+ * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef USB_H_INCLUDED
+#define USB_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+#include <pinmux.h>
+#include <system_interrupt.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_usb_group SAM Universal Serial Bus (USB)
+ *
+ * The Universal Serial Bus (USB) module complies with the USB 2.1 specification.
+ *
+ * The following peripherals are used by this module:
+ *  - USB (Universal Serial Bus)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D11 (Only USB device support on SAM D11 device)
+ *  - Atmel | SMART SAM L21
+ *  - Atmel | SMART SAM L22 (Only USB device support on SAM L22 device)
+ *  - Atmel | SMART SAM DA1
+ *
+ * The USB module covers following mode:
+ * \if USB_DEVICE_MODE
+ *  - USB Device Mode
+ * \endif
+ * \if USB_HOST_MODE
+ *  - USB Host Mode
+ * \endif
+ *
+ * The USB module covers following speed:
+ * \if USB_HS_MODE
+ *  - USB High Speed (480Mbit/s)
+ * \endif
+ *  - USB Full Speed (12Mbit/s)
+ * \if USB_LS_MODE
+ *  - USB Low Speed (1.5Mbit/s)
+ * \endif
+ *
+ * \if USB_LPM_MODE
+ * The USB module supports Link Power Management (LPM-L1) protocol.
+ * \endif
+ *
+ * USB support needs whole set of enumeration process, to make the device
+ * recognizable and usable. The USB driver is designed to interface to the
+ * USB Stack in Atmel Software Framework (ASF).
+ *
+ * \if USB_DEVICE_MODE
+ * \section asfdoc_sam0_usb_device USB Device Mode
+ * The ASF USB Device Stack has defined the USB Device Driver (UDD) interface,
+ * to support USB device operations. The USB module device driver complies with
+ * this interface, so that the USB Device Stack can work based on the
+ * USB module.
+ *
+ * Refer to <a href="http://www.atmel.com/images/doc8360.pdf">
+ * "ASF - USB Device Stack"</a> for more details.
+ * \endif
+ *
+ * \if USB_HOST_MODE
+ * \section adfdoc_sam0_usb_host USB Host Mode
+ * The ASF USB Host Stack has defined the USB Host Driver (UHD) interface,
+ * to support USB host operations. The USB module host driver complies with
+ * this interface, so that the USB Host Stack can work based on the USB module.
+ *
+ * Refer to <a href="http://www.atmel.com/images/doc8486.pdf">
+ * "ASF - USB Host Stack"</a> for more details.
+ * \endif
+ */
+
+/** Enum for the speed status for the USB module */
+enum usb_speed {
+	USB_SPEED_LOW,
+	USB_SPEED_FULL,
+};
+
+/** Enum for the possible callback types for the USB in host module */
+enum usb_host_callback {
+	USB_HOST_CALLBACK_SOF,
+	USB_HOST_CALLBACK_RESET,
+	USB_HOST_CALLBACK_WAKEUP,
+	USB_HOST_CALLBACK_DNRSM,
+	USB_HOST_CALLBACK_UPRSM,
+	USB_HOST_CALLBACK_RAMACER,
+	USB_HOST_CALLBACK_CONNECT,
+	USB_HOST_CALLBACK_DISCONNECT,
+	USB_HOST_CALLBACK_N,
+};
+
+/** Enum for the possible callback types for the USB pipe in host module */
+enum usb_host_pipe_callback {
+	USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE,
+	USB_HOST_PIPE_CALLBACK_ERROR,
+	USB_HOST_PIPE_CALLBACK_SETUP,
+	USB_HOST_PIPE_CALLBACK_STALL,
+	USB_HOST_PIPE_CALLBACK_N,
+};
+
+/**
+ * \brief Host pipe types.
+ */
+enum usb_host_pipe_type {
+	USB_HOST_PIPE_TYPE_DISABLE,
+	USB_HOST_PIPE_TYPE_CONTROL,
+	USB_HOST_PIPE_TYPE_ISO,
+	USB_HOST_PIPE_TYPE_BULK,
+	USB_HOST_PIPE_TYPE_INTERRUPT,
+	USB_HOST_PIPE_TYPE_EXTENDED,
+};
+
+/**
+ * \brief Host pipe token types.
+ */
+enum usb_host_pipe_token {
+	USB_HOST_PIPE_TOKEN_SETUP,
+	USB_HOST_PIPE_TOKEN_IN,
+	USB_HOST_PIPE_TOKEN_OUT,
+};
+
+/**
+ * \brief Enumeration for the possible callback types for the USB in device module
+ */
+enum usb_device_callback {
+	USB_DEVICE_CALLBACK_SOF,
+	USB_DEVICE_CALLBACK_RESET,
+	USB_DEVICE_CALLBACK_WAKEUP,
+	USB_DEVICE_CALLBACK_RAMACER,
+	USB_DEVICE_CALLBACK_SUSPEND,
+	USB_DEVICE_CALLBACK_LPMNYET,
+	USB_DEVICE_CALLBACK_LPMSUSP,
+	USB_DEVICE_CALLBACK_N,
+};
+
+/**
+ * \brief Enumeration for the possible callback types for the USB endpoint in device module
+ */
+enum usb_device_endpoint_callback {
+	USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,
+	USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL,
+	USB_DEVICE_ENDPOINT_CALLBACK_RXSTP,
+	USB_DEVICE_ENDPOINT_CALLBACK_STALL,
+	USB_DEVICE_EP_CALLBACK_N,
+};
+
+/**
+ * \brief Device Endpoint types.
+ */
+enum usb_device_endpoint_type {
+	USB_DEVICE_ENDPOINT_TYPE_DISABLE,
+	USB_DEVICE_ENDPOINT_TYPE_CONTROL,
+	USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS,
+	USB_DEVICE_ENDPOINT_TYPE_BULK,
+	USB_DEVICE_ENDPOINT_TYPE_INTERRUPT,
+};
+
+/**
+ * \brief Endpoint Size
+ */
+enum usb_endpoint_size {
+	USB_ENDPOINT_8_BYTE,
+	USB_ENDPOINT_16_BYTE,
+	USB_ENDPOINT_32_BYTE,
+    USB_ENDPOINT_64_BYTE,
+	USB_ENDPOINT_128_BYTE,
+	USB_ENDPOINT_256_BYTE,
+	USB_ENDPOINT_512_BYTE,
+	USB_ENDPOINT_1023_BYTE,
+};
+
+/**
+ * \brief Link Power Management Handshake.
+ */
+enum usb_device_lpm_mode {
+	USB_DEVICE_LPM_NOT_SUPPORT,
+	USB_DEVICE_LPM_ACK,
+	USB_DEVICE_LPM_NYET,
+};
+
+/**
+ * \brief Module structure
+ */
+struct usb_module;
+
+/**
+ * \name Host Callback Functions Types
+ * @{
+ */
+typedef void (*usb_host_callback_t)(struct usb_module *module_inst);
+typedef void (*usb_host_pipe_callback_t)(struct usb_module *module_inst, void *);
+/** @} */
+
+/**
+ * \name Device Callback Functions Types
+ * @{
+ */
+typedef void (*usb_device_callback_t)(struct usb_module *module_inst, void* pointer);
+typedef void (*usb_device_endpoint_callback_t)(struct usb_module *module_inst, void* pointer);
+/** @} */
+
+
+/** USB configurations */
+struct usb_config {
+	/** \c true for host, \c false for device. */
+	bool select_host_mode;
+	/** When \c true the module is enabled during standby. */
+	bool run_in_standby;
+	/** Generic Clock Generator source channel. */
+	enum gclk_generator source_generator;
+	/** Speed mode */
+	enum usb_speed speed_mode;
+};
+
+/**
+ * \brief USB software module instance structure.
+ *
+ * USB software module instance structure, used to retain software state
+ * information of an associated hardware module instance.
+ *
+ */
+struct usb_module {
+	/** Hardware module pointer of the associated USB peripheral. */
+	Usb *hw;
+
+#if !SAMD11 && !SAML22
+	/** Array to store host related callback functions */
+	usb_host_callback_t host_callback[USB_HOST_CALLBACK_N];
+	usb_host_pipe_callback_t host_pipe_callback[USB_PIPE_NUM][USB_HOST_PIPE_CALLBACK_N];
+	/** Bit mask for host callbacks registered */
+	uint8_t host_registered_callback_mask;
+	/** Bit mask for host callbacks enabled */
+	uint8_t host_enabled_callback_mask;
+	/** Bit mask for host pipe callbacks registered */
+	uint8_t host_pipe_registered_callback_mask[USB_PIPE_NUM];
+	/** Bit mask for host pipe callbacks enabled */
+	uint8_t host_pipe_enabled_callback_mask[USB_PIPE_NUM];
+#endif
+
+	/** Array to store device related callback functions */
+	usb_device_callback_t device_callback[USB_DEVICE_CALLBACK_N];
+	usb_device_endpoint_callback_t device_endpoint_callback[USB_EPT_NUM][USB_DEVICE_EP_CALLBACK_N];
+	/** Bit mask for device callbacks registered */
+	uint16_t device_registered_callback_mask;
+	/** Bit mask for device callbacks enabled */
+	uint16_t device_enabled_callback_mask;
+	/** Bit mask for device endpoint callbacks registered */
+	uint8_t device_endpoint_registered_callback_mask[USB_EPT_NUM];
+	/** Bit mask for device endpoint callbacks enabled */
+	uint8_t device_endpoint_enabled_callback_mask[USB_EPT_NUM];
+};
+
+/** USB host pipe configurations */
+struct usb_host_pipe_config {
+	/** device address */
+	uint8_t device_address;
+	/** endpoint address  */
+	uint8_t endpoint_address;
+	/** Pipe type */
+	enum usb_host_pipe_type pipe_type;
+	/** interval */
+	uint8_t binterval;
+	/** pipe size */
+	uint16_t size;
+};
+
+/** USB device endpoint configurations */
+struct usb_device_endpoint_config {
+	/** device address */
+	uint8_t ep_address;
+	/** endpoint size */
+	enum usb_endpoint_size ep_size;
+	/** automatic zero length packet mode, \c true to enable */
+	bool auto_zlp;
+	/** type of endpoint with Bank */
+	enum usb_device_endpoint_type ep_type;
+};
+
+/** USB host pipe callback status parameter structure */
+struct usb_pipe_callback_parameter {
+	/** current pipe number */
+	uint8_t pipe_num;
+	/** pipe error status */
+	uint8_t pipe_error_status;
+	/** actual transferred data size */
+	uint16_t transfered_size;
+	/** required data size */
+	uint16_t required_size;
+};
+
+/** USB device endpoint callback status parameter structure */
+struct usb_endpoint_callback_parameter {
+	uint16_t received_bytes;
+	uint16_t sent_bytes;
+	uint16_t out_buffer_size;
+	uint8_t endpoint_address;
+};
+
+void usb_enable(struct usb_module *module_inst);
+void usb_disable(struct usb_module *module_inst);
+
+/**
+ * \brief Get the status of USB module's state machine
+ *
+ * \param module_inst Pointer to USB module instance
+ */
+static inline uint8_t usb_get_state_machine_status(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	return module_inst->hw->DEVICE.FSMSTATUS.reg;
+}
+
+void usb_get_config_defaults(struct usb_config *module_config);
+enum status_code usb_init(struct usb_module *module_inst, Usb *const hw,
+		struct usb_config *module_config);
+
+#if !SAMD11 && !SAML22
+/**
+ * \brief Enable the USB host by setting the VBUS OK
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_enable(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.CTRLB.bit.VBUSOK = 1;
+}
+
+/**
+ * \brief Send the USB reset
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_send_reset(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.CTRLB.bit.BUSRESET = 1;
+}
+
+/**
+ * \brief Enable the USB SOF generation
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_enable_sof(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.CTRLB.bit.SOFE = 1;
+}
+
+/**
+ * \brief Disable the USB SOF generation
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_disable_sof(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.CTRLB.bit.SOFE = 0;
+}
+
+/**
+ * \brief Check the USB SOF generation status
+ *
+ * \param module_inst Pointer to USB software instance struct
+ *
+ * \return USB SOF generation status, \c true if SOF generation is ON.
+ */
+static inline bool usb_host_is_sof_enabled(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	return module_inst->hw->HOST.CTRLB.bit.SOFE;
+}
+
+/**
+ * \brief Send the USB host resume
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_send_resume(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.CTRLB.bit.RESUME= 1;
+}
+
+/**
+ * \brief Send the USB host LPM resume
+ *
+ * \param module_inst Pointer to USB software instance struct
+ */
+static inline void usb_host_send_l1_resume(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.CTRLB.bit.L1RESUME = 1;
+}
+
+/**
+ * \brief Get the speed mode of USB host
+ *
+ * \param module_inst Pointer to USB module instance struct
+ *
+ * \return USB speed mode (\ref usb_speed).
+ */
+static inline enum usb_speed usb_host_get_speed(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	if (module_inst->hw->HOST.STATUS.bit.SPEED == 0) {
+		return USB_SPEED_FULL;
+	} else {
+		return USB_SPEED_LOW;
+	}
+}
+
+/**
+ * \brief Get the frame number
+ *
+ * \param module_inst Pointer to USB software instance struct
+ *
+ * \return frame number value.
+ */
+static inline uint16_t usb_host_get_frame_number(struct usb_module *module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	return (uint16_t)(module_inst->hw->HOST.FNUM.bit.FNUM);
+}
+#endif
+
+/**
+ * \brief Attach USB device to the bus
+ *
+ * \param module_inst Pointer to USB device module instance
+ */
+static inline void usb_device_attach(struct usb_module *module_inst)
+{
+	module_inst->hw->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
+}
+
+/**
+ * \brief Detach USB device from the bus
+ *
+ * \param module_inst Pointer to USB device module instance
+ */
+static inline void usb_device_detach(struct usb_module *module_inst)
+{
+	module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH;
+}
+
+/**
+ * \brief Get the speed mode of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \return USB Speed mode (\ref usb_speed).
+ */
+static inline enum usb_speed usb_device_get_speed(struct usb_module *module_inst)
+{
+	if (!(module_inst->hw->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk)) {
+		return USB_SPEED_FULL;
+	} else {
+		return USB_SPEED_LOW;
+	}
+}
+
+/**
+ * \brief Get the address of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \return USB device address value.
+ */
+static inline uint8_t usb_device_get_address(struct usb_module *module_inst)
+{
+	return ((uint8_t)(module_inst->hw->DEVICE.DADD.bit.DADD));
+}
+
+/**
+ * \brief Set the speed mode of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \param address     USB device address value
+ */
+static inline void usb_device_set_address(struct usb_module *module_inst, uint8_t address)
+{
+	module_inst->hw->DEVICE.DADD.reg = USB_DEVICE_DADD_ADDEN | address;
+}
+
+/**
+ * \brief Get the frame number of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \return USB device frame number value.
+ */
+static inline uint16_t usb_device_get_frame_number(struct usb_module *module_inst)
+{
+	return ((uint16_t)(module_inst->hw->DEVICE.FNUM.bit.FNUM));
+}
+
+/**
+ * \brief Get the micro-frame number of USB device
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \return USB device micro-frame number value.
+ */
+static inline uint16_t usb_device_get_micro_frame_number(struct usb_module *module_inst)
+{
+	return ((uint16_t)(module_inst->hw->DEVICE.FNUM.reg));
+}
+
+/**
+ * \brief USB device send the resume wakeup
+ *
+ * \param module_inst Pointer to USB device module instance
+ */
+static inline void usb_device_send_remote_wake_up(struct usb_module *module_inst)
+{
+	module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM;
+}
+
+/**
+ * \brief USB device set the LPM mode
+ *
+ * \param module_inst Pointer to USB device module instance
+ * \param lpm_mode    LPM mode
+ */
+static inline void usb_device_set_lpm_mode(struct usb_module *module_inst,
+		enum usb_device_lpm_mode lpm_mode)
+{
+	module_inst->hw->DEVICE.CTRLB.bit.LPMHDSK = lpm_mode;
+}
+
+/**
+ * \name USB Host Callback Management
+ * @{
+ */
+enum status_code usb_host_register_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type,
+		usb_host_callback_t callback_func);
+enum status_code usb_host_unregister_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type);
+enum status_code usb_host_enable_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type);
+enum status_code usb_host_disable_callback(struct usb_module *module_inst,
+		enum usb_host_callback callback_type);
+/** @} */
+
+/**
+ * \name USB Device Callback Management
+ * @{
+ */
+enum status_code usb_device_register_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type,
+		usb_device_callback_t callback_func);
+enum status_code usb_device_unregister_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type);
+enum status_code usb_device_enable_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type);
+enum status_code usb_device_disable_callback(struct usb_module *module_inst,
+		enum usb_device_callback callback_type);
+/** @} */
+
+/**
+ * \name USB Host Pipe Configuration
+ * @{
+ */
+void usb_host_pipe_get_config_defaults(struct usb_host_pipe_config *ep_config);
+enum status_code usb_host_pipe_set_config(struct usb_module *module_inst, uint8_t pipe_num,
+		struct usb_host_pipe_config *ep_config);
+enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_t pipe_num,
+		struct usb_host_pipe_config *ep_config);
+/** @} */
+
+/**
+ * \name USB Device Endpoint Configuration
+ * @{
+ */
+void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *ep_config);
+enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst,
+		struct usb_device_endpoint_config *ep_config);
+bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t ep);
+/** @} */
+
+/**
+ * \name USB Host Pipe Callback Management
+ * @{
+ */
+enum status_code usb_host_pipe_register_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type,
+		usb_host_pipe_callback_t callback_func);
+enum status_code usb_host_pipe_unregister_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type);
+enum status_code usb_host_pipe_enable_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type);
+enum status_code usb_host_pipe_disable_callback(
+		struct usb_module *module_inst, uint8_t pipe_num,
+		enum usb_host_pipe_callback callback_type);
+/** @} */
+
+/**
+ * \name USB Device Endpoint Callback Management
+ * @{
+ */
+enum status_code usb_device_endpoint_register_callback(
+		struct usb_module *module_inst, uint8_t ep_num,
+		enum usb_device_endpoint_callback callback_type,
+		usb_device_endpoint_callback_t callback_func);
+enum status_code usb_device_endpoint_unregister_callback(
+		struct usb_module *module_inst, uint8_t ep_num,
+		enum usb_device_endpoint_callback callback_type);
+enum status_code usb_device_endpoint_enable_callback(
+		struct usb_module *module_inst, uint8_t ep,
+		enum usb_device_endpoint_callback callback_type);
+enum status_code usb_device_endpoint_disable_callback(
+		struct usb_module *module_inst, uint8_t ep,
+		enum usb_device_endpoint_callback callback_type);
+/** @} */
+
+/**
+ * \name USB Host Pipe Job Management
+ * @{
+ */
+enum status_code usb_host_pipe_setup_job(struct usb_module *module_inst,
+		uint8_t pipe_num, uint8_t *buf);
+enum status_code usb_host_pipe_read_job(struct usb_module *module_inst,
+		uint8_t pipe_num, uint8_t *buf, uint32_t buf_size);
+enum status_code usb_host_pipe_write_job(struct usb_module *module_inst,
+		uint8_t pipe_num, uint8_t *buf, uint32_t buf_size);
+enum status_code usb_host_pipe_abort_job(struct usb_module *module_inst, uint8_t pipe_num);
+enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst,
+		uint8_t pipe_num, bool b_remotewakeup, uint8_t hird);
+/** @} */
+
+/**
+ * \name USB Device Endpoint Job Management
+ * @{
+ */
+enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
+		uint8_t* pbuf, uint32_t buf_size);
+enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
+		uint8_t* pbuf, uint32_t buf_size);
+enum status_code usb_device_endpoint_setup_buffer_job(struct usb_module *module_inst,
+		uint8_t* pbuf);
+void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep);
+/** @} */
+
+#if !SAMD11 && !SAML22
+/**
+ * \name USB Host Pipe Operations
+ * @{
+ */
+
+/**
+ * \brief Freeze a pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num    Pipe number
+ */
+static inline void usb_host_pipe_freeze(struct usb_module *module_inst, uint8_t pipe_num)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
+}
+
+/**
+ * \brief Unfreeze a pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num    Pipe number
+ */
+static inline void usb_host_pipe_unfreeze(struct usb_module *module_inst, uint8_t pipe_num)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE;
+}
+
+/**
+ * \brief Check if the pipe is frozen
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num    Pipe number
+ */
+static inline bool usb_host_pipe_is_frozen(struct usb_module *module_inst, uint8_t pipe_num)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	return (module_inst->hw->HOST.HostPipe[pipe_num].PSTATUS.bit.PFREEZE == 1);
+}
+
+/**
+ * \brief Set the data toggle bit of pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num    Pipe number
+ */
+static inline void usb_host_pipe_set_toggle(struct usb_module *module_inst, uint8_t pipe_num)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_DTGL;
+}
+
+/**
+ * \brief Clear the data toggle bit of pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num    Pipe number
+ */
+static inline void usb_host_pipe_clear_toggle(struct usb_module *module_inst, uint8_t pipe_num)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_DTGL;
+}
+
+/**
+ * \brief Set the auto zero length packet of pipe
+ *
+ * \param module_inst Pointer to USB module instance
+ * \param pipe_num    Pipe number
+ * \param value       \c true to enable auto ZLP and \c false to disable
+ */
+void usb_host_pipe_set_auto_zlp(struct usb_module *module_inst, uint8_t pipe_num, bool value);
+
+/** @} */
+#endif
+
+/**
+ * \name USB Device Endpoint Operations
+ * @{
+ */
+
+bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep);
+void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep);
+void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB_H_INCLUDED */

asf/sam0/utils/cmsis/samd21/include/component/ac.h

@@ -3,24 +3,39 @@
  *
  * \brief Component description for AC
  *
- * Copyright (c) 2017 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *
  * \asf_license_stop
  *
@@ -53,18 +68,18 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define AC_CTRLA_OFFSET             0x00         /**< \brief (AC_CTRLA offset) Control A */
-#define AC_CTRLA_RESETVALUE         _U(0x00)     /**< \brief (AC_CTRLA reset_value) Control A */
+#define AC_CTRLA_RESETVALUE         0x00ul       /**< \brief (AC_CTRLA reset_value) Control A */
 
 #define AC_CTRLA_SWRST_Pos          0            /**< \brief (AC_CTRLA) Software Reset */
-#define AC_CTRLA_SWRST              (_U(0x1) << AC_CTRLA_SWRST_Pos)
+#define AC_CTRLA_SWRST              (0x1ul << AC_CTRLA_SWRST_Pos)
 #define AC_CTRLA_ENABLE_Pos         1            /**< \brief (AC_CTRLA) Enable */
-#define AC_CTRLA_ENABLE             (_U(0x1) << AC_CTRLA_ENABLE_Pos)
+#define AC_CTRLA_ENABLE             (0x1ul << AC_CTRLA_ENABLE_Pos)
 #define AC_CTRLA_RUNSTDBY_Pos       2            /**< \brief (AC_CTRLA) Run in Standby */
-#define AC_CTRLA_RUNSTDBY_Msk       (_U(0x1) << AC_CTRLA_RUNSTDBY_Pos)
+#define AC_CTRLA_RUNSTDBY_Msk       (0x1ul << AC_CTRLA_RUNSTDBY_Pos)
 #define AC_CTRLA_RUNSTDBY(value)    (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos))
 #define AC_CTRLA_LPMUX_Pos          7            /**< \brief (AC_CTRLA) Low-Power Mux */
-#define AC_CTRLA_LPMUX              (_U(0x1) << AC_CTRLA_LPMUX_Pos)
-#define AC_CTRLA_MASK               _U(0x87)     /**< \brief (AC_CTRLA) MASK Register */
+#define AC_CTRLA_LPMUX              (0x1ul << AC_CTRLA_LPMUX_Pos)
+#define AC_CTRLA_MASK               0x87ul       /**< \brief (AC_CTRLA) MASK Register */
 
 /* -------- AC_CTRLB : (AC Offset: 0x01) ( /W  8) Control B -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -83,16 +98,16 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define AC_CTRLB_OFFSET             0x01         /**< \brief (AC_CTRLB offset) Control B */
-#define AC_CTRLB_RESETVALUE         _U(0x00)     /**< \brief (AC_CTRLB reset_value) Control B */
+#define AC_CTRLB_RESETVALUE         0x00ul       /**< \brief (AC_CTRLB reset_value) Control B */
 
 #define AC_CTRLB_START0_Pos         0            /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
 #define AC_CTRLB_START0             (1 << AC_CTRLB_START0_Pos)
 #define AC_CTRLB_START1_Pos         1            /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
 #define AC_CTRLB_START1             (1 << AC_CTRLB_START1_Pos)
 #define AC_CTRLB_START_Pos          0            /**< \brief (AC_CTRLB) Comparator x Start Comparison */
-#define AC_CTRLB_START_Msk          (_U(0x3) << AC_CTRLB_START_Pos)
+#define AC_CTRLB_START_Msk          (0x3ul << AC_CTRLB_START_Pos)
 #define AC_CTRLB_START(value)       (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
-#define AC_CTRLB_MASK               _U(0x03)     /**< \brief (AC_CTRLB) MASK Register */
+#define AC_CTRLB_MASK               0x03ul       /**< \brief (AC_CTRLB) MASK Register */
 
 /* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -120,28 +135,28 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define AC_EVCTRL_OFFSET            0x02         /**< \brief (AC_EVCTRL offset) Event Control */
-#define AC_EVCTRL_RESETVALUE        _U(0x0000)   /**< \brief (AC_EVCTRL reset_value) Event Control */
+#define AC_EVCTRL_RESETVALUE        0x0000ul     /**< \brief (AC_EVCTRL reset_value) Event Control */
 
 #define AC_EVCTRL_COMPEO0_Pos       0            /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
 #define AC_EVCTRL_COMPEO0           (1 << AC_EVCTRL_COMPEO0_Pos)
 #define AC_EVCTRL_COMPEO1_Pos       1            /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
 #define AC_EVCTRL_COMPEO1           (1 << AC_EVCTRL_COMPEO1_Pos)
 #define AC_EVCTRL_COMPEO_Pos        0            /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
-#define AC_EVCTRL_COMPEO_Msk        (_U(0x3) << AC_EVCTRL_COMPEO_Pos)
+#define AC_EVCTRL_COMPEO_Msk        (0x3ul << AC_EVCTRL_COMPEO_Pos)
 #define AC_EVCTRL_COMPEO(value)     (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
 #define AC_EVCTRL_WINEO0_Pos        4            /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
 #define AC_EVCTRL_WINEO0            (1 << AC_EVCTRL_WINEO0_Pos)
 #define AC_EVCTRL_WINEO_Pos         4            /**< \brief (AC_EVCTRL) Window x Event Output Enable */
-#define AC_EVCTRL_WINEO_Msk         (_U(0x1) << AC_EVCTRL_WINEO_Pos)
+#define AC_EVCTRL_WINEO_Msk         (0x1ul << AC_EVCTRL_WINEO_Pos)
 #define AC_EVCTRL_WINEO(value)      (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
 #define AC_EVCTRL_COMPEI0_Pos       8            /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
 #define AC_EVCTRL_COMPEI0           (1 << AC_EVCTRL_COMPEI0_Pos)
 #define AC_EVCTRL_COMPEI1_Pos       9            /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
 #define AC_EVCTRL_COMPEI1           (1 << AC_EVCTRL_COMPEI1_Pos)
 #define AC_EVCTRL_COMPEI_Pos        8            /**< \brief (AC_EVCTRL) Comparator x Event Input */
-#define AC_EVCTRL_COMPEI_Msk        (_U(0x3) << AC_EVCTRL_COMPEI_Pos)
+#define AC_EVCTRL_COMPEI_Msk        (0x3ul << AC_EVCTRL_COMPEI_Pos)
 #define AC_EVCTRL_COMPEI(value)     (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
-#define AC_EVCTRL_MASK              _U(0x0313)   /**< \brief (AC_EVCTRL) MASK Register */
+#define AC_EVCTRL_MASK              0x0313ul     /**< \brief (AC_EVCTRL) MASK Register */
 
 /* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -164,21 +179,21 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define AC_INTENCLR_OFFSET          0x04         /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
-#define AC_INTENCLR_RESETVALUE      _U(0x00)     /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
+#define AC_INTENCLR_RESETVALUE      0x00ul       /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
 
 #define AC_INTENCLR_COMP0_Pos       0            /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
 #define AC_INTENCLR_COMP0           (1 << AC_INTENCLR_COMP0_Pos)
 #define AC_INTENCLR_COMP1_Pos       1            /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
 #define AC_INTENCLR_COMP1           (1 << AC_INTENCLR_COMP1_Pos)
 #define AC_INTENCLR_COMP_Pos        0            /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
-#define AC_INTENCLR_COMP_Msk        (_U(0x3) << AC_INTENCLR_COMP_Pos)
+#define AC_INTENCLR_COMP_Msk        (0x3ul << AC_INTENCLR_COMP_Pos)
 #define AC_INTENCLR_COMP(value)     (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
 #define AC_INTENCLR_WIN0_Pos        4            /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
 #define AC_INTENCLR_WIN0            (1 << AC_INTENCLR_WIN0_Pos)
 #define AC_INTENCLR_WIN_Pos         4            /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
-#define AC_INTENCLR_WIN_Msk         (_U(0x1) << AC_INTENCLR_WIN_Pos)
+#define AC_INTENCLR_WIN_Msk         (0x1ul << AC_INTENCLR_WIN_Pos)
 #define AC_INTENCLR_WIN(value)      (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
-#define AC_INTENCLR_MASK            _U(0x13)     /**< \brief (AC_INTENCLR) MASK Register */
+#define AC_INTENCLR_MASK            0x13ul       /**< \brief (AC_INTENCLR) MASK Register */
 
 /* -------- AC_INTENSET : (AC Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -201,21 +216,21 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define AC_INTENSET_OFFSET          0x05         /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
-#define AC_INTENSET_RESETVALUE      _U(0x00)     /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
+#define AC_INTENSET_RESETVALUE      0x00ul       /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
 
 #define AC_INTENSET_COMP0_Pos       0            /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
 #define AC_INTENSET_COMP0           (1 << AC_INTENSET_COMP0_Pos)
 #define AC_INTENSET_COMP1_Pos       1            /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
 #define AC_INTENSET_COMP1           (1 << AC_INTENSET_COMP1_Pos)
 #define AC_INTENSET_COMP_Pos        0            /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
-#define AC_INTENSET_COMP_Msk        (_U(0x3) << AC_INTENSET_COMP_Pos)
+#define AC_INTENSET_COMP_Msk        (0x3ul << AC_INTENSET_COMP_Pos)
 #define AC_INTENSET_COMP(value)     (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
 #define AC_INTENSET_WIN0_Pos        4            /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
 #define AC_INTENSET_WIN0            (1 << AC_INTENSET_WIN0_Pos)
 #define AC_INTENSET_WIN_Pos         4            /**< \brief (AC_INTENSET) Window x Interrupt Enable */
-#define AC_INTENSET_WIN_Msk         (_U(0x1) << AC_INTENSET_WIN_Pos)
+#define AC_INTENSET_WIN_Msk         (0x1ul << AC_INTENSET_WIN_Pos)
 #define AC_INTENSET_WIN(value)      (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
-#define AC_INTENSET_MASK            _U(0x13)     /**< \brief (AC_INTENSET) MASK Register */
+#define AC_INTENSET_MASK            0x13ul       /**< \brief (AC_INTENSET) MASK Register */
 
 /* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -238,21 +253,21 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define AC_INTFLAG_OFFSET           0x06         /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define AC_INTFLAG_RESETVALUE       _U(0x00)     /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+#define AC_INTFLAG_RESETVALUE       0x00ul       /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
 
 #define AC_INTFLAG_COMP0_Pos        0            /**< \brief (AC_INTFLAG) Comparator 0 */
 #define AC_INTFLAG_COMP0            (1 << AC_INTFLAG_COMP0_Pos)
 #define AC_INTFLAG_COMP1_Pos        1            /**< \brief (AC_INTFLAG) Comparator 1 */
 #define AC_INTFLAG_COMP1            (1 << AC_INTFLAG_COMP1_Pos)
 #define AC_INTFLAG_COMP_Pos         0            /**< \brief (AC_INTFLAG) Comparator x */
-#define AC_INTFLAG_COMP_Msk         (_U(0x3) << AC_INTFLAG_COMP_Pos)
+#define AC_INTFLAG_COMP_Msk         (0x3ul << AC_INTFLAG_COMP_Pos)
 #define AC_INTFLAG_COMP(value)      (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
 #define AC_INTFLAG_WIN0_Pos         4            /**< \brief (AC_INTFLAG) Window 0 */
 #define AC_INTFLAG_WIN0             (1 << AC_INTFLAG_WIN0_Pos)
 #define AC_INTFLAG_WIN_Pos          4            /**< \brief (AC_INTFLAG) Window x */
-#define AC_INTFLAG_WIN_Msk          (_U(0x1) << AC_INTFLAG_WIN_Pos)
+#define AC_INTFLAG_WIN_Msk          (0x1ul << AC_INTFLAG_WIN_Pos)
 #define AC_INTFLAG_WIN(value)       (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
-#define AC_INTFLAG_MASK             _U(0x13)     /**< \brief (AC_INTFLAG) MASK Register */
+#define AC_INTFLAG_MASK             0x13ul       /**< \brief (AC_INTFLAG) MASK Register */
 
 /* -------- AC_STATUSA : (AC Offset: 0x08) (R/   8) Status A -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -273,25 +288,25 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define AC_STATUSA_OFFSET           0x08         /**< \brief (AC_STATUSA offset) Status A */
-#define AC_STATUSA_RESETVALUE       _U(0x00)     /**< \brief (AC_STATUSA reset_value) Status A */
+#define AC_STATUSA_RESETVALUE       0x00ul       /**< \brief (AC_STATUSA reset_value) Status A */
 
 #define AC_STATUSA_STATE0_Pos       0            /**< \brief (AC_STATUSA) Comparator 0 Current State */
 #define AC_STATUSA_STATE0           (1 << AC_STATUSA_STATE0_Pos)
 #define AC_STATUSA_STATE1_Pos       1            /**< \brief (AC_STATUSA) Comparator 1 Current State */
 #define AC_STATUSA_STATE1           (1 << AC_STATUSA_STATE1_Pos)
 #define AC_STATUSA_STATE_Pos        0            /**< \brief (AC_STATUSA) Comparator x Current State */
-#define AC_STATUSA_STATE_Msk        (_U(0x3) << AC_STATUSA_STATE_Pos)
+#define AC_STATUSA_STATE_Msk        (0x3ul << AC_STATUSA_STATE_Pos)
 #define AC_STATUSA_STATE(value)     (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
 #define AC_STATUSA_WSTATE0_Pos      4            /**< \brief (AC_STATUSA) Window 0 Current State */
-#define AC_STATUSA_WSTATE0_Msk      (_U(0x3) << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_Msk      (0x3ul << AC_STATUSA_WSTATE0_Pos)
 #define AC_STATUSA_WSTATE0(value)   (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
-#define   AC_STATUSA_WSTATE0_ABOVE_Val    _U(0x0)   /**< \brief (AC_STATUSA) Signal is above window */
-#define   AC_STATUSA_WSTATE0_INSIDE_Val   _U(0x1)   /**< \brief (AC_STATUSA) Signal is inside window */
-#define   AC_STATUSA_WSTATE0_BELOW_Val    _U(0x2)   /**< \brief (AC_STATUSA) Signal is below window */
+#define   AC_STATUSA_WSTATE0_ABOVE_Val    0x0ul  /**< \brief (AC_STATUSA) Signal is above window */
+#define   AC_STATUSA_WSTATE0_INSIDE_Val   0x1ul  /**< \brief (AC_STATUSA) Signal is inside window */
+#define   AC_STATUSA_WSTATE0_BELOW_Val    0x2ul  /**< \brief (AC_STATUSA) Signal is below window */
 #define AC_STATUSA_WSTATE0_ABOVE    (AC_STATUSA_WSTATE0_ABOVE_Val  << AC_STATUSA_WSTATE0_Pos)
 #define AC_STATUSA_WSTATE0_INSIDE   (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
 #define AC_STATUSA_WSTATE0_BELOW    (AC_STATUSA_WSTATE0_BELOW_Val  << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_MASK             _U(0x33)     /**< \brief (AC_STATUSA) MASK Register */
+#define AC_STATUSA_MASK             0x33ul       /**< \brief (AC_STATUSA) MASK Register */
 
 /* -------- AC_STATUSB : (AC Offset: 0x09) (R/   8) Status B -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -311,18 +326,18 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define AC_STATUSB_OFFSET           0x09         /**< \brief (AC_STATUSB offset) Status B */
-#define AC_STATUSB_RESETVALUE       _U(0x00)     /**< \brief (AC_STATUSB reset_value) Status B */
+#define AC_STATUSB_RESETVALUE       0x00ul       /**< \brief (AC_STATUSB reset_value) Status B */
 
 #define AC_STATUSB_READY0_Pos       0            /**< \brief (AC_STATUSB) Comparator 0 Ready */
 #define AC_STATUSB_READY0           (1 << AC_STATUSB_READY0_Pos)
 #define AC_STATUSB_READY1_Pos       1            /**< \brief (AC_STATUSB) Comparator 1 Ready */
 #define AC_STATUSB_READY1           (1 << AC_STATUSB_READY1_Pos)
 #define AC_STATUSB_READY_Pos        0            /**< \brief (AC_STATUSB) Comparator x Ready */
-#define AC_STATUSB_READY_Msk        (_U(0x3) << AC_STATUSB_READY_Pos)
+#define AC_STATUSB_READY_Msk        (0x3ul << AC_STATUSB_READY_Pos)
 #define AC_STATUSB_READY(value)     (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
 #define AC_STATUSB_SYNCBUSY_Pos     7            /**< \brief (AC_STATUSB) Synchronization Busy */
-#define AC_STATUSB_SYNCBUSY         (_U(0x1) << AC_STATUSB_SYNCBUSY_Pos)
-#define AC_STATUSB_MASK             _U(0x83)     /**< \brief (AC_STATUSB) MASK Register */
+#define AC_STATUSB_SYNCBUSY         (0x1ul << AC_STATUSB_SYNCBUSY_Pos)
+#define AC_STATUSB_MASK             0x83ul       /**< \brief (AC_STATUSB) MASK Register */
 
 /* -------- AC_STATUSC : (AC Offset: 0x0A) (R/   8) Status C -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -343,25 +358,25 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define AC_STATUSC_OFFSET           0x0A         /**< \brief (AC_STATUSC offset) Status C */
-#define AC_STATUSC_RESETVALUE       _U(0x00)     /**< \brief (AC_STATUSC reset_value) Status C */
+#define AC_STATUSC_RESETVALUE       0x00ul       /**< \brief (AC_STATUSC reset_value) Status C */
 
 #define AC_STATUSC_STATE0_Pos       0            /**< \brief (AC_STATUSC) Comparator 0 Current State */
 #define AC_STATUSC_STATE0           (1 << AC_STATUSC_STATE0_Pos)
 #define AC_STATUSC_STATE1_Pos       1            /**< \brief (AC_STATUSC) Comparator 1 Current State */
 #define AC_STATUSC_STATE1           (1 << AC_STATUSC_STATE1_Pos)
 #define AC_STATUSC_STATE_Pos        0            /**< \brief (AC_STATUSC) Comparator x Current State */
-#define AC_STATUSC_STATE_Msk        (_U(0x3) << AC_STATUSC_STATE_Pos)
+#define AC_STATUSC_STATE_Msk        (0x3ul << AC_STATUSC_STATE_Pos)
 #define AC_STATUSC_STATE(value)     (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos))
 #define AC_STATUSC_WSTATE0_Pos      4            /**< \brief (AC_STATUSC) Window 0 Current State */
-#define AC_STATUSC_WSTATE0_Msk      (_U(0x3) << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_Msk      (0x3ul << AC_STATUSC_WSTATE0_Pos)
 #define AC_STATUSC_WSTATE0(value)   (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos))
-#define   AC_STATUSC_WSTATE0_ABOVE_Val    _U(0x0)   /**< \brief (AC_STATUSC) Signal is above window */
-#define   AC_STATUSC_WSTATE0_INSIDE_Val   _U(0x1)   /**< \brief (AC_STATUSC) Signal is inside window */
-#define   AC_STATUSC_WSTATE0_BELOW_Val    _U(0x2)   /**< \brief (AC_STATUSC) Signal is below window */
+#define   AC_STATUSC_WSTATE0_ABOVE_Val    0x0ul  /**< \brief (AC_STATUSC) Signal is above window */
+#define   AC_STATUSC_WSTATE0_INSIDE_Val   0x1ul  /**< \brief (AC_STATUSC) Signal is inside window */
+#define   AC_STATUSC_WSTATE0_BELOW_Val    0x2ul  /**< \brief (AC_STATUSC) Signal is below window */
 #define AC_STATUSC_WSTATE0_ABOVE    (AC_STATUSC_WSTATE0_ABOVE_Val  << AC_STATUSC_WSTATE0_Pos)
 #define AC_STATUSC_WSTATE0_INSIDE   (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos)
 #define AC_STATUSC_WSTATE0_BELOW    (AC_STATUSC_WSTATE0_BELOW_Val  << AC_STATUSC_WSTATE0_Pos)
-#define AC_STATUSC_MASK             _U(0x33)     /**< \brief (AC_STATUSC) MASK Register */
+#define AC_STATUSC_MASK             0x33ul       /**< \brief (AC_STATUSC) MASK Register */
 
 /* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W  8) Window Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -376,22 +391,22 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define AC_WINCTRL_OFFSET           0x0C         /**< \brief (AC_WINCTRL offset) Window Control */
-#define AC_WINCTRL_RESETVALUE       _U(0x00)     /**< \brief (AC_WINCTRL reset_value) Window Control */
+#define AC_WINCTRL_RESETVALUE       0x00ul       /**< \brief (AC_WINCTRL reset_value) Window Control */
 
 #define AC_WINCTRL_WEN0_Pos         0            /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
-#define AC_WINCTRL_WEN0             (_U(0x1) << AC_WINCTRL_WEN0_Pos)
+#define AC_WINCTRL_WEN0             (0x1ul << AC_WINCTRL_WEN0_Pos)
 #define AC_WINCTRL_WINTSEL0_Pos     1            /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
-#define AC_WINCTRL_WINTSEL0_Msk     (_U(0x3) << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_Msk     (0x3ul << AC_WINCTRL_WINTSEL0_Pos)
 #define AC_WINCTRL_WINTSEL0(value)  (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
-#define   AC_WINCTRL_WINTSEL0_ABOVE_Val   _U(0x0)   /**< \brief (AC_WINCTRL) Interrupt on signal above window */
-#define   AC_WINCTRL_WINTSEL0_INSIDE_Val  _U(0x1)   /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
-#define   AC_WINCTRL_WINTSEL0_BELOW_Val   _U(0x2)   /**< \brief (AC_WINCTRL) Interrupt on signal below window */
-#define   AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U(0x3)   /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
+#define   AC_WINCTRL_WINTSEL0_ABOVE_Val   0x0ul  /**< \brief (AC_WINCTRL) Interrupt on signal above window */
+#define   AC_WINCTRL_WINTSEL0_INSIDE_Val  0x1ul  /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
+#define   AC_WINCTRL_WINTSEL0_BELOW_Val   0x2ul  /**< \brief (AC_WINCTRL) Interrupt on signal below window */
+#define   AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul  /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
 #define AC_WINCTRL_WINTSEL0_ABOVE   (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
 #define AC_WINCTRL_WINTSEL0_INSIDE  (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
 #define AC_WINCTRL_WINTSEL0_BELOW   (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
 #define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_MASK             _U(0x07)     /**< \brief (AC_WINCTRL) MASK Register */
+#define AC_WINCTRL_MASK             0x07ul       /**< \brief (AC_WINCTRL) MASK Register */
 
 /* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -420,41 +435,41 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define AC_COMPCTRL_OFFSET          0x10         /**< \brief (AC_COMPCTRL offset) Comparator Control n */
-#define AC_COMPCTRL_RESETVALUE      _U(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
+#define AC_COMPCTRL_RESETVALUE      0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
 
 #define AC_COMPCTRL_ENABLE_Pos      0            /**< \brief (AC_COMPCTRL) Enable */
-#define AC_COMPCTRL_ENABLE          (_U(0x1) << AC_COMPCTRL_ENABLE_Pos)
+#define AC_COMPCTRL_ENABLE          (0x1ul << AC_COMPCTRL_ENABLE_Pos)
 #define AC_COMPCTRL_SINGLE_Pos      1            /**< \brief (AC_COMPCTRL) Single-Shot Mode */
-#define AC_COMPCTRL_SINGLE          (_U(0x1) << AC_COMPCTRL_SINGLE_Pos)
+#define AC_COMPCTRL_SINGLE          (0x1ul << AC_COMPCTRL_SINGLE_Pos)
 #define AC_COMPCTRL_SPEED_Pos       2            /**< \brief (AC_COMPCTRL) Speed Selection */
-#define AC_COMPCTRL_SPEED_Msk       (_U(0x3) << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED_Msk       (0x3ul << AC_COMPCTRL_SPEED_Pos)
 #define AC_COMPCTRL_SPEED(value)    (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
-#define   AC_COMPCTRL_SPEED_LOW_Val       _U(0x0)   /**< \brief (AC_COMPCTRL) Low speed */
-#define   AC_COMPCTRL_SPEED_HIGH_Val      _U(0x1)   /**< \brief (AC_COMPCTRL) High speed */
+#define   AC_COMPCTRL_SPEED_LOW_Val       0x0ul  /**< \brief (AC_COMPCTRL) Low speed */
+#define   AC_COMPCTRL_SPEED_HIGH_Val      0x1ul  /**< \brief (AC_COMPCTRL) High speed */
 #define AC_COMPCTRL_SPEED_LOW       (AC_COMPCTRL_SPEED_LOW_Val     << AC_COMPCTRL_SPEED_Pos)
 #define AC_COMPCTRL_SPEED_HIGH      (AC_COMPCTRL_SPEED_HIGH_Val    << AC_COMPCTRL_SPEED_Pos)
 #define AC_COMPCTRL_INTSEL_Pos      5            /**< \brief (AC_COMPCTRL) Interrupt Selection */
-#define AC_COMPCTRL_INTSEL_Msk      (_U(0x3) << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_Msk      (0x3ul << AC_COMPCTRL_INTSEL_Pos)
 #define AC_COMPCTRL_INTSEL(value)   (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
-#define   AC_COMPCTRL_INTSEL_TOGGLE_Val   _U(0x0)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
-#define   AC_COMPCTRL_INTSEL_RISING_Val   _U(0x1)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
-#define   AC_COMPCTRL_INTSEL_FALLING_Val  _U(0x2)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
-#define   AC_COMPCTRL_INTSEL_EOC_Val      _U(0x3)   /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
+#define   AC_COMPCTRL_INTSEL_TOGGLE_Val   0x0ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
+#define   AC_COMPCTRL_INTSEL_RISING_Val   0x1ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
+#define   AC_COMPCTRL_INTSEL_FALLING_Val  0x2ul  /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
+#define   AC_COMPCTRL_INTSEL_EOC_Val      0x3ul  /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
 #define AC_COMPCTRL_INTSEL_TOGGLE   (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
 #define AC_COMPCTRL_INTSEL_RISING   (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
 #define AC_COMPCTRL_INTSEL_FALLING  (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
 #define AC_COMPCTRL_INTSEL_EOC      (AC_COMPCTRL_INTSEL_EOC_Val    << AC_COMPCTRL_INTSEL_Pos)
 #define AC_COMPCTRL_MUXNEG_Pos      8            /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
-#define AC_COMPCTRL_MUXNEG_Msk      (_U(0x7) << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_Msk      (0x7ul << AC_COMPCTRL_MUXNEG_Pos)
 #define AC_COMPCTRL_MUXNEG(value)   (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
-#define   AC_COMPCTRL_MUXNEG_PIN0_Val     _U(0x0)   /**< \brief (AC_COMPCTRL) I/O pin 0 */
-#define   AC_COMPCTRL_MUXNEG_PIN1_Val     _U(0x1)   /**< \brief (AC_COMPCTRL) I/O pin 1 */
-#define   AC_COMPCTRL_MUXNEG_PIN2_Val     _U(0x2)   /**< \brief (AC_COMPCTRL) I/O pin 2 */
-#define   AC_COMPCTRL_MUXNEG_PIN3_Val     _U(0x3)   /**< \brief (AC_COMPCTRL) I/O pin 3 */
-#define   AC_COMPCTRL_MUXNEG_GND_Val      _U(0x4)   /**< \brief (AC_COMPCTRL) Ground */
-#define   AC_COMPCTRL_MUXNEG_VSCALE_Val   _U(0x5)   /**< \brief (AC_COMPCTRL) VDD scaler */
-#define   AC_COMPCTRL_MUXNEG_BANDGAP_Val  _U(0x6)   /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
-#define   AC_COMPCTRL_MUXNEG_DAC_Val      _U(0x7)   /**< \brief (AC_COMPCTRL) DAC output */
+#define   AC_COMPCTRL_MUXNEG_PIN0_Val     0x0ul  /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define   AC_COMPCTRL_MUXNEG_PIN1_Val     0x1ul  /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define   AC_COMPCTRL_MUXNEG_PIN2_Val     0x2ul  /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define   AC_COMPCTRL_MUXNEG_PIN3_Val     0x3ul  /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define   AC_COMPCTRL_MUXNEG_GND_Val      0x4ul  /**< \brief (AC_COMPCTRL) Ground */
+#define   AC_COMPCTRL_MUXNEG_VSCALE_Val   0x5ul  /**< \brief (AC_COMPCTRL) VDD scaler */
+#define   AC_COMPCTRL_MUXNEG_BANDGAP_Val  0x6ul  /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
+#define   AC_COMPCTRL_MUXNEG_DAC_Val      0x7ul  /**< \brief (AC_COMPCTRL) DAC output */
 #define AC_COMPCTRL_MUXNEG_PIN0     (AC_COMPCTRL_MUXNEG_PIN0_Val   << AC_COMPCTRL_MUXNEG_Pos)
 #define AC_COMPCTRL_MUXNEG_PIN1     (AC_COMPCTRL_MUXNEG_PIN1_Val   << AC_COMPCTRL_MUXNEG_Pos)
 #define AC_COMPCTRL_MUXNEG_PIN2     (AC_COMPCTRL_MUXNEG_PIN2_Val   << AC_COMPCTRL_MUXNEG_Pos)
@@ -464,39 +479,39 @@ typedef union {
 #define AC_COMPCTRL_MUXNEG_BANDGAP  (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
 #define AC_COMPCTRL_MUXNEG_DAC      (AC_COMPCTRL_MUXNEG_DAC_Val    << AC_COMPCTRL_MUXNEG_Pos)
 #define AC_COMPCTRL_MUXPOS_Pos      12           /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
-#define AC_COMPCTRL_MUXPOS_Msk      (_U(0x3) << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_Msk      (0x3ul << AC_COMPCTRL_MUXPOS_Pos)
 #define AC_COMPCTRL_MUXPOS(value)   (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
-#define   AC_COMPCTRL_MUXPOS_PIN0_Val     _U(0x0)   /**< \brief (AC_COMPCTRL) I/O pin 0 */
-#define   AC_COMPCTRL_MUXPOS_PIN1_Val     _U(0x1)   /**< \brief (AC_COMPCTRL) I/O pin 1 */
-#define   AC_COMPCTRL_MUXPOS_PIN2_Val     _U(0x2)   /**< \brief (AC_COMPCTRL) I/O pin 2 */
-#define   AC_COMPCTRL_MUXPOS_PIN3_Val     _U(0x3)   /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define   AC_COMPCTRL_MUXPOS_PIN0_Val     0x0ul  /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define   AC_COMPCTRL_MUXPOS_PIN1_Val     0x1ul  /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define   AC_COMPCTRL_MUXPOS_PIN2_Val     0x2ul  /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define   AC_COMPCTRL_MUXPOS_PIN3_Val     0x3ul  /**< \brief (AC_COMPCTRL) I/O pin 3 */
 #define AC_COMPCTRL_MUXPOS_PIN0     (AC_COMPCTRL_MUXPOS_PIN0_Val   << AC_COMPCTRL_MUXPOS_Pos)
 #define AC_COMPCTRL_MUXPOS_PIN1     (AC_COMPCTRL_MUXPOS_PIN1_Val   << AC_COMPCTRL_MUXPOS_Pos)
 #define AC_COMPCTRL_MUXPOS_PIN2     (AC_COMPCTRL_MUXPOS_PIN2_Val   << AC_COMPCTRL_MUXPOS_Pos)
 #define AC_COMPCTRL_MUXPOS_PIN3     (AC_COMPCTRL_MUXPOS_PIN3_Val   << AC_COMPCTRL_MUXPOS_Pos)
 #define AC_COMPCTRL_SWAP_Pos        15           /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
-#define AC_COMPCTRL_SWAP            (_U(0x1) << AC_COMPCTRL_SWAP_Pos)
+#define AC_COMPCTRL_SWAP            (0x1ul << AC_COMPCTRL_SWAP_Pos)
 #define AC_COMPCTRL_OUT_Pos         16           /**< \brief (AC_COMPCTRL) Output */
-#define AC_COMPCTRL_OUT_Msk         (_U(0x3) << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_Msk         (0x3ul << AC_COMPCTRL_OUT_Pos)
 #define AC_COMPCTRL_OUT(value)      (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
-#define   AC_COMPCTRL_OUT_OFF_Val         _U(0x0)   /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
-#define   AC_COMPCTRL_OUT_ASYNC_Val       _U(0x1)   /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
-#define   AC_COMPCTRL_OUT_SYNC_Val        _U(0x2)   /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_OFF_Val         0x0ul  /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_ASYNC_Val       0x1ul  /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_SYNC_Val        0x2ul  /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
 #define AC_COMPCTRL_OUT_OFF         (AC_COMPCTRL_OUT_OFF_Val       << AC_COMPCTRL_OUT_Pos)
 #define AC_COMPCTRL_OUT_ASYNC       (AC_COMPCTRL_OUT_ASYNC_Val     << AC_COMPCTRL_OUT_Pos)
 #define AC_COMPCTRL_OUT_SYNC        (AC_COMPCTRL_OUT_SYNC_Val      << AC_COMPCTRL_OUT_Pos)
 #define AC_COMPCTRL_HYST_Pos        19           /**< \brief (AC_COMPCTRL) Hysteresis Enable */
-#define AC_COMPCTRL_HYST            (_U(0x1) << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_HYST            (0x1ul << AC_COMPCTRL_HYST_Pos)
 #define AC_COMPCTRL_FLEN_Pos        24           /**< \brief (AC_COMPCTRL) Filter Length */
-#define AC_COMPCTRL_FLEN_Msk        (_U(0x7) << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_Msk        (0x7ul << AC_COMPCTRL_FLEN_Pos)
 #define AC_COMPCTRL_FLEN(value)     (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
-#define   AC_COMPCTRL_FLEN_OFF_Val        _U(0x0)   /**< \brief (AC_COMPCTRL) No filtering */
-#define   AC_COMPCTRL_FLEN_MAJ3_Val       _U(0x1)   /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
-#define   AC_COMPCTRL_FLEN_MAJ5_Val       _U(0x2)   /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
+#define   AC_COMPCTRL_FLEN_OFF_Val        0x0ul  /**< \brief (AC_COMPCTRL) No filtering */
+#define   AC_COMPCTRL_FLEN_MAJ3_Val       0x1ul  /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
+#define   AC_COMPCTRL_FLEN_MAJ5_Val       0x2ul  /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
 #define AC_COMPCTRL_FLEN_OFF        (AC_COMPCTRL_FLEN_OFF_Val      << AC_COMPCTRL_FLEN_Pos)
 #define AC_COMPCTRL_FLEN_MAJ3       (AC_COMPCTRL_FLEN_MAJ3_Val     << AC_COMPCTRL_FLEN_Pos)
 #define AC_COMPCTRL_FLEN_MAJ5       (AC_COMPCTRL_FLEN_MAJ5_Val     << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_MASK            _U(0x070BB76F) /**< \brief (AC_COMPCTRL) MASK Register */
+#define AC_COMPCTRL_MASK            0x070BB76Ful /**< \brief (AC_COMPCTRL) MASK Register */
 
 /* -------- AC_SCALER : (AC Offset: 0x20) (R/W  8) Scaler n -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -510,12 +525,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define AC_SCALER_OFFSET            0x20         /**< \brief (AC_SCALER offset) Scaler n */
-#define AC_SCALER_RESETVALUE        _U(0x00)     /**< \brief (AC_SCALER reset_value) Scaler n */
+#define AC_SCALER_RESETVALUE        0x00ul       /**< \brief (AC_SCALER reset_value) Scaler n */
 
 #define AC_SCALER_VALUE_Pos         0            /**< \brief (AC_SCALER) Scaler Value */
-#define AC_SCALER_VALUE_Msk         (_U(0x3F) << AC_SCALER_VALUE_Pos)
+#define AC_SCALER_VALUE_Msk         (0x3Ful << AC_SCALER_VALUE_Pos)
 #define AC_SCALER_VALUE(value)      (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
-#define AC_SCALER_MASK              _U(0x3F)     /**< \brief (AC_SCALER) MASK Register */
+#define AC_SCALER_MASK              0x3Ful       /**< \brief (AC_SCALER) MASK Register */
 
 /** \brief AC hardware registers */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

asf/sam0/utils/cmsis/samd21/include/component/adc.h

@@ -3,24 +3,39 @@
  *
  * \brief Component description for ADC
  *
- * Copyright (c) 2016 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *
  * \asf_license_stop
  *
@@ -52,15 +67,15 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_CTRLA_OFFSET            0x00         /**< \brief (ADC_CTRLA offset) Control A */
-#define ADC_CTRLA_RESETVALUE        _U(0x00)     /**< \brief (ADC_CTRLA reset_value) Control A */
+#define ADC_CTRLA_RESETVALUE        0x00ul       /**< \brief (ADC_CTRLA reset_value) Control A */
 
 #define ADC_CTRLA_SWRST_Pos         0            /**< \brief (ADC_CTRLA) Software Reset */
-#define ADC_CTRLA_SWRST             (_U(0x1) << ADC_CTRLA_SWRST_Pos)
+#define ADC_CTRLA_SWRST             (0x1ul << ADC_CTRLA_SWRST_Pos)
 #define ADC_CTRLA_ENABLE_Pos        1            /**< \brief (ADC_CTRLA) Enable */
-#define ADC_CTRLA_ENABLE            (_U(0x1) << ADC_CTRLA_ENABLE_Pos)
+#define ADC_CTRLA_ENABLE            (0x1ul << ADC_CTRLA_ENABLE_Pos)
 #define ADC_CTRLA_RUNSTDBY_Pos      2            /**< \brief (ADC_CTRLA) Run in Standby */
-#define ADC_CTRLA_RUNSTDBY          (_U(0x1) << ADC_CTRLA_RUNSTDBY_Pos)
-#define ADC_CTRLA_MASK              _U(0x07)     /**< \brief (ADC_CTRLA) MASK Register */
+#define ADC_CTRLA_RUNSTDBY          (0x1ul << ADC_CTRLA_RUNSTDBY_Pos)
+#define ADC_CTRLA_MASK              0x07ul       /**< \brief (ADC_CTRLA) MASK Register */
 
 /* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W  8) Reference Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -75,24 +90,24 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_REFCTRL_OFFSET          0x01         /**< \brief (ADC_REFCTRL offset) Reference Control */
-#define ADC_REFCTRL_RESETVALUE      _U(0x00)     /**< \brief (ADC_REFCTRL reset_value) Reference Control */
+#define ADC_REFCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_REFCTRL reset_value) Reference Control */
 
 #define ADC_REFCTRL_REFSEL_Pos      0            /**< \brief (ADC_REFCTRL) Reference Selection */
-#define ADC_REFCTRL_REFSEL_Msk      (_U(0xF) << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_Msk      (0xFul << ADC_REFCTRL_REFSEL_Pos)
 #define ADC_REFCTRL_REFSEL(value)   (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
-#define   ADC_REFCTRL_REFSEL_INT1V_Val    _U(0x0)   /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
-#define   ADC_REFCTRL_REFSEL_INTVCC0_Val  _U(0x1)   /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
-#define   ADC_REFCTRL_REFSEL_INTVCC1_Val  _U(0x2)   /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
-#define   ADC_REFCTRL_REFSEL_AREFA_Val    _U(0x3)   /**< \brief (ADC_REFCTRL) External reference */
-#define   ADC_REFCTRL_REFSEL_AREFB_Val    _U(0x4)   /**< \brief (ADC_REFCTRL) External reference */
+#define   ADC_REFCTRL_REFSEL_INT1V_Val    0x0ul  /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
+#define   ADC_REFCTRL_REFSEL_INTVCC0_Val  0x1ul  /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
+#define   ADC_REFCTRL_REFSEL_INTVCC1_Val  0x2ul  /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
+#define   ADC_REFCTRL_REFSEL_AREFA_Val    0x3ul  /**< \brief (ADC_REFCTRL) External reference */
+#define   ADC_REFCTRL_REFSEL_AREFB_Val    0x4ul  /**< \brief (ADC_REFCTRL) External reference */
 #define ADC_REFCTRL_REFSEL_INT1V    (ADC_REFCTRL_REFSEL_INT1V_Val  << ADC_REFCTRL_REFSEL_Pos)
 #define ADC_REFCTRL_REFSEL_INTVCC0  (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
 #define ADC_REFCTRL_REFSEL_INTVCC1  (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
 #define ADC_REFCTRL_REFSEL_AREFA    (ADC_REFCTRL_REFSEL_AREFA_Val  << ADC_REFCTRL_REFSEL_Pos)
 #define ADC_REFCTRL_REFSEL_AREFB    (ADC_REFCTRL_REFSEL_AREFB_Val  << ADC_REFCTRL_REFSEL_Pos)
 #define ADC_REFCTRL_REFCOMP_Pos     7            /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
-#define ADC_REFCTRL_REFCOMP         (_U(0x1) << ADC_REFCTRL_REFCOMP_Pos)
-#define ADC_REFCTRL_MASK            _U(0x8F)     /**< \brief (ADC_REFCTRL) MASK Register */
+#define ADC_REFCTRL_REFCOMP         (0x1ul << ADC_REFCTRL_REFCOMP_Pos)
+#define ADC_REFCTRL_MASK            0x8Ful       /**< \brief (ADC_REFCTRL) MASK Register */
 
 /* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W  8) Average Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -107,22 +122,22 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_AVGCTRL_OFFSET          0x02         /**< \brief (ADC_AVGCTRL offset) Average Control */
-#define ADC_AVGCTRL_RESETVALUE      _U(0x00)     /**< \brief (ADC_AVGCTRL reset_value) Average Control */
+#define ADC_AVGCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_AVGCTRL reset_value) Average Control */
 
 #define ADC_AVGCTRL_SAMPLENUM_Pos   0            /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
-#define ADC_AVGCTRL_SAMPLENUM_Msk   (_U(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_Msk   (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos)
 #define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
-#define   ADC_AVGCTRL_SAMPLENUM_1_Val     _U(0x0)   /**< \brief (ADC_AVGCTRL) 1 sample */
-#define   ADC_AVGCTRL_SAMPLENUM_2_Val     _U(0x1)   /**< \brief (ADC_AVGCTRL) 2 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_4_Val     _U(0x2)   /**< \brief (ADC_AVGCTRL) 4 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_8_Val     _U(0x3)   /**< \brief (ADC_AVGCTRL) 8 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_16_Val    _U(0x4)   /**< \brief (ADC_AVGCTRL) 16 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_32_Val    _U(0x5)   /**< \brief (ADC_AVGCTRL) 32 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_64_Val    _U(0x6)   /**< \brief (ADC_AVGCTRL) 64 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_128_Val   _U(0x7)   /**< \brief (ADC_AVGCTRL) 128 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_256_Val   _U(0x8)   /**< \brief (ADC_AVGCTRL) 256 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_512_Val   _U(0x9)   /**< \brief (ADC_AVGCTRL) 512 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_1024_Val  _U(0xA)   /**< \brief (ADC_AVGCTRL) 1024 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_1_Val     0x0ul  /**< \brief (ADC_AVGCTRL) 1 sample */
+#define   ADC_AVGCTRL_SAMPLENUM_2_Val     0x1ul  /**< \brief (ADC_AVGCTRL) 2 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_4_Val     0x2ul  /**< \brief (ADC_AVGCTRL) 4 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_8_Val     0x3ul  /**< \brief (ADC_AVGCTRL) 8 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_16_Val    0x4ul  /**< \brief (ADC_AVGCTRL) 16 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_32_Val    0x5ul  /**< \brief (ADC_AVGCTRL) 32 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_64_Val    0x6ul  /**< \brief (ADC_AVGCTRL) 64 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_128_Val   0x7ul  /**< \brief (ADC_AVGCTRL) 128 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_256_Val   0x8ul  /**< \brief (ADC_AVGCTRL) 256 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_512_Val   0x9ul  /**< \brief (ADC_AVGCTRL) 512 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_1024_Val  0xAul  /**< \brief (ADC_AVGCTRL) 1024 samples */
 #define ADC_AVGCTRL_SAMPLENUM_1     (ADC_AVGCTRL_SAMPLENUM_1_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
 #define ADC_AVGCTRL_SAMPLENUM_2     (ADC_AVGCTRL_SAMPLENUM_2_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
 #define ADC_AVGCTRL_SAMPLENUM_4     (ADC_AVGCTRL_SAMPLENUM_4_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
@@ -135,9 +150,9 @@ typedef union {
 #define ADC_AVGCTRL_SAMPLENUM_512   (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
 #define ADC_AVGCTRL_SAMPLENUM_1024  (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
 #define ADC_AVGCTRL_ADJRES_Pos      4            /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
-#define ADC_AVGCTRL_ADJRES_Msk      (_U(0x7) << ADC_AVGCTRL_ADJRES_Pos)
+#define ADC_AVGCTRL_ADJRES_Msk      (0x7ul << ADC_AVGCTRL_ADJRES_Pos)
 #define ADC_AVGCTRL_ADJRES(value)   (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
-#define ADC_AVGCTRL_MASK            _U(0x7F)     /**< \brief (ADC_AVGCTRL) MASK Register */
+#define ADC_AVGCTRL_MASK            0x7Ful       /**< \brief (ADC_AVGCTRL) MASK Register */
 
 /* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W  8) Sampling Time Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -151,12 +166,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_SAMPCTRL_OFFSET         0x03         /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
-#define ADC_SAMPCTRL_RESETVALUE     _U(0x00)     /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
+#define ADC_SAMPCTRL_RESETVALUE     0x00ul       /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
 
 #define ADC_SAMPCTRL_SAMPLEN_Pos    0            /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
-#define ADC_SAMPCTRL_SAMPLEN_Msk    (_U(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)
+#define ADC_SAMPCTRL_SAMPLEN_Msk    (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos)
 #define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
-#define ADC_SAMPCTRL_MASK           _U(0x3F)     /**< \brief (ADC_SAMPCTRL) MASK Register */
+#define ADC_SAMPCTRL_MASK           0x3Ful       /**< \brief (ADC_SAMPCTRL) MASK Register */
 
 /* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -176,38 +191,38 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_CTRLB_OFFSET            0x04         /**< \brief (ADC_CTRLB offset) Control B */
-#define ADC_CTRLB_RESETVALUE        _U(0x0000)   /**< \brief (ADC_CTRLB reset_value) Control B */
+#define ADC_CTRLB_RESETVALUE        0x0000ul     /**< \brief (ADC_CTRLB reset_value) Control B */
 
 #define ADC_CTRLB_DIFFMODE_Pos      0            /**< \brief (ADC_CTRLB) Differential Mode */
-#define ADC_CTRLB_DIFFMODE          (_U(0x1) << ADC_CTRLB_DIFFMODE_Pos)
+#define ADC_CTRLB_DIFFMODE          (0x1ul << ADC_CTRLB_DIFFMODE_Pos)
 #define ADC_CTRLB_LEFTADJ_Pos       1            /**< \brief (ADC_CTRLB) Left-Adjusted Result */
-#define ADC_CTRLB_LEFTADJ           (_U(0x1) << ADC_CTRLB_LEFTADJ_Pos)
+#define ADC_CTRLB_LEFTADJ           (0x1ul << ADC_CTRLB_LEFTADJ_Pos)
 #define ADC_CTRLB_FREERUN_Pos       2            /**< \brief (ADC_CTRLB) Free Running Mode */
-#define ADC_CTRLB_FREERUN           (_U(0x1) << ADC_CTRLB_FREERUN_Pos)
+#define ADC_CTRLB_FREERUN           (0x1ul << ADC_CTRLB_FREERUN_Pos)
 #define ADC_CTRLB_CORREN_Pos        3            /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
-#define ADC_CTRLB_CORREN            (_U(0x1) << ADC_CTRLB_CORREN_Pos)
+#define ADC_CTRLB_CORREN            (0x1ul << ADC_CTRLB_CORREN_Pos)
 #define ADC_CTRLB_RESSEL_Pos        4            /**< \brief (ADC_CTRLB) Conversion Result Resolution */
-#define ADC_CTRLB_RESSEL_Msk        (_U(0x3) << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_Msk        (0x3ul << ADC_CTRLB_RESSEL_Pos)
 #define ADC_CTRLB_RESSEL(value)     (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
-#define   ADC_CTRLB_RESSEL_12BIT_Val      _U(0x0)   /**< \brief (ADC_CTRLB) 12-bit result */
-#define   ADC_CTRLB_RESSEL_16BIT_Val      _U(0x1)   /**< \brief (ADC_CTRLB) For averaging mode output */
-#define   ADC_CTRLB_RESSEL_10BIT_Val      _U(0x2)   /**< \brief (ADC_CTRLB) 10-bit result */
-#define   ADC_CTRLB_RESSEL_8BIT_Val       _U(0x3)   /**< \brief (ADC_CTRLB) 8-bit result */
+#define   ADC_CTRLB_RESSEL_12BIT_Val      0x0ul  /**< \brief (ADC_CTRLB) 12-bit result */
+#define   ADC_CTRLB_RESSEL_16BIT_Val      0x1ul  /**< \brief (ADC_CTRLB) For averaging mode output */
+#define   ADC_CTRLB_RESSEL_10BIT_Val      0x2ul  /**< \brief (ADC_CTRLB) 10-bit result */
+#define   ADC_CTRLB_RESSEL_8BIT_Val       0x3ul  /**< \brief (ADC_CTRLB) 8-bit result */
 #define ADC_CTRLB_RESSEL_12BIT      (ADC_CTRLB_RESSEL_12BIT_Val    << ADC_CTRLB_RESSEL_Pos)
 #define ADC_CTRLB_RESSEL_16BIT      (ADC_CTRLB_RESSEL_16BIT_Val    << ADC_CTRLB_RESSEL_Pos)
 #define ADC_CTRLB_RESSEL_10BIT      (ADC_CTRLB_RESSEL_10BIT_Val    << ADC_CTRLB_RESSEL_Pos)
 #define ADC_CTRLB_RESSEL_8BIT       (ADC_CTRLB_RESSEL_8BIT_Val     << ADC_CTRLB_RESSEL_Pos)
 #define ADC_CTRLB_PRESCALER_Pos     8            /**< \brief (ADC_CTRLB) Prescaler Configuration */
-#define ADC_CTRLB_PRESCALER_Msk     (_U(0x7) << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_Msk     (0x7ul << ADC_CTRLB_PRESCALER_Pos)
 #define ADC_CTRLB_PRESCALER(value)  (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))
-#define   ADC_CTRLB_PRESCALER_DIV4_Val    _U(0x0)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
-#define   ADC_CTRLB_PRESCALER_DIV8_Val    _U(0x1)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
-#define   ADC_CTRLB_PRESCALER_DIV16_Val   _U(0x2)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
-#define   ADC_CTRLB_PRESCALER_DIV32_Val   _U(0x3)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
-#define   ADC_CTRLB_PRESCALER_DIV64_Val   _U(0x4)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
-#define   ADC_CTRLB_PRESCALER_DIV128_Val  _U(0x5)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
-#define   ADC_CTRLB_PRESCALER_DIV256_Val  _U(0x6)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
-#define   ADC_CTRLB_PRESCALER_DIV512_Val  _U(0x7)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
+#define   ADC_CTRLB_PRESCALER_DIV4_Val    0x0ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
+#define   ADC_CTRLB_PRESCALER_DIV8_Val    0x1ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
+#define   ADC_CTRLB_PRESCALER_DIV16_Val   0x2ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
+#define   ADC_CTRLB_PRESCALER_DIV32_Val   0x3ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
+#define   ADC_CTRLB_PRESCALER_DIV64_Val   0x4ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
+#define   ADC_CTRLB_PRESCALER_DIV128_Val  0x5ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
+#define   ADC_CTRLB_PRESCALER_DIV256_Val  0x6ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
+#define   ADC_CTRLB_PRESCALER_DIV512_Val  0x7ul  /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
 #define ADC_CTRLB_PRESCALER_DIV4    (ADC_CTRLB_PRESCALER_DIV4_Val  << ADC_CTRLB_PRESCALER_Pos)
 #define ADC_CTRLB_PRESCALER_DIV8    (ADC_CTRLB_PRESCALER_DIV8_Val  << ADC_CTRLB_PRESCALER_Pos)
 #define ADC_CTRLB_PRESCALER_DIV16   (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
@@ -216,7 +231,7 @@ typedef union {
 #define ADC_CTRLB_PRESCALER_DIV128  (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
 #define ADC_CTRLB_PRESCALER_DIV256  (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
 #define ADC_CTRLB_PRESCALER_DIV512  (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
-#define ADC_CTRLB_MASK              _U(0x073F)   /**< \brief (ADC_CTRLB) MASK Register */
+#define ADC_CTRLB_MASK              0x073Ful     /**< \brief (ADC_CTRLB) MASK Register */
 
 /* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W  8) Window Monitor Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -230,22 +245,22 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_WINCTRL_OFFSET          0x08         /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
-#define ADC_WINCTRL_RESETVALUE      _U(0x00)     /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
+#define ADC_WINCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
 
 #define ADC_WINCTRL_WINMODE_Pos     0            /**< \brief (ADC_WINCTRL) Window Monitor Mode */
-#define ADC_WINCTRL_WINMODE_Msk     (_U(0x7) << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_Msk     (0x7ul << ADC_WINCTRL_WINMODE_Pos)
 #define ADC_WINCTRL_WINMODE(value)  (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))
-#define   ADC_WINCTRL_WINMODE_DISABLE_Val _U(0x0)   /**< \brief (ADC_WINCTRL) No window mode (default) */
-#define   ADC_WINCTRL_WINMODE_MODE1_Val   _U(0x1)   /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
-#define   ADC_WINCTRL_WINMODE_MODE2_Val   _U(0x2)   /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
-#define   ADC_WINCTRL_WINMODE_MODE3_Val   _U(0x3)   /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
-#define   ADC_WINCTRL_WINMODE_MODE4_Val   _U(0x4)   /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
+#define   ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul  /**< \brief (ADC_WINCTRL) No window mode (default) */
+#define   ADC_WINCTRL_WINMODE_MODE1_Val   0x1ul  /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
+#define   ADC_WINCTRL_WINMODE_MODE2_Val   0x2ul  /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
+#define   ADC_WINCTRL_WINMODE_MODE3_Val   0x3ul  /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
+#define   ADC_WINCTRL_WINMODE_MODE4_Val   0x4ul  /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
 #define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
 #define ADC_WINCTRL_WINMODE_MODE1   (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
 #define ADC_WINCTRL_WINMODE_MODE2   (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
 #define ADC_WINCTRL_WINMODE_MODE3   (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
 #define ADC_WINCTRL_WINMODE_MODE4   (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
-#define ADC_WINCTRL_MASK            _U(0x07)     /**< \brief (ADC_WINCTRL) MASK Register */
+#define ADC_WINCTRL_MASK            0x07ul       /**< \brief (ADC_WINCTRL) MASK Register */
 
 /* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W  8) Software Trigger -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -260,13 +275,13 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_SWTRIG_OFFSET           0x0C         /**< \brief (ADC_SWTRIG offset) Software Trigger */
-#define ADC_SWTRIG_RESETVALUE       _U(0x00)     /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
+#define ADC_SWTRIG_RESETVALUE       0x00ul       /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
 
 #define ADC_SWTRIG_FLUSH_Pos        0            /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
-#define ADC_SWTRIG_FLUSH            (_U(0x1) << ADC_SWTRIG_FLUSH_Pos)
+#define ADC_SWTRIG_FLUSH            (0x1ul << ADC_SWTRIG_FLUSH_Pos)
 #define ADC_SWTRIG_START_Pos        1            /**< \brief (ADC_SWTRIG) ADC Start Conversion */
-#define ADC_SWTRIG_START            (_U(0x1) << ADC_SWTRIG_START_Pos)
-#define ADC_SWTRIG_MASK             _U(0x03)     /**< \brief (ADC_SWTRIG) MASK Register */
+#define ADC_SWTRIG_START            (0x1ul << ADC_SWTRIG_START_Pos)
+#define ADC_SWTRIG_MASK             0x03ul       /**< \brief (ADC_SWTRIG) MASK Register */
 
 /* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -286,36 +301,36 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_INPUTCTRL_OFFSET        0x10         /**< \brief (ADC_INPUTCTRL offset) Input Control */
-#define ADC_INPUTCTRL_RESETVALUE    _U(0x00000000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
+#define ADC_INPUTCTRL_RESETVALUE    0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
 
 #define ADC_INPUTCTRL_MUXPOS_Pos    0            /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
-#define ADC_INPUTCTRL_MUXPOS_Msk    (_U(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_Msk    (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos)
 #define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
-#define   ADC_INPUTCTRL_MUXPOS_PIN0_Val   _U(0x0)   /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN1_Val   _U(0x1)   /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN2_Val   _U(0x2)   /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN3_Val   _U(0x3)   /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN4_Val   _U(0x4)   /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN5_Val   _U(0x5)   /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN6_Val   _U(0x6)   /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN7_Val   _U(0x7)   /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN8_Val   _U(0x8)   /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN9_Val   _U(0x9)   /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN10_Val  _U(0xA)   /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN11_Val  _U(0xB)   /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN12_Val  _U(0xC)   /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN13_Val  _U(0xD)   /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN14_Val  _U(0xE)   /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN15_Val  _U(0xF)   /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN16_Val  _U(0x10)   /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN17_Val  _U(0x11)   /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN18_Val  _U(0x12)   /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_PIN19_Val  _U(0x13)   /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_TEMP_Val   _U(0x18)   /**< \brief (ADC_INPUTCTRL) Temperature Reference */
-#define   ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U(0x19)   /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
-#define   ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U(0x1A)   /**< \brief (ADC_INPUTCTRL) 1/4  Scaled Core Supply */
-#define   ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U(0x1B)   /**< \brief (ADC_INPUTCTRL) 1/4  Scaled I/O Supply */
-#define   ADC_INPUTCTRL_MUXPOS_DAC_Val    _U(0x1C)   /**< \brief (ADC_INPUTCTRL) DAC Output */
+#define   ADC_INPUTCTRL_MUXPOS_PIN0_Val   0x0ul  /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN1_Val   0x1ul  /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN2_Val   0x2ul  /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN3_Val   0x3ul  /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN4_Val   0x4ul  /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN5_Val   0x5ul  /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN6_Val   0x6ul  /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN7_Val   0x7ul  /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN8_Val   0x8ul  /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN9_Val   0x9ul  /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN10_Val  0xAul  /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN11_Val  0xBul  /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN12_Val  0xCul  /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN13_Val  0xDul  /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN14_Val  0xEul  /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN15_Val  0xFul  /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN16_Val  0x10ul  /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN17_Val  0x11ul  /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN18_Val  0x12ul  /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_PIN19_Val  0x13ul  /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_TEMP_Val   0x18ul  /**< \brief (ADC_INPUTCTRL) Temperature Reference */
+#define   ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul  /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul  /**< \brief (ADC_INPUTCTRL) 1/4  Scaled Core Supply */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul  /**< \brief (ADC_INPUTCTRL) 1/4  Scaled I/O Supply */
+#define   ADC_INPUTCTRL_MUXPOS_DAC_Val    0x1Cul  /**< \brief (ADC_INPUTCTRL) DAC Output */
 #define ADC_INPUTCTRL_MUXPOS_PIN0   (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
 #define ADC_INPUTCTRL_MUXPOS_PIN1   (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
 #define ADC_INPUTCTRL_MUXPOS_PIN2   (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
@@ -342,18 +357,18 @@ typedef union {
 #define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
 #define ADC_INPUTCTRL_MUXPOS_DAC    (ADC_INPUTCTRL_MUXPOS_DAC_Val  << ADC_INPUTCTRL_MUXPOS_Pos)
 #define ADC_INPUTCTRL_MUXNEG_Pos    8            /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
-#define ADC_INPUTCTRL_MUXNEG_Msk    (_U(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_Msk    (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos)
 #define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
-#define   ADC_INPUTCTRL_MUXNEG_PIN0_Val   _U(0x0)   /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_PIN1_Val   _U(0x1)   /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_PIN2_Val   _U(0x2)   /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_PIN3_Val   _U(0x3)   /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_PIN4_Val   _U(0x4)   /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_PIN5_Val   _U(0x5)   /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_PIN6_Val   _U(0x6)   /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_PIN7_Val   _U(0x7)   /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_GND_Val    _U(0x18)   /**< \brief (ADC_INPUTCTRL) Internal Ground */
-#define   ADC_INPUTCTRL_MUXNEG_IOGND_Val  _U(0x19)   /**< \brief (ADC_INPUTCTRL) I/O Ground */
+#define   ADC_INPUTCTRL_MUXNEG_PIN0_Val   0x0ul  /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN1_Val   0x1ul  /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN2_Val   0x2ul  /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN3_Val   0x3ul  /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN4_Val   0x4ul  /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN5_Val   0x5ul  /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN6_Val   0x6ul  /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_PIN7_Val   0x7ul  /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_GND_Val    0x18ul  /**< \brief (ADC_INPUTCTRL) Internal Ground */
+#define   ADC_INPUTCTRL_MUXNEG_IOGND_Val  0x19ul  /**< \brief (ADC_INPUTCTRL) I/O Ground */
 #define ADC_INPUTCTRL_MUXNEG_PIN0   (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
 #define ADC_INPUTCTRL_MUXNEG_PIN1   (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
 #define ADC_INPUTCTRL_MUXNEG_PIN2   (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
@@ -365,27 +380,27 @@ typedef union {
 #define ADC_INPUTCTRL_MUXNEG_GND    (ADC_INPUTCTRL_MUXNEG_GND_Val  << ADC_INPUTCTRL_MUXNEG_Pos)
 #define ADC_INPUTCTRL_MUXNEG_IOGND  (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
 #define ADC_INPUTCTRL_INPUTSCAN_Pos 16           /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
-#define ADC_INPUTCTRL_INPUTSCAN_Msk (_U(0xF) << ADC_INPUTCTRL_INPUTSCAN_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos)
 #define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))
 #define ADC_INPUTCTRL_INPUTOFFSET_Pos 20           /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
-#define ADC_INPUTCTRL_INPUTOFFSET_Msk (_U(0xF) << ADC_INPUTCTRL_INPUTOFFSET_Pos)
+#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos)
 #define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))
 #define ADC_INPUTCTRL_GAIN_Pos      24           /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
-#define ADC_INPUTCTRL_GAIN_Msk      (_U(0xF) << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_Msk      (0xFul << ADC_INPUTCTRL_GAIN_Pos)
 #define ADC_INPUTCTRL_GAIN(value)   (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))
-#define   ADC_INPUTCTRL_GAIN_1X_Val       _U(0x0)   /**< \brief (ADC_INPUTCTRL) 1x */
-#define   ADC_INPUTCTRL_GAIN_2X_Val       _U(0x1)   /**< \brief (ADC_INPUTCTRL) 2x */
-#define   ADC_INPUTCTRL_GAIN_4X_Val       _U(0x2)   /**< \brief (ADC_INPUTCTRL) 4x */
-#define   ADC_INPUTCTRL_GAIN_8X_Val       _U(0x3)   /**< \brief (ADC_INPUTCTRL) 8x */
-#define   ADC_INPUTCTRL_GAIN_16X_Val      _U(0x4)   /**< \brief (ADC_INPUTCTRL) 16x */
-#define   ADC_INPUTCTRL_GAIN_DIV2_Val     _U(0xF)   /**< \brief (ADC_INPUTCTRL) 1/2x */
+#define   ADC_INPUTCTRL_GAIN_1X_Val       0x0ul  /**< \brief (ADC_INPUTCTRL) 1x */
+#define   ADC_INPUTCTRL_GAIN_2X_Val       0x1ul  /**< \brief (ADC_INPUTCTRL) 2x */
+#define   ADC_INPUTCTRL_GAIN_4X_Val       0x2ul  /**< \brief (ADC_INPUTCTRL) 4x */
+#define   ADC_INPUTCTRL_GAIN_8X_Val       0x3ul  /**< \brief (ADC_INPUTCTRL) 8x */
+#define   ADC_INPUTCTRL_GAIN_16X_Val      0x4ul  /**< \brief (ADC_INPUTCTRL) 16x */
+#define   ADC_INPUTCTRL_GAIN_DIV2_Val     0xFul  /**< \brief (ADC_INPUTCTRL) 1/2x */
 #define ADC_INPUTCTRL_GAIN_1X       (ADC_INPUTCTRL_GAIN_1X_Val     << ADC_INPUTCTRL_GAIN_Pos)
 #define ADC_INPUTCTRL_GAIN_2X       (ADC_INPUTCTRL_GAIN_2X_Val     << ADC_INPUTCTRL_GAIN_Pos)
 #define ADC_INPUTCTRL_GAIN_4X       (ADC_INPUTCTRL_GAIN_4X_Val     << ADC_INPUTCTRL_GAIN_Pos)
 #define ADC_INPUTCTRL_GAIN_8X       (ADC_INPUTCTRL_GAIN_8X_Val     << ADC_INPUTCTRL_GAIN_Pos)
 #define ADC_INPUTCTRL_GAIN_16X      (ADC_INPUTCTRL_GAIN_16X_Val    << ADC_INPUTCTRL_GAIN_Pos)
 #define ADC_INPUTCTRL_GAIN_DIV2     (ADC_INPUTCTRL_GAIN_DIV2_Val   << ADC_INPUTCTRL_GAIN_Pos)
-#define ADC_INPUTCTRL_MASK          _U(0x0FFF1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */
+#define ADC_INPUTCTRL_MASK          0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */
 
 /* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W  8) Event Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -403,17 +418,17 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_EVCTRL_OFFSET           0x14         /**< \brief (ADC_EVCTRL offset) Event Control */
-#define ADC_EVCTRL_RESETVALUE       _U(0x00)     /**< \brief (ADC_EVCTRL reset_value) Event Control */
+#define ADC_EVCTRL_RESETVALUE       0x00ul       /**< \brief (ADC_EVCTRL reset_value) Event Control */
 
 #define ADC_EVCTRL_STARTEI_Pos      0            /**< \brief (ADC_EVCTRL) Start Conversion Event In */
-#define ADC_EVCTRL_STARTEI          (_U(0x1) << ADC_EVCTRL_STARTEI_Pos)
+#define ADC_EVCTRL_STARTEI          (0x1ul << ADC_EVCTRL_STARTEI_Pos)
 #define ADC_EVCTRL_SYNCEI_Pos       1            /**< \brief (ADC_EVCTRL) Synchronization Event In */
-#define ADC_EVCTRL_SYNCEI           (_U(0x1) << ADC_EVCTRL_SYNCEI_Pos)
+#define ADC_EVCTRL_SYNCEI           (0x1ul << ADC_EVCTRL_SYNCEI_Pos)
 #define ADC_EVCTRL_RESRDYEO_Pos     4            /**< \brief (ADC_EVCTRL) Result Ready Event Out */
-#define ADC_EVCTRL_RESRDYEO         (_U(0x1) << ADC_EVCTRL_RESRDYEO_Pos)
+#define ADC_EVCTRL_RESRDYEO         (0x1ul << ADC_EVCTRL_RESRDYEO_Pos)
 #define ADC_EVCTRL_WINMONEO_Pos     5            /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
-#define ADC_EVCTRL_WINMONEO         (_U(0x1) << ADC_EVCTRL_WINMONEO_Pos)
-#define ADC_EVCTRL_MASK             _U(0x33)     /**< \brief (ADC_EVCTRL) MASK Register */
+#define ADC_EVCTRL_WINMONEO         (0x1ul << ADC_EVCTRL_WINMONEO_Pos)
+#define ADC_EVCTRL_MASK             0x33ul       /**< \brief (ADC_EVCTRL) MASK Register */
 
 /* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W  8) Interrupt Enable Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -430,17 +445,17 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_INTENCLR_OFFSET         0x16         /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
-#define ADC_INTENCLR_RESETVALUE     _U(0x00)     /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
+#define ADC_INTENCLR_RESETVALUE     0x00ul       /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
 
 #define ADC_INTENCLR_RESRDY_Pos     0            /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
-#define ADC_INTENCLR_RESRDY         (_U(0x1) << ADC_INTENCLR_RESRDY_Pos)
+#define ADC_INTENCLR_RESRDY         (0x1ul << ADC_INTENCLR_RESRDY_Pos)
 #define ADC_INTENCLR_OVERRUN_Pos    1            /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
-#define ADC_INTENCLR_OVERRUN        (_U(0x1) << ADC_INTENCLR_OVERRUN_Pos)
+#define ADC_INTENCLR_OVERRUN        (0x1ul << ADC_INTENCLR_OVERRUN_Pos)
 #define ADC_INTENCLR_WINMON_Pos     2            /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
-#define ADC_INTENCLR_WINMON         (_U(0x1) << ADC_INTENCLR_WINMON_Pos)
+#define ADC_INTENCLR_WINMON         (0x1ul << ADC_INTENCLR_WINMON_Pos)
 #define ADC_INTENCLR_SYNCRDY_Pos    3            /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
-#define ADC_INTENCLR_SYNCRDY        (_U(0x1) << ADC_INTENCLR_SYNCRDY_Pos)
-#define ADC_INTENCLR_MASK           _U(0x0F)     /**< \brief (ADC_INTENCLR) MASK Register */
+#define ADC_INTENCLR_SYNCRDY        (0x1ul << ADC_INTENCLR_SYNCRDY_Pos)
+#define ADC_INTENCLR_MASK           0x0Ful       /**< \brief (ADC_INTENCLR) MASK Register */
 
 /* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W  8) Interrupt Enable Set -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -457,17 +472,17 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_INTENSET_OFFSET         0x17         /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
-#define ADC_INTENSET_RESETVALUE     _U(0x00)     /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
+#define ADC_INTENSET_RESETVALUE     0x00ul       /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
 
 #define ADC_INTENSET_RESRDY_Pos     0            /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
-#define ADC_INTENSET_RESRDY         (_U(0x1) << ADC_INTENSET_RESRDY_Pos)
+#define ADC_INTENSET_RESRDY         (0x1ul << ADC_INTENSET_RESRDY_Pos)
 #define ADC_INTENSET_OVERRUN_Pos    1            /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
-#define ADC_INTENSET_OVERRUN        (_U(0x1) << ADC_INTENSET_OVERRUN_Pos)
+#define ADC_INTENSET_OVERRUN        (0x1ul << ADC_INTENSET_OVERRUN_Pos)
 #define ADC_INTENSET_WINMON_Pos     2            /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
-#define ADC_INTENSET_WINMON         (_U(0x1) << ADC_INTENSET_WINMON_Pos)
+#define ADC_INTENSET_WINMON         (0x1ul << ADC_INTENSET_WINMON_Pos)
 #define ADC_INTENSET_SYNCRDY_Pos    3            /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
-#define ADC_INTENSET_SYNCRDY        (_U(0x1) << ADC_INTENSET_SYNCRDY_Pos)
-#define ADC_INTENSET_MASK           _U(0x0F)     /**< \brief (ADC_INTENSET) MASK Register */
+#define ADC_INTENSET_SYNCRDY        (0x1ul << ADC_INTENSET_SYNCRDY_Pos)
+#define ADC_INTENSET_MASK           0x0Ful       /**< \brief (ADC_INTENSET) MASK Register */
 
 /* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W  8) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -484,17 +499,17 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_INTFLAG_OFFSET          0x18         /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define ADC_INTFLAG_RESETVALUE      _U(0x00)     /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+#define ADC_INTFLAG_RESETVALUE      0x00ul       /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
 
 #define ADC_INTFLAG_RESRDY_Pos      0            /**< \brief (ADC_INTFLAG) Result Ready */
-#define ADC_INTFLAG_RESRDY          (_U(0x1) << ADC_INTFLAG_RESRDY_Pos)
+#define ADC_INTFLAG_RESRDY          (0x1ul << ADC_INTFLAG_RESRDY_Pos)
 #define ADC_INTFLAG_OVERRUN_Pos     1            /**< \brief (ADC_INTFLAG) Overrun */
-#define ADC_INTFLAG_OVERRUN         (_U(0x1) << ADC_INTFLAG_OVERRUN_Pos)
+#define ADC_INTFLAG_OVERRUN         (0x1ul << ADC_INTFLAG_OVERRUN_Pos)
 #define ADC_INTFLAG_WINMON_Pos      2            /**< \brief (ADC_INTFLAG) Window Monitor */
-#define ADC_INTFLAG_WINMON          (_U(0x1) << ADC_INTFLAG_WINMON_Pos)
+#define ADC_INTFLAG_WINMON          (0x1ul << ADC_INTFLAG_WINMON_Pos)
 #define ADC_INTFLAG_SYNCRDY_Pos     3            /**< \brief (ADC_INTFLAG) Synchronization Ready */
-#define ADC_INTFLAG_SYNCRDY         (_U(0x1) << ADC_INTFLAG_SYNCRDY_Pos)
-#define ADC_INTFLAG_MASK            _U(0x0F)     /**< \brief (ADC_INTFLAG) MASK Register */
+#define ADC_INTFLAG_SYNCRDY         (0x1ul << ADC_INTFLAG_SYNCRDY_Pos)
+#define ADC_INTFLAG_MASK            0x0Ful       /**< \brief (ADC_INTFLAG) MASK Register */
 
 /* -------- ADC_STATUS : (ADC Offset: 0x19) (R/   8) Status -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -508,11 +523,11 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_STATUS_OFFSET           0x19         /**< \brief (ADC_STATUS offset) Status */
-#define ADC_STATUS_RESETVALUE       _U(0x00)     /**< \brief (ADC_STATUS reset_value) Status */
+#define ADC_STATUS_RESETVALUE       0x00ul       /**< \brief (ADC_STATUS reset_value) Status */
 
 #define ADC_STATUS_SYNCBUSY_Pos     7            /**< \brief (ADC_STATUS) Synchronization Busy */
-#define ADC_STATUS_SYNCBUSY         (_U(0x1) << ADC_STATUS_SYNCBUSY_Pos)
-#define ADC_STATUS_MASK             _U(0x80)     /**< \brief (ADC_STATUS) MASK Register */
+#define ADC_STATUS_SYNCBUSY         (0x1ul << ADC_STATUS_SYNCBUSY_Pos)
+#define ADC_STATUS_MASK             0x80ul       /**< \brief (ADC_STATUS) MASK Register */
 
 /* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/  16) Result -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -525,12 +540,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_RESULT_OFFSET           0x1A         /**< \brief (ADC_RESULT offset) Result */
-#define ADC_RESULT_RESETVALUE       _U(0x0000)   /**< \brief (ADC_RESULT reset_value) Result */
+#define ADC_RESULT_RESETVALUE       0x0000ul     /**< \brief (ADC_RESULT reset_value) Result */
 
 #define ADC_RESULT_RESULT_Pos       0            /**< \brief (ADC_RESULT) Result Conversion Value */
-#define ADC_RESULT_RESULT_Msk       (_U(0xFFFF) << ADC_RESULT_RESULT_Pos)
+#define ADC_RESULT_RESULT_Msk       (0xFFFFul << ADC_RESULT_RESULT_Pos)
 #define ADC_RESULT_RESULT(value)    (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
-#define ADC_RESULT_MASK             _U(0xFFFF)   /**< \brief (ADC_RESULT) MASK Register */
+#define ADC_RESULT_MASK             0xFFFFul     /**< \brief (ADC_RESULT) MASK Register */
 
 /* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -543,12 +558,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_WINLT_OFFSET            0x1C         /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
-#define ADC_WINLT_RESETVALUE        _U(0x0000)   /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
+#define ADC_WINLT_RESETVALUE        0x0000ul     /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
 
 #define ADC_WINLT_WINLT_Pos         0            /**< \brief (ADC_WINLT) Window Lower Threshold */
-#define ADC_WINLT_WINLT_Msk         (_U(0xFFFF) << ADC_WINLT_WINLT_Pos)
+#define ADC_WINLT_WINLT_Msk         (0xFFFFul << ADC_WINLT_WINLT_Pos)
 #define ADC_WINLT_WINLT(value)      (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
-#define ADC_WINLT_MASK              _U(0xFFFF)   /**< \brief (ADC_WINLT) MASK Register */
+#define ADC_WINLT_MASK              0xFFFFul     /**< \brief (ADC_WINLT) MASK Register */
 
 /* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -561,12 +576,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_WINUT_OFFSET            0x20         /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
-#define ADC_WINUT_RESETVALUE        _U(0x0000)   /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
+#define ADC_WINUT_RESETVALUE        0x0000ul     /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
 
 #define ADC_WINUT_WINUT_Pos         0            /**< \brief (ADC_WINUT) Window Upper Threshold */
-#define ADC_WINUT_WINUT_Msk         (_U(0xFFFF) << ADC_WINUT_WINUT_Pos)
+#define ADC_WINUT_WINUT_Msk         (0xFFFFul << ADC_WINUT_WINUT_Pos)
 #define ADC_WINUT_WINUT(value)      (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
-#define ADC_WINUT_MASK              _U(0xFFFF)   /**< \brief (ADC_WINUT) MASK Register */
+#define ADC_WINUT_MASK              0xFFFFul     /**< \brief (ADC_WINUT) MASK Register */
 
 /* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -580,12 +595,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_GAINCORR_OFFSET         0x24         /**< \brief (ADC_GAINCORR offset) Gain Correction */
-#define ADC_GAINCORR_RESETVALUE     _U(0x0000)   /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
+#define ADC_GAINCORR_RESETVALUE     0x0000ul     /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
 
 #define ADC_GAINCORR_GAINCORR_Pos   0            /**< \brief (ADC_GAINCORR) Gain Correction Value */
-#define ADC_GAINCORR_GAINCORR_Msk   (_U(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)
+#define ADC_GAINCORR_GAINCORR_Msk   (0xFFFul << ADC_GAINCORR_GAINCORR_Pos)
 #define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
-#define ADC_GAINCORR_MASK           _U(0x0FFF)   /**< \brief (ADC_GAINCORR) MASK Register */
+#define ADC_GAINCORR_MASK           0x0FFFul     /**< \brief (ADC_GAINCORR) MASK Register */
 
 /* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -599,12 +614,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_OFFSETCORR_OFFSET       0x26         /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
-#define ADC_OFFSETCORR_RESETVALUE   _U(0x0000)   /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
+#define ADC_OFFSETCORR_RESETVALUE   0x0000ul     /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
 
 #define ADC_OFFSETCORR_OFFSETCORR_Pos 0            /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
-#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)
+#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos)
 #define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
-#define ADC_OFFSETCORR_MASK         _U(0x0FFF)   /**< \brief (ADC_OFFSETCORR) MASK Register */
+#define ADC_OFFSETCORR_MASK         0x0FFFul     /**< \brief (ADC_OFFSETCORR) MASK Register */
 
 /* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -619,15 +634,15 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_CALIB_OFFSET            0x28         /**< \brief (ADC_CALIB offset) Calibration */
-#define ADC_CALIB_RESETVALUE        _U(0x0000)   /**< \brief (ADC_CALIB reset_value) Calibration */
+#define ADC_CALIB_RESETVALUE        0x0000ul     /**< \brief (ADC_CALIB reset_value) Calibration */
 
 #define ADC_CALIB_LINEARITY_CAL_Pos 0            /**< \brief (ADC_CALIB) Linearity Calibration Value */
-#define ADC_CALIB_LINEARITY_CAL_Msk (_U(0xFF) << ADC_CALIB_LINEARITY_CAL_Pos)
+#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos)
 #define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))
 #define ADC_CALIB_BIAS_CAL_Pos      8            /**< \brief (ADC_CALIB) Bias Calibration Value */
-#define ADC_CALIB_BIAS_CAL_Msk      (_U(0x7) << ADC_CALIB_BIAS_CAL_Pos)
+#define ADC_CALIB_BIAS_CAL_Msk      (0x7ul << ADC_CALIB_BIAS_CAL_Pos)
 #define ADC_CALIB_BIAS_CAL(value)   (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))
-#define ADC_CALIB_MASK              _U(0x07FF)   /**< \brief (ADC_CALIB) MASK Register */
+#define ADC_CALIB_MASK              0x07FFul     /**< \brief (ADC_CALIB) MASK Register */
 
 /* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W  8) Debug Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -641,11 +656,11 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define ADC_DBGCTRL_OFFSET          0x2A         /**< \brief (ADC_DBGCTRL offset) Debug Control */
-#define ADC_DBGCTRL_RESETVALUE      _U(0x00)     /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
+#define ADC_DBGCTRL_RESETVALUE      0x00ul       /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
 
 #define ADC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (ADC_DBGCTRL) Debug Run */
-#define ADC_DBGCTRL_DBGRUN          (_U(0x1) << ADC_DBGCTRL_DBGRUN_Pos)
-#define ADC_DBGCTRL_MASK            _U(0x01)     /**< \brief (ADC_DBGCTRL) MASK Register */
+#define ADC_DBGCTRL_DBGRUN          (0x1ul << ADC_DBGCTRL_DBGRUN_Pos)
+#define ADC_DBGCTRL_MASK            0x01ul       /**< \brief (ADC_DBGCTRL) MASK Register */
 
 /** \brief ADC hardware registers */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

asf/sam0/utils/cmsis/samd21/include/component/dac.h

@@ -3,24 +3,39 @@
  *
  * \brief Component description for DAC
  *
- * Copyright (c) 2017 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *
  * \asf_license_stop
  *
@@ -52,15 +67,15 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DAC_CTRLA_OFFSET            0x0          /**< \brief (DAC_CTRLA offset) Control A */
-#define DAC_CTRLA_RESETVALUE        _U(0x00)     /**< \brief (DAC_CTRLA reset_value) Control A */
+#define DAC_CTRLA_RESETVALUE        0x00ul       /**< \brief (DAC_CTRLA reset_value) Control A */
 
 #define DAC_CTRLA_SWRST_Pos         0            /**< \brief (DAC_CTRLA) Software Reset */
-#define DAC_CTRLA_SWRST             (_U(0x1) << DAC_CTRLA_SWRST_Pos)
+#define DAC_CTRLA_SWRST             (0x1ul << DAC_CTRLA_SWRST_Pos)
 #define DAC_CTRLA_ENABLE_Pos        1            /**< \brief (DAC_CTRLA) Enable */
-#define DAC_CTRLA_ENABLE            (_U(0x1) << DAC_CTRLA_ENABLE_Pos)
+#define DAC_CTRLA_ENABLE            (0x1ul << DAC_CTRLA_ENABLE_Pos)
 #define DAC_CTRLA_RUNSTDBY_Pos      2            /**< \brief (DAC_CTRLA) Run in Standby */
-#define DAC_CTRLA_RUNSTDBY          (_U(0x1) << DAC_CTRLA_RUNSTDBY_Pos)
-#define DAC_CTRLA_MASK              _U(0x07)     /**< \brief (DAC_CTRLA) MASK Register */
+#define DAC_CTRLA_RUNSTDBY          (0x1ul << DAC_CTRLA_RUNSTDBY_Pos)
+#define DAC_CTRLA_MASK              0x07ul       /**< \brief (DAC_CTRLA) MASK Register */
 
 /* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W  8) Control B -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -79,28 +94,28 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DAC_CTRLB_OFFSET            0x1          /**< \brief (DAC_CTRLB offset) Control B */
-#define DAC_CTRLB_RESETVALUE        _U(0x00)     /**< \brief (DAC_CTRLB reset_value) Control B */
+#define DAC_CTRLB_RESETVALUE        0x00ul       /**< \brief (DAC_CTRLB reset_value) Control B */
 
 #define DAC_CTRLB_EOEN_Pos          0            /**< \brief (DAC_CTRLB) External Output Enable */
-#define DAC_CTRLB_EOEN              (_U(0x1) << DAC_CTRLB_EOEN_Pos)
+#define DAC_CTRLB_EOEN              (0x1ul << DAC_CTRLB_EOEN_Pos)
 #define DAC_CTRLB_IOEN_Pos          1            /**< \brief (DAC_CTRLB) Internal Output Enable */
-#define DAC_CTRLB_IOEN              (_U(0x1) << DAC_CTRLB_IOEN_Pos)
+#define DAC_CTRLB_IOEN              (0x1ul << DAC_CTRLB_IOEN_Pos)
 #define DAC_CTRLB_LEFTADJ_Pos       2            /**< \brief (DAC_CTRLB) Left Adjusted Data */
-#define DAC_CTRLB_LEFTADJ           (_U(0x1) << DAC_CTRLB_LEFTADJ_Pos)
+#define DAC_CTRLB_LEFTADJ           (0x1ul << DAC_CTRLB_LEFTADJ_Pos)
 #define DAC_CTRLB_VPD_Pos           3            /**< \brief (DAC_CTRLB) Voltage Pump Disable */
-#define DAC_CTRLB_VPD               (_U(0x1) << DAC_CTRLB_VPD_Pos)
+#define DAC_CTRLB_VPD               (0x1ul << DAC_CTRLB_VPD_Pos)
 #define DAC_CTRLB_BDWP_Pos          4            /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
-#define DAC_CTRLB_BDWP              (_U(0x1) << DAC_CTRLB_BDWP_Pos)
+#define DAC_CTRLB_BDWP              (0x1ul << DAC_CTRLB_BDWP_Pos)
 #define DAC_CTRLB_REFSEL_Pos        6            /**< \brief (DAC_CTRLB) Reference Selection */
-#define DAC_CTRLB_REFSEL_Msk        (_U(0x3) << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_Msk        (0x3ul << DAC_CTRLB_REFSEL_Pos)
 #define DAC_CTRLB_REFSEL(value)     (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
-#define   DAC_CTRLB_REFSEL_INT1V_Val      _U(0x0)   /**< \brief (DAC_CTRLB) Internal 1.0V reference */
-#define   DAC_CTRLB_REFSEL_AVCC_Val       _U(0x1)   /**< \brief (DAC_CTRLB) AVCC */
-#define   DAC_CTRLB_REFSEL_VREFP_Val      _U(0x2)   /**< \brief (DAC_CTRLB) External reference */
+#define   DAC_CTRLB_REFSEL_INT1V_Val      0x0ul  /**< \brief (DAC_CTRLB) Internal 1.0V reference */
+#define   DAC_CTRLB_REFSEL_AVCC_Val       0x1ul  /**< \brief (DAC_CTRLB) AVCC */
+#define   DAC_CTRLB_REFSEL_VREFP_Val      0x2ul  /**< \brief (DAC_CTRLB) External reference */
 #define DAC_CTRLB_REFSEL_INT1V      (DAC_CTRLB_REFSEL_INT1V_Val    << DAC_CTRLB_REFSEL_Pos)
 #define DAC_CTRLB_REFSEL_AVCC       (DAC_CTRLB_REFSEL_AVCC_Val     << DAC_CTRLB_REFSEL_Pos)
 #define DAC_CTRLB_REFSEL_VREFP      (DAC_CTRLB_REFSEL_VREFP_Val    << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_MASK              _U(0xDF)     /**< \brief (DAC_CTRLB) MASK Register */
+#define DAC_CTRLB_MASK              0xDFul       /**< \brief (DAC_CTRLB) MASK Register */
 
 /* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W  8) Event Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -115,13 +130,13 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DAC_EVCTRL_OFFSET           0x2          /**< \brief (DAC_EVCTRL offset) Event Control */
-#define DAC_EVCTRL_RESETVALUE       _U(0x00)     /**< \brief (DAC_EVCTRL reset_value) Event Control */
+#define DAC_EVCTRL_RESETVALUE       0x00ul       /**< \brief (DAC_EVCTRL reset_value) Event Control */
 
 #define DAC_EVCTRL_STARTEI_Pos      0            /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
-#define DAC_EVCTRL_STARTEI          (_U(0x1) << DAC_EVCTRL_STARTEI_Pos)
+#define DAC_EVCTRL_STARTEI          (0x1ul << DAC_EVCTRL_STARTEI_Pos)
 #define DAC_EVCTRL_EMPTYEO_Pos      1            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
-#define DAC_EVCTRL_EMPTYEO          (_U(0x1) << DAC_EVCTRL_EMPTYEO_Pos)
-#define DAC_EVCTRL_MASK             _U(0x03)     /**< \brief (DAC_EVCTRL) MASK Register */
+#define DAC_EVCTRL_EMPTYEO          (0x1ul << DAC_EVCTRL_EMPTYEO_Pos)
+#define DAC_EVCTRL_MASK             0x03ul       /**< \brief (DAC_EVCTRL) MASK Register */
 
 /* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W  8) Interrupt Enable Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -137,15 +152,15 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DAC_INTENCLR_OFFSET         0x4          /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
-#define DAC_INTENCLR_RESETVALUE     _U(0x00)     /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
+#define DAC_INTENCLR_RESETVALUE     0x00ul       /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
 
 #define DAC_INTENCLR_UNDERRUN_Pos   0            /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
-#define DAC_INTENCLR_UNDERRUN       (_U(0x1) << DAC_INTENCLR_UNDERRUN_Pos)
+#define DAC_INTENCLR_UNDERRUN       (0x1ul << DAC_INTENCLR_UNDERRUN_Pos)
 #define DAC_INTENCLR_EMPTY_Pos      1            /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
-#define DAC_INTENCLR_EMPTY          (_U(0x1) << DAC_INTENCLR_EMPTY_Pos)
+#define DAC_INTENCLR_EMPTY          (0x1ul << DAC_INTENCLR_EMPTY_Pos)
 #define DAC_INTENCLR_SYNCRDY_Pos    2            /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
-#define DAC_INTENCLR_SYNCRDY        (_U(0x1) << DAC_INTENCLR_SYNCRDY_Pos)
-#define DAC_INTENCLR_MASK           _U(0x07)     /**< \brief (DAC_INTENCLR) MASK Register */
+#define DAC_INTENCLR_SYNCRDY        (0x1ul << DAC_INTENCLR_SYNCRDY_Pos)
+#define DAC_INTENCLR_MASK           0x07ul       /**< \brief (DAC_INTENCLR) MASK Register */
 
 /* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W  8) Interrupt Enable Set -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -161,15 +176,15 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DAC_INTENSET_OFFSET         0x5          /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
-#define DAC_INTENSET_RESETVALUE     _U(0x00)     /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
+#define DAC_INTENSET_RESETVALUE     0x00ul       /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
 
 #define DAC_INTENSET_UNDERRUN_Pos   0            /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
-#define DAC_INTENSET_UNDERRUN       (_U(0x1) << DAC_INTENSET_UNDERRUN_Pos)
+#define DAC_INTENSET_UNDERRUN       (0x1ul << DAC_INTENSET_UNDERRUN_Pos)
 #define DAC_INTENSET_EMPTY_Pos      1            /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
-#define DAC_INTENSET_EMPTY          (_U(0x1) << DAC_INTENSET_EMPTY_Pos)
+#define DAC_INTENSET_EMPTY          (0x1ul << DAC_INTENSET_EMPTY_Pos)
 #define DAC_INTENSET_SYNCRDY_Pos    2            /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
-#define DAC_INTENSET_SYNCRDY        (_U(0x1) << DAC_INTENSET_SYNCRDY_Pos)
-#define DAC_INTENSET_MASK           _U(0x07)     /**< \brief (DAC_INTENSET) MASK Register */
+#define DAC_INTENSET_SYNCRDY        (0x1ul << DAC_INTENSET_SYNCRDY_Pos)
+#define DAC_INTENSET_MASK           0x07ul       /**< \brief (DAC_INTENSET) MASK Register */
 
 /* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -185,15 +200,15 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DAC_INTFLAG_OFFSET          0x6          /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define DAC_INTFLAG_RESETVALUE      _U(0x00)     /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+#define DAC_INTFLAG_RESETVALUE      0x00ul       /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
 
 #define DAC_INTFLAG_UNDERRUN_Pos    0            /**< \brief (DAC_INTFLAG) Underrun */
-#define DAC_INTFLAG_UNDERRUN        (_U(0x1) << DAC_INTFLAG_UNDERRUN_Pos)
+#define DAC_INTFLAG_UNDERRUN        (0x1ul << DAC_INTFLAG_UNDERRUN_Pos)
 #define DAC_INTFLAG_EMPTY_Pos       1            /**< \brief (DAC_INTFLAG) Data Buffer Empty */
-#define DAC_INTFLAG_EMPTY           (_U(0x1) << DAC_INTFLAG_EMPTY_Pos)
+#define DAC_INTFLAG_EMPTY           (0x1ul << DAC_INTFLAG_EMPTY_Pos)
 #define DAC_INTFLAG_SYNCRDY_Pos     2            /**< \brief (DAC_INTFLAG) Synchronization Ready */
-#define DAC_INTFLAG_SYNCRDY         (_U(0x1) << DAC_INTFLAG_SYNCRDY_Pos)
-#define DAC_INTFLAG_MASK            _U(0x07)     /**< \brief (DAC_INTFLAG) MASK Register */
+#define DAC_INTFLAG_SYNCRDY         (0x1ul << DAC_INTFLAG_SYNCRDY_Pos)
+#define DAC_INTFLAG_MASK            0x07ul       /**< \brief (DAC_INTFLAG) MASK Register */
 
 /* -------- DAC_STATUS : (DAC Offset: 0x7) (R/   8) Status -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -207,11 +222,11 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DAC_STATUS_OFFSET           0x7          /**< \brief (DAC_STATUS offset) Status */
-#define DAC_STATUS_RESETVALUE       _U(0x00)     /**< \brief (DAC_STATUS reset_value) Status */
+#define DAC_STATUS_RESETVALUE       0x00ul       /**< \brief (DAC_STATUS reset_value) Status */
 
 #define DAC_STATUS_SYNCBUSY_Pos     7            /**< \brief (DAC_STATUS) Synchronization Busy Status */
-#define DAC_STATUS_SYNCBUSY         (_U(0x1) << DAC_STATUS_SYNCBUSY_Pos)
-#define DAC_STATUS_MASK             _U(0x80)     /**< \brief (DAC_STATUS) MASK Register */
+#define DAC_STATUS_SYNCBUSY         (0x1ul << DAC_STATUS_SYNCBUSY_Pos)
+#define DAC_STATUS_MASK             0x80ul       /**< \brief (DAC_STATUS) MASK Register */
 
 /* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -224,12 +239,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DAC_DATA_OFFSET             0x8          /**< \brief (DAC_DATA offset) Data */
-#define DAC_DATA_RESETVALUE         _U(0x0000)   /**< \brief (DAC_DATA reset_value) Data */
+#define DAC_DATA_RESETVALUE         0x0000ul     /**< \brief (DAC_DATA reset_value) Data */
 
 #define DAC_DATA_DATA_Pos           0            /**< \brief (DAC_DATA) Data value to be converted */
-#define DAC_DATA_DATA_Msk           (_U(0xFFFF) << DAC_DATA_DATA_Pos)
+#define DAC_DATA_DATA_Msk           (0xFFFFul << DAC_DATA_DATA_Pos)
 #define DAC_DATA_DATA(value)        (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
-#define DAC_DATA_MASK               _U(0xFFFF)   /**< \brief (DAC_DATA) MASK Register */
+#define DAC_DATA_MASK               0xFFFFul     /**< \brief (DAC_DATA) MASK Register */
 
 /* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -242,12 +257,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DAC_DATABUF_OFFSET          0xC          /**< \brief (DAC_DATABUF offset) Data Buffer */
-#define DAC_DATABUF_RESETVALUE      _U(0x0000)   /**< \brief (DAC_DATABUF reset_value) Data Buffer */
+#define DAC_DATABUF_RESETVALUE      0x0000ul     /**< \brief (DAC_DATABUF reset_value) Data Buffer */
 
 #define DAC_DATABUF_DATABUF_Pos     0            /**< \brief (DAC_DATABUF) Data Buffer */
-#define DAC_DATABUF_DATABUF_Msk     (_U(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
+#define DAC_DATABUF_DATABUF_Msk     (0xFFFFul << DAC_DATABUF_DATABUF_Pos)
 #define DAC_DATABUF_DATABUF(value)  (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
-#define DAC_DATABUF_MASK            _U(0xFFFF)   /**< \brief (DAC_DATABUF) MASK Register */
+#define DAC_DATABUF_MASK            0xFFFFul     /**< \brief (DAC_DATABUF) MASK Register */
 
 /** \brief DAC hardware registers */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

asf/sam0/utils/cmsis/samd21/include/component/dmac.h

@@ -3,24 +3,39 @@
  *
  * \brief Component description for DMAC
  *
- * Copyright (c) 2016 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *
  * \asf_license_stop
  *
@@ -62,14 +77,14 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_CTRL_OFFSET            0x00         /**< \brief (DMAC_CTRL offset) Control */
-#define DMAC_CTRL_RESETVALUE        _U(0x0000)   /**< \brief (DMAC_CTRL reset_value) Control */
+#define DMAC_CTRL_RESETVALUE        0x0000ul     /**< \brief (DMAC_CTRL reset_value) Control */
 
 #define DMAC_CTRL_SWRST_Pos         0            /**< \brief (DMAC_CTRL) Software Reset */
-#define DMAC_CTRL_SWRST             (_U(0x1) << DMAC_CTRL_SWRST_Pos)
+#define DMAC_CTRL_SWRST             (0x1ul << DMAC_CTRL_SWRST_Pos)
 #define DMAC_CTRL_DMAENABLE_Pos     1            /**< \brief (DMAC_CTRL) DMA Enable */
-#define DMAC_CTRL_DMAENABLE         (_U(0x1) << DMAC_CTRL_DMAENABLE_Pos)
+#define DMAC_CTRL_DMAENABLE         (0x1ul << DMAC_CTRL_DMAENABLE_Pos)
 #define DMAC_CTRL_CRCENABLE_Pos     2            /**< \brief (DMAC_CTRL) CRC Enable */
-#define DMAC_CTRL_CRCENABLE         (_U(0x1) << DMAC_CTRL_CRCENABLE_Pos)
+#define DMAC_CTRL_CRCENABLE         (0x1ul << DMAC_CTRL_CRCENABLE_Pos)
 #define DMAC_CTRL_LVLEN0_Pos        8            /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
 #define DMAC_CTRL_LVLEN0            (1 << DMAC_CTRL_LVLEN0_Pos)
 #define DMAC_CTRL_LVLEN1_Pos        9            /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
@@ -79,9 +94,9 @@ typedef union {
 #define DMAC_CTRL_LVLEN3_Pos        11           /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
 #define DMAC_CTRL_LVLEN3            (1 << DMAC_CTRL_LVLEN3_Pos)
 #define DMAC_CTRL_LVLEN_Pos         8            /**< \brief (DMAC_CTRL) Priority Level x Enable */
-#define DMAC_CTRL_LVLEN_Msk         (_U(0xF) << DMAC_CTRL_LVLEN_Pos)
+#define DMAC_CTRL_LVLEN_Msk         (0xFul << DMAC_CTRL_LVLEN_Pos)
 #define DMAC_CTRL_LVLEN(value)      (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
-#define DMAC_CTRL_MASK              _U(0x0F07)   /**< \brief (DMAC_CTRL) MASK Register */
+#define DMAC_CTRL_MASK              0x0F07ul     /**< \brief (DMAC_CTRL) MASK Register */
 
 /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -98,32 +113,32 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_CRCCTRL_OFFSET         0x02         /**< \brief (DMAC_CRCCTRL offset) CRC Control */
-#define DMAC_CRCCTRL_RESETVALUE     _U(0x0000)   /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
+#define DMAC_CRCCTRL_RESETVALUE     0x0000ul     /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
 
 #define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0            /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
-#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
 #define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
-#define   DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U(0x0)   /**< \brief (DMAC_CRCCTRL) Byte bus access */
-#define   DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U(0x1)   /**< \brief (DMAC_CRCCTRL) Half-word bus access */
-#define   DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U(0x2)   /**< \brief (DMAC_CRCCTRL) Word bus access */
+#define   DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul  /**< \brief (DMAC_CRCCTRL) Byte bus access */
+#define   DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul  /**< \brief (DMAC_CRCCTRL) Half-word bus access */
+#define   DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul  /**< \brief (DMAC_CRCCTRL) Word bus access */
 #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
 #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
 #define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
 #define DMAC_CRCCTRL_CRCPOLY_Pos    2            /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
-#define DMAC_CRCCTRL_CRCPOLY_Msk    (_U(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_Msk    (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos)
 #define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
-#define   DMAC_CRCCTRL_CRCPOLY_CRC16_Val  _U(0x0)   /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
-#define   DMAC_CRCCTRL_CRCPOLY_CRC32_Val  _U(0x1)   /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
+#define   DMAC_CRCCTRL_CRCPOLY_CRC16_Val  0x0ul  /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
+#define   DMAC_CRCCTRL_CRCPOLY_CRC32_Val  0x1ul  /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
 #define DMAC_CRCCTRL_CRCPOLY_CRC16  (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
 #define DMAC_CRCCTRL_CRCPOLY_CRC32  (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
 #define DMAC_CRCCTRL_CRCSRC_Pos     8            /**< \brief (DMAC_CRCCTRL) CRC Input Source */
-#define DMAC_CRCCTRL_CRCSRC_Msk     (_U(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC_Msk     (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos)
 #define DMAC_CRCCTRL_CRCSRC(value)  (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
-#define   DMAC_CRCCTRL_CRCSRC_NOACT_Val   _U(0x0)   /**< \brief (DMAC_CRCCTRL) No action */
-#define   DMAC_CRCCTRL_CRCSRC_IO_Val      _U(0x1)   /**< \brief (DMAC_CRCCTRL) I/O interface */
+#define   DMAC_CRCCTRL_CRCSRC_NOACT_Val   0x0ul  /**< \brief (DMAC_CRCCTRL) No action */
+#define   DMAC_CRCCTRL_CRCSRC_IO_Val      0x1ul  /**< \brief (DMAC_CRCCTRL) I/O interface */
 #define DMAC_CRCCTRL_CRCSRC_NOACT   (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
 #define DMAC_CRCCTRL_CRCSRC_IO      (DMAC_CRCCTRL_CRCSRC_IO_Val    << DMAC_CRCCTRL_CRCSRC_Pos)
-#define DMAC_CRCCTRL_MASK           _U(0x3F0F)   /**< \brief (DMAC_CRCCTRL) MASK Register */
+#define DMAC_CRCCTRL_MASK           0x3F0Ful     /**< \brief (DMAC_CRCCTRL) MASK Register */
 
 /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -136,12 +151,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_CRCDATAIN_OFFSET       0x04         /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
-#define DMAC_CRCDATAIN_RESETVALUE   _U(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
+#define DMAC_CRCDATAIN_RESETVALUE   0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
 
 #define DMAC_CRCDATAIN_CRCDATAIN_Pos 0            /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
-#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos)
+#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos)
 #define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
-#define DMAC_CRCDATAIN_MASK         _U(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */
+#define DMAC_CRCDATAIN_MASK         0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */
 
 /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -154,12 +169,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_CRCCHKSUM_OFFSET       0x08         /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
-#define DMAC_CRCCHKSUM_RESETVALUE   _U(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
+#define DMAC_CRCCHKSUM_RESETVALUE   0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
 
 #define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0            /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
-#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
 #define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
-#define DMAC_CRCCHKSUM_MASK         _U(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */
+#define DMAC_CRCCHKSUM_MASK         0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */
 
 /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W  8) CRC Status -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -174,13 +189,13 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_CRCSTATUS_OFFSET       0x0C         /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
-#define DMAC_CRCSTATUS_RESETVALUE   _U(0x00)     /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
+#define DMAC_CRCSTATUS_RESETVALUE   0x00ul       /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
 
 #define DMAC_CRCSTATUS_CRCBUSY_Pos  0            /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
-#define DMAC_CRCSTATUS_CRCBUSY      (_U(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos)
+#define DMAC_CRCSTATUS_CRCBUSY      (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos)
 #define DMAC_CRCSTATUS_CRCZERO_Pos  1            /**< \brief (DMAC_CRCSTATUS) CRC Zero */
-#define DMAC_CRCSTATUS_CRCZERO      (_U(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos)
-#define DMAC_CRCSTATUS_MASK         _U(0x03)     /**< \brief (DMAC_CRCSTATUS) MASK Register */
+#define DMAC_CRCSTATUS_CRCZERO      (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos)
+#define DMAC_CRCSTATUS_MASK         0x03ul       /**< \brief (DMAC_CRCSTATUS) MASK Register */
 
 /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W  8) Debug Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -194,11 +209,11 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_DBGCTRL_OFFSET         0x0D         /**< \brief (DMAC_DBGCTRL offset) Debug Control */
-#define DMAC_DBGCTRL_RESETVALUE     _U(0x00)     /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
+#define DMAC_DBGCTRL_RESETVALUE     0x00ul       /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
 
 #define DMAC_DBGCTRL_DBGRUN_Pos     0            /**< \brief (DMAC_DBGCTRL) Debug Run */
-#define DMAC_DBGCTRL_DBGRUN         (_U(0x1) << DMAC_DBGCTRL_DBGRUN_Pos)
-#define DMAC_DBGCTRL_MASK           _U(0x01)     /**< \brief (DMAC_DBGCTRL) MASK Register */
+#define DMAC_DBGCTRL_DBGRUN         (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos)
+#define DMAC_DBGCTRL_MASK           0x01ul       /**< \brief (DMAC_DBGCTRL) MASK Register */
 
 /* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W  8) QOS Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -214,42 +229,42 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_QOSCTRL_OFFSET         0x0E         /**< \brief (DMAC_QOSCTRL offset) QOS Control */
-#define DMAC_QOSCTRL_RESETVALUE     _U(0x15)     /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */
+#define DMAC_QOSCTRL_RESETVALUE     0x15ul       /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */
 
 #define DMAC_QOSCTRL_WRBQOS_Pos     0            /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */
-#define DMAC_QOSCTRL_WRBQOS_Msk     (_U(0x3) << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_Msk     (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos)
 #define DMAC_QOSCTRL_WRBQOS(value)  (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos))
-#define   DMAC_QOSCTRL_WRBQOS_DISABLE_Val _U(0x0)   /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
-#define   DMAC_QOSCTRL_WRBQOS_LOW_Val     _U(0x1)   /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
-#define   DMAC_QOSCTRL_WRBQOS_MEDIUM_Val  _U(0x2)   /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
-#define   DMAC_QOSCTRL_WRBQOS_HIGH_Val    _U(0x3)   /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define   DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul  /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define   DMAC_QOSCTRL_WRBQOS_LOW_Val     0x1ul  /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define   DMAC_QOSCTRL_WRBQOS_MEDIUM_Val  0x2ul  /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define   DMAC_QOSCTRL_WRBQOS_HIGH_Val    0x3ul  /**< \brief (DMAC_QOSCTRL) Critical Latency */
 #define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos)
 #define DMAC_QOSCTRL_WRBQOS_LOW     (DMAC_QOSCTRL_WRBQOS_LOW_Val   << DMAC_QOSCTRL_WRBQOS_Pos)
 #define DMAC_QOSCTRL_WRBQOS_MEDIUM  (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos)
 #define DMAC_QOSCTRL_WRBQOS_HIGH    (DMAC_QOSCTRL_WRBQOS_HIGH_Val  << DMAC_QOSCTRL_WRBQOS_Pos)
 #define DMAC_QOSCTRL_FQOS_Pos       2            /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */
-#define DMAC_QOSCTRL_FQOS_Msk       (_U(0x3) << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_Msk       (0x3ul << DMAC_QOSCTRL_FQOS_Pos)
 #define DMAC_QOSCTRL_FQOS(value)    (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos))
-#define   DMAC_QOSCTRL_FQOS_DISABLE_Val   _U(0x0)   /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
-#define   DMAC_QOSCTRL_FQOS_LOW_Val       _U(0x1)   /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
-#define   DMAC_QOSCTRL_FQOS_MEDIUM_Val    _U(0x2)   /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
-#define   DMAC_QOSCTRL_FQOS_HIGH_Val      _U(0x3)   /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define   DMAC_QOSCTRL_FQOS_DISABLE_Val   0x0ul  /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define   DMAC_QOSCTRL_FQOS_LOW_Val       0x1ul  /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define   DMAC_QOSCTRL_FQOS_MEDIUM_Val    0x2ul  /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define   DMAC_QOSCTRL_FQOS_HIGH_Val      0x3ul  /**< \brief (DMAC_QOSCTRL) Critical Latency */
 #define DMAC_QOSCTRL_FQOS_DISABLE   (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos)
 #define DMAC_QOSCTRL_FQOS_LOW       (DMAC_QOSCTRL_FQOS_LOW_Val     << DMAC_QOSCTRL_FQOS_Pos)
 #define DMAC_QOSCTRL_FQOS_MEDIUM    (DMAC_QOSCTRL_FQOS_MEDIUM_Val  << DMAC_QOSCTRL_FQOS_Pos)
 #define DMAC_QOSCTRL_FQOS_HIGH      (DMAC_QOSCTRL_FQOS_HIGH_Val    << DMAC_QOSCTRL_FQOS_Pos)
 #define DMAC_QOSCTRL_DQOS_Pos       4            /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */
-#define DMAC_QOSCTRL_DQOS_Msk       (_U(0x3) << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_Msk       (0x3ul << DMAC_QOSCTRL_DQOS_Pos)
 #define DMAC_QOSCTRL_DQOS(value)    (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos))
-#define   DMAC_QOSCTRL_DQOS_DISABLE_Val   _U(0x0)   /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
-#define   DMAC_QOSCTRL_DQOS_LOW_Val       _U(0x1)   /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
-#define   DMAC_QOSCTRL_DQOS_MEDIUM_Val    _U(0x2)   /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
-#define   DMAC_QOSCTRL_DQOS_HIGH_Val      _U(0x3)   /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define   DMAC_QOSCTRL_DQOS_DISABLE_Val   0x0ul  /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define   DMAC_QOSCTRL_DQOS_LOW_Val       0x1ul  /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define   DMAC_QOSCTRL_DQOS_MEDIUM_Val    0x2ul  /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define   DMAC_QOSCTRL_DQOS_HIGH_Val      0x3ul  /**< \brief (DMAC_QOSCTRL) Critical Latency */
 #define DMAC_QOSCTRL_DQOS_DISABLE   (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos)
 #define DMAC_QOSCTRL_DQOS_LOW       (DMAC_QOSCTRL_DQOS_LOW_Val     << DMAC_QOSCTRL_DQOS_Pos)
 #define DMAC_QOSCTRL_DQOS_MEDIUM    (DMAC_QOSCTRL_DQOS_MEDIUM_Val  << DMAC_QOSCTRL_DQOS_Pos)
 #define DMAC_QOSCTRL_DQOS_HIGH      (DMAC_QOSCTRL_DQOS_HIGH_Val    << DMAC_QOSCTRL_DQOS_Pos)
-#define DMAC_QOSCTRL_MASK           _U(0x3F)     /**< \brief (DMAC_QOSCTRL) MASK Register */
+#define DMAC_QOSCTRL_MASK           0x3Ful       /**< \brief (DMAC_QOSCTRL) MASK Register */
 
 /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -278,7 +293,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_SWTRIGCTRL_OFFSET      0x10         /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
-#define DMAC_SWTRIGCTRL_RESETVALUE  _U(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
+#define DMAC_SWTRIGCTRL_RESETVALUE  0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
 
 #define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0            /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
 #define DMAC_SWTRIGCTRL_SWTRIG0     (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
@@ -305,9 +320,9 @@ typedef union {
 #define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11           /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
 #define DMAC_SWTRIGCTRL_SWTRIG11    (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
 #define DMAC_SWTRIGCTRL_SWTRIG_Pos  0            /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG_Msk  (_U(0xFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG_Msk  (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos)
 #define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
-#define DMAC_SWTRIGCTRL_MASK        _U(0x00000FFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
+#define DMAC_SWTRIGCTRL_MASK        0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
 
 /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -331,29 +346,29 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_PRICTRL0_OFFSET        0x14         /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
-#define DMAC_PRICTRL0_RESETVALUE    _U(0x00000000) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
+#define DMAC_PRICTRL0_RESETVALUE    0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
 
 #define DMAC_PRICTRL0_LVLPRI0_Pos   0            /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI0_Msk   (_U(0xF) << DMAC_PRICTRL0_LVLPRI0_Pos)
+#define DMAC_PRICTRL0_LVLPRI0_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos)
 #define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
 #define DMAC_PRICTRL0_RRLVLEN0_Pos  7            /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN0      (_U(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos)
+#define DMAC_PRICTRL0_RRLVLEN0      (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos)
 #define DMAC_PRICTRL0_LVLPRI1_Pos   8            /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI1_Msk   (_U(0xF) << DMAC_PRICTRL0_LVLPRI1_Pos)
+#define DMAC_PRICTRL0_LVLPRI1_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos)
 #define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
 #define DMAC_PRICTRL0_RRLVLEN1_Pos  15           /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN1      (_U(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos)
+#define DMAC_PRICTRL0_RRLVLEN1      (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos)
 #define DMAC_PRICTRL0_LVLPRI2_Pos   16           /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI2_Msk   (_U(0xF) << DMAC_PRICTRL0_LVLPRI2_Pos)
+#define DMAC_PRICTRL0_LVLPRI2_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos)
 #define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
 #define DMAC_PRICTRL0_RRLVLEN2_Pos  23           /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN2      (_U(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos)
+#define DMAC_PRICTRL0_RRLVLEN2      (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos)
 #define DMAC_PRICTRL0_LVLPRI3_Pos   24           /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI3_Msk   (_U(0xF) << DMAC_PRICTRL0_LVLPRI3_Pos)
+#define DMAC_PRICTRL0_LVLPRI3_Msk   (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos)
 #define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
 #define DMAC_PRICTRL0_RRLVLEN3_Pos  31           /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN3      (_U(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos)
-#define DMAC_PRICTRL0_MASK          _U(0x8F8F8F8F) /**< \brief (DMAC_PRICTRL0) MASK Register */
+#define DMAC_PRICTRL0_RRLVLEN3      (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos)
+#define DMAC_PRICTRL0_MASK          0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */
 
 /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -374,24 +389,24 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_INTPEND_OFFSET         0x20         /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
-#define DMAC_INTPEND_RESETVALUE     _U(0x0000)   /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
+#define DMAC_INTPEND_RESETVALUE     0x0000ul     /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
 
 #define DMAC_INTPEND_ID_Pos         0            /**< \brief (DMAC_INTPEND) Channel ID */
-#define DMAC_INTPEND_ID_Msk         (_U(0xF) << DMAC_INTPEND_ID_Pos)
+#define DMAC_INTPEND_ID_Msk         (0xFul << DMAC_INTPEND_ID_Pos)
 #define DMAC_INTPEND_ID(value)      (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
 #define DMAC_INTPEND_TERR_Pos       8            /**< \brief (DMAC_INTPEND) Transfer Error */
-#define DMAC_INTPEND_TERR           (_U(0x1) << DMAC_INTPEND_TERR_Pos)
+#define DMAC_INTPEND_TERR           (0x1ul << DMAC_INTPEND_TERR_Pos)
 #define DMAC_INTPEND_TCMPL_Pos      9            /**< \brief (DMAC_INTPEND) Transfer Complete */
-#define DMAC_INTPEND_TCMPL          (_U(0x1) << DMAC_INTPEND_TCMPL_Pos)
+#define DMAC_INTPEND_TCMPL          (0x1ul << DMAC_INTPEND_TCMPL_Pos)
 #define DMAC_INTPEND_SUSP_Pos       10           /**< \brief (DMAC_INTPEND) Channel Suspend */
-#define DMAC_INTPEND_SUSP           (_U(0x1) << DMAC_INTPEND_SUSP_Pos)
+#define DMAC_INTPEND_SUSP           (0x1ul << DMAC_INTPEND_SUSP_Pos)
 #define DMAC_INTPEND_FERR_Pos       13           /**< \brief (DMAC_INTPEND) Fetch Error */
-#define DMAC_INTPEND_FERR           (_U(0x1) << DMAC_INTPEND_FERR_Pos)
+#define DMAC_INTPEND_FERR           (0x1ul << DMAC_INTPEND_FERR_Pos)
 #define DMAC_INTPEND_BUSY_Pos       14           /**< \brief (DMAC_INTPEND) Busy */
-#define DMAC_INTPEND_BUSY           (_U(0x1) << DMAC_INTPEND_BUSY_Pos)
+#define DMAC_INTPEND_BUSY           (0x1ul << DMAC_INTPEND_BUSY_Pos)
 #define DMAC_INTPEND_PEND_Pos       15           /**< \brief (DMAC_INTPEND) Pending */
-#define DMAC_INTPEND_PEND           (_U(0x1) << DMAC_INTPEND_PEND_Pos)
-#define DMAC_INTPEND_MASK           _U(0xE70F)   /**< \brief (DMAC_INTPEND) MASK Register */
+#define DMAC_INTPEND_PEND           (0x1ul << DMAC_INTPEND_PEND_Pos)
+#define DMAC_INTPEND_MASK           0xE70Ful     /**< \brief (DMAC_INTPEND) MASK Register */
 
 /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/  32) Interrupt Status -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -420,7 +435,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_INTSTATUS_OFFSET       0x24         /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
-#define DMAC_INTSTATUS_RESETVALUE   _U(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
+#define DMAC_INTSTATUS_RESETVALUE   0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
 
 #define DMAC_INTSTATUS_CHINT0_Pos   0            /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
 #define DMAC_INTSTATUS_CHINT0       (1 << DMAC_INTSTATUS_CHINT0_Pos)
@@ -447,9 +462,9 @@ typedef union {
 #define DMAC_INTSTATUS_CHINT11_Pos  11           /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
 #define DMAC_INTSTATUS_CHINT11      (1 << DMAC_INTSTATUS_CHINT11_Pos)
 #define DMAC_INTSTATUS_CHINT_Pos    0            /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT_Msk    (_U(0xFFF) << DMAC_INTSTATUS_CHINT_Pos)
+#define DMAC_INTSTATUS_CHINT_Msk    (0xFFFul << DMAC_INTSTATUS_CHINT_Pos)
 #define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
-#define DMAC_INTSTATUS_MASK         _U(0x00000FFF) /**< \brief (DMAC_INTSTATUS) MASK Register */
+#define DMAC_INTSTATUS_MASK         0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */
 
 /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/  32) Busy Channels -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -478,7 +493,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_BUSYCH_OFFSET          0x28         /**< \brief (DMAC_BUSYCH offset) Busy Channels */
-#define DMAC_BUSYCH_RESETVALUE      _U(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
+#define DMAC_BUSYCH_RESETVALUE      0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
 
 #define DMAC_BUSYCH_BUSYCH0_Pos     0            /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
 #define DMAC_BUSYCH_BUSYCH0         (1 << DMAC_BUSYCH_BUSYCH0_Pos)
@@ -505,9 +520,9 @@ typedef union {
 #define DMAC_BUSYCH_BUSYCH11_Pos    11           /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
 #define DMAC_BUSYCH_BUSYCH11        (1 << DMAC_BUSYCH_BUSYCH11_Pos)
 #define DMAC_BUSYCH_BUSYCH_Pos      0            /**< \brief (DMAC_BUSYCH) Busy Channel x */
-#define DMAC_BUSYCH_BUSYCH_Msk      (_U(0xFFF) << DMAC_BUSYCH_BUSYCH_Pos)
+#define DMAC_BUSYCH_BUSYCH_Msk      (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos)
 #define DMAC_BUSYCH_BUSYCH(value)   (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
-#define DMAC_BUSYCH_MASK            _U(0x00000FFF) /**< \brief (DMAC_BUSYCH) MASK Register */
+#define DMAC_BUSYCH_MASK            0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */
 
 /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/  32) Pending Channels -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -536,7 +551,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_PENDCH_OFFSET          0x2C         /**< \brief (DMAC_PENDCH offset) Pending Channels */
-#define DMAC_PENDCH_RESETVALUE      _U(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
+#define DMAC_PENDCH_RESETVALUE      0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
 
 #define DMAC_PENDCH_PENDCH0_Pos     0            /**< \brief (DMAC_PENDCH) Pending Channel 0 */
 #define DMAC_PENDCH_PENDCH0         (1 << DMAC_PENDCH_PENDCH0_Pos)
@@ -563,9 +578,9 @@ typedef union {
 #define DMAC_PENDCH_PENDCH11_Pos    11           /**< \brief (DMAC_PENDCH) Pending Channel 11 */
 #define DMAC_PENDCH_PENDCH11        (1 << DMAC_PENDCH_PENDCH11_Pos)
 #define DMAC_PENDCH_PENDCH_Pos      0            /**< \brief (DMAC_PENDCH) Pending Channel x */
-#define DMAC_PENDCH_PENDCH_Msk      (_U(0xFFF) << DMAC_PENDCH_PENDCH_Pos)
+#define DMAC_PENDCH_PENDCH_Msk      (0xFFFul << DMAC_PENDCH_PENDCH_Pos)
 #define DMAC_PENDCH_PENDCH(value)   (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
-#define DMAC_PENDCH_MASK            _U(0x00000FFF) /**< \brief (DMAC_PENDCH) MASK Register */
+#define DMAC_PENDCH_MASK            0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */
 
 /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/  32) Active Channel and Levels -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -590,7 +605,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_ACTIVE_OFFSET          0x30         /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
-#define DMAC_ACTIVE_RESETVALUE      _U(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
+#define DMAC_ACTIVE_RESETVALUE      0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
 
 #define DMAC_ACTIVE_LVLEX0_Pos      0            /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
 #define DMAC_ACTIVE_LVLEX0          (1 << DMAC_ACTIVE_LVLEX0_Pos)
@@ -601,17 +616,17 @@ typedef union {
 #define DMAC_ACTIVE_LVLEX3_Pos      3            /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
 #define DMAC_ACTIVE_LVLEX3          (1 << DMAC_ACTIVE_LVLEX3_Pos)
 #define DMAC_ACTIVE_LVLEX_Pos       0            /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX_Msk       (_U(0xF) << DMAC_ACTIVE_LVLEX_Pos)
+#define DMAC_ACTIVE_LVLEX_Msk       (0xFul << DMAC_ACTIVE_LVLEX_Pos)
 #define DMAC_ACTIVE_LVLEX(value)    (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
 #define DMAC_ACTIVE_ID_Pos          8            /**< \brief (DMAC_ACTIVE) Active Channel ID */
-#define DMAC_ACTIVE_ID_Msk          (_U(0x1F) << DMAC_ACTIVE_ID_Pos)
+#define DMAC_ACTIVE_ID_Msk          (0x1Ful << DMAC_ACTIVE_ID_Pos)
 #define DMAC_ACTIVE_ID(value)       (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
 #define DMAC_ACTIVE_ABUSY_Pos       15           /**< \brief (DMAC_ACTIVE) Active Channel Busy */
-#define DMAC_ACTIVE_ABUSY           (_U(0x1) << DMAC_ACTIVE_ABUSY_Pos)
+#define DMAC_ACTIVE_ABUSY           (0x1ul << DMAC_ACTIVE_ABUSY_Pos)
 #define DMAC_ACTIVE_BTCNT_Pos       16           /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
-#define DMAC_ACTIVE_BTCNT_Msk       (_U(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos)
+#define DMAC_ACTIVE_BTCNT_Msk       (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos)
 #define DMAC_ACTIVE_BTCNT(value)    (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
-#define DMAC_ACTIVE_MASK            _U(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */
+#define DMAC_ACTIVE_MASK            0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */
 
 /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -624,12 +639,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_BASEADDR_OFFSET        0x34         /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
-#define DMAC_BASEADDR_RESETVALUE    _U(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
+#define DMAC_BASEADDR_RESETVALUE    0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
 
 #define DMAC_BASEADDR_BASEADDR_Pos  0            /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
-#define DMAC_BASEADDR_BASEADDR_Msk  (_U(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos)
+#define DMAC_BASEADDR_BASEADDR_Msk  (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos)
 #define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
-#define DMAC_BASEADDR_MASK          _U(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */
+#define DMAC_BASEADDR_MASK          0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */
 
 /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -642,12 +657,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_WRBADDR_OFFSET         0x38         /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
-#define DMAC_WRBADDR_RESETVALUE     _U(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
+#define DMAC_WRBADDR_RESETVALUE     0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
 
 #define DMAC_WRBADDR_WRBADDR_Pos    0            /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
-#define DMAC_WRBADDR_WRBADDR_Msk    (_U(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos)
+#define DMAC_WRBADDR_WRBADDR_Msk    (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos)
 #define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
-#define DMAC_WRBADDR_MASK           _U(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */
+#define DMAC_WRBADDR_MASK           0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */
 
 /* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W  8) Channel ID -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -661,12 +676,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_CHID_OFFSET            0x3F         /**< \brief (DMAC_CHID offset) Channel ID */
-#define DMAC_CHID_RESETVALUE        _U(0x00)     /**< \brief (DMAC_CHID reset_value) Channel ID */
+#define DMAC_CHID_RESETVALUE        0x00ul       /**< \brief (DMAC_CHID reset_value) Channel ID */
 
 #define DMAC_CHID_ID_Pos            0            /**< \brief (DMAC_CHID) Channel ID */
-#define DMAC_CHID_ID_Msk            (_U(0xF) << DMAC_CHID_ID_Pos)
+#define DMAC_CHID_ID_Msk            (0xFul << DMAC_CHID_ID_Pos)
 #define DMAC_CHID_ID(value)         (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))
-#define DMAC_CHID_MASK              _U(0x0F)     /**< \brief (DMAC_CHID) MASK Register */
+#define DMAC_CHID_MASK              0x0Ful       /**< \brief (DMAC_CHID) MASK Register */
 
 /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W  8) Channel Control A -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -681,13 +696,13 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_CHCTRLA_OFFSET         0x40         /**< \brief (DMAC_CHCTRLA offset) Channel Control A */
-#define DMAC_CHCTRLA_RESETVALUE     _U(0x00)     /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */
+#define DMAC_CHCTRLA_RESETVALUE     0x00ul       /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */
 
 #define DMAC_CHCTRLA_SWRST_Pos      0            /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
-#define DMAC_CHCTRLA_SWRST          (_U(0x1) << DMAC_CHCTRLA_SWRST_Pos)
+#define DMAC_CHCTRLA_SWRST          (0x1ul << DMAC_CHCTRLA_SWRST_Pos)
 #define DMAC_CHCTRLA_ENABLE_Pos     1            /**< \brief (DMAC_CHCTRLA) Channel Enable */
-#define DMAC_CHCTRLA_ENABLE         (_U(0x1) << DMAC_CHCTRLA_ENABLE_Pos)
-#define DMAC_CHCTRLA_MASK           _U(0x03)     /**< \brief (DMAC_CHCTRLA) MASK Register */
+#define DMAC_CHCTRLA_ENABLE         (0x1ul << DMAC_CHCTRLA_ENABLE_Pos)
+#define DMAC_CHCTRLA_MASK           0x03ul       /**< \brief (DMAC_CHCTRLA) MASK Register */
 
 /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -709,18 +724,18 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_CHCTRLB_OFFSET         0x44         /**< \brief (DMAC_CHCTRLB offset) Channel Control B */
-#define DMAC_CHCTRLB_RESETVALUE     _U(0x00000000) /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */
+#define DMAC_CHCTRLB_RESETVALUE     0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */
 
 #define DMAC_CHCTRLB_EVACT_Pos      0            /**< \brief (DMAC_CHCTRLB) Event Input Action */
-#define DMAC_CHCTRLB_EVACT_Msk      (_U(0x7) << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_Msk      (0x7ul << DMAC_CHCTRLB_EVACT_Pos)
 #define DMAC_CHCTRLB_EVACT(value)   (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))
-#define   DMAC_CHCTRLB_EVACT_NOACT_Val    _U(0x0)   /**< \brief (DMAC_CHCTRLB) No action */
-#define   DMAC_CHCTRLB_EVACT_TRIG_Val     _U(0x1)   /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
-#define   DMAC_CHCTRLB_EVACT_CTRIG_Val    _U(0x2)   /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
-#define   DMAC_CHCTRLB_EVACT_CBLOCK_Val   _U(0x3)   /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
-#define   DMAC_CHCTRLB_EVACT_SUSPEND_Val  _U(0x4)   /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
-#define   DMAC_CHCTRLB_EVACT_RESUME_Val   _U(0x5)   /**< \brief (DMAC_CHCTRLB) Channel resume operation */
-#define   DMAC_CHCTRLB_EVACT_SSKIP_Val    _U(0x6)   /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
+#define   DMAC_CHCTRLB_EVACT_NOACT_Val    0x0ul  /**< \brief (DMAC_CHCTRLB) No action */
+#define   DMAC_CHCTRLB_EVACT_TRIG_Val     0x1ul  /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
+#define   DMAC_CHCTRLB_EVACT_CTRIG_Val    0x2ul  /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
+#define   DMAC_CHCTRLB_EVACT_CBLOCK_Val   0x3ul  /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
+#define   DMAC_CHCTRLB_EVACT_SUSPEND_Val  0x4ul  /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define   DMAC_CHCTRLB_EVACT_RESUME_Val   0x5ul  /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define   DMAC_CHCTRLB_EVACT_SSKIP_Val    0x6ul  /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
 #define DMAC_CHCTRLB_EVACT_NOACT    (DMAC_CHCTRLB_EVACT_NOACT_Val  << DMAC_CHCTRLB_EVACT_Pos)
 #define DMAC_CHCTRLB_EVACT_TRIG     (DMAC_CHCTRLB_EVACT_TRIG_Val   << DMAC_CHCTRLB_EVACT_Pos)
 #define DMAC_CHCTRLB_EVACT_CTRIG    (DMAC_CHCTRLB_EVACT_CTRIG_Val  << DMAC_CHCTRLB_EVACT_Pos)
@@ -729,44 +744,44 @@ typedef union {
 #define DMAC_CHCTRLB_EVACT_RESUME   (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos)
 #define DMAC_CHCTRLB_EVACT_SSKIP    (DMAC_CHCTRLB_EVACT_SSKIP_Val  << DMAC_CHCTRLB_EVACT_Pos)
 #define DMAC_CHCTRLB_EVIE_Pos       3            /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */
-#define DMAC_CHCTRLB_EVIE           (_U(0x1) << DMAC_CHCTRLB_EVIE_Pos)
+#define DMAC_CHCTRLB_EVIE           (0x1ul << DMAC_CHCTRLB_EVIE_Pos)
 #define DMAC_CHCTRLB_EVOE_Pos       4            /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */
-#define DMAC_CHCTRLB_EVOE           (_U(0x1) << DMAC_CHCTRLB_EVOE_Pos)
+#define DMAC_CHCTRLB_EVOE           (0x1ul << DMAC_CHCTRLB_EVOE_Pos)
 #define DMAC_CHCTRLB_LVL_Pos        5            /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
-#define DMAC_CHCTRLB_LVL_Msk        (_U(0x3) << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_Msk        (0x3ul << DMAC_CHCTRLB_LVL_Pos)
 #define DMAC_CHCTRLB_LVL(value)     (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))
-#define   DMAC_CHCTRLB_LVL_LVL0_Val       _U(0x0)   /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
-#define   DMAC_CHCTRLB_LVL_LVL1_Val       _U(0x1)   /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
-#define   DMAC_CHCTRLB_LVL_LVL2_Val       _U(0x2)   /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
-#define   DMAC_CHCTRLB_LVL_LVL3_Val       _U(0x3)   /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
+#define   DMAC_CHCTRLB_LVL_LVL0_Val       0x0ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
+#define   DMAC_CHCTRLB_LVL_LVL1_Val       0x1ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
+#define   DMAC_CHCTRLB_LVL_LVL2_Val       0x2ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
+#define   DMAC_CHCTRLB_LVL_LVL3_Val       0x3ul  /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
 #define DMAC_CHCTRLB_LVL_LVL0       (DMAC_CHCTRLB_LVL_LVL0_Val     << DMAC_CHCTRLB_LVL_Pos)
 #define DMAC_CHCTRLB_LVL_LVL1       (DMAC_CHCTRLB_LVL_LVL1_Val     << DMAC_CHCTRLB_LVL_Pos)
 #define DMAC_CHCTRLB_LVL_LVL2       (DMAC_CHCTRLB_LVL_LVL2_Val     << DMAC_CHCTRLB_LVL_Pos)
 #define DMAC_CHCTRLB_LVL_LVL3       (DMAC_CHCTRLB_LVL_LVL3_Val     << DMAC_CHCTRLB_LVL_Pos)
 #define DMAC_CHCTRLB_TRIGSRC_Pos    8            /**< \brief (DMAC_CHCTRLB) Peripheral Trigger Source */
-#define DMAC_CHCTRLB_TRIGSRC_Msk    (_U(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGSRC_Msk    (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos)
 #define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))
-#define   DMAC_CHCTRLB_TRIGSRC_DISABLE_Val _U(0x0)   /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
+#define   DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul  /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
 #define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
 #define DMAC_CHCTRLB_TRIGACT_Pos    22           /**< \brief (DMAC_CHCTRLB) Trigger Action */
-#define DMAC_CHCTRLB_TRIGACT_Msk    (_U(0x3) << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_Msk    (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos)
 #define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))
-#define   DMAC_CHCTRLB_TRIGACT_BLOCK_Val  _U(0x0)   /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
-#define   DMAC_CHCTRLB_TRIGACT_BEAT_Val   _U(0x2)   /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
-#define   DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _U(0x3)   /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
+#define   DMAC_CHCTRLB_TRIGACT_BLOCK_Val  0x0ul  /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
+#define   DMAC_CHCTRLB_TRIGACT_BEAT_Val   0x2ul  /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
+#define   DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul  /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
 #define DMAC_CHCTRLB_TRIGACT_BLOCK  (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos)
 #define DMAC_CHCTRLB_TRIGACT_BEAT   (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos)
 #define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
 #define DMAC_CHCTRLB_CMD_Pos        24           /**< \brief (DMAC_CHCTRLB) Software Command */
-#define DMAC_CHCTRLB_CMD_Msk        (_U(0x3) << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_Msk        (0x3ul << DMAC_CHCTRLB_CMD_Pos)
 #define DMAC_CHCTRLB_CMD(value)     (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
-#define   DMAC_CHCTRLB_CMD_NOACT_Val      _U(0x0)   /**< \brief (DMAC_CHCTRLB) No action */
-#define   DMAC_CHCTRLB_CMD_SUSPEND_Val    _U(0x1)   /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
-#define   DMAC_CHCTRLB_CMD_RESUME_Val     _U(0x2)   /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define   DMAC_CHCTRLB_CMD_NOACT_Val      0x0ul  /**< \brief (DMAC_CHCTRLB) No action */
+#define   DMAC_CHCTRLB_CMD_SUSPEND_Val    0x1ul  /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define   DMAC_CHCTRLB_CMD_RESUME_Val     0x2ul  /**< \brief (DMAC_CHCTRLB) Channel resume operation */
 #define DMAC_CHCTRLB_CMD_NOACT      (DMAC_CHCTRLB_CMD_NOACT_Val    << DMAC_CHCTRLB_CMD_Pos)
 #define DMAC_CHCTRLB_CMD_SUSPEND    (DMAC_CHCTRLB_CMD_SUSPEND_Val  << DMAC_CHCTRLB_CMD_Pos)
 #define DMAC_CHCTRLB_CMD_RESUME     (DMAC_CHCTRLB_CMD_RESUME_Val   << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_MASK           _U(0x03C03F7F) /**< \brief (DMAC_CHCTRLB) MASK Register */
+#define DMAC_CHCTRLB_MASK           0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */
 
 /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W  8) Channel Interrupt Enable Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -782,15 +797,15 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_CHINTENCLR_OFFSET      0x4C         /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */
-#define DMAC_CHINTENCLR_RESETVALUE  _U(0x00)     /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */
+#define DMAC_CHINTENCLR_RESETVALUE  0x00ul       /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */
 
 #define DMAC_CHINTENCLR_TERR_Pos    0            /**< \brief (DMAC_CHINTENCLR) Transfer Error Interrupt Enable */
-#define DMAC_CHINTENCLR_TERR        (_U(0x1) << DMAC_CHINTENCLR_TERR_Pos)
+#define DMAC_CHINTENCLR_TERR        (0x1ul << DMAC_CHINTENCLR_TERR_Pos)
 #define DMAC_CHINTENCLR_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENCLR) Transfer Complete Interrupt Enable */
-#define DMAC_CHINTENCLR_TCMPL       (_U(0x1) << DMAC_CHINTENCLR_TCMPL_Pos)
+#define DMAC_CHINTENCLR_TCMPL       (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos)
 #define DMAC_CHINTENCLR_SUSP_Pos    2            /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
-#define DMAC_CHINTENCLR_SUSP        (_U(0x1) << DMAC_CHINTENCLR_SUSP_Pos)
-#define DMAC_CHINTENCLR_MASK        _U(0x07)     /**< \brief (DMAC_CHINTENCLR) MASK Register */
+#define DMAC_CHINTENCLR_SUSP        (0x1ul << DMAC_CHINTENCLR_SUSP_Pos)
+#define DMAC_CHINTENCLR_MASK        0x07ul       /**< \brief (DMAC_CHINTENCLR) MASK Register */
 
 /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W  8) Channel Interrupt Enable Set -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -806,15 +821,15 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_CHINTENSET_OFFSET      0x4D         /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */
-#define DMAC_CHINTENSET_RESETVALUE  _U(0x00)     /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */
+#define DMAC_CHINTENSET_RESETVALUE  0x00ul       /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */
 
 #define DMAC_CHINTENSET_TERR_Pos    0            /**< \brief (DMAC_CHINTENSET) Transfer Error Interrupt Enable */
-#define DMAC_CHINTENSET_TERR        (_U(0x1) << DMAC_CHINTENSET_TERR_Pos)
+#define DMAC_CHINTENSET_TERR        (0x1ul << DMAC_CHINTENSET_TERR_Pos)
 #define DMAC_CHINTENSET_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENSET) Transfer Complete Interrupt Enable */
-#define DMAC_CHINTENSET_TCMPL       (_U(0x1) << DMAC_CHINTENSET_TCMPL_Pos)
+#define DMAC_CHINTENSET_TCMPL       (0x1ul << DMAC_CHINTENSET_TCMPL_Pos)
 #define DMAC_CHINTENSET_SUSP_Pos    2            /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
-#define DMAC_CHINTENSET_SUSP        (_U(0x1) << DMAC_CHINTENSET_SUSP_Pos)
-#define DMAC_CHINTENSET_MASK        _U(0x07)     /**< \brief (DMAC_CHINTENSET) MASK Register */
+#define DMAC_CHINTENSET_SUSP        (0x1ul << DMAC_CHINTENSET_SUSP_Pos)
+#define DMAC_CHINTENSET_MASK        0x07ul       /**< \brief (DMAC_CHINTENSET) MASK Register */
 
 /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W  8) Channel Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -830,15 +845,15 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_CHINTFLAG_OFFSET       0x4E         /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */
-#define DMAC_CHINTFLAG_RESETVALUE   _U(0x00)     /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */
+#define DMAC_CHINTFLAG_RESETVALUE   0x00ul       /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */
 
 #define DMAC_CHINTFLAG_TERR_Pos     0            /**< \brief (DMAC_CHINTFLAG) Transfer Error */
-#define DMAC_CHINTFLAG_TERR         (_U(0x1) << DMAC_CHINTFLAG_TERR_Pos)
+#define DMAC_CHINTFLAG_TERR         (0x1ul << DMAC_CHINTFLAG_TERR_Pos)
 #define DMAC_CHINTFLAG_TCMPL_Pos    1            /**< \brief (DMAC_CHINTFLAG) Transfer Complete */
-#define DMAC_CHINTFLAG_TCMPL        (_U(0x1) << DMAC_CHINTFLAG_TCMPL_Pos)
+#define DMAC_CHINTFLAG_TCMPL        (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos)
 #define DMAC_CHINTFLAG_SUSP_Pos     2            /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
-#define DMAC_CHINTFLAG_SUSP         (_U(0x1) << DMAC_CHINTFLAG_SUSP_Pos)
-#define DMAC_CHINTFLAG_MASK         _U(0x07)     /**< \brief (DMAC_CHINTFLAG) MASK Register */
+#define DMAC_CHINTFLAG_SUSP         (0x1ul << DMAC_CHINTFLAG_SUSP_Pos)
+#define DMAC_CHINTFLAG_MASK         0x07ul       /**< \brief (DMAC_CHINTFLAG) MASK Register */
 
 /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/   8) Channel Status -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -854,15 +869,15 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_CHSTATUS_OFFSET        0x4F         /**< \brief (DMAC_CHSTATUS offset) Channel Status */
-#define DMAC_CHSTATUS_RESETVALUE    _U(0x00)     /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */
+#define DMAC_CHSTATUS_RESETVALUE    0x00ul       /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */
 
 #define DMAC_CHSTATUS_PEND_Pos      0            /**< \brief (DMAC_CHSTATUS) Channel Pending */
-#define DMAC_CHSTATUS_PEND          (_U(0x1) << DMAC_CHSTATUS_PEND_Pos)
+#define DMAC_CHSTATUS_PEND          (0x1ul << DMAC_CHSTATUS_PEND_Pos)
 #define DMAC_CHSTATUS_BUSY_Pos      1            /**< \brief (DMAC_CHSTATUS) Channel Busy */
-#define DMAC_CHSTATUS_BUSY          (_U(0x1) << DMAC_CHSTATUS_BUSY_Pos)
+#define DMAC_CHSTATUS_BUSY          (0x1ul << DMAC_CHSTATUS_BUSY_Pos)
 #define DMAC_CHSTATUS_FERR_Pos      2            /**< \brief (DMAC_CHSTATUS) Fetch Error */
-#define DMAC_CHSTATUS_FERR          (_U(0x1) << DMAC_CHSTATUS_FERR_Pos)
-#define DMAC_CHSTATUS_MASK          _U(0x07)     /**< \brief (DMAC_CHSTATUS) MASK Register */
+#define DMAC_CHSTATUS_FERR          (0x1ul << DMAC_CHSTATUS_FERR_Pos)
+#define DMAC_CHSTATUS_MASK          0x07ul       /**< \brief (DMAC_CHSTATUS) MASK Register */
 
 /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -883,60 +898,60 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DMAC_BTCTRL_OFFSET          0x00         /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
-#define DMAC_BTCTRL_RESETVALUE      _U(0x0000)   /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
+#define DMAC_BTCTRL_RESETVALUE      0x0000ul     /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
 
 #define DMAC_BTCTRL_VALID_Pos       0            /**< \brief (DMAC_BTCTRL) Descriptor Valid */
-#define DMAC_BTCTRL_VALID           (_U(0x1) << DMAC_BTCTRL_VALID_Pos)
+#define DMAC_BTCTRL_VALID           (0x1ul << DMAC_BTCTRL_VALID_Pos)
 #define DMAC_BTCTRL_EVOSEL_Pos      1            /**< \brief (DMAC_BTCTRL) Event Output Selection */
-#define DMAC_BTCTRL_EVOSEL_Msk      (_U(0x3) << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_Msk      (0x3ul << DMAC_BTCTRL_EVOSEL_Pos)
 #define DMAC_BTCTRL_EVOSEL(value)   (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
-#define   DMAC_BTCTRL_EVOSEL_DISABLE_Val  _U(0x0)   /**< \brief (DMAC_BTCTRL) Event generation disabled */
-#define   DMAC_BTCTRL_EVOSEL_BLOCK_Val    _U(0x1)   /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
-#define   DMAC_BTCTRL_EVOSEL_BEAT_Val     _U(0x3)   /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
+#define   DMAC_BTCTRL_EVOSEL_DISABLE_Val  0x0ul  /**< \brief (DMAC_BTCTRL) Event generation disabled */
+#define   DMAC_BTCTRL_EVOSEL_BLOCK_Val    0x1ul  /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
+#define   DMAC_BTCTRL_EVOSEL_BEAT_Val     0x3ul  /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
 #define DMAC_BTCTRL_EVOSEL_DISABLE  (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
 #define DMAC_BTCTRL_EVOSEL_BLOCK    (DMAC_BTCTRL_EVOSEL_BLOCK_Val  << DMAC_BTCTRL_EVOSEL_Pos)
 #define DMAC_BTCTRL_EVOSEL_BEAT     (DMAC_BTCTRL_EVOSEL_BEAT_Val   << DMAC_BTCTRL_EVOSEL_Pos)
 #define DMAC_BTCTRL_BLOCKACT_Pos    3            /**< \brief (DMAC_BTCTRL) Block Action */
-#define DMAC_BTCTRL_BLOCKACT_Msk    (_U(0x3) << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_Msk    (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos)
 #define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
-#define   DMAC_BTCTRL_BLOCKACT_NOACT_Val  _U(0x0)   /**< \brief (DMAC_BTCTRL) No action */
-#define   DMAC_BTCTRL_BLOCKACT_INT_Val    _U(0x1)   /**< \brief (DMAC_BTCTRL) Channel in normal operation and block interrupt */
-#define   DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U(0x2)   /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
-#define   DMAC_BTCTRL_BLOCKACT_BOTH_Val   _U(0x3)   /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
+#define   DMAC_BTCTRL_BLOCKACT_NOACT_Val  0x0ul  /**< \brief (DMAC_BTCTRL) No action */
+#define   DMAC_BTCTRL_BLOCKACT_INT_Val    0x1ul  /**< \brief (DMAC_BTCTRL) Channel in normal operation and block interrupt */
+#define   DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul  /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
+#define   DMAC_BTCTRL_BLOCKACT_BOTH_Val   0x3ul  /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
 #define DMAC_BTCTRL_BLOCKACT_NOACT  (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
 #define DMAC_BTCTRL_BLOCKACT_INT    (DMAC_BTCTRL_BLOCKACT_INT_Val  << DMAC_BTCTRL_BLOCKACT_Pos)
 #define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
 #define DMAC_BTCTRL_BLOCKACT_BOTH   (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
 #define DMAC_BTCTRL_BEATSIZE_Pos    8            /**< \brief (DMAC_BTCTRL) Beat Size */
-#define DMAC_BTCTRL_BEATSIZE_Msk    (_U(0x3) << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_Msk    (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos)
 #define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
-#define   DMAC_BTCTRL_BEATSIZE_BYTE_Val   _U(0x0)   /**< \brief (DMAC_BTCTRL) 8-bit access */
-#define   DMAC_BTCTRL_BEATSIZE_HWORD_Val  _U(0x1)   /**< \brief (DMAC_BTCTRL) 16-bit access */
-#define   DMAC_BTCTRL_BEATSIZE_WORD_Val   _U(0x2)   /**< \brief (DMAC_BTCTRL) 32-bit access */
+#define   DMAC_BTCTRL_BEATSIZE_BYTE_Val   0x0ul  /**< \brief (DMAC_BTCTRL) 8-bit access */
+#define   DMAC_BTCTRL_BEATSIZE_HWORD_Val  0x1ul  /**< \brief (DMAC_BTCTRL) 16-bit access */
+#define   DMAC_BTCTRL_BEATSIZE_WORD_Val   0x2ul  /**< \brief (DMAC_BTCTRL) 32-bit access */
 #define DMAC_BTCTRL_BEATSIZE_BYTE   (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
 #define DMAC_BTCTRL_BEATSIZE_HWORD  (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
 #define DMAC_BTCTRL_BEATSIZE_WORD   (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
 #define DMAC_BTCTRL_SRCINC_Pos      10           /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
-#define DMAC_BTCTRL_SRCINC          (_U(0x1) << DMAC_BTCTRL_SRCINC_Pos)
+#define DMAC_BTCTRL_SRCINC          (0x1ul << DMAC_BTCTRL_SRCINC_Pos)
 #define DMAC_BTCTRL_DSTINC_Pos      11           /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
-#define DMAC_BTCTRL_DSTINC          (_U(0x1) << DMAC_BTCTRL_DSTINC_Pos)
+#define DMAC_BTCTRL_DSTINC          (0x1ul << DMAC_BTCTRL_DSTINC_Pos)
 #define DMAC_BTCTRL_STEPSEL_Pos     12           /**< \brief (DMAC_BTCTRL) Step Selection */
-#define DMAC_BTCTRL_STEPSEL         (_U(0x1) << DMAC_BTCTRL_STEPSEL_Pos)
-#define   DMAC_BTCTRL_STEPSEL_DST_Val     _U(0x0)   /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
-#define   DMAC_BTCTRL_STEPSEL_SRC_Val     _U(0x1)   /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
+#define DMAC_BTCTRL_STEPSEL         (0x1ul << DMAC_BTCTRL_STEPSEL_Pos)
+#define   DMAC_BTCTRL_STEPSEL_DST_Val     0x0ul  /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
+#define   DMAC_BTCTRL_STEPSEL_SRC_Val     0x1ul  /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
 #define DMAC_BTCTRL_STEPSEL_DST     (DMAC_BTCTRL_STEPSEL_DST_Val   << DMAC_BTCTRL_STEPSEL_Pos)
 #define DMAC_BTCTRL_STEPSEL_SRC     (DMAC_BTCTRL_STEPSEL_SRC_Val   << DMAC_BTCTRL_STEPSEL_Pos)
 #define DMAC_BTCTRL_STEPSIZE_Pos    13           /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
-#define DMAC_BTCTRL_STEPSIZE_Msk    (_U(0x7) << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_Msk    (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos)
 #define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
-#define   DMAC_BTCTRL_STEPSIZE_X1_Val     _U(0x0)   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 1 */
-#define   DMAC_BTCTRL_STEPSIZE_X2_Val     _U(0x1)   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 2 */
-#define   DMAC_BTCTRL_STEPSIZE_X4_Val     _U(0x2)   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 4 */
-#define   DMAC_BTCTRL_STEPSIZE_X8_Val     _U(0x3)   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 8 */
-#define   DMAC_BTCTRL_STEPSIZE_X16_Val    _U(0x4)   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 16 */
-#define   DMAC_BTCTRL_STEPSIZE_X32_Val    _U(0x5)   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 32 */
-#define   DMAC_BTCTRL_STEPSIZE_X64_Val    _U(0x6)   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 64 */
-#define   DMAC_BTCTRL_STEPSIZE_X128_Val   _U(0x7)   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 128 */
+#define   DMAC_BTCTRL_STEPSIZE_X1_Val     0x0ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 1 */
+#define   DMAC_BTCTRL_STEPSIZE_X2_Val     0x1ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 2 */
+#define   DMAC_BTCTRL_STEPSIZE_X4_Val     0x2ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 4 */
+#define   DMAC_BTCTRL_STEPSIZE_X8_Val     0x3ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 8 */
+#define   DMAC_BTCTRL_STEPSIZE_X16_Val    0x4ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 16 */
+#define   DMAC_BTCTRL_STEPSIZE_X32_Val    0x5ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 32 */
+#define   DMAC_BTCTRL_STEPSIZE_X64_Val    0x6ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 64 */
+#define   DMAC_BTCTRL_STEPSIZE_X128_Val   0x7ul  /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 128 */
 #define DMAC_BTCTRL_STEPSIZE_X1     (DMAC_BTCTRL_STEPSIZE_X1_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
 #define DMAC_BTCTRL_STEPSIZE_X2     (DMAC_BTCTRL_STEPSIZE_X2_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
 #define DMAC_BTCTRL_STEPSIZE_X4     (DMAC_BTCTRL_STEPSIZE_X4_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
@@ -945,7 +960,7 @@ typedef union {
 #define DMAC_BTCTRL_STEPSIZE_X32    (DMAC_BTCTRL_STEPSIZE_X32_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
 #define DMAC_BTCTRL_STEPSIZE_X64    (DMAC_BTCTRL_STEPSIZE_X64_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
 #define DMAC_BTCTRL_STEPSIZE_X128   (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_MASK            _U(0xFF1F)   /**< \brief (DMAC_BTCTRL) MASK Register */
+#define DMAC_BTCTRL_MASK            0xFF1Ful     /**< \brief (DMAC_BTCTRL) MASK Register */
 
 /* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -960,9 +975,9 @@ typedef union {
 #define DMAC_BTCNT_OFFSET           0x02         /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
 
 #define DMAC_BTCNT_BTCNT_Pos        0            /**< \brief (DMAC_BTCNT) Block Transfer Count */
-#define DMAC_BTCNT_BTCNT_Msk        (_U(0xFFFF) << DMAC_BTCNT_BTCNT_Pos)
+#define DMAC_BTCNT_BTCNT_Msk        (0xFFFFul << DMAC_BTCNT_BTCNT_Pos)
 #define DMAC_BTCNT_BTCNT(value)     (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
-#define DMAC_BTCNT_MASK             _U(0xFFFF)   /**< \brief (DMAC_BTCNT) MASK Register */
+#define DMAC_BTCNT_MASK             0xFFFFul     /**< \brief (DMAC_BTCNT) MASK Register */
 
 /* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -977,9 +992,9 @@ typedef union {
 #define DMAC_SRCADDR_OFFSET         0x04         /**< \brief (DMAC_SRCADDR offset) Transfer Source Address */
 
 #define DMAC_SRCADDR_SRCADDR_Pos    0            /**< \brief (DMAC_SRCADDR) Transfer Source Address */
-#define DMAC_SRCADDR_SRCADDR_Msk    (_U(0xFFFFFFFF) << DMAC_SRCADDR_SRCADDR_Pos)
+#define DMAC_SRCADDR_SRCADDR_Msk    (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos)
 #define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
-#define DMAC_SRCADDR_MASK           _U(0xFFFFFFFF) /**< \brief (DMAC_SRCADDR) MASK Register */
+#define DMAC_SRCADDR_MASK           0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */
 
 /* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -994,9 +1009,9 @@ typedef union {
 #define DMAC_DSTADDR_OFFSET         0x08         /**< \brief (DMAC_DSTADDR offset) Transfer Destination Address */
 
 #define DMAC_DSTADDR_DSTADDR_Pos    0            /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
-#define DMAC_DSTADDR_DSTADDR_Msk    (_U(0xFFFFFFFF) << DMAC_DSTADDR_DSTADDR_Pos)
+#define DMAC_DSTADDR_DSTADDR_Msk    (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos)
 #define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
-#define DMAC_DSTADDR_MASK           _U(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR) MASK Register */
+#define DMAC_DSTADDR_MASK           0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */
 
 /* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -1011,9 +1026,9 @@ typedef union {
 #define DMAC_DESCADDR_OFFSET        0x0C         /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
 
 #define DMAC_DESCADDR_DESCADDR_Pos  0            /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
-#define DMAC_DESCADDR_DESCADDR_Msk  (_U(0xFFFFFFFF) << DMAC_DESCADDR_DESCADDR_Pos)
+#define DMAC_DESCADDR_DESCADDR_Msk  (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos)
 #define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
-#define DMAC_DESCADDR_MASK          _U(0xFFFFFFFF) /**< \brief (DMAC_DESCADDR) MASK Register */
+#define DMAC_DESCADDR_MASK          0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */
 
 /** \brief DMAC APB hardware registers */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

asf/sam0/utils/cmsis/samd21/include/component/dsu.h

@@ -3,24 +3,39 @@
  *
  * \brief Component description for DSU
  *
- * Copyright (c) 2017 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *
  * \asf_license_stop
  *
@@ -54,17 +69,17 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_CTRL_OFFSET             0x0000       /**< \brief (DSU_CTRL offset) Control */
-#define DSU_CTRL_RESETVALUE         _U(0x00)     /**< \brief (DSU_CTRL reset_value) Control */
+#define DSU_CTRL_RESETVALUE         0x00ul       /**< \brief (DSU_CTRL reset_value) Control */
 
 #define DSU_CTRL_SWRST_Pos          0            /**< \brief (DSU_CTRL) Software Reset */
-#define DSU_CTRL_SWRST              (_U(0x1) << DSU_CTRL_SWRST_Pos)
+#define DSU_CTRL_SWRST              (0x1ul << DSU_CTRL_SWRST_Pos)
 #define DSU_CTRL_CRC_Pos            2            /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
-#define DSU_CTRL_CRC                (_U(0x1) << DSU_CTRL_CRC_Pos)
+#define DSU_CTRL_CRC                (0x1ul << DSU_CTRL_CRC_Pos)
 #define DSU_CTRL_MBIST_Pos          3            /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
-#define DSU_CTRL_MBIST              (_U(0x1) << DSU_CTRL_MBIST_Pos)
+#define DSU_CTRL_MBIST              (0x1ul << DSU_CTRL_MBIST_Pos)
 #define DSU_CTRL_CE_Pos             4            /**< \brief (DSU_CTRL) Chip Erase */
-#define DSU_CTRL_CE                 (_U(0x1) << DSU_CTRL_CE_Pos)
-#define DSU_CTRL_MASK               _U(0x1D)     /**< \brief (DSU_CTRL) MASK Register */
+#define DSU_CTRL_CE                 (0x1ul << DSU_CTRL_CE_Pos)
+#define DSU_CTRL_MASK               0x1Dul       /**< \brief (DSU_CTRL) MASK Register */
 
 /* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W  8) Status A -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -82,19 +97,19 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_STATUSA_OFFSET          0x0001       /**< \brief (DSU_STATUSA offset) Status A */
-#define DSU_STATUSA_RESETVALUE      _U(0x00)     /**< \brief (DSU_STATUSA reset_value) Status A */
+#define DSU_STATUSA_RESETVALUE      0x00ul       /**< \brief (DSU_STATUSA reset_value) Status A */
 
 #define DSU_STATUSA_DONE_Pos        0            /**< \brief (DSU_STATUSA) Done */
-#define DSU_STATUSA_DONE            (_U(0x1) << DSU_STATUSA_DONE_Pos)
+#define DSU_STATUSA_DONE            (0x1ul << DSU_STATUSA_DONE_Pos)
 #define DSU_STATUSA_CRSTEXT_Pos     1            /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
-#define DSU_STATUSA_CRSTEXT         (_U(0x1) << DSU_STATUSA_CRSTEXT_Pos)
+#define DSU_STATUSA_CRSTEXT         (0x1ul << DSU_STATUSA_CRSTEXT_Pos)
 #define DSU_STATUSA_BERR_Pos        2            /**< \brief (DSU_STATUSA) Bus Error */
-#define DSU_STATUSA_BERR            (_U(0x1) << DSU_STATUSA_BERR_Pos)
+#define DSU_STATUSA_BERR            (0x1ul << DSU_STATUSA_BERR_Pos)
 #define DSU_STATUSA_FAIL_Pos        3            /**< \brief (DSU_STATUSA) Failure */
-#define DSU_STATUSA_FAIL            (_U(0x1) << DSU_STATUSA_FAIL_Pos)
+#define DSU_STATUSA_FAIL            (0x1ul << DSU_STATUSA_FAIL_Pos)
 #define DSU_STATUSA_PERR_Pos        4            /**< \brief (DSU_STATUSA) Protection Error */
-#define DSU_STATUSA_PERR            (_U(0x1) << DSU_STATUSA_PERR_Pos)
-#define DSU_STATUSA_MASK            _U(0x1F)     /**< \brief (DSU_STATUSA) MASK Register */
+#define DSU_STATUSA_PERR            (0x1ul << DSU_STATUSA_PERR_Pos)
+#define DSU_STATUSA_MASK            0x1Ful       /**< \brief (DSU_STATUSA) MASK Register */
 
 /* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/   8) Status B -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -117,22 +132,22 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_STATUSB_OFFSET          0x0002       /**< \brief (DSU_STATUSB offset) Status B */
-#define DSU_STATUSB_RESETVALUE      _U(0x10)     /**< \brief (DSU_STATUSB reset_value) Status B */
+#define DSU_STATUSB_RESETVALUE      0x10ul       /**< \brief (DSU_STATUSB reset_value) Status B */
 
 #define DSU_STATUSB_PROT_Pos        0            /**< \brief (DSU_STATUSB) Protected */
-#define DSU_STATUSB_PROT            (_U(0x1) << DSU_STATUSB_PROT_Pos)
+#define DSU_STATUSB_PROT            (0x1ul << DSU_STATUSB_PROT_Pos)
 #define DSU_STATUSB_DBGPRES_Pos     1            /**< \brief (DSU_STATUSB) Debugger Present */
-#define DSU_STATUSB_DBGPRES         (_U(0x1) << DSU_STATUSB_DBGPRES_Pos)
+#define DSU_STATUSB_DBGPRES         (0x1ul << DSU_STATUSB_DBGPRES_Pos)
 #define DSU_STATUSB_DCCD0_Pos       2            /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
 #define DSU_STATUSB_DCCD0           (1 << DSU_STATUSB_DCCD0_Pos)
 #define DSU_STATUSB_DCCD1_Pos       3            /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
 #define DSU_STATUSB_DCCD1           (1 << DSU_STATUSB_DCCD1_Pos)
 #define DSU_STATUSB_DCCD_Pos        2            /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
-#define DSU_STATUSB_DCCD_Msk        (_U(0x3) << DSU_STATUSB_DCCD_Pos)
+#define DSU_STATUSB_DCCD_Msk        (0x3ul << DSU_STATUSB_DCCD_Pos)
 #define DSU_STATUSB_DCCD(value)     (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
 #define DSU_STATUSB_HPE_Pos         4            /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
-#define DSU_STATUSB_HPE             (_U(0x1) << DSU_STATUSB_HPE_Pos)
-#define DSU_STATUSB_MASK            _U(0x1F)     /**< \brief (DSU_STATUSB) MASK Register */
+#define DSU_STATUSB_HPE             (0x1ul << DSU_STATUSB_HPE_Pos)
+#define DSU_STATUSB_MASK            0x1Ful       /**< \brief (DSU_STATUSB) MASK Register */
 
 /* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -146,12 +161,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_ADDR_OFFSET             0x0004       /**< \brief (DSU_ADDR offset) Address */
-#define DSU_ADDR_RESETVALUE         _U(0x00000000) /**< \brief (DSU_ADDR reset_value) Address */
+#define DSU_ADDR_RESETVALUE         0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */
 
 #define DSU_ADDR_ADDR_Pos           2            /**< \brief (DSU_ADDR) Address */
-#define DSU_ADDR_ADDR_Msk           (_U(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos)
+#define DSU_ADDR_ADDR_Msk           (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos)
 #define DSU_ADDR_ADDR(value)        (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
-#define DSU_ADDR_MASK               _U(0xFFFFFFFC) /**< \brief (DSU_ADDR) MASK Register */
+#define DSU_ADDR_MASK               0xFFFFFFFCul /**< \brief (DSU_ADDR) MASK Register */
 
 /* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -165,12 +180,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_LENGTH_OFFSET           0x0008       /**< \brief (DSU_LENGTH offset) Length */
-#define DSU_LENGTH_RESETVALUE       _U(0x00000000) /**< \brief (DSU_LENGTH reset_value) Length */
+#define DSU_LENGTH_RESETVALUE       0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */
 
 #define DSU_LENGTH_LENGTH_Pos       2            /**< \brief (DSU_LENGTH) Length */
-#define DSU_LENGTH_LENGTH_Msk       (_U(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos)
+#define DSU_LENGTH_LENGTH_Msk       (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos)
 #define DSU_LENGTH_LENGTH(value)    (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
-#define DSU_LENGTH_MASK             _U(0xFFFFFFFC) /**< \brief (DSU_LENGTH) MASK Register */
+#define DSU_LENGTH_MASK             0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */
 
 /* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -183,12 +198,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_DATA_OFFSET             0x000C       /**< \brief (DSU_DATA offset) Data */
-#define DSU_DATA_RESETVALUE         _U(0x00000000) /**< \brief (DSU_DATA reset_value) Data */
+#define DSU_DATA_RESETVALUE         0x00000000ul /**< \brief (DSU_DATA reset_value) Data */
 
 #define DSU_DATA_DATA_Pos           0            /**< \brief (DSU_DATA) Data */
-#define DSU_DATA_DATA_Msk           (_U(0xFFFFFFFF) << DSU_DATA_DATA_Pos)
+#define DSU_DATA_DATA_Msk           (0xFFFFFFFFul << DSU_DATA_DATA_Pos)
 #define DSU_DATA_DATA(value)        (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
-#define DSU_DATA_MASK               _U(0xFFFFFFFF) /**< \brief (DSU_DATA) MASK Register */
+#define DSU_DATA_MASK               0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */
 
 /* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -201,12 +216,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_DCC_OFFSET              0x0010       /**< \brief (DSU_DCC offset) Debug Communication Channel n */
-#define DSU_DCC_RESETVALUE          _U(0x00000000) /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
+#define DSU_DCC_RESETVALUE          0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
 
 #define DSU_DCC_DATA_Pos            0            /**< \brief (DSU_DCC) Data */
-#define DSU_DCC_DATA_Msk            (_U(0xFFFFFFFF) << DSU_DCC_DATA_Pos)
+#define DSU_DCC_DATA_Msk            (0xFFFFFFFFul << DSU_DCC_DATA_Pos)
 #define DSU_DCC_DATA(value)         (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
-#define DSU_DCC_MASK                _U(0xFFFFFFFF) /**< \brief (DSU_DCC) MASK Register */
+#define DSU_DCC_MASK                0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */
 
 /* -------- DSU_DID : (DSU Offset: 0x0018) (R/  32) Device Identification -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -227,24 +242,24 @@ typedef union {
 #define DSU_DID_OFFSET              0x0018       /**< \brief (DSU_DID offset) Device Identification */
 
 #define DSU_DID_DEVSEL_Pos          0            /**< \brief (DSU_DID) Device Select */
-#define DSU_DID_DEVSEL_Msk          (_U(0xFF) << DSU_DID_DEVSEL_Pos)
+#define DSU_DID_DEVSEL_Msk          (0xFFul << DSU_DID_DEVSEL_Pos)
 #define DSU_DID_DEVSEL(value)       (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
 #define DSU_DID_REVISION_Pos        8            /**< \brief (DSU_DID) Revision */
-#define DSU_DID_REVISION_Msk        (_U(0xF) << DSU_DID_REVISION_Pos)
+#define DSU_DID_REVISION_Msk        (0xFul << DSU_DID_REVISION_Pos)
 #define DSU_DID_REVISION(value)     (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
 #define DSU_DID_DIE_Pos             12           /**< \brief (DSU_DID) Die Identification */
-#define DSU_DID_DIE_Msk             (_U(0xF) << DSU_DID_DIE_Pos)
+#define DSU_DID_DIE_Msk             (0xFul << DSU_DID_DIE_Pos)
 #define DSU_DID_DIE(value)          (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
 #define DSU_DID_SERIES_Pos          16           /**< \brief (DSU_DID) Product Series */
-#define DSU_DID_SERIES_Msk          (_U(0x3F) << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES_Msk          (0x3Ful << DSU_DID_SERIES_Pos)
 #define DSU_DID_SERIES(value)       (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
 #define DSU_DID_FAMILY_Pos          23           /**< \brief (DSU_DID) Product Family */
-#define DSU_DID_FAMILY_Msk          (_U(0x1F) << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY_Msk          (0x1Ful << DSU_DID_FAMILY_Pos)
 #define DSU_DID_FAMILY(value)       (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
 #define DSU_DID_PROCESSOR_Pos       28           /**< \brief (DSU_DID) Processor */
-#define DSU_DID_PROCESSOR_Msk       (_U(0xF) << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_Msk       (0xFul << DSU_DID_PROCESSOR_Pos)
 #define DSU_DID_PROCESSOR(value)    (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
-#define DSU_DID_MASK                _U(0xFFBFFFFF) /**< \brief (DSU_DID) MASK Register */
+#define DSU_DID_MASK                0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */
 
 /* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/  32) Coresight ROM Table Entry n -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -260,16 +275,16 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_ENTRY_OFFSET            0x1000       /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
-#define DSU_ENTRY_RESETVALUE        _U(0x00000002) /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
+#define DSU_ENTRY_RESETVALUE        0x00000002ul /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
 
 #define DSU_ENTRY_EPRES_Pos         0            /**< \brief (DSU_ENTRY) Entry Present */
-#define DSU_ENTRY_EPRES             (_U(0x1) << DSU_ENTRY_EPRES_Pos)
+#define DSU_ENTRY_EPRES             (0x1ul << DSU_ENTRY_EPRES_Pos)
 #define DSU_ENTRY_FMT_Pos           1            /**< \brief (DSU_ENTRY) Format */
-#define DSU_ENTRY_FMT               (_U(0x1) << DSU_ENTRY_FMT_Pos)
+#define DSU_ENTRY_FMT               (0x1ul << DSU_ENTRY_FMT_Pos)
 #define DSU_ENTRY_ADDOFF_Pos        12           /**< \brief (DSU_ENTRY) Address Offset */
-#define DSU_ENTRY_ADDOFF_Msk        (_U(0xFFFFF) << DSU_ENTRY_ADDOFF_Pos)
+#define DSU_ENTRY_ADDOFF_Msk        (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos)
 #define DSU_ENTRY_ADDOFF(value)     (DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos))
-#define DSU_ENTRY_MASK              _U(0xFFFFF003) /**< \brief (DSU_ENTRY) MASK Register */
+#define DSU_ENTRY_MASK              0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */
 
 /* -------- DSU_END : (DSU Offset: 0x1008) (R/  32) Coresight ROM Table End -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -282,12 +297,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_END_OFFSET              0x1008       /**< \brief (DSU_END offset) Coresight ROM Table End */
-#define DSU_END_RESETVALUE          _U(0x00000000) /**< \brief (DSU_END reset_value) Coresight ROM Table End */
+#define DSU_END_RESETVALUE          0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */
 
 #define DSU_END_END_Pos             0            /**< \brief (DSU_END) End Marker */
-#define DSU_END_END_Msk             (_U(0xFFFFFFFF) << DSU_END_END_Pos)
+#define DSU_END_END_Msk             (0xFFFFFFFFul << DSU_END_END_Pos)
 #define DSU_END_END(value)          (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
-#define DSU_END_MASK                _U(0xFFFFFFFF) /**< \brief (DSU_END) MASK Register */
+#define DSU_END_MASK                0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */
 
 /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/  32) Coresight ROM Table Memory Type -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -301,11 +316,11 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_MEMTYPE_OFFSET          0x1FCC       /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
-#define DSU_MEMTYPE_RESETVALUE      _U(0x00000000) /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
+#define DSU_MEMTYPE_RESETVALUE      0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
 
 #define DSU_MEMTYPE_SMEMP_Pos       0            /**< \brief (DSU_MEMTYPE) System Memory Present */
-#define DSU_MEMTYPE_SMEMP           (_U(0x1) << DSU_MEMTYPE_SMEMP_Pos)
-#define DSU_MEMTYPE_MASK            _U(0x00000001) /**< \brief (DSU_MEMTYPE) MASK Register */
+#define DSU_MEMTYPE_SMEMP           (0x1ul << DSU_MEMTYPE_SMEMP_Pos)
+#define DSU_MEMTYPE_MASK            0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */
 
 /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/  32) Peripheral Identification 4 -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -320,15 +335,15 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_PID4_OFFSET             0x1FD0       /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
-#define DSU_PID4_RESETVALUE         _U(0x00000000) /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
+#define DSU_PID4_RESETVALUE         0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
 
 #define DSU_PID4_JEPCC_Pos          0            /**< \brief (DSU_PID4) JEP-106 Continuation Code */
-#define DSU_PID4_JEPCC_Msk          (_U(0xF) << DSU_PID4_JEPCC_Pos)
+#define DSU_PID4_JEPCC_Msk          (0xFul << DSU_PID4_JEPCC_Pos)
 #define DSU_PID4_JEPCC(value)       (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
 #define DSU_PID4_FKBC_Pos           4            /**< \brief (DSU_PID4) 4KB Count */
-#define DSU_PID4_FKBC_Msk           (_U(0xF) << DSU_PID4_FKBC_Pos)
+#define DSU_PID4_FKBC_Msk           (0xFul << DSU_PID4_FKBC_Pos)
 #define DSU_PID4_FKBC(value)        (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
-#define DSU_PID4_MASK               _U(0x000000FF) /**< \brief (DSU_PID4) MASK Register */
+#define DSU_PID4_MASK               0x000000FFul /**< \brief (DSU_PID4) MASK Register */
 
 /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/  32) Peripheral Identification 0 -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -342,12 +357,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_PID0_OFFSET             0x1FE0       /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
-#define DSU_PID0_RESETVALUE         _U(0x000000D0) /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
+#define DSU_PID0_RESETVALUE         0x000000D0ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
 
 #define DSU_PID0_PARTNBL_Pos        0            /**< \brief (DSU_PID0) Part Number Low */
-#define DSU_PID0_PARTNBL_Msk        (_U(0xFF) << DSU_PID0_PARTNBL_Pos)
+#define DSU_PID0_PARTNBL_Msk        (0xFFul << DSU_PID0_PARTNBL_Pos)
 #define DSU_PID0_PARTNBL(value)     (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
-#define DSU_PID0_MASK               _U(0x000000FF) /**< \brief (DSU_PID0) MASK Register */
+#define DSU_PID0_MASK               0x000000FFul /**< \brief (DSU_PID0) MASK Register */
 
 /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/  32) Peripheral Identification 1 -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -362,15 +377,15 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_PID1_OFFSET             0x1FE4       /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
-#define DSU_PID1_RESETVALUE         _U(0x000000FC) /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
+#define DSU_PID1_RESETVALUE         0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
 
 #define DSU_PID1_PARTNBH_Pos        0            /**< \brief (DSU_PID1) Part Number High */
-#define DSU_PID1_PARTNBH_Msk        (_U(0xF) << DSU_PID1_PARTNBH_Pos)
+#define DSU_PID1_PARTNBH_Msk        (0xFul << DSU_PID1_PARTNBH_Pos)
 #define DSU_PID1_PARTNBH(value)     (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
 #define DSU_PID1_JEPIDCL_Pos        4            /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
-#define DSU_PID1_JEPIDCL_Msk        (_U(0xF) << DSU_PID1_JEPIDCL_Pos)
+#define DSU_PID1_JEPIDCL_Msk        (0xFul << DSU_PID1_JEPIDCL_Pos)
 #define DSU_PID1_JEPIDCL(value)     (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
-#define DSU_PID1_MASK               _U(0x000000FF) /**< \brief (DSU_PID1) MASK Register */
+#define DSU_PID1_MASK               0x000000FFul /**< \brief (DSU_PID1) MASK Register */
 
 /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/  32) Peripheral Identification 2 -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -386,17 +401,17 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_PID2_OFFSET             0x1FE8       /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
-#define DSU_PID2_RESETVALUE         _U(0x00000009) /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
+#define DSU_PID2_RESETVALUE         0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
 
 #define DSU_PID2_JEPIDCH_Pos        0            /**< \brief (DSU_PID2) JEP-106 Identity Code High */
-#define DSU_PID2_JEPIDCH_Msk        (_U(0x7) << DSU_PID2_JEPIDCH_Pos)
+#define DSU_PID2_JEPIDCH_Msk        (0x7ul << DSU_PID2_JEPIDCH_Pos)
 #define DSU_PID2_JEPIDCH(value)     (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
 #define DSU_PID2_JEPU_Pos           3            /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
-#define DSU_PID2_JEPU               (_U(0x1) << DSU_PID2_JEPU_Pos)
+#define DSU_PID2_JEPU               (0x1ul << DSU_PID2_JEPU_Pos)
 #define DSU_PID2_REVISION_Pos       4            /**< \brief (DSU_PID2) Revision Number */
-#define DSU_PID2_REVISION_Msk       (_U(0xF) << DSU_PID2_REVISION_Pos)
+#define DSU_PID2_REVISION_Msk       (0xFul << DSU_PID2_REVISION_Pos)
 #define DSU_PID2_REVISION(value)    (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
-#define DSU_PID2_MASK               _U(0x000000FF) /**< \brief (DSU_PID2) MASK Register */
+#define DSU_PID2_MASK               0x000000FFul /**< \brief (DSU_PID2) MASK Register */
 
 /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/  32) Peripheral Identification 3 -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -411,15 +426,15 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_PID3_OFFSET             0x1FEC       /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
-#define DSU_PID3_RESETVALUE         _U(0x00000000) /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
+#define DSU_PID3_RESETVALUE         0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
 
 #define DSU_PID3_CUSMOD_Pos         0            /**< \brief (DSU_PID3) ARM CUSMOD */
-#define DSU_PID3_CUSMOD_Msk         (_U(0xF) << DSU_PID3_CUSMOD_Pos)
+#define DSU_PID3_CUSMOD_Msk         (0xFul << DSU_PID3_CUSMOD_Pos)
 #define DSU_PID3_CUSMOD(value)      (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
 #define DSU_PID3_REVAND_Pos         4            /**< \brief (DSU_PID3) Revision Number */
-#define DSU_PID3_REVAND_Msk         (_U(0xF) << DSU_PID3_REVAND_Pos)
+#define DSU_PID3_REVAND_Msk         (0xFul << DSU_PID3_REVAND_Pos)
 #define DSU_PID3_REVAND(value)      (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
-#define DSU_PID3_MASK               _U(0x000000FF) /**< \brief (DSU_PID3) MASK Register */
+#define DSU_PID3_MASK               0x000000FFul /**< \brief (DSU_PID3) MASK Register */
 
 /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/  32) Component Identification 0 -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -433,12 +448,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_CID0_OFFSET             0x1FF0       /**< \brief (DSU_CID0 offset) Component Identification 0 */
-#define DSU_CID0_RESETVALUE         _U(0x0000000D) /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
+#define DSU_CID0_RESETVALUE         0x0000000Dul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
 
 #define DSU_CID0_PREAMBLEB0_Pos     0            /**< \brief (DSU_CID0) Preamble Byte 0 */
-#define DSU_CID0_PREAMBLEB0_Msk     (_U(0xFF) << DSU_CID0_PREAMBLEB0_Pos)
+#define DSU_CID0_PREAMBLEB0_Msk     (0xFFul << DSU_CID0_PREAMBLEB0_Pos)
 #define DSU_CID0_PREAMBLEB0(value)  (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
-#define DSU_CID0_MASK               _U(0x000000FF) /**< \brief (DSU_CID0) MASK Register */
+#define DSU_CID0_MASK               0x000000FFul /**< \brief (DSU_CID0) MASK Register */
 
 /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/  32) Component Identification 1 -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -453,15 +468,15 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_CID1_OFFSET             0x1FF4       /**< \brief (DSU_CID1 offset) Component Identification 1 */
-#define DSU_CID1_RESETVALUE         _U(0x00000010) /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
+#define DSU_CID1_RESETVALUE         0x00000010ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
 
 #define DSU_CID1_PREAMBLE_Pos       0            /**< \brief (DSU_CID1) Preamble */
-#define DSU_CID1_PREAMBLE_Msk       (_U(0xF) << DSU_CID1_PREAMBLE_Pos)
+#define DSU_CID1_PREAMBLE_Msk       (0xFul << DSU_CID1_PREAMBLE_Pos)
 #define DSU_CID1_PREAMBLE(value)    (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
 #define DSU_CID1_CCLASS_Pos         4            /**< \brief (DSU_CID1) Component Class */
-#define DSU_CID1_CCLASS_Msk         (_U(0xF) << DSU_CID1_CCLASS_Pos)
+#define DSU_CID1_CCLASS_Msk         (0xFul << DSU_CID1_CCLASS_Pos)
 #define DSU_CID1_CCLASS(value)      (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
-#define DSU_CID1_MASK               _U(0x000000FF) /**< \brief (DSU_CID1) MASK Register */
+#define DSU_CID1_MASK               0x000000FFul /**< \brief (DSU_CID1) MASK Register */
 
 /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/  32) Component Identification 2 -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -475,12 +490,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_CID2_OFFSET             0x1FF8       /**< \brief (DSU_CID2 offset) Component Identification 2 */
-#define DSU_CID2_RESETVALUE         _U(0x00000005) /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
+#define DSU_CID2_RESETVALUE         0x00000005ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
 
 #define DSU_CID2_PREAMBLEB2_Pos     0            /**< \brief (DSU_CID2) Preamble Byte 2 */
-#define DSU_CID2_PREAMBLEB2_Msk     (_U(0xFF) << DSU_CID2_PREAMBLEB2_Pos)
+#define DSU_CID2_PREAMBLEB2_Msk     (0xFFul << DSU_CID2_PREAMBLEB2_Pos)
 #define DSU_CID2_PREAMBLEB2(value)  (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
-#define DSU_CID2_MASK               _U(0x000000FF) /**< \brief (DSU_CID2) MASK Register */
+#define DSU_CID2_MASK               0x000000FFul /**< \brief (DSU_CID2) MASK Register */
 
 /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/  32) Component Identification 3 -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -494,12 +509,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define DSU_CID3_OFFSET             0x1FFC       /**< \brief (DSU_CID3 offset) Component Identification 3 */
-#define DSU_CID3_RESETVALUE         _U(0x000000B1) /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
+#define DSU_CID3_RESETVALUE         0x000000B1ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
 
 #define DSU_CID3_PREAMBLEB3_Pos     0            /**< \brief (DSU_CID3) Preamble Byte 3 */
-#define DSU_CID3_PREAMBLEB3_Msk     (_U(0xFF) << DSU_CID3_PREAMBLEB3_Pos)
+#define DSU_CID3_PREAMBLEB3_Msk     (0xFFul << DSU_CID3_PREAMBLEB3_Pos)
 #define DSU_CID3_PREAMBLEB3(value)  (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
-#define DSU_CID3_MASK               _U(0x000000FF) /**< \brief (DSU_CID3) MASK Register */
+#define DSU_CID3_MASK               0x000000FFul /**< \brief (DSU_CID3) MASK Register */
 
 /** \brief DSU hardware registers */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

asf/sam0/utils/cmsis/samd21/include/component/eic.h

@@ -3,24 +3,39 @@
  *
  * \brief Component description for EIC
  *
- * Copyright (c) 2016 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *
  * \asf_license_stop
  *
@@ -51,13 +66,13 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EIC_CTRL_OFFSET             0x00         /**< \brief (EIC_CTRL offset) Control */
-#define EIC_CTRL_RESETVALUE         _U(0x00)     /**< \brief (EIC_CTRL reset_value) Control */
+#define EIC_CTRL_RESETVALUE         0x00ul       /**< \brief (EIC_CTRL reset_value) Control */
 
 #define EIC_CTRL_SWRST_Pos          0            /**< \brief (EIC_CTRL) Software Reset */
-#define EIC_CTRL_SWRST              (_U(0x1) << EIC_CTRL_SWRST_Pos)
+#define EIC_CTRL_SWRST              (0x1ul << EIC_CTRL_SWRST_Pos)
 #define EIC_CTRL_ENABLE_Pos         1            /**< \brief (EIC_CTRL) Enable */
-#define EIC_CTRL_ENABLE             (_U(0x1) << EIC_CTRL_ENABLE_Pos)
-#define EIC_CTRL_MASK               _U(0x03)     /**< \brief (EIC_CTRL) MASK Register */
+#define EIC_CTRL_ENABLE             (0x1ul << EIC_CTRL_ENABLE_Pos)
+#define EIC_CTRL_MASK               0x03ul       /**< \brief (EIC_CTRL) MASK Register */
 
 /* -------- EIC_STATUS : (EIC Offset: 0x01) (R/   8) Status -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -71,11 +86,11 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EIC_STATUS_OFFSET           0x01         /**< \brief (EIC_STATUS offset) Status */
-#define EIC_STATUS_RESETVALUE       _U(0x00)     /**< \brief (EIC_STATUS reset_value) Status */
+#define EIC_STATUS_RESETVALUE       0x00ul       /**< \brief (EIC_STATUS reset_value) Status */
 
 #define EIC_STATUS_SYNCBUSY_Pos     7            /**< \brief (EIC_STATUS) Synchronization Busy */
-#define EIC_STATUS_SYNCBUSY         (_U(0x1) << EIC_STATUS_SYNCBUSY_Pos)
-#define EIC_STATUS_MASK             _U(0x80)     /**< \brief (EIC_STATUS) MASK Register */
+#define EIC_STATUS_SYNCBUSY         (0x1ul << EIC_STATUS_SYNCBUSY_Pos)
+#define EIC_STATUS_MASK             0x80ul       /**< \brief (EIC_STATUS) MASK Register */
 
 /* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W  8) Non-Maskable Interrupt Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,17 +105,17 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EIC_NMICTRL_OFFSET          0x02         /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
-#define EIC_NMICTRL_RESETVALUE      _U(0x00)     /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
+#define EIC_NMICTRL_RESETVALUE      0x00ul       /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
 
 #define EIC_NMICTRL_NMISENSE_Pos    0            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
-#define EIC_NMICTRL_NMISENSE_Msk    (_U(0x7) << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_Msk    (0x7ul << EIC_NMICTRL_NMISENSE_Pos)
 #define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
-#define   EIC_NMICTRL_NMISENSE_NONE_Val   _U(0x0)   /**< \brief (EIC_NMICTRL) No detection */
-#define   EIC_NMICTRL_NMISENSE_RISE_Val   _U(0x1)   /**< \brief (EIC_NMICTRL) Rising-edge detection */
-#define   EIC_NMICTRL_NMISENSE_FALL_Val   _U(0x2)   /**< \brief (EIC_NMICTRL) Falling-edge detection */
-#define   EIC_NMICTRL_NMISENSE_BOTH_Val   _U(0x3)   /**< \brief (EIC_NMICTRL) Both-edges detection */
-#define   EIC_NMICTRL_NMISENSE_HIGH_Val   _U(0x4)   /**< \brief (EIC_NMICTRL) High-level detection */
-#define   EIC_NMICTRL_NMISENSE_LOW_Val    _U(0x5)   /**< \brief (EIC_NMICTRL) Low-level detection */
+#define   EIC_NMICTRL_NMISENSE_NONE_Val   0x0ul  /**< \brief (EIC_NMICTRL) No detection */
+#define   EIC_NMICTRL_NMISENSE_RISE_Val   0x1ul  /**< \brief (EIC_NMICTRL) Rising-edge detection */
+#define   EIC_NMICTRL_NMISENSE_FALL_Val   0x2ul  /**< \brief (EIC_NMICTRL) Falling-edge detection */
+#define   EIC_NMICTRL_NMISENSE_BOTH_Val   0x3ul  /**< \brief (EIC_NMICTRL) Both-edges detection */
+#define   EIC_NMICTRL_NMISENSE_HIGH_Val   0x4ul  /**< \brief (EIC_NMICTRL) High-level detection */
+#define   EIC_NMICTRL_NMISENSE_LOW_Val    0x5ul  /**< \brief (EIC_NMICTRL) Low-level detection */
 #define EIC_NMICTRL_NMISENSE_NONE   (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
 #define EIC_NMICTRL_NMISENSE_RISE   (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
 #define EIC_NMICTRL_NMISENSE_FALL   (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
@@ -108,8 +123,8 @@ typedef union {
 #define EIC_NMICTRL_NMISENSE_HIGH   (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
 #define EIC_NMICTRL_NMISENSE_LOW    (EIC_NMICTRL_NMISENSE_LOW_Val  << EIC_NMICTRL_NMISENSE_Pos)
 #define EIC_NMICTRL_NMIFILTEN_Pos   3            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
-#define EIC_NMICTRL_NMIFILTEN       (_U(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)
-#define EIC_NMICTRL_MASK            _U(0x0F)     /**< \brief (EIC_NMICTRL) MASK Register */
+#define EIC_NMICTRL_NMIFILTEN       (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos)
+#define EIC_NMICTRL_MASK            0x0Ful       /**< \brief (EIC_NMICTRL) MASK Register */
 
 /* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W  8) Non-Maskable Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -123,11 +138,11 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EIC_NMIFLAG_OFFSET          0x03         /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
-#define EIC_NMIFLAG_RESETVALUE      _U(0x00)     /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
+#define EIC_NMIFLAG_RESETVALUE      0x00ul       /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
 
 #define EIC_NMIFLAG_NMI_Pos         0            /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
-#define EIC_NMIFLAG_NMI             (_U(0x1) << EIC_NMIFLAG_NMI_Pos)
-#define EIC_NMIFLAG_MASK            _U(0x01)     /**< \brief (EIC_NMIFLAG) MASK Register */
+#define EIC_NMIFLAG_NMI             (0x1ul << EIC_NMIFLAG_NMI_Pos)
+#define EIC_NMIFLAG_MASK            0x01ul       /**< \brief (EIC_NMIFLAG) MASK Register */
 
 /* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -160,7 +175,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EIC_EVCTRL_OFFSET           0x04         /**< \brief (EIC_EVCTRL offset) Event Control */
-#define EIC_EVCTRL_RESETVALUE       _U(0x00000000) /**< \brief (EIC_EVCTRL reset_value) Event Control */
+#define EIC_EVCTRL_RESETVALUE       0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */
 
 #define EIC_EVCTRL_EXTINTEO0_Pos    0            /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */
 #define EIC_EVCTRL_EXTINTEO0        (1 << EIC_EVCTRL_EXTINTEO0_Pos)
@@ -195,9 +210,9 @@ typedef union {
 #define EIC_EVCTRL_EXTINTEO15_Pos   15           /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
 #define EIC_EVCTRL_EXTINTEO15       (1 << EIC_EVCTRL_EXTINTEO15_Pos)
 #define EIC_EVCTRL_EXTINTEO_Pos     0            /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO_Msk     (_U(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)
+#define EIC_EVCTRL_EXTINTEO_Msk     (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos)
 #define EIC_EVCTRL_EXTINTEO(value)  (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
-#define EIC_EVCTRL_MASK             _U(0x0000FFFF) /**< \brief (EIC_EVCTRL) MASK Register */
+#define EIC_EVCTRL_MASK             0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */
 
 /* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -230,7 +245,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EIC_INTENCLR_OFFSET         0x08         /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
-#define EIC_INTENCLR_RESETVALUE     _U(0x00000000) /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
+#define EIC_INTENCLR_RESETVALUE     0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
 
 #define EIC_INTENCLR_EXTINT0_Pos    0            /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */
 #define EIC_INTENCLR_EXTINT0        (1 << EIC_INTENCLR_EXTINT0_Pos)
@@ -265,9 +280,9 @@ typedef union {
 #define EIC_INTENCLR_EXTINT15_Pos   15           /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
 #define EIC_INTENCLR_EXTINT15       (1 << EIC_INTENCLR_EXTINT15_Pos)
 #define EIC_INTENCLR_EXTINT_Pos     0            /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
-#define EIC_INTENCLR_EXTINT_Msk     (_U(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)
+#define EIC_INTENCLR_EXTINT_Msk     (0xFFFFul << EIC_INTENCLR_EXTINT_Pos)
 #define EIC_INTENCLR_EXTINT(value)  (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
-#define EIC_INTENCLR_MASK           _U(0x0000FFFF) /**< \brief (EIC_INTENCLR) MASK Register */
+#define EIC_INTENCLR_MASK           0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */
 
 /* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -300,7 +315,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EIC_INTENSET_OFFSET         0x0C         /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
-#define EIC_INTENSET_RESETVALUE     _U(0x00000000) /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
+#define EIC_INTENSET_RESETVALUE     0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
 
 #define EIC_INTENSET_EXTINT0_Pos    0            /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */
 #define EIC_INTENSET_EXTINT0        (1 << EIC_INTENSET_EXTINT0_Pos)
@@ -335,9 +350,9 @@ typedef union {
 #define EIC_INTENSET_EXTINT15_Pos   15           /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
 #define EIC_INTENSET_EXTINT15       (1 << EIC_INTENSET_EXTINT15_Pos)
 #define EIC_INTENSET_EXTINT_Pos     0            /**< \brief (EIC_INTENSET) External Interrupt x Enable */
-#define EIC_INTENSET_EXTINT_Msk     (_U(0xFFFF) << EIC_INTENSET_EXTINT_Pos)
+#define EIC_INTENSET_EXTINT_Msk     (0xFFFFul << EIC_INTENSET_EXTINT_Pos)
 #define EIC_INTENSET_EXTINT(value)  (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
-#define EIC_INTENSET_MASK           _U(0x0000FFFF) /**< \brief (EIC_INTENSET) MASK Register */
+#define EIC_INTENSET_MASK           0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */
 
 /* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -370,7 +385,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EIC_INTFLAG_OFFSET          0x10         /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define EIC_INTFLAG_RESETVALUE      _U(0x00000000) /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+#define EIC_INTFLAG_RESETVALUE      0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
 
 #define EIC_INTFLAG_EXTINT0_Pos     0            /**< \brief (EIC_INTFLAG) External Interrupt 0 */
 #define EIC_INTFLAG_EXTINT0         (1 << EIC_INTFLAG_EXTINT0_Pos)
@@ -405,9 +420,9 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 #define EIC_INTFLAG_EXTINT15_Pos    15           /**< \brief (EIC_INTFLAG) External Interrupt 15 */
 #define EIC_INTFLAG_EXTINT15        (1 << EIC_INTFLAG_EXTINT15_Pos)
 #define EIC_INTFLAG_EXTINT_Pos      0            /**< \brief (EIC_INTFLAG) External Interrupt x */
-#define EIC_INTFLAG_EXTINT_Msk      (_U(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)
+#define EIC_INTFLAG_EXTINT_Msk      (0xFFFFul << EIC_INTFLAG_EXTINT_Pos)
 #define EIC_INTFLAG_EXTINT(value)   (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
-#define EIC_INTFLAG_MASK            _U(0x0000FFFF) /**< \brief (EIC_INTFLAG) MASK Register */
+#define EIC_INTFLAG_MASK            0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */
 
 /* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -440,7 +455,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EIC_WAKEUP_OFFSET           0x14         /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */
-#define EIC_WAKEUP_RESETVALUE       _U(0x00000000) /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
+#define EIC_WAKEUP_RESETVALUE       0x00000000ul /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
 
 #define EIC_WAKEUP_WAKEUPEN0_Pos    0            /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */
 #define EIC_WAKEUP_WAKEUPEN0        (1 << EIC_WAKEUP_WAKEUPEN0_Pos)
@@ -475,9 +490,9 @@ typedef union {
 #define EIC_WAKEUP_WAKEUPEN15_Pos   15           /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
 #define EIC_WAKEUP_WAKEUPEN15       (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
 #define EIC_WAKEUP_WAKEUPEN_Pos     0            /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
-#define EIC_WAKEUP_WAKEUPEN_Msk     (_U(0xFFFF) << EIC_WAKEUP_WAKEUPEN_Pos)
+#define EIC_WAKEUP_WAKEUPEN_Msk     (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos)
 #define EIC_WAKEUP_WAKEUPEN(value)  (EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos))
-#define EIC_WAKEUP_MASK             _U(0x0000FFFF) /**< \brief (EIC_WAKEUP) MASK Register */
+#define EIC_WAKEUP_MASK             0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */
 
 /* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -505,17 +520,17 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EIC_CONFIG_OFFSET           0x18         /**< \brief (EIC_CONFIG offset) Configuration n */
-#define EIC_CONFIG_RESETVALUE       _U(0x00000000) /**< \brief (EIC_CONFIG reset_value) Configuration n */
+#define EIC_CONFIG_RESETVALUE       0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */
 
 #define EIC_CONFIG_SENSE0_Pos       0            /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
-#define EIC_CONFIG_SENSE0_Msk       (_U(0x7) << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_Msk       (0x7ul << EIC_CONFIG_SENSE0_Pos)
 #define EIC_CONFIG_SENSE0(value)    (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
-#define   EIC_CONFIG_SENSE0_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE0_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising-edge detection */
-#define   EIC_CONFIG_SENSE0_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling-edge detection */
-#define   EIC_CONFIG_SENSE0_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both-edges detection */
-#define   EIC_CONFIG_SENSE0_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High-level detection */
-#define   EIC_CONFIG_SENSE0_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low-level detection */
+#define   EIC_CONFIG_SENSE0_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE0_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising-edge detection */
+#define   EIC_CONFIG_SENSE0_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling-edge detection */
+#define   EIC_CONFIG_SENSE0_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both-edges detection */
+#define   EIC_CONFIG_SENSE0_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High-level detection */
+#define   EIC_CONFIG_SENSE0_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low-level detection */
 #define EIC_CONFIG_SENSE0_NONE      (EIC_CONFIG_SENSE0_NONE_Val    << EIC_CONFIG_SENSE0_Pos)
 #define EIC_CONFIG_SENSE0_RISE      (EIC_CONFIG_SENSE0_RISE_Val    << EIC_CONFIG_SENSE0_Pos)
 #define EIC_CONFIG_SENSE0_FALL      (EIC_CONFIG_SENSE0_FALL_Val    << EIC_CONFIG_SENSE0_Pos)
@@ -523,16 +538,16 @@ typedef union {
 #define EIC_CONFIG_SENSE0_HIGH      (EIC_CONFIG_SENSE0_HIGH_Val    << EIC_CONFIG_SENSE0_Pos)
 #define EIC_CONFIG_SENSE0_LOW       (EIC_CONFIG_SENSE0_LOW_Val     << EIC_CONFIG_SENSE0_Pos)
 #define EIC_CONFIG_FILTEN0_Pos      3            /**< \brief (EIC_CONFIG) Filter 0 Enable */
-#define EIC_CONFIG_FILTEN0          (_U(0x1) << EIC_CONFIG_FILTEN0_Pos)
+#define EIC_CONFIG_FILTEN0          (0x1ul << EIC_CONFIG_FILTEN0_Pos)
 #define EIC_CONFIG_SENSE1_Pos       4            /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
-#define EIC_CONFIG_SENSE1_Msk       (_U(0x7) << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_Msk       (0x7ul << EIC_CONFIG_SENSE1_Pos)
 #define EIC_CONFIG_SENSE1(value)    (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
-#define   EIC_CONFIG_SENSE1_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE1_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE1_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE1_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE1_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE1_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define   EIC_CONFIG_SENSE1_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE1_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE1_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE1_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE1_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE1_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
 #define EIC_CONFIG_SENSE1_NONE      (EIC_CONFIG_SENSE1_NONE_Val    << EIC_CONFIG_SENSE1_Pos)
 #define EIC_CONFIG_SENSE1_RISE      (EIC_CONFIG_SENSE1_RISE_Val    << EIC_CONFIG_SENSE1_Pos)
 #define EIC_CONFIG_SENSE1_FALL      (EIC_CONFIG_SENSE1_FALL_Val    << EIC_CONFIG_SENSE1_Pos)
@@ -540,16 +555,16 @@ typedef union {
 #define EIC_CONFIG_SENSE1_HIGH      (EIC_CONFIG_SENSE1_HIGH_Val    << EIC_CONFIG_SENSE1_Pos)
 #define EIC_CONFIG_SENSE1_LOW       (EIC_CONFIG_SENSE1_LOW_Val     << EIC_CONFIG_SENSE1_Pos)
 #define EIC_CONFIG_FILTEN1_Pos      7            /**< \brief (EIC_CONFIG) Filter 1 Enable */
-#define EIC_CONFIG_FILTEN1          (_U(0x1) << EIC_CONFIG_FILTEN1_Pos)
+#define EIC_CONFIG_FILTEN1          (0x1ul << EIC_CONFIG_FILTEN1_Pos)
 #define EIC_CONFIG_SENSE2_Pos       8            /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
-#define EIC_CONFIG_SENSE2_Msk       (_U(0x7) << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_Msk       (0x7ul << EIC_CONFIG_SENSE2_Pos)
 #define EIC_CONFIG_SENSE2(value)    (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
-#define   EIC_CONFIG_SENSE2_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE2_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE2_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE2_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE2_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE2_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define   EIC_CONFIG_SENSE2_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE2_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE2_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE2_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE2_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE2_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
 #define EIC_CONFIG_SENSE2_NONE      (EIC_CONFIG_SENSE2_NONE_Val    << EIC_CONFIG_SENSE2_Pos)
 #define EIC_CONFIG_SENSE2_RISE      (EIC_CONFIG_SENSE2_RISE_Val    << EIC_CONFIG_SENSE2_Pos)
 #define EIC_CONFIG_SENSE2_FALL      (EIC_CONFIG_SENSE2_FALL_Val    << EIC_CONFIG_SENSE2_Pos)
@@ -557,16 +572,16 @@ typedef union {
 #define EIC_CONFIG_SENSE2_HIGH      (EIC_CONFIG_SENSE2_HIGH_Val    << EIC_CONFIG_SENSE2_Pos)
 #define EIC_CONFIG_SENSE2_LOW       (EIC_CONFIG_SENSE2_LOW_Val     << EIC_CONFIG_SENSE2_Pos)
 #define EIC_CONFIG_FILTEN2_Pos      11           /**< \brief (EIC_CONFIG) Filter 2 Enable */
-#define EIC_CONFIG_FILTEN2          (_U(0x1) << EIC_CONFIG_FILTEN2_Pos)
+#define EIC_CONFIG_FILTEN2          (0x1ul << EIC_CONFIG_FILTEN2_Pos)
 #define EIC_CONFIG_SENSE3_Pos       12           /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
-#define EIC_CONFIG_SENSE3_Msk       (_U(0x7) << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_Msk       (0x7ul << EIC_CONFIG_SENSE3_Pos)
 #define EIC_CONFIG_SENSE3(value)    (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
-#define   EIC_CONFIG_SENSE3_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE3_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE3_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE3_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE3_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE3_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define   EIC_CONFIG_SENSE3_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE3_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE3_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE3_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE3_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE3_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
 #define EIC_CONFIG_SENSE3_NONE      (EIC_CONFIG_SENSE3_NONE_Val    << EIC_CONFIG_SENSE3_Pos)
 #define EIC_CONFIG_SENSE3_RISE      (EIC_CONFIG_SENSE3_RISE_Val    << EIC_CONFIG_SENSE3_Pos)
 #define EIC_CONFIG_SENSE3_FALL      (EIC_CONFIG_SENSE3_FALL_Val    << EIC_CONFIG_SENSE3_Pos)
@@ -574,16 +589,16 @@ typedef union {
 #define EIC_CONFIG_SENSE3_HIGH      (EIC_CONFIG_SENSE3_HIGH_Val    << EIC_CONFIG_SENSE3_Pos)
 #define EIC_CONFIG_SENSE3_LOW       (EIC_CONFIG_SENSE3_LOW_Val     << EIC_CONFIG_SENSE3_Pos)
 #define EIC_CONFIG_FILTEN3_Pos      15           /**< \brief (EIC_CONFIG) Filter 3 Enable */
-#define EIC_CONFIG_FILTEN3          (_U(0x1) << EIC_CONFIG_FILTEN3_Pos)
+#define EIC_CONFIG_FILTEN3          (0x1ul << EIC_CONFIG_FILTEN3_Pos)
 #define EIC_CONFIG_SENSE4_Pos       16           /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
-#define EIC_CONFIG_SENSE4_Msk       (_U(0x7) << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_Msk       (0x7ul << EIC_CONFIG_SENSE4_Pos)
 #define EIC_CONFIG_SENSE4(value)    (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
-#define   EIC_CONFIG_SENSE4_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE4_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE4_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE4_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE4_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE4_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define   EIC_CONFIG_SENSE4_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE4_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE4_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE4_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE4_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE4_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
 #define EIC_CONFIG_SENSE4_NONE      (EIC_CONFIG_SENSE4_NONE_Val    << EIC_CONFIG_SENSE4_Pos)
 #define EIC_CONFIG_SENSE4_RISE      (EIC_CONFIG_SENSE4_RISE_Val    << EIC_CONFIG_SENSE4_Pos)
 #define EIC_CONFIG_SENSE4_FALL      (EIC_CONFIG_SENSE4_FALL_Val    << EIC_CONFIG_SENSE4_Pos)
@@ -591,16 +606,16 @@ typedef union {
 #define EIC_CONFIG_SENSE4_HIGH      (EIC_CONFIG_SENSE4_HIGH_Val    << EIC_CONFIG_SENSE4_Pos)
 #define EIC_CONFIG_SENSE4_LOW       (EIC_CONFIG_SENSE4_LOW_Val     << EIC_CONFIG_SENSE4_Pos)
 #define EIC_CONFIG_FILTEN4_Pos      19           /**< \brief (EIC_CONFIG) Filter 4 Enable */
-#define EIC_CONFIG_FILTEN4          (_U(0x1) << EIC_CONFIG_FILTEN4_Pos)
+#define EIC_CONFIG_FILTEN4          (0x1ul << EIC_CONFIG_FILTEN4_Pos)
 #define EIC_CONFIG_SENSE5_Pos       20           /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
-#define EIC_CONFIG_SENSE5_Msk       (_U(0x7) << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_Msk       (0x7ul << EIC_CONFIG_SENSE5_Pos)
 #define EIC_CONFIG_SENSE5(value)    (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
-#define   EIC_CONFIG_SENSE5_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE5_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE5_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE5_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE5_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE5_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define   EIC_CONFIG_SENSE5_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE5_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE5_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE5_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE5_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE5_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
 #define EIC_CONFIG_SENSE5_NONE      (EIC_CONFIG_SENSE5_NONE_Val    << EIC_CONFIG_SENSE5_Pos)
 #define EIC_CONFIG_SENSE5_RISE      (EIC_CONFIG_SENSE5_RISE_Val    << EIC_CONFIG_SENSE5_Pos)
 #define EIC_CONFIG_SENSE5_FALL      (EIC_CONFIG_SENSE5_FALL_Val    << EIC_CONFIG_SENSE5_Pos)
@@ -608,16 +623,16 @@ typedef union {
 #define EIC_CONFIG_SENSE5_HIGH      (EIC_CONFIG_SENSE5_HIGH_Val    << EIC_CONFIG_SENSE5_Pos)
 #define EIC_CONFIG_SENSE5_LOW       (EIC_CONFIG_SENSE5_LOW_Val     << EIC_CONFIG_SENSE5_Pos)
 #define EIC_CONFIG_FILTEN5_Pos      23           /**< \brief (EIC_CONFIG) Filter 5 Enable */
-#define EIC_CONFIG_FILTEN5          (_U(0x1) << EIC_CONFIG_FILTEN5_Pos)
+#define EIC_CONFIG_FILTEN5          (0x1ul << EIC_CONFIG_FILTEN5_Pos)
 #define EIC_CONFIG_SENSE6_Pos       24           /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
-#define EIC_CONFIG_SENSE6_Msk       (_U(0x7) << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_Msk       (0x7ul << EIC_CONFIG_SENSE6_Pos)
 #define EIC_CONFIG_SENSE6(value)    (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
-#define   EIC_CONFIG_SENSE6_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE6_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE6_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE6_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE6_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE6_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define   EIC_CONFIG_SENSE6_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE6_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE6_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE6_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE6_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE6_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
 #define EIC_CONFIG_SENSE6_NONE      (EIC_CONFIG_SENSE6_NONE_Val    << EIC_CONFIG_SENSE6_Pos)
 #define EIC_CONFIG_SENSE6_RISE      (EIC_CONFIG_SENSE6_RISE_Val    << EIC_CONFIG_SENSE6_Pos)
 #define EIC_CONFIG_SENSE6_FALL      (EIC_CONFIG_SENSE6_FALL_Val    << EIC_CONFIG_SENSE6_Pos)
@@ -625,16 +640,16 @@ typedef union {
 #define EIC_CONFIG_SENSE6_HIGH      (EIC_CONFIG_SENSE6_HIGH_Val    << EIC_CONFIG_SENSE6_Pos)
 #define EIC_CONFIG_SENSE6_LOW       (EIC_CONFIG_SENSE6_LOW_Val     << EIC_CONFIG_SENSE6_Pos)
 #define EIC_CONFIG_FILTEN6_Pos      27           /**< \brief (EIC_CONFIG) Filter 6 Enable */
-#define EIC_CONFIG_FILTEN6          (_U(0x1) << EIC_CONFIG_FILTEN6_Pos)
+#define EIC_CONFIG_FILTEN6          (0x1ul << EIC_CONFIG_FILTEN6_Pos)
 #define EIC_CONFIG_SENSE7_Pos       28           /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
-#define EIC_CONFIG_SENSE7_Msk       (_U(0x7) << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_Msk       (0x7ul << EIC_CONFIG_SENSE7_Pos)
 #define EIC_CONFIG_SENSE7(value)    (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
-#define   EIC_CONFIG_SENSE7_NONE_Val      _U(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE7_RISE_Val      _U(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE7_FALL_Val      _U(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE7_BOTH_Val      _U(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE7_HIGH_Val      _U(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE7_LOW_Val       _U(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define   EIC_CONFIG_SENSE7_NONE_Val      0x0ul  /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE7_RISE_Val      0x1ul  /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE7_FALL_Val      0x2ul  /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE7_BOTH_Val      0x3ul  /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE7_HIGH_Val      0x4ul  /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE7_LOW_Val       0x5ul  /**< \brief (EIC_CONFIG) Low level detection */
 #define EIC_CONFIG_SENSE7_NONE      (EIC_CONFIG_SENSE7_NONE_Val    << EIC_CONFIG_SENSE7_Pos)
 #define EIC_CONFIG_SENSE7_RISE      (EIC_CONFIG_SENSE7_RISE_Val    << EIC_CONFIG_SENSE7_Pos)
 #define EIC_CONFIG_SENSE7_FALL      (EIC_CONFIG_SENSE7_FALL_Val    << EIC_CONFIG_SENSE7_Pos)
@@ -642,8 +657,8 @@ typedef union {
 #define EIC_CONFIG_SENSE7_HIGH      (EIC_CONFIG_SENSE7_HIGH_Val    << EIC_CONFIG_SENSE7_Pos)
 #define EIC_CONFIG_SENSE7_LOW       (EIC_CONFIG_SENSE7_LOW_Val     << EIC_CONFIG_SENSE7_Pos)
 #define EIC_CONFIG_FILTEN7_Pos      31           /**< \brief (EIC_CONFIG) Filter 7 Enable */
-#define EIC_CONFIG_FILTEN7          (_U(0x1) << EIC_CONFIG_FILTEN7_Pos)
-#define EIC_CONFIG_MASK             _U(0xFFFFFFFF) /**< \brief (EIC_CONFIG) MASK Register */
+#define EIC_CONFIG_FILTEN7          (0x1ul << EIC_CONFIG_FILTEN7_Pos)
+#define EIC_CONFIG_MASK             0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */
 
 /** \brief EIC hardware registers */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

asf/sam0/utils/cmsis/samd21/include/component/evsys.h

@@ -3,24 +3,39 @@
  *
  * \brief Component description for EVSYS
  *
- * Copyright (c) 2016 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *
  * \asf_license_stop
  *
@@ -52,13 +67,13 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EVSYS_CTRL_OFFSET           0x00         /**< \brief (EVSYS_CTRL offset) Control */
-#define EVSYS_CTRL_RESETVALUE       _U(0x00)     /**< \brief (EVSYS_CTRL reset_value) Control */
+#define EVSYS_CTRL_RESETVALUE       0x00ul       /**< \brief (EVSYS_CTRL reset_value) Control */
 
 #define EVSYS_CTRL_SWRST_Pos        0            /**< \brief (EVSYS_CTRL) Software Reset */
-#define EVSYS_CTRL_SWRST            (_U(0x1) << EVSYS_CTRL_SWRST_Pos)
+#define EVSYS_CTRL_SWRST            (0x1ul << EVSYS_CTRL_SWRST_Pos)
 #define EVSYS_CTRL_GCLKREQ_Pos      4            /**< \brief (EVSYS_CTRL) Generic Clock Requests */
-#define EVSYS_CTRL_GCLKREQ          (_U(0x1) << EVSYS_CTRL_GCLKREQ_Pos)
-#define EVSYS_CTRL_MASK             _U(0x11)     /**< \brief (EVSYS_CTRL) MASK Register */
+#define EVSYS_CTRL_GCLKREQ          (0x1ul << EVSYS_CTRL_GCLKREQ_Pos)
+#define EVSYS_CTRL_MASK             0x11ul       /**< \brief (EVSYS_CTRL) MASK Register */
 
 /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -79,37 +94,37 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EVSYS_CHANNEL_OFFSET        0x04         /**< \brief (EVSYS_CHANNEL offset) Channel */
-#define EVSYS_CHANNEL_RESETVALUE    _U(0x00000000) /**< \brief (EVSYS_CHANNEL reset_value) Channel */
+#define EVSYS_CHANNEL_RESETVALUE    0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
 
 #define EVSYS_CHANNEL_CHANNEL_Pos   0            /**< \brief (EVSYS_CHANNEL) Channel Selection */
-#define EVSYS_CHANNEL_CHANNEL_Msk   (_U(0xF) << EVSYS_CHANNEL_CHANNEL_Pos)
+#define EVSYS_CHANNEL_CHANNEL_Msk   (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
 #define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
 #define EVSYS_CHANNEL_SWEVT_Pos     8            /**< \brief (EVSYS_CHANNEL) Software Event */
-#define EVSYS_CHANNEL_SWEVT         (_U(0x1) << EVSYS_CHANNEL_SWEVT_Pos)
+#define EVSYS_CHANNEL_SWEVT         (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
 #define EVSYS_CHANNEL_EVGEN_Pos     16           /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
-#define EVSYS_CHANNEL_EVGEN_Msk     (_U(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)
+#define EVSYS_CHANNEL_EVGEN_Msk     (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
 #define EVSYS_CHANNEL_EVGEN(value)  (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
 #define EVSYS_CHANNEL_PATH_Pos      24           /**< \brief (EVSYS_CHANNEL) Path Selection */
-#define EVSYS_CHANNEL_PATH_Msk      (_U(0x3) << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_Msk      (0x3ul << EVSYS_CHANNEL_PATH_Pos)
 #define EVSYS_CHANNEL_PATH(value)   (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
-#define   EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U(0x0)   /**< \brief (EVSYS_CHANNEL) Synchronous path */
-#define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U(0x1)   /**< \brief (EVSYS_CHANNEL) Resynchronized path */
-#define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U(0x2)   /**< \brief (EVSYS_CHANNEL) Asynchronous path */
+#define   EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) Synchronous path */
+#define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Resynchronized path */
+#define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Asynchronous path */
 #define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
 #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
 #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
 #define EVSYS_CHANNEL_EDGSEL_Pos    26           /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
-#define EVSYS_CHANNEL_EDGSEL_Msk    (_U(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_Msk    (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
 #define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
-#define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U(0x0)   /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
-#define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U(0x1)   /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
-#define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U(0x2)   /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
-#define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U(0x3)   /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul  /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul  /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul  /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
 #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
 #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
 #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
 #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_MASK          _U(0x0F7F010F) /**< \brief (EVSYS_CHANNEL) MASK Register */
+#define EVSYS_CHANNEL_MASK          0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */
 
 /* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -125,17 +140,17 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EVSYS_USER_OFFSET           0x08         /**< \brief (EVSYS_USER offset) User Multiplexer */
-#define EVSYS_USER_RESETVALUE       _U(0x0000)   /**< \brief (EVSYS_USER reset_value) User Multiplexer */
+#define EVSYS_USER_RESETVALUE       0x0000ul     /**< \brief (EVSYS_USER reset_value) User Multiplexer */
 
 #define EVSYS_USER_USER_Pos         0            /**< \brief (EVSYS_USER) User Multiplexer Selection */
-#define EVSYS_USER_USER_Msk         (_U(0x1F) << EVSYS_USER_USER_Pos)
+#define EVSYS_USER_USER_Msk         (0x1Ful << EVSYS_USER_USER_Pos)
 #define EVSYS_USER_USER(value)      (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
 #define EVSYS_USER_CHANNEL_Pos      8            /**< \brief (EVSYS_USER) Channel Event Selection */
-#define EVSYS_USER_CHANNEL_Msk      (_U(0x1F) << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_CHANNEL_Msk      (0x1Ful << EVSYS_USER_CHANNEL_Pos)
 #define EVSYS_USER_CHANNEL(value)   (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
-#define   EVSYS_USER_CHANNEL_0_Val        _U(0x0)   /**< \brief (EVSYS_USER) No Channel Output Selected */
+#define   EVSYS_USER_CHANNEL_0_Val        0x0ul  /**< \brief (EVSYS_USER) No Channel Output Selected */
 #define EVSYS_USER_CHANNEL_0        (EVSYS_USER_CHANNEL_0_Val      << EVSYS_USER_CHANNEL_Pos)
-#define EVSYS_USER_MASK             _U(0x1F1F)   /**< \brief (EVSYS_USER) MASK Register */
+#define EVSYS_USER_MASK             0x1F1Ful     /**< \brief (EVSYS_USER) MASK Register */
 
 /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/  32) Channel Status -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -181,7 +196,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EVSYS_CHSTATUS_OFFSET       0x0C         /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
-#define EVSYS_CHSTATUS_RESETVALUE   _U(0x000F00FF) /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
+#define EVSYS_CHSTATUS_RESETVALUE   0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
 
 #define EVSYS_CHSTATUS_USRRDY0_Pos  0            /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
 #define EVSYS_CHSTATUS_USRRDY0      (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
@@ -200,7 +215,7 @@ typedef union {
 #define EVSYS_CHSTATUS_USRRDY7_Pos  7            /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
 #define EVSYS_CHSTATUS_USRRDY7      (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
 #define EVSYS_CHSTATUS_USRRDY_Pos   0            /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
-#define EVSYS_CHSTATUS_USRRDY_Msk   (_U(0xFF) << EVSYS_CHSTATUS_USRRDY_Pos)
+#define EVSYS_CHSTATUS_USRRDY_Msk   (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
 #define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
 #define EVSYS_CHSTATUS_CHBUSY0_Pos  8            /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
 #define EVSYS_CHSTATUS_CHBUSY0      (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
@@ -219,7 +234,7 @@ typedef union {
 #define EVSYS_CHSTATUS_CHBUSY7_Pos  15           /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
 #define EVSYS_CHSTATUS_CHBUSY7      (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
 #define EVSYS_CHSTATUS_CHBUSY_Pos   8            /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
-#define EVSYS_CHSTATUS_CHBUSY_Msk   (_U(0xFF) << EVSYS_CHSTATUS_CHBUSY_Pos)
+#define EVSYS_CHSTATUS_CHBUSY_Msk   (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
 #define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
 #define EVSYS_CHSTATUS_USRRDY8_Pos  16           /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
 #define EVSYS_CHSTATUS_USRRDY8      (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
@@ -230,7 +245,7 @@ typedef union {
 #define EVSYS_CHSTATUS_USRRDY11_Pos 19           /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
 #define EVSYS_CHSTATUS_USRRDY11     (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
 #define EVSYS_CHSTATUS_USRRDYp8_Pos 16           /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
-#define EVSYS_CHSTATUS_USRRDYp8_Msk (_U(0xF) << EVSYS_CHSTATUS_USRRDYp8_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
 #define EVSYS_CHSTATUS_USRRDYp8(value) (EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))
 #define EVSYS_CHSTATUS_CHBUSY8_Pos  24           /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
 #define EVSYS_CHSTATUS_CHBUSY8      (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
@@ -241,9 +256,9 @@ typedef union {
 #define EVSYS_CHSTATUS_CHBUSY11_Pos 27           /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
 #define EVSYS_CHSTATUS_CHBUSY11     (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
 #define EVSYS_CHSTATUS_CHBUSYp8_Pos 24           /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
-#define EVSYS_CHSTATUS_CHBUSYp8_Msk (_U(0xF) << EVSYS_CHSTATUS_CHBUSYp8_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
 #define EVSYS_CHSTATUS_CHBUSYp8(value) (EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))
-#define EVSYS_CHSTATUS_MASK         _U(0x0F0FFFFF) /**< \brief (EVSYS_CHSTATUS) MASK Register */
+#define EVSYS_CHSTATUS_MASK         0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
 
 /* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -289,7 +304,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EVSYS_INTENCLR_OFFSET       0x10         /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
-#define EVSYS_INTENCLR_RESETVALUE   _U(0x00000000) /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
+#define EVSYS_INTENCLR_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
 
 #define EVSYS_INTENCLR_OVR0_Pos     0            /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
 #define EVSYS_INTENCLR_OVR0         (1 << EVSYS_INTENCLR_OVR0_Pos)
@@ -308,7 +323,7 @@ typedef union {
 #define EVSYS_INTENCLR_OVR7_Pos     7            /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
 #define EVSYS_INTENCLR_OVR7         (1 << EVSYS_INTENCLR_OVR7_Pos)
 #define EVSYS_INTENCLR_OVR_Pos      0            /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVR_Msk      (_U(0xFF) << EVSYS_INTENCLR_OVR_Pos)
+#define EVSYS_INTENCLR_OVR_Msk      (0xFFul << EVSYS_INTENCLR_OVR_Pos)
 #define EVSYS_INTENCLR_OVR(value)   (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
 #define EVSYS_INTENCLR_EVD0_Pos     8            /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
 #define EVSYS_INTENCLR_EVD0         (1 << EVSYS_INTENCLR_EVD0_Pos)
@@ -327,7 +342,7 @@ typedef union {
 #define EVSYS_INTENCLR_EVD7_Pos     15           /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
 #define EVSYS_INTENCLR_EVD7         (1 << EVSYS_INTENCLR_EVD7_Pos)
 #define EVSYS_INTENCLR_EVD_Pos      8            /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVD_Msk      (_U(0xFF) << EVSYS_INTENCLR_EVD_Pos)
+#define EVSYS_INTENCLR_EVD_Msk      (0xFFul << EVSYS_INTENCLR_EVD_Pos)
 #define EVSYS_INTENCLR_EVD(value)   (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
 #define EVSYS_INTENCLR_OVR8_Pos     16           /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
 #define EVSYS_INTENCLR_OVR8         (1 << EVSYS_INTENCLR_OVR8_Pos)
@@ -338,7 +353,7 @@ typedef union {
 #define EVSYS_INTENCLR_OVR11_Pos    19           /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
 #define EVSYS_INTENCLR_OVR11        (1 << EVSYS_INTENCLR_OVR11_Pos)
 #define EVSYS_INTENCLR_OVRp8_Pos    16           /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
-#define EVSYS_INTENCLR_OVRp8_Msk    (_U(0xF) << EVSYS_INTENCLR_OVRp8_Pos)
+#define EVSYS_INTENCLR_OVRp8_Msk    (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
 #define EVSYS_INTENCLR_OVRp8(value) (EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))
 #define EVSYS_INTENCLR_EVD8_Pos     24           /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
 #define EVSYS_INTENCLR_EVD8         (1 << EVSYS_INTENCLR_EVD8_Pos)
@@ -349,9 +364,9 @@ typedef union {
 #define EVSYS_INTENCLR_EVD11_Pos    27           /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
 #define EVSYS_INTENCLR_EVD11        (1 << EVSYS_INTENCLR_EVD11_Pos)
 #define EVSYS_INTENCLR_EVDp8_Pos    24           /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
-#define EVSYS_INTENCLR_EVDp8_Msk    (_U(0xF) << EVSYS_INTENCLR_EVDp8_Pos)
+#define EVSYS_INTENCLR_EVDp8_Msk    (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
 #define EVSYS_INTENCLR_EVDp8(value) (EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))
-#define EVSYS_INTENCLR_MASK         _U(0x0F0FFFFF) /**< \brief (EVSYS_INTENCLR) MASK Register */
+#define EVSYS_INTENCLR_MASK         0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
 
 /* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -397,7 +412,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EVSYS_INTENSET_OFFSET       0x14         /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
-#define EVSYS_INTENSET_RESETVALUE   _U(0x00000000) /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
+#define EVSYS_INTENSET_RESETVALUE   0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
 
 #define EVSYS_INTENSET_OVR0_Pos     0            /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
 #define EVSYS_INTENSET_OVR0         (1 << EVSYS_INTENSET_OVR0_Pos)
@@ -416,7 +431,7 @@ typedef union {
 #define EVSYS_INTENSET_OVR7_Pos     7            /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
 #define EVSYS_INTENSET_OVR7         (1 << EVSYS_INTENSET_OVR7_Pos)
 #define EVSYS_INTENSET_OVR_Pos      0            /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVR_Msk      (_U(0xFF) << EVSYS_INTENSET_OVR_Pos)
+#define EVSYS_INTENSET_OVR_Msk      (0xFFul << EVSYS_INTENSET_OVR_Pos)
 #define EVSYS_INTENSET_OVR(value)   (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
 #define EVSYS_INTENSET_EVD0_Pos     8            /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
 #define EVSYS_INTENSET_EVD0         (1 << EVSYS_INTENSET_EVD0_Pos)
@@ -435,7 +450,7 @@ typedef union {
 #define EVSYS_INTENSET_EVD7_Pos     15           /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
 #define EVSYS_INTENSET_EVD7         (1 << EVSYS_INTENSET_EVD7_Pos)
 #define EVSYS_INTENSET_EVD_Pos      8            /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVD_Msk      (_U(0xFF) << EVSYS_INTENSET_EVD_Pos)
+#define EVSYS_INTENSET_EVD_Msk      (0xFFul << EVSYS_INTENSET_EVD_Pos)
 #define EVSYS_INTENSET_EVD(value)   (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
 #define EVSYS_INTENSET_OVR8_Pos     16           /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
 #define EVSYS_INTENSET_OVR8         (1 << EVSYS_INTENSET_OVR8_Pos)
@@ -446,7 +461,7 @@ typedef union {
 #define EVSYS_INTENSET_OVR11_Pos    19           /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
 #define EVSYS_INTENSET_OVR11        (1 << EVSYS_INTENSET_OVR11_Pos)
 #define EVSYS_INTENSET_OVRp8_Pos    16           /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
-#define EVSYS_INTENSET_OVRp8_Msk    (_U(0xF) << EVSYS_INTENSET_OVRp8_Pos)
+#define EVSYS_INTENSET_OVRp8_Msk    (0xFul << EVSYS_INTENSET_OVRp8_Pos)
 #define EVSYS_INTENSET_OVRp8(value) (EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))
 #define EVSYS_INTENSET_EVD8_Pos     24           /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
 #define EVSYS_INTENSET_EVD8         (1 << EVSYS_INTENSET_EVD8_Pos)
@@ -457,9 +472,9 @@ typedef union {
 #define EVSYS_INTENSET_EVD11_Pos    27           /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
 #define EVSYS_INTENSET_EVD11        (1 << EVSYS_INTENSET_EVD11_Pos)
 #define EVSYS_INTENSET_EVDp8_Pos    24           /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
-#define EVSYS_INTENSET_EVDp8_Msk    (_U(0xF) << EVSYS_INTENSET_EVDp8_Pos)
+#define EVSYS_INTENSET_EVDp8_Msk    (0xFul << EVSYS_INTENSET_EVDp8_Pos)
 #define EVSYS_INTENSET_EVDp8(value) (EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))
-#define EVSYS_INTENSET_MASK         _U(0x0F0FFFFF) /**< \brief (EVSYS_INTENSET) MASK Register */
+#define EVSYS_INTENSET_MASK         0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
 
 /* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -505,7 +520,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define EVSYS_INTFLAG_OFFSET        0x18         /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
-#define EVSYS_INTFLAG_RESETVALUE    _U(0x00000000) /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
+#define EVSYS_INTFLAG_RESETVALUE    0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
 
 #define EVSYS_INTFLAG_OVR0_Pos      0            /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
 #define EVSYS_INTFLAG_OVR0          (1 << EVSYS_INTFLAG_OVR0_Pos)
@@ -524,7 +539,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 #define EVSYS_INTFLAG_OVR7_Pos      7            /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
 #define EVSYS_INTFLAG_OVR7          (1 << EVSYS_INTFLAG_OVR7_Pos)
 #define EVSYS_INTFLAG_OVR_Pos       0            /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
-#define EVSYS_INTFLAG_OVR_Msk       (_U(0xFF) << EVSYS_INTFLAG_OVR_Pos)
+#define EVSYS_INTFLAG_OVR_Msk       (0xFFul << EVSYS_INTFLAG_OVR_Pos)
 #define EVSYS_INTFLAG_OVR(value)    (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
 #define EVSYS_INTFLAG_EVD0_Pos      8            /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
 #define EVSYS_INTFLAG_EVD0          (1 << EVSYS_INTFLAG_EVD0_Pos)
@@ -543,7 +558,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 #define EVSYS_INTFLAG_EVD7_Pos      15           /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
 #define EVSYS_INTFLAG_EVD7          (1 << EVSYS_INTFLAG_EVD7_Pos)
 #define EVSYS_INTFLAG_EVD_Pos       8            /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
-#define EVSYS_INTFLAG_EVD_Msk       (_U(0xFF) << EVSYS_INTFLAG_EVD_Pos)
+#define EVSYS_INTFLAG_EVD_Msk       (0xFFul << EVSYS_INTFLAG_EVD_Pos)
 #define EVSYS_INTFLAG_EVD(value)    (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
 #define EVSYS_INTFLAG_OVR8_Pos      16           /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
 #define EVSYS_INTFLAG_OVR8          (1 << EVSYS_INTFLAG_OVR8_Pos)
@@ -554,7 +569,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 #define EVSYS_INTFLAG_OVR11_Pos     19           /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
 #define EVSYS_INTFLAG_OVR11         (1 << EVSYS_INTFLAG_OVR11_Pos)
 #define EVSYS_INTFLAG_OVRp8_Pos     16           /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
-#define EVSYS_INTFLAG_OVRp8_Msk     (_U(0xF) << EVSYS_INTFLAG_OVRp8_Pos)
+#define EVSYS_INTFLAG_OVRp8_Msk     (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
 #define EVSYS_INTFLAG_OVRp8(value)  (EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))
 #define EVSYS_INTFLAG_EVD8_Pos      24           /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
 #define EVSYS_INTFLAG_EVD8          (1 << EVSYS_INTFLAG_EVD8_Pos)
@@ -565,9 +580,9 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 #define EVSYS_INTFLAG_EVD11_Pos     27           /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
 #define EVSYS_INTFLAG_EVD11         (1 << EVSYS_INTFLAG_EVD11_Pos)
 #define EVSYS_INTFLAG_EVDp8_Pos     24           /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
-#define EVSYS_INTFLAG_EVDp8_Msk     (_U(0xF) << EVSYS_INTFLAG_EVDp8_Pos)
+#define EVSYS_INTFLAG_EVDp8_Msk     (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
 #define EVSYS_INTFLAG_EVDp8(value)  (EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))
-#define EVSYS_INTFLAG_MASK          _U(0x0F0FFFFF) /**< \brief (EVSYS_INTFLAG) MASK Register */
+#define EVSYS_INTFLAG_MASK          0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
 
 /** \brief EVSYS hardware registers */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

asf/sam0/utils/cmsis/samd21/include/component/gclk.h

@@ -3,24 +3,39 @@
  *
  * \brief Component description for GCLK
  *
- * Copyright (c) 2017 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *
  * \asf_license_stop
  *
@@ -50,11 +65,11 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define GCLK_CTRL_OFFSET            0x0          /**< \brief (GCLK_CTRL offset) Control */
-#define GCLK_CTRL_RESETVALUE        _U(0x00)     /**< \brief (GCLK_CTRL reset_value) Control */
+#define GCLK_CTRL_RESETVALUE        0x00ul       /**< \brief (GCLK_CTRL reset_value) Control */
 
 #define GCLK_CTRL_SWRST_Pos         0            /**< \brief (GCLK_CTRL) Software Reset */
-#define GCLK_CTRL_SWRST             (_U(0x1) << GCLK_CTRL_SWRST_Pos)
-#define GCLK_CTRL_MASK              _U(0x01)     /**< \brief (GCLK_CTRL) MASK Register */
+#define GCLK_CTRL_SWRST             (0x1ul << GCLK_CTRL_SWRST_Pos)
+#define GCLK_CTRL_MASK              0x01ul       /**< \brief (GCLK_CTRL) MASK Register */
 
 /* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/   8) Status -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -68,11 +83,11 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define GCLK_STATUS_OFFSET          0x1          /**< \brief (GCLK_STATUS offset) Status */
-#define GCLK_STATUS_RESETVALUE      _U(0x00)     /**< \brief (GCLK_STATUS reset_value) Status */
+#define GCLK_STATUS_RESETVALUE      0x00ul       /**< \brief (GCLK_STATUS reset_value) Status */
 
 #define GCLK_STATUS_SYNCBUSY_Pos    7            /**< \brief (GCLK_STATUS) Synchronization Busy Status */
-#define GCLK_STATUS_SYNCBUSY        (_U(0x1) << GCLK_STATUS_SYNCBUSY_Pos)
-#define GCLK_STATUS_MASK            _U(0x80)     /**< \brief (GCLK_STATUS) MASK Register */
+#define GCLK_STATUS_SYNCBUSY        (0x1ul << GCLK_STATUS_SYNCBUSY_Pos)
+#define GCLK_STATUS_MASK            0x80ul       /**< \brief (GCLK_STATUS) MASK Register */
 
 /* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,48 +105,48 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define GCLK_CLKCTRL_OFFSET         0x2          /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
-#define GCLK_CLKCTRL_RESETVALUE     _U(0x0000)   /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
+#define GCLK_CLKCTRL_RESETVALUE     0x0000ul     /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
 
 #define GCLK_CLKCTRL_ID_Pos         0            /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
-#define GCLK_CLKCTRL_ID_Msk         (_U(0x3F) << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_Msk         (0x3Ful << GCLK_CLKCTRL_ID_Pos)
 #define GCLK_CLKCTRL_ID(value)      (GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))
-#define   GCLK_CLKCTRL_ID_DFLL48_Val      _U(0x0)   /**< \brief (GCLK_CLKCTRL) DFLL48 */
-#define   GCLK_CLKCTRL_ID_FDPLL_Val       _U(0x1)   /**< \brief (GCLK_CLKCTRL) FDPLL */
-#define   GCLK_CLKCTRL_ID_FDPLL32K_Val    _U(0x2)   /**< \brief (GCLK_CLKCTRL) FDPLL32K */
-#define   GCLK_CLKCTRL_ID_WDT_Val         _U(0x3)   /**< \brief (GCLK_CLKCTRL) WDT */
-#define   GCLK_CLKCTRL_ID_RTC_Val         _U(0x4)   /**< \brief (GCLK_CLKCTRL) RTC */
-#define   GCLK_CLKCTRL_ID_EIC_Val         _U(0x5)   /**< \brief (GCLK_CLKCTRL) EIC */
-#define   GCLK_CLKCTRL_ID_USB_Val         _U(0x6)   /**< \brief (GCLK_CLKCTRL) USB */
-#define   GCLK_CLKCTRL_ID_EVSYS_0_Val     _U(0x7)   /**< \brief (GCLK_CLKCTRL) EVSYS_0 */
-#define   GCLK_CLKCTRL_ID_EVSYS_1_Val     _U(0x8)   /**< \brief (GCLK_CLKCTRL) EVSYS_1 */
-#define   GCLK_CLKCTRL_ID_EVSYS_2_Val     _U(0x9)   /**< \brief (GCLK_CLKCTRL) EVSYS_2 */
-#define   GCLK_CLKCTRL_ID_EVSYS_3_Val     _U(0xA)   /**< \brief (GCLK_CLKCTRL) EVSYS_3 */
-#define   GCLK_CLKCTRL_ID_EVSYS_4_Val     _U(0xB)   /**< \brief (GCLK_CLKCTRL) EVSYS_4 */
-#define   GCLK_CLKCTRL_ID_EVSYS_5_Val     _U(0xC)   /**< \brief (GCLK_CLKCTRL) EVSYS_5 */
-#define   GCLK_CLKCTRL_ID_EVSYS_6_Val     _U(0xD)   /**< \brief (GCLK_CLKCTRL) EVSYS_6 */
-#define   GCLK_CLKCTRL_ID_EVSYS_7_Val     _U(0xE)   /**< \brief (GCLK_CLKCTRL) EVSYS_7 */
-#define   GCLK_CLKCTRL_ID_EVSYS_8_Val     _U(0xF)   /**< \brief (GCLK_CLKCTRL) EVSYS_8 */
-#define   GCLK_CLKCTRL_ID_EVSYS_9_Val     _U(0x10)   /**< \brief (GCLK_CLKCTRL) EVSYS_9 */
-#define   GCLK_CLKCTRL_ID_EVSYS_10_Val    _U(0x11)   /**< \brief (GCLK_CLKCTRL) EVSYS_10 */
-#define   GCLK_CLKCTRL_ID_EVSYS_11_Val    _U(0x12)   /**< \brief (GCLK_CLKCTRL) EVSYS_11 */
-#define   GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val _U(0x13)   /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */
-#define   GCLK_CLKCTRL_ID_SERCOM0_CORE_Val _U(0x14)   /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
-#define   GCLK_CLKCTRL_ID_SERCOM1_CORE_Val _U(0x15)   /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
-#define   GCLK_CLKCTRL_ID_SERCOM2_CORE_Val _U(0x16)   /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
-#define   GCLK_CLKCTRL_ID_SERCOM3_CORE_Val _U(0x17)   /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */
-#define   GCLK_CLKCTRL_ID_SERCOM4_CORE_Val _U(0x18)   /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */
-#define   GCLK_CLKCTRL_ID_SERCOM5_CORE_Val _U(0x19)   /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */
-#define   GCLK_CLKCTRL_ID_TCC0_TCC1_Val   _U(0x1A)   /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */
-#define   GCLK_CLKCTRL_ID_TCC2_TC3_Val    _U(0x1B)   /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */
-#define   GCLK_CLKCTRL_ID_TC4_TC5_Val     _U(0x1C)   /**< \brief (GCLK_CLKCTRL) TC4_TC5 */
-#define   GCLK_CLKCTRL_ID_TC6_TC7_Val     _U(0x1D)   /**< \brief (GCLK_CLKCTRL) TC6_TC7 */
-#define   GCLK_CLKCTRL_ID_ADC_Val         _U(0x1E)   /**< \brief (GCLK_CLKCTRL) ADC */
-#define   GCLK_CLKCTRL_ID_AC_DIG_Val      _U(0x1F)   /**< \brief (GCLK_CLKCTRL) AC_DIG */
-#define   GCLK_CLKCTRL_ID_AC_ANA_Val      _U(0x20)   /**< \brief (GCLK_CLKCTRL) AC_ANA */
-#define   GCLK_CLKCTRL_ID_DAC_Val         _U(0x21)   /**< \brief (GCLK_CLKCTRL) DAC */
-#define   GCLK_CLKCTRL_ID_PTC_Val         _U(0x22)   /**< \brief (GCLK_CLKCTRL) PTC */
-#define   GCLK_CLKCTRL_ID_I2S_0_Val       _U(0x23)   /**< \brief (GCLK_CLKCTRL) I2S_0 */
-#define   GCLK_CLKCTRL_ID_I2S_1_Val       _U(0x24)   /**< \brief (GCLK_CLKCTRL) I2S_1 */
+#define   GCLK_CLKCTRL_ID_DFLL48_Val      0x0ul  /**< \brief (GCLK_CLKCTRL) DFLL48 */
+#define   GCLK_CLKCTRL_ID_FDPLL_Val       0x1ul  /**< \brief (GCLK_CLKCTRL) FDPLL */
+#define   GCLK_CLKCTRL_ID_FDPLL32K_Val    0x2ul  /**< \brief (GCLK_CLKCTRL) FDPLL32K */
+#define   GCLK_CLKCTRL_ID_WDT_Val         0x3ul  /**< \brief (GCLK_CLKCTRL) WDT */
+#define   GCLK_CLKCTRL_ID_RTC_Val         0x4ul  /**< \brief (GCLK_CLKCTRL) RTC */
+#define   GCLK_CLKCTRL_ID_EIC_Val         0x5ul  /**< \brief (GCLK_CLKCTRL) EIC */
+#define   GCLK_CLKCTRL_ID_USB_Val         0x6ul  /**< \brief (GCLK_CLKCTRL) USB */
+#define   GCLK_CLKCTRL_ID_EVSYS_0_Val     0x7ul  /**< \brief (GCLK_CLKCTRL) EVSYS_0 */
+#define   GCLK_CLKCTRL_ID_EVSYS_1_Val     0x8ul  /**< \brief (GCLK_CLKCTRL) EVSYS_1 */
+#define   GCLK_CLKCTRL_ID_EVSYS_2_Val     0x9ul  /**< \brief (GCLK_CLKCTRL) EVSYS_2 */
+#define   GCLK_CLKCTRL_ID_EVSYS_3_Val     0xAul  /**< \brief (GCLK_CLKCTRL) EVSYS_3 */
+#define   GCLK_CLKCTRL_ID_EVSYS_4_Val     0xBul  /**< \brief (GCLK_CLKCTRL) EVSYS_4 */
+#define   GCLK_CLKCTRL_ID_EVSYS_5_Val     0xCul  /**< \brief (GCLK_CLKCTRL) EVSYS_5 */
+#define   GCLK_CLKCTRL_ID_EVSYS_6_Val     0xDul  /**< \brief (GCLK_CLKCTRL) EVSYS_6 */
+#define   GCLK_CLKCTRL_ID_EVSYS_7_Val     0xEul  /**< \brief (GCLK_CLKCTRL) EVSYS_7 */
+#define   GCLK_CLKCTRL_ID_EVSYS_8_Val     0xFul  /**< \brief (GCLK_CLKCTRL) EVSYS_8 */
+#define   GCLK_CLKCTRL_ID_EVSYS_9_Val     0x10ul  /**< \brief (GCLK_CLKCTRL) EVSYS_9 */
+#define   GCLK_CLKCTRL_ID_EVSYS_10_Val    0x11ul  /**< \brief (GCLK_CLKCTRL) EVSYS_10 */
+#define   GCLK_CLKCTRL_ID_EVSYS_11_Val    0x12ul  /**< \brief (GCLK_CLKCTRL) EVSYS_11 */
+#define   GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0x13ul  /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */
+#define   GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0x14ul  /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0x15ul  /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0x16ul  /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM3_CORE_Val 0x17ul  /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM4_CORE_Val 0x18ul  /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */
+#define   GCLK_CLKCTRL_ID_SERCOM5_CORE_Val 0x19ul  /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */
+#define   GCLK_CLKCTRL_ID_TCC0_TCC1_Val   0x1Aul  /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */
+#define   GCLK_CLKCTRL_ID_TCC2_TC3_Val    0x1Bul  /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */
+#define   GCLK_CLKCTRL_ID_TC4_TC5_Val     0x1Cul  /**< \brief (GCLK_CLKCTRL) TC4_TC5 */
+#define   GCLK_CLKCTRL_ID_TC6_TC7_Val     0x1Dul  /**< \brief (GCLK_CLKCTRL) TC6_TC7 */
+#define   GCLK_CLKCTRL_ID_ADC_Val         0x1Eul  /**< \brief (GCLK_CLKCTRL) ADC */
+#define   GCLK_CLKCTRL_ID_AC_DIG_Val      0x1Ful  /**< \brief (GCLK_CLKCTRL) AC_DIG */
+#define   GCLK_CLKCTRL_ID_AC_ANA_Val      0x20ul  /**< \brief (GCLK_CLKCTRL) AC_ANA */
+#define   GCLK_CLKCTRL_ID_DAC_Val         0x21ul  /**< \brief (GCLK_CLKCTRL) DAC */
+#define   GCLK_CLKCTRL_ID_PTC_Val         0x22ul  /**< \brief (GCLK_CLKCTRL) PTC */
+#define   GCLK_CLKCTRL_ID_I2S_0_Val       0x23ul  /**< \brief (GCLK_CLKCTRL) I2S_0 */
+#define   GCLK_CLKCTRL_ID_I2S_1_Val       0x24ul  /**< \brief (GCLK_CLKCTRL) I2S_1 */
 #define GCLK_CLKCTRL_ID_DFLL48      (GCLK_CLKCTRL_ID_DFLL48_Val    << GCLK_CLKCTRL_ID_Pos)
 #define GCLK_CLKCTRL_ID_FDPLL       (GCLK_CLKCTRL_ID_FDPLL_Val     << GCLK_CLKCTRL_ID_Pos)
 #define GCLK_CLKCTRL_ID_FDPLL32K    (GCLK_CLKCTRL_ID_FDPLL32K_Val  << GCLK_CLKCTRL_ID_Pos)
@@ -170,16 +185,16 @@ typedef union {
 #define GCLK_CLKCTRL_ID_I2S_0       (GCLK_CLKCTRL_ID_I2S_0_Val     << GCLK_CLKCTRL_ID_Pos)
 #define GCLK_CLKCTRL_ID_I2S_1       (GCLK_CLKCTRL_ID_I2S_1_Val     << GCLK_CLKCTRL_ID_Pos)
 #define GCLK_CLKCTRL_GEN_Pos        8            /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
-#define GCLK_CLKCTRL_GEN_Msk        (_U(0xF) << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_Msk        (0xFul << GCLK_CLKCTRL_GEN_Pos)
 #define GCLK_CLKCTRL_GEN(value)     (GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))
-#define   GCLK_CLKCTRL_GEN_GCLK0_Val      _U(0x0)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
-#define   GCLK_CLKCTRL_GEN_GCLK1_Val      _U(0x1)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
-#define   GCLK_CLKCTRL_GEN_GCLK2_Val      _U(0x2)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
-#define   GCLK_CLKCTRL_GEN_GCLK3_Val      _U(0x3)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
-#define   GCLK_CLKCTRL_GEN_GCLK4_Val      _U(0x4)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
-#define   GCLK_CLKCTRL_GEN_GCLK5_Val      _U(0x5)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
-#define   GCLK_CLKCTRL_GEN_GCLK6_Val      _U(0x6)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
-#define   GCLK_CLKCTRL_GEN_GCLK7_Val      _U(0x7)   /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
+#define   GCLK_CLKCTRL_GEN_GCLK0_Val      0x0ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
+#define   GCLK_CLKCTRL_GEN_GCLK1_Val      0x1ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
+#define   GCLK_CLKCTRL_GEN_GCLK2_Val      0x2ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
+#define   GCLK_CLKCTRL_GEN_GCLK3_Val      0x3ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
+#define   GCLK_CLKCTRL_GEN_GCLK4_Val      0x4ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
+#define   GCLK_CLKCTRL_GEN_GCLK5_Val      0x5ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
+#define   GCLK_CLKCTRL_GEN_GCLK6_Val      0x6ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
+#define   GCLK_CLKCTRL_GEN_GCLK7_Val      0x7ul  /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
 #define GCLK_CLKCTRL_GEN_GCLK0      (GCLK_CLKCTRL_GEN_GCLK0_Val    << GCLK_CLKCTRL_GEN_Pos)
 #define GCLK_CLKCTRL_GEN_GCLK1      (GCLK_CLKCTRL_GEN_GCLK1_Val    << GCLK_CLKCTRL_GEN_Pos)
 #define GCLK_CLKCTRL_GEN_GCLK2      (GCLK_CLKCTRL_GEN_GCLK2_Val    << GCLK_CLKCTRL_GEN_Pos)
@@ -189,10 +204,10 @@ typedef union {
 #define GCLK_CLKCTRL_GEN_GCLK6      (GCLK_CLKCTRL_GEN_GCLK6_Val    << GCLK_CLKCTRL_GEN_Pos)
 #define GCLK_CLKCTRL_GEN_GCLK7      (GCLK_CLKCTRL_GEN_GCLK7_Val    << GCLK_CLKCTRL_GEN_Pos)
 #define GCLK_CLKCTRL_CLKEN_Pos      14           /**< \brief (GCLK_CLKCTRL) Clock Enable */
-#define GCLK_CLKCTRL_CLKEN          (_U(0x1) << GCLK_CLKCTRL_CLKEN_Pos)
+#define GCLK_CLKCTRL_CLKEN          (0x1ul << GCLK_CLKCTRL_CLKEN_Pos)
 #define GCLK_CLKCTRL_WRTLOCK_Pos    15           /**< \brief (GCLK_CLKCTRL) Write Lock */
-#define GCLK_CLKCTRL_WRTLOCK        (_U(0x1) << GCLK_CLKCTRL_WRTLOCK_Pos)
-#define GCLK_CLKCTRL_MASK           _U(0xCF3F)   /**< \brief (GCLK_CLKCTRL) MASK Register */
+#define GCLK_CLKCTRL_WRTLOCK        (0x1ul << GCLK_CLKCTRL_WRTLOCK_Pos)
+#define GCLK_CLKCTRL_MASK           0xCF3Ful     /**< \brief (GCLK_CLKCTRL) MASK Register */
 
 /* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -215,23 +230,23 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define GCLK_GENCTRL_OFFSET         0x4          /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
-#define GCLK_GENCTRL_RESETVALUE     _U(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
+#define GCLK_GENCTRL_RESETVALUE     0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
 
 #define GCLK_GENCTRL_ID_Pos         0            /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
-#define GCLK_GENCTRL_ID_Msk         (_U(0xF) << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID_Msk         (0xFul << GCLK_GENCTRL_ID_Pos)
 #define GCLK_GENCTRL_ID(value)      (GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))
 #define GCLK_GENCTRL_SRC_Pos        8            /**< \brief (GCLK_GENCTRL) Source Select */
-#define GCLK_GENCTRL_SRC_Msk        (_U(0x1F) << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_Msk        (0x1Ful << GCLK_GENCTRL_SRC_Pos)
 #define GCLK_GENCTRL_SRC(value)     (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
-#define   GCLK_GENCTRL_SRC_XOSC_Val       _U(0x0)   /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
-#define   GCLK_GENCTRL_SRC_GCLKIN_Val     _U(0x1)   /**< \brief (GCLK_GENCTRL) Generator input pad */
-#define   GCLK_GENCTRL_SRC_GCLKGEN1_Val   _U(0x2)   /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
-#define   GCLK_GENCTRL_SRC_OSCULP32K_Val  _U(0x3)   /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
-#define   GCLK_GENCTRL_SRC_OSC32K_Val     _U(0x4)   /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
-#define   GCLK_GENCTRL_SRC_XOSC32K_Val    _U(0x5)   /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
-#define   GCLK_GENCTRL_SRC_OSC8M_Val      _U(0x6)   /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
-#define   GCLK_GENCTRL_SRC_DFLL48M_Val    _U(0x7)   /**< \brief (GCLK_GENCTRL) DFLL48M output */
-#define   GCLK_GENCTRL_SRC_FDPLL_Val      _U(0x8)   /**< \brief (GCLK_GENCTRL) FDPLL output */
+#define   GCLK_GENCTRL_SRC_XOSC_Val       0x0ul  /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
+#define   GCLK_GENCTRL_SRC_GCLKIN_Val     0x1ul  /**< \brief (GCLK_GENCTRL) Generator input pad */
+#define   GCLK_GENCTRL_SRC_GCLKGEN1_Val   0x2ul  /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
+#define   GCLK_GENCTRL_SRC_OSCULP32K_Val  0x3ul  /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
+#define   GCLK_GENCTRL_SRC_OSC32K_Val     0x4ul  /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
+#define   GCLK_GENCTRL_SRC_XOSC32K_Val    0x5ul  /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
+#define   GCLK_GENCTRL_SRC_OSC8M_Val      0x6ul  /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
+#define   GCLK_GENCTRL_SRC_DFLL48M_Val    0x7ul  /**< \brief (GCLK_GENCTRL) DFLL48M output */
+#define   GCLK_GENCTRL_SRC_FDPLL_Val      0x8ul  /**< \brief (GCLK_GENCTRL) FDPLL output */
 #define GCLK_GENCTRL_SRC_XOSC       (GCLK_GENCTRL_SRC_XOSC_Val     << GCLK_GENCTRL_SRC_Pos)
 #define GCLK_GENCTRL_SRC_GCLKIN     (GCLK_GENCTRL_SRC_GCLKIN_Val   << GCLK_GENCTRL_SRC_Pos)
 #define GCLK_GENCTRL_SRC_GCLKGEN1   (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
@@ -242,18 +257,18 @@ typedef union {
 #define GCLK_GENCTRL_SRC_DFLL48M    (GCLK_GENCTRL_SRC_DFLL48M_Val  << GCLK_GENCTRL_SRC_Pos)
 #define GCLK_GENCTRL_SRC_FDPLL      (GCLK_GENCTRL_SRC_FDPLL_Val    << GCLK_GENCTRL_SRC_Pos)
 #define GCLK_GENCTRL_GENEN_Pos      16           /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
-#define GCLK_GENCTRL_GENEN          (_U(0x1) << GCLK_GENCTRL_GENEN_Pos)
+#define GCLK_GENCTRL_GENEN          (0x1ul << GCLK_GENCTRL_GENEN_Pos)
 #define GCLK_GENCTRL_IDC_Pos        17           /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
-#define GCLK_GENCTRL_IDC            (_U(0x1) << GCLK_GENCTRL_IDC_Pos)
+#define GCLK_GENCTRL_IDC            (0x1ul << GCLK_GENCTRL_IDC_Pos)
 #define GCLK_GENCTRL_OOV_Pos        18           /**< \brief (GCLK_GENCTRL) Output Off Value */
-#define GCLK_GENCTRL_OOV            (_U(0x1) << GCLK_GENCTRL_OOV_Pos)
+#define GCLK_GENCTRL_OOV            (0x1ul << GCLK_GENCTRL_OOV_Pos)
 #define GCLK_GENCTRL_OE_Pos         19           /**< \brief (GCLK_GENCTRL) Output Enable */
-#define GCLK_GENCTRL_OE             (_U(0x1) << GCLK_GENCTRL_OE_Pos)
+#define GCLK_GENCTRL_OE             (0x1ul << GCLK_GENCTRL_OE_Pos)
 #define GCLK_GENCTRL_DIVSEL_Pos     20           /**< \brief (GCLK_GENCTRL) Divide Selection */
-#define GCLK_GENCTRL_DIVSEL         (_U(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
+#define GCLK_GENCTRL_DIVSEL         (0x1ul << GCLK_GENCTRL_DIVSEL_Pos)
 #define GCLK_GENCTRL_RUNSTDBY_Pos   21           /**< \brief (GCLK_GENCTRL) Run in Standby */
-#define GCLK_GENCTRL_RUNSTDBY       (_U(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
-#define GCLK_GENCTRL_MASK           _U(0x003F1F0F) /**< \brief (GCLK_GENCTRL) MASK Register */
+#define GCLK_GENCTRL_RUNSTDBY       (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos)
+#define GCLK_GENCTRL_MASK           0x003F1F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */
 
 /* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -269,15 +284,15 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define GCLK_GENDIV_OFFSET          0x8          /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
-#define GCLK_GENDIV_RESETVALUE      _U(0x00000000) /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
+#define GCLK_GENDIV_RESETVALUE      0x00000000ul /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
 
 #define GCLK_GENDIV_ID_Pos          0            /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
-#define GCLK_GENDIV_ID_Msk          (_U(0xF) << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID_Msk          (0xFul << GCLK_GENDIV_ID_Pos)
 #define GCLK_GENDIV_ID(value)       (GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))
 #define GCLK_GENDIV_DIV_Pos         8            /**< \brief (GCLK_GENDIV) Division Factor */
-#define GCLK_GENDIV_DIV_Msk         (_U(0xFFFF) << GCLK_GENDIV_DIV_Pos)
+#define GCLK_GENDIV_DIV_Msk         (0xFFFFul << GCLK_GENDIV_DIV_Pos)
 #define GCLK_GENDIV_DIV(value)      (GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))
-#define GCLK_GENDIV_MASK            _U(0x00FFFF0F) /**< \brief (GCLK_GENDIV) MASK Register */
+#define GCLK_GENDIV_MASK            0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */
 
 /** \brief GCLK hardware registers */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

asf/sam0/utils/cmsis/samd21/include/component/hmatrixb.h

@@ -3,24 +3,39 @@
  *
  * \brief Component description for HMATRIXB
  *
- * Copyright (c) 2016 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *
  * \asf_license_stop
  *
@@ -46,9 +61,9 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define HMATRIXB_PRAS_OFFSET        0x080        /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
-#define HMATRIXB_PRAS_RESETVALUE    _U(0x00000000) /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
+#define HMATRIXB_PRAS_RESETVALUE    0x00000000ul /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
 
-#define HMATRIXB_PRAS_MASK          _U(0x00000000) /**< \brief (HMATRIXB_PRAS) MASK Register */
+#define HMATRIXB_PRAS_MASK          0x00000000ul /**< \brief (HMATRIXB_PRAS) MASK Register */
 
 /* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -58,9 +73,9 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define HMATRIXB_PRBS_OFFSET        0x084        /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
-#define HMATRIXB_PRBS_RESETVALUE    _U(0x00000000) /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
+#define HMATRIXB_PRBS_RESETVALUE    0x00000000ul /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
 
-#define HMATRIXB_PRBS_MASK          _U(0x00000000) /**< \brief (HMATRIXB_PRBS) MASK Register */
+#define HMATRIXB_PRBS_MASK          0x00000000ul /**< \brief (HMATRIXB_PRBS) MASK Register */
 
 /* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -73,12 +88,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define HMATRIXB_SFR_OFFSET         0x110        /**< \brief (HMATRIXB_SFR offset) Special Function */
-#define HMATRIXB_SFR_RESETVALUE     _U(0x00000000) /**< \brief (HMATRIXB_SFR reset_value) Special Function */
+#define HMATRIXB_SFR_RESETVALUE     0x00000000ul /**< \brief (HMATRIXB_SFR reset_value) Special Function */
 
 #define HMATRIXB_SFR_SFR_Pos        0            /**< \brief (HMATRIXB_SFR) Special Function Register */
-#define HMATRIXB_SFR_SFR_Msk        (_U(0xFFFFFFFF) << HMATRIXB_SFR_SFR_Pos)
+#define HMATRIXB_SFR_SFR_Msk        (0xFFFFFFFFul << HMATRIXB_SFR_SFR_Pos)
 #define HMATRIXB_SFR_SFR(value)     (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos))
-#define HMATRIXB_SFR_MASK           _U(0xFFFFFFFF) /**< \brief (HMATRIXB_SFR) MASK Register */
+#define HMATRIXB_SFR_MASK           0xFFFFFFFFul /**< \brief (HMATRIXB_SFR) MASK Register */
 
 /** \brief HmatrixbPrs hardware registers */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

asf/sam0/utils/cmsis/samd21/include/component/i2s.h

@@ -3,24 +3,39 @@
  *
  * \brief Component description for I2S
  *
- * Copyright (c) 2016 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *
  * \asf_license_stop
  *
@@ -61,27 +76,27 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define I2S_CTRLA_OFFSET            0x00         /**< \brief (I2S_CTRLA offset) Control A */
-#define I2S_CTRLA_RESETVALUE        _U(0x00)     /**< \brief (I2S_CTRLA reset_value) Control A */
+#define I2S_CTRLA_RESETVALUE        0x00ul       /**< \brief (I2S_CTRLA reset_value) Control A */
 
 #define I2S_CTRLA_SWRST_Pos         0            /**< \brief (I2S_CTRLA) Software Reset */
-#define I2S_CTRLA_SWRST             (_U(0x1) << I2S_CTRLA_SWRST_Pos)
+#define I2S_CTRLA_SWRST             (0x1ul << I2S_CTRLA_SWRST_Pos)
 #define I2S_CTRLA_ENABLE_Pos        1            /**< \brief (I2S_CTRLA) Enable */
-#define I2S_CTRLA_ENABLE            (_U(0x1) << I2S_CTRLA_ENABLE_Pos)
+#define I2S_CTRLA_ENABLE            (0x1ul << I2S_CTRLA_ENABLE_Pos)
 #define I2S_CTRLA_CKEN0_Pos         2            /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
 #define I2S_CTRLA_CKEN0             (1 << I2S_CTRLA_CKEN0_Pos)
 #define I2S_CTRLA_CKEN1_Pos         3            /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
 #define I2S_CTRLA_CKEN1             (1 << I2S_CTRLA_CKEN1_Pos)
 #define I2S_CTRLA_CKEN_Pos          2            /**< \brief (I2S_CTRLA) Clock Unit x Enable */
-#define I2S_CTRLA_CKEN_Msk          (_U(0x3) << I2S_CTRLA_CKEN_Pos)
+#define I2S_CTRLA_CKEN_Msk          (0x3ul << I2S_CTRLA_CKEN_Pos)
 #define I2S_CTRLA_CKEN(value)       (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
 #define I2S_CTRLA_SEREN0_Pos        4            /**< \brief (I2S_CTRLA) Serializer 0 Enable */
 #define I2S_CTRLA_SEREN0            (1 << I2S_CTRLA_SEREN0_Pos)
 #define I2S_CTRLA_SEREN1_Pos        5            /**< \brief (I2S_CTRLA) Serializer 1 Enable */
 #define I2S_CTRLA_SEREN1            (1 << I2S_CTRLA_SEREN1_Pos)
 #define I2S_CTRLA_SEREN_Pos         4            /**< \brief (I2S_CTRLA) Serializer x Enable */
-#define I2S_CTRLA_SEREN_Msk         (_U(0x3) << I2S_CTRLA_SEREN_Pos)
+#define I2S_CTRLA_SEREN_Msk         (0x3ul << I2S_CTRLA_SEREN_Pos)
 #define I2S_CTRLA_SEREN(value)      (I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos))
-#define I2S_CTRLA_MASK              _U(0x3F)     /**< \brief (I2S_CTRLA) MASK Register */
+#define I2S_CTRLA_MASK              0x3Ful       /**< \brief (I2S_CTRLA) MASK Register */
 
 /* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -110,74 +125,74 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define I2S_CLKCTRL_OFFSET          0x04         /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
-#define I2S_CLKCTRL_RESETVALUE      _U(0x00000000) /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
+#define I2S_CLKCTRL_RESETVALUE      0x00000000ul /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
 
 #define I2S_CLKCTRL_SLOTSIZE_Pos    0            /**< \brief (I2S_CLKCTRL) Slot Size */
-#define I2S_CLKCTRL_SLOTSIZE_Msk    (_U(0x3) << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_Msk    (0x3ul << I2S_CLKCTRL_SLOTSIZE_Pos)
 #define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
-#define   I2S_CLKCTRL_SLOTSIZE_8_Val      _U(0x0)   /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
-#define   I2S_CLKCTRL_SLOTSIZE_16_Val     _U(0x1)   /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
-#define   I2S_CLKCTRL_SLOTSIZE_24_Val     _U(0x2)   /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
-#define   I2S_CLKCTRL_SLOTSIZE_32_Val     _U(0x3)   /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_8_Val      0x0ul  /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_16_Val     0x1ul  /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_24_Val     0x2ul  /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_32_Val     0x3ul  /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
 #define I2S_CLKCTRL_SLOTSIZE_8      (I2S_CLKCTRL_SLOTSIZE_8_Val    << I2S_CLKCTRL_SLOTSIZE_Pos)
 #define I2S_CLKCTRL_SLOTSIZE_16     (I2S_CLKCTRL_SLOTSIZE_16_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
 #define I2S_CLKCTRL_SLOTSIZE_24     (I2S_CLKCTRL_SLOTSIZE_24_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
 #define I2S_CLKCTRL_SLOTSIZE_32     (I2S_CLKCTRL_SLOTSIZE_32_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
 #define I2S_CLKCTRL_NBSLOTS_Pos     2            /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
-#define I2S_CLKCTRL_NBSLOTS_Msk     (_U(0x7) << I2S_CLKCTRL_NBSLOTS_Pos)
+#define I2S_CLKCTRL_NBSLOTS_Msk     (0x7ul << I2S_CLKCTRL_NBSLOTS_Pos)
 #define I2S_CLKCTRL_NBSLOTS(value)  (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
 #define I2S_CLKCTRL_FSWIDTH_Pos     5            /**< \brief (I2S_CLKCTRL) Frame Sync Width */
-#define I2S_CLKCTRL_FSWIDTH_Msk     (_U(0x3) << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_Msk     (0x3ul << I2S_CLKCTRL_FSWIDTH_Pos)
 #define I2S_CLKCTRL_FSWIDTH(value)  (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
-#define   I2S_CLKCTRL_FSWIDTH_SLOT_Val    _U(0x0)   /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
-#define   I2S_CLKCTRL_FSWIDTH_HALF_Val    _U(0x1)   /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
-#define   I2S_CLKCTRL_FSWIDTH_BIT_Val     _U(0x2)   /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
-#define   I2S_CLKCTRL_FSWIDTH_BURST_Val   _U(0x3)   /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
+#define   I2S_CLKCTRL_FSWIDTH_SLOT_Val    0x0ul  /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
+#define   I2S_CLKCTRL_FSWIDTH_HALF_Val    0x1ul  /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
+#define   I2S_CLKCTRL_FSWIDTH_BIT_Val     0x2ul  /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
+#define   I2S_CLKCTRL_FSWIDTH_BURST_Val   0x3ul  /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
 #define I2S_CLKCTRL_FSWIDTH_SLOT    (I2S_CLKCTRL_FSWIDTH_SLOT_Val  << I2S_CLKCTRL_FSWIDTH_Pos)
 #define I2S_CLKCTRL_FSWIDTH_HALF    (I2S_CLKCTRL_FSWIDTH_HALF_Val  << I2S_CLKCTRL_FSWIDTH_Pos)
 #define I2S_CLKCTRL_FSWIDTH_BIT     (I2S_CLKCTRL_FSWIDTH_BIT_Val   << I2S_CLKCTRL_FSWIDTH_Pos)
 #define I2S_CLKCTRL_FSWIDTH_BURST   (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
 #define I2S_CLKCTRL_BITDELAY_Pos    7            /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
-#define I2S_CLKCTRL_BITDELAY        (_U(0x1) << I2S_CLKCTRL_BITDELAY_Pos)
-#define   I2S_CLKCTRL_BITDELAY_LJ_Val     _U(0x0)   /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
-#define   I2S_CLKCTRL_BITDELAY_I2S_Val    _U(0x1)   /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY        (0x1ul << I2S_CLKCTRL_BITDELAY_Pos)
+#define   I2S_CLKCTRL_BITDELAY_LJ_Val     0x0ul  /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
+#define   I2S_CLKCTRL_BITDELAY_I2S_Val    0x1ul  /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
 #define I2S_CLKCTRL_BITDELAY_LJ     (I2S_CLKCTRL_BITDELAY_LJ_Val   << I2S_CLKCTRL_BITDELAY_Pos)
 #define I2S_CLKCTRL_BITDELAY_I2S    (I2S_CLKCTRL_BITDELAY_I2S_Val  << I2S_CLKCTRL_BITDELAY_Pos)
 #define I2S_CLKCTRL_FSSEL_Pos       8            /**< \brief (I2S_CLKCTRL) Frame Sync Select */
-#define I2S_CLKCTRL_FSSEL           (_U(0x1) << I2S_CLKCTRL_FSSEL_Pos)
-#define   I2S_CLKCTRL_FSSEL_SCKDIV_Val    _U(0x0)   /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
-#define   I2S_CLKCTRL_FSSEL_FSPIN_Val     _U(0x1)   /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL           (0x1ul << I2S_CLKCTRL_FSSEL_Pos)
+#define   I2S_CLKCTRL_FSSEL_SCKDIV_Val    0x0ul  /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
+#define   I2S_CLKCTRL_FSSEL_FSPIN_Val     0x1ul  /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
 #define I2S_CLKCTRL_FSSEL_SCKDIV    (I2S_CLKCTRL_FSSEL_SCKDIV_Val  << I2S_CLKCTRL_FSSEL_Pos)
 #define I2S_CLKCTRL_FSSEL_FSPIN     (I2S_CLKCTRL_FSSEL_FSPIN_Val   << I2S_CLKCTRL_FSSEL_Pos)
 #define I2S_CLKCTRL_FSINV_Pos       11           /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
-#define I2S_CLKCTRL_FSINV           (_U(0x1) << I2S_CLKCTRL_FSINV_Pos)
+#define I2S_CLKCTRL_FSINV           (0x1ul << I2S_CLKCTRL_FSINV_Pos)
 #define I2S_CLKCTRL_SCKSEL_Pos      12           /**< \brief (I2S_CLKCTRL) Serial Clock Select */
-#define I2S_CLKCTRL_SCKSEL          (_U(0x1) << I2S_CLKCTRL_SCKSEL_Pos)
-#define   I2S_CLKCTRL_SCKSEL_MCKDIV_Val   _U(0x0)   /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
-#define   I2S_CLKCTRL_SCKSEL_SCKPIN_Val   _U(0x1)   /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL          (0x1ul << I2S_CLKCTRL_SCKSEL_Pos)
+#define   I2S_CLKCTRL_SCKSEL_MCKDIV_Val   0x0ul  /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
+#define   I2S_CLKCTRL_SCKSEL_SCKPIN_Val   0x1ul  /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
 #define I2S_CLKCTRL_SCKSEL_MCKDIV   (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
 #define I2S_CLKCTRL_SCKSEL_SCKPIN   (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
 #define I2S_CLKCTRL_MCKSEL_Pos      16           /**< \brief (I2S_CLKCTRL) Master Clock Select */
-#define I2S_CLKCTRL_MCKSEL          (_U(0x1) << I2S_CLKCTRL_MCKSEL_Pos)
-#define   I2S_CLKCTRL_MCKSEL_GCLK_Val     _U(0x0)   /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
-#define   I2S_CLKCTRL_MCKSEL_MCKPIN_Val   _U(0x1)   /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL          (0x1ul << I2S_CLKCTRL_MCKSEL_Pos)
+#define   I2S_CLKCTRL_MCKSEL_GCLK_Val     0x0ul  /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
+#define   I2S_CLKCTRL_MCKSEL_MCKPIN_Val   0x1ul  /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
 #define I2S_CLKCTRL_MCKSEL_GCLK     (I2S_CLKCTRL_MCKSEL_GCLK_Val   << I2S_CLKCTRL_MCKSEL_Pos)
 #define I2S_CLKCTRL_MCKSEL_MCKPIN   (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
 #define I2S_CLKCTRL_MCKEN_Pos       18           /**< \brief (I2S_CLKCTRL) Master Clock Enable */
-#define I2S_CLKCTRL_MCKEN           (_U(0x1) << I2S_CLKCTRL_MCKEN_Pos)
+#define I2S_CLKCTRL_MCKEN           (0x1ul << I2S_CLKCTRL_MCKEN_Pos)
 #define I2S_CLKCTRL_MCKDIV_Pos      19           /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
-#define I2S_CLKCTRL_MCKDIV_Msk      (_U(0x1F) << I2S_CLKCTRL_MCKDIV_Pos)
+#define I2S_CLKCTRL_MCKDIV_Msk      (0x1Ful << I2S_CLKCTRL_MCKDIV_Pos)
 #define I2S_CLKCTRL_MCKDIV(value)   (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
 #define I2S_CLKCTRL_MCKOUTDIV_Pos   24           /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
-#define I2S_CLKCTRL_MCKOUTDIV_Msk   (_U(0x1F) << I2S_CLKCTRL_MCKOUTDIV_Pos)
+#define I2S_CLKCTRL_MCKOUTDIV_Msk   (0x1Ful << I2S_CLKCTRL_MCKOUTDIV_Pos)
 #define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
 #define I2S_CLKCTRL_FSOUTINV_Pos    29           /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
-#define I2S_CLKCTRL_FSOUTINV        (_U(0x1) << I2S_CLKCTRL_FSOUTINV_Pos)
+#define I2S_CLKCTRL_FSOUTINV        (0x1ul << I2S_CLKCTRL_FSOUTINV_Pos)
 #define I2S_CLKCTRL_SCKOUTINV_Pos   30           /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
-#define I2S_CLKCTRL_SCKOUTINV       (_U(0x1) << I2S_CLKCTRL_SCKOUTINV_Pos)
+#define I2S_CLKCTRL_SCKOUTINV       (0x1ul << I2S_CLKCTRL_SCKOUTINV_Pos)
 #define I2S_CLKCTRL_MCKOUTINV_Pos   31           /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
-#define I2S_CLKCTRL_MCKOUTINV       (_U(0x1) << I2S_CLKCTRL_MCKOUTINV_Pos)
-#define I2S_CLKCTRL_MASK            _U(0xFFFD19FF) /**< \brief (I2S_CLKCTRL) MASK Register */
+#define I2S_CLKCTRL_MCKOUTINV       (0x1ul << I2S_CLKCTRL_MCKOUTINV_Pos)
+#define I2S_CLKCTRL_MASK            0xFFFD19FFul /**< \brief (I2S_CLKCTRL) MASK Register */
 
 /* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -211,37 +226,37 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define I2S_INTENCLR_OFFSET         0x0C         /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
-#define I2S_INTENCLR_RESETVALUE     _U(0x0000)   /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
+#define I2S_INTENCLR_RESETVALUE     0x0000ul     /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
 
 #define I2S_INTENCLR_RXRDY0_Pos     0            /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
 #define I2S_INTENCLR_RXRDY0         (1 << I2S_INTENCLR_RXRDY0_Pos)
 #define I2S_INTENCLR_RXRDY1_Pos     1            /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
 #define I2S_INTENCLR_RXRDY1         (1 << I2S_INTENCLR_RXRDY1_Pos)
 #define I2S_INTENCLR_RXRDY_Pos      0            /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
-#define I2S_INTENCLR_RXRDY_Msk      (_U(0x3) << I2S_INTENCLR_RXRDY_Pos)
+#define I2S_INTENCLR_RXRDY_Msk      (0x3ul << I2S_INTENCLR_RXRDY_Pos)
 #define I2S_INTENCLR_RXRDY(value)   (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
 #define I2S_INTENCLR_RXOR0_Pos      4            /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
 #define I2S_INTENCLR_RXOR0          (1 << I2S_INTENCLR_RXOR0_Pos)
 #define I2S_INTENCLR_RXOR1_Pos      5            /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
 #define I2S_INTENCLR_RXOR1          (1 << I2S_INTENCLR_RXOR1_Pos)
 #define I2S_INTENCLR_RXOR_Pos       4            /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
-#define I2S_INTENCLR_RXOR_Msk       (_U(0x3) << I2S_INTENCLR_RXOR_Pos)
+#define I2S_INTENCLR_RXOR_Msk       (0x3ul << I2S_INTENCLR_RXOR_Pos)
 #define I2S_INTENCLR_RXOR(value)    (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
 #define I2S_INTENCLR_TXRDY0_Pos     8            /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
 #define I2S_INTENCLR_TXRDY0         (1 << I2S_INTENCLR_TXRDY0_Pos)
 #define I2S_INTENCLR_TXRDY1_Pos     9            /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
 #define I2S_INTENCLR_TXRDY1         (1 << I2S_INTENCLR_TXRDY1_Pos)
 #define I2S_INTENCLR_TXRDY_Pos      8            /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
-#define I2S_INTENCLR_TXRDY_Msk      (_U(0x3) << I2S_INTENCLR_TXRDY_Pos)
+#define I2S_INTENCLR_TXRDY_Msk      (0x3ul << I2S_INTENCLR_TXRDY_Pos)
 #define I2S_INTENCLR_TXRDY(value)   (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
 #define I2S_INTENCLR_TXUR0_Pos      12           /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
 #define I2S_INTENCLR_TXUR0          (1 << I2S_INTENCLR_TXUR0_Pos)
 #define I2S_INTENCLR_TXUR1_Pos      13           /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
 #define I2S_INTENCLR_TXUR1          (1 << I2S_INTENCLR_TXUR1_Pos)
 #define I2S_INTENCLR_TXUR_Pos       12           /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
-#define I2S_INTENCLR_TXUR_Msk       (_U(0x3) << I2S_INTENCLR_TXUR_Pos)
+#define I2S_INTENCLR_TXUR_Msk       (0x3ul << I2S_INTENCLR_TXUR_Pos)
 #define I2S_INTENCLR_TXUR(value)    (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
-#define I2S_INTENCLR_MASK           _U(0x3333)   /**< \brief (I2S_INTENCLR) MASK Register */
+#define I2S_INTENCLR_MASK           0x3333ul     /**< \brief (I2S_INTENCLR) MASK Register */
 
 /* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -275,37 +290,37 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define I2S_INTENSET_OFFSET         0x10         /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
-#define I2S_INTENSET_RESETVALUE     _U(0x0000)   /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
+#define I2S_INTENSET_RESETVALUE     0x0000ul     /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
 
 #define I2S_INTENSET_RXRDY0_Pos     0            /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
 #define I2S_INTENSET_RXRDY0         (1 << I2S_INTENSET_RXRDY0_Pos)
 #define I2S_INTENSET_RXRDY1_Pos     1            /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
 #define I2S_INTENSET_RXRDY1         (1 << I2S_INTENSET_RXRDY1_Pos)
 #define I2S_INTENSET_RXRDY_Pos      0            /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
-#define I2S_INTENSET_RXRDY_Msk      (_U(0x3) << I2S_INTENSET_RXRDY_Pos)
+#define I2S_INTENSET_RXRDY_Msk      (0x3ul << I2S_INTENSET_RXRDY_Pos)
 #define I2S_INTENSET_RXRDY(value)   (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
 #define I2S_INTENSET_RXOR0_Pos      4            /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
 #define I2S_INTENSET_RXOR0          (1 << I2S_INTENSET_RXOR0_Pos)
 #define I2S_INTENSET_RXOR1_Pos      5            /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
 #define I2S_INTENSET_RXOR1          (1 << I2S_INTENSET_RXOR1_Pos)
 #define I2S_INTENSET_RXOR_Pos       4            /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
-#define I2S_INTENSET_RXOR_Msk       (_U(0x3) << I2S_INTENSET_RXOR_Pos)
+#define I2S_INTENSET_RXOR_Msk       (0x3ul << I2S_INTENSET_RXOR_Pos)
 #define I2S_INTENSET_RXOR(value)    (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
 #define I2S_INTENSET_TXRDY0_Pos     8            /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
 #define I2S_INTENSET_TXRDY0         (1 << I2S_INTENSET_TXRDY0_Pos)
 #define I2S_INTENSET_TXRDY1_Pos     9            /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
 #define I2S_INTENSET_TXRDY1         (1 << I2S_INTENSET_TXRDY1_Pos)
 #define I2S_INTENSET_TXRDY_Pos      8            /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
-#define I2S_INTENSET_TXRDY_Msk      (_U(0x3) << I2S_INTENSET_TXRDY_Pos)
+#define I2S_INTENSET_TXRDY_Msk      (0x3ul << I2S_INTENSET_TXRDY_Pos)
 #define I2S_INTENSET_TXRDY(value)   (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
 #define I2S_INTENSET_TXUR0_Pos      12           /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
 #define I2S_INTENSET_TXUR0          (1 << I2S_INTENSET_TXUR0_Pos)
 #define I2S_INTENSET_TXUR1_Pos      13           /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
 #define I2S_INTENSET_TXUR1          (1 << I2S_INTENSET_TXUR1_Pos)
 #define I2S_INTENSET_TXUR_Pos       12           /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
-#define I2S_INTENSET_TXUR_Msk       (_U(0x3) << I2S_INTENSET_TXUR_Pos)
+#define I2S_INTENSET_TXUR_Msk       (0x3ul << I2S_INTENSET_TXUR_Pos)
 #define I2S_INTENSET_TXUR(value)    (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
-#define I2S_INTENSET_MASK           _U(0x3333)   /**< \brief (I2S_INTENSET) MASK Register */
+#define I2S_INTENSET_MASK           0x3333ul     /**< \brief (I2S_INTENSET) MASK Register */
 
 /* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -339,37 +354,37 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define I2S_INTFLAG_OFFSET          0x14         /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
-#define I2S_INTFLAG_RESETVALUE      _U(0x0000)   /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
+#define I2S_INTFLAG_RESETVALUE      0x0000ul     /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
 
 #define I2S_INTFLAG_RXRDY0_Pos      0            /**< \brief (I2S_INTFLAG) Receive Ready 0 */
 #define I2S_INTFLAG_RXRDY0          (1 << I2S_INTFLAG_RXRDY0_Pos)
 #define I2S_INTFLAG_RXRDY1_Pos      1            /**< \brief (I2S_INTFLAG) Receive Ready 1 */
 #define I2S_INTFLAG_RXRDY1          (1 << I2S_INTFLAG_RXRDY1_Pos)
 #define I2S_INTFLAG_RXRDY_Pos       0            /**< \brief (I2S_INTFLAG) Receive Ready x */
-#define I2S_INTFLAG_RXRDY_Msk       (_U(0x3) << I2S_INTFLAG_RXRDY_Pos)
+#define I2S_INTFLAG_RXRDY_Msk       (0x3ul << I2S_INTFLAG_RXRDY_Pos)
 #define I2S_INTFLAG_RXRDY(value)    (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
 #define I2S_INTFLAG_RXOR0_Pos       4            /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
 #define I2S_INTFLAG_RXOR0           (1 << I2S_INTFLAG_RXOR0_Pos)
 #define I2S_INTFLAG_RXOR1_Pos       5            /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
 #define I2S_INTFLAG_RXOR1           (1 << I2S_INTFLAG_RXOR1_Pos)
 #define I2S_INTFLAG_RXOR_Pos        4            /**< \brief (I2S_INTFLAG) Receive Overrun x */
-#define I2S_INTFLAG_RXOR_Msk        (_U(0x3) << I2S_INTFLAG_RXOR_Pos)
+#define I2S_INTFLAG_RXOR_Msk        (0x3ul << I2S_INTFLAG_RXOR_Pos)
 #define I2S_INTFLAG_RXOR(value)     (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
 #define I2S_INTFLAG_TXRDY0_Pos      8            /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
 #define I2S_INTFLAG_TXRDY0          (1 << I2S_INTFLAG_TXRDY0_Pos)
 #define I2S_INTFLAG_TXRDY1_Pos      9            /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
 #define I2S_INTFLAG_TXRDY1          (1 << I2S_INTFLAG_TXRDY1_Pos)
 #define I2S_INTFLAG_TXRDY_Pos       8            /**< \brief (I2S_INTFLAG) Transmit Ready x */
-#define I2S_INTFLAG_TXRDY_Msk       (_U(0x3) << I2S_INTFLAG_TXRDY_Pos)
+#define I2S_INTFLAG_TXRDY_Msk       (0x3ul << I2S_INTFLAG_TXRDY_Pos)
 #define I2S_INTFLAG_TXRDY(value)    (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
 #define I2S_INTFLAG_TXUR0_Pos       12           /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
 #define I2S_INTFLAG_TXUR0           (1 << I2S_INTFLAG_TXUR0_Pos)
 #define I2S_INTFLAG_TXUR1_Pos       13           /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
 #define I2S_INTFLAG_TXUR1           (1 << I2S_INTFLAG_TXUR1_Pos)
 #define I2S_INTFLAG_TXUR_Pos        12           /**< \brief (I2S_INTFLAG) Transmit Underrun x */
-#define I2S_INTFLAG_TXUR_Msk        (_U(0x3) << I2S_INTFLAG_TXUR_Pos)
+#define I2S_INTFLAG_TXUR_Msk        (0x3ul << I2S_INTFLAG_TXUR_Pos)
 #define I2S_INTFLAG_TXUR(value)     (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
-#define I2S_INTFLAG_MASK            _U(0x3333)   /**< \brief (I2S_INTFLAG) MASK Register */
+#define I2S_INTFLAG_MASK            0x3333ul     /**< \brief (I2S_INTFLAG) MASK Register */
 
 /* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/  16) Synchronization Status -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -399,34 +414,34 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define I2S_SYNCBUSY_OFFSET         0x18         /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
-#define I2S_SYNCBUSY_RESETVALUE     _U(0x0000)   /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
+#define I2S_SYNCBUSY_RESETVALUE     0x0000ul     /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
 
 #define I2S_SYNCBUSY_SWRST_Pos      0            /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
-#define I2S_SYNCBUSY_SWRST          (_U(0x1) << I2S_SYNCBUSY_SWRST_Pos)
+#define I2S_SYNCBUSY_SWRST          (0x1ul << I2S_SYNCBUSY_SWRST_Pos)
 #define I2S_SYNCBUSY_ENABLE_Pos     1            /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
-#define I2S_SYNCBUSY_ENABLE         (_U(0x1) << I2S_SYNCBUSY_ENABLE_Pos)
+#define I2S_SYNCBUSY_ENABLE         (0x1ul << I2S_SYNCBUSY_ENABLE_Pos)
 #define I2S_SYNCBUSY_CKEN0_Pos      2            /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
 #define I2S_SYNCBUSY_CKEN0          (1 << I2S_SYNCBUSY_CKEN0_Pos)
 #define I2S_SYNCBUSY_CKEN1_Pos      3            /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
 #define I2S_SYNCBUSY_CKEN1          (1 << I2S_SYNCBUSY_CKEN1_Pos)
 #define I2S_SYNCBUSY_CKEN_Pos       2            /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
-#define I2S_SYNCBUSY_CKEN_Msk       (_U(0x3) << I2S_SYNCBUSY_CKEN_Pos)
+#define I2S_SYNCBUSY_CKEN_Msk       (0x3ul << I2S_SYNCBUSY_CKEN_Pos)
 #define I2S_SYNCBUSY_CKEN(value)    (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
 #define I2S_SYNCBUSY_SEREN0_Pos     4            /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */
 #define I2S_SYNCBUSY_SEREN0         (1 << I2S_SYNCBUSY_SEREN0_Pos)
 #define I2S_SYNCBUSY_SEREN1_Pos     5            /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */
 #define I2S_SYNCBUSY_SEREN1         (1 << I2S_SYNCBUSY_SEREN1_Pos)
 #define I2S_SYNCBUSY_SEREN_Pos      4            /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */
-#define I2S_SYNCBUSY_SEREN_Msk      (_U(0x3) << I2S_SYNCBUSY_SEREN_Pos)
+#define I2S_SYNCBUSY_SEREN_Msk      (0x3ul << I2S_SYNCBUSY_SEREN_Pos)
 #define I2S_SYNCBUSY_SEREN(value)   (I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos))
 #define I2S_SYNCBUSY_DATA0_Pos      8            /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */
 #define I2S_SYNCBUSY_DATA0          (1 << I2S_SYNCBUSY_DATA0_Pos)
 #define I2S_SYNCBUSY_DATA1_Pos      9            /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */
 #define I2S_SYNCBUSY_DATA1          (1 << I2S_SYNCBUSY_DATA1_Pos)
 #define I2S_SYNCBUSY_DATA_Pos       8            /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */
-#define I2S_SYNCBUSY_DATA_Msk       (_U(0x3) << I2S_SYNCBUSY_DATA_Pos)
+#define I2S_SYNCBUSY_DATA_Msk       (0x3ul << I2S_SYNCBUSY_DATA_Pos)
 #define I2S_SYNCBUSY_DATA(value)    (I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos))
-#define I2S_SYNCBUSY_MASK           _U(0x033F)   /**< \brief (I2S_SYNCBUSY) MASK Register */
+#define I2S_SYNCBUSY_MASK           0x033Ful     /**< \brief (I2S_SYNCBUSY) MASK Register */
 
 /* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -466,55 +481,55 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define I2S_SERCTRL_OFFSET          0x20         /**< \brief (I2S_SERCTRL offset) Serializer n Control */
-#define I2S_SERCTRL_RESETVALUE      _U(0x00000000) /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */
+#define I2S_SERCTRL_RESETVALUE      0x00000000ul /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */
 
 #define I2S_SERCTRL_SERMODE_Pos     0            /**< \brief (I2S_SERCTRL) Serializer Mode */
-#define I2S_SERCTRL_SERMODE_Msk     (_U(0x3) << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE_Msk     (0x3ul << I2S_SERCTRL_SERMODE_Pos)
 #define I2S_SERCTRL_SERMODE(value)  (I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos))
-#define   I2S_SERCTRL_SERMODE_RX_Val      _U(0x0)   /**< \brief (I2S_SERCTRL) Receive */
-#define   I2S_SERCTRL_SERMODE_TX_Val      _U(0x1)   /**< \brief (I2S_SERCTRL) Transmit */
-#define   I2S_SERCTRL_SERMODE_PDM2_Val    _U(0x2)   /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
+#define   I2S_SERCTRL_SERMODE_RX_Val      0x0ul  /**< \brief (I2S_SERCTRL) Receive */
+#define   I2S_SERCTRL_SERMODE_TX_Val      0x1ul  /**< \brief (I2S_SERCTRL) Transmit */
+#define   I2S_SERCTRL_SERMODE_PDM2_Val    0x2ul  /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
 #define I2S_SERCTRL_SERMODE_RX      (I2S_SERCTRL_SERMODE_RX_Val    << I2S_SERCTRL_SERMODE_Pos)
 #define I2S_SERCTRL_SERMODE_TX      (I2S_SERCTRL_SERMODE_TX_Val    << I2S_SERCTRL_SERMODE_Pos)
 #define I2S_SERCTRL_SERMODE_PDM2    (I2S_SERCTRL_SERMODE_PDM2_Val  << I2S_SERCTRL_SERMODE_Pos)
 #define I2S_SERCTRL_TXDEFAULT_Pos   2            /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */
-#define I2S_SERCTRL_TXDEFAULT_Msk   (_U(0x3) << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT_Msk   (0x3ul << I2S_SERCTRL_TXDEFAULT_Pos)
 #define I2S_SERCTRL_TXDEFAULT(value) (I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos))
-#define   I2S_SERCTRL_TXDEFAULT_ZERO_Val  _U(0x0)   /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
-#define   I2S_SERCTRL_TXDEFAULT_ONE_Val   _U(0x1)   /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
-#define   I2S_SERCTRL_TXDEFAULT_HIZ_Val   _U(0x3)   /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
+#define   I2S_SERCTRL_TXDEFAULT_ZERO_Val  0x0ul  /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
+#define   I2S_SERCTRL_TXDEFAULT_ONE_Val   0x1ul  /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
+#define   I2S_SERCTRL_TXDEFAULT_HIZ_Val   0x3ul  /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
 #define I2S_SERCTRL_TXDEFAULT_ZERO  (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos)
 #define I2S_SERCTRL_TXDEFAULT_ONE   (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos)
 #define I2S_SERCTRL_TXDEFAULT_HIZ   (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos)
 #define I2S_SERCTRL_TXSAME_Pos      4            /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */
-#define I2S_SERCTRL_TXSAME          (_U(0x1) << I2S_SERCTRL_TXSAME_Pos)
-#define   I2S_SERCTRL_TXSAME_ZERO_Val     _U(0x0)   /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */
-#define   I2S_SERCTRL_TXSAME_SAME_Val     _U(0x1)   /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */
+#define I2S_SERCTRL_TXSAME          (0x1ul << I2S_SERCTRL_TXSAME_Pos)
+#define   I2S_SERCTRL_TXSAME_ZERO_Val     0x0ul  /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */
+#define   I2S_SERCTRL_TXSAME_SAME_Val     0x1ul  /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */
 #define I2S_SERCTRL_TXSAME_ZERO     (I2S_SERCTRL_TXSAME_ZERO_Val   << I2S_SERCTRL_TXSAME_Pos)
 #define I2S_SERCTRL_TXSAME_SAME     (I2S_SERCTRL_TXSAME_SAME_Val   << I2S_SERCTRL_TXSAME_Pos)
 #define I2S_SERCTRL_CLKSEL_Pos      5            /**< \brief (I2S_SERCTRL) Clock Unit Selection */
-#define I2S_SERCTRL_CLKSEL          (_U(0x1) << I2S_SERCTRL_CLKSEL_Pos)
-#define   I2S_SERCTRL_CLKSEL_CLK0_Val     _U(0x0)   /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */
-#define   I2S_SERCTRL_CLKSEL_CLK1_Val     _U(0x1)   /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */
+#define I2S_SERCTRL_CLKSEL          (0x1ul << I2S_SERCTRL_CLKSEL_Pos)
+#define   I2S_SERCTRL_CLKSEL_CLK0_Val     0x0ul  /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */
+#define   I2S_SERCTRL_CLKSEL_CLK1_Val     0x1ul  /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */
 #define I2S_SERCTRL_CLKSEL_CLK0     (I2S_SERCTRL_CLKSEL_CLK0_Val   << I2S_SERCTRL_CLKSEL_Pos)
 #define I2S_SERCTRL_CLKSEL_CLK1     (I2S_SERCTRL_CLKSEL_CLK1_Val   << I2S_SERCTRL_CLKSEL_Pos)
 #define I2S_SERCTRL_SLOTADJ_Pos     7            /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */
-#define I2S_SERCTRL_SLOTADJ         (_U(0x1) << I2S_SERCTRL_SLOTADJ_Pos)
-#define   I2S_SERCTRL_SLOTADJ_RIGHT_Val   _U(0x0)   /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */
-#define   I2S_SERCTRL_SLOTADJ_LEFT_Val    _U(0x1)   /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */
+#define I2S_SERCTRL_SLOTADJ         (0x1ul << I2S_SERCTRL_SLOTADJ_Pos)
+#define   I2S_SERCTRL_SLOTADJ_RIGHT_Val   0x0ul  /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */
+#define   I2S_SERCTRL_SLOTADJ_LEFT_Val    0x1ul  /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */
 #define I2S_SERCTRL_SLOTADJ_RIGHT   (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos)
 #define I2S_SERCTRL_SLOTADJ_LEFT    (I2S_SERCTRL_SLOTADJ_LEFT_Val  << I2S_SERCTRL_SLOTADJ_Pos)
 #define I2S_SERCTRL_DATASIZE_Pos    8            /**< \brief (I2S_SERCTRL) Data Word Size */
-#define I2S_SERCTRL_DATASIZE_Msk    (_U(0x7) << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_Msk    (0x7ul << I2S_SERCTRL_DATASIZE_Pos)
 #define I2S_SERCTRL_DATASIZE(value) (I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos))
-#define   I2S_SERCTRL_DATASIZE_32_Val     _U(0x0)   /**< \brief (I2S_SERCTRL) 32 bits */
-#define   I2S_SERCTRL_DATASIZE_24_Val     _U(0x1)   /**< \brief (I2S_SERCTRL) 24 bits */
-#define   I2S_SERCTRL_DATASIZE_20_Val     _U(0x2)   /**< \brief (I2S_SERCTRL) 20 bits */
-#define   I2S_SERCTRL_DATASIZE_18_Val     _U(0x3)   /**< \brief (I2S_SERCTRL) 18 bits */
-#define   I2S_SERCTRL_DATASIZE_16_Val     _U(0x4)   /**< \brief (I2S_SERCTRL) 16 bits */
-#define   I2S_SERCTRL_DATASIZE_16C_Val    _U(0x5)   /**< \brief (I2S_SERCTRL) 16 bits compact stereo */
-#define   I2S_SERCTRL_DATASIZE_8_Val      _U(0x6)   /**< \brief (I2S_SERCTRL) 8 bits */
-#define   I2S_SERCTRL_DATASIZE_8C_Val     _U(0x7)   /**< \brief (I2S_SERCTRL) 8 bits compact stereo */
+#define   I2S_SERCTRL_DATASIZE_32_Val     0x0ul  /**< \brief (I2S_SERCTRL) 32 bits */
+#define   I2S_SERCTRL_DATASIZE_24_Val     0x1ul  /**< \brief (I2S_SERCTRL) 24 bits */
+#define   I2S_SERCTRL_DATASIZE_20_Val     0x2ul  /**< \brief (I2S_SERCTRL) 20 bits */
+#define   I2S_SERCTRL_DATASIZE_18_Val     0x3ul  /**< \brief (I2S_SERCTRL) 18 bits */
+#define   I2S_SERCTRL_DATASIZE_16_Val     0x4ul  /**< \brief (I2S_SERCTRL) 16 bits */
+#define   I2S_SERCTRL_DATASIZE_16C_Val    0x5ul  /**< \brief (I2S_SERCTRL) 16 bits compact stereo */
+#define   I2S_SERCTRL_DATASIZE_8_Val      0x6ul  /**< \brief (I2S_SERCTRL) 8 bits */
+#define   I2S_SERCTRL_DATASIZE_8C_Val     0x7ul  /**< \brief (I2S_SERCTRL) 8 bits compact stereo */
 #define I2S_SERCTRL_DATASIZE_32     (I2S_SERCTRL_DATASIZE_32_Val   << I2S_SERCTRL_DATASIZE_Pos)
 #define I2S_SERCTRL_DATASIZE_24     (I2S_SERCTRL_DATASIZE_24_Val   << I2S_SERCTRL_DATASIZE_Pos)
 #define I2S_SERCTRL_DATASIZE_20     (I2S_SERCTRL_DATASIZE_20_Val   << I2S_SERCTRL_DATASIZE_Pos)
@@ -524,26 +539,26 @@ typedef union {
 #define I2S_SERCTRL_DATASIZE_8      (I2S_SERCTRL_DATASIZE_8_Val    << I2S_SERCTRL_DATASIZE_Pos)
 #define I2S_SERCTRL_DATASIZE_8C     (I2S_SERCTRL_DATASIZE_8C_Val   << I2S_SERCTRL_DATASIZE_Pos)
 #define I2S_SERCTRL_WORDADJ_Pos     12           /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */
-#define I2S_SERCTRL_WORDADJ         (_U(0x1) << I2S_SERCTRL_WORDADJ_Pos)
-#define   I2S_SERCTRL_WORDADJ_RIGHT_Val   _U(0x0)   /**< \brief (I2S_SERCTRL) Data is right adjusted in word */
-#define   I2S_SERCTRL_WORDADJ_LEFT_Val    _U(0x1)   /**< \brief (I2S_SERCTRL) Data is left adjusted in word */
+#define I2S_SERCTRL_WORDADJ         (0x1ul << I2S_SERCTRL_WORDADJ_Pos)
+#define   I2S_SERCTRL_WORDADJ_RIGHT_Val   0x0ul  /**< \brief (I2S_SERCTRL) Data is right adjusted in word */
+#define   I2S_SERCTRL_WORDADJ_LEFT_Val    0x1ul  /**< \brief (I2S_SERCTRL) Data is left adjusted in word */
 #define I2S_SERCTRL_WORDADJ_RIGHT   (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos)
 #define I2S_SERCTRL_WORDADJ_LEFT    (I2S_SERCTRL_WORDADJ_LEFT_Val  << I2S_SERCTRL_WORDADJ_Pos)
 #define I2S_SERCTRL_EXTEND_Pos      13           /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */
-#define I2S_SERCTRL_EXTEND_Msk      (_U(0x3) << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_Msk      (0x3ul << I2S_SERCTRL_EXTEND_Pos)
 #define I2S_SERCTRL_EXTEND(value)   (I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos))
-#define   I2S_SERCTRL_EXTEND_ZERO_Val     _U(0x0)   /**< \brief (I2S_SERCTRL) Extend with zeroes */
-#define   I2S_SERCTRL_EXTEND_ONE_Val      _U(0x1)   /**< \brief (I2S_SERCTRL) Extend with ones */
-#define   I2S_SERCTRL_EXTEND_MSBIT_Val    _U(0x2)   /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
-#define   I2S_SERCTRL_EXTEND_LSBIT_Val    _U(0x3)   /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */
+#define   I2S_SERCTRL_EXTEND_ZERO_Val     0x0ul  /**< \brief (I2S_SERCTRL) Extend with zeroes */
+#define   I2S_SERCTRL_EXTEND_ONE_Val      0x1ul  /**< \brief (I2S_SERCTRL) Extend with ones */
+#define   I2S_SERCTRL_EXTEND_MSBIT_Val    0x2ul  /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
+#define   I2S_SERCTRL_EXTEND_LSBIT_Val    0x3ul  /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */
 #define I2S_SERCTRL_EXTEND_ZERO     (I2S_SERCTRL_EXTEND_ZERO_Val   << I2S_SERCTRL_EXTEND_Pos)
 #define I2S_SERCTRL_EXTEND_ONE      (I2S_SERCTRL_EXTEND_ONE_Val    << I2S_SERCTRL_EXTEND_Pos)
 #define I2S_SERCTRL_EXTEND_MSBIT    (I2S_SERCTRL_EXTEND_MSBIT_Val  << I2S_SERCTRL_EXTEND_Pos)
 #define I2S_SERCTRL_EXTEND_LSBIT    (I2S_SERCTRL_EXTEND_LSBIT_Val  << I2S_SERCTRL_EXTEND_Pos)
 #define I2S_SERCTRL_BITREV_Pos      15           /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */
-#define I2S_SERCTRL_BITREV          (_U(0x1) << I2S_SERCTRL_BITREV_Pos)
-#define   I2S_SERCTRL_BITREV_MSBIT_Val    _U(0x0)   /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
-#define   I2S_SERCTRL_BITREV_LSBIT_Val    _U(0x1)   /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */
+#define I2S_SERCTRL_BITREV          (0x1ul << I2S_SERCTRL_BITREV_Pos)
+#define   I2S_SERCTRL_BITREV_MSBIT_Val    0x0ul  /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
+#define   I2S_SERCTRL_BITREV_LSBIT_Val    0x1ul  /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */
 #define I2S_SERCTRL_BITREV_MSBIT    (I2S_SERCTRL_BITREV_MSBIT_Val  << I2S_SERCTRL_BITREV_Pos)
 #define I2S_SERCTRL_BITREV_LSBIT    (I2S_SERCTRL_BITREV_LSBIT_Val  << I2S_SERCTRL_BITREV_Pos)
 #define I2S_SERCTRL_SLOTDIS0_Pos    16           /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */
@@ -563,23 +578,23 @@ typedef union {
 #define I2S_SERCTRL_SLOTDIS7_Pos    23           /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */
 #define I2S_SERCTRL_SLOTDIS7        (1 << I2S_SERCTRL_SLOTDIS7_Pos)
 #define I2S_SERCTRL_SLOTDIS_Pos     16           /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */
-#define I2S_SERCTRL_SLOTDIS_Msk     (_U(0xFF) << I2S_SERCTRL_SLOTDIS_Pos)
+#define I2S_SERCTRL_SLOTDIS_Msk     (0xFFul << I2S_SERCTRL_SLOTDIS_Pos)
 #define I2S_SERCTRL_SLOTDIS(value)  (I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos))
 #define I2S_SERCTRL_MONO_Pos        24           /**< \brief (I2S_SERCTRL) Mono Mode */
-#define I2S_SERCTRL_MONO            (_U(0x1) << I2S_SERCTRL_MONO_Pos)
-#define   I2S_SERCTRL_MONO_STEREO_Val     _U(0x0)   /**< \brief (I2S_SERCTRL) Normal mode */
-#define   I2S_SERCTRL_MONO_MONO_Val       _U(0x1)   /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */
+#define I2S_SERCTRL_MONO            (0x1ul << I2S_SERCTRL_MONO_Pos)
+#define   I2S_SERCTRL_MONO_STEREO_Val     0x0ul  /**< \brief (I2S_SERCTRL) Normal mode */
+#define   I2S_SERCTRL_MONO_MONO_Val       0x1ul  /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */
 #define I2S_SERCTRL_MONO_STEREO     (I2S_SERCTRL_MONO_STEREO_Val   << I2S_SERCTRL_MONO_Pos)
 #define I2S_SERCTRL_MONO_MONO       (I2S_SERCTRL_MONO_MONO_Val     << I2S_SERCTRL_MONO_Pos)
 #define I2S_SERCTRL_DMA_Pos         25           /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */
-#define I2S_SERCTRL_DMA             (_U(0x1) << I2S_SERCTRL_DMA_Pos)
-#define   I2S_SERCTRL_DMA_SINGLE_Val      _U(0x0)   /**< \brief (I2S_SERCTRL) Single DMA channel */
-#define   I2S_SERCTRL_DMA_MULTIPLE_Val    _U(0x1)   /**< \brief (I2S_SERCTRL) One DMA channel per data channel */
+#define I2S_SERCTRL_DMA             (0x1ul << I2S_SERCTRL_DMA_Pos)
+#define   I2S_SERCTRL_DMA_SINGLE_Val      0x0ul  /**< \brief (I2S_SERCTRL) Single DMA channel */
+#define   I2S_SERCTRL_DMA_MULTIPLE_Val    0x1ul  /**< \brief (I2S_SERCTRL) One DMA channel per data channel */
 #define I2S_SERCTRL_DMA_SINGLE      (I2S_SERCTRL_DMA_SINGLE_Val    << I2S_SERCTRL_DMA_Pos)
 #define I2S_SERCTRL_DMA_MULTIPLE    (I2S_SERCTRL_DMA_MULTIPLE_Val  << I2S_SERCTRL_DMA_Pos)
 #define I2S_SERCTRL_RXLOOP_Pos      26           /**< \brief (I2S_SERCTRL) Loop-back Test Mode */
-#define I2S_SERCTRL_RXLOOP          (_U(0x1) << I2S_SERCTRL_RXLOOP_Pos)
-#define I2S_SERCTRL_MASK            _U(0x07FFF7BF) /**< \brief (I2S_SERCTRL) MASK Register */
+#define I2S_SERCTRL_RXLOOP          (0x1ul << I2S_SERCTRL_RXLOOP_Pos)
+#define I2S_SERCTRL_MASK            0x07FFF7BFul /**< \brief (I2S_SERCTRL) MASK Register */
 
 /* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -592,12 +607,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define I2S_DATA_OFFSET             0x30         /**< \brief (I2S_DATA offset) Data n */
-#define I2S_DATA_RESETVALUE         _U(0x00000000) /**< \brief (I2S_DATA reset_value) Data n */
+#define I2S_DATA_RESETVALUE         0x00000000ul /**< \brief (I2S_DATA reset_value) Data n */
 
 #define I2S_DATA_DATA_Pos           0            /**< \brief (I2S_DATA) Sample Data */
-#define I2S_DATA_DATA_Msk           (_U(0xFFFFFFFF) << I2S_DATA_DATA_Pos)
+#define I2S_DATA_DATA_Msk           (0xFFFFFFFFul << I2S_DATA_DATA_Pos)
 #define I2S_DATA_DATA(value)        (I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos))
-#define I2S_DATA_MASK               _U(0xFFFFFFFF) /**< \brief (I2S_DATA) MASK Register */
+#define I2S_DATA_MASK               0xFFFFFFFFul /**< \brief (I2S_DATA) MASK Register */
 
 /** \brief I2S hardware registers */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

asf/sam0/utils/cmsis/samd21/include/component/mtb.h

@@ -3,24 +3,39 @@
  *
  * \brief Component description for MTB
  *
- * Copyright (c) 2016 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *
  * \asf_license_stop
  *
@@ -53,11 +68,11 @@ typedef union {
 #define MTB_POSITION_OFFSET         0x000        /**< \brief (MTB_POSITION offset) MTB Position */
 
 #define MTB_POSITION_WRAP_Pos       2            /**< \brief (MTB_POSITION) Pointer Value Wraps */
-#define MTB_POSITION_WRAP           (_U(0x1) << MTB_POSITION_WRAP_Pos)
+#define MTB_POSITION_WRAP           (0x1ul << MTB_POSITION_WRAP_Pos)
 #define MTB_POSITION_POINTER_Pos    3            /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
-#define MTB_POSITION_POINTER_Msk    (_U(0x1FFFFFFF) << MTB_POSITION_POINTER_Pos)
+#define MTB_POSITION_POINTER_Msk    (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos)
 #define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))
-#define MTB_POSITION_MASK           _U(0xFFFFFFFC) /**< \brief (MTB_POSITION) MASK Register */
+#define MTB_POSITION_MASK           0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */
 
 /* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -77,24 +92,24 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_MASTER_OFFSET           0x004        /**< \brief (MTB_MASTER offset) MTB Master */
-#define MTB_MASTER_RESETVALUE       _U(0x00000000) /**< \brief (MTB_MASTER reset_value) MTB Master */
+#define MTB_MASTER_RESETVALUE       0x00000000ul /**< \brief (MTB_MASTER reset_value) MTB Master */
 
 #define MTB_MASTER_MASK_Pos         0            /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
-#define MTB_MASTER_MASK_Msk         (_U(0x1F) << MTB_MASTER_MASK_Pos)
+#define MTB_MASTER_MASK_Msk         (0x1Ful << MTB_MASTER_MASK_Pos)
 #define MTB_MASTER_MASK(value)      (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))
 #define MTB_MASTER_TSTARTEN_Pos     5            /**< \brief (MTB_MASTER) Trace Start Input Enable */
-#define MTB_MASTER_TSTARTEN         (_U(0x1) << MTB_MASTER_TSTARTEN_Pos)
+#define MTB_MASTER_TSTARTEN         (0x1ul << MTB_MASTER_TSTARTEN_Pos)
 #define MTB_MASTER_TSTOPEN_Pos      6            /**< \brief (MTB_MASTER) Trace Stop Input Enable */
-#define MTB_MASTER_TSTOPEN          (_U(0x1) << MTB_MASTER_TSTOPEN_Pos)
+#define MTB_MASTER_TSTOPEN          (0x1ul << MTB_MASTER_TSTOPEN_Pos)
 #define MTB_MASTER_SFRWPRIV_Pos     7            /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
-#define MTB_MASTER_SFRWPRIV         (_U(0x1) << MTB_MASTER_SFRWPRIV_Pos)
+#define MTB_MASTER_SFRWPRIV         (0x1ul << MTB_MASTER_SFRWPRIV_Pos)
 #define MTB_MASTER_RAMPRIV_Pos      8            /**< \brief (MTB_MASTER) SRAM Privilege */
-#define MTB_MASTER_RAMPRIV          (_U(0x1) << MTB_MASTER_RAMPRIV_Pos)
+#define MTB_MASTER_RAMPRIV          (0x1ul << MTB_MASTER_RAMPRIV_Pos)
 #define MTB_MASTER_HALTREQ_Pos      9            /**< \brief (MTB_MASTER) Halt Request */
-#define MTB_MASTER_HALTREQ          (_U(0x1) << MTB_MASTER_HALTREQ_Pos)
+#define MTB_MASTER_HALTREQ          (0x1ul << MTB_MASTER_HALTREQ_Pos)
 #define MTB_MASTER_EN_Pos           31           /**< \brief (MTB_MASTER) Main Trace Enable */
-#define MTB_MASTER_EN               (_U(0x1) << MTB_MASTER_EN_Pos)
-#define MTB_MASTER_MASK_            _U(0x800003FF) /**< \brief (MTB_MASTER) MASK Register */
+#define MTB_MASTER_EN               (0x1ul << MTB_MASTER_EN_Pos)
+#define MTB_MASTER_MASK_            0x800003FFul /**< \brief (MTB_MASTER) MASK Register */
 
 /* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -110,16 +125,16 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_FLOW_OFFSET             0x008        /**< \brief (MTB_FLOW offset) MTB Flow */
-#define MTB_FLOW_RESETVALUE         _U(0x00000000) /**< \brief (MTB_FLOW reset_value) MTB Flow */
+#define MTB_FLOW_RESETVALUE         0x00000000ul /**< \brief (MTB_FLOW reset_value) MTB Flow */
 
 #define MTB_FLOW_AUTOSTOP_Pos       0            /**< \brief (MTB_FLOW) Auto Stop Tracing */
-#define MTB_FLOW_AUTOSTOP           (_U(0x1) << MTB_FLOW_AUTOSTOP_Pos)
+#define MTB_FLOW_AUTOSTOP           (0x1ul << MTB_FLOW_AUTOSTOP_Pos)
 #define MTB_FLOW_AUTOHALT_Pos       1            /**< \brief (MTB_FLOW) Auto Halt Request */
-#define MTB_FLOW_AUTOHALT           (_U(0x1) << MTB_FLOW_AUTOHALT_Pos)
+#define MTB_FLOW_AUTOHALT           (0x1ul << MTB_FLOW_AUTOHALT_Pos)
 #define MTB_FLOW_WATERMARK_Pos      3            /**< \brief (MTB_FLOW) Watermark value */
-#define MTB_FLOW_WATERMARK_Msk      (_U(0x1FFFFFFF) << MTB_FLOW_WATERMARK_Pos)
+#define MTB_FLOW_WATERMARK_Msk      (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos)
 #define MTB_FLOW_WATERMARK(value)   (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))
-#define MTB_FLOW_MASK               _U(0xFFFFFFFB) /**< \brief (MTB_FLOW) MASK Register */
+#define MTB_FLOW_MASK               0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */
 
 /* -------- MTB_BASE : (MTB Offset: 0x00C) (R/  32) MTB Base -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -129,7 +144,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_BASE_OFFSET             0x00C        /**< \brief (MTB_BASE offset) MTB Base */
-#define MTB_BASE_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_BASE) MASK Register */
+#define MTB_BASE_MASK               0xFFFFFFFFul /**< \brief (MTB_BASE) MASK Register */
 
 /* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -139,7 +154,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_ITCTRL_OFFSET           0xF00        /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
-#define MTB_ITCTRL_MASK             _U(0xFFFFFFFF) /**< \brief (MTB_ITCTRL) MASK Register */
+#define MTB_ITCTRL_MASK             0xFFFFFFFFul /**< \brief (MTB_ITCTRL) MASK Register */
 
 /* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -149,7 +164,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_CLAIMSET_OFFSET         0xFA0        /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
-#define MTB_CLAIMSET_MASK           _U(0xFFFFFFFF) /**< \brief (MTB_CLAIMSET) MASK Register */
+#define MTB_CLAIMSET_MASK           0xFFFFFFFFul /**< \brief (MTB_CLAIMSET) MASK Register */
 
 /* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -159,7 +174,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_CLAIMCLR_OFFSET         0xFA4        /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
-#define MTB_CLAIMCLR_MASK           _U(0xFFFFFFFF) /**< \brief (MTB_CLAIMCLR) MASK Register */
+#define MTB_CLAIMCLR_MASK           0xFFFFFFFFul /**< \brief (MTB_CLAIMCLR) MASK Register */
 
 /* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -169,7 +184,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_LOCKACCESS_OFFSET       0xFB0        /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
-#define MTB_LOCKACCESS_MASK         _U(0xFFFFFFFF) /**< \brief (MTB_LOCKACCESS) MASK Register */
+#define MTB_LOCKACCESS_MASK         0xFFFFFFFFul /**< \brief (MTB_LOCKACCESS) MASK Register */
 
 /* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/  32) MTB Lock Status -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -179,7 +194,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_LOCKSTATUS_OFFSET       0xFB4        /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
-#define MTB_LOCKSTATUS_MASK         _U(0xFFFFFFFF) /**< \brief (MTB_LOCKSTATUS) MASK Register */
+#define MTB_LOCKSTATUS_MASK         0xFFFFFFFFul /**< \brief (MTB_LOCKSTATUS) MASK Register */
 
 /* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/  32) MTB Authentication Status -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -189,7 +204,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_AUTHSTATUS_OFFSET       0xFB8        /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
-#define MTB_AUTHSTATUS_MASK         _U(0xFFFFFFFF) /**< \brief (MTB_AUTHSTATUS) MASK Register */
+#define MTB_AUTHSTATUS_MASK         0xFFFFFFFFul /**< \brief (MTB_AUTHSTATUS) MASK Register */
 
 /* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/  32) MTB Device Architecture -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -199,7 +214,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_DEVARCH_OFFSET          0xFBC        /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
-#define MTB_DEVARCH_MASK            _U(0xFFFFFFFF) /**< \brief (MTB_DEVARCH) MASK Register */
+#define MTB_DEVARCH_MASK            0xFFFFFFFFul /**< \brief (MTB_DEVARCH) MASK Register */
 
 /* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/  32) MTB Device Configuration -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -209,7 +224,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_DEVID_OFFSET            0xFC8        /**< \brief (MTB_DEVID offset) MTB Device Configuration */
-#define MTB_DEVID_MASK              _U(0xFFFFFFFF) /**< \brief (MTB_DEVID) MASK Register */
+#define MTB_DEVID_MASK              0xFFFFFFFFul /**< \brief (MTB_DEVID) MASK Register */
 
 /* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/  32) MTB Device Type -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -219,7 +234,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_DEVTYPE_OFFSET          0xFCC        /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
-#define MTB_DEVTYPE_MASK            _U(0xFFFFFFFF) /**< \brief (MTB_DEVTYPE) MASK Register */
+#define MTB_DEVTYPE_MASK            0xFFFFFFFFul /**< \brief (MTB_DEVTYPE) MASK Register */
 
 /* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/  32) CoreSight -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -229,7 +244,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_PID4_OFFSET             0xFD0        /**< \brief (MTB_PID4 offset) CoreSight */
-#define MTB_PID4_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID4) MASK Register */
+#define MTB_PID4_MASK               0xFFFFFFFFul /**< \brief (MTB_PID4) MASK Register */
 
 /* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/  32) CoreSight -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -239,7 +254,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_PID5_OFFSET             0xFD4        /**< \brief (MTB_PID5 offset) CoreSight */
-#define MTB_PID5_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID5) MASK Register */
+#define MTB_PID5_MASK               0xFFFFFFFFul /**< \brief (MTB_PID5) MASK Register */
 
 /* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/  32) CoreSight -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -249,7 +264,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_PID6_OFFSET             0xFD8        /**< \brief (MTB_PID6 offset) CoreSight */
-#define MTB_PID6_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID6) MASK Register */
+#define MTB_PID6_MASK               0xFFFFFFFFul /**< \brief (MTB_PID6) MASK Register */
 
 /* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/  32) CoreSight -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -259,7 +274,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_PID7_OFFSET             0xFDC        /**< \brief (MTB_PID7 offset) CoreSight */
-#define MTB_PID7_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID7) MASK Register */
+#define MTB_PID7_MASK               0xFFFFFFFFul /**< \brief (MTB_PID7) MASK Register */
 
 /* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/  32) CoreSight -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -269,7 +284,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_PID0_OFFSET             0xFE0        /**< \brief (MTB_PID0 offset) CoreSight */
-#define MTB_PID0_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID0) MASK Register */
+#define MTB_PID0_MASK               0xFFFFFFFFul /**< \brief (MTB_PID0) MASK Register */
 
 /* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/  32) CoreSight -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -279,7 +294,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_PID1_OFFSET             0xFE4        /**< \brief (MTB_PID1 offset) CoreSight */
-#define MTB_PID1_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID1) MASK Register */
+#define MTB_PID1_MASK               0xFFFFFFFFul /**< \brief (MTB_PID1) MASK Register */
 
 /* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/  32) CoreSight -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -289,7 +304,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_PID2_OFFSET             0xFE8        /**< \brief (MTB_PID2 offset) CoreSight */
-#define MTB_PID2_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID2) MASK Register */
+#define MTB_PID2_MASK               0xFFFFFFFFul /**< \brief (MTB_PID2) MASK Register */
 
 /* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/  32) CoreSight -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -299,7 +314,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_PID3_OFFSET             0xFEC        /**< \brief (MTB_PID3 offset) CoreSight */
-#define MTB_PID3_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_PID3) MASK Register */
+#define MTB_PID3_MASK               0xFFFFFFFFul /**< \brief (MTB_PID3) MASK Register */
 
 /* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/  32) CoreSight -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -309,7 +324,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_CID0_OFFSET             0xFF0        /**< \brief (MTB_CID0 offset) CoreSight */
-#define MTB_CID0_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_CID0) MASK Register */
+#define MTB_CID0_MASK               0xFFFFFFFFul /**< \brief (MTB_CID0) MASK Register */
 
 /* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/  32) CoreSight -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -319,7 +334,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_CID1_OFFSET             0xFF4        /**< \brief (MTB_CID1 offset) CoreSight */
-#define MTB_CID1_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_CID1) MASK Register */
+#define MTB_CID1_MASK               0xFFFFFFFFul /**< \brief (MTB_CID1) MASK Register */
 
 /* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/  32) CoreSight -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -329,7 +344,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_CID2_OFFSET             0xFF8        /**< \brief (MTB_CID2 offset) CoreSight */
-#define MTB_CID2_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_CID2) MASK Register */
+#define MTB_CID2_MASK               0xFFFFFFFFul /**< \brief (MTB_CID2) MASK Register */
 
 /* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/  32) CoreSight -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -339,7 +354,7 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define MTB_CID3_OFFSET             0xFFC        /**< \brief (MTB_CID3 offset) CoreSight */
-#define MTB_CID3_MASK               _U(0xFFFFFFFF) /**< \brief (MTB_CID3) MASK Register */
+#define MTB_CID3_MASK               0xFFFFFFFFul /**< \brief (MTB_CID3) MASK Register */
 
 /** \brief MTB hardware registers */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

asf/sam0/utils/cmsis/samd21/include/component/nvmctrl.h

@@ -3,24 +3,39 @@
  *
  * \brief Component description for NVMCTRL
  *
- * Copyright (c) 2016 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *
  * \asf_license_stop
  *
@@ -51,26 +66,26 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define NVMCTRL_CTRLA_OFFSET        0x00         /**< \brief (NVMCTRL_CTRLA offset) Control A */
-#define NVMCTRL_CTRLA_RESETVALUE    _U(0x0000)   /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
+#define NVMCTRL_CTRLA_RESETVALUE    0x0000ul     /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
 
 #define NVMCTRL_CTRLA_CMD_Pos       0            /**< \brief (NVMCTRL_CTRLA) Command */
-#define NVMCTRL_CTRLA_CMD_Msk       (_U(0x7F) << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_Msk       (0x7Ful << NVMCTRL_CTRLA_CMD_Pos)
 #define NVMCTRL_CTRLA_CMD(value)    (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))
-#define   NVMCTRL_CTRLA_CMD_ER_Val        _U(0x2)   /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_WP_Val        _U(0x4)   /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_EAR_Val       _U(0x5)   /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
-#define   NVMCTRL_CTRLA_CMD_WAP_Val       _U(0x6)   /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
-#define   NVMCTRL_CTRLA_CMD_SF_Val        _U(0xA)   /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
-#define   NVMCTRL_CTRLA_CMD_WL_Val        _U(0xF)   /**< \brief (NVMCTRL_CTRLA) Write lockbits */
-#define   NVMCTRL_CTRLA_CMD_RWWEEER_Val   _U(0x1A)   /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_RWWEEWP_Val   _U(0x1C)   /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_LR_Val        _U(0x40)   /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_UR_Val        _U(0x41)   /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
-#define   NVMCTRL_CTRLA_CMD_SPRM_Val      _U(0x42)   /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
-#define   NVMCTRL_CTRLA_CMD_CPRM_Val      _U(0x43)   /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
-#define   NVMCTRL_CTRLA_CMD_PBC_Val       _U(0x44)   /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
-#define   NVMCTRL_CTRLA_CMD_SSB_Val       _U(0x45)   /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
-#define   NVMCTRL_CTRLA_CMD_INVALL_Val    _U(0x46)   /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */
+#define   NVMCTRL_CTRLA_CMD_ER_Val        0x2ul  /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_WP_Val        0x4ul  /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_EAR_Val       0x5ul  /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define   NVMCTRL_CTRLA_CMD_WAP_Val       0x6ul  /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define   NVMCTRL_CTRLA_CMD_SF_Val        0xAul  /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
+#define   NVMCTRL_CTRLA_CMD_WL_Val        0xFul  /**< \brief (NVMCTRL_CTRLA) Write lockbits */
+#define   NVMCTRL_CTRLA_CMD_RWWEEER_Val   0x1Aul  /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_RWWEEWP_Val   0x1Cul  /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_LR_Val        0x40ul  /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_UR_Val        0x41ul  /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_SPRM_Val      0x42ul  /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
+#define   NVMCTRL_CTRLA_CMD_CPRM_Val      0x43ul  /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
+#define   NVMCTRL_CTRLA_CMD_PBC_Val       0x44ul  /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
+#define   NVMCTRL_CTRLA_CMD_SSB_Val       0x45ul  /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
+#define   NVMCTRL_CTRLA_CMD_INVALL_Val    0x46ul  /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */
 #define NVMCTRL_CTRLA_CMD_ER        (NVMCTRL_CTRLA_CMD_ER_Val      << NVMCTRL_CTRLA_CMD_Pos)
 #define NVMCTRL_CTRLA_CMD_WP        (NVMCTRL_CTRLA_CMD_WP_Val      << NVMCTRL_CTRLA_CMD_Pos)
 #define NVMCTRL_CTRLA_CMD_EAR       (NVMCTRL_CTRLA_CMD_EAR_Val     << NVMCTRL_CTRLA_CMD_Pos)
@@ -87,11 +102,11 @@ typedef union {
 #define NVMCTRL_CTRLA_CMD_SSB       (NVMCTRL_CTRLA_CMD_SSB_Val     << NVMCTRL_CTRLA_CMD_Pos)
 #define NVMCTRL_CTRLA_CMD_INVALL    (NVMCTRL_CTRLA_CMD_INVALL_Val  << NVMCTRL_CTRLA_CMD_Pos)
 #define NVMCTRL_CTRLA_CMDEX_Pos     8            /**< \brief (NVMCTRL_CTRLA) Command Execution */
-#define NVMCTRL_CTRLA_CMDEX_Msk     (_U(0xFF) << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_CMDEX_Msk     (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos)
 #define NVMCTRL_CTRLA_CMDEX(value)  (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))
-#define   NVMCTRL_CTRLA_CMDEX_KEY_Val     _U(0xA5)   /**< \brief (NVMCTRL_CTRLA) Execution Key */
+#define   NVMCTRL_CTRLA_CMDEX_KEY_Val     0xA5ul  /**< \brief (NVMCTRL_CTRLA) Execution Key */
 #define NVMCTRL_CTRLA_CMDEX_KEY     (NVMCTRL_CTRLA_CMDEX_KEY_Val   << NVMCTRL_CTRLA_CMDEX_Pos)
-#define NVMCTRL_CTRLA_MASK          _U(0xFF7F)   /**< \brief (NVMCTRL_CTRLA) MASK Register */
+#define NVMCTRL_CTRLA_MASK          0xFF7Ful     /**< \brief (NVMCTRL_CTRLA) MASK Register */
 
 /* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -112,40 +127,40 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define NVMCTRL_CTRLB_OFFSET        0x04         /**< \brief (NVMCTRL_CTRLB offset) Control B */
-#define NVMCTRL_CTRLB_RESETVALUE    _U(0x00000000) /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
+#define NVMCTRL_CTRLB_RESETVALUE    0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
 
 #define NVMCTRL_CTRLB_RWS_Pos       1            /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
-#define NVMCTRL_CTRLB_RWS_Msk       (_U(0xF) << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_Msk       (0xFul << NVMCTRL_CTRLB_RWS_Pos)
 #define NVMCTRL_CTRLB_RWS(value)    (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))
-#define   NVMCTRL_CTRLB_RWS_SINGLE_Val    _U(0x0)   /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
-#define   NVMCTRL_CTRLB_RWS_HALF_Val      _U(0x1)   /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
-#define   NVMCTRL_CTRLB_RWS_DUAL_Val      _U(0x2)   /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_SINGLE_Val    0x0ul  /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_HALF_Val      0x1ul  /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_DUAL_Val      0x2ul  /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
 #define NVMCTRL_CTRLB_RWS_SINGLE    (NVMCTRL_CTRLB_RWS_SINGLE_Val  << NVMCTRL_CTRLB_RWS_Pos)
 #define NVMCTRL_CTRLB_RWS_HALF      (NVMCTRL_CTRLB_RWS_HALF_Val    << NVMCTRL_CTRLB_RWS_Pos)
 #define NVMCTRL_CTRLB_RWS_DUAL      (NVMCTRL_CTRLB_RWS_DUAL_Val    << NVMCTRL_CTRLB_RWS_Pos)
 #define NVMCTRL_CTRLB_MANW_Pos      7            /**< \brief (NVMCTRL_CTRLB) Manual Write */
-#define NVMCTRL_CTRLB_MANW          (_U(0x1) << NVMCTRL_CTRLB_MANW_Pos)
+#define NVMCTRL_CTRLB_MANW          (0x1ul << NVMCTRL_CTRLB_MANW_Pos)
 #define NVMCTRL_CTRLB_SLEEPPRM_Pos  8            /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
-#define NVMCTRL_CTRLB_SLEEPPRM_Msk  (_U(0x3) << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_Msk  (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos)
 #define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))
-#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val _U(0x0)   /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
-#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val _U(0x1)   /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
-#define   NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val _U(0x3)   /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul  /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul  /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul  /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
 #define NVMCTRL_CTRLB_READMODE_Pos  16           /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
-#define NVMCTRL_CTRLB_READMODE_Msk  (_U(0x3) << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_Msk  (0x3ul << NVMCTRL_CTRLB_READMODE_Pos)
 #define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))
-#define   NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val _U(0x0)   /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
-#define   NVMCTRL_CTRLB_READMODE_LOW_POWER_Val _U(0x1)   /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
-#define   NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val _U(0x2)   /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
+#define   NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul  /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
+#define   NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul  /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
+#define   NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul  /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
 #define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
 #define NVMCTRL_CTRLB_CACHEDIS_Pos  18           /**< \brief (NVMCTRL_CTRLB) Cache Disable */
-#define NVMCTRL_CTRLB_CACHEDIS      (_U(0x1) << NVMCTRL_CTRLB_CACHEDIS_Pos)
-#define NVMCTRL_CTRLB_MASK          _U(0x0007039E) /**< \brief (NVMCTRL_CTRLB) MASK Register */
+#define NVMCTRL_CTRLB_CACHEDIS      (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos)
+#define NVMCTRL_CTRLB_MASK          0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */
 
 /* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -161,22 +176,22 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define NVMCTRL_PARAM_OFFSET        0x08         /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
-#define NVMCTRL_PARAM_RESETVALUE    _U(0x00000000) /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
+#define NVMCTRL_PARAM_RESETVALUE    0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
 
 #define NVMCTRL_PARAM_NVMP_Pos      0            /**< \brief (NVMCTRL_PARAM) NVM Pages */
-#define NVMCTRL_PARAM_NVMP_Msk      (_U(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos)
+#define NVMCTRL_PARAM_NVMP_Msk      (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos)
 #define NVMCTRL_PARAM_NVMP(value)   (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
 #define NVMCTRL_PARAM_PSZ_Pos       16           /**< \brief (NVMCTRL_PARAM) Page Size */
-#define NVMCTRL_PARAM_PSZ_Msk       (_U(0x7) << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_Msk       (0x7ul << NVMCTRL_PARAM_PSZ_Pos)
 #define NVMCTRL_PARAM_PSZ(value)    (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
-#define   NVMCTRL_PARAM_PSZ_8_Val         _U(0x0)   /**< \brief (NVMCTRL_PARAM) 8 bytes */
-#define   NVMCTRL_PARAM_PSZ_16_Val        _U(0x1)   /**< \brief (NVMCTRL_PARAM) 16 bytes */
-#define   NVMCTRL_PARAM_PSZ_32_Val        _U(0x2)   /**< \brief (NVMCTRL_PARAM) 32 bytes */
-#define   NVMCTRL_PARAM_PSZ_64_Val        _U(0x3)   /**< \brief (NVMCTRL_PARAM) 64 bytes */
-#define   NVMCTRL_PARAM_PSZ_128_Val       _U(0x4)   /**< \brief (NVMCTRL_PARAM) 128 bytes */
-#define   NVMCTRL_PARAM_PSZ_256_Val       _U(0x5)   /**< \brief (NVMCTRL_PARAM) 256 bytes */
-#define   NVMCTRL_PARAM_PSZ_512_Val       _U(0x6)   /**< \brief (NVMCTRL_PARAM) 512 bytes */
-#define   NVMCTRL_PARAM_PSZ_1024_Val      _U(0x7)   /**< \brief (NVMCTRL_PARAM) 1024 bytes */
+#define   NVMCTRL_PARAM_PSZ_8_Val         0x0ul  /**< \brief (NVMCTRL_PARAM) 8 bytes */
+#define   NVMCTRL_PARAM_PSZ_16_Val        0x1ul  /**< \brief (NVMCTRL_PARAM) 16 bytes */
+#define   NVMCTRL_PARAM_PSZ_32_Val        0x2ul  /**< \brief (NVMCTRL_PARAM) 32 bytes */
+#define   NVMCTRL_PARAM_PSZ_64_Val        0x3ul  /**< \brief (NVMCTRL_PARAM) 64 bytes */
+#define   NVMCTRL_PARAM_PSZ_128_Val       0x4ul  /**< \brief (NVMCTRL_PARAM) 128 bytes */
+#define   NVMCTRL_PARAM_PSZ_256_Val       0x5ul  /**< \brief (NVMCTRL_PARAM) 256 bytes */
+#define   NVMCTRL_PARAM_PSZ_512_Val       0x6ul  /**< \brief (NVMCTRL_PARAM) 512 bytes */
+#define   NVMCTRL_PARAM_PSZ_1024_Val      0x7ul  /**< \brief (NVMCTRL_PARAM) 1024 bytes */
 #define NVMCTRL_PARAM_PSZ_8         (NVMCTRL_PARAM_PSZ_8_Val       << NVMCTRL_PARAM_PSZ_Pos)
 #define NVMCTRL_PARAM_PSZ_16        (NVMCTRL_PARAM_PSZ_16_Val      << NVMCTRL_PARAM_PSZ_Pos)
 #define NVMCTRL_PARAM_PSZ_32        (NVMCTRL_PARAM_PSZ_32_Val      << NVMCTRL_PARAM_PSZ_Pos)
@@ -186,9 +201,9 @@ typedef union {
 #define NVMCTRL_PARAM_PSZ_512       (NVMCTRL_PARAM_PSZ_512_Val     << NVMCTRL_PARAM_PSZ_Pos)
 #define NVMCTRL_PARAM_PSZ_1024      (NVMCTRL_PARAM_PSZ_1024_Val    << NVMCTRL_PARAM_PSZ_Pos)
 #define NVMCTRL_PARAM_RWWEEP_Pos    20           /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */
-#define NVMCTRL_PARAM_RWWEEP_Msk    (_U(0xFFF) << NVMCTRL_PARAM_RWWEEP_Pos)
+#define NVMCTRL_PARAM_RWWEEP_Msk    (0xFFFul << NVMCTRL_PARAM_RWWEEP_Pos)
 #define NVMCTRL_PARAM_RWWEEP(value) (NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos))
-#define NVMCTRL_PARAM_MASK          _U(0xFFF7FFFF) /**< \brief (NVMCTRL_PARAM) MASK Register */
+#define NVMCTRL_PARAM_MASK          0xFFF7FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
 
 /* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W  8) Interrupt Enable Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -203,13 +218,13 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define NVMCTRL_INTENCLR_OFFSET     0x0C         /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
-#define NVMCTRL_INTENCLR_RESETVALUE _U(0x00)     /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+#define NVMCTRL_INTENCLR_RESETVALUE 0x00ul       /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
 
 #define NVMCTRL_INTENCLR_READY_Pos  0            /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
-#define NVMCTRL_INTENCLR_READY      (_U(0x1) << NVMCTRL_INTENCLR_READY_Pos)
+#define NVMCTRL_INTENCLR_READY      (0x1ul << NVMCTRL_INTENCLR_READY_Pos)
 #define NVMCTRL_INTENCLR_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
-#define NVMCTRL_INTENCLR_ERROR      (_U(0x1) << NVMCTRL_INTENCLR_ERROR_Pos)
-#define NVMCTRL_INTENCLR_MASK       _U(0x03)     /**< \brief (NVMCTRL_INTENCLR) MASK Register */
+#define NVMCTRL_INTENCLR_ERROR      (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos)
+#define NVMCTRL_INTENCLR_MASK       0x03ul       /**< \brief (NVMCTRL_INTENCLR) MASK Register */
 
 /* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W  8) Interrupt Enable Set -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -224,13 +239,13 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define NVMCTRL_INTENSET_OFFSET     0x10         /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
-#define NVMCTRL_INTENSET_RESETVALUE _U(0x00)     /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
+#define NVMCTRL_INTENSET_RESETVALUE 0x00ul       /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
 
 #define NVMCTRL_INTENSET_READY_Pos  0            /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
-#define NVMCTRL_INTENSET_READY      (_U(0x1) << NVMCTRL_INTENSET_READY_Pos)
+#define NVMCTRL_INTENSET_READY      (0x1ul << NVMCTRL_INTENSET_READY_Pos)
 #define NVMCTRL_INTENSET_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
-#define NVMCTRL_INTENSET_ERROR      (_U(0x1) << NVMCTRL_INTENSET_ERROR_Pos)
-#define NVMCTRL_INTENSET_MASK       _U(0x03)     /**< \brief (NVMCTRL_INTENSET) MASK Register */
+#define NVMCTRL_INTENSET_ERROR      (0x1ul << NVMCTRL_INTENSET_ERROR_Pos)
+#define NVMCTRL_INTENSET_MASK       0x03ul       /**< \brief (NVMCTRL_INTENSET) MASK Register */
 
 /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W  8) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -245,13 +260,13 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define NVMCTRL_INTFLAG_OFFSET      0x14         /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
-#define NVMCTRL_INTFLAG_RESETVALUE  _U(0x00)     /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+#define NVMCTRL_INTFLAG_RESETVALUE  0x00ul       /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
 
 #define NVMCTRL_INTFLAG_READY_Pos   0            /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
-#define NVMCTRL_INTFLAG_READY       (_U(0x1) << NVMCTRL_INTFLAG_READY_Pos)
+#define NVMCTRL_INTFLAG_READY       (0x1ul << NVMCTRL_INTFLAG_READY_Pos)
 #define NVMCTRL_INTFLAG_ERROR_Pos   1            /**< \brief (NVMCTRL_INTFLAG) Error */
-#define NVMCTRL_INTFLAG_ERROR       (_U(0x1) << NVMCTRL_INTFLAG_ERROR_Pos)
-#define NVMCTRL_INTFLAG_MASK        _U(0x03)     /**< \brief (NVMCTRL_INTFLAG) MASK Register */
+#define NVMCTRL_INTFLAG_ERROR       (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos)
+#define NVMCTRL_INTFLAG_MASK        0x03ul       /**< \brief (NVMCTRL_INTFLAG) MASK Register */
 
 /* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -271,21 +286,21 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define NVMCTRL_STATUS_OFFSET       0x18         /**< \brief (NVMCTRL_STATUS offset) Status */
-#define NVMCTRL_STATUS_RESETVALUE   _U(0x0000)   /**< \brief (NVMCTRL_STATUS reset_value) Status */
+#define NVMCTRL_STATUS_RESETVALUE   0x0000ul     /**< \brief (NVMCTRL_STATUS reset_value) Status */
 
 #define NVMCTRL_STATUS_PRM_Pos      0            /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
-#define NVMCTRL_STATUS_PRM          (_U(0x1) << NVMCTRL_STATUS_PRM_Pos)
+#define NVMCTRL_STATUS_PRM          (0x1ul << NVMCTRL_STATUS_PRM_Pos)
 #define NVMCTRL_STATUS_LOAD_Pos     1            /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
-#define NVMCTRL_STATUS_LOAD         (_U(0x1) << NVMCTRL_STATUS_LOAD_Pos)
+#define NVMCTRL_STATUS_LOAD         (0x1ul << NVMCTRL_STATUS_LOAD_Pos)
 #define NVMCTRL_STATUS_PROGE_Pos    2            /**< \brief (NVMCTRL_STATUS) Programming Error Status */
-#define NVMCTRL_STATUS_PROGE        (_U(0x1) << NVMCTRL_STATUS_PROGE_Pos)
+#define NVMCTRL_STATUS_PROGE        (0x1ul << NVMCTRL_STATUS_PROGE_Pos)
 #define NVMCTRL_STATUS_LOCKE_Pos    3            /**< \brief (NVMCTRL_STATUS) Lock Error Status */
-#define NVMCTRL_STATUS_LOCKE        (_U(0x1) << NVMCTRL_STATUS_LOCKE_Pos)
+#define NVMCTRL_STATUS_LOCKE        (0x1ul << NVMCTRL_STATUS_LOCKE_Pos)
 #define NVMCTRL_STATUS_NVME_Pos     4            /**< \brief (NVMCTRL_STATUS) NVM Error */
-#define NVMCTRL_STATUS_NVME         (_U(0x1) << NVMCTRL_STATUS_NVME_Pos)
+#define NVMCTRL_STATUS_NVME         (0x1ul << NVMCTRL_STATUS_NVME_Pos)
 #define NVMCTRL_STATUS_SB_Pos       8            /**< \brief (NVMCTRL_STATUS) Security Bit Status */
-#define NVMCTRL_STATUS_SB           (_U(0x1) << NVMCTRL_STATUS_SB_Pos)
-#define NVMCTRL_STATUS_MASK         _U(0x011F)   /**< \brief (NVMCTRL_STATUS) MASK Register */
+#define NVMCTRL_STATUS_SB           (0x1ul << NVMCTRL_STATUS_SB_Pos)
+#define NVMCTRL_STATUS_MASK         0x011Ful     /**< \brief (NVMCTRL_STATUS) MASK Register */
 
 /* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -299,12 +314,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define NVMCTRL_ADDR_OFFSET         0x1C         /**< \brief (NVMCTRL_ADDR offset) Address */
-#define NVMCTRL_ADDR_RESETVALUE     _U(0x00000000) /**< \brief (NVMCTRL_ADDR reset_value) Address */
+#define NVMCTRL_ADDR_RESETVALUE     0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */
 
 #define NVMCTRL_ADDR_ADDR_Pos       0            /**< \brief (NVMCTRL_ADDR) NVM Address */
-#define NVMCTRL_ADDR_ADDR_Msk       (_U(0x3FFFFF) << NVMCTRL_ADDR_ADDR_Pos)
+#define NVMCTRL_ADDR_ADDR_Msk       (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos)
 #define NVMCTRL_ADDR_ADDR(value)    (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
-#define NVMCTRL_ADDR_MASK           _U(0x003FFFFF) /**< \brief (NVMCTRL_ADDR) MASK Register */
+#define NVMCTRL_ADDR_MASK           0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */
 
 /* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -319,9 +334,9 @@ typedef union {
 #define NVMCTRL_LOCK_OFFSET         0x20         /**< \brief (NVMCTRL_LOCK offset) Lock Section */
 
 #define NVMCTRL_LOCK_LOCK_Pos       0            /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
-#define NVMCTRL_LOCK_LOCK_Msk       (_U(0xFFFF) << NVMCTRL_LOCK_LOCK_Pos)
+#define NVMCTRL_LOCK_LOCK_Msk       (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos)
 #define NVMCTRL_LOCK_LOCK(value)    (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))
-#define NVMCTRL_LOCK_MASK           _U(0xFFFF)   /**< \brief (NVMCTRL_LOCK) MASK Register */
+#define NVMCTRL_LOCK_MASK           0xFFFFul     /**< \brief (NVMCTRL_LOCK) MASK Register */
 
 /** \brief NVMCTRL APB hardware registers */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -370,171 +385,241 @@ typedef struct {
 
 #define ADC_FUSES_BIASCAL_ADDR      (NVMCTRL_OTP4 + 4)
 #define ADC_FUSES_BIASCAL_Pos       3            /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
-#define ADC_FUSES_BIASCAL_Msk       (_U(0x7) << ADC_FUSES_BIASCAL_Pos)
+#define ADC_FUSES_BIASCAL_Msk       (0x7ul << ADC_FUSES_BIASCAL_Pos)
 #define ADC_FUSES_BIASCAL(value)    (ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))
 
 #define ADC_FUSES_LINEARITY_0_ADDR  NVMCTRL_OTP4
 #define ADC_FUSES_LINEARITY_0_Pos   27           /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
-#define ADC_FUSES_LINEARITY_0_Msk   (_U(0x1F) << ADC_FUSES_LINEARITY_0_Pos)
+#define ADC_FUSES_LINEARITY_0_Msk   (0x1Ful << ADC_FUSES_LINEARITY_0_Pos)
 #define ADC_FUSES_LINEARITY_0(value) (ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos))
 
 #define ADC_FUSES_LINEARITY_1_ADDR  (NVMCTRL_OTP4 + 4)
 #define ADC_FUSES_LINEARITY_1_Pos   0            /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
-#define ADC_FUSES_LINEARITY_1_Msk   (_U(0x7) << ADC_FUSES_LINEARITY_1_Pos)
+#define ADC_FUSES_LINEARITY_1_Msk   (0x7ul << ADC_FUSES_LINEARITY_1_Pos)
 #define ADC_FUSES_LINEARITY_1(value) (ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos))
 
 #define FUSES_BOD33USERLEVEL_ADDR   NVMCTRL_USER
 #define FUSES_BOD33USERLEVEL_Pos    8            /**< \brief (NVMCTRL_USER) BOD33 User Level */
-#define FUSES_BOD33USERLEVEL_Msk    (_U(0x3F) << FUSES_BOD33USERLEVEL_Pos)
+#define FUSES_BOD33USERLEVEL_Msk    (0x3Ful << FUSES_BOD33USERLEVEL_Pos)
 #define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
 
 #define FUSES_BOD33_ACTION_ADDR     NVMCTRL_USER
 #define FUSES_BOD33_ACTION_Pos      15           /**< \brief (NVMCTRL_USER) BOD33 Action */
-#define FUSES_BOD33_ACTION_Msk      (_U(0x3) << FUSES_BOD33_ACTION_Pos)
+#define FUSES_BOD33_ACTION_Msk      (0x3ul << FUSES_BOD33_ACTION_Pos)
 #define FUSES_BOD33_ACTION(value)   (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
 
 #define FUSES_BOD33_EN_ADDR         NVMCTRL_USER
 #define FUSES_BOD33_EN_Pos          14           /**< \brief (NVMCTRL_USER) BOD33 Enable */
-#define FUSES_BOD33_EN_Msk          (_U(0x1) << FUSES_BOD33_EN_Pos)
+#define FUSES_BOD33_EN_Msk          (0x1ul << FUSES_BOD33_EN_Pos)
 
 #define FUSES_BOD33_HYST_ADDR       (NVMCTRL_USER + 4)
 #define FUSES_BOD33_HYST_Pos        8            /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
-#define FUSES_BOD33_HYST_Msk        (_U(0x1) << FUSES_BOD33_HYST_Pos)
+#define FUSES_BOD33_HYST_Msk        (0x1ul << FUSES_BOD33_HYST_Pos)
 
 #define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
 #define FUSES_DFLL48M_COARSE_CAL_Pos 26           /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
-#define FUSES_DFLL48M_COARSE_CAL_Msk (_U(0x3F) << FUSES_DFLL48M_COARSE_CAL_Pos)
+#define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos)
 #define FUSES_DFLL48M_COARSE_CAL(value) (FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos))
 
 #define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
 #define FUSES_DFLL48M_FINE_CAL_Pos  0            /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
-#define FUSES_DFLL48M_FINE_CAL_Msk  (_U(0x3FF) << FUSES_DFLL48M_FINE_CAL_Pos)
+#define FUSES_DFLL48M_FINE_CAL_Msk  (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos)
 #define FUSES_DFLL48M_FINE_CAL(value) (FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos))
 
 #define FUSES_HOT_ADC_VAL_ADDR      (NVMCTRL_TEMP_LOG + 4)
 #define FUSES_HOT_ADC_VAL_Pos       20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
-#define FUSES_HOT_ADC_VAL_Msk       (_U(0xFFF) << FUSES_HOT_ADC_VAL_Pos)
+#define FUSES_HOT_ADC_VAL_Msk       (0xFFFul << FUSES_HOT_ADC_VAL_Pos)
 #define FUSES_HOT_ADC_VAL(value)    (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))
 
 #define FUSES_HOT_INT1V_VAL_ADDR    (NVMCTRL_TEMP_LOG + 4)
 #define FUSES_HOT_INT1V_VAL_Pos     0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
-#define FUSES_HOT_INT1V_VAL_Msk     (_U(0xFF) << FUSES_HOT_INT1V_VAL_Pos)
+#define FUSES_HOT_INT1V_VAL_Msk     (0xFFul << FUSES_HOT_INT1V_VAL_Pos)
 #define FUSES_HOT_INT1V_VAL(value)  (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
 
 #define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
 #define FUSES_HOT_TEMP_VAL_DEC_Pos  20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
-#define FUSES_HOT_TEMP_VAL_DEC_Msk  (_U(0xF) << FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define FUSES_HOT_TEMP_VAL_DEC_Msk  (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos)
 #define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
 
 #define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
 #define FUSES_HOT_TEMP_VAL_INT_Pos  12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
-#define FUSES_HOT_TEMP_VAL_INT_Msk  (_U(0xFF) << FUSES_HOT_TEMP_VAL_INT_Pos)
+#define FUSES_HOT_TEMP_VAL_INT_Msk  (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos)
 #define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
 
 #define FUSES_OSC32K_CAL_ADDR       (NVMCTRL_OTP4 + 4)
 #define FUSES_OSC32K_CAL_Pos        6            /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
-#define FUSES_OSC32K_CAL_Msk        (_U(0x7F) << FUSES_OSC32K_CAL_Pos)
+#define FUSES_OSC32K_CAL_Msk        (0x7Ful << FUSES_OSC32K_CAL_Pos)
 #define FUSES_OSC32K_CAL(value)     (FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos))
 
 #define FUSES_ROOM_ADC_VAL_ADDR     (NVMCTRL_TEMP_LOG + 4)
 #define FUSES_ROOM_ADC_VAL_Pos      8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
-#define FUSES_ROOM_ADC_VAL_Msk      (_U(0xFFF) << FUSES_ROOM_ADC_VAL_Pos)
+#define FUSES_ROOM_ADC_VAL_Msk      (0xFFFul << FUSES_ROOM_ADC_VAL_Pos)
 #define FUSES_ROOM_ADC_VAL(value)   (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))
 
 #define FUSES_ROOM_INT1V_VAL_ADDR   NVMCTRL_TEMP_LOG
 #define FUSES_ROOM_INT1V_VAL_Pos    24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
-#define FUSES_ROOM_INT1V_VAL_Msk    (_U(0xFF) << FUSES_ROOM_INT1V_VAL_Pos)
+#define FUSES_ROOM_INT1V_VAL_Msk    (0xFFul << FUSES_ROOM_INT1V_VAL_Pos)
 #define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
 
 #define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
 #define FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
-#define FUSES_ROOM_TEMP_VAL_DEC_Msk (_U(0xF) << FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos)
 #define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
 
 #define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
 #define FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
-#define FUSES_ROOM_TEMP_VAL_INT_Msk (_U(0xFF) << FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos)
 #define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
 
 #define FUSES_SERIAL_NUMBER_0_ADDR  (NVMCTRL_AUX3 + 64)
 #define FUSES_SERIAL_NUMBER_0_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 31:0 */
-#define FUSES_SERIAL_NUMBER_0_Msk   (_U(0xFFFFFFFF) << FUSES_SERIAL_NUMBER_0_Pos)
+#define FUSES_SERIAL_NUMBER_0_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_0_Pos)
 #define FUSES_SERIAL_NUMBER_0(value) (FUSES_SERIAL_NUMBER_0_Msk & ((value) << FUSES_SERIAL_NUMBER_0_Pos))
 
 #define FUSES_SERIAL_NUMBER_1_ADDR  (NVMCTRL_AUX3 + 68)
 #define FUSES_SERIAL_NUMBER_1_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 63:32 */
-#define FUSES_SERIAL_NUMBER_1_Msk   (_U(0xFFFFFFFF) << FUSES_SERIAL_NUMBER_1_Pos)
+#define FUSES_SERIAL_NUMBER_1_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_1_Pos)
 #define FUSES_SERIAL_NUMBER_1(value) (FUSES_SERIAL_NUMBER_1_Msk & ((value) << FUSES_SERIAL_NUMBER_1_Pos))
 
 #define FUSES_SERIAL_NUMBER_2_ADDR  (NVMCTRL_AUX3 + 72)
 #define FUSES_SERIAL_NUMBER_2_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 95:64 */
-#define FUSES_SERIAL_NUMBER_2_Msk   (_U(0xFFFFFFFF) << FUSES_SERIAL_NUMBER_2_Pos)
+#define FUSES_SERIAL_NUMBER_2_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_2_Pos)
 #define FUSES_SERIAL_NUMBER_2(value) (FUSES_SERIAL_NUMBER_2_Msk & ((value) << FUSES_SERIAL_NUMBER_2_Pos))
 
 #define FUSES_SERIAL_NUMBER_3_ADDR  (NVMCTRL_AUX3 + 12)
 #define FUSES_SERIAL_NUMBER_3_Pos   0            /**< \brief (NVMCTRL_AUX3) Serial Number word 3 */
-#define FUSES_SERIAL_NUMBER_3_Msk   (_U(0xFFFFFFFF) << FUSES_SERIAL_NUMBER_3_Pos)
+#define FUSES_SERIAL_NUMBER_3_Msk   (0xFFFFFFFFul << FUSES_SERIAL_NUMBER_3_Pos)
 #define FUSES_SERIAL_NUMBER_3(value) (FUSES_SERIAL_NUMBER_3_Msk & ((value) << FUSES_SERIAL_NUMBER_3_Pos))
 
 #define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
 #define NVMCTRL_FUSES_BOOTPROT_Pos  0            /**< \brief (NVMCTRL_USER) Bootloader Size */
-#define NVMCTRL_FUSES_BOOTPROT_Msk  (_U(0x7) << NVMCTRL_FUSES_BOOTPROT_Pos)
+#define NVMCTRL_FUSES_BOOTPROT_Msk  (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos)
 #define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
 
 #define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
 #define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4            /**< \brief (NVMCTRL_USER) EEPROM Size */
-#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (_U(0x7) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
+#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
 #define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))
 
+/* Compatible definition for previous driver (begin 1) */
+#define NVMCTRL_FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_HOT_ADC_VAL_Pos 20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
+#define NVMCTRL_FUSES_HOT_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)
+#define NVMCTRL_FUSES_HOT_ADC_VAL(value) ((NVMCTRL_FUSES_HOT_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)))
+
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define NVMCTRL_FUSES_HOT_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)
+#define NVMCTRL_FUSES_HOT_INT1V_VAL(value) ((NVMCTRL_FUSES_HOT_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)))
+
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos 20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)))
+
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos 12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)
+#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)))
+/* Compatible definition for previous driver (end 1) */
 #define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
 #define NVMCTRL_FUSES_REGION_LOCKS_Pos 16           /**< \brief (NVMCTRL_USER) NVM Region Locks */
-#define NVMCTRL_FUSES_REGION_LOCKS_Msk (_U(0xFFFF) << NVMCTRL_FUSES_REGION_LOCKS_Pos)
+#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos)
 #define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
 
+/* Compatible definition for previous driver (begin 2) */
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
+#define NVMCTRL_FUSES_ROOM_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)
+#define NVMCTRL_FUSES_ROOM_ADC_VAL(value) ((NVMCTRL_FUSES_ROOM_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos 24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)
+#define NVMCTRL_FUSES_ROOM_INT1V_VAL(value) ((NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)))
+
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)))
+
+#define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33USERLEVEL_Pos 8            /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define SYSCTRL_FUSES_BOD33USERLEVEL_Msk (0x3Fu << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)
+#define SYSCTRL_FUSES_BOD33USERLEVEL(value) ((SYSCTRL_FUSES_BOD33USERLEVEL_Msk & ((value) << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)))
+
+#define SYSCTRL_FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33_ACTION_Pos 15           /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define SYSCTRL_FUSES_BOD33_ACTION_Msk (0x3u << SYSCTRL_FUSES_BOD33_ACTION_Pos)
+#define SYSCTRL_FUSES_BOD33_ACTION(value) ((SYSCTRL_FUSES_BOD33_ACTION_Msk & ((value) << SYSCTRL_FUSES_BOD33_ACTION_Pos)))
+
+#define SYSCTRL_FUSES_BOD33_EN_ADDR NVMCTRL_USER
+#define SYSCTRL_FUSES_BOD33_EN_Pos  14           /**< \brief (NVMCTRL_USER) BOD33 Enable */
+#define SYSCTRL_FUSES_BOD33_EN_Msk  (0x1u << SYSCTRL_FUSES_BOD33_EN_Pos)
+
+#define SYSCTRL_FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4)
+#define SYSCTRL_FUSES_BOD33_HYST_Pos 8            /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define SYSCTRL_FUSES_BOD33_HYST_Msk (0x1u << SYSCTRL_FUSES_BOD33_HYST_Pos)
+
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos 26           /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk (0x3Fu << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)
+#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL(value) ((SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)))
+
+#define SYSCTRL_FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define SYSCTRL_FUSES_OSC32K_CAL_Pos 6            /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
+#define SYSCTRL_FUSES_OSC32K_CAL_Msk (0x7Fu << SYSCTRL_FUSES_OSC32K_CAL_Pos)
+#define SYSCTRL_FUSES_OSC32K_CAL(value) ((SYSCTRL_FUSES_OSC32K_CAL_Msk & ((value) << SYSCTRL_FUSES_OSC32K_CAL_Pos)))
+/* Compatible definition for previous driver (end 2) */
 #define USB_FUSES_TRANSN_ADDR       (NVMCTRL_OTP4 + 4)
 #define USB_FUSES_TRANSN_Pos        13           /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
-#define USB_FUSES_TRANSN_Msk        (_U(0x1F) << USB_FUSES_TRANSN_Pos)
+#define USB_FUSES_TRANSN_Msk        (0x1Ful << USB_FUSES_TRANSN_Pos)
 #define USB_FUSES_TRANSN(value)     (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
 
 #define USB_FUSES_TRANSP_ADDR       (NVMCTRL_OTP4 + 4)
 #define USB_FUSES_TRANSP_Pos        18           /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
-#define USB_FUSES_TRANSP_Msk        (_U(0x1F) << USB_FUSES_TRANSP_Pos)
+#define USB_FUSES_TRANSP_Msk        (0x1Ful << USB_FUSES_TRANSP_Pos)
 #define USB_FUSES_TRANSP(value)     (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
 
 #define USB_FUSES_TRIM_ADDR         (NVMCTRL_OTP4 + 4)
 #define USB_FUSES_TRIM_Pos          23           /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
-#define USB_FUSES_TRIM_Msk          (_U(0x7) << USB_FUSES_TRIM_Pos)
+#define USB_FUSES_TRIM_Msk          (0x7ul << USB_FUSES_TRIM_Pos)
 #define USB_FUSES_TRIM(value)       (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
 
 #define WDT_FUSES_ALWAYSON_ADDR     NVMCTRL_USER
 #define WDT_FUSES_ALWAYSON_Pos      26           /**< \brief (NVMCTRL_USER) WDT Always On */
-#define WDT_FUSES_ALWAYSON_Msk      (_U(0x1) << WDT_FUSES_ALWAYSON_Pos)
+#define WDT_FUSES_ALWAYSON_Msk      (0x1ul << WDT_FUSES_ALWAYSON_Pos)
 
 #define WDT_FUSES_ENABLE_ADDR       NVMCTRL_USER
 #define WDT_FUSES_ENABLE_Pos        25           /**< \brief (NVMCTRL_USER) WDT Enable */
-#define WDT_FUSES_ENABLE_Msk        (_U(0x1) << WDT_FUSES_ENABLE_Pos)
+#define WDT_FUSES_ENABLE_Msk        (0x1ul << WDT_FUSES_ENABLE_Pos)
 
 #define WDT_FUSES_EWOFFSET_ADDR     (NVMCTRL_USER + 4)
 #define WDT_FUSES_EWOFFSET_Pos      3            /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
-#define WDT_FUSES_EWOFFSET_Msk      (_U(0xF) << WDT_FUSES_EWOFFSET_Pos)
+#define WDT_FUSES_EWOFFSET_Msk      (0xFul << WDT_FUSES_EWOFFSET_Pos)
 #define WDT_FUSES_EWOFFSET(value)   (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
 
 #define WDT_FUSES_PER_ADDR          NVMCTRL_USER
 #define WDT_FUSES_PER_Pos           27           /**< \brief (NVMCTRL_USER) WDT Period */
-#define WDT_FUSES_PER_Msk           (_U(0xF) << WDT_FUSES_PER_Pos)
+#define WDT_FUSES_PER_Msk           (0xFul << WDT_FUSES_PER_Pos)
 #define WDT_FUSES_PER(value)        (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
 
 #define WDT_FUSES_WEN_ADDR          (NVMCTRL_USER + 4)
 #define WDT_FUSES_WEN_Pos           7            /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
-#define WDT_FUSES_WEN_Msk           (_U(0x1) << WDT_FUSES_WEN_Pos)
+#define WDT_FUSES_WEN_Msk           (0x1ul << WDT_FUSES_WEN_Pos)
 
 #define WDT_FUSES_WINDOW_0_ADDR     NVMCTRL_USER
 #define WDT_FUSES_WINDOW_0_Pos      31           /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
-#define WDT_FUSES_WINDOW_0_Msk      (_U(0x1) << WDT_FUSES_WINDOW_0_Pos)
+#define WDT_FUSES_WINDOW_0_Msk      (0x1ul << WDT_FUSES_WINDOW_0_Pos)
 
 #define WDT_FUSES_WINDOW_1_ADDR     (NVMCTRL_USER + 4)
 #define WDT_FUSES_WINDOW_1_Pos      0            /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
-#define WDT_FUSES_WINDOW_1_Msk      (_U(0x7) << WDT_FUSES_WINDOW_1_Pos)
+#define WDT_FUSES_WINDOW_1_Msk      (0x7ul << WDT_FUSES_WINDOW_1_Pos)
 #define WDT_FUSES_WINDOW_1(value)   (WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos))
 
 /*@}*/

asf/sam0/utils/cmsis/samd21/include/component/pac.h

@@ -3,24 +3,39 @@
  *
  * \brief Component description for PAC
  *
- * Copyright (c) 2017 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *
  * \asf_license_stop
  *
@@ -50,12 +65,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PAC_WPCLR_OFFSET            0x0          /**< \brief (PAC_WPCLR offset) Write Protection Clear */
-#define PAC_WPCLR_RESETVALUE        _U(0x00000000) /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */
+#define PAC_WPCLR_RESETVALUE        0x00000000ul /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */
 
 #define PAC_WPCLR_WP_Pos            1            /**< \brief (PAC_WPCLR) Write Protection Clear */
-#define PAC_WPCLR_WP_Msk            (_U(0x7FFFFFFF) << PAC_WPCLR_WP_Pos)
+#define PAC_WPCLR_WP_Msk            (0x7FFFFFFFul << PAC_WPCLR_WP_Pos)
 #define PAC_WPCLR_WP(value)         (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos))
-#define PAC_WPCLR_MASK              _U(0xFFFFFFFE) /**< \brief (PAC_WPCLR) MASK Register */
+#define PAC_WPCLR_MASK              0xFFFFFFFEul /**< \brief (PAC_WPCLR) MASK Register */
 
 /* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -69,12 +84,12 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PAC_WPSET_OFFSET            0x4          /**< \brief (PAC_WPSET offset) Write Protection Set */
-#define PAC_WPSET_RESETVALUE        _U(0x00000000) /**< \brief (PAC_WPSET reset_value) Write Protection Set */
+#define PAC_WPSET_RESETVALUE        0x00000000ul /**< \brief (PAC_WPSET reset_value) Write Protection Set */
 
 #define PAC_WPSET_WP_Pos            1            /**< \brief (PAC_WPSET) Write Protection Set */
-#define PAC_WPSET_WP_Msk            (_U(0x7FFFFFFF) << PAC_WPSET_WP_Pos)
+#define PAC_WPSET_WP_Msk            (0x7FFFFFFFul << PAC_WPSET_WP_Pos)
 #define PAC_WPSET_WP(value)         (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos))
-#define PAC_WPSET_MASK              _U(0xFFFFFFFE) /**< \brief (PAC_WPSET) MASK Register */
+#define PAC_WPSET_MASK              0xFFFFFFFEul /**< \brief (PAC_WPSET) MASK Register */
 
 /** \brief PAC hardware registers */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

asf/sam0/utils/cmsis/samd21/include/component/pm.h

@@ -3,24 +3,39 @@
  *
  * \brief Component description for PM
  *
- * Copyright (c) 2017 Atmel Corporation,
- *                    a wholly owned subsidiary of Microchip Technology Inc.
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
  *
  * \asf_license_start
  *
  * \page License
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *
  * \asf_license_stop
  *
@@ -46,9 +61,9 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_CTRL_OFFSET              0x00         /**< \brief (PM_CTRL offset) Control */
-#define PM_CTRL_RESETVALUE          _U(0x00)     /**< \brief (PM_CTRL reset_value) Control */
+#define PM_CTRL_RESETVALUE          0x00ul       /**< \brief (PM_CTRL reset_value) Control */
 
-#define PM_CTRL_MASK                _U(0x00)     /**< \brief (PM_CTRL) MASK Register */
+#define PM_CTRL_MASK                0x00ul       /**< \brief (PM_CTRL) MASK Register */
 
 /* -------- PM_SLEEP : (PM Offset: 0x01) (R/W  8) Sleep Mode -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -62,18 +77,18 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_SLEEP_OFFSET             0x01         /**< \brief (PM_SLEEP offset) Sleep Mode */
-#define PM_SLEEP_RESETVALUE         _U(0x00)     /**< \brief (PM_SLEEP reset_value) Sleep Mode */
+#define PM_SLEEP_RESETVALUE         0x00ul       /**< \brief (PM_SLEEP reset_value) Sleep Mode */
 
 #define PM_SLEEP_IDLE_Pos           0            /**< \brief (PM_SLEEP) Idle Mode Configuration */
-#define PM_SLEEP_IDLE_Msk           (_U(0x3) << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_Msk           (0x3ul << PM_SLEEP_IDLE_Pos)
 #define PM_SLEEP_IDLE(value)        (PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))
-#define   PM_SLEEP_IDLE_CPU_Val           _U(0x0)   /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
-#define   PM_SLEEP_IDLE_AHB_Val           _U(0x1)   /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
-#define   PM_SLEEP_IDLE_APB_Val           _U(0x2)   /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
+#define   PM_SLEEP_IDLE_CPU_Val           0x0ul  /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
+#define   PM_SLEEP_IDLE_AHB_Val           0x1ul  /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
+#define   PM_SLEEP_IDLE_APB_Val           0x2ul  /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
 #define PM_SLEEP_IDLE_CPU           (PM_SLEEP_IDLE_CPU_Val         << PM_SLEEP_IDLE_Pos)
 #define PM_SLEEP_IDLE_AHB           (PM_SLEEP_IDLE_AHB_Val         << PM_SLEEP_IDLE_Pos)
 #define PM_SLEEP_IDLE_APB           (PM_SLEEP_IDLE_APB_Val         << PM_SLEEP_IDLE_Pos)
-#define PM_SLEEP_MASK               _U(0x03)     /**< \brief (PM_SLEEP) MASK Register */
+#define PM_SLEEP_MASK               0x03ul       /**< \brief (PM_SLEEP) MASK Register */
 
 /* -------- PM_EXTCTRL : (PM Offset: 0x02) (R/W  8) External Reset Controller -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -87,11 +102,11 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_EXTCTRL_OFFSET           0x02         /**< \brief (PM_EXTCTRL offset) External Reset Controller */
-#define PM_EXTCTRL_RESETVALUE       _U(0x00)     /**< \brief (PM_EXTCTRL reset_value) External Reset Controller */
+#define PM_EXTCTRL_RESETVALUE       0x00ul       /**< \brief (PM_EXTCTRL reset_value) External Reset Controller */
 
 #define PM_EXTCTRL_SETDIS_Pos       0            /**< \brief (PM_EXTCTRL) External Reset Disable */
-#define PM_EXTCTRL_SETDIS           (_U(0x1) << PM_EXTCTRL_SETDIS_Pos)
-#define PM_EXTCTRL_MASK             _U(0x01)     /**< \brief (PM_EXTCTRL) MASK Register */
+#define PM_EXTCTRL_SETDIS           (0x1ul << PM_EXTCTRL_SETDIS_Pos)
+#define PM_EXTCTRL_MASK             0x01ul       /**< \brief (PM_EXTCTRL) MASK Register */
 
 /* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W  8) CPU Clock Select -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -105,19 +120,19 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_CPUSEL_OFFSET            0x08         /**< \brief (PM_CPUSEL offset) CPU Clock Select */
-#define PM_CPUSEL_RESETVALUE        _U(0x00)     /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
+#define PM_CPUSEL_RESETVALUE        0x00ul       /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
 
 #define PM_CPUSEL_CPUDIV_Pos        0            /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
-#define PM_CPUSEL_CPUDIV_Msk        (_U(0x7) << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_Msk        (0x7ul << PM_CPUSEL_CPUDIV_Pos)
 #define PM_CPUSEL_CPUDIV(value)     (PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))
-#define   PM_CPUSEL_CPUDIV_DIV1_Val       _U(0x0)   /**< \brief (PM_CPUSEL) Divide by 1 */
-#define   PM_CPUSEL_CPUDIV_DIV2_Val       _U(0x1)   /**< \brief (PM_CPUSEL) Divide by 2 */
-#define   PM_CPUSEL_CPUDIV_DIV4_Val       _U(0x2)   /**< \brief (PM_CPUSEL) Divide by 4 */
-#define   PM_CPUSEL_CPUDIV_DIV8_Val       _U(0x3)   /**< \brief (PM_CPUSEL) Divide by 8 */
-#define   PM_CPUSEL_CPUDIV_DIV16_Val      _U(0x4)   /**< \brief (PM_CPUSEL) Divide by 16 */
-#define   PM_CPUSEL_CPUDIV_DIV32_Val      _U(0x5)   /**< \brief (PM_CPUSEL) Divide by 32 */
-#define   PM_CPUSEL_CPUDIV_DIV64_Val      _U(0x6)   /**< \brief (PM_CPUSEL) Divide by 64 */
-#define   PM_CPUSEL_CPUDIV_DIV128_Val     _U(0x7)   /**< \brief (PM_CPUSEL) Divide by 128 */
+#define   PM_CPUSEL_CPUDIV_DIV1_Val       0x0ul  /**< \brief (PM_CPUSEL) Divide by 1 */
+#define   PM_CPUSEL_CPUDIV_DIV2_Val       0x1ul  /**< \brief (PM_CPUSEL) Divide by 2 */
+#define   PM_CPUSEL_CPUDIV_DIV4_Val       0x2ul  /**< \brief (PM_CPUSEL) Divide by 4 */
+#define   PM_CPUSEL_CPUDIV_DIV8_Val       0x3ul  /**< \brief (PM_CPUSEL) Divide by 8 */
+#define   PM_CPUSEL_CPUDIV_DIV16_Val      0x4ul  /**< \brief (PM_CPUSEL) Divide by 16 */
+#define   PM_CPUSEL_CPUDIV_DIV32_Val      0x5ul  /**< \brief (PM_CPUSEL) Divide by 32 */
+#define   PM_CPUSEL_CPUDIV_DIV64_Val      0x6ul  /**< \brief (PM_CPUSEL) Divide by 64 */
+#define   PM_CPUSEL_CPUDIV_DIV128_Val     0x7ul  /**< \brief (PM_CPUSEL) Divide by 128 */
 #define PM_CPUSEL_CPUDIV_DIV1       (PM_CPUSEL_CPUDIV_DIV1_Val     << PM_CPUSEL_CPUDIV_Pos)
 #define PM_CPUSEL_CPUDIV_DIV2       (PM_CPUSEL_CPUDIV_DIV2_Val     << PM_CPUSEL_CPUDIV_Pos)
 #define PM_CPUSEL_CPUDIV_DIV4       (PM_CPUSEL_CPUDIV_DIV4_Val     << PM_CPUSEL_CPUDIV_Pos)
@@ -126,7 +141,7 @@ typedef union {
 #define PM_CPUSEL_CPUDIV_DIV32      (PM_CPUSEL_CPUDIV_DIV32_Val    << PM_CPUSEL_CPUDIV_Pos)
 #define PM_CPUSEL_CPUDIV_DIV64      (PM_CPUSEL_CPUDIV_DIV64_Val    << PM_CPUSEL_CPUDIV_Pos)
 #define PM_CPUSEL_CPUDIV_DIV128     (PM_CPUSEL_CPUDIV_DIV128_Val   << PM_CPUSEL_CPUDIV_Pos)
-#define PM_CPUSEL_MASK              _U(0x07)     /**< \brief (PM_CPUSEL) MASK Register */
+#define PM_CPUSEL_MASK              0x07ul       /**< \brief (PM_CPUSEL) MASK Register */
 
 /* -------- PM_APBASEL : (PM Offset: 0x09) (R/W  8) APBA Clock Select -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -140,19 +155,19 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_APBASEL_OFFSET           0x09         /**< \brief (PM_APBASEL offset) APBA Clock Select */
-#define PM_APBASEL_RESETVALUE       _U(0x00)     /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
+#define PM_APBASEL_RESETVALUE       0x00ul       /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
 
 #define PM_APBASEL_APBADIV_Pos      0            /**< \brief (PM_APBASEL) APBA Prescaler Selection */
-#define PM_APBASEL_APBADIV_Msk      (_U(0x7) << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_Msk      (0x7ul << PM_APBASEL_APBADIV_Pos)
 #define PM_APBASEL_APBADIV(value)   (PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))
-#define   PM_APBASEL_APBADIV_DIV1_Val     _U(0x0)   /**< \brief (PM_APBASEL) Divide by 1 */
-#define   PM_APBASEL_APBADIV_DIV2_Val     _U(0x1)   /**< \brief (PM_APBASEL) Divide by 2 */
-#define   PM_APBASEL_APBADIV_DIV4_Val     _U(0x2)   /**< \brief (PM_APBASEL) Divide by 4 */
-#define   PM_APBASEL_APBADIV_DIV8_Val     _U(0x3)   /**< \brief (PM_APBASEL) Divide by 8 */
-#define   PM_APBASEL_APBADIV_DIV16_Val    _U(0x4)   /**< \brief (PM_APBASEL) Divide by 16 */
-#define   PM_APBASEL_APBADIV_DIV32_Val    _U(0x5)   /**< \brief (PM_APBASEL) Divide by 32 */
-#define   PM_APBASEL_APBADIV_DIV64_Val    _U(0x6)   /**< \brief (PM_APBASEL) Divide by 64 */
-#define   PM_APBASEL_APBADIV_DIV128_Val   _U(0x7)   /**< \brief (PM_APBASEL) Divide by 128 */
+#define   PM_APBASEL_APBADIV_DIV1_Val     0x0ul  /**< \brief (PM_APBASEL) Divide by 1 */
+#define   PM_APBASEL_APBADIV_DIV2_Val     0x1ul  /**< \brief (PM_APBASEL) Divide by 2 */
+#define   PM_APBASEL_APBADIV_DIV4_Val     0x2ul  /**< \brief (PM_APBASEL) Divide by 4 */
+#define   PM_APBASEL_APBADIV_DIV8_Val     0x3ul  /**< \brief (PM_APBASEL) Divide by 8 */
+#define   PM_APBASEL_APBADIV_DIV16_Val    0x4ul  /**< \brief (PM_APBASEL) Divide by 16 */
+#define   PM_APBASEL_APBADIV_DIV32_Val    0x5ul  /**< \brief (PM_APBASEL) Divide by 32 */
+#define   PM_APBASEL_APBADIV_DIV64_Val    0x6ul  /**< \brief (PM_APBASEL) Divide by 64 */
+#define   PM_APBASEL_APBADIV_DIV128_Val   0x7ul  /**< \brief (PM_APBASEL) Divide by 128 */
 #define PM_APBASEL_APBADIV_DIV1     (PM_APBASEL_APBADIV_DIV1_Val   << PM_APBASEL_APBADIV_Pos)
 #define PM_APBASEL_APBADIV_DIV2     (PM_APBASEL_APBADIV_DIV2_Val   << PM_APBASEL_APBADIV_Pos)
 #define PM_APBASEL_APBADIV_DIV4     (PM_APBASEL_APBADIV_DIV4_Val   << PM_APBASEL_APBADIV_Pos)
@@ -161,7 +176,7 @@ typedef union {
 #define PM_APBASEL_APBADIV_DIV32    (PM_APBASEL_APBADIV_DIV32_Val  << PM_APBASEL_APBADIV_Pos)
 #define PM_APBASEL_APBADIV_DIV64    (PM_APBASEL_APBADIV_DIV64_Val  << PM_APBASEL_APBADIV_Pos)
 #define PM_APBASEL_APBADIV_DIV128   (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
-#define PM_APBASEL_MASK             _U(0x07)     /**< \brief (PM_APBASEL) MASK Register */
+#define PM_APBASEL_MASK             0x07ul       /**< \brief (PM_APBASEL) MASK Register */
 
 /* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W  8) APBB Clock Select -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -175,19 +190,19 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_APBBSEL_OFFSET           0x0A         /**< \brief (PM_APBBSEL offset) APBB Clock Select */
-#define PM_APBBSEL_RESETVALUE       _U(0x00)     /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
+#define PM_APBBSEL_RESETVALUE       0x00ul       /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
 
 #define PM_APBBSEL_APBBDIV_Pos      0            /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
-#define PM_APBBSEL_APBBDIV_Msk      (_U(0x7) << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_Msk      (0x7ul << PM_APBBSEL_APBBDIV_Pos)
 #define PM_APBBSEL_APBBDIV(value)   (PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))
-#define   PM_APBBSEL_APBBDIV_DIV1_Val     _U(0x0)   /**< \brief (PM_APBBSEL) Divide by 1 */
-#define   PM_APBBSEL_APBBDIV_DIV2_Val     _U(0x1)   /**< \brief (PM_APBBSEL) Divide by 2 */
-#define   PM_APBBSEL_APBBDIV_DIV4_Val     _U(0x2)   /**< \brief (PM_APBBSEL) Divide by 4 */
-#define   PM_APBBSEL_APBBDIV_DIV8_Val     _U(0x3)   /**< \brief (PM_APBBSEL) Divide by 8 */
-#define   PM_APBBSEL_APBBDIV_DIV16_Val    _U(0x4)   /**< \brief (PM_APBBSEL) Divide by 16 */
-#define   PM_APBBSEL_APBBDIV_DIV32_Val    _U(0x5)   /**< \brief (PM_APBBSEL) Divide by 32 */
-#define   PM_APBBSEL_APBBDIV_DIV64_Val    _U(0x6)   /**< \brief (PM_APBBSEL) Divide by 64 */
-#define   PM_APBBSEL_APBBDIV_DIV128_Val   _U(0x7)   /**< \brief (PM_APBBSEL) Divide by 128 */
+#define   PM_APBBSEL_APBBDIV_DIV1_Val     0x0ul  /**< \brief (PM_APBBSEL) Divide by 1 */
+#define   PM_APBBSEL_APBBDIV_DIV2_Val     0x1ul  /**< \brief (PM_APBBSEL) Divide by 2 */
+#define   PM_APBBSEL_APBBDIV_DIV4_Val     0x2ul  /**< \brief (PM_APBBSEL) Divide by 4 */
+#define   PM_APBBSEL_APBBDIV_DIV8_Val     0x3ul  /**< \brief (PM_APBBSEL) Divide by 8 */
+#define   PM_APBBSEL_APBBDIV_DIV16_Val    0x4ul  /**< \brief (PM_APBBSEL) Divide by 16 */
+#define   PM_APBBSEL_APBBDIV_DIV32_Val    0x5ul  /**< \brief (PM_APBBSEL) Divide by 32 */
+#define   PM_APBBSEL_APBBDIV_DIV64_Val    0x6ul  /**< \brief (PM_APBBSEL) Divide by 64 */
+#define   PM_APBBSEL_APBBDIV_DIV128_Val   0x7ul  /**< \brief (PM_APBBSEL) Divide by 128 */
 #define PM_APBBSEL_APBBDIV_DIV1     (PM_APBBSEL_APBBDIV_DIV1_Val   << PM_APBBSEL_APBBDIV_Pos)
 #define PM_APBBSEL_APBBDIV_DIV2     (PM_APBBSEL_APBBDIV_DIV2_Val   << PM_APBBSEL_APBBDIV_Pos)
 #define PM_APBBSEL_APBBDIV_DIV4     (PM_APBBSEL_APBBDIV_DIV4_Val   << PM_APBBSEL_APBBDIV_Pos)
@@ -196,7 +211,7 @@ typedef union {
 #define PM_APBBSEL_APBBDIV_DIV32    (PM_APBBSEL_APBBDIV_DIV32_Val  << PM_APBBSEL_APBBDIV_Pos)
 #define PM_APBBSEL_APBBDIV_DIV64    (PM_APBBSEL_APBBDIV_DIV64_Val  << PM_APBBSEL_APBBDIV_Pos)
 #define PM_APBBSEL_APBBDIV_DIV128   (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
-#define PM_APBBSEL_MASK             _U(0x07)     /**< \brief (PM_APBBSEL) MASK Register */
+#define PM_APBBSEL_MASK             0x07ul       /**< \brief (PM_APBBSEL) MASK Register */
 
 /* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W  8) APBC Clock Select -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -210,19 +225,19 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_APBCSEL_OFFSET           0x0B         /**< \brief (PM_APBCSEL offset) APBC Clock Select */
-#define PM_APBCSEL_RESETVALUE       _U(0x00)     /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
+#define PM_APBCSEL_RESETVALUE       0x00ul       /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
 
 #define PM_APBCSEL_APBCDIV_Pos      0            /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
-#define PM_APBCSEL_APBCDIV_Msk      (_U(0x7) << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_Msk      (0x7ul << PM_APBCSEL_APBCDIV_Pos)
 #define PM_APBCSEL_APBCDIV(value)   (PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))
-#define   PM_APBCSEL_APBCDIV_DIV1_Val     _U(0x0)   /**< \brief (PM_APBCSEL) Divide by 1 */
-#define   PM_APBCSEL_APBCDIV_DIV2_Val     _U(0x1)   /**< \brief (PM_APBCSEL) Divide by 2 */
-#define   PM_APBCSEL_APBCDIV_DIV4_Val     _U(0x2)   /**< \brief (PM_APBCSEL) Divide by 4 */
-#define   PM_APBCSEL_APBCDIV_DIV8_Val     _U(0x3)   /**< \brief (PM_APBCSEL) Divide by 8 */
-#define   PM_APBCSEL_APBCDIV_DIV16_Val    _U(0x4)   /**< \brief (PM_APBCSEL) Divide by 16 */
-#define   PM_APBCSEL_APBCDIV_DIV32_Val    _U(0x5)   /**< \brief (PM_APBCSEL) Divide by 32 */
-#define   PM_APBCSEL_APBCDIV_DIV64_Val    _U(0x6)   /**< \brief (PM_APBCSEL) Divide by 64 */
-#define   PM_APBCSEL_APBCDIV_DIV128_Val   _U(0x7)   /**< \brief (PM_APBCSEL) Divide by 128 */
+#define   PM_APBCSEL_APBCDIV_DIV1_Val     0x0ul  /**< \brief (PM_APBCSEL) Divide by 1 */
+#define   PM_APBCSEL_APBCDIV_DIV2_Val     0x1ul  /**< \brief (PM_APBCSEL) Divide by 2 */
+#define   PM_APBCSEL_APBCDIV_DIV4_Val     0x2ul  /**< \brief (PM_APBCSEL) Divide by 4 */
+#define   PM_APBCSEL_APBCDIV_DIV8_Val     0x3ul  /**< \brief (PM_APBCSEL) Divide by 8 */
+#define   PM_APBCSEL_APBCDIV_DIV16_Val    0x4ul  /**< \brief (PM_APBCSEL) Divide by 16 */
+#define   PM_APBCSEL_APBCDIV_DIV32_Val    0x5ul  /**< \brief (PM_APBCSEL) Divide by 32 */
+#define   PM_APBCSEL_APBCDIV_DIV64_Val    0x6ul  /**< \brief (PM_APBCSEL) Divide by 64 */
+#define   PM_APBCSEL_APBCDIV_DIV128_Val   0x7ul  /**< \brief (PM_APBCSEL) Divide by 128 */
 #define PM_APBCSEL_APBCDIV_DIV1     (PM_APBCSEL_APBCDIV_DIV1_Val   << PM_APBCSEL_APBCDIV_Pos)
 #define PM_APBCSEL_APBCDIV_DIV2     (PM_APBCSEL_APBCDIV_DIV2_Val   << PM_APBCSEL_APBCDIV_Pos)
 #define PM_APBCSEL_APBCDIV_DIV4     (PM_APBCSEL_APBCDIV_DIV4_Val   << PM_APBCSEL_APBCDIV_Pos)
@@ -231,7 +246,7 @@ typedef union {
 #define PM_APBCSEL_APBCDIV_DIV32    (PM_APBCSEL_APBCDIV_DIV32_Val  << PM_APBCSEL_APBCDIV_Pos)
 #define PM_APBCSEL_APBCDIV_DIV64    (PM_APBCSEL_APBCDIV_DIV64_Val  << PM_APBCSEL_APBCDIV_Pos)
 #define PM_APBCSEL_APBCDIV_DIV128   (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
-#define PM_APBCSEL_MASK             _U(0x07)     /**< \brief (PM_APBCSEL) MASK Register */
+#define PM_APBCSEL_MASK             0x07ul       /**< \brief (PM_APBCSEL) MASK Register */
 
 /* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -251,23 +266,23 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_AHBMASK_OFFSET           0x14         /**< \brief (PM_AHBMASK offset) AHB Mask */
-#define PM_AHBMASK_RESETVALUE       _U(0x0000007F) /**< \brief (PM_AHBMASK reset_value) AHB Mask */
+#define PM_AHBMASK_RESETVALUE       0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */
 
 #define PM_AHBMASK_HPB0_Pos         0            /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
-#define PM_AHBMASK_HPB0             (_U(0x1) << PM_AHBMASK_HPB0_Pos)
+#define PM_AHBMASK_HPB0             (0x1ul << PM_AHBMASK_HPB0_Pos)
 #define PM_AHBMASK_HPB1_Pos         1            /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
-#define PM_AHBMASK_HPB1             (_U(0x1) << PM_AHBMASK_HPB1_Pos)
+#define PM_AHBMASK_HPB1             (0x1ul << PM_AHBMASK_HPB1_Pos)
 #define PM_AHBMASK_HPB2_Pos         2            /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
-#define PM_AHBMASK_HPB2             (_U(0x1) << PM_AHBMASK_HPB2_Pos)
+#define PM_AHBMASK_HPB2             (0x1ul << PM_AHBMASK_HPB2_Pos)
 #define PM_AHBMASK_DSU_Pos          3            /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
-#define PM_AHBMASK_DSU              (_U(0x1) << PM_AHBMASK_DSU_Pos)
+#define PM_AHBMASK_DSU              (0x1ul << PM_AHBMASK_DSU_Pos)
 #define PM_AHBMASK_NVMCTRL_Pos      4            /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
-#define PM_AHBMASK_NVMCTRL          (_U(0x1) << PM_AHBMASK_NVMCTRL_Pos)
+#define PM_AHBMASK_NVMCTRL          (0x1ul << PM_AHBMASK_NVMCTRL_Pos)
 #define PM_AHBMASK_DMAC_Pos         5            /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */
-#define PM_AHBMASK_DMAC             (_U(0x1) << PM_AHBMASK_DMAC_Pos)
+#define PM_AHBMASK_DMAC             (0x1ul << PM_AHBMASK_DMAC_Pos)
 #define PM_AHBMASK_USB_Pos          6            /**< \brief (PM_AHBMASK) USB AHB Clock Mask */
-#define PM_AHBMASK_USB              (_U(0x1) << PM_AHBMASK_USB_Pos)
-#define PM_AHBMASK_MASK             _U(0x0000007F) /**< \brief (PM_AHBMASK) MASK Register */
+#define PM_AHBMASK_USB              (0x1ul << PM_AHBMASK_USB_Pos)
+#define PM_AHBMASK_MASK             0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */
 
 /* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -287,23 +302,23 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_APBAMASK_OFFSET          0x18         /**< \brief (PM_APBAMASK offset) APBA Mask */
-#define PM_APBAMASK_RESETVALUE      _U(0x0000007F) /**< \brief (PM_APBAMASK reset_value) APBA Mask */
+#define PM_APBAMASK_RESETVALUE      0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */
 
 #define PM_APBAMASK_PAC0_Pos        0            /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
-#define PM_APBAMASK_PAC0            (_U(0x1) << PM_APBAMASK_PAC0_Pos)
+#define PM_APBAMASK_PAC0            (0x1ul << PM_APBAMASK_PAC0_Pos)
 #define PM_APBAMASK_PM_Pos          1            /**< \brief (PM_APBAMASK) PM APB Clock Enable */
-#define PM_APBAMASK_PM              (_U(0x1) << PM_APBAMASK_PM_Pos)
+#define PM_APBAMASK_PM              (0x1ul << PM_APBAMASK_PM_Pos)
 #define PM_APBAMASK_SYSCTRL_Pos     2            /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
-#define PM_APBAMASK_SYSCTRL         (_U(0x1) << PM_APBAMASK_SYSCTRL_Pos)
+#define PM_APBAMASK_SYSCTRL         (0x1ul << PM_APBAMASK_SYSCTRL_Pos)
 #define PM_APBAMASK_GCLK_Pos        3            /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
-#define PM_APBAMASK_GCLK            (_U(0x1) << PM_APBAMASK_GCLK_Pos)
+#define PM_APBAMASK_GCLK            (0x1ul << PM_APBAMASK_GCLK_Pos)
 #define PM_APBAMASK_WDT_Pos         4            /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
-#define PM_APBAMASK_WDT             (_U(0x1) << PM_APBAMASK_WDT_Pos)
+#define PM_APBAMASK_WDT             (0x1ul << PM_APBAMASK_WDT_Pos)
 #define PM_APBAMASK_RTC_Pos         5            /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
-#define PM_APBAMASK_RTC             (_U(0x1) << PM_APBAMASK_RTC_Pos)
+#define PM_APBAMASK_RTC             (0x1ul << PM_APBAMASK_RTC_Pos)
 #define PM_APBAMASK_EIC_Pos         6            /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
-#define PM_APBAMASK_EIC             (_U(0x1) << PM_APBAMASK_EIC_Pos)
-#define PM_APBAMASK_MASK            _U(0x0000007F) /**< \brief (PM_APBAMASK) MASK Register */
+#define PM_APBAMASK_EIC             (0x1ul << PM_APBAMASK_EIC_Pos)
+#define PM_APBAMASK_MASK            0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */
 
 /* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -323,23 +338,23 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_APBBMASK_OFFSET          0x1C         /**< \brief (PM_APBBMASK offset) APBB Mask */
-#define PM_APBBMASK_RESETVALUE      _U(0x0000007F) /**< \brief (PM_APBBMASK reset_value) APBB Mask */
+#define PM_APBBMASK_RESETVALUE      0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */
 
 #define PM_APBBMASK_PAC1_Pos        0            /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
-#define PM_APBBMASK_PAC1            (_U(0x1) << PM_APBBMASK_PAC1_Pos)
+#define PM_APBBMASK_PAC1            (0x1ul << PM_APBBMASK_PAC1_Pos)
 #define PM_APBBMASK_DSU_Pos         1            /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
-#define PM_APBBMASK_DSU             (_U(0x1) << PM_APBBMASK_DSU_Pos)
+#define PM_APBBMASK_DSU             (0x1ul << PM_APBBMASK_DSU_Pos)
 #define PM_APBBMASK_NVMCTRL_Pos     2            /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
-#define PM_APBBMASK_NVMCTRL         (_U(0x1) << PM_APBBMASK_NVMCTRL_Pos)
+#define PM_APBBMASK_NVMCTRL         (0x1ul << PM_APBBMASK_NVMCTRL_Pos)
 #define PM_APBBMASK_PORT_Pos        3            /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
-#define PM_APBBMASK_PORT            (_U(0x1) << PM_APBBMASK_PORT_Pos)
+#define PM_APBBMASK_PORT            (0x1ul << PM_APBBMASK_PORT_Pos)
 #define PM_APBBMASK_DMAC_Pos        4            /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
-#define PM_APBBMASK_DMAC            (_U(0x1) << PM_APBBMASK_DMAC_Pos)
+#define PM_APBBMASK_DMAC            (0x1ul << PM_APBBMASK_DMAC_Pos)
 #define PM_APBBMASK_USB_Pos         5            /**< \brief (PM_APBBMASK) USB APB Clock Enable */
-#define PM_APBBMASK_USB             (_U(0x1) << PM_APBBMASK_USB_Pos)
+#define PM_APBBMASK_USB             (0x1ul << PM_APBBMASK_USB_Pos)
 #define PM_APBBMASK_HMATRIX_Pos     6            /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */
-#define PM_APBBMASK_HMATRIX         (_U(0x1) << PM_APBBMASK_HMATRIX_Pos)
-#define PM_APBBMASK_MASK            _U(0x0000007F) /**< \brief (PM_APBBMASK) MASK Register */
+#define PM_APBBMASK_HMATRIX         (0x1ul << PM_APBBMASK_HMATRIX_Pos)
+#define PM_APBBMASK_MASK            0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */
 
 /* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -374,53 +389,53 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_APBCMASK_OFFSET          0x20         /**< \brief (PM_APBCMASK offset) APBC Mask */
-#define PM_APBCMASK_RESETVALUE      _U(0x00010000) /**< \brief (PM_APBCMASK reset_value) APBC Mask */
+#define PM_APBCMASK_RESETVALUE      0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */
 
 #define PM_APBCMASK_PAC2_Pos        0            /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
-#define PM_APBCMASK_PAC2            (_U(0x1) << PM_APBCMASK_PAC2_Pos)
+#define PM_APBCMASK_PAC2            (0x1ul << PM_APBCMASK_PAC2_Pos)
 #define PM_APBCMASK_EVSYS_Pos       1            /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
-#define PM_APBCMASK_EVSYS           (_U(0x1) << PM_APBCMASK_EVSYS_Pos)
+#define PM_APBCMASK_EVSYS           (0x1ul << PM_APBCMASK_EVSYS_Pos)
 #define PM_APBCMASK_SERCOM0_Pos     2            /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
-#define PM_APBCMASK_SERCOM0         (_U(0x1) << PM_APBCMASK_SERCOM0_Pos)
+#define PM_APBCMASK_SERCOM0         (0x1ul << PM_APBCMASK_SERCOM0_Pos)
 #define PM_APBCMASK_SERCOM1_Pos     3            /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
-#define PM_APBCMASK_SERCOM1         (_U(0x1) << PM_APBCMASK_SERCOM1_Pos)
+#define PM_APBCMASK_SERCOM1         (0x1ul << PM_APBCMASK_SERCOM1_Pos)
 #define PM_APBCMASK_SERCOM2_Pos     4            /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
-#define PM_APBCMASK_SERCOM2         (_U(0x1) << PM_APBCMASK_SERCOM2_Pos)
+#define PM_APBCMASK_SERCOM2         (0x1ul << PM_APBCMASK_SERCOM2_Pos)
 #define PM_APBCMASK_SERCOM3_Pos     5            /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
-#define PM_APBCMASK_SERCOM3         (_U(0x1) << PM_APBCMASK_SERCOM3_Pos)
+#define PM_APBCMASK_SERCOM3         (0x1ul << PM_APBCMASK_SERCOM3_Pos)
 #define PM_APBCMASK_SERCOM4_Pos     6            /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
-#define PM_APBCMASK_SERCOM4         (_U(0x1) << PM_APBCMASK_SERCOM4_Pos)
+#define PM_APBCMASK_SERCOM4         (0x1ul << PM_APBCMASK_SERCOM4_Pos)
 #define PM_APBCMASK_SERCOM5_Pos     7            /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
-#define PM_APBCMASK_SERCOM5         (_U(0x1) << PM_APBCMASK_SERCOM5_Pos)
+#define PM_APBCMASK_SERCOM5         (0x1ul << PM_APBCMASK_SERCOM5_Pos)
 #define PM_APBCMASK_TCC0_Pos        8            /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
-#define PM_APBCMASK_TCC0            (_U(0x1) << PM_APBCMASK_TCC0_Pos)
+#define PM_APBCMASK_TCC0            (0x1ul << PM_APBCMASK_TCC0_Pos)
 #define PM_APBCMASK_TCC1_Pos        9            /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
-#define PM_APBCMASK_TCC1            (_U(0x1) << PM_APBCMASK_TCC1_Pos)
+#define PM_APBCMASK_TCC1            (0x1ul << PM_APBCMASK_TCC1_Pos)
 #define PM_APBCMASK_TCC2_Pos        10           /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
-#define PM_APBCMASK_TCC2            (_U(0x1) << PM_APBCMASK_TCC2_Pos)
+#define PM_APBCMASK_TCC2            (0x1ul << PM_APBCMASK_TCC2_Pos)
 #define PM_APBCMASK_TC3_Pos         11           /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
-#define PM_APBCMASK_TC3             (_U(0x1) << PM_APBCMASK_TC3_Pos)
+#define PM_APBCMASK_TC3             (0x1ul << PM_APBCMASK_TC3_Pos)
 #define PM_APBCMASK_TC4_Pos         12           /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
-#define PM_APBCMASK_TC4             (_U(0x1) << PM_APBCMASK_TC4_Pos)
+#define PM_APBCMASK_TC4             (0x1ul << PM_APBCMASK_TC4_Pos)
 #define PM_APBCMASK_TC5_Pos         13           /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
-#define PM_APBCMASK_TC5             (_U(0x1) << PM_APBCMASK_TC5_Pos)
+#define PM_APBCMASK_TC5             (0x1ul << PM_APBCMASK_TC5_Pos)
 #define PM_APBCMASK_TC6_Pos         14           /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
-#define PM_APBCMASK_TC6             (_U(0x1) << PM_APBCMASK_TC6_Pos)
+#define PM_APBCMASK_TC6             (0x1ul << PM_APBCMASK_TC6_Pos)
 #define PM_APBCMASK_TC7_Pos         15           /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
-#define PM_APBCMASK_TC7             (_U(0x1) << PM_APBCMASK_TC7_Pos)
+#define PM_APBCMASK_TC7             (0x1ul << PM_APBCMASK_TC7_Pos)
 #define PM_APBCMASK_ADC_Pos         16           /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
-#define PM_APBCMASK_ADC             (_U(0x1) << PM_APBCMASK_ADC_Pos)
+#define PM_APBCMASK_ADC             (0x1ul << PM_APBCMASK_ADC_Pos)
 #define PM_APBCMASK_AC_Pos          17           /**< \brief (PM_APBCMASK) AC APB Clock Enable */
-#define PM_APBCMASK_AC              (_U(0x1) << PM_APBCMASK_AC_Pos)
+#define PM_APBCMASK_AC              (0x1ul << PM_APBCMASK_AC_Pos)
 #define PM_APBCMASK_DAC_Pos         18           /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
-#define PM_APBCMASK_DAC             (_U(0x1) << PM_APBCMASK_DAC_Pos)
+#define PM_APBCMASK_DAC             (0x1ul << PM_APBCMASK_DAC_Pos)
 #define PM_APBCMASK_PTC_Pos         19           /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
-#define PM_APBCMASK_PTC             (_U(0x1) << PM_APBCMASK_PTC_Pos)
+#define PM_APBCMASK_PTC             (0x1ul << PM_APBCMASK_PTC_Pos)
 #define PM_APBCMASK_I2S_Pos         20           /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
-#define PM_APBCMASK_I2S             (_U(0x1) << PM_APBCMASK_I2S_Pos)
+#define PM_APBCMASK_I2S             (0x1ul << PM_APBCMASK_I2S_Pos)
 #define PM_APBCMASK_AC1_Pos         21           /**< \brief (PM_APBCMASK) AC1 APB Clock Enable */
-#define PM_APBCMASK_AC1             (_U(0x1) << PM_APBCMASK_AC1_Pos)
-#define PM_APBCMASK_MASK            _U(0x003FFFFF) /**< \brief (PM_APBCMASK) MASK Register */
+#define PM_APBCMASK_AC1             (0x1ul << PM_APBCMASK_AC1_Pos)
+#define PM_APBCMASK_MASK            0x003FFFFFul /**< \brief (PM_APBCMASK) MASK Register */
 
 /* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W  8) Interrupt Enable Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -434,11 +449,11 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_INTENCLR_OFFSET          0x34         /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
-#define PM_INTENCLR_RESETVALUE      _U(0x00)     /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
+#define PM_INTENCLR_RESETVALUE      0x00ul       /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
 
 #define PM_INTENCLR_CKRDY_Pos       0            /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
-#define PM_INTENCLR_CKRDY           (_U(0x1) << PM_INTENCLR_CKRDY_Pos)
-#define PM_INTENCLR_MASK            _U(0x01)     /**< \brief (PM_INTENCLR) MASK Register */
+#define PM_INTENCLR_CKRDY           (0x1ul << PM_INTENCLR_CKRDY_Pos)
+#define PM_INTENCLR_MASK            0x01ul       /**< \brief (PM_INTENCLR) MASK Register */
 
 /* -------- PM_INTENSET : (PM Offset: 0x35) (R/W  8) Interrupt Enable Set -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -452,11 +467,11 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_INTENSET_OFFSET          0x35         /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
-#define PM_INTENSET_RESETVALUE      _U(0x00)     /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
+#define PM_INTENSET_RESETVALUE      0x00ul       /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
 
 #define PM_INTENSET_CKRDY_Pos       0            /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
-#define PM_INTENSET_CKRDY           (_U(0x1) << PM_INTENSET_CKRDY_Pos)
-#define PM_INTENSET_MASK            _U(0x01)     /**< \brief (PM_INTENSET) MASK Register */
+#define PM_INTENSET_CKRDY           (0x1ul << PM_INTENSET_CKRDY_Pos)
+#define PM_INTENSET_MASK            0x01ul       /**< \brief (PM_INTENSET) MASK Register */
 
 /* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W  8) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -470,11 +485,11 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_INTFLAG_OFFSET           0x36         /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
-#define PM_INTFLAG_RESETVALUE       _U(0x00)     /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
+#define PM_INTFLAG_RESETVALUE       0x00ul       /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
 
 #define PM_INTFLAG_CKRDY_Pos        0            /**< \brief (PM_INTFLAG) Clock Ready */
-#define PM_INTFLAG_CKRDY            (_U(0x1) << PM_INTFLAG_CKRDY_Pos)
-#define PM_INTFLAG_MASK             _U(0x01)     /**< \brief (PM_INTFLAG) MASK Register */
+#define PM_INTFLAG_CKRDY            (0x1ul << PM_INTFLAG_CKRDY_Pos)
+#define PM_INTFLAG_MASK             0x01ul       /**< \brief (PM_INTFLAG) MASK Register */
 
 /* -------- PM_RCAUSE : (PM Offset: 0x38) (R/   8) Reset Cause -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -494,21 +509,21 @@ typedef union {
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 #define PM_RCAUSE_OFFSET            0x38         /**< \brief (PM_RCAUSE offset) Reset Cause */
-#define PM_RCAUSE_RESETVALUE        _U(0x01)     /**< \brief (PM_RCAUSE reset_value) Reset Cause */
+#define PM_RCAUSE_RESETVALUE        0x01ul       /**< \brief (PM_RCAUSE reset_value) Reset Cause */
 
 #define PM_RCAUSE_POR_Pos           0            /**< \brief (PM_RCAUSE) Power On Reset */
-#define PM_RCAUSE_POR               (_U(0x1) << PM_RCAUSE_POR_Pos)
+#define PM_RCAUSE_POR               (0x1ul << PM_RCAUSE_POR_Pos)
 #define PM_RCAUSE_BOD12_Pos         1            /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
-#define PM_RCAUSE_BOD12             (_U(0x1) << PM_RCAUSE_BOD12_Pos)
+#define PM_RCAUSE_BOD12             (0x1ul << PM_RCAUSE_BOD12_Pos)
 #define PM_RCAUSE_BOD33_Pos         2            /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
-#define PM_RCAUSE_BOD33             (_U(0x1) << PM_RCAUSE_BOD33_Pos)
+#define PM_RCAUSE_BOD33             (0x1ul << PM_RCAUSE_BOD33_Pos)
 #define PM_RCAUSE_EXT_Pos           4            /**< \brief (PM_RCAUSE) External Reset */
-#define PM_RCAUSE_EXT               (_U(0x1) << PM_RCAUSE_EXT_Pos)
+#define PM_RCAUSE_EXT               (0x1ul << PM_RCAUSE_EXT_Pos)
 #define PM_RCAUSE_WDT_Pos           5            /**< \brief (PM_RCAUSE) Watchdog Reset */
-#define PM_RCAUSE_WDT               (_U(0x1) << PM_RCAUSE_WDT_Pos)
+#define PM_RCAUSE_WDT               (0x1ul << PM_RCAUSE_WDT_Pos)
 #define PM_RCAUSE_SYST_Pos          6            /**< \brief (PM_RCAUSE) System Reset Request */
-#define PM_RCAUSE_SYST              (_U(0x1) << PM_RCAUSE_SYST_Pos)
-#define PM_RCAUSE_MASK              _U(0x77)     /**< \brief (PM_RCAUSE) MASK Register */
+#define PM_RCAUSE_SYST              (0x1ul << PM_RCAUSE_SYST_Pos)
+#define PM_RCAUSE_MASK              0x77ul       /**< \brief (PM_RCAUSE) MASK Register */
 
 /** \brief PM hardware registers */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))