From 01d8291a61762c888587ea82bb099aad2d551df6 Mon Sep 17 00:00:00 2001
From: Jeff Epler <jepler@gmail.com>
Date: Sat, 22 Oct 2022 18:00:54 -0500
Subject: [PATCH] standalone build for riscv ulp programs

---
 .gitignore   |  2 ++
 Makefile     | 32 ++++++++++++++++++++++++++++++++
 sdkconfig.h  |  1 +
 ulp.c        | 31 +++++++++++++++++++++++++++++++
 ulp.riscv.ld | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 114 insertions(+)
 create mode 100644 .gitignore
 create mode 100644 Makefile
 create mode 100644 sdkconfig.h
 create mode 100644 ulp.c
 create mode 100644 ulp.riscv.ld

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..859ba00
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+/link.ld
+/a.out
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..7cf81b5
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,32 @@
+COPROC_RESERVE_MEM ?= 8176
+SOC := esp32s3
+CC := riscv32-esp-elf-gcc
+CFLAGS := -Os -march=rv32imc -mdiv -fdata-sections -ffunction-sections
+CFLAGS += -isystem $(IDF_PATH)/components/ulp/ulp_riscv/include/
+CFLAGS += -isystem $(IDF_PATH)/components/soc/$(SOC)/include
+CFLAGS += -isystem $(IDF_PATH)/components/esp_common/include
+CFLAGS += -DCOPROC_RESERVE_MEM=$(COPROC_RESERVE_MEM)
+ifeq ($(SOC),esp32s3)
+CFLAGS += -DCONFIG_IDF_TARGET_ESP32S3
+endif
+ifeq ($(SOC),esp32s2)
+CFLAGS += -DCONFIG_IDF_TARGET_ESP32S2
+endif
+LDFLAGS := -march=rv32imc --specs=nano.specs --specs=nosys.specs
+
+SRCS ?= ulp.c
+SRCS += $(IDF_PATH)/components/ulp/ulp_riscv/ulp_riscv_utils.c
+LDFLAGS += link.ld
+
+
+.PHONY: default
+default: a.out
+a.out: $(SRCS) link.ld
+	$(CC) -flto $(CFLAGS) $^ -o $@ $(LDFLAGS)
+
+.PHONY: clean
+clean:
+	rm -f a.out link.ld
+
+link.ld: ulp.riscv.ld
+	$(CC) -E -P -xc $(CFLAGS) -o $@ $<
diff --git a/sdkconfig.h b/sdkconfig.h
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/sdkconfig.h
@@ -0,0 +1 @@
+
diff --git a/ulp.c b/ulp.c
new file mode 100644
index 0000000..de54480
--- /dev/null
+++ b/ulp.c
@@ -0,0 +1,31 @@
+// ULP-RISCV
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "ulp_riscv/ulp_riscv.h"
+#include "ulp_riscv/ulp_riscv_utils.h"
+#include "ulp_riscv/ulp_riscv_gpio.h"
+
+// global variables will be exported as public symbols, visible from main CPU
+__attribute__((used)) uint8_t shared_mem[1024];
+__attribute__((used)) uint16_t shared_mem_len = 1024;
+
+int main (void) {
+    shared_mem[0] = 10;
+    shared_mem_len = 1024;
+
+    bool gpio_level = true;
+
+    ulp_riscv_gpio_init(GPIO_NUM_21);
+    ulp_riscv_gpio_output_enable(GPIO_NUM_21);
+
+    while(1) {
+        ulp_riscv_gpio_output_level(GPIO_NUM_21, gpio_level);
+        ulp_riscv_delay_cycles(shared_mem[0] * 10 * ULP_RISCV_CYCLES_PER_MS);
+        gpio_level = !gpio_level;
+    }
+
+    // ulp_riscv_shutdown() is called automatically when main exits
+    return 0;
+}
diff --git a/ulp.riscv.ld b/ulp.riscv.ld
new file mode 100644
index 0000000..86e88c8
--- /dev/null
+++ b/ulp.riscv.ld
@@ -0,0 +1,48 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "sdkconfig.h"
+
+ENTRY(reset_vector)
+
+MEMORY
+{
+    ram(RW) : ORIGIN = 0, LENGTH = COPROC_RESERVE_MEM
+}
+
+SECTIONS
+{
+    . = ORIGIN(ram);
+    .text :
+    {
+        *start.S.obj(.text.vectors) /* Default reset vector must link to offset 0x0 */
+        *(.text)
+        *(.text*)
+    } >ram
+
+    .rodata ALIGN(4):
+    {
+        *(.rodata)
+        *(.rodata*)
+    } > ram
+
+    .data ALIGN(4):
+    {
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+    } > ram
+
+    .bss ALIGN(4) :
+    {
+        *(.bss)
+        *(.bss*)
+        *(.sbss)
+        *(.sbss*)
+    } >ram
+
+    __stack_top = ORIGIN(ram) + LENGTH(ram);
+}