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10 changed files with 66 additions and 43 deletions
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@ -40,7 +40,7 @@ variables:
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GIT_FETCH_EXTRA_FLAGS: "--no-recurse-submodules --prune --prune-tags"
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# we're using .cache folder for caches
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GIT_CLEAN_FLAGS: -ffdx -e .cache/
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LATEST_GIT_TAG: v5.5-rc1
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LATEST_GIT_TAG: v5.5
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SUBMODULE_FETCH_TOOL: "tools/ci/ci_fetch_submodule.py"
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# by default we will fetch all submodules
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24
README.md
24
README.md
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@ -15,18 +15,18 @@ ESP-IDF is the development framework for Espressif SoCs supported on Windows, Li
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The following table shows ESP-IDF support of Espressif SoCs where ![alt text][preview] and ![alt text][supported] denote preview status and support, respectively. The preview support is usually limited in time and intended for beta versions of chips. Please use an ESP-IDF release where the desired SoC is already supported.
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|Chip | v5.0 | v5.1 | v5.2 | v5.3 | v5.4 | |
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|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------: |:------------------------------------------------------------------- |
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|ESP32 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
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|ESP32-S2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
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|ESP32-C3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
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|ESP32-S3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_S3) |
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|ESP32-C2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32-C2) |
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|ESP32-C6 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_C6) |
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|ESP32-H2 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_H2) |
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|ESP32-P4 | | | | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32-P4) |
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|ESP32-C5 | | | | | ![alt text][preview] |[Announcement](https://www.espressif.com/en/news/ESP32-C5) |
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|ESP32-C61 | | | | | ![alt text][preview] |[Announcement](https://www.espressif.com/en/products/socs/esp32-c61) |
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|Chip | v5.1 | v5.2 | v5.3 | v5.4 | v5.5 | |
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|:----------- |:--------------------: | :--------------------: | :--------------------: | :--------------------: | :--------------------: |:------------------------------------------------------------------- |
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|ESP32 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
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|ESP32-S2 |![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
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|ESP32-C3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
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|ESP32-S3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_S3) |
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|ESP32-C2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32-C2) |
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|ESP32-C6 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_C6) |
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|ESP32-H2 |![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_H2) |
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|ESP32-P4 | | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32-P4) |
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|ESP32-C5 | | | | |![alt text][preview] |[Announcement](https://www.espressif.com/en/news/ESP32-C5) |
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|ESP32-C61 | | | | |![alt text][preview] |[Announcement](https://www.espressif.com/en/products/socs/esp32-c61) |
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[supported]: https://img.shields.io/badge/-supported-green "supported"
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[preview]: https://img.shields.io/badge/-preview-orange "preview"
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25
README_CN.md
25
README_CN.md
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@ -15,18 +15,19 @@ ESP-IDF 是乐鑫官方推出的物联网开发框架，支持 Windows、Linux
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下表总结了乐鑫芯片在 ESP-IDF 各版本中的支持状态，其中 ![alt text][supported] 代表已支持，![alt text][preview] 代表目前处于预览支持状态。预览支持状态通常有时间限制，而且仅适用于测试版芯片。请确保使用与芯片相匹配的 ESP-IDF 版本。
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|芯片 | v5.0 | v5.1 | v5.2 | v5.3 | v5.4 | |
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|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------: | :------------------------------------------------------------------------ |
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|ESP32 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
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|ESP32-S2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
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|ESP32-C3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
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|ESP32-S3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) |
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|ESP32-C2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) |
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|ESP32-C6 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) |
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|ESP32-H2 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) |
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|ESP32-P4 | | | | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-P4) |
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|ESP32-C5 | | | | | ![alt text][preview] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5) |
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|ESP32-C61 | | | | | ![alt text][preview] | [芯片发布公告](https://www.espressif.com/zh-hans/products/socs/esp32-c61) |
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芯片 | v5.1 | v5.2 | v5.3 | v5.4 | v5.5 | |
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|:----------- | :--------------------: | :--------------------: | :--------------------: | :--------------------: | :--------------------: |:------------------------------------------------------------------------ |
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|ESP32 |![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |![alt text][supported] | |
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|ESP32-S2 |![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
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|ESP32-C3 |![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
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|ESP32-S3 |![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) |
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|ESP32-C2 |![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) |
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|ESP32-C6 |![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) |
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|ESP32-H2 |![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) |
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|ESP32-P4 | | | ![alt text][supported] | ![alt text][supported] |![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-P4) |
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|ESP32-C5 | | | | |![alt text][preview] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5) |
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|ESP32-C61 | | | | |![alt text][preview] | [芯片发布公告](https://www.espressif.com/zh-hans/products/socs/esp32-c61) |
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[supported]: https://img.shields.io/badge/-%E6%94%AF%E6%8C%81-green "supported"
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[preview]: https://img.shields.io/badge/-%E9%A2%84%E8%A7%88-orange "preview"
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@ -201,7 +201,11 @@
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#if SOC_PM_SUPPORT_TOP_PD
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// IDF console uses 8 bits data mode without parity, so each char occupy 8(data)+1(start)+1(stop)=10bits
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#ifdef CONFIG_ESP_CONSOLE_UART_NONE
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#define UART_FLUSH_US_PER_CHAR (0)
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#else
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#define UART_FLUSH_US_PER_CHAR (10*1000*1000 / CONFIG_ESP_CONSOLE_UART_BAUDRATE)
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#endif
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#define CONCATENATE_HELPER(x, y) (x##y)
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#define CONCATENATE(x, y) CONCATENATE_HELPER(x, y)
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#define CONSOLE_UART_DEV (&CONCATENATE(UART, CONFIG_ESP_CONSOLE_UART_NUM))
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@ -17,7 +17,7 @@
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extern "C" {
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#endif
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#if SOC_PARLIO_SUPPORTED
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#ifdef SOC_PARLIO_SUPPORTED
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/**
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* @brief Parallel Panel IO configuration structure, for intel 8080 interface(8 data-lines) or SPI interface(1 data-lines)
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*/
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@ -42,6 +42,13 @@ bool esp_psram_is_initialized(void);
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*/
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size_t esp_psram_get_size(void);
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/**
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* @brief Get the memory mapped address of the attached PSRAM chip
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*
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* @return Pointer to the start of PSRAM memory, or NULL if PSRAM isn't successfully initialized
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*/
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uint8_t* esp_psram_get_address(void);
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#ifdef __cplusplus
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}
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#endif
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@ -530,6 +530,15 @@ size_t esp_psram_get_size(void)
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return (size_t)available_size;
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}
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uint8_t* esp_psram_get_address(void)
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{
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if (!s_psram_ctx.is_initialised) {
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return NULL;
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}
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return (uint8_t *)s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_start;
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}
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uint8_t esp_psram_io_get_cs_io(void)
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{
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return esp_psram_impl_get_cs_io();
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@ -3,6 +3,8 @@ choice ESPTOOLPY_FLASHFREQ
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default ESPTOOLPY_FLASHFREQ_64M
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config ESPTOOLPY_FLASHFREQ_64M
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bool "64 MHz"
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config ESPTOOLPY_FLASHFREQ_48M
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bool "48 MHz"
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config ESPTOOLPY_FLASHFREQ_32M
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bool "32 MHz"
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config ESPTOOLPY_FLASHFREQ_16M
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@ -41,7 +41,9 @@ if(CONFIG_ULP_COPROC_TYPE_FSM OR CONFIG_ULP_COPROC_TYPE_RISCV)
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"ulp_fsm/ulp.c"
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"ulp_fsm/ulp_macro.c")
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elseif(CONFIG_ULP_COPROC_TYPE_RISCV)
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endif()
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if(CONFIG_ULP_COPROC_TYPE_RISCV)
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list(APPEND srcs
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"ulp_riscv/ulp_riscv.c"
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"ulp_riscv/ulp_riscv_lock.c"
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@ -8,23 +8,21 @@ menu "Ultra Low Power (ULP) Co-processor"
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Enable this feature if you plan to use the ULP Co-processor.
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Once this option is enabled, further ULP co-processor configuration will appear in the menu.
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choice ULP_COPROC_TYPE
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prompt "ULP Co-processor type"
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depends on ULP_COPROC_ENABLED
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default ULP_COPROC_TYPE_RISCV if (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3)
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config ULP_COPROC_TYPE_FSM
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bool "Enable ULP FSM (Finite State Machine)"
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depends on (SOC_ULP_FSM_SUPPORTED && ULP_COPROC_ENABLED)
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help
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Choose the ULP Coprocessor type: ULP FSM (Finite State Machine) or ULP RISC-V.
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config ULP_COPROC_TYPE_FSM
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bool "ULP FSM (Finite State Machine)"
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depends on SOC_ULP_FSM_SUPPORTED
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config ULP_COPROC_TYPE_RISCV
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bool "ULP RISC-V"
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depends on SOC_RISCV_COPROC_SUPPORTED
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config ULP_COPROC_TYPE_LP_CORE
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bool "LP core RISC-V"
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depends on SOC_LP_CORE_SUPPORTED
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endchoice
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Note: On devices with both ULP FSM and ULP RISC-V, both ULPs can be enabled simultaneously at compile-time,
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but may not be used simultaneously at run-time.
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config ULP_COPROC_TYPE_RISCV
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bool "Enable ULP RISC-V"
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depends on (SOC_RISCV_COPROC_SUPPORTED && ULP_COPROC_ENABLED)
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help
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Note: On devices with both ULP FSM and ULP RISC-V, both ULPs can be enabled simultaneously at compile-time,
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but may not be used simultaneously at run-time.
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config ULP_COPROC_TYPE_LP_CORE
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bool "Enable LP core RISC-V"
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depends on (SOC_LP_CORE_SUPPORTED && ULP_COPROC_ENABLED)
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config ULP_COPROC_RESERVE_MEM
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int
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