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dts: riscv: introduce PolarFire SoC GPIO interface

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Add support for the Microchip PolarFire SoC GPIO interface

Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
This commit is contained in:
Conor Paxton 2022-06-21 08:55:03 +01:00 committed by Carles Cufí
parent 3e0f738cb2
commit 0db19661e6
2 changed files with 64 additions and 0 deletions
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22
dts/bindings/gpio/microchip,mpfs-gpio.yaml Normal file
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@ -0,0 +1,22 @@
# Copyright (c) 2022 Microchip Technology Inc.
# SPDX-License-Identifier: Apache-2.0
description: Microchip PolarFire SoC GPIO node
compatible: "microchip,mpfs-gpio"
include: [gpio-controller.yaml, base.yaml]
properties:
reg:
required: true
interrupts:
required: false
"#gpio-cells":
const: 2
gpio-cells:
- pin
- flags

42
dts/riscv/mpfs-icicle.dtsi
View file

@ -4,6 +4,9 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <skeleton.dtsi>
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
@ -92,5 +95,44 @@
status = "disabled";
clock-frequency = <150000000>;
};
gpio0: gpio@20120000 {
compatible = "microchip,mpfs-gpio";
reg = <0x20120000 0x1000>;
interrupt-parent = <&plic>;
interrupts = <51 1>;
interrupt-controller;
#interrupt-cells = <1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
status = "disabled";
};
gpio1: gpio@20121000 {
compatible = "microchip,mpfs-gpio";
reg = <0x20121000 0x1000>;
interrupt-parent = <&plic>;
interrupts = <52 1>;
interrupt-controller;
#interrupt-cells = <1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
status = "disabled";
};
gpio2: gpio@20122000 {
compatible = "microchip,mpfs-gpio";
reg = <0x20122000 0x1000>;
interrupt-parent = <&plic>;
interrupts = <53 1>;
interrupt-controller;
#interrupt-cells = <1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
status = "disabled";
};
};
};