dts: arm: nxp: s32: add #address-cells to interrupt provider
Add `#address-cells = <0>;` to interrupt provider nodes in the NXP S32 device tree to resolve warnings: e.g. Warning (interrupt_provider): /soc/interrupt-controller@47800000: Missing Warning (interrupt_provider): /soc/siul2@40520000/eirq0@40520010: Missing This ensures compliance with device tree specifications and eliminates build warnings. Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
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2 changed files with 6 additions and 0 deletions
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@ -90,6 +90,7 @@
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eirq0: eirq@40290010 {
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compatible = "nxp,s32-siul2-eirq";
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reg = <0x40290010 0xb4>;
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#address-cells = <0>;
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interrupts = <53 0>, <54 0>, <55 0>, <56 0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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@ -105,6 +105,7 @@
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0x47800000 0x10000>,
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<0x47900000 0x80000>;
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#address-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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@ -219,6 +220,7 @@
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eirq0: eirq0@40520010 {
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compatible = "nxp,s32-siul2-eirq";
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reg = <0x40520010 0xb4>;
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#address-cells = <0>;
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interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-controller;
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#interrupt-cells = <2>;
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@ -270,6 +272,7 @@
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eirq1: eirq1@40d20010 {
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compatible = "nxp,s32-siul2-eirq";
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reg = <0x40d20010 0xb4>;
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#address-cells = <0>;
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interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-controller;
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#interrupt-cells = <2>;
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@ -345,6 +348,7 @@
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eirq4: eirq4@42520010 {
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compatible = "nxp,s32-siul2-eirq";
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reg = <0x42520010 0xb4>;
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#address-cells = <0>;
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interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-controller;
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#interrupt-cells = <2>;
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@ -418,6 +422,7 @@
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eirq5: eirq5@42d20010 {
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compatible = "nxp,s32-siul2-eirq";
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reg = <0x42d20010 0xb4>;
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#address-cells = <0>;
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interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-controller;
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#interrupt-cells = <2>;
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