boards: shields: add support for rtkmipilcdb00000be shield

First commit to support rtkmipilcdb00000be display shield

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
This commit is contained in:
The Nguyen 2024-11-19 16:29:22 +07:00 committed by Johan Hedberg
parent 1d6a453a6a
commit 3bb3a9626f
10 changed files with 365 additions and 33 deletions

View file

@ -10,4 +10,18 @@ config NET_L2_ETHERNET
endif # NETWORKING
if SHIELD_RTKMIPILCDB00000BE
config MEMC
default y
if LVGL
config LV_Z_VBD_CUSTOM_SECTION
default y
endif # LVGL
endif # SHIELD_RTKMIPILCDB00000BE
endif # BOARD_EK_RA8D1

View file

@ -85,39 +85,42 @@ Supported Features
The below features are currently supported on Zephyr OS for EK-RA8D1 board:
+--------------+------------+------------------+
| Interface | Controller | Driver/Component |
+==============+============+==================+
| GPIO | on-chip | gpio |
+--------------+------------+------------------+
| MPU | on-chip | arch/arm |
+--------------+------------+------------------+
| NVIC | on-chip | arch/arm |
+--------------+------------+------------------+
| UART | on-chip | serial |
+--------------+------------+------------------+
| CLOCK | on-chip | clock control |
+--------------+------------+------------------+
| ENTROPY | on-chip | entropy |
+--------------+------------+------------------+
| SPI | on-chip | spi |
+--------------+------------+------------------+
| FLASH | on-chip | flash |
+--------------+------------+------------------+
| PWM | on-chip | pwm |
+--------------+------------+------------------+
| COUNTER | on-chip | counter |
+--------------+------------+------------------+
| CAN | on-chip | canfd |
+--------------+------------+------------------+
| I2C | on-chip | i2c |
+--------------+------------+------------------+
| USBHS | on-chip | udc |
+--------------+------------+------------------+
| ETHERNET | on-chip | ethernet |
+--------------+------------+------------------+
| ADC | on-chip | adc |
+--------------+------------+------------------+
+--------------+------------+-----------------------------------+
| Interface | Controller | Driver/Component |
+==============+============+===================================+
| GPIO | on-chip | gpio |
+--------------+------------+-----------------------------------+
| MPU | on-chip | arch/arm |
+--------------+------------+-----------------------------------+
| NVIC | on-chip | arch/arm |
+--------------+------------+-----------------------------------+
| UART | on-chip | serial |
+--------------+------------+-----------------------------------+
| CLOCK | on-chip | clock control |
+--------------+------------+-----------------------------------+
| ENTROPY | on-chip | entropy |
+--------------+------------+-----------------------------------+
| SPI | on-chip | spi |
+--------------+------------+-----------------------------------+
| FLASH | on-chip | flash |
+--------------+------------+-----------------------------------+
| PWM | on-chip | pwm |
+--------------+------------+-----------------------------------+
| COUNTER | on-chip | counter |
+--------------+------------+-----------------------------------+
| CAN | on-chip | canfd |
+--------------+------------+-----------------------------------+
| I2C | on-chip | i2c |
+--------------+------------+-----------------------------------+
| USBHS | on-chip | udc |
+--------------+------------+-----------------------------------+
| DISPLAY | on-chip | LCDIF; MIPI-DSI. Tested with |
| | | :ref:`rtkmipilcdb00000be` shields |
+--------------+------------+-----------------------------------+
| ETHERNET | on-chip | ethernet |
+--------------+------------+-----------------------------------+
| ADC | on-chip | adc |
+--------------+------------+-----------------------------------+
**Note:** for using Ethernet on RA8D1 board please set switch SW1 as following configuration:

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@ -178,4 +178,69 @@
<RA_PSEL(RA_PSEL_BUS, 10, 10)>;
};
};
glcdc_default: glcdc_default {
group1 {
/* LCDC_TCON0 */
psels = <RA_PSEL(RA_PSEL_GLCDC, 8, 5)>,
/* LCDC_TCON1 */
<RA_PSEL(RA_PSEL_GLCDC, 8, 7)>,
/* LCDC_TCON2 */
<RA_PSEL(RA_PSEL_GLCDC, 5, 13)>,
/* LCDC_TCON3 */
<RA_PSEL(RA_PSEL_GLCDC, 5, 15)>,
/* LCDC_DATA00 */
<RA_PSEL(RA_PSEL_GLCDC, 9, 14)>,
/* LCDC_DATA01 */
<RA_PSEL(RA_PSEL_GLCDC, 9, 15)>,
/* LCDC_DATA02 */
<RA_PSEL(RA_PSEL_GLCDC, 9, 10)>,
/* LCDC_DATA03 */
<RA_PSEL(RA_PSEL_GLCDC, 9, 11)>,
/* LCDC_DATA04 */
<RA_PSEL(RA_PSEL_GLCDC, 9, 12)>,
/* LCDC_DATA05 */
<RA_PSEL(RA_PSEL_GLCDC, 9, 13)>,
/* LCDC_DATA06 */
<RA_PSEL(RA_PSEL_GLCDC, 9, 4)>,
/* LCDC_DATA07 */
<RA_PSEL(RA_PSEL_GLCDC, 9, 3)>,
/* LCDC_DATA08 */
<RA_PSEL(RA_PSEL_GLCDC, 9, 2)>,
/* LCDC_DATA09 */
<RA_PSEL(RA_PSEL_GLCDC, 2, 7)>,
/* LCDC_DATA10 */
<RA_PSEL(RA_PSEL_GLCDC, 7, 11)>,
/* LCDC_DATA11 */
<RA_PSEL(RA_PSEL_GLCDC, 7, 12)>,
/* LCDC_DATA12 */
<RA_PSEL(RA_PSEL_GLCDC, 7, 13)>,
/* LCDC_DATA13 */
<RA_PSEL(RA_PSEL_GLCDC, 7, 14)>,
/* LCDC_DATA14 */
<RA_PSEL(RA_PSEL_GLCDC, 7, 15)>,
/* LCDC_DATA15 */
<RA_PSEL(RA_PSEL_GLCDC, 11, 7)>,
/* LCDC_DATA16 */
<RA_PSEL(RA_PSEL_GLCDC, 11, 6)>,
/* LCDC_DATA17 */
<RA_PSEL(RA_PSEL_GLCDC, 11, 5)>,
/* LCDC_DATA18 */
<RA_PSEL(RA_PSEL_GLCDC, 11, 1)>,
/* LCDC_DATA19 */
<RA_PSEL(RA_PSEL_GLCDC, 11, 4)>,
/* LCDC_DATA20 */
<RA_PSEL(RA_PSEL_GLCDC, 11, 3)>,
/* LCDC_DATA21 */
<RA_PSEL(RA_PSEL_GLCDC, 11, 2)>,
/* LCDC_DATA22 */
<RA_PSEL(RA_PSEL_GLCDC, 11, 0)>,
/* LCDC_DATA23 */
<RA_PSEL(RA_PSEL_GLCDC, 7, 7)>,
/* LCDC_CLK */
<RA_PSEL(RA_PSEL_GLCDC, 8, 6)>,
/* LCDC_EXTCLK */
<RA_PSEL(RA_PSEL_GLCDC, 5, 14)>;
};
};
};

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@ -65,10 +65,23 @@
status = "okay";
};
renesas_mipi_connector: mipi-connector {
compatible = "renesas,ra-gpio-mipi-header";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <14 0 &ioport5 11 0>, /* IIC_SDA */
<15 0 &ioport4 4 0>, /* DISP_BLEN */
<16 0 &ioport5 12 0>, /* IIC_SCL */
<17 0 &ioport5 10 0>, /* DISP_INT */
<18 0 &ioporta 1 0>; /* DISP_RST */
};
aliases {
led0 = &led1;
sw0 = &button0;
sw1 = &button1;
mipi-dsi = &mipi_dsi;
};
};
@ -111,6 +124,12 @@
status = "okay";
};
&lcdclk {
clocks = <&pll>;
div = <2>;
status = "okay";
};
&ioport0 {
status = "okay";
};
@ -123,10 +142,18 @@
status = "okay";
};
&ioport5 {
status = "okay";
};
&ioport6 {
status = "okay";
};
&ioporta {
status = "okay";
};
&sci0 {
/* sci0 and spi0 cannot be enabled together */
pinctrl-0 = <&sci9_default>;
@ -262,3 +289,12 @@
SDRAM_TREFW_8CYCLES>;
};
};
zephyr_lcdif: &lcdif {
pinctrl-0 = <&glcdc_default>;
pinctrl-names = "default";
};
zephyr_mipi_dsi: &mipi_dsi {};
renesas_mipi_i2c: &iic1{};

View file

@ -10,6 +10,9 @@ SECTION_DATA_PROLOGUE(.sdram,(NOLOAD),)
{
__SDRAM_Start = .;
KEEP(*(.sdram*))
#ifdef CONFIG_LVGL
KEEP(*(.lvgl_buf*))
#endif
__SDRAM_End = .;
} GROUP_LINK_IN(SDRAM)

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@ -0,0 +1,57 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
if SHIELD_RTKMIPILCDB00000BE
if DISPLAY
# Enable MIPI DSI, as this display controller requires it.
config MIPI_DSI
default y
endif # DISPLAY
if LVGL
# Configure LVGL to use touchscreen with input API
config INPUT
default y
if INPUT
# GT911 driver drives reset pin low, GT911 and ILI9806E_DSI driver share a reset line,
# so it needs to initialize before the display_ili9806e_dsi driver but after the MIPI DSI driver
config INPUT_INIT_PRIORITY
default 89
endif # INPUT
# LVGL should allocate buffers equal to size of display
config LV_Z_VDB_SIZE
default 100
# Enable double buffering
config LV_Z_DOUBLE_VDB
default y
# Force full refresh. This prevents memory copy associated with partial
# display refreshes, which is not necessary for the GLCDC driver
config LV_Z_FULL_REFRESH
default y
config LV_Z_BITS_PER_PIXEL
default 32
# Use offloaded render thread
config LV_Z_FLUSH_THREAD
default y
choice LV_COLOR_DEPTH
default LV_COLOR_DEPTH_32
endchoice
endif # LVGL
endif # SHIELD_RTKMIPILCDB00000BE

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@ -0,0 +1,5 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config SHIELD_RTKMIPILCDB00000BE
def_bool $(shields_list_contains,rtkmipilcdb00000be)

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@ -0,0 +1,25 @@
/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
&pinctrl {
iic1_default: iic1_default {
group1 {
/* SCL1 SDA1 */
psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,
<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
drive-strength = "medium";
};
};
};
&iic1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <DT_FREQ_K(100)>;
pinctrl-0 = <&iic1_default>;
pinctrl-names = "default";
};

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@ -0,0 +1,61 @@
.. _rtkmipilcdb00000be:
RTKMIPILCDB00000BE MIPI Display
###############################
Overview
********
The Focus LCDs RTKMIPILCDB00000BE MIPI Display is a 4.5 inch TFT 480x854 pixels
capacitive touch panel, and a backlight unit.
This display uses a 26 pin connector header.
Pins Assignment of the Renesas RTKMIPILCDB00000BE MIPI Display
==============================================================
+-----------------------+------------------------+
| Connector Pin | Function |
+=======================+========================+
| 14 | Touch ctrl I2C SDA |
+-----------------------+------------------------+
| 15 | Display backlight enable|
+-----------------------+------------------------+
| 16 | Touch ctrl I2C SCL |
+-----------------------+------------------------+
| 17 | External interrupt |
+-----------------------+------------------------+
| 18 | Display reset |
+-----------------------+------------------------+
Hardware Requirements:
**********************
Supported Renesas RA boards: EK-RA8D1
- 1 x RA Board
- 1 x Micro USB cable
Hardware Configuration:
***********************
The MIPI Graphics Expansion Port (J58) connects the EK-RA8D1 board to the MIPI Graphics Expansion Board
supplied as part of the kit.
Set the configuration switches (SW1) as below to avoid potential failures.
+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
| SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C |
+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
| OFF | OFF | OFF | OFF | OFF | ON | ON | OFF |
+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
Programming
***********
Set ``--shield=rtkmipilcdb00000be`` when you invoke ``west build``. For
example:
.. zephyr-app-commands::
:zephyr-app: tests/drivers/display/display_read_write
:board: ek_ra8d1
:shield: rtkmipilcdb00000be
:goals: build

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@ -0,0 +1,63 @@
/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/display/panel.h>
/{
chosen {
zephyr,display = &zephyr_lcdif;
};
lvgl_pointer {
compatible = "zephyr,lvgl-pointer-input";
input = <&gt911_rtkmipilcdb00000be>;
};
};
&renesas_mipi_i2c {
status = "okay";
gt911_rtkmipilcdb00000be: gt911-rtkmipilcdb00000be@5d {
compatible = "goodix,gt911";
reg = <0x5d>;
irq-gpios = <&renesas_mipi_connector 17 GPIO_ACTIVE_HIGH>;
reset-gpios = <&renesas_mipi_connector 18 GPIO_ACTIVE_LOW>;
};
};
&zephyr_mipi_dsi {
status = "okay";
ili9806e: ili9806e@0 {
status = "okay";
compatible = "ilitek,ili9806e-dsi";
reg = <0x0>;
height = <854>;
width = <480>;
data-lanes = <2>;
pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
};
};
&zephyr_lcdif {
status = "okay";
width = <480>;
height = <854>;
input-pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
output-pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
display-timings {
compatible = "zephyr,panel-timing";
hsync-len = <2>;
hback-porch = <5>;
vsync-len = <3>;
vback-porch = <20>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
hfront-porch = <72>;
vfront-porch = <17>;
};
backlight-gpios = <&renesas_mipi_connector 15 GPIO_ACTIVE_HIGH>;
};