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dts: riscv: sifive: fu540: add missing ngpios property

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FU540 SoC has 16 GPIOs, this way, the GPIO API can perform correct
asserts when a pin is provided. Note that default is 32, correct for eg
FE310.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2024-01-16 15:04:03 +01:00 committed by Fabio Baltieri
parent 27f14eb3a8
commit c42ef7117d
1 changed files with 1 additions and 0 deletions
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dts/riscv/sifive/riscv64-fu540.dtsi
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@ -179,6 +179,7 @@
gpio0: gpio@10060000 { gpio0: gpio@10060000 {
compatible = "sifive,gpio0"; compatible = "sifive,gpio0";
gpio-controller; gpio-controller;
ngpios = <16>;
interrupt-parent = <&plic>; interrupt-parent = <&plic>;
interrupts = <7 1>, <8 1>, <9 1>, <10 1>, interrupts = <7 1>, <8 1>, <9 1>, <10 1>,
<11 1>, <12 1>, <13 1>, <14 1>, <11 1>, <12 1>, <13 1>, <14 1>,