dts: riscv: neorv32: define machine timer

Define machine timer in Devicetree.

Ref. https://stnolting.github.io/neorv32/#_machine_system_timer_mtime

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

dts/bindings/timer/neorv32-machine-timer.yaml

@@ -0,0 +1,19 @@
+# Copyright (c) 2022 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  NEORV32 Machine Timer
+
+  The NEORV32 machine timer provides RISC-V privileged mtime and mtimecmp
+  registers.
+
+compatible: "neorv32-machine-timer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true

dts/riscv/neorv32.dtsi

@@ -63,6 +63,12 @@
 		#size-cells = <1>;
 		ranges;
 
+		mtimer: timer@ffffff90 {
+			compatible = "neorv32-machine-timer";
+			reg = <0xffffff90 0x10>;
+			interrupts = <7>;
+		};
+
 		uart0: serial@ffffffa0 {
 			compatible = "neorv32-uart";
 			status = "disabled";