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dts: riscv: neorv32: define machine timer

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Define machine timer in Devicetree.

Ref. https://stnolting.github.io/neorv32/#_machine_system_timer_mtime

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas 2022-07-28 16:44:00 +02:00 committed by Carles Cufí
parent c17ee81af4
commit e5e8822658
2 changed files with 25 additions and 0 deletions
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19
dts/bindings/timer/neorv32-machine-timer.yaml Normal file
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@ -0,0 +1,19 @@
# Copyright (c) 2022 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
description: |
NEORV32 Machine Timer
The NEORV32 machine timer provides RISC-V privileged mtime and mtimecmp
registers.
compatible: "neorv32-machine-timer"
include: base.yaml
properties:
reg:
required: true
interrupts:
required: true

6
dts/riscv/neorv32.dtsi
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@ -63,6 +63,12 @@
#size-cells = <1>;
ranges;
mtimer: timer@ffffff90 {
compatible = "neorv32-machine-timer";
reg = <0xffffff90 0x10>;
interrupts = <7>;
};
uart0: serial@ffffffa0 {
compatible = "neorv32-uart";
status = "disabled";