boards: adi: Update MAX78002EVKIT index.rst file
- Removed unrelated information with MAX78002EVKIT. - Updated "Connections and IOs" part's format. Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
This commit is contained in:
Furkan Akkiz
Benjamin Cabé
parent
141fe2d0f1
commit
e8b29aae35
1 changed files with 319 additions and 139 deletions
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@ -42,7 +42,7 @@ Hardware
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- MIPI Camera Serial Interface 2 (MIPI CSI-2) Controller V2.1
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- Support for Two Data Lanes
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- 12-Bit Parallel Camera Interface
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- I 2S Controller/Target for Digital Audio Interface
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- I2S Controller/Target for Digital Audio Interface
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- Secure Digital Interface Supports SD 3.0/SDIO 3.0/eMMC 4.51
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- Convolutional Neural Network (CNN) Accelerator
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@ -71,51 +71,6 @@ Hardware
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- AES 128/192/256 Hardware Acceleration Engine
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- True Random Number Generator (TRNG) Seed Generator
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- Ultra-Low-Power Wireless Microcontroller
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- Internal 100MHz Oscillator
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- Flexible Low-Power Modes with 7.3728MHz System Clock Option
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- 512KB Flash and 128KB SRAM (Optional ECC on One 32KB SRAM Bank)
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- 16KB Instruction Cache
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- Bluetooth 5.2 LE Radio
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- Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload Timing-Critical Bluetooth Processing
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- Fully Open-Source Bluetooth 5.2 Stack Available
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- Supports AoA, AoD, LE Audio, and Mesh
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- High-Throughput (2Mbps) Mode
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- Long-Range (125kbps and 500kbps) Modes
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- Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm
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- Single-Ended Antenna Connection (50Ω)
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- Power Management Maximizes Battery Life
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- 2.0V to 3.6V Supply Voltage Range
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- Integrated SIMO Power Regulator
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- Dynamic Voltage Scaling (DVS)
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- 23.8μA/MHz Active Current at 3.0V
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- 4.4μA at 3.0V Retention Current for 32KB
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- Selectable SRAM Retention + RTC in Low-Power Modes
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- Multiple Peripherals for System Control
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- Up to Two High-Speed SPI Master/Slave
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- Up to Three High-Speed I2C Master/Slave (3.4Mbps)
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- Up to Four UART, One I2S Master/Slave
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- Up to 8-Input, 10-Bit Sigma-Delta ADC 7.8ksps
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- Up to Four Micro-Power Comparators
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- Timers: Up to Two Four 32-Bit, Two LP, TwoWatchdog Timers
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- 1-Wire® Master
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- Up to Four Pulse Train (PWM) Engines
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- RTC with Wake-Up Timer
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- Up to 52 GPIOs
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- Security and Integrity
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- Available Secure Boot
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- TRNG Seed Generator
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- AES 128/192/256 Hardware Acceleration Engine
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- External devices connected to the MAX78002 EVKIT:
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- Color TFT Display
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@ -165,99 +120,324 @@ The ``max78002evkit/max78002/m4`` board target supports the following interfaces
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Connections and IOs
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===================
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| Name | Signal | Usage |
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+===========+===================+==================================================================================+
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| JP1 | 3V3 MON | Normal operation in conjunction with JP3 jumpered 1-2 |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP2 | 3V3 SW PM BYPASS | Power monitor shunts for main 3.3 V system power are bypassed |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP3 | CNN MON | Normal operation in conjunction with JP6 jumpered 1-2 |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP4 | VCOREA PM BYPASS | Power monitor shunts for U4's share of VCOREA + CNN loads are bypassed |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP5 | VCOREB PM BYPASS | Power monitor shunts for VCOREB are bypassed |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP6 | VREGO_A PM BYPASS | Power monitor shunts for VREGO_A are bypassed |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP7 | VBAT | Enable/Disable 3V3 VBAT power |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP8 | VREGI | Enable/Disable 3V3 VREGI power |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP9 | VREGI/VBAT | Onboard 3V3_PM / external source at TP10 supplies VREGI/VBAT |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP10 | VDDIOH | Onboard 3V3_PM/3V3_SW supplies VDDIOH |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP11 | VDDA | VREGO_A_PM powers VDDA |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP12 | VDDIO | VREGO_A_PM powers VDDIO |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP13 | VCOREB | VREGO_B powers VCOREB |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP14 | VCOREA | VREGO_C ties to net VCOREA |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP15 | VREF | DUT ADC VREF is supplied by precision external reference |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP16 | I2C1 SDA | I2C1 DATA pull-up |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP17 | I2C1 SCL | I2C1 CLOCK pull-up |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP18 | TRIG1 | PWR accumulator trigger signal 1 ties to port 1.6 |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP19 | TRIG2 | PWR accumulator trigger signal 2 ties to port 1.7 |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP20 | UART0 EN | Connect/Disconnect USB-UART bridge to UART0 |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP21 | I2C0_SDA | I2C0 DATA pull-up |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP22 | I2C0_SCL | I2C0 CLOCK pull-up |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP23 | UART1 EN | Connect/Disconnect USB-UART bridge to UART1 |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP24 | EXT I2C0 EN | Enable/Disable QWIIC interface for I2C0 |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP25 | PB1 PU | Enable/Disable 100kΩ pull-up for pushbutton mode, port 2.6 |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP26 | PB2 PU | Enable/Disable 100kΩ pull-up for pushbutton mode, port 2.7 |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP27 | I2C2 SDA | I2C2 DATA pull-up |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP28 | I2C2 SCL | I2C2 CLOCK pull-up |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP29 | VDDB | USB XCVR VDDB powered from VBUS / powered full time by system 3V3_PM |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP30 | EXT I2C2 EN | Enable/Disable QWIIC interface for I2C2 |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP31 | L/R SEL | Select MIC ON R/L CH, I2S microphone data stream |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP32 | MIC-I2S I/O | External I2S/MIC data from I2S I/O / MIC header connected to I2S SDI |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP33 | MIC-I2S/CODEC | Onboard CODEC data / external I2S data from header connects to I2S SDI |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP34 | I2S VDD | Select 1.8V/3.3V for external MIC and DATA I2S interface |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP35 | I2C1 SDA | I2C1 DATA pull-up |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP36 | I2C1 SCL | I2C1 CLOCK pull-up |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP37 | I2S CK SEL | Select SMA connector J6 / onboard crystal oscillator for I2S master clock source |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP38 | DVP CAM PWR | Enable/Disable OVM7692 for DVP camera PWDN input |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP39 | SW CAM PWUP | Camera reset and power up under port pin control |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP40 | HW PWUP / SW PWUP | Camera will reset and power up as soon as 3.3V reaches a valid level |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP41 | CSI CAM I2C EN | Connect/Disconnect I2C1 to CSI camera Digilent P5C I2C |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP42 | TFT DC | TFT data/command select connects to port 2.2 |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP43 | TFT CS | Select port 0.3 / port 1.7 to drive TFT CS |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP44 | LED1 EN | Enable/Disable LED1 |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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| JP45 | LED2 EN | Enable/Disable LED2 |
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+-----------+-------------------+----------------------------------------------------------------------------------+
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| Name | Name | Settings | Description |
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+===========+===================+===============+==================================================================================================+
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| JP1 | 3V3 MON | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Normal operation in conjunction with JP3 jumpered 1-2 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Test access point for current measurement | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP2 | 3V3 SW PM BYPASS | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Power monitor shunts for main 3.3 V system power are bypassed | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Main 3.3V input routes through shunts for power accumulator measurements | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP3 | CNN MON | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Normal operation in conjunction with JP6 jumpered 1-2 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Test access point for current measurement of U4's share of VCOREA and CNN loads | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP4 | VCOREA PM BYPASS | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Power monitor shunts for U4's share of VCOREA + CNN loads are bypassed | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | VCOREA + CNN loads route through shunts for power accumulator | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP5 | VCOREB PM BYPASS | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Power monitor shunts for VCOREB are bypassed | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | VCOREB power routes through shunts for power accumulator | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP6 | VREGO_A PM BYPASS | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Power monitor shunts for VREGO_A are bypassed | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | VREGO_A power routes through shunts for power accumulator | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP7 | VBAT | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Enables 3V3 VBAT power | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Disables 3V3 VBAT power | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP8 | VREGI | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Enables 3V3 VREGI power | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Disables 3V3 VREGI power | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP9 | VREGI/VBAT | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 2-1 | | | Onboard 3V3_PM supplies VREGI/VBAT | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 2-3 | | | External source at TP10 supplies VREGI/VBAT | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP10 | VDDIOH | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 2-1 | | | Onboard 3V3_PM supplies VDDIOH | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 2-3 | | | Onboard 3V3_SW supplies VDDIOH | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP11 | VDDA | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | VREGO_A_PM powers VDDA | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | VDDA may be powered using TP6 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP12 | VDDIO | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | VREGO_A_PM powers VDDIO | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | VDDIO may be powered using TP7 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP13 | VCOREB | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | VREGO_B powers VCOREB | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | VCOREB may be powered using TP8 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP14 | VCOREA | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | VREGO_C ties to net VCOREA | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Net VCOREA may be powered using TP9; JP17 may also be used as a current test point | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP15 | VREF | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | DUT ADC VREF is supplied by precision external reference | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | External ADC VREF disabled; ref voltage may be injected at JP18.1 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP16 | I2C1 SDA | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | I2C1 DATA pullup | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Close this jumper as needed to assure proper termination | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP17 | I2C1 SCL | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | I2C1 CLOCK pullup | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Close this jumper as needed to assure proper termination | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP18 | TRIG1 | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | PWR accumulator trigger signal 1 ties to port 1.6 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | TRIG1 is disabled, so DVP camera PCIF_D10 may be used instead | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP19 | TRIG2 | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | PWR accumulator trigger signal 2 ties to port 1.7 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | TRIG2 is disabled, so DVP camera PCIF_D11 may be used instead | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP20 | UART0 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Closed | | | USB-UART bridge connected to DUT UART0 (RTS and CTS are supported) | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | USB-UART bridge disconnected from DUT UART0 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP21 | I2C0_SDA | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | I2C0 DATA pull-up | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Close this jumper as needed to assure proper termination | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP22 | I2C0_SCL | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | I2C0 CLOCK pull-up | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Close this jumper as needed to assure proper termination | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP23 | UART1 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Closed | | | USB-UART bridge connected to DUT UART1 (no HW flow control) | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | USB-UART bridge disconnected from DUT UART1 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP24 | EXT I2C0 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | QWIIC interface for I2C0 enabled by default | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Open this jumper to place the QWIIC level translator into a high-Z state | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP25 | PB1 PU | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | 100kΩ pull-up enabled for pushbutton mode, port 2.6 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Pull-up disabled, allowing port pin to be repurposed (this port shared with AIN6) | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP26 | PB2 PU | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | 100kΩ pull-up enabled for pushbutton mode, port 2.7 | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Pull-up disabled, allowing port pin to be repurposed (this port shared with AIN7) | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP27 | I2C2 SDA | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | I2C2 DATA pull-up | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Close this jumper as needed to assure proper termination | |
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| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP28 | I2C2 SCL | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | I2C2 CLOCK pull-up | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Close this jumper as needed to assure proper termination | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP29 | VDDB | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-1 | | | DUT USB XCVR VDDB powered from VBUS regulated with dedicated 3.3V LDO | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-3 | | | USB XCVR VDDB powered full time by system 3V3_PM | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP30 | EXT I2C2 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | QWIIC interface for I2C2 enabled by default | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Open this jumper to place the QWIIC level translator into a high-Z state | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP31 | L/R SEL | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | MIC ON R CH, I2S microphone data stream | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | MIC ON L CH, I2S microphone data stream | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP32 | MIC-I2S I/O | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | External I2S data from I2S I/O header connected to I2S SDI. | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | External MIC data from I2S MIC header connected to I2S SDI | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP33 | MIC-I2S/CODEC | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | Onboard CODEC data connects to I2S SDI | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | External I2S data (mic or slave I2S) from header connects to I2S SDI | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP34 | I2S VDD | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-1 | | | External MIC and DATA I2S interface headers run at 1.8V | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-3 | | | External MIC and DATA I2S interface headers run at 3.3V | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP35 | I2C1 SDA | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | I2C1 DATA pull-up | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Close this jumper as needed to assure proper termination | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP36 | I2C1 SCL | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | I2C1 CLOCK pull-up | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Close this jumper as needed to assure proper termination | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP37 | I2S CK SEL | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | I2S master clock sourced from SMA connector J6 | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | I2S master clock sourced from onboard crystal oscillator | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP38 | DVP CAM PWR | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-1 | | | Sets state of DVP camera PWDN input; default is OFF for OVM7692 | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-3 | | | Sets state of DVP camera PWDN input; 2-3 will power up OVM7692 | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP39 | SW CAM PWUP | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | Camera reset and power up under port pin control | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Digilent P5C camera powered down, JP39 can over ride this condition | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP40 | HW PWUP / SW PWUP | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | Camera will reset and power up as soon as 3.3V reaches a valid level | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Camera reset and power up under port pin control if JP39 is installed; else, camera off | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP41 | CSI CAM I2C EN | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | CSI camera Digilent P5C I2C connects to I2C1 for register setup | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Level translator and I2C PU are in high-Z state; I2C1 disconnected from P5C registers | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP42 | TFT DC | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | TFT data/command select connects to port 2.2 | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Pull jumper if using AIN2 | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP43 | TFT CS | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-1 | | | TFT CS driven by port 0.3, shared with UART0 RTS | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-3 | | | TFT CS driven by port 1.7, shared with DVP DATA 11 and TRIG2 | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP44 | LED1 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | LED0 illuminates when port 2.4 is high | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Pull jumper if using AIN4 | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
| JP45 | LED2 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | LED1 illuminates when port 2.5 is high | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Pull jumper if using AIN5 | |
|
||||
| | | +-----------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
|
||||
|
||||
Programming and Debugging
|
||||
*************************
|
||||
|
|
|
|||
Loading…
Reference in a new issue