drivers: mbox: Add support for TI OMAP mailbox
TI OMAP mailbox is the inter-processor mailbox IP found in TI K3 devices (AM62X, AM64X, J721E .etc). The mailbox hardware uses a queued mailbox interrupt mechanism that provides a communication channel between processors through a set of registers and their associated interrupt signals by sending and receiving messages. The interrupt/bank associated with each processor entity is found through the usr_id property from device tree. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
This commit is contained in:
Vaishnav Achath
Benjamin Cabé
parent
a211999141
commit
fca38adb7f
5 changed files with 265 additions and 0 deletions
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@ -19,3 +19,4 @@ zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_BELLBOARD_RX mbox_nrf_bellboard_rx.
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zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_BELLBOARD_TX mbox_nrf_bellboard_tx.c)
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zephyr_library_sources_ifdef(CONFIG_MBOX_STM32_HSEM mbox_stm32_hsem.c)
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zephyr_library_sources_ifdef(CONFIG_MBOX_IVSHMEM mbox_ivshmem.c)
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zephyr_library_sources_ifdef(CONFIG_MBOX_TI_OMAP_MAILBOX mbox_ti_omap.c)
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@ -23,6 +23,8 @@ source "drivers/mbox/Kconfig.nrf_bellboard"
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source "drivers/mbox/Kconfig.stm32_hsem"
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source "drivers/mbox/Kconfig.esp32"
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source "drivers/mbox/Kconfig.ivshmem"
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source "drivers/mbox/Kconfig.ti_omap"
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config MBOX_INIT_PRIORITY
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int "MBOX init priority"
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9
drivers/mbox/Kconfig.ti_omap
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9
drivers/mbox/Kconfig.ti_omap
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@ -0,0 +1,9 @@
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# Copyright 2024 Texas Instruments Incorporated.
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# SPDX-License-Identifier: Apache-2.0
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config MBOX_TI_OMAP_MAILBOX
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bool "TI OMAP Mailbox driver"
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default y
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depends on DT_HAS_TI_OMAP_MAILBOX_ENABLED
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help
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Driver for TI OMAP Mailbox.
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230
drivers/mbox/mbox_ti_omap.c
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230
drivers/mbox/mbox_ti_omap.c
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@ -0,0 +1,230 @@
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/*
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* Copyright (c) 2024 Texas Instruments Incorporated.
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*
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* TI OMAP Mailbox driver for Zephyr's MBOX model.
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/mbox.h>
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#include <zephyr/irq.h>
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#include <zephyr/spinlock.h>
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#define LOG_LEVEL CONFIG_MBOX_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(ti_omap_mailbox);
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#define DT_DRV_COMPAT ti_omap_mailbox
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#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
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#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
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#define OMAP_MAILBOX_NUM_MSGS 16
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#define MAILBOX_MAX_CHANNELS 16
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#define OMAP_MAILBOX_NUM_USERS 4
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#define MAILBOX_MBOX_SIZE sizeof(uint32_t)
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#define DEV_CFG(_dev) ((const struct omap_mailbox_config *)(_dev)->config)
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#define DEV_DATA(_dev) ((struct omap_mailbox_data *)(_dev)->data)
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#define DEV_REG_BASE(dev) ((struct omap_mailbox_regs *)DEVICE_MMIO_NAMED_GET(dev, reg_base))
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struct omap_mailbox_data {
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DEVICE_MMIO_NAMED_RAM(reg_base);
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mbox_callback_t cb[MAILBOX_MAX_CHANNELS];
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void *user_data[MAILBOX_MAX_CHANNELS];
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bool channel_enable[MAILBOX_MAX_CHANNELS];
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uint32_t received_data;
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struct k_spinlock lock;
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};
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struct omap_mailbox_config {
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DEVICE_MMIO_NAMED_ROM(reg_base);
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uint32_t irq;
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uint32_t usr_id;
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};
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struct omap_mailbox_irq_regs {
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uint32_t status_raw;
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uint32_t status_clear;
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uint32_t enable_set;
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uint32_t enable_clear;
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};
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struct omap_mailbox_regs {
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uint32_t revision;
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uint32_t __pad0[3];
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uint32_t sysconfig;
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uint32_t __pad1[11];
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uint32_t message[OMAP_MAILBOX_NUM_MSGS];
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uint32_t fifo_status[OMAP_MAILBOX_NUM_MSGS];
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uint32_t msg_status[OMAP_MAILBOX_NUM_MSGS];
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struct omap_mailbox_irq_regs irq_regs[OMAP_MAILBOX_NUM_USERS];
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};
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static void omap_mailbox_isr(const struct device *dev)
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{
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volatile struct omap_mailbox_regs *regs = DEV_REG_BASE(dev);
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const struct omap_mailbox_config *cfg = DEV_CFG(dev);
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struct omap_mailbox_data *data = DEV_DATA(dev);
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uint32_t irq_enabled = regs->irq_regs[cfg->usr_id].enable_set;
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uint32_t flags = regs->irq_regs[cfg->usr_id].status_clear;
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regs->irq_regs[cfg->usr_id].enable_set = 0;
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for (int i_channel = 0; i_channel < MAILBOX_MAX_CHANNELS; i_channel++) {
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if (!data->channel_enable[i_channel]) {
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continue;
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}
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if ((flags & MAILBOX_IRQ_NEWMSG(i_channel))) {
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data->received_data = regs->message[i_channel];
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struct mbox_msg msg = {
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.data = (const void *)&data->received_data,
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.size = MAILBOX_MBOX_SIZE,
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};
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if (data->cb[i_channel]) {
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data->cb[i_channel](dev, i_channel, data->user_data[i_channel],
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&msg);
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}
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}
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}
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regs->irq_regs[cfg->usr_id].status_clear = flags;
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regs->irq_regs[cfg->usr_id].enable_set = irq_enabled;
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}
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static int omap_mailbox_send(const struct device *dev, uint32_t channel, const struct mbox_msg *msg)
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{
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uint32_t __aligned(4) data32;
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volatile struct omap_mailbox_regs *regs = DEV_REG_BASE(dev);
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struct omap_mailbox_data *data = DEV_DATA(dev);
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k_spinlock_key_t key;
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if (channel >= MAILBOX_MAX_CHANNELS) {
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return -EINVAL;
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}
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if (regs->fifo_status[channel]) {
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return -EBUSY;
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}
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key = k_spin_lock(&data->lock);
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if (!msg) {
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regs->message[channel] = 0;
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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if (msg->size > MAILBOX_MBOX_SIZE) {
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k_spin_unlock(&data->lock, key);
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return -EMSGSIZE;
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}
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memcpy(&data32, msg->data, msg->size);
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regs->message[channel] = data32;
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int omap_mailbox_register_callback(const struct device *dev, uint32_t channel,
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mbox_callback_t cb, void *user_data)
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{
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struct omap_mailbox_data *data = DEV_DATA(dev);
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k_spinlock_key_t key;
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if (channel >= MAILBOX_MAX_CHANNELS) {
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return -EINVAL;
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}
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key = k_spin_lock(&data->lock);
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data->cb[channel] = cb;
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data->user_data[channel] = user_data;
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int omap_mailbox_mtu_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return MAILBOX_MBOX_SIZE;
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}
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static uint32_t omap_mailbox_max_channels_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return MAILBOX_MAX_CHANNELS;
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}
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static int omap_mailbox_set_enabled(const struct device *dev, uint32_t channel, bool enable)
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{
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const struct omap_mailbox_config *cfg = DEV_CFG(dev);
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struct omap_mailbox_data *data = DEV_DATA(dev);
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volatile struct omap_mailbox_regs *regs;
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k_spinlock_key_t key;
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uint32_t irqstatus;
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if (channel >= MAILBOX_MAX_CHANNELS) {
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return -EINVAL;
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}
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if (enable && data->channel_enable[channel]) {
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return -EALREADY;
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}
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key = k_spin_lock(&data->lock);
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regs = DEV_REG_BASE(dev);
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irqstatus = regs->irq_regs[cfg->usr_id].enable_set;
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if (enable) {
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irqstatus |= MAILBOX_IRQ_NEWMSG(channel);
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} else {
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irqstatus &= ~MAILBOX_IRQ_NEWMSG(channel);
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}
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regs->irq_regs[cfg->usr_id].enable_set = irqstatus;
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data->channel_enable[channel] = enable;
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if (enable) {
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irq_enable(cfg->irq);
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} else {
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irq_disable(cfg->irq);
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}
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static const struct mbox_driver_api omap_mailbox_driver_api = {
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.send = omap_mailbox_send,
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.register_callback = omap_mailbox_register_callback,
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.mtu_get = omap_mailbox_mtu_get,
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.max_channels_get = omap_mailbox_max_channels_get,
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.set_enabled = omap_mailbox_set_enabled,
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};
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#define MAILBOX_INSTANCE_DEFINE(idx) \
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static struct omap_mailbox_data omap_mailbox_##idx##_data; \
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const static struct omap_mailbox_config omap_mailbox_##idx##_config = { \
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DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(idx)), \
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.irq = DT_INST_IRQN(idx), \
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.usr_id = DT_INST_PROP(idx, usr_id), \
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}; \
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static int omap_mailbox_##idx##_init(const struct device *dev) \
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{ \
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DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE); \
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IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), omap_mailbox_isr, \
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DEVICE_DT_INST_GET(idx), \
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COND_CODE_1(DT_INST_IRQ_HAS_CELL(idx, flags), \
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(DT_INST_IRQ(idx, flags)), (0))); \
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return 0; \
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} \
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DEVICE_DT_INST_DEFINE(idx, omap_mailbox_##idx##_init, NULL, &omap_mailbox_##idx##_data, \
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&omap_mailbox_##idx##_config, POST_KERNEL, \
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CONFIG_MBOX_INIT_PRIORITY, &omap_mailbox_driver_api)
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DT_INST_FOREACH_STATUS_OKAY(MAILBOX_INSTANCE_DEFINE)
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23
dts/bindings/mbox/ti,omap-mailbox.yaml
Normal file
23
dts/bindings/mbox/ti,omap-mailbox.yaml
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@ -0,0 +1,23 @@
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# Copyright 2024 Texas Instruments Incorporated.
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# SPDX-License-Identifier: Apache-2.0
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description: TI OMAP MAILBOX
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compatible: "ti,omap-mailbox"
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include: [base.yaml, mailbox-controller.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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usr-id:
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type: int
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required: true
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description: User ID for processor
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mbox-cells:
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- channel
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