Use macros to wrap the interaction between the assembly code and the
struct __cpu_context. This helps making the assembly more readable.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Remove all xPSR-related registers from struct __cpu_context, and the
associated save/restore code in S2RAM code, as they are not needed:
* EPSR and IPSR are read-only - they cannot be "restored"
* Bits N, V, Z, C, V, Q, and GE (if DSP Extension is implemented) of APSR
could be restored, but this is not needed as the AAPCS indicates these
bits to be "undefined on entry to or return from a public interface"
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The currently IPI implementation assumes that CLINT exists in the
system, however, that might not be the case as IPI can be implemented
with PLIC that supports software-triggering as well, such as the Andes
NCEPLIC100.
Refactor the CLINT-based IPI implementations into `ipi_clint.c`, and
create Kconfig that selects the CLINT implementation when
`sifive-clint0` exists and enabled, otherwise default to
`RISCV_SMP_IPI_CUSTOM` which allows OOT implementation. This also
makes way for the upstreaming of non-clint IPI implementation later.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The STKALIGN mask is not present for CONFIG_ARMV8_M_BASELINE as
well as CONFIG_ARMV8_M_MAINLINE. So filter out that check when
setting the sp for ARM core dumps.
Signed-off-by: Mark Holden <mholden@meta.com>
Reset the gp on exception entry from u-mode to protect the kernel
against a possible rogue user thread.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
ramfunc region is copied into RAM from FLASH region during XIP init. We
copy from the loadaddr of the region, and were previously loading to the
symbol __ramfunc_start. This is incorrect when using an MPU with
alignment requirements, as the __ramfunc_start symbol may have padding
placed before it in the region. The __ramfunc_start symbol still needs
to be aligned in order to be used by the MPU though, so define a new
symbol __ramfunc_region_start, and use that symbol when copying the
__ramfunc region from FLASH to RAM.
Fixes#75296
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The FPU is already disabled by the z_arm_svc function when the first
thread starts. Therefore, disabling the FPU at boot is unnecessary for
lazy FPU; instead, it must be enabled to handle floating-point instructions
before the lazy FPU works.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
Gdb is typically able to reconstruct the first two frames of the
failing stack using the "pc" and "lr" registers. After that, (if
the frame pointer is omitted) it appears to need the stack pointer
(sp register) to point to the top of the stack before a fatal
error occurred.
The ARM Cortex-M processors push registers r0-r3, r12, LR,
{possibly FPU registers}, PC, SPSR onto the stack before entering the
exception handler. We adjust the stack pointer back to the point
before these registers were pushed for preservation in the dump.
During k_oops/k_panic, the sp wasn't stored in the core dump at all.
Apply similar logic to store it when failures occur in that path.
Signed-off-by: Mark Holden <mholden@meta.com>
This change was in the same commit previously reverted and seem to be
unrelated and should not be reverted.
Fixes the problem:
..... /swap_helper.S:432:(.text.z_arm_svc+0x26):
relocation truncated to fit: R_ARM_THM_JUMP11 against symbol
`z_arm_int_exit' defined in .text._HandlerModeExit section in
....core/cortex_m/libarch__arm__core__cortex_m.a(exc_exit.c.obj)
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add "memory" to the clobber list"
From GCC 14 the compiler optimizes away memory accesses that do not
impact the asm block. Adding the memory to the clobber list lets the
compiler know that the memory state is to be preserved.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Move the _main argument to the input list rather than the output one on
the asm block and change the spec to "r". The ASM block does not return,
so it does not make sense for it to expect any output.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
To use Xtensa toolchain, various environment variables must be
set so the executables can find necessary files and what core
to compile for. This becomes an annoyance when you have to
test multiple boards with different cores. You have to use
one set of environment variables per core. Twister cannot test
them all in one setting, and it is especially annoying doing
west builds. So enhance the environment variables handling so
that TOOLCHAIN_VER and XTENSA_CORE can be replaced by
TOOLCHAIN_VAR_<board> and XTENSA_CORE_<board> where <board>
is the normalized board target (think <board>.yaml). CMake
will then figure out the core ID for the toolchain to use.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The coprocessor number in ARM `mrc` and `mcr` instructions must be prefixed
with `p`.
GNU assembler allows specifying coprocessor number without the `p` prefix;
but, LLVM assembler is more picky about this and prints out "invalid
instruction" error otherwise.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Added casts to uint32_t in arch_timing_cycles_get() to handle the
wrap-around of the 32-bit cycle counter correctly.
Signed-off-by: Simon Tomschik <simon.tomschik@askgroup.global>
_xtos_pso_savearea and _xtos_core_restore_nw have been renamed to
xthal_pso_savearea and xthal_core_restore_nw in recent Xtensa
toolchains. Rename them in reset_vector.S to prevent linker errors
when building Zephyr with Xtensa toolchain.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
What is changed?
Updated the condition thats prevents mpu config for null dereference.
Added a new check so that mpu is configured for null dereference if
devicetree contains a memory-region node with:
- node address starting at 0
- size covered by the node is more than the null dereference page
size (0x400) and
- contains a memory-attr
Why is the change needed?
The check relied on flash base address to align with 0 for
configuring the mpu for null dereference but, a device tree
could have a flash starting at an address other than 0 and
still need the mpu config for null dereference.
The new extra check provides a way to connfigure mpu for
null dereference even if flash base address is not 0.
Note, though this change helps with mpu config for new boards having
flash address other than 0, this change does not change existing
behaviour for existing boards.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The S2RAM procedure requires marker checking after reset.
Such checking is performed on very early stage of the system initialization
and must ensure that the stack is not used due to the TLS pointer which is
not initialized yet.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
The commit introduced regression for hsdk4xd platform.
The hsdk4xd SoC setup from soc_early_asm_init_percpu need to be done
in early code before any C code execution.
The current approach has multiple issues
- we call function (which can be easily implemented in C for
this or other SoC) from the place where we haven't setup stack
pointer (so we can't use stack) - which is very error-prone
- we never return back from soc_reset_hook on hsdk4xd platform
So let's just revert it for now. If any other ARC SoC need to use
soc_reset_hook - than it can be implemented properly.
This reverts commit 8c32a82e47.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Adds support for cooperative locking/unlocking the VPX vector registers.
Provided that all VPX enabled threads use these routines to control
access to the VPX vector registers, it will allow multiple threads to
safely use them without the need for saving/restoring them upon each
context switch.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Support for R_XTENSA_SLOT0_OP was implemented with a relocation table
test case, containing only one entry at offset 0. For multiple
entries .r_addend has to be taken into account.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
What is changed?
1. Updated the data sync barrier to make sure the other parameters of
`arm_cpu_boot_params` are updated before updating its member `mpidr`
2. Updated the MPIDR affinity level mask to account for affinity level
1 and 2 along with level 0.
Why do we need this change?
1. As reported in issue #76182, on Cortex_A_R, the current code
execution fails to consider the correct sequence of data sync
barrier and cache maintenece for the code to work on non cache
coherent cores in SMP enabled mode.
The secondary cores are waiting in a loop for primary core to set
`arm_cpu_boot_params.mpidr`. As soon as primary core set this,
the secondary cores start reading other parameters from the
`arm_cpu_boot_params` however, the existing position of DSB
instruction doesn't guarantee that `arg`, `cpu_num` and other
parameters of `arm_cpu_boot_params` would be updated before `mpidr`
is udpated and this could lead to a unpredicatble behaviour so,
we need to move the DSB instruction.
2. The affinity level mask is updated because it didn't account for
level 1 to identify individual cores within a cluster and
level 2 to identify different clusters within the system which can
lead to an incorrect conversion between mpidr to core-id.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
What is changed?
Secondary cores can now boot successfully on cache and non-cache
coherent systems if the Zephyr image/vector table is loaded at an
address other than the default address 0x0.
How is it changed?
1. By calling the relocate_vector() from reset.S as part of EL1 reset
initialization instead of prep_c to have VBAR set for all cores and
not just for the primary core.
2. Remove dead code under CONFIG_SW_VECTOR_RELAY and
CONFIG_SW_VECTOR_RELAY_CLIENT.
Why do we need this change?
1. As reported in issue #76182, on Cortex_ar, VBAR is set only for
the primary cores while VBAR for the secondary cores are left with
default value 0.
This results in Zephyr not booting on secondary cores if the vector
table for secondary cores is loaded at an address other than 0x0.
VBAR is set in relocate_vector() so we move it to reboot.c which is
better suited to have configs related to system control block.
2. The two SW_VECTOR_RELAY configs have a direct dependency on
CONFIG_CPU_CORTEX_M, which is disabled while compiling for
Cortex-A and Cortex-R hence leading to a dead code.
How is the change verified?
Verified with fvp_baser_aemv8r/fvp_aemv8r_aarch32/smp.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
This reverts commit ec7943bb18.
This commit introduced a regression.
Let's revert it so we do not block development in main.
For more information see:
https://github.com/zephyrproject-rtos/zephyr/issues/79594
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Gdb is typically able to reconstruct the first two frames of the
failing stack using the "pc" and "lr" registers. After that, (if
the frame pointer is omitted) it appears to need the stack pointer
(sp register) to point to the top of the stack before a fatal
error occurred.
The ARM Cortex-M processors push registers r0-r3, r12, LR,
{possibly FPU registers}, PC, SPSR onto the stack before entering the
exception handler. We adjust the stack pointer back to the point
before these registers were pushed for preservation in the dump.
During k_oops/k_panic, the sp wasn't stored in the core dump at all.
Apply similar logic to store it when failures occur in that path.
Signed-off-by: Mark Holden <mholden@meta.com>
This reverts commit 88f6851a3d.
This is being reverted because it is redundant with the capabilities of
zephyr,memory-region and zephyr,memory-attr properties.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The `CONFIG_PLIC_IRQ_AFFINITY` depends on `CONFIG_SMP` in the
Kconfig layer, nested #ifdef can be avoided for readability.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This commit introduces architecture-specific ELF relocations for RISC-V,
in accordance with the RISC-V PSABI specification:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
Also, the necessary compiler configurations for compiling LLEXT
extensions on RISC-V are added, and the llext tests are executed on
RISC-V targets.
Calling llext extensions from user threads in RISC-V is still
unsupported as of this commit.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
"in behave of" -> "on behalf of", which is more accurate of
what is actually happening in the code.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
- Implement irq-set-affinity in RISCV PLIC.
- Added new affinity shell command to get/set the irq(s)
affinity in runtime, when `0` is sent as the `local_irq`, it
means set/get all IRQs affinity.
- Some minor optimizations
Updated the build_all test to build this new configuration.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Restore the s0 we saved early in ISR entry so it shows up
properly in the CSF.
Signed-off-by: David Reiss <dreiss@meta.com>
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Enable Cortex R8 support, similar to Cortex-R5.
Signed-off-by: Krzysztof Sychla <ksychla@antmicro.com>
Signed-off-by: Marek Slowinski <mslowinski@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
When building LLEXT for Xtensa with custom sections the compiler
can leave unresolved references in them. Then this has to be done by
the LLEXT core during linking. This commit adds linking support for
the L32R Xtensa instruction.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Red zone was causing issues in places where inline assembly was pushing
data to stack, like arch_irq_lock, and possibly in other places.
Initially -mno-red-zone was enabled on x86_64, but was later, maybe
accidentially, disabled in https://github.com/zephyrproject-rtos/zephyr/
commit/b7eb04b3007767be9febe677924918d2422a4406
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Up until now, the `__thread` keyword has been used for declaring
variables as Thread local storage. However, `__thread` is a GNU
specific keyword which thus limits compatibility with other
toolchains (for instance IAR).
This PR intoduces a new macro `Z_THREAD_LOCAL` which expands to the
corresponding C11, C23 or C++11 standard keyword based on the standard
that is specified during compilation, else it uses the old `__thread`
keyword.
Signed-off-by: Daniel Flodin <daniel.flodin@iar.com>
This adds the bits to call into architecture code to dump
the privileged stack for user threads.
The weak implementation is simply there as a stub until
all architectures have implemented the associated function.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For code clarity, remove unnecessary `return` statements
in functions with a void return type they don't affect control flow.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
`CONFIG_MP_NUM_CPUS` has been deprecated for more than 2
releases, it's time to remove it.
Updated all usage of `CONFIG_MP_NUM_CPUS` to
`CONFIG_MP_MAX_NUM_CPUS`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Do not use SYS_INIT for initializing irq_offload when enabled, instead
using a new interface that is called during the boot process for all
architectures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a new call for initializing cache on architectures that need that.
Avoid using SYS_INIT for this and instead call the hook in a fixed place
and run if implemented.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This adds a kconfig to enable making the interrupts
non-preemptible by other interrupts. Enabling this will set
the INTLEVEL to the max non-debug level before clearing
the EXCM bit.
Signed-off-by: Christopher J. Champagne <christopher.j.champagne@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
nocache ram is usually used by DMA to transfer data between
peripherals and ram. Some chips use isolated nocache ram,
which does not necessarily have to be in RAMABLE-REGION.
By specifying the zephyr,nocache-ram options, users can specify
the region where nocache-ram is located. If the user does not
specify it, it defaults to RAMABLE-REGION.
Signed-off-by: Weiwei Guo <guoweiwei@syriusrobotics.com>
Otherwise we can't escape from DEPRECATED being selected, and so getting
build warnings. It doesn't make sense that the option replacing the
deprecated one is used to automatically enable it.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
If adding/removing to the domain of the current running
thread, we need to update the hardware MPU regions or else
the addition or removal would not be reflected to current
running thread.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a spinlock to make sure writing to hardware MPU
regions is atomic, and cannot be interrupted until all
regions are written to hardware.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Fill the memory of all CPU's IRQ stack with 0xAA on init, so
that `z_stack_space_get` can calculate the remaining space
correctly.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Adds support for all relocation type produced by GCC
on AARCH64 platform using partial linking (-r flag) or
shared link (-fpic and -shared flag).
Signed-off-by: Adam Wojasinski <awojasinski@baylibre.com>
If PSCI is enabled, it will leverage psci reset API to achieve system
reboot, otherwise a weak dump reboot API is provided, and platform
can override these APIs if platform specified implementation provided.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Convention is to call k_mem_page_fault() with IRQs enabled if they were
enabled when the fault occurred.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This has two purposes: maintain the accessed and dirty page states, or
call the generic demand paging fault handler otherwise.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
A page table entry used for demand paging is always from the last level
page table and never completely zeroed. Anything else is considered
ARCH_DATA_PAGE_NOT_MAPPED.
Loaded pages use a PTE_PAGE_DESC table entry type. Paged-out pages use a
PTE_INVALID_DESC table entry type and the physical address field is
reused to hold the backing store location token value.
ARCH_DATA_PAGE_ACCESSED corresponds to the AF flag. It is initially
unset and manually set to catch when pages are being accessed and
eventually do something about it.
ARCH_DATA_PAGE_DIRTY corresponds to the lack of the AP_RO flag.
Similarly to the AF flag, pages are initially made read-only to catch
writes.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Let's consider free entries as being completely zeroed. Future patches
for demand paging support will populate entries and still mark them as
"invalid" which should not be considered free. Current code always clear
entries to be freed so no issues there.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
With this commit, it is now allowed to register any ISR and arg
combination for the same IRQ, except the case when the exact same
ISR-arg combination is already registered.
The previous assert logic had a restriction where the same ISR could not
be registered multiple times with different arguments.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The callee-saved-registers can be helpful to debug the state of
a core upon an exception, however, currently there's no way to
access that information in user-implemented
`k_sys_fatal_error_handler()`, even though the csf is already stored
in the stack.
This patch conditionally add a `csf` member in the `arch_esf` when
`CONFIG_EXTRA_EXCEPTION_INFO=y`*, which the `_isr_wrapper` would update
when a fatal error occurs before invoking `z_riscv_fatal_error_csf()`.
Functions such as `k_sys_fatal_error_handler()` would then be able
to access the callee-saved-registers at the time of exception via
`esf->csf`.
* For SoCs that select `RISCV_SOC_HAS_ISR_STACKING`, the
`SOC_ISR_STACKING_ESF_DECLARE` has to include the `csf` member,
otherwise the build would fail.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
On 32-bit x86, it was supposed to print the first argument to
the function during stack trace. However, it only works when
code optimizations are totally disabled (i.e. -O0). As such,
printing the args is not meaningful to aid with debugging.
So change it to simply print the function address, the same
as x86 64-bit.
Also, since unwind_stack() has exactly one caller, make it
ALWAYS_INLINE to skip a function call.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Get rid of the switch statement and use an string array
for the cause instead. This saves about ~600 bytes.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Rename `cause_str` to `z_riscv_mcause_str` and make it non-static,
so that it can be used in user-implemented `k_sys_fatal_error_handler`.
Also, this function should return a constant string, so add `const`
to it.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Relocate the logging of mcause & mtval from `_Fault` to
`z_riscv_fatal_error_csf` so that they are always printed
upon exception.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARC.
Replace soc_early_asm_init_percpu() with platform_reset()
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.
Replace z_arm_platform_init() with platform_reset().
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introduce soc and board hooks to replace arch specific code
and replace usages of SYS_INIT for platform initialization.
include/zephyr/platform/hooks.h introduces the hooks to be implemented
by boards and SoCs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The bits allocated for each aggregator level only need to be enough to
encode CONFIG_MAX_IRQ_PER_AGGREGATOR, instead of the combined number of
IRQs from all aggregators in that level.
Add additional check for L3 interrupts as well, if it is enabled.
Updated the assert in `z_get_sw_isr_table_idx()` to be more verbose.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Add bootargs support to zefi. This implements
get_bootargs() when both efi and bootargs are
selected in config.
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Zefi was only including include/zephyr but not the generated include
directory that contains autoconf.h. This commit fixes that.
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Add bootargs support for multiboot. This
implements get_bootargs() when multiboot and
bootargs are selected in config.
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Add Kconfig option to specify Xen interface version to use. This will
make it easier to switch between different versions of Xen.
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
Add the possibility to disable fault handling in spurious
interrupt handler on RISCs and replacce it with an infinite loop.
Signed-off-by: Magdalena Pastula <magdalena.pastula@nordicsemi.no>
The change of alignment check in #76045 could be wrong and
isn't unnecessary to fix the stack traces output, undo it for
now.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This implements arch_thread_priv_stack_space_get() so this can
be used to figure out how much privileged stack space is used.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the bits to initialize the privileged stack when
a thread is transitioning to user mode. This prevents
information leaking if the stack is reused, and also aids
in calculating stack space usage during system calls.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This implements arch_thread_priv_stack_space_get() so this can
be used to figure out how much privileged stack space is used.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the bits to initialize the privileged stack for
each thread during thread initialization. This prevents
information leaking if the thread stack is reused, and
also aids in calculating stack space usage during system
calls.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This implements arch_thread_priv_stack_space_get() so this can
be used to figure out how much privileged stack space is used.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the bits to initialize the privileged stack for
each thread during thread initialization. This prevents
information leaking if the thread stack is reused, and
also aids in calculating stack space usage during system
calls.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Only set the privileged stack pointer for thread stacks, but
nullify the pointer for kernel-only stacks, as these stacks
do not have the reserved space. The psp pointer may point to
arbitrary memory in this case if stack is not big enough.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a new arch_thread_priv_stack_space_get() interface for
each architecture to report privileged stack space usage. Each
architecture will need to implement this function as each arch
has their own way of defining privileged stacks.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Before commit baa70d8d36 ("arch/arm64/mmu: fix page table reference
counting part 2") it was possible to perform a partial unmap of a block
mapping. Restore that ability and provide a test case to validate it.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This provides memory mappings with the ability to be initialized in their
paged-out state and be paged in on demand. This is especially nice for
anonymous memory mappings as they no longer have to allocate all memory
at mem_map time. This also allows for file mappings to be implemented by
simply providing backing store location tokens.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
