There are 4 Kconfig names about the "Draw Buffer". Rename 'VBD' to 'VDB'
in Kconfig option 'LV_Z_*VBD*_CUSTOM_SECTION' to make name consistent.
config LV_Z_VDB_ALIGN
int "Rending buffer alignment"
config LV_Z_VBD_CUSTOM_SECTION
bool "Link rendering buffers to custom section"
config LV_Z_DOUBLE_VDB
bool "Use two rendering buffers"
config LV_Z_VDB_SIZE
int "Rendering buffer size"
default 100 if LV_Z_FULL_REFRESH
And the draw buffer definition is now:
static uint8_t buf0[BUFFER_SIZE]
#ifdef CONFIG_LV_Z_VDB_CUSTOM_SECTION
Z_GENERIC_SECTION(.lvgl_buf)
#endif
__aligned(CONFIG_LV_Z_VDB_ALIGN);
Signed-off-by: Haiyue Wang <haiyuewa@163.com>
Add support for UDC on highspeed port on these boards:
- ek_ra8m1
- ek_ra8d1
- ek_ra6m5
- ek_ra6m3
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Enable Ethernet controller node and mdio node for RA boards.
Add pinctl for mdio and Ethernet usage
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Gap filling in hex files are now disabled per default, and therefore
there is no reason to explicitly disable gap filling.
It has never been possible to disable gap filling in binary files.
Disabling gap filling would just result in the binary file to be gap
filled with the tool's default value, objcopy=0x00.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
The new update of clock device tree make the pll p q r clock
source cannot be choose by other node
This fix add 1 new dts binding for pll out p q r out line
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
- boards: renesas: Add support for agt.
- drivers: counter: Add support for counter driver use agt
- dts: arm: Add support for agt.
- dts: bindings: Add support for agt counter driver.
- soc: renesas: Add support for agt counter driver.
- samples: drivers: counter: alarm: Add support for RA8
This is initial support with only basic functionality for counter
operation on Zephyr using AGT hardware, current support for
count source is limited to LOCO and PCLKB, other count source
like underflow signal external pin or AGTIO from another AGT
channel will be added in later support
Signed-off-by: Ha Nguyen <ha.nguyen.fz@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Full name was set based on the information available either in board
documentation or in Twister files.
Whenever applicable, vendor name was dropped from the full name so that
all boards have a consistent naming scheme.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Move the process of replacing numerical values with macros to
the header, and set the division ratio in a numeric without
using macros in the device tree.
Change `clk-div` defined in `renesas,ra-cgc-pclk.yaml` to `div`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
DeviceTree typically references the clock source using the `clocks`
property defined in `base.yaml`, so we'll change it to this.
Also delete the custom clock source definitions in
`renesas,ra-cgc-pclk-block.yaml`, `renesas,ra-cgc-pclk.yaml`, and
`renesas,ra-cgc-pll.yaml`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Change the interrupt number of flash in device tree due to duplication
And disable CONFIG_FLASH as default
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
`-` is preferred over `_` in devicetree property names.
Since, change `clk_src`, `clk_div`, and `clk_out_div` to
`clk-src`, `clk-div`, and `clk-out-div`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Initial support for EK-RA8D1 board this commit
only support basic GPIO and Serial driver for
RA8D1 board
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
