Allow the battery voltage to be read through the ADC even if the
CONFIG_STM32_VBAT driver is not enabled.
I guessed this part of code is conditionally compiled depending on
CONFIG_STM32_VBAT because this feature, and hence the
LL_ADC_CHANNEL_VBAT constant is not available on all families. As the
feature is already checked at runtime (as the same driver supports
multiple instances), we can conditionally compile it depending on
LL_ADC_CHANNEL_VBAT instead.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix indentations of `adc_stm32_oversampling` function comments
to have everything aligned properly.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
According to the ES0418 about the ADC of the stm32G071
or other stm32g0x devices:
for sampling time set to 1.5 or 3.5 cycles,
the sampling in a single ADC conversion or in the first
conversion of a sequence takes one extra cycle.
Minimizing to 7.5 is fine.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
There is a build warning of unused `adc_stm32_oversampling_ratioshift`
function: [-Werror=unused-function]. This makes twister fail, as all
warnings are treated as errors.
Fix that by ifndef'ing adc_stm32_oversampling_ratioshift().
Fixes: c57a41c5d2 ("drivers/adc: stm32: do not disable the ADC if
resolution is unchanged")
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
It allows the path for VBATEN on stm32 series
to monitor the Vbat voltage, in case of CONFIG_STM32_VBAT
Add the common Vref value as a property of the ADC.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In case the resolution is already correct (probably the common use
case), do nothing instead of disabling the ADC.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The ADC is currently disabled and re-enabled multiple time during each
read. Enabling the ADC is not a free operation on some series and some
internal channels like VREFINT take even longer. This patch improve the
situation by removing the calls to adc_stm32_enable(), replacing it by a
single call just before triggering the conversion.
This also open the possibility to not reconfigure the ADC if it is
already configured, implemented in the following patches.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Refactor code so that an unused variable 'adc' warning
is not generated when building for CONFIG_SOC_SERIES_STM32G4X
and not using adc1 or adc5.
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
G4 series have specific LL ADC API that discriminate ADC1 and ADC5
channels. Take this into account in adc_stm32_setup_channels().
Additionally, fix this function to use LL defines as argument of macro
__LL_ADC_CHANNEL_TO_DECIMAL_NB, as good practice.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use the devicetree properties to determine if the dedicated temperature or
voltage reference channels should be configured for the ADC.
Fixes#43750.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This change includes special handling of the internal voltage
reference and internal die temperature channels for all currently
defined STM32 models
The code now looks for specific ADC + channel ID pairs instead
of just a channel ID to determine if the caller is trying to
configure an internal channel.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
Some drivers explicitely casted data/config from void * to the
corresponding type. However, this is unnecessary and, in many drivers it
has been misused to drop const qualifier (refer to previous commits).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Clear ADRDY before enabling ADC to ensure the subsequent
wait for ADRDY does not stop prematurely in case ADRDY
was already set.
The "ADC on-off control" sections of the following reference manuals
were consulted. That gives at least one instance per series affected
by this change, even if not every affected MCU is covered.
- RM0438 (STM32L552xx and STM32L562xx)
- RM0351 (STM32L47xxx, STM32L48xxx, STM32L49xxx and STM32L4Axxx)
- RM0434 (STM32WB55xx and STM32WB35xx)
- RM0454 (STM32G0x0)
- RM0440 (STM32G4 Series)
- RM0399 (STM32H745/755 and STM32H747/757)
- RM0433 (STM32H742, STM32H743/753 and STM32H750)
- RM0453 (STM32WL5x)
Signed-off-by: Alexander Mihajlovic <a@abxy.se>
Use a wrapper for LL_ADC_Enable that also waits for ADRDY if required
by the SoC to make sure it's properly enabled everywhere this is done.
Signed-off-by: Alexander Mihajlovic <a@abxy.se>
Certain stm32 soc's have a single shared irq for all adc channels
on those soc's only a single channel is supported.
Added a Kconfig that enables a shared irq for stm32f2x, stm32f4x,
stm32f7x soc's. The shared IRQ uses a flag to limit the number of
interrupts defined to only 1. A shared irq handler is added which
determines which ADC instance the interrupt is for, it then calls
into the existing interrupt.
Signed-off-by: Marius Scholtz <mariuss@ricelectronics.com>
RM 0453: the sw is allowed to write the Oversampling
ratio or shift of the ADC Config.Reg.2 only when ADSTART = 0
(no conversion is on-going). So disabling it will be stopped.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
RM 0453: the sw is allowed to write the Data Resolution bits
of the ADC Config.Reg.1 only when ADEN = 0 (ADC disable).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The PINCTRL_DT_(INST_)DEFINE macros already defined the trailing ;,
making its usage inconsistent with other macros such as
DEVICE_DT_DEFINE.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The STM32 docs state that the ADC may not be calibrated unless
the ADC is disabled (ADEN=0). This commit implements this constraint
Fixes#40936
Signed-off-by: Pete Dietl <petedietl@gmail.com>
The STM32U5x device has ADC instance of different versions
similar to the stm32H7 about the oversampling.
ADC1 of 14bit resolution has a ratio from 1..1024 on OSR[9:0]
ADC4 of 12bit resolution has a ratio on OVSR[2:0]
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit extends the configuration of the oversampling
ratio and shift for the stm32U5xx soc, depending on the
ADC instance: ratio is a value from 1..1024 or a LL_ADC_OVS_RATIO_x
to be used with the stm32Cube LL function.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On the stm32H7 family, there are ADC which have Oversampling ratio
of 10 bits OSVR[9:0] in the CFGR2 register. It means that oversampling
512x or 1024x are possible.
Other values are not allowed as the oversampling field of the struct
adc_sequence (adc.h) is 2^oversampling.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The adc_stm32_oversampling function is used to configure
the ratio and shift for each sequence->oversampling
depending on the soc serie and ADC instance in the serie
In the stm32H7 serie, only ADC3 of ADC_VER_V5_V90 version
have a LL_ADC_OVS_RATIO_x contant (other a 9bit value).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Change the access to the PCSEL register by using the LL function
because on the STM32H7xx soc, some devices have no PCEL register
especially on ADC3 of the stm32H723.
The LL function manages this difference.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Refactors all of the ADC drivers to use a shared driver class
initialization priority configuration, CONFIG_ADC_INIT_PRIORITY, to
allow configuring ADC drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers. The
exceptions are lmp90xxx, mcp320x, and mcux_adc16 drivers which have
dependencies on GPIO, SPI, and/or DMA drivers and must therefore
initialize later than the default device priority.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Setting Oversampling also applies on stm32L5 but disabling
the ADC will cause endless loop except for the stm32L0 serie.
Errata applies only on stm32G0 soc series when
writing ADC_CFGR1 register.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On those STM32 series, setting of this feature is conditioned to
the ADC state: it is allowed to set/reset the oversampler (OVSE bit)
and set the Oversampling ratio (OVSR bits) in the ADC_CFGR2 register
only when ADC is disabled or enabled without conversion on going.
Then is the ADC re-enabled.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On those STM32 series, setting of this feature is conditioned to
the ADC state: it is allowed to write the Data resolution (RES bits)
in the ADC_CFGR1 register only when ADC is disabled (ADEN=0).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The LL_ADC_ConfigOverSamplingRatioShift function for
the stm32H7xx soc serie differs from other for the 'ratio':
"This parameter can be in the range from 1 to 1024"
Note that in the stm32h7xx_ll_adc.c the LL_ADC_OVS_RATIO_xxx value is
defined for ADC of type ADC_VER_V5_V90.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The STM32 G0, G4, H7, L0, L4, WB and WL series have hardware support for
oversampling. This patch adds support for it, using the oversampling
value provided in the adc sequence. The result is shifted right
accordingly to not change the resolution of the measured value, like it
is done on other ADC drivers.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Commit c045cbd336 added support for internal voltage reference source,
but in practice only the temp sensor is supported. Fix that.
Also change the code to keep the existing paths so that VREFINT and
TEMPSENSOR can be used at the same time.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The patch fixes driver compile errors and ADC management for the f3x
series. It was developed and tested for the stm32f373 variant.
Tested-by: Dario Binacchi <dariobin@libero.it>
Signed-off-by: Dario Binacchi <dariobin@libero.it>
The STM32H7 series has a special ADC, which is calibrated
on the factory. The calibration values are stored in flash
and must be retrieved upon powering up the device.
Failure to calibrate the device leads to missing codes in
the ADC readings.
Fixes#35529
Signed-off-by: Lasse Sangild <lsangild@gmail.com>
Since we removed various series headers, move stm32 driver
under main driver/pinmux folder.
Take this change into account into various drivers.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add ADC support for the STM32WL family, this seems to work following
most of the L0X code path.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
This commit it to resolve following bugs:
* Operands don't affect result.
* Logical dead code in stm32_adc driver.
Above mentioned bugs were solved by adding parenthesis and
changed the method of comparing. Since comparison of ADC
channel_id with the channel may cause loss of value.
So instead of direct comparison, introduced a mechanism to
convert channel constant to a decimal using
__LL_ADC_CHANNEL_TO_DECIMAL_NB() and strips away
the INTERNAL_CH bit and then compare with channel_id.
fix:
* zephyrproject-rtos/zephyr#35130
* zephyrproject-rtos/zephyr#35136
Signed-off-by: Affrin Pinhero <affrin.pinhero@hcl.com>
Convert from device_get_binding to DEVICE_DT_GET. In doing this we
no longer need the label in the devicetree node so we remove that.
Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
For multiple channels detection, channels variable was compared with
the output of find_lsb_set which actually is a decimal number.
Since channel is a bitfield the comparison was not behaving as
expected (detecting several channels while only one channel was used).
Rework the code to use the already existing bitfield "index" for
the test.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The STM32 driver currently does not support reading a sequence of
multiple ADC channels. Only the first channel of the sequence was
read and the rest was silently ignored.
Fix: Return an error if reading multiple channels is requested.
Signed-off-by: Martin Jäger <martin@libre.solar>
Adds support for ADC on G0 series.
Simple implementation: sequencer not fully configurable,
and only one common sampling time.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Convert adc drivers to use new DT variants of the DEVICE APIs.
DEVICE_AND_API_INIT -> DEVICE_DT_DEFINE
DEVICE_GET -> DEVICE_DT_GET
DEVICE_DECLARE -> DEVICE_DT_INST_DECLARE
etc..
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Set stm32_dt_pinctrl_configure function as the unique entry point
to STM32 DT pinctrl management.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The driver-specific config_info structure referenced from the device
structure is marked const. Some drivers fail to preserve that
qualifier when casting the pointer to the driver-specific structure,
violating MISRA 11.8.
Changes produced by scripts/coccinelle/const_config_info.cocci.
Some changes proposed by the script are not included because they
reveal mutation of state through the const pointer, though the
code works as long as the driver-specific object is defined without
the const qualifier.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.
Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.
To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:
- emit macros for all existing nodes in gen_defines.py, regardless
of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add support for ADC on H7 series. Note that ADC1 and ADC2 share the same
register set, so it is added as "adc1_2".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Make drivers multi-instance wherever possible using DT_INST_FOREACH.
This allows removing DT_HAS_DRV_INST in favor of making drivers just
do the right thing regardless of how many instances there are.
There are a few exceptions:
- SoC drivers which use CMake input files (like i2c_dw.c) or otherwise
would require more time to convert than I have at the moment. For the
sake of expediency, just inline the DT_HAS_DRV_INST expansion for
now in these cases.
- SoC drivers which are explicitly single-instance (like the nRF SAADC
driver). Again for the sake of expediency, drop a BUILD_ASSERT in
those cases to make sure the assumption that all supported SoCs have
at most one available instance is valid, failing fast otherwise.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Like other STM32 series the STM32L4x SoCs have an internal voltage
reference source that need to be enabled.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Convert older DT_INST_ macro use in STM32 drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The build infrastructure should not be adding the drivers subdirectory
to the include path. Fix the legacy uses that depended on that
addition.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Fix clock setup for stm32 f3, l4, wb and g4 series.
The macro __LL_ADC_COMMON_INSTANCE() is called without argument, which
leads to a compile error. Fix by passing adc parameter.
Signed-off-by: Thomas Schmid <tom@lfence.de>
The adc_stm32 driver used system timer frequency as a base for
busy-wait delay calculation. This commit corrects that by obtaining
the needed value from SystemCoreClock variable.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
move adc.h to drivers/adc.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Per guidelines, all statements should have braces around them. We do not
have a CI check for this, so a few went in unnoticed.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit adds driver support for ADC1 on all 8 supported series of
stm32 with resolution and conversion time selection and calibration.
Currently DMA is not supported for all series, and without it, zephyr
won't be able to catch up ADC's end of conversion interrupt, so this
version of the driver supports one channel conversion only. Users want
multi-channel conversion should use multiple sequences in their app
code.
This driver uses LL lib rather than HAL because the current HAL lib for
ADC will call HAL_DMA_* functions rather than using zephyr's common DMA
interface, so that way the driver will break the consistency of the
code.
This driver has been tested on multiple nucleo boards including
NUCLEO_F091RC/F103RB/F207ZG/F302R8/F401RE/F746ZG/L073RZ/L476RG and all
passed the test cases in tests/drivers/adc/adc_api. If the external ADC
line is floating, it may fail the tests since ADC may get 0V and the
test cases think 0 is failing. Connect it to any voltage source between
0-3.3V will help passing the test cases.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
