Enables the fractional-N (FRACN) setting for PLL1 in the STM32H5XX
clock driver.
This feature allows achieving a system clock frequency of 250 MHz from
an 8 MHz `clk_hse`.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Support specifying divided clock buses by introduction of
STM32_CLOCK_DIV(div) macro. This macro can be used in devicetree to define
clock source of peripherals.
HSE is selected in devicetree using:
<&rcc STM32_SRC_HSE ...>;
HSE/2 can now be selected with:
<&rcc (STM32_SRC_HSE | STM32_CLOCK_DIV(2)) ...>;
This allows to use clock_control_get_rate() API in peripherals in order to
get desired clock rate.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Rely on the DTS to get the MCO input source clock and prescaler.
DTS configuration has been introduced and Kconfig method
deprecated two releases before and can be then safely removed.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Remove address-of operator ('&') when assigning `clock_control_xxx_init`
function pointer in `DEVICE_DT_INST_DEFINE` macro.
This change aims to maintain consistency among the drivers in
`drivers/clock_control`, ensuring that all function pointer assignments
follow the same pattern.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This commit removes unnecessary initialization of the local variable
where its value is guaranteed to be overwritten by subsequent operations.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Use a code spell-checking tool to scan and correct spelling errors in
the following files:
- clock_stm32_ll_common.c
- clock_stm32_ll_h5.c
- clock_stm32_ll_h7.c
- clock_stm32_ll_u5.c
- clock_stm32_ll_wba.c
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Make clock_control_on for STM32 behave the same as the HAL,
delaying after enabling peripheral clocks. Otherwise it may return
before the clock is actually enabled, causing subsequent writes to
peripheral registers to be silently ignored.
Signed-off-by: Kevin ORourke <kevin.orourke@ferroamp.se>
Set the correct VCO input range for the PLL frequency
with each bit PLL1RGE of the PLL1CFGR register
This get_vco_input_range is similar to the stm32h7 one.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
STM32H5 series lacked support for MCO configuration.
Added SOC_SERIES_STM32H5X to approperiate kconfig MCO source
configurations. Added new MCO sources from H5 series and
updated the clock_stm32_ll_h5.c with MCO configuration.
Signed-off-by: Kacper Dalach <dalachowsky@gmail.com>
When the image is chain-loaded, clocks may already by initialized.
The driver was lacking support for already configured HSE and
PLL sources. When CONFIG_ASSERT=y get_startup_frequency was
failing since it did not recognize these sources.
It's the same issue that was addressed in #58109 for stm32u5.
Signed-off-by: Kacper Dalach <dalachowsky@gmail.com>
According to the stm32h5x product specifications, the values of the
voltage ragulator depends on the system clock as follows:
• VOS0 (Vcore = 1.35V) with CPU and peripherals running at up to 250 MHz
• VOS1 (Vcore = 1.2V) with CPU and peripherals running at up to 200 MHz
• VOS2 (Vcore = 1.1V) with CPU and peripherals running at up to 150 MHz
• VOS3 (Vcore = 1.0V) with CPU and peripherals running at up to 100 MHz
Signed-off-by: Francois Ramu <francois.ramu@st.com>
If clock frequency was already high and a ahb prescaler greater than 1
was used frequency could temporary become higher than allowed.
Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>
By default HSIDIV is set to 0x01, so default frequency is 32 MHz.
This register should be always set based on dts value.
Signed-off-by: Wojciech Slenska <wsl@trackunit.com>
Add the driver for the clock control of the new stm32h5.
See the corresponding Ref Man to get the clock scheme :
HSI, CSI, HSI48, HSE, LSE, and 2 or 3 PLLs
Signed-off-by: Francois Ramu <francois.ramu@st.com>
