The commit adds support for testing non-explicite-erase
device on Flash Simulator. This is addition to already supported
explicit erase before write, aka Flash, type of device behaviour.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The commit adds two new API calls:
- flash_fill - that allows to fill selected part of device with
specified value;
- flash_flatten - that allows to erase or fill device with
erase_value, depending on whether driver for the device provides
erase callback.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The commit adds and no_explicit_erase capability to flash_parameters,
that indicates whether device is program-erase type device; such
devices, like Flash type devices, require erase prior to writing
random data at any previously programmed location.
This capability should only be set by drivers.
The flash_params_get_erase_cap() function has been added, for parsing
flash_parameters object to obtain erase capabilities of device.
The function returns capabilities as combination of bits representing
them. Currently it will return:
0 -- no erase capabilities
FLASH_ERASE_C_EXPLICIT -- erase required before write of random data.
Additional capabilities have been reserved but are not yet used.
There are following Kconfig options added:
FLASH_HAS_EXPLICIT_ERASE
FLASH_HAS_NO_EXPLICIT_ERASE
that should be selected by device driver to indicate whether
devices served by driver needs erase prior to write.
The above Kconfigs are used to figure out whether app is built
for hardware that requires erase prior to write.
They can be also used to detect that it is attempted to build
some subsystem that will not work with provided hardware, for example
file system that has not been prepared to work with devices that
do not require erase.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
This change is aborting the memoryMapped mode of the octo-flash
before erasing or writing the NOR. Operations are performed in
command mode.
Reading is always performed in MemoryMapped mode (memcopy)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Enable the MemoryMapped Mode for the stm32 octoFlash driver
Configure the Flash in MemoryMapped to use in XiP mode.
With this mode the erase and write are not supported.
Address and size are given by the DTS register property.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.
Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.
Updated the includes path of in-tree sources accordingly.
Most of the changes here are scripted, check the PR for more
info.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Check the return values of commands such as spi_nor_cmd_* and
spi_nor_wait_until_ready and ensure they are propagated back to the
caller on error.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The commit removes unneeded check for enter_4byte_addr_exist in
the function, as the utility function is supposed to set the address
by parsing enter_4byte_addr parameter, while the enter_4byte_addr_exist
used to exist only for DTS entries that directly set enter-4byte-addr
parameters for a flash node.
The change also moves LOG_DBG reporting enter_4byte_addr before
it is processed, to allow logging what actually function will be working
with, before it does so.
The enter_4byte_addr_exist is removed as it is no longer used anywhere.
Setting of data->flag_access_32bit has been moved in the same code block
as call to the spi_nor_cmd_write, as it can be only consequence of
successful call to that function.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
This block of code was in the original commit that added
CONFIG_SPI_NOR_IDLE_IN_DPD but later modifications
added acquire_device() and release_device() calls
earlier in spi_nor_configure() and the release_device()
function will have already done the enter_dpd().
Signed-off-by: Mike J. Chen <mjchen@google.com>
In simulated targets the RRAM is not allocated
starting at address 0x0, but on an area allocated
at runtime.
Let's support this, to enable running the
real RRAM driver for simulated targets.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Implement more robust handling for legacy SFDP tables, which may not
implement some of the JEDEC defined DWORDS for SFDP data. Instead of
failing to probe/initialize the flash when these DWORDS are not defined
in the basic flash parameter table, revert to sane defaults for SPI
flash.
Fixes#72051
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This puts the QSPI peripheral into memory-mapped mode when
CONFIG_STM32_MEMMAP is set. Writes and erase put it back into indirect
write mode.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
This CONFIG_STM32_MEMMAP is for enabling the MemoryMapped mode
on external octo or quad spi memory.
In this case, the flash_stm32_read is done in mem map mode
the flash_stm32_erase is not available.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Some stm32 devices with quadspi (like stm32l47x or stm32l48x)
does not support Dual-Flash Mode. Avoid building error even if
the &quadspi node has a <flash-id> property defined.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduce a XSPI driver to cover the common XSPI peripherals
of the stm32 mcu: X is for single or quad or octo or hexa
SPI bus access to external memories
DMA not supported in this version
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Select that the STM32 driver has extended operations feature when
the FLASH_STM32_BLOCK_REGISTERS is set.
It allows using only block registers extended operation.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
FLEXSPI nor driver uses several LUTs for "scratch" commands during the
SFDP probe phase that are not needed once the flash is configured. Set a
second "end" marker we can use to configure the FLEXSPI MEMC driver, so
that we can indicate the true number of LUTs needed by this driver when
init is completed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The clk, dqs and ncs pins can be remapped between OSPI instances, but the
driver doesn't support it, yet. Therefore replace hard coded numbers to
device tree optional properties.
Signed-off-by: Samuel Kleiser <s.kleiser@vega.com>
This commit adapts the Ambiq flash controller to support the Apollo3
SOC (e.g. Apollo3 Blue, Apollo3 Blue Plus).
Also uses the Zephyr common IRQ API to replace the Ambiq HAL ones.
Signed-off-by: Aaron Ye <aye@ambiq.com>
The esp_flash*() functions don't return
negative errno codes, so it's return value
should not be used for the flash api functions.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Non-secure images cannot reference NRF_RRAMC_NS because NRF_RRAMC_NS
does not exist.
TF-M will configure RRAMC according to these Kconfig's before booting
the non-secure image so we ifdef out this code.
Also, rewrite the implementation of commit_changes to also work when
the commit task is not available.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Fix incorrect note that write only allows to change value of
bit to zero, where proper information is that change is only allowed
from erase-value to the opposite.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The commit adds missing binary or in write operation.
Assuming that program-erase devices only allow switching bits
from erase-value to opposite, in case of 0x00 erase value device
only ones can be written.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
This commit removes unnecessary usage of the `ARG_UNUSED` macro and
unnecessary initialization of the `ret` variable where its value is
guaranteed to be overwritten by subsequent operations.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Use the most adapted instruction for the sector erase command
It can be 0x20 or ox21 or 0x21DE in octo - DTR mode.
The value is given by the SFDP table and filled in the erase_types
table the during the SFDP discovery process.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The commit adds dependency on Kconfig FLASH_PAGE_LAYOUT to subsystems
that really require it:
FCB, NVS, LittleFS
and removes direct selection from '*.conf' files where no longer
needed.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
It is impossible to perform flash reads during a flash write. When the
data to write to flash lies in the flash itself, it is buffered in ram
before writing.
Signed-off-by: Lukas Gehreke <lk.gehreke@gmail.com>
Use `pm_device_driver_init` to ensure that init is run correctly
regardless of the power state.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
There has been missing line initializing the hold pin,
which caused SPI NOR device init to fail with -ENODEV,
if property defining such pin has been present in device
definition.
Fixes#70661
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Modify the SPI Nor driver to be able to have multiple instances at
the same time.
This patch is heavily inspired by the at45 driver.
It was tested on the nRF5340 DK by using the external spi memory two times.
Macros were improved by de-nordic
Signed-off-by: Mehdi Zemzem <mehdi.zemzem2@gmail.com>
The nrfx_qspi driver in nrfx 3.4.0 started checking conditions that
could trigger anomaly 159 on nRF5340 so make sure that QSPI transfers
are only performed with properly configured clocks (PCLK192M undivided
and HCLK128M divided by 2).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add new devicetree bindings for F4 and L1 series for configuration of
block size used in flash write operations.
Allow byte-size write operations in `flash_stm32f1x.c`. This file is
being shared between F0, F1, F3, L0 and L1 series. L0 and L1 series
allows for single byte writes.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
Add Nuvoton numaker series flash memory controller(RMC) with erase,
read & write features of soc-flash.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
HAL_OSPI_AutoPolling is checking is the status match
happened in a busy loop. That CPU intensive operation
can cause starvation of other tasks especially on flash
erase operations which can take seconds to complete.
So, replace the use of HAL_OSPI_AutoPolling with
HAL_OSPI_AutoPolling_IT. The match results
HAL_OSPI_StatusMatchCallback being called.
Signed-off-by: Miika Karanki <miika.karanki@vaisala.com>
Opcodes for erase is taken from jedec basic flash parameter table
These expects 3 byte addresses.
When running with 4 byte addresses, opcodes to be used shall be taken
from JEDEC 4-byte Address Instruction Parameter table
Signed-off-by: Brian Juel Folkmann <bju@trackunit.com>
Adds conditional usage of locking mechanisms to allow building
without multithreading.
Signed-off-by: Mateusz Michalek <mateusz.michalek@nordicsemi.no>
Now RRAMC is set to use up to 512 B burst writes by default as most
time effective.
Requested slot time was changed to 8000 us for that case, as this is
required in order to hold the longest write operation.
Drivers differs slot duration depending on configured RRAMC buffers count
(CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE).
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
When radio-synchronization was on
(CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE=n) context of writing was shifted
by 4 instead of write-length (this caused redundant, self-shortening
writes to the same block.)
write-len was unset when requested write len was less than
RRAM_MAX_WRITE_BUFFER.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Added synchronization with BLE radio operation to the RRAM flash
driver. The implementation is using framework which is already
provided for nrf52's flash driver.
Additional added resource locking mechanism while driver does writing
which solves mutual exclusion write access problem.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Added a simple driver for RRAM. It is implemented as a flash driver,
because the "RRAM eFlash" macro obeys flash-like constraints.
Although users are not required to erase before write.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Address and size are given by the DTS register property
of the qspi nor : to be used by the qspi driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Address and size are given by the DTS register property
of the ospi nor : to be used by the ospi driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Support SFDP probe in flexspi nor driver. This probe will allow the
flash driver to dynamically configure quad spi flashes for 1-4-4 mode,
expanding the flash chips supported with this driver.
The following data is read from the SFDP header:
- quad enable method
- fast read command (1-4-4 is maximum supported)
Fixes#55379
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking the FlexSPI on NXP iMX RT10XX. This
functionality requires an SOC specific clock function to set
the clock rate, since the FlexSPI must be reset directly
before applying the new clock frequency.
Note that all clock constants are defined in this commit, since the
memc flexspi driver now depends on a clock node being present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
For the flash driver, the base address is the MCU internal flash
address (usually 0x8000000). This PR gets the that address
from the device tree node "st,stm32-nv-flash"
instead of relying on the CONFIG_FLASH_BASE_ADDRESS
which might differ when building for another flash memory.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This file uses several functions which are extensions to the the
std C library. Let's explicity select one of the extensions
which includes it instead of relaying on somebody having
set it for this file somewhere else.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The implementation uses the same approach as STM32F1x.
Program/erase speed can be set by setting 'write-block-size' flash
property to 1, 2, 4 or 8.
Signed-off-by: Patryk Duda <patrykd@google.com>
Provide different loop delays to `wait_until_ready` based upon the
operation that we are waiting for.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Don't monopolise the CPU in `spi_nor_wait_until_ready`. For slow flash
chips, operations can take minutes (Full chip erase on MX25R is listed
as 120s typical, 240s max).
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This commit updates the driver to use the flash layout pages,
rewriting it to utilize the flash_page_layout.c driver to
avoid duplicate code.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Adjusted the code to guarantee resource release irrespective of operation
success or failure.
Fixes#67336
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This is a follow-up to commit ea1be7f242.
After the driver performs its initialization, it needs to deactivate
the QSPI peripheral. Otherwise, the peripheral would unnecessarily
consume power until some QSPI operation is performed (and only then
it will get deactivated), what depending on the application may take
a significant amount of time.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Added Kconfig assignment of qspi timeout.
Per nrfx v3.2 addition of qspi timeout in config
struct.
Signed-off-by: Kelly Helmut Lord <kellyhlord@gmail.com>
This fix adds the STM32L4P5xx to the list of devices that have an
offset-to-page shift calculation of 12 bits. Previously, the driver
would only shift the offset by 11 bits when calculating the page to
erase.
This would prevent the driver from erasing the correct page.
Signed-off-by: George Beckstein <george.beckstein@ampaworks.com>
Erase operation with block of 64KByte
larger size than the default 4K sector size
if the flash supports.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When Bluetooth is enabled, it is required to arbitrate flash accesses
between RF and write accesses (for user activity).
A dedicated flash manager is provided as part of STM32WBA BLE lib.
Implement a dedicated driver using FM Apis to handle RF activity.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Boot into the deep power down state when `SPI_NOR_IDLE_IN_DPD` is not
enabled. DPD is the correct hardware state for the `SUSPENDED` software
state. Without this change, it takes a cycle of
`SUSPENDED->ACTIVE->SUSPENDED` to get to the low power state.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
STM32U5X has 128k/256k/512k/1M/2M dual bank Flash.
The address of the 2 bank are continuous, so it's no need a "Dummy page"
in "stm32_flash_layout", which cause wrong slot1 section (for secondary
image), and the BANK2_OFFSET is not right either, which cause
"flash_stm32_valid_range" return a failure.
To fix the issue, just set CONFIG_FLASH_SIZE to STM32_SERIES_MAX_FLASH
Tested on NUCLEO-U545RE with mcuboot.
Signed-off-by: Weifeng Li <weifeng.li@aofrio.com>
So far the driver first changed the configuration of the flash chip
and after that checked the signature of that chip. This could lead
to improper change of the chip configuration if the actually found
one was different than that specified in devicetree.
This commit reverses the order of these two initialization steps and
also restructures a bit the initialization code.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
After integration of nrfx 3.2.0, it is no longer needed to deinitialize
the nrfx_qspi driver to avoid increased power consumption when the QSPI
peripheral is idle. Now it is enough to call `nrfx_qspi_dectivate()`
when a given operation is done. The driver will automatically activate
the QSPI peripheral again when a next operation is requested.
This commit applies the following changes:
- `qspi_device_init` and `qspi_device_uninit` functions are replaced
by `qspi_acquire` and `qspi_release`, respectively; those handle
exclusive access to the QSPI peripheral and deactivation of it or
runtime device power management
- locking is removed from `qspi_send_cmd` as it is the resposibility
of the caller of that function
- `trans_lock` and `trans_unlock` functions are removed together with
the related semaphore as they are no longer needed
- checking of input parameters is moved from `qspi_erase` to its
caller, `qspi_nor_erase`
- `qspi_nor_pm_action` is refactored to properly handle locking of
the QSPI peripheral; checking of the `xip_enabled` flag is removed
from that function as now the call to `pm_device_is_busy()` covers
that (when XIP is enabled, the device is kept indicated as busy)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Consistently use `res` for results of calls to nrfx functions
and `rc` for Zephyr return codes, to avoid mixing up those two
and for example calling `qspi_get_zephyr_ret_code()` for a value
that is already a Zephyr return code. Correct also such call in
`qspi_nor_write()`.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
After entering the Deep Power-down mode, some flash chips ignore all
commands except from the one that releases the chip from the DP mode
and it is not possible to successfully read their Status Register then.
Since the QSPI peripheral tries to read this register when it is being
activated, it consequently fails to send the actual command that would
release the flash chip from the DP mode if that is to be done right
after QSPI initialization.
Prevent this problem by performing the QSPI activation with all pins
disconnected. This causes that the Status Register value is read as
all zeros and allows the activation to always finish successfully,
and the RDPD command to be properly sent.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Do not enable subsystem/driver shell modules by default and stop abusing
CONFIG_SHELL_MINIMAL, which is internal to the shell subsystem, to decide
when to enable a driver shell.
The list of shell modules has grown considerably through the
years. Enabling CONFIG_SHELL for doing e.g. an interactive debug session
leads to a large number of shell modules also being enabled unless
explicitly disabled, which again leads to non-negligible increases in
RAM/ROM usage.
This commit attempts to establish a policy of subsystem/driver shell
modules being disabled by default, requiring the user/application to
explicitly enable only those needed.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This CL is to minimize `CONFIG_SOC_SERIES_XXXX` definitions when we
introduce a new chip series. Most of them are relevant to register
layouts in different npcx soc series. It moves soc-specific register
definitions from `reg_def.h` to its own soc.h file.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Care must be taken to avoid any flash access while programming the flash
attached to the FlexSPI either via executing XIP code or reading RO data.
Remove locations where a constant device pointer might be dereferenced
within the mcux_flexspi_nor driver, to help avoid RWW hazards.
Fixes#64702
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The way that the QSPI peripheral is activated has been changed in
nrfx 3.2.0. Now the peripheral is not activated during the driver
initialization. Instead, the driver activates the peripheral when
the first operation is requested or when `nrfx_qspi_activate()` is
called. In case of XIP, the latter needs to be used, as there may
be no standard operation request.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Fix the SFDP command to be sent by the qspi driver
to get the SFDP table from the NOR quad flash.
Note that CONFIG_FLASH_STM32_QSPI=y and CONFIG_SPI_NOR=n
HAL_DMA_Abort declared as weak to fix compilation error with stm32f7x
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Move the syscall_handler.h header, used internally only to a dedicated
internal folder that should not be used outside of Zephyr.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In the CONFIG_SPI_NOR_SFDP_MINIMAL configuration this value is hard
coded to 256 bytes. Make it configurable via devicetree.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
changes enable flash driver to provide api interface to send reset memory
spi command to the spi flash. The reset memory command would bring the
spi flash to its default power-on state and loose all the volatile register
settings.
Flash reset is needed when more than one controller access the flash chip
in a shared mode.
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com>
Because shadow variable warning is turned on, a warning was thrown and
could fail some twister tests that don't use the -W option. This commit
gets rid of the warning.
Signed-off-by: David Corbeil <david.corbeil@dynon.com>
Replace Nuvoton NPCX series definitions with new Kconfig definitions in
the npcx drivers. The benefit of this approach is that we won't touch
the npcx driver sources again during introducing a new npcx series next
time.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Update interface of memc flexspi driver to better handle multiple
devices. Previously, using multiple devices on one FlexSPI bus would
require the user to configure each device to install its command table
(referred to as a LUT table by the driver) at an offset, so that it did
not overlap with other devices on the bus.
This commit changes the interface of the memc flexspi driver to instead
configure the LUT and flash device in one call. This allows the memc
driver to record the port each LUT sequence is used with, so that
future FlexSPI transfer requests can have their LUT offsets adjusted
based on the target port (which will correspond to a target device)
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
rand32.h does not make much sense, since the random subsystem
provides more APIs than just getting a random 32 bits value.
Rename it to random.h and get consistently with other
subsystems.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Per the MX25UM51325G datasheet, all page programs in OPI DTR mode need to
start at an even address, and be of even length. Update the minimum
write size reported by the driver and check all writes when OPI DTR mode
is enabled, so that subsystems using the flash driver can align to this
requirement.
Fixes#63639
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adjusted the prompt of the load command to make it more obvious that
the user is being prompted for keyboard input.
Signed-off-by: Kelly Helmut Lord <helmut@helmutlord.com>
Add "st,stm32-flash-controller" as compatible for STM32H7 so that
what is defined for STM32 in general is also defined for STM32H7.
Already most of the other STM32 versions have this addition.
Also removed the specific STM32H7 flag check in
/flash/driver/Kconfig.stm32.
Signed-off-by: Stefan Petersen <spe@ciellt.se>
Drivers for nRF SoCs using pinctrl did not select PINCTRL. This means
boards are forced to enable PINCTRL.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Manufacturer id is skipped when reading jedec_id, due to wrong
address mode.
Before: flash_stm32_ospi: Jedec ID = [60 20 00]
After: flash_stm32_ospi: Jedec ID = [ef 60 20]
Signed-off-by: Brian Juel Folkmann <bju@trackunit.com>
Adds support for forcing XIP support at boot time, and reduces the
init priority of the driver so that it inits earlier.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fix compilation error on variable used for size of array in
OSPI and QSPI drivers.
Fixes#61804
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Fix a few issues with the reset-gpio functionality in spi_nor, missing
header, missing semicolon, unnecessary and not working condition on a
struct field that is not a pointer.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Move workaround methods for npcx series to soc init functions. If
there's no workaround for this series, drop its soc.c file directly.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces new Flash Interface Unit (FIU) hardware in npcx4
series. The different operations of npcx9 and npcx4 FIU include:
1. 4-byte mode support for DRA mode move to SPI_DEV reg
2. To access the second flash in DRA mode, we need to configure
SPI_DEV_SEL field in BURST_CFG additionally.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Due to source data pointer having no alignment constraint,
extra care needs to be taken when reading source data
as dword
Signed-off-by: Tomislav Milkovic <tomislav.milkovic95@gmail.com>
Commit slters z_impl_nrf_qspi_nor_xip_enable to not call
qspi_device_init in case when xip_enabled has the same value
as requested.
In case when qspi_device_init returns non-zero no further actions
are taken and xip_enabled will not be to set requested value.
Fixes#59535.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Removed single offset alignment check mechanism and replaced it with
offset alignment check for each iteration
Signed-off-by: Madhurima Paruchuri <mparuchuri@google.com>
The spi_nor erase op selection was based on the alignment of the end of
the region to be erased. This prevented larger erase operations being
selected in many cases
Closes#60904
Signed-off-by: Joshua Crawford <joshua.crawford@levno.com>
Modify the NPCX driver erase method to allow 0x1000 byte size erases
along with 0x10000 byte size erases based on input parameters
Signed-off-by: Madhurima Paruchuri <mparuchuri@google.com>
Most implementations have the same logic, with only a different write
block size. Now that we are using write-block-size from the device tree,
it is possible to use a default implementation that can be overridden if
necessary.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
STM32L5 have a write block size of 8, but STM32U5 and STM32H5 have a
write block size of 16. Convert write_dword() and
flash_stm32_write_range() to write write-block-size data at a time.
Fixes#60724
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
STM32L5 have a write block size of 8, but STM32U5 and STM32H5 have a
write block size of 16. Use write-block-size from the device tree
instead of hardcoding this value when validating the range of write
operations.
Fixes#60724
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
Add support for flash NOR memory devices on a NXP S32 QSPI bus. The
driver uses a fixed LUT configuration assuming a default standard page
size and erase types, and allows to select between multiple read/program
instructions/modes. It is also possible to read the flash device
characteristics from the device at run-time as long as the memory is
JESD216 compatible, providing more flexibility.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add Nuvoton numaker series flash memory controller(FMC) with erase,
read & write features of soc-flash. Also update Nuvoton manifest
to include zephyrproject-rtos/hal_nuvoton#6.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Flash API states that drivers should support write requests without
any restrictions on location or alignment of the source buffer.
Due to hardware limitations of the QSPI peripheral, the nrf_qspi_nor
driver currently fails to perform a write from a RAM buffer that is
not word-aligned. Fix this by using in such case the same mechanism
that is used when the source buffer is located in the internal flash
(copy data to a buffer located on stack).
Also correct the length parameter for writes from this stack-based
buffer to be the actual data chunk length, not always the size of
the buffer (as for CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE > 4
this may lead to overwriting of some data located next in the flash).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Refactor the part of the flash simulator that interacts with the
host when build for native platforms, so it is possible to use
it also with the embedded libCs.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Support device power management in spi_nor driver. Only use
SUSPEND/RESUME if `CONFIG_SPI_NOR_IDLE_IN_DPD` is not enabled to avoid
state conflicts.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This commit adds the jedec216 read sfdp and Read ID
function API. The qspi commands are issued to the
quad flash device.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Avoid timeout when taking semaphores in ISR.
This enables flash operations inside interrupted context
such as exceptions, allowing operations like saving core
dump to flash for instance.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Allows to configure OSPI Manager IO ports with devicetree.
If properties are absent, then original default values
are preserved for compatibility.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
This adds a few line use zephyr_syscall_header() to include
headers containing syscall function prototypes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Copy the LUT to SRAM before updating it. This avoids the application
reading LUT entries from FlexSPI while trying to write them to FlexSPI
configuration registers, which could result in invalid LUT entries being
added.
This update is applied to all in tree flash FlexSPI drivers, although
the failure has only been observed with the flash_mcux_flexspi_nor
driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This make MCUboot build as Zephyr application.
Providing optinal 2nd stage bootloader to the
IDF bootloader, which is used by default.
This provides more flexibility when building
and loading multiple images and aims to
brings better DX to users by using the sysbuild.
MCUboot and applications has now separate
linker scripts.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Like other stm32 drivers, especially the stm32 flash ospi,
the DMA callback accepts a null or positive status.
It returns an error in case of negative.
BTW it also sets variable as unused, like stm32 flash ospi does.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Replace memcpy usage in write since it is not linked to non-external
flash which might cause read-while-write issues.
Move the function that invalidated the data cache inside the critical
section to avoid context switch before it is invalidated.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Check memc_flexspi_is_running_xip before calling
memc_flexspi_set_device_config in hyperflash init.
This aligns with the nor flash driver.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Hyperflash write operations resulted in invalid writes. This commit
fixes the issue by temporarily lowering the clock during writes.
This aligns with the mcux-sdk-examples.
Fixes https://github.com/zephyrproject-rtos/zephyr/issues/53855
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add a function to wait for the full (bulk) Nor-octoflah erase command.
When erasing the full octo-flash, the drivers waits until
the operation is ready and the external NOR mem becomes ready itself.
The full (bulk) erase operation lasts for several seconds.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
- Update KCONFIG for flash driver to depend on
DT_HAS_FIXED_PARTITIONS_ENABLED, since that is necessary for the
driver implementation
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Most available AT45 flash chips have their first two sectors shorter
than the consecutive ones. Usually, the first sector is marked as 0a
and has its size equal to eight pages (one block) and the second one
(usually 0b) is the complement to the size of a regular sector.
This commits modifies the driver so that erasing of these first two
sectors is performed correctly. This modified behavior is configurable
with a new DT property so that it is still possible to also use legacy
AT45 chips that do not feature such sector split. Such legacy chips
usually also do not support the chip erase and sector erase commands,
so two more DT properties are introduced to cover that.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- Added initial version of Infineon CAT1 Flash driver
- Added binding file for infineon,cat1-flash-controller.yaml
- Added overlays for subsys/nvs and drivers/flash_shell
to support cy8cproto_063_ble, cy8cproto_062_4343w boards
- Defined erase-block-size in PSoC6 MPN dtsi.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Use new nrfx hal function to memcpy from flash
instead of accessing the array directly.
That function is inlining a memcpy for real targets,
so there is no practical difference for those.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Make use of positive status values in the DMA callback to pass
info to the DMA client after a successful DMA operation.
A completed DMA transfer uses the status 0 while a reached
water mark uses the status 1.
Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
Add the ability for the flash simulator to store its contents in a
memory region.
This allows filesystems on the flash simulator to survive a reboot.
And allows subsystems (e.g. coredump) to store their info on ram while
using the (existing) flash partition backend.
Add a example (for nucleo_f411re) that shows how to configure the flash
simulator for hardware (cfg discussion #54166).
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
This fixes this bug:
https://github.com/zephyrproject-rtos/zephyr/issues/57498
If bit 1 is set, then a write enable is required before
sending the 0xb7 instruction to enable the 4 byte address
mode, which this PR implements.
Signed-off-by: Frank Buss <fb@frank-buss.de>
SPI / QSPI flash with density above 16MB must use 4 byte addressing mode
also on sector erase.
This patch selects the right addressing mode and opcode when 4 byte
addressing mode is selected
Signed-off-by: Brian Juel Folkmann <bju@trackunit.com>
Mark the device as busy when it is locked to perform a flash operation
so that the PM subsystem does not try to suspend it. Also refuse to run
a PM action when the device is busy (in case `qspi_nor_pm_action()` is
called directly, not by the PM subsystem).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Original computation seems to be based on
QSPI that has prescaler range [0, 255].
However, OSPI clock prescaler has different
value range [1, 256].
Adapt prescaler computation to valid OSPI
domain and add min value assert.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
For the POSIX architecture, add options to:
* Clear the flash content at boot
* To delete the file on exit
* To just keep the flash in RAM instead of a file in disk
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The delayblock is bypassed when the <dlyb-bypass> property is true.
DT_NODE_HAS_PROP tests whether the property is defined at all,
not whether a boolean property is true or false.
To get a boolean property’s truth value,
use DT_PROP(node_id, prop) instead.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Remove all init functions that do nothing, and provide a `NULL` to
*DEVICE*DEFINE* macros.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Normally, the driver deactivates the QSPI peripheral for periods when
no QSPI operation is performed. This is done to avoid increased current
consumption when the peripheral is idle. For the same reason, the base
clock on nRF53 Series SoCs (HFCLK192M) is configured for those periods
with the default /4 divider that cannot be used otherwise. However,
when XIP accesses are used, the driver must be prevented from doing
both these things as that would make XIP to fail. Hence, a function
is provided so that applications can inform the driver that XIP is
needed and the above idle actions should be suppressed.
This function (`nrf_qspi_nor_xip_enable()`) replaces the old one
(`nrf_qspi_nor_base_clock_div_force()`) that was intended for similar
purpose but after deactivation of the peripheral was introduced in
commit 95d867e8ed it became useless.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
MISRA Rule 5.7 requires uniqueness of tag identifiers. Shell is
frequently problematic because many code uses `const struct shell
*shell`. This causes CI noise every time one of these shell files is
edited, so let's update all of them with `const struct shell *sh`
instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
With the stm32h5x, hal driver is xspi for octospi
Add a header file to map functions and constants.
The ospi driver of the stm32H5x serie does not support DMA yet.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduce flash extended operations that can be used to disable access
to option and control registers until reset. Disabling access to these
registers improves system security, because flash content (or protection
settings) can't be changed even when exploit was found.
On STM32 devices, registers can be locked until reset by writing wrong
key during unlock procedure. It triggers a bus fault, so during the
procedure we need to ignore faults and clear bus fault pending bit.
Please note that option register disabling was implemented for devices
that have OPTCR register (F2, F4, F7 and H7). Implementation on other
devices requires more testing, since documentation is not precise
enough. Disabling control register was implemented for devices that
have CR register.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This patch makes possible to choose custom byte which should be used
to enable non-permanent readout protection (RDP1). Actually, any byte
except 0xAA and 0xCC (which are used by RDP0 and RDP2 respectively)
can be used to enable RDP1 but in multi-image environment, some other
image could check if RDP1 is enabled by comparing it to some hardcoded
value.
If property is not defined, 0x55 will be used to enable RDP1. The
default value comes from STM32 HAL.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This patch adds flash readout protection support for STM32F4 devices
family. These devices can enable protection on entire flash content.
Readout protection functionality was exposed as vendor extended
operation. To change readout protection state, caller should provide a
structure which describes desired RDP state.
Enabling readout protection permanently or disabling readout protection
(changing from level 1 to level 0) is guarded by
CONFIG_FLASH_STM32_READOUT_PROTECTION_PERMANENT_ALLOW and
CONFIG_FLASH_STM32_READOUT_PROTECTION_DISABLE_ALLOW respectively.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This patch adds sector write protection support for STM32F4 devices
family. These devices can protect flash content with sector precision.
Write protection functionality was exposed as vendor extended operation.
To change write protection state, caller should provide mask of enabled
and disabled sectors.
Function responsible for locking/unlocking option bytes was implemented
for all STM32 devices supported by this driver.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Introduce the stm32h5 serie to the the existing flash driver
It is based on the stm32l5 model.
Add a function to check if the flash is in dual
or single bank mode.
Some stm32 devices can map 2 or 1 flash banks.
Adapt the FLASH register names for the stm32h5 mcu.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".
Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move the SoC Flash nRF sync ticker implementation into
Bluetooth Controller Subsystem folder, as internal headers
are included.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Add PM_DEVICE_RUNTIME support to nordic QSPI NOR flash driver, putting
the QSPI peripheral and flash ship into DPD if available
Signed-off-by: Zack Cornelius <zcornelius@securityesys.com>
Besides of standard flash operations like write or erase, flash
controllers also support additional features like write protection or
readout protection. These features are not available in every flash
controller, what's more controllers can implement it in a different way.
It doesn't make sense to add a separate flash API function for every
flash controller feature, because it could be unique (supported on small
number of flash controllers) or the API won't be able to represent the
same feature on every flash controller.
Extended operation interface provides flexible way for supporting flash
controller features. Code space is divided equally into Zephyr codes
(MSb == 0) and vendor codes (MSb == 1). This way we can easily add
extended operations to the drivers without cluttering the API or
problems with API incompatibility. Extended operation can be promoted
from vendor codes to Zephyr codes if the feature is available in most
flash controllers and can be represented in the same way.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Since PINCTRL and pinctrl-0 is now required, there's no point in doing
extra validation at driver level. Modify the macro to just check that
sleep state is present when needed, since it was the only remaining
assertion that was not covered. Renamed the macro to make it more clear
what it does: NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Move to using 'select SPI' instead of 'depends on SPI'
(see commit df81fef for more details)
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
No need to read back the CR (NOR flash config or control register)
to check if entering the 4-Byte Address Mode is effective.
The action of this command is immediate and the result
(bit field of the CR) is NOR flash vendor-specific.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The check_arr used the TEST_ARR_SIZE value for the size, but
has been removed and replaced with CONFIG_FLASH_SHELL_BUFFER_SIZE.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Fixes spi_nor_erase to return -EINVAL instead of -ENODEV
when erase requested is out of flash range.
This makes the SPI NOR return the same error as all other errors.
Fixes#54897
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Previously when the repeat argument wasn't supplied to the shell
command it would falsely seem to succeed, even though the
test was never run. Instead of displaying an error message this
rather overrides the repeat to 1, so that the test is run once.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Previously cmd_test could falsely give the indication that the
flash driver is functioning properly, because the written data
isn't validated and could have silently failed.
This commit adds a verify step to ensure the data was written successfully.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Requesting page layout triggers filling bank array
only once, and returns pre-filled array on consequential calls.
But ignores array size.
Remember size of this array as well.
Fixes#54563
Signed-off-by: Maciej Zagrabski <mzi@trackunit.com>
