Add the Sensor Fusion Low Power (SFLP) FIFO streaming capability,
using RTIO. The decode function is now aware of parsing following FIFO
tags:
- LSM6DSV16X_SFLP_GAME_ROTATION_VECTOR_TAG
- LSM6DSV16X_SFLP_GYROSCOPE_BIAS_TAG
- LSM6DSV16X_SFLP_GRAVITY_VECTOR_TAG
To activate SFLP the user should put in DT the proper configuration.
For example, to activate a 60Hz SFLP FIFO batching rate of game rotation
vector, gravity vector and gbias components, the user should add in DT
the following:
sflp-odr = <LSM6DSV16X_DT_SFLP_ODR_AT_60Hz>;
sflp-fifo-enable = <LSM6DSV16X_DT_SFLP_FIFO_GAME_ROTATION_GRAVITY_GBIAS>;
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The it8801 template is helpful but in the current state it does not
allow changing the device address as that is in the template itself. Fix
that by moving the template content down a level in the hierarchy, so
that it extends the mfd device itself rather than than instantiate it,
then the base instance can have any address, now the only limitation is
that only one instance is possible, but that is probably alright for
now.
Alternatives would be to use a define for the address, or even a
template per address, but this feels like a better compromise for now.
This may also use
https://github.com/zephyrproject-rtos/zephyr/pull/82825 in the future if
that ever becomes a thing.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The EFR32MG24B210F1536IM48 has 4 more GPIOs than the
EFR32MG24B310F1536IM48, and does not support the high accuracy
mode for the IADC.
Signed-off-by: Daniel Fuchs <software@sagacioussuricata.com>
Enables use of the counter dts property which allows to configure a counter
device as the timing source for the stepping.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Adds a timing source api which is used by the step-dir stepper common code.
This allows the reusable common code to configure different timing sources,
since the initial delayable work implementation was inacurate for higher
maximum velocities.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
The LIS2DUXS12 is a smart, digital, 3-axis linear accelerometer whose
MEMS and ASIC have been expressly designed to combine the lowest current
consumption possible with features such as always-on antialiasing
filtering, a finite state machine (FSM) and machine learning core (MLC)
with adaptive self-configuration (ASC), and an analog hub / Qvar sensing
channel.
(https://www.st.com/en/mems-and-sensors/lis2duxs12.html)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Avoid referring to Pico 2 (the name of a board). In this context,
RPI_PICO is used to refer to the (Zephyr) `SOC_FAMILY` rather than the
Pico 1 board. This clarifies common numerical values between the RP2040
and RP2350 SoC series, and enables existing DTS files to be used with
RP2350-based boards with fewer changes.
Remove the use of Zehpyr's `CONFIG_` macros from the device tree files,
and replace them with `SOC_SERIES`-specific files. Update the driver
implementation to conditionally include the correct file. Update
documentation and samples to match.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Add initial support for the RP2350's DMA peripheral, allow tests
under drivers/dma/loop_transfer to run on on the Raspberry Pi Pico 2,
and update the board's documentation.
Signed-off-by: Manuel Aebischer <manuel.aebischer@belden.com>
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Add initial support for the RP2350's PIO peripherals, extend the
existing example under samples/boards/raspberrypi/rpi_pico/uart_pio to
demonstrate this on the Raspberry Pi Pico 2, and update the board's
documentation.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Signed-off-by: Manuel Aebischer <manuel.aebischer@belden.com>
RP2350 is Raspberry Pi's newest SoC. From the datasheet:
"RP2350 is a new family of microcontrollers from Raspberry Pi that
offers significant enhancements over RP2040. Key features include:
• Dual Cortex-M33 or Hazard3 processors at 150 MHz
• 520 kB on-chip SRAM, in 10 independent banks
• 8 kB of one-time-programmable storage (OTP)
• Up to 16 MB of external QSPI flash/PSRAM via dedicated QSPI bus
...
"
This commit introduces some changes to support the existing RP2040 and
what is describe by Raspberry Pi as the "RP2350 family". Currently there
are 4 published products in the family: RP2350A, RP2350B, RP2354A, and
RP2354A. Within Zephyr's taxonomy, split the configuration as follows:
Family: Raspberry Pi Pico. This contains all RP2XXX SoCs,
SoC Series: RP2040 and RP2350.
SoC: RP2040 and, for now, just the RP2350A, which is present on the Pico
2, where the A suffix indicates QFN-60 package type. This structure is
reflected in `soc/raspberrypi/soc.yml`, and somewhat assumes that there
won't be a RP2050, for example, as a RP2040 with more RAM.
This is foundation work ahead of introducing support for Raspberry Pi's
Pico 2 board, which is fitted with a RP2350A and 4MB of flash.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add support for SoC-specific clock ids and update the initialization
function to support the existing RP2040 and add support for the RP2350.
clock_control_rpi_pico.c uses numerical values for clock ids taken from
rpi_pico_clock.h which are the "clock generator". For the RP2350 these
values are different for some of the same logical clock sources, as well
as the RP2040 and RP2350 having different clock sources available.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Add a GPIO driver for the Microchip MEC5 HAL based chips.
Current devices are: MEC174x, MEC175x, and HAL version of
MEC172x named MECH172x.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This adds initial support for NXP SDMA controller. We make use
of NXP HAL to configure the IP.
SDMA uses BD (buffer descriptors) to describe a transfer. We create
a cyclic list of descriptors and trigger them manually at start and
later when data is available.
This is tested using Sound Open Firmware app on top of Zephyr.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
- rename enable-gpios to en-gpios in adi,tmc2209
- place en-gpios in common stepper-controller.yaml
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Fast SPIM instances in nRF54H20 (SPIM120 and SPIM121) are driven by
the global HSFLL (HSFLL120). Add `clocks` property in these nodes
to reflect this.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
NXP FlexTimer Module is a configurable timer peripheral hence it should
be located under bindings/timer.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Rename "nxp,kinetis-ftm-pwm" compatible to "nxp,ftm-pwm" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Update the GC9X01X display driver binding documentation with the current
MIPI DBI SPI binding structure. The old example used direct SPI device
binding which is now deprecated in favor of the MIPI DBI API.
Signed-off-by: Benjamin Geiger <BenjaminGeiger1@gmail.com>
Add nrf twis (I2C controller supporting I2C peripheral role and
EasyDMA) support, including updating the existing twis dt binding
to match the hardware with proper examples.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
This patch adds support for HOST OpenThread communication to the RCP
co-processor via UART using SPINEL protocol.
The aim is to use OpenThread's RCP (Radio Co-Processor) with HOST device
(for example imxRT1020). Such configuration is the same as one used
with PC program (ot-cli) and RCP.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
