DWC2 otg OUT transfers are being used for SETUP DATA0, OUT Data Stage
packets and OUT Status Stage ZLP. On High-Speed it is possible for IN
Data Stage, OUT Status Stage ZLP and subsequent SETUP DATA0 to happen
in very quick succession, making all the three events appear at the same
time to the handler thread.
The handler thread is picking up next endpoint to handle based on the
least significant bit set. When OUT endpoints were on bits 0-15 and IN
endpoints were on bits 16-31, the least significant bit policy favored
OUT endpoints over IN endpoints. This caused problems in Completer mode
(but suprisingly not in Buffer DMA mode) that lead to incorrect control
transfer handling.
The choice between least significant bit first or most significant bit
first is arbitrary. Switching from least to most significant bit first
would have resolved the issue. It would also favor higher numbered
endpoints over lower numbered endpoints.
Swap the order of endpoints in bitmaps to have IN on bits 0-15 and OUT
on bits 16-31 to keep handling lower numbered endpoints first and
resolve the control transfer handling in Completer mode.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Rename the Silabs HCI driver to hci_silabs_efr32.c to better indicate what
hardware it supports. Also rename the associated devicetree binding and
Kconfig options to be consistent with the new driver name.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Boards under a folder that doesn't directly match a vendor prefix
incorrectly end up being categorized as "zephyr" since that's the only
prefix that is eventually found when navigating up the folder hierarchy.
This commits treats boards in the "others" and "native" folders as
special cases and associates them to an "Unknown/Other" category.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Updated imx8mm/n/p and imx93 Cortex-A Core supported features in board
yaml file, and also fixed ram size for the board.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Ensured flash size and partition size are specified in bytes
as required by the STM32 QSPI NOR driver.
Signed-off-by: Harry Jiang <explora26@gmail.com>
Check error codes when sending invalid frames:
- too big data payload;
- wrong set of flags.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
There is negative test for too high data bitrate.
Add test that checks too low data bitrate.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
Update the board cmake to use xsdb runner, If users would like to
use default xsdb.cfg then need to pass the fsbl.elf binary via
--fsbl option when using west flash or twister commands.
Usage:
1) west flash --runner xsdb --elf-file kv260_r5/zephyr/zephyr.elf
--fsbl <path>/fsbl.elf
2) ./scripts/twister -p kv260_r5 --west-runner xsdb --device-testing
--device-serial /dev/ttyUSB0 --west-flash="--fsbl=<path>/fsbl.elf"
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Add support for xsdb(Xilinx System Debugger) used with AMD's FPGA
and SOC platforms, it is a user-friendly, interactive, and scriptable
command line interface, by design choice it's expected that platforms
to have xsdb scripts present inside their platform code.
xsdb runner has bitstream and fsbl optional arguments, bitstream is
needed for fpga targets and fsbl is needed for SOC targets, added
support for both options.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
remove k_work related code and change
the argument of the callback to `struct net_socket_service_event`.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add PCI device IDs for common Intel Raptor Lake variants and Alder Lake N.
These all have cAVS2.5 audio DSP.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Numerically sort the PCI DIDs for cAVS2.5 hardware. This follows
the convention in e.g. Linux and coreboot and eases maintainance. No
functional change.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The "Detected cAVS 1.8+ hardware" message is misleading as it implies
some version of Intel cAVS hardware has been found, while in fact this
script supports also other types of hardware, including Intel ACE.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Clean up code documentation to drop references to platforms no longer
supported in the code. Continues the cleanup started in commit
086e4f84ed ("intel_adsp: cavstool: Remove
legacy code").
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Added a check in unicast_client_ase_discover_cb that if
no ASE was discovered, then it would stop the discovery
there instead of attempting to call
unicast_client_ase_cp_discover to discover the control point
which would not be useful to use anyhow.
This terminates the discovery earlier in case of the remote
side not supporting the audio direction we are discovering.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
The default configuration for PINCTRL should not be set with
the other default configurations in .defconfig, instead select
a default value as part of defining the UART driver.
Signed-off-by: Andrew Davis <afd@ti.com>
Add initial SoC support for the TI J721E SoC series Cortex-R5 core.
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Use full board name in cmake file.
Akin to the fix done in zephyrproject-rtos#80270
zephyrproject-rtos#80270
following the changes from
zephyrproject-rtos#77250
In which twister now uses the full board name when calling cmake.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
In case the host doesn't pull the new data from the endpoint, the work task
would schedule itself again delayed (at the max. priority). When there is
no terminal program or active application reading the endpoint this
results in a constant polling of the endpoint burning up to 5% of the
CPU cycles.
By using a atomic flag for tx busy, the polling is solved and changed into
a postponed execution of the next work task which saves up to 5% of
CPU cycles and allows a better real-time behavior for other tasks.
Secondly, if the TX interrupt is disabled but there is still data in the TX
FIFO (ring buffer), the implementation will continue to trigger subsequent
TX work and attempt to flush the data to the host.
Signed-off-by: Vincent van der Locht <vincent@synchronicit.nl>
DT_INST* should be used in MSPI_CONFIG or device tree value capture
will fail sliently and fall back to defaults.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Switch from using direct `strtol` calls to `shell_strtol`.
This change leverages the extensive error handling provided
by `shell_strtol`.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Since `<host>` is a mandatory argument, the (_mand, _opt) values
should be adjusted to 2 and 12, respectively.
Note that `_mand` includes the number of mandatory arguments,
including the command name (`ping` itself).
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This commit does the following:
1. tests set_callback and user_data
2. fixes the api as well as the drivers by passing user_data
back to the set callback
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
IS25LP flash chips have a similar P[6:3] register to the IS25WP series,
and need the same workaround.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
IS25WP flash chips support 133MHz only when P[6:3] is programmed, which
will not occur during the SFDP probe sequence used in the FlexSPI nor
driver. With the default P[6:3] value, the best frequency supported for
read instruction 0xEB is 104MHz, so set this for all boards using this
flash chip with the FlexSPI nor driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Some NXP boards program the read parameters bits (P[6:3]) within the
IS25WP flash device during init, which will result in JESD216 probe
commands failing (as the number of dummy cycles will be incorrect). Add
handling to force these volatile bits to their default value to the
flexspi flash driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Quad enable method 5 reads status register 2 (one byte), but then writes
to 2 bytes to the status registers, so we need to shift the output
buffer in order to manage this correctly.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Writing the quad enable bit on flash chips typically requires a write
enable instruction be issued before writing the non-volatile status
register, and the flash may remain busy briefly after programming this
bit. Add code to send the WREN instruction, and to wait for the flash to
finish programming after writing the status register.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Move the LUT used for probing to be stored in .data, instead of on the
stack. This reduces stack usage during probe by 192 bytes, which avoids
stack overflows that were occurring on some platforms.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Even in cases where the alt-addr is set, we can still use the INT pin
during probe. Some boards require this, as if a reset GPIO is not
defined the INT pin may still need to be toggled in order to initialize
the GT911 IC correctly.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
