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altr,nios2f.yaml
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andes,andescore-v5.yaml
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dts/riscv/andes: add andestech,andescore-v5 compatible string
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2024-01-31 10:41:49 +01:00 |
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arm,cortex-a53.yaml
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arm,cortex-a55.yaml
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arm,cortex-a72.yaml
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arm,cortex-a76.yaml
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arm,cortex-m.yaml
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arm,cortex-m0+.yaml
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arm,cortex-m0.yaml
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arm,cortex-m1.yaml
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arm,cortex-m3.yaml
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arm,cortex-m4.yaml
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arm,cortex-m4f.yaml
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arm,cortex-m7.yaml
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arm,cortex-m23.yaml
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arm,cortex-m33.yaml
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arm,cortex-m33f.yaml
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arm,cortex-m55.yaml
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dts: bindings: cpu: add definition for arm,cortex-m55
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2024-06-27 20:06:06 -04:00 |
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arm,cortex-m55f.yaml
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dts: bindings: cpu: add definition for arm,cortex-m55
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2024-06-27 20:06:06 -04:00 |
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arm,cortex-m85.yaml
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arch: arm: Add initial support for Cortex-M85 Core
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2024-06-26 13:36:14 -04:00 |
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arm,cortex-m85f.yaml
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arch: arm: Add initial support for Cortex-M85 Core
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2024-06-26 13:36:14 -04:00 |
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arm,cortex-r4.yaml
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arm,cortex-r4f.yaml
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arm,cortex-r5.yaml
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arm,cortex-r5f.yaml
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arm,cortex-r7.yaml
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arm,cortex-r52.yaml
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arm,cortex-r82.yaml
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cdns,tensilica-xtensa-lx3.yaml
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cdns,tensilica-xtensa-lx4.yaml
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cdns,tensilica-xtensa-lx6.yaml
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cdns,tensilica-xtensa-lx7.yaml
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cpu.yaml
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efinix,vexriscv-sapphire.yaml
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dts/riscv/efinix: add the efinix,vexriscv-sapphire compatible string
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2024-01-31 10:41:49 +01:00 |
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espressif,riscv.yaml
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soc: esp32c2: Add support to ESP32C2 and ESP8684
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2024-08-16 14:08:22 -04:00 |
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espressif,xtensa-lx6.yaml
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soc: esp32xx: refactor clock and RTC subsystems
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2024-05-27 01:37:18 -07:00 |
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espressif,xtensa-lx7.yaml
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soc: esp32xx: refactor clock and RTC subsystems
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2024-05-27 01:37:18 -07:00 |
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gaisler,leon3.yaml
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intel,alder-lake.yaml
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intel,apollo-lake.yaml
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intel,elkhart-lake.yaml
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intel,ish.yaml
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intel,lakemont.yaml
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intel,niosv.yaml
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intel,raptor-lake.yaml
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intel,x86.yaml
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ite,riscv-ite.yaml
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litex,vexriscv-standard.yaml
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dts/riscv/litex: add litex,vexriscv-standard compatible string
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2024-01-31 10:41:49 +01:00 |
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lowrisc,ibex.yaml
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dts/riscv/lowrisc: add lowrisc,ibex compatible string
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2024-01-31 10:41:49 +01:00 |
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neorv32-cpu.yaml
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nordic,vpr.yaml
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dts: Add and extend Nordic bindings needed for nRF54H20
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2024-02-02 16:40:11 +01:00 |
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nuclei,bumblebee.yaml
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soc: riscv: gd32vf103: simplify MCAUSE exception mask handling
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2024-01-15 09:58:03 +01:00 |
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openisa,ri5cy.yaml
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dts/riscv/openisa: add compatible strings for the RI5CY cores
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2024-01-31 10:41:49 +01:00 |
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openisa,zero-ri5cy.yaml
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dts/riscv/openisa: add compatible strings for the RI5CY cores
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2024-01-31 10:41:49 +01:00 |
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qemu,nios2-zephyr.yaml
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qemu,riscv-virt.yaml
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dts: set the riscv,isa property for virt-based targets
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2024-05-15 09:30:23 +02:00 |
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riscv,cpus.yaml
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dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/
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2024-01-31 10:41:49 +01:00 |
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sample_controller.yaml
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sensry,ganymed-sy1xx.yaml
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soc: sensry: Add support for SY120-GBM and SY120-GEN1
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2024-09-16 20:19:31 +02:00 |
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sifive,e24.yaml
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dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/
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2024-01-31 10:41:49 +01:00 |
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sifive,e31.yaml
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dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/
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2024-01-31 10:41:49 +01:00 |
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sifive,e51.yaml
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dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/
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2024-01-31 10:41:49 +01:00 |
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sifive,s7.yaml
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dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/
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2024-01-31 10:41:49 +01:00 |
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sifive,u54.yaml
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dts/riscv/microchip: add missing cpu nodes compats in mpfs.dtsi
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2024-01-31 10:41:49 +01:00 |
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sifive-common.yaml
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dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/
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2024-01-31 10:41:49 +01:00 |
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snps,arcem.yaml
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telink,b91.yaml
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wch,qingke-v2.yaml
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dts: riscv: include riscv,cpus.yaml in qingke-v2
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2025-01-15 11:58:58 +01:00 |
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zephyr,native-posix-cpu.yaml
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