Cong Nguyen Huu 40a27244f0 boards: s32z2xx: enable flash controller QSPI ... The on-board S26HS512T 512M-bit HyperFlash memory is connected to the QSPI controller port A1. This board configuration selects it as the default flash controller. Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>		2025-01-21 19:26:45 +01:00
..
arc/synopsys	dts: bindings: gpio: use hyphens instead of underscore	2025-01-15 11:51:33 +01:00
arm	boards: s32z2xx: enable flash controller QSPI	2025-01-21 19:26:45 +01:00
arm64	dts: arm64: imx95: add TPM device nodes	2025-01-20 02:58:28 +00:00
bindings	drivers: flash: add NXP S32 QSPI HyperFlash driver	2025-01-21 19:26:45 +01:00
common	dts: common: nordic: nrf54h20: Fix flpr bus-width	2025-01-17 10:42:22 +01:00
nios2/intel	dts: nios2: intel: Fix unit and first address mismatch	2024-09-18 15:30:24 +02:00
posix
riscv	dts: sy1xx: add gpio support	2025-01-21 09:12:55 +01:00
sparc/gaisler	soc/gr716a: Enable GPIO support on LEON GR716A	2024-07-29 14:27:15 +02:00
x86/intel	alder lake: Add missing intel,x86_64 compat	2025-01-09 18:12:07 +01:00
xtensa	dts: xtensa: Fix gpio-reserved-ranges of gpio1	2024-12-26 15:31:43 +01:00
binding-template.yaml
Kconfig	dts: drop HAS_DTS	2023-10-20 12:18:17 -07:00