Adrian Warecki e4a9503706 mm: tlb: Improve the context saving function ... Attempt to invalidate cache for an unmapped address results in cpu exception for the ptl platform. Perform cache invalidation after translation activation in tlb. Add address mapping in mmu for platforms that have it. Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>		2024-11-19 16:23:52 +01:00
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CMakeLists.txt	drivers: mm: Add support for TI RAT module using system_mm API	2023-07-11 09:44:48 +02:00
Kconfig	drivers: mm: Add support for TI RAT module using system_mm API	2023-07-11 09:44:48 +02:00
mm_drv_bank.c	mm: rename struct mem_drv_bank to sys_mm_drv_bank	2023-11-21 08:42:01 +00:00
mm_drv_common.c	mm: common: reset mappings during simple mapping failures	2024-08-28 16:35:43 -04:00
mm_drv_common.h	mm: introduce update memory flags api	2022-07-13 15:53:14 +02:00
mm_drv_intel_adsp.h	drivers: mm/intel_adsp: Add MMU support to MM driver	2024-06-04 13:40:04 +02:00
mm_drv_intel_adsp_mtl_tlb.c	mm: tlb: Improve the context saving function	2024-11-19 16:23:52 +01:00
mm_drv_intel_adsp_regions.c	mm: intel: adsp: simplify code in mm_drv_intel_adsp_regions.c	2023-03-23 16:31:08 -04:00
mm_drv_intel_adsp_tlb.c	xtensa: move to use system cache API support for coherency	2024-02-03 13:42:33 -05:00
mm_drv_ti_rat.c	drivers: mm: refine includes of the header	2023-09-26 15:09:12 +02:00