141 lines
4.9 KiB
C
141 lines
4.9 KiB
C
/**
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* \file
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*
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* \brief SAM Direct Memory Access Controller Driver
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*
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* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef DMA_H_INCLUDED
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#define DMA_H_INCLUDED
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// THIS IS A PARED-DOWN VERSION OF DMA.H FROM ATMEL ASFCORE 3.
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// Please keep original copyright and license intact!
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern DmacDescriptor // 128 bit alignment
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_descriptor[DMAC_CH_NUM],
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_writeback[DMAC_CH_NUM];
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#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || defined(__DOXYGEN__) || defined(__SAMD51__)
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#define FEATURE_DMA_CHANNEL_STANDBY
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#endif
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enum dma_transfer_trigger_action{
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#ifdef __SAMD51__
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// SAMD51 has a 'burst' transfer which can be set to one
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// beat to accomplish same idea as SAMD21's 'beat' transfer.
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// Trigger name is ACTON_BEAT for backward compatibility.
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DMA_TRIGGER_ACTON_BLOCK = DMAC_CHCTRLA_TRIGACT_BLOCK_Val,
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DMA_TRIGGER_ACTON_BEAT = DMAC_CHCTRLA_TRIGACT_BURST_Val,
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DMA_TRIGGER_ACTON_TRANSACTION = DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val,
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#else
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DMA_TRIGGER_ACTON_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val,
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DMA_TRIGGER_ACTON_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val,
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DMA_TRIGGER_ACTON_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val,
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#endif
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};
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enum dma_callback_type {
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// First item here is for any transfer errors. A transfer error is
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// flagged if a bus error is detected during an AHB access or when
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// the DMAC fetches an invalid descriptor
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DMA_CALLBACK_TRANSFER_ERROR,
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DMA_CALLBACK_TRANSFER_DONE,
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DMA_CALLBACK_CHANNEL_SUSPEND,
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DMA_CALLBACK_N, // Number of available callbacks
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};
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enum dma_beat_size {
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DMA_BEAT_SIZE_BYTE = 0, // 8-bit
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DMA_BEAT_SIZE_HWORD, // 16-bit
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DMA_BEAT_SIZE_WORD, // 32-bit
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};
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enum dma_event_output_selection {
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DMA_EVENT_OUTPUT_DISABLE = 0, // Disable event generation
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DMA_EVENT_OUTPUT_BLOCK, // Event strobe when block xfer complete
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DMA_EVENT_OUTPUT_RESERVED,
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DMA_EVENT_OUTPUT_BEAT, // Event strobe when beat xfer complete
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};
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enum dma_block_action {
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DMA_BLOCK_ACTION_NOACT = 0,
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// Channel in normal operation and sets transfer complete interrupt
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// flag after block transfer
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DMA_BLOCK_ACTION_INT,
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// Trigger channel suspend after block transfer and sets channel
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// suspend interrupt flag once the channel is suspended
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DMA_BLOCK_ACTION_SUSPEND,
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// Sets transfer complete interrupt flag after a block transfer and
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// trigger channel suspend. The channel suspend interrupt flag will
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// be set once the channel is suspended.
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DMA_BLOCK_ACTION_BOTH,
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};
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// DMA step selection. This bit determines whether the step size setting
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// is applied to source or destination address.
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enum dma_step_selection {
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DMA_STEPSEL_DST = 0,
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DMA_STEPSEL_SRC,
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};
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// Address increment step size. These bits select the address increment step
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// size. The setting apply to source or destination address, depending on
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// STEPSEL setting.
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enum dma_address_increment_stepsize {
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DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0, // beat size * 1
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DMA_ADDRESS_INCREMENT_STEP_SIZE_2, // beat size * 2
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DMA_ADDRESS_INCREMENT_STEP_SIZE_4, // beat size * 4
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DMA_ADDRESS_INCREMENT_STEP_SIZE_8, // etc...
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DMA_ADDRESS_INCREMENT_STEP_SIZE_16,
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DMA_ADDRESS_INCREMENT_STEP_SIZE_32,
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DMA_ADDRESS_INCREMENT_STEP_SIZE_64,
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DMA_ADDRESS_INCREMENT_STEP_SIZE_128,
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};
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#ifdef __cplusplus
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}
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#endif
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#endif // DMA_H_INCLUDED
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