m680x0 update:
- Added working PMMU address translation (not feature complete, but sufficient to boot several 68030 Macs in MESS) - Fixed up disassembly of some PMMU instructions - Added "68020 with 68851" CPU type
This commit is contained in:
R. Belmont
Emmanuel Anne
parent
8126887721
commit
d5576b3797
7 changed files with 317 additions and 27 deletions
76
m68k_in.c
76
m68k_in.c
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@ -8469,7 +8469,81 @@ M68KMAKE_OP(pmove, 32, ., .)
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modes = m68ki_read_imm_16();
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ea = M68KMAKE_GET_EA_AY_32;
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fprintf(stderr,"680x0: unhandled PMOVE modes %x ea %x\n", modes, ea);
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if ((modes & 0xfde0) == 0x2000) // PLOAD
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{
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fprintf(stderr,"680x0: unhandled PLOAD\n");
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return;
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}
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if ((modes & 0xe200) == 0x2000) // PFLUSHA
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{
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fprintf(stderr,"680x0: unhandled PFLUSHA\n");
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return;
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}
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switch ((modes>>13) & 0x7)
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{
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case 0: // MC68030/040 form with FD bit
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case 2: // MC68881 form, FD never set
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if (modes & 0x200)
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{
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fprintf(stderr,"680x0: PMOVE from MMU not supported\n");
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}
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else
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{
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switch ((modes>>10) & 7)
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{
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case 0: // translation control register
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m68ki_cpu.mmu_tc = m68k_read_memory_16( ea)<<16;
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m68ki_cpu.mmu_tc |= m68k_read_memory_16( ea+2);
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if (m68ki_cpu.mmu_tc & 0x80000000)
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{
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m68ki_cpu.pmmu_enabled = 1;
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}
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else
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{
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m68ki_cpu.pmmu_enabled = 0;
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}
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break;
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case 2: // supervisor root pointer
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m68ki_cpu.mmu_srp_limit = m68k_read_memory_16( ea)<<16;
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m68ki_cpu.mmu_srp_limit |= m68k_read_memory_16( ea+2);
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m68ki_cpu.mmu_srp_aptr = m68k_read_memory_16( ea+4)<<16;
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m68ki_cpu.mmu_srp_aptr |= m68k_read_memory_16( ea+6);
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break;
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case 3: // CPU root pointer
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m68ki_cpu.mmu_crp_limit = m68k_read_memory_16( ea)<<16;
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m68ki_cpu.mmu_crp_limit |= m68k_read_memory_16( ea+2);
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m68ki_cpu.mmu_crp_aptr = m68k_read_memory_16( ea+4)<<16;
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m68ki_cpu.mmu_crp_aptr |= m68k_read_memory_16( ea+6);
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break;
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default:
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fprintf(stderr,"680x0: PMOVE to unknown MMU register %x\n", (modes>>10) & 7);
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break;
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}
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}
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break;
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case 3: // MC68030 to/from status reg
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if (modes & 0x200)
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{
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m68k_write_memory_16(ea, m68ki_cpu.mmu_sr);
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}
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else
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{
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m68ki_cpu.mmu_sr = m68k_read_memory_16( ea);
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}
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break;
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default:
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fprintf(stderr,"680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes>>13) & 0x7, modes, REG_PC);
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break;
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}
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}
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else
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{
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@ -184,6 +184,9 @@
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#define M68K_LOG_1010_1111 OPT_OFF
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#define M68K_LOG_FILEHANDLE some_file_handle
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/* Emulate PMMU : if you enable this, there will be a test to see if the current chip has some enabled pmmu added to every memory access,
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* so enable this only if it's useful */
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#define M68K_EMULATE_PMMU OPT_ON
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/* ----------------------------- COMPATIBILITY ---------------------------- */
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@ -3,7 +3,7 @@
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/* ======================================================================== */
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/*
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* MUSASHI
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* Version 4.10
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* Version 4.5
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*
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* A portable Motorola M680x0 processor emulation engine.
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* Copyright Karl Stenerud. All rights reserved.
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@ -597,7 +597,6 @@ static void default_instr_hook_callback(unsigned int pc)
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jmp_buf m68ki_aerr_trap;
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#endif /* M68K_EMULATE_ADDRESS_ERROR */
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/* ======================================================================== */
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/* ================================= API ================================== */
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/* ======================================================================== */
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@ -1046,6 +1045,9 @@ void m68k_init(void)
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/* Pulse the RESET line on the CPU */
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void m68k_pulse_reset(void)
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{
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/* Disable the PMMU on reset */
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m68ki_cpu.pmmu_enabled = 0;
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/* Clear all stop levels and eat up all remaining cycles */
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CPU_STOPPED = 0;
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SET_CYCLES(0);
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@ -1088,7 +1090,6 @@ void m68k_pulse_halt(void)
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CPU_STOPPED |= STOP_LEVEL_HALT;
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}
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/* Get and set the current CPU context */
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/* This is to allow for multiple CPUs */
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unsigned int m68k_context_size()
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16
m68kcpu.h
16
m68kcpu.h
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@ -3,7 +3,7 @@
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/* ======================================================================== */
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/*
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* MUSASHI
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* Version 3.32
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* Version 4.5
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*
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* A portable Motorola M680x0 processor emulation engine.
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* Copyright Karl Stenerud. All rights reserved.
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@ -267,7 +267,11 @@ extern "C" {
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#endif /* M68K_INT_GT_32_BIT || M68K_USE_64_BIT */
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/* Simulate address lines of 68k family */
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#if M68K_EMULATE_PMMU
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#define ADDRESS_68K(A) (PMMU_ENABLED ? pmmu_translate_addr((A)&CPU_ADDRESS_MASK) : ((A)&CPU_ADDRESS_MASK))
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#else
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#define ADDRESS_68K(A) ((A)&CPU_ADDRESS_MASK)
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#endif
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/* Shift & Rotate Macros. */
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@ -369,6 +373,7 @@ extern "C" {
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#define CYC_SHIFT m68ki_cpu.cyc_shift
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#define CYC_RESET m68ki_cpu.cyc_reset
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#define HAS_PMMU m68ki_cpu.has_pmmu
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#define PMMU_ENABLED m68ki_cpu.pmmu_enabled
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#define RESET_CYCLES m68ki_cpu.reset_cycles
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@ -945,6 +950,7 @@ typedef struct
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uint instr_mode; /* Stores whether we are in instruction mode or group 0/1 exception mode */
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uint run_mode; /* Stores whether we are processing a reset, bus error, address error, or something else */
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int has_pmmu; /* Indicates if a PMMU available (yes on 030, 040, no on EC030) */
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int pmmu_enabled; /* Indicates if the PMMU is enabled */
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uint reset_cycles;
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/* Clocks required for instructions / exceptions */
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@ -962,6 +968,12 @@ typedef struct
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uint virq_state;
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uint nmi_pending;
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/* PMMU registers */
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uint mmu_crp_aptr, mmu_crp_limit;
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uint mmu_srp_aptr, mmu_srp_limit;
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uint mmu_tc;
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uint16 mmu_sr;
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const uint8* cyc_instruction;
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const uint8* cyc_exception;
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@ -1011,6 +1023,8 @@ char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type);
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/* ---------------------------- Read Immediate ---------------------------- */
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#include "m68kmmu.h"
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/* Handles all immediate reads, does address error check, function code setting,
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* and prefetching if they are enabled in m68kconf.h
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*/
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28
m68kdasm.c
28
m68kdasm.c
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@ -3019,6 +3019,32 @@ static void d68030_pmove(void)
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// do this after fetching the second PMOVE word so we properly get the 3rd if necessary
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str = get_ea_mode_str_32(g_cpu_ir);
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if ((modes & 0xfde0) == 0x2000) // PLOAD
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{
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if (modes & 0x0200)
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{
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sprintf(g_dasm_str, "pload #%d, %s", (modes>>10)&7, str);
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}
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else
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{
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sprintf(g_dasm_str, "pload %s, #%d", str, (modes>>10)&7);
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}
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return;
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}
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if ((modes & 0xe200) == 0x2000) // PFLUSHA
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{
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if (modes & 0x0200)
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{
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sprintf(g_dasm_str, "pflush %s, %s", g_mmuregs[(modes>>10)&7], str);
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}
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else
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{
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sprintf(g_dasm_str, "pflush %s, %s", str, g_mmuregs[(modes>>10)&7]);
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}
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return;
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}
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switch ((modes>>13) & 0x7)
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{
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case 0: // MC68030/040 form with FD bit
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@ -3767,7 +3793,7 @@ unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cp
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return 1;
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}
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// f028 2215 0008
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/* ======================================================================== */
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/* ============================== END OF FILE ============================= */
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21
m68kfpu.c
21
m68kfpu.c
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@ -1,27 +1,6 @@
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#include <math.h>
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#include <stdarg.h>
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#include <stdio.h>
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#include "m68kcpu.h"
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extern void exit(int);
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#if defined(_MSC_VER)
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# define NORETURN __declspec(noreturn)
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#elif defined(__clang__) || defined(__GNUC__)
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# define NORETURN __attribute__((noreturn))
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#else
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# define NORETURN
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#endif
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// TODO: Remove this and replace with a non-fatal signaling mechanism
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static NORETURN void fatalerror(char *format, ...) {
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va_list ap;
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va_start(ap,format);
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fprintf(stderr,format,ap);
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va_end(ap);
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exit(1);
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}
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#define FPCC_N 0x08000000
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#define FPCC_Z 0x04000000
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#define FPCC_I 0x02000000
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193
m68kmmu.h
Normal file
193
m68kmmu.h
Normal file
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@ -0,0 +1,193 @@
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/*
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m68kmmu.h - PMMU implementation for 68851/68030/68040
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By R. Belmont
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Copyright Nicola Salmoria and the MAME Team.
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Visit http://mamedev.org for licensing and usage restrictions.
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*/
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#include <stdio.h>
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#include <stdarg.h>
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extern void exit(int);
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// TODO: Remove this and replace with a non-fatal signaling mechanism
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inline void fatalerror(char *format, ...) {
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va_list ap;
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va_start(ap,format);
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fprintf(stderr,format,ap);
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va_end(ap);
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exit(1);
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}
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/*
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pmmu_translate_addr: perform 68851/68030-style PMMU address translation
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*/
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inline uint pmmu_translate_addr(uint addr_in)
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{
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uint addr_out, tbl_entry, tbl_entry2, tamode, tbmode;
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uint root_aptr, root_limit, tofs, is, abits, bbits; // , cbits;
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uint resolved, tptr, shift;
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resolved = 0;
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addr_out = addr_in;
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// if SRP is enabled and we're in supervisor mode, use it
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if ((m68ki_cpu.mmu_tc & 0x02000000) && (m68ki_get_sr() & 0x2000))
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{
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root_aptr = m68ki_cpu.mmu_srp_aptr;
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root_limit = m68ki_cpu.mmu_srp_limit;
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}
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else // else use the CRP
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{
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root_aptr = m68ki_cpu.mmu_crp_aptr;
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root_limit = m68ki_cpu.mmu_crp_limit;
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}
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// get initial shift (# of top bits to ignore)
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is = (m68ki_cpu.mmu_tc>>16) & 0xf;
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abits = (m68ki_cpu.mmu_tc>>12)&0xf;
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bbits = (m68ki_cpu.mmu_tc>>8)&0xf;
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// cbits = (m68ki_cpu.mmu_tc>>4)&0xf;
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// fprintf(stderr,"PMMU: tcr %08x limit %08x aptr %08x is %x abits %d bbits %d cbits %d\n", m68ki_cpu.mmu_tc, root_limit, root_aptr, is, abits, bbits, cbits);
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// get table A offset
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tofs = (addr_in<<is)>>(32-abits);
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// find out what format table A is
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switch (root_limit & 3)
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{
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case 0: // invalid, should cause MMU exception
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case 1: // page descriptor, should cause direct mapping
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fatalerror("680x0 PMMU: Unhandled root mode\n");
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break;
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case 2: // valid 4 byte descriptors
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tofs *= 4;
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// fprintf(stderr,"PMMU: reading table A entry at %08x\n", tofs + (root_aptr & 0xfffffffc));
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tbl_entry = m68k_read_memory_32( tofs + (root_aptr & 0xfffffffc));
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tamode = tbl_entry & 3;
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// fprintf(stderr,"PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tamode, tofs);
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break;
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case 3: // valid 8 byte descriptors
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tofs *= 8;
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// fprintf(stderr,"PMMU: reading table A entries at %08x\n", tofs + (root_aptr & 0xfffffffc));
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tbl_entry2 = m68k_read_memory_32( tofs + (root_aptr & 0xfffffffc));
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tbl_entry = m68k_read_memory_32( tofs + (root_aptr & 0xfffffffc)+4);
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tamode = tbl_entry2 & 3;
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// fprintf(stderr,"PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tamode, tofs);
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break;
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}
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// get table B offset and pointer
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tofs = (addr_in<<(is+abits))>>(32-bbits);
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tptr = tbl_entry & 0xfffffff0;
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// find out what format table B is, if any
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switch (tamode)
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{
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case 0: // invalid, should cause MMU exception
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fatalerror("680x0 PMMU: Unhandled Table A mode %d (addr_in %08x)\n", tamode, addr_in);
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break;
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case 2: // 4-byte table B descriptor
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tofs *= 4;
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// fprintf(stderr,"PMMU: reading table B entry at %08x\n", tofs + tptr);
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tbl_entry = m68k_read_memory_32( tofs + tptr);
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tbmode = tbl_entry & 3;
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// fprintf(stderr,"PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs);
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break;
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case 3: // 8-byte table B descriptor
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tofs *= 8;
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// fprintf(stderr,"PMMU: reading table B entries at %08x\n", tofs + tptr);
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tbl_entry2 = m68k_read_memory_32( tofs + tptr);
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tbl_entry = m68k_read_memory_32( tofs + tptr + 4);
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tbmode = tbl_entry2 & 3;
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// fprintf(stderr,"PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tbmode, tofs);
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break;
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case 1: // early termination descriptor
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tbl_entry &= 0xffffff00;
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shift = is+abits;
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addr_out = ((addr_in<<shift)>>shift) + tbl_entry;
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resolved = 1;
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break;
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}
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// if table A wasn't early-out, continue to process table B
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if (!resolved)
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{
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switch (tbmode)
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{
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case 0: // invalid, should cause MMU exception
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case 2: // 4-byte table C descriptor
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case 3: // 8-byte table C descriptor
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fatalerror("680x0 PMMU: Unhandled Table B mode %d (addr_in %08x)\n", tbmode, addr_in);
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break;
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case 1: // early termination descriptor
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tbl_entry &= 0xffffff00;
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shift = is+abits+bbits;
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addr_out = ((addr_in<<shift)>>shift) + tbl_entry;
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resolved = 1;
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break;
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}
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}
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// if ((addr_in < 0x40000000) || (addr_in > 0x4fffffff)) printf("PMMU: [%08x] => [%08x]\n", addr_in, addr_out);
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return addr_out;
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}
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/*
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maincpu at 40804366: called unimplemented instruction f000 (cpgen)
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PMMU: tcr 80f05570 limit 7fff0003 aptr 043ffcc0 is 0
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PMMU: reading table A entries at 043ffce0
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PMMU: addr 4080438a entry 00000000 entry2 7ffffc18 mode 0 aofs 20
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680x0 PMMU: Unhandled Table A mode 0
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enable, PS = f
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tblA @ 043ffcc0:
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043ffcc0 0001fc0a 043ffcb0 => 00000019 04000019
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043ffcc8 7ffffc18 00000000
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043ffcd0 7ffffc18 00000000
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043ffcd8 7ffffc18 00000000
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043ffce0 7ffffc18 00000000
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043ffce8 7ffffc18 00000000
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043ffcf0 7ffffc18 00000000
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043ffcf8 7ffffc18 00000000
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043ffd00 7ffffc19 40000000
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043ffd08 7ffffc19 48000000
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043ffd10 7ffffc59 50000000
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043ffd18 7ffffc59 58000000
|
||||
043ffd20 7ffffc59 60000000
|
||||
043ffd28 7ffffc59 68000000
|
||||
043ffd30 7ffffc59 70000000
|
||||
043ffd38 7ffffc59 78000000
|
||||
043ffd40 7ffffc59 80000000
|
||||
043ffd48 7ffffc59 88000000
|
||||
043ffd50 7ffffc59 90000000
|
||||
043ffd58 7ffffc59 98000000
|
||||
043ffd60 7ffffc59 a0000000
|
||||
043ffd68 7ffffc59 a8000000
|
||||
043ffd70 7ffffc59 b0000000
|
||||
043ffd78 7ffffc59 b8000000
|
||||
043ffd80 7ffffc59 c0000000
|
||||
043ffd88 7ffffc59 c8000000
|
||||
043ffd90 7ffffc59 d0000000
|
||||
043ffd98 7ffffc59 d8000000
|
||||
043ffda0 7ffffc59 e0000000
|
||||
043ffda8 7ffffc59 e8000000
|
||||
043ffdb0 7ffffc59 f0000000
|
||||
043ffdb8 7ffffc59 f8000000
|
||||
|
||||
*/
|
||||
|
||||
Loading…
Reference in a new issue