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2 commits
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| a513f8b60e | |||
| 3e8ba7ca42 |
3 changed files with 23 additions and 8 deletions
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@ -38,6 +38,13 @@ Wire up your DVI breakout as follows:
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If using jumper jerky, twist the - and + wires for each signal together to help with signal integrity.
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If using jumper jerky, twist the - and + wires for each signal together to help with signal integrity.
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Other pinouts can be used by passing a `pinout` parameter to the `init`
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function.
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This pinout consists of 4 numbers giving the *positive* pin in each differential pair, in the order CK, D0, D1, D2, D3, using GPIO numbering.
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The default pinout is written `{13, 15, 17, 19}`.
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Only pin numbers from 12 to 19 are valid, as other pins are not connected to the HSTX peripheral.
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Using invalid pin numbers is an undignosed error.
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TODO
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TODO
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## C/C++ Resources
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## C/C++ Resources
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@ -599,7 +599,7 @@ DVHSTX::DVHSTX()
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dma_claim_mask((1 << NUM_CHANS) - 1);
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dma_claim_mask((1 << NUM_CHANS) - 1);
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}
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}
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bool DVHSTX::init(uint16_t width, uint16_t height, Mode mode_)
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bool DVHSTX::init(uint16_t width, uint16_t height, Mode mode_, Pinout pinout)
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{
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{
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if (inited) reset();
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if (inited) reset();
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@ -889,23 +889,27 @@ bool DVHSTX::init(uint16_t width, uint16_t height, Mode mode_)
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HSTX_CTRL_CSR_EN_BITS;
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HSTX_CTRL_CSR_EN_BITS;
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// HSTX outputs 0 through 7 appear on GPIO 12 through 19.
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// HSTX outputs 0 through 7 appear on GPIO 12 through 19.
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constexpr int HSTX_FIRST_PIN = 12;
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// Assign clock pair to two neighbouring pins:
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// Assign clock pair to two neighbouring pins:
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hstx_ctrl_hw->bit[1] = HSTX_CTRL_BIT0_CLK_BITS;
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{
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hstx_ctrl_hw->bit[0] = HSTX_CTRL_BIT0_CLK_BITS | HSTX_CTRL_BIT0_INV_BITS;
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int bit = pinout.clk_p - HSTX_FIRST_PIN;
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hstx_ctrl_hw->bit[bit ] = HSTX_CTRL_BIT0_CLK_BITS;
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hstx_ctrl_hw->bit[bit ^ 1] = HSTX_CTRL_BIT0_CLK_BITS | HSTX_CTRL_BIT0_INV_BITS;
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}
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for (uint lane = 0; lane < 3; ++lane) {
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for (uint lane = 0; lane < 3; ++lane) {
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// For each TMDS lane, assign it to the correct GPIO pair based on the
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// For each TMDS lane, assign it to the correct GPIO pair based on the
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// desired pinout:
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// desired pinout:
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static const int lane_to_output_bit[3] = {2, 4, 6};
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int bit = pinout.rgb_p[lane] - HSTX_FIRST_PIN;
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int bit = lane_to_output_bit[lane];
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// Output even bits during first half of each HSTX cycle, and odd bits
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// Output even bits during first half of each HSTX cycle, and odd bits
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// during second half. The shifter advances by two bits each cycle.
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// during second half. The shifter advances by two bits each cycle.
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uint32_t lane_data_sel_bits =
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uint32_t lane_data_sel_bits =
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(lane * 10 ) << HSTX_CTRL_BIT0_SEL_P_LSB |
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(lane * 10 ) << HSTX_CTRL_BIT0_SEL_P_LSB |
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(lane * 10 + 1) << HSTX_CTRL_BIT0_SEL_N_LSB;
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(lane * 10 + 1) << HSTX_CTRL_BIT0_SEL_N_LSB;
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// The two halves of each pair get identical data, but one pin is inverted.
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// The two halves of each pair get identical data, but one pin is inverted.
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hstx_ctrl_hw->bit[bit ] = lane_data_sel_bits | HSTX_CTRL_BIT0_INV_BITS;
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hstx_ctrl_hw->bit[bit ] = lane_data_sel_bits;
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hstx_ctrl_hw->bit[bit + 1] = lane_data_sel_bits;
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hstx_ctrl_hw->bit[bit ^ 1] = lane_data_sel_bits | HSTX_CTRL_BIT0_INV_BITS;
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}
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}
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for (int i = 12; i <= 19; ++i) {
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for (int i = 12; i <= 19; ++i) {
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@ -29,6 +29,10 @@ namespace pimoroni {
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public:
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public:
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static constexpr int PALETTE_SIZE = 256;
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static constexpr int PALETTE_SIZE = 256;
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struct Pinout {
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uint8_t clk_p, rgb_p[3];
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};
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enum Mode {
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enum Mode {
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MODE_PALETTE = 2,
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MODE_PALETTE = 2,
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MODE_RGB565 = 1,
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MODE_RGB565 = 1,
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@ -92,7 +96,7 @@ namespace pimoroni {
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void clear();
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void clear();
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bool init(uint16_t width, uint16_t height, Mode mode = MODE_RGB565);
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bool init(uint16_t width, uint16_t height, Mode mode = MODE_RGB565, Pinout pinout = {13, 15, 17, 19});
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void reset();
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void reset();
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// Wait for vsync and then flip the buffers
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// Wait for vsync and then flip the buffers
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