standalone build for riscv ulp programs
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commit
01d8291a61
5 changed files with 114 additions and 0 deletions
2
.gitignore
vendored
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2
.gitignore
vendored
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/link.ld
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/a.out
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32
Makefile
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32
Makefile
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COPROC_RESERVE_MEM ?= 8176
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SOC := esp32s3
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CC := riscv32-esp-elf-gcc
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CFLAGS := -Os -march=rv32imc -mdiv -fdata-sections -ffunction-sections
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CFLAGS += -isystem $(IDF_PATH)/components/ulp/ulp_riscv/include/
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CFLAGS += -isystem $(IDF_PATH)/components/soc/$(SOC)/include
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CFLAGS += -isystem $(IDF_PATH)/components/esp_common/include
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CFLAGS += -DCOPROC_RESERVE_MEM=$(COPROC_RESERVE_MEM)
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ifeq ($(SOC),esp32s3)
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CFLAGS += -DCONFIG_IDF_TARGET_ESP32S3
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endif
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ifeq ($(SOC),esp32s2)
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CFLAGS += -DCONFIG_IDF_TARGET_ESP32S2
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endif
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LDFLAGS := -march=rv32imc --specs=nano.specs --specs=nosys.specs
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SRCS ?= ulp.c
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SRCS += $(IDF_PATH)/components/ulp/ulp_riscv/ulp_riscv_utils.c
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LDFLAGS += link.ld
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.PHONY: default
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default: a.out
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a.out: $(SRCS) link.ld
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$(CC) -flto $(CFLAGS) $^ -o $@ $(LDFLAGS)
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.PHONY: clean
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clean:
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rm -f a.out link.ld
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link.ld: ulp.riscv.ld
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$(CC) -E -P -xc $(CFLAGS) -o $@ $<
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1
sdkconfig.h
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1
sdkconfig.h
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@ -0,0 +1 @@
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31
ulp.c
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31
ulp.c
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// ULP-RISCV
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#include <stdio.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "ulp_riscv/ulp_riscv.h"
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#include "ulp_riscv/ulp_riscv_utils.h"
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#include "ulp_riscv/ulp_riscv_gpio.h"
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// global variables will be exported as public symbols, visible from main CPU
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__attribute__((used)) uint8_t shared_mem[1024];
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__attribute__((used)) uint16_t shared_mem_len = 1024;
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int main (void) {
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shared_mem[0] = 10;
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shared_mem_len = 1024;
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bool gpio_level = true;
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ulp_riscv_gpio_init(GPIO_NUM_21);
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ulp_riscv_gpio_output_enable(GPIO_NUM_21);
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while(1) {
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ulp_riscv_gpio_output_level(GPIO_NUM_21, gpio_level);
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ulp_riscv_delay_cycles(shared_mem[0] * 10 * ULP_RISCV_CYCLES_PER_MS);
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gpio_level = !gpio_level;
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}
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// ulp_riscv_shutdown() is called automatically when main exits
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return 0;
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}
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48
ulp.riscv.ld
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48
ulp.riscv.ld
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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ENTRY(reset_vector)
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MEMORY
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{
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ram(RW) : ORIGIN = 0, LENGTH = COPROC_RESERVE_MEM
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}
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SECTIONS
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{
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. = ORIGIN(ram);
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.text :
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{
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*start.S.obj(.text.vectors) /* Default reset vector must link to offset 0x0 */
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*(.text)
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*(.text*)
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} >ram
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.rodata ALIGN(4):
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{
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*(.rodata)
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*(.rodata*)
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} > ram
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.data ALIGN(4):
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{
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*(.data)
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*(.data*)
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*(.sdata)
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*(.sdata*)
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} > ram
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.bss ALIGN(4) :
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{
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*(.bss)
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*(.bss*)
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*(.sbss)
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*(.sbss*)
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} >ram
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__stack_top = ORIGIN(ram) + LENGTH(ram);
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}
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