Instead of fixing csi2rx clock frequencies, set them according to the
pixel rate got from the camera sensor.
Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Enabled the MRT at the board level for
mcxn947. Enabled the clocking for the MRT
in the clock control.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
To check if DVFS can be used, the CONFIG_NRFS_DVFS_LOCAL_DOMAIN symbol
needs to be used, not CONFIG_NRFS_HAS_DVFS_SERVICE which only indicates
that DVFS is technically possible, not that its local domain part is
actually included in the build.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit 7a2ce2882a.
Do not enable clock control by default on nRF54H Series SoCs when
the system timer is present, because clock control is not needed
for this purpose there.
Add missing `default y` in the CLOCK_CONTROL_NRF2 Kconfig option that
enables compilation of clock control drivers for nRF54H Series.
This way modules that actually require clock control (like drivers
that use radio) will be able to enable it using the generic option
(CLOCK_CONTROL), not the above one that is specific for nRF54H.
Update accordingly applications that referenced the CLOCK_CONTROL_NRF2
option.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The Drivers using Pinctrl should be turning Pinctrl on
this should not be the responsibility of the board. This
commit removes CONFIG_PINCTRL from the boards side for nxp boards.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
STM32C0 have a different prescaler for SYSCLK and for HCLK.
Updates the clock driver to use the appropriate prescaler for each series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fixes garbage characters on mcuboot by adjusting UART baudrate
during boot phase according to clock source.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Adding the macros `RA_CGC_CLK_SRC` and `RA_CGC_CLK_DIV` that derive
the BSP clock settings from the DeviceTree node settings.
I also define some aliases to fill in the gaps with the BSP
naming conventions.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This will calibrate the HSI's PLLX clocks if enabled
The value rcc_hsicalibartion_default is 0x40U for h7/h7rs.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Deprecate support for configuring the MCO source and prescaler from
Kconfig configurations.
This is now done by devicetree and an MCO driver instead, which also
configures the pin to be used by the MCO peripheral.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add device driver for STM32 MCO peripheral which takes configures
the MCO clock source and prescaler, and outputs it on one of the GPIO
pins.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add clock sources PLL2CLK, PLL3CLK and EXT_HSE.
Needed to check that these clocks are enabled in MCO code.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
remove check for system clock frequency in clock_stm32_ll_h7 because of
addition of fracn (difficult to handle)
Signed-off-by: Nathan Olff <nathan@kickmaker.net>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Remove all entries that as not being used.
This also update hal to re-enable warning flags
as such as -Wno-unused-variable.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.
Replace z_arm_platform_init() with platform_reset().
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rather setting the driver default in soc, make it directly at symbol
level rather than soc and clean up redundant `select` occurrences.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Add custom clock_control API for nRF platforms that allows requesting
clocks with specified minimal required attributes (accuracy, precision,
and frequency). Provide an implementation of this API for FLL16M, HFXO,
HSFLL, and LFCLK controllers in the nRF54H20 SoC.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
When omitting the clk_src definition in a child node of a pclkblock,
it uses the source of the parent node.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Allows MSTP register addresses to be changed in the device tree
to support different configuration SoCs.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This serves two main purposes:
- change the CPU clock via devicetree nodes
- provide the APB frequency to device drivers via the clock driver
interface
Theoretically this could also support choosing between the available
clock sources, but right now we only support LPOSC0 going into PLL0,
going into AHB.
Turning the PLL back off is also not supported since the only current
use case is to set the PLL frequency, turn it on, and switch the AHB
over to it.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
Reuse the file clock_stm32g0.c for the STM32U0 and
rename it to clock_stm32g0_u0.c
because the G0 and U0 series share the same clock control.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Move all dependencies of the family config to series level,
and put a disclaimer saying not to use the family config.
Change all occurrences of the family config in code to the
MCXNX4X series config.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This includes:
1) Source containing helper functions, each
implementing a command from the clock management
protocol.
2) A clock controller driver making use of said
helper functions and implementing the clock
subsystem API.
3) A DT binding for clock protocol node.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add support for the stm32h755 which is a close relative of
the stm32h745 with additional cryptography and hashing
peripherals.
Signed-off-by: Mike Banducci <michael.banducci@sandc.com>
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Clock is disabled at startup for LP core peripherals, greatly
improving power consumption in deep sleep mode.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Device tree configuration for USB serial node and clock control
fix for proper device initialization.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
This update is to support clock API for RA8
Move the clock initialize function into clock driver
Peripheral clock now has 2 more property in clock cell for enable
and disable clock to peripheral module
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
remove litex,sys-clock-frequency from litex,clk,
because we already define that in the clock-frequency of cpu0.
This can be accessed via
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
ESP32-S2 Wi-Fi clock is not initialized properly, causing
instability when scanning or connecting to a SSID.
Fixes#74899Fixes#74417
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Setting the number of memory wait cycles must take place while the clock
is set to 32MHz or less. This patch ensure the MEMWAIT register is
changed before the clock is changed from its default value (of 8MHz).
Note that in order to set MEMWAIT to 1 the power control mode must be
set to high speed (which is why the lines of code interacting with the
OPCCR register have also been moved).
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Remove address-of operator ('&') when assigning `clock_control_xxx_init`
function pointer in `DEVICE_DT_INST_DEFINE` macro.
This change aims to maintain consistency among the drivers in
`drivers/clock_control`, ensuring that all function pointer assignments
follow the same pattern.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
There was an error in calculation of LFXO INTCAP code that prevented
obtaining desired XTAL accuracy below 50PPM. The error was fixed
the accuracy should be within expected range.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Smartbodn does not have dedicated USB clock.
For USB to work PLL needs to be turned on.
To allow for flexible configuration artificial USB clock
is added that can be operated via clock_control subsystem.
This new clock turns on PLL when USB subsystem is enabled.
PLL can also be request in DT if application requires
more speed.
PLL can be automatically turned off when USB enters suspend
state and application did not requested it.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Adds get_status API for clock_stm32_ll_u5 driver
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
The clock should be initialised only once at the
drivers init function.
Check wether the subsys needs to be disabled in
peripheral initialization according to reset reason
in clock control.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Found via static analysis. Two separate error paths where failing to
check the return code leads to undefined behavior:
1. In `litex_clk_get_phase`, the divider stays set to 0 when
`litex_clk_get_clkout_divider` errors out, which leads to a division
by 0.
2. In `litex_clk_calc_duty_normal`, the `duty` struct is used
uninitialized if `litex_clk_get_duty_cycle` errors out.
In both case, checking the return code and returning early resolves the
issue.
Signed-off-by: François Baldassari <francois@memfault.com>
Add ENET_1G clock value to the RT11XX CCM version.
Implemented enabling ENET_1G clock and getting its frequency.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Introduce the stm32h7RS serie to the clock_controller,
based on the stm32h7 clock driver
Datasheet DS14359 rev 1 gives CPU max freq of 500MHz
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Default the clock accuracy for the simulated 54L15 target
just as for the real target.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Fix a compilation error occurring when a prescaler was set for ADC on F1
and F3 family.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit should deal with the followings:
1. PLL requires that VDD level be changed to 1V2 and then released
to 0V9 when it's turned off. Changing the VDD level should be
done when the regulator driver is available. Otherwise, the VDD
level will be fixed to 1V2 (reset value).
2. Check if PLL is allowed to be turned off as it might happen that
USB is enabled which is clocked by PLL.
3. Do not wait for the PLL to lock. This is now performed silently
when PLL is requested.
4. Before switching to PLL we should check if PLL is already enabled
as it might happen that PLL node is initially disabled.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
This patch adds a timeout to the clock_control_on() implementation. The
reason for this timeout is to prevent system freezes when the PLL is
configured incorrectly, or, if BICR is wrong. The locking time of the
AUXPLL is <30us, however, when it starts it also starts other
dependencies which take much longer to become ready. The locking time
has been experimentally measured to be around 2ms, so a 10x bound has
been added.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This WDT is responsible for monitoring the external
32.728 Hz crystal connected to pins XTAL_32K_P and
XTAL_32K_N. If an oscillation failure is detected
the hardware automatically switch to RTC_RC_SLOW
clock source and triggers an interrupt.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
STM32 MCU shall set voltage regulator level with respect to set clock
frequency to reach optimal power consumption.
Voltage regulator is set prior to clock setting based on configuration
from dts/overlay file. Config_regulator_voltage is set as weak in
clock_stm32_ll_common - config_regulator_voltage can be
extended to other STM32 families without need to rewrite heavily
family clock driver, default one can be still used.
Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
Add a new driver for the AUXPLL peripheral found in some new Nordic
SoCs, e.g. nRF54H20. AUXPLL is used to clock some peripherals like e.g.
CAN. Note that driver is implemented natively as Nordic HAL lacks
definitions for the AUXPLL IP, this may be changed once these become
available.
Note that usage of nrf_auxpll_config_set generates unnecessary extra
assembly code compared to the proposed API in
https://github.com/zephyrproject-rtos/hal_nordic/pull/185 which
guarantees static initialization and single write access, possible in
the Zephyr context. However, current solution has been enforced until
further discussion on raw access APIs takes place.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit removes unnecessary initialization of the local variable
where its value is guaranteed to be overwritten by subsequent operations.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Use a code spell-checking tool to scan and correct spelling errors in
the following files:
- clock_stm32_ll_common.c
- clock_stm32_ll_h5.c
- clock_stm32_ll_h7.c
- clock_stm32_ll_u5.c
- clock_stm32_ll_wba.c
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Clock must be restored as soon as the SoC leaves standby.
Keep the logic inside the SoC instead of delegate it to the pm
subsystem.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.
This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.
It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
- Add initial version of CYW920829M2EVK-02 board
- [drivers: clock_control] Make it possible to set up both iho and imo
clocks instead of just one or the other
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
The CMAC uses lp_clk as a sleep clock so it has to be updated if
frequency of lp_clk has changed. This happens either after XTAL32K
settling or RCX calibration.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
1. Update the clock control driver so it can update timing settings for
QSPIC2 following system clock transitions (translated based on
AHB AMBA bus clock).
2. Remove the QSPIC related subroutines and use the respective HAL API
which is now available.
3. Add support for PM (CONFIG_PM_DEVICE). This is required as QSPIC2
register file is powered by PD_SYS which is turned off during device
sleep and so registers contents are lost (in contrast to QSPIC which
is used to drive the flash memory).
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Added initial board support for the
frdm_ke15z board.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Signed-off-by: Pavel Krenek <pavel.krenek@nxp.com>
